Commit | Line | Data |
---|---|---|
1e019421 | 1 | /* |
8eba1842 | 2 | * SGI NMI/TRACE support routines |
1e019421 MT |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | * | |
18 | * Copyright (c) 2009-2013 Silicon Graphics, Inc. All Rights Reserved. | |
19 | * Copyright (c) Mike Travis | |
20 | */ | |
21 | ||
22 | #include <linux/cpu.h> | |
0d12ef0c | 23 | #include <linux/delay.h> |
12ba6c99 | 24 | #include <linux/kexec.h> |
0d12ef0c | 25 | #include <linux/module.h> |
1e019421 | 26 | #include <linux/nmi.h> |
0d12ef0c MT |
27 | #include <linux/sched.h> |
28 | #include <linux/slab.h> | |
1e019421 MT |
29 | |
30 | #include <asm/apic.h> | |
0d12ef0c MT |
31 | #include <asm/current.h> |
32 | #include <asm/kdebug.h> | |
33 | #include <asm/local64.h> | |
1e019421 MT |
34 | #include <asm/nmi.h> |
35 | #include <asm/uv/uv.h> | |
36 | #include <asm/uv/uv_hub.h> | |
37 | #include <asm/uv/uv_mmrs.h> | |
38 | ||
8eba1842 MT |
39 | void (*uv_trace_func)(const char *f, const int l, const char *fmt, ...); |
40 | EXPORT_SYMBOL(uv_trace_func); | |
41 | ||
42 | void (*uv_trace_nmi_func)(unsigned int reason, struct pt_regs *regs); | |
43 | EXPORT_SYMBOL(uv_trace_nmi_func); | |
44 | ||
45 | ||
0d12ef0c MT |
46 | /* |
47 | * UV handler for NMI | |
48 | * | |
49 | * Handle system-wide NMI events generated by the global 'power nmi' command. | |
50 | * | |
51 | * Basic operation is to field the NMI interrupt on each cpu and wait | |
52 | * until all cpus have arrived into the nmi handler. If some cpus do not | |
53 | * make it into the handler, try and force them in with the IPI(NMI) signal. | |
54 | * | |
55 | * We also have to lessen UV Hub MMR accesses as much as possible as this | |
56 | * disrupts the UV Hub's primary mission of directing NumaLink traffic and | |
57 | * can cause system problems to occur. | |
58 | * | |
59 | * To do this we register our primary NMI notifier on the NMI_UNKNOWN | |
60 | * chain. This reduces the number of false NMI calls when the perf | |
61 | * tools are running which generate an enormous number of NMIs per | |
62 | * second (~4M/s for 1024 cpu threads). Our secondary NMI handler is | |
63 | * very short as it only checks that if it has been "pinged" with the | |
64 | * IPI(NMI) signal as mentioned above, and does not read the UV Hub's MMR. | |
65 | * | |
66 | */ | |
67 | ||
68 | static struct uv_hub_nmi_s **uv_hub_nmi_list; | |
69 | ||
70 | DEFINE_PER_CPU(struct uv_cpu_nmi_s, __uv_cpu_nmi); | |
71 | EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_nmi); | |
72 | ||
73 | static unsigned long nmi_mmr; | |
74 | static unsigned long nmi_mmr_clear; | |
75 | static unsigned long nmi_mmr_pending; | |
76 | ||
77 | static atomic_t uv_in_nmi; | |
78 | static atomic_t uv_nmi_cpu = ATOMIC_INIT(-1); | |
79 | static atomic_t uv_nmi_cpus_in_nmi = ATOMIC_INIT(-1); | |
80 | static atomic_t uv_nmi_slave_continue; | |
12ba6c99 | 81 | static atomic_t uv_nmi_kexec_failed; |
0d12ef0c MT |
82 | static cpumask_var_t uv_nmi_cpu_mask; |
83 | ||
84 | /* Values for uv_nmi_slave_continue */ | |
85 | #define SLAVE_CLEAR 0 | |
86 | #define SLAVE_CONTINUE 1 | |
87 | #define SLAVE_EXIT 2 | |
1e019421 MT |
88 | |
89 | /* | |
0d12ef0c MT |
90 | * Default is all stack dumps go to the console and buffer. |
91 | * Lower level to send to log buffer only. | |
1e019421 | 92 | */ |
0d12ef0c MT |
93 | static int uv_nmi_loglevel = 7; |
94 | module_param_named(dump_loglevel, uv_nmi_loglevel, int, 0644); | |
95 | ||
96 | /* | |
97 | * The following values show statistics on how perf events are affecting | |
98 | * this system. | |
99 | */ | |
100 | static int param_get_local64(char *buffer, const struct kernel_param *kp) | |
1e019421 | 101 | { |
0d12ef0c MT |
102 | return sprintf(buffer, "%lu\n", local64_read((local64_t *)kp->arg)); |
103 | } | |
1e019421 | 104 | |
0d12ef0c MT |
105 | static int param_set_local64(const char *val, const struct kernel_param *kp) |
106 | { | |
107 | /* clear on any write */ | |
108 | local64_set((local64_t *)kp->arg, 0); | |
109 | return 0; | |
110 | } | |
111 | ||
112 | static struct kernel_param_ops param_ops_local64 = { | |
113 | .get = param_get_local64, | |
114 | .set = param_set_local64, | |
115 | }; | |
116 | #define param_check_local64(name, p) __param_check(name, p, local64_t) | |
117 | ||
118 | static local64_t uv_nmi_count; | |
119 | module_param_named(nmi_count, uv_nmi_count, local64, 0644); | |
120 | ||
121 | static local64_t uv_nmi_misses; | |
122 | module_param_named(nmi_misses, uv_nmi_misses, local64, 0644); | |
123 | ||
124 | static local64_t uv_nmi_ping_count; | |
125 | module_param_named(ping_count, uv_nmi_ping_count, local64, 0644); | |
126 | ||
127 | static local64_t uv_nmi_ping_misses; | |
128 | module_param_named(ping_misses, uv_nmi_ping_misses, local64, 0644); | |
129 | ||
130 | /* | |
131 | * Following values allow tuning for large systems under heavy loading | |
132 | */ | |
133 | static int uv_nmi_initial_delay = 100; | |
134 | module_param_named(initial_delay, uv_nmi_initial_delay, int, 0644); | |
135 | ||
136 | static int uv_nmi_slave_delay = 100; | |
137 | module_param_named(slave_delay, uv_nmi_slave_delay, int, 0644); | |
138 | ||
139 | static int uv_nmi_loop_delay = 100; | |
140 | module_param_named(loop_delay, uv_nmi_loop_delay, int, 0644); | |
141 | ||
142 | static int uv_nmi_trigger_delay = 10000; | |
143 | module_param_named(trigger_delay, uv_nmi_trigger_delay, int, 0644); | |
144 | ||
145 | static int uv_nmi_wait_count = 100; | |
146 | module_param_named(wait_count, uv_nmi_wait_count, int, 0644); | |
147 | ||
148 | static int uv_nmi_retry_count = 500; | |
149 | module_param_named(retry_count, uv_nmi_retry_count, int, 0644); | |
150 | ||
3c121d9a MT |
151 | /* |
152 | * Valid NMI Actions: | |
153 | * "dump" - dump process stack for each cpu | |
154 | * "ips" - dump IP info for each cpu | |
12ba6c99 | 155 | * "kdump" - do crash dump |
3c121d9a MT |
156 | */ |
157 | static char uv_nmi_action[8] = "dump"; | |
158 | module_param_string(action, uv_nmi_action, sizeof(uv_nmi_action), 0644); | |
159 | ||
160 | static inline bool uv_nmi_action_is(const char *action) | |
161 | { | |
162 | return (strncmp(uv_nmi_action, action, strlen(action)) == 0); | |
163 | } | |
164 | ||
0d12ef0c MT |
165 | /* Setup which NMI support is present in system */ |
166 | static void uv_nmi_setup_mmrs(void) | |
167 | { | |
168 | if (uv_read_local_mmr(UVH_NMI_MMRX_SUPPORTED)) { | |
169 | uv_write_local_mmr(UVH_NMI_MMRX_REQ, | |
170 | 1UL << UVH_NMI_MMRX_REQ_SHIFT); | |
171 | nmi_mmr = UVH_NMI_MMRX; | |
172 | nmi_mmr_clear = UVH_NMI_MMRX_CLEAR; | |
173 | nmi_mmr_pending = 1UL << UVH_NMI_MMRX_SHIFT; | |
174 | pr_info("UV: SMI NMI support: %s\n", UVH_NMI_MMRX_TYPE); | |
175 | } else { | |
176 | nmi_mmr = UVH_NMI_MMR; | |
177 | nmi_mmr_clear = UVH_NMI_MMR_CLEAR; | |
178 | nmi_mmr_pending = 1UL << UVH_NMI_MMR_SHIFT; | |
179 | pr_info("UV: SMI NMI support: %s\n", UVH_NMI_MMR_TYPE); | |
180 | } | |
181 | } | |
182 | ||
183 | /* Read NMI MMR and check if NMI flag was set by BMC. */ | |
184 | static inline int uv_nmi_test_mmr(struct uv_hub_nmi_s *hub_nmi) | |
185 | { | |
186 | hub_nmi->nmi_value = uv_read_local_mmr(nmi_mmr); | |
187 | atomic_inc(&hub_nmi->read_mmr_count); | |
188 | return !!(hub_nmi->nmi_value & nmi_mmr_pending); | |
189 | } | |
190 | ||
191 | static inline void uv_local_mmr_clear_nmi(void) | |
192 | { | |
193 | uv_write_local_mmr(nmi_mmr_clear, nmi_mmr_pending); | |
194 | } | |
195 | ||
196 | /* | |
197 | * If first cpu in on this hub, set hub_nmi "in_nmi" and "owner" values and | |
198 | * return true. If first cpu in on the system, set global "in_nmi" flag. | |
199 | */ | |
200 | static int uv_set_in_nmi(int cpu, struct uv_hub_nmi_s *hub_nmi) | |
201 | { | |
202 | int first = atomic_add_unless(&hub_nmi->in_nmi, 1, 1); | |
203 | ||
204 | if (first) { | |
205 | atomic_set(&hub_nmi->cpu_owner, cpu); | |
206 | if (atomic_add_unless(&uv_in_nmi, 1, 1)) | |
207 | atomic_set(&uv_nmi_cpu, cpu); | |
208 | ||
209 | atomic_inc(&hub_nmi->nmi_count); | |
210 | } | |
211 | return first; | |
212 | } | |
213 | ||
214 | /* Check if this is a system NMI event */ | |
215 | static int uv_check_nmi(struct uv_hub_nmi_s *hub_nmi) | |
216 | { | |
217 | int cpu = smp_processor_id(); | |
218 | int nmi = 0; | |
219 | ||
220 | local64_inc(&uv_nmi_count); | |
221 | uv_cpu_nmi.queries++; | |
222 | ||
223 | do { | |
224 | nmi = atomic_read(&hub_nmi->in_nmi); | |
225 | if (nmi) | |
226 | break; | |
227 | ||
228 | if (raw_spin_trylock(&hub_nmi->nmi_lock)) { | |
229 | ||
230 | /* check hub MMR NMI flag */ | |
231 | if (uv_nmi_test_mmr(hub_nmi)) { | |
232 | uv_set_in_nmi(cpu, hub_nmi); | |
233 | nmi = 1; | |
234 | break; | |
235 | } | |
236 | ||
237 | /* MMR NMI flag is clear */ | |
238 | raw_spin_unlock(&hub_nmi->nmi_lock); | |
239 | ||
240 | } else { | |
241 | /* wait a moment for the hub nmi locker to set flag */ | |
242 | cpu_relax(); | |
243 | udelay(uv_nmi_slave_delay); | |
244 | ||
245 | /* re-check hub in_nmi flag */ | |
246 | nmi = atomic_read(&hub_nmi->in_nmi); | |
247 | if (nmi) | |
248 | break; | |
249 | } | |
250 | ||
251 | /* check if this BMC missed setting the MMR NMI flag */ | |
252 | if (!nmi) { | |
253 | nmi = atomic_read(&uv_in_nmi); | |
254 | if (nmi) | |
255 | uv_set_in_nmi(cpu, hub_nmi); | |
256 | } | |
257 | ||
258 | } while (0); | |
259 | ||
260 | if (!nmi) | |
261 | local64_inc(&uv_nmi_misses); | |
262 | ||
263 | return nmi; | |
264 | } | |
265 | ||
266 | /* Need to reset the NMI MMR register, but only once per hub. */ | |
267 | static inline void uv_clear_nmi(int cpu) | |
268 | { | |
269 | struct uv_hub_nmi_s *hub_nmi = uv_hub_nmi; | |
270 | ||
271 | if (cpu == atomic_read(&hub_nmi->cpu_owner)) { | |
272 | atomic_set(&hub_nmi->cpu_owner, -1); | |
273 | atomic_set(&hub_nmi->in_nmi, 0); | |
274 | uv_local_mmr_clear_nmi(); | |
275 | raw_spin_unlock(&hub_nmi->nmi_lock); | |
276 | } | |
277 | } | |
278 | ||
279 | /* Print non-responding cpus */ | |
280 | static void uv_nmi_nr_cpus_pr(char *fmt) | |
281 | { | |
282 | static char cpu_list[1024]; | |
283 | int len = sizeof(cpu_list); | |
284 | int c = cpumask_weight(uv_nmi_cpu_mask); | |
285 | int n = cpulist_scnprintf(cpu_list, len, uv_nmi_cpu_mask); | |
286 | ||
287 | if (n >= len-1) | |
288 | strcpy(&cpu_list[len - 6], "...\n"); | |
289 | ||
290 | printk(fmt, c, cpu_list); | |
291 | } | |
292 | ||
293 | /* Ping non-responding cpus attemping to force them into the NMI handler */ | |
294 | static void uv_nmi_nr_cpus_ping(void) | |
295 | { | |
296 | int cpu; | |
297 | ||
298 | for_each_cpu(cpu, uv_nmi_cpu_mask) | |
299 | atomic_set(&uv_cpu_nmi_per(cpu).pinging, 1); | |
300 | ||
301 | apic->send_IPI_mask(uv_nmi_cpu_mask, APIC_DM_NMI); | |
302 | } | |
303 | ||
304 | /* Clean up flags for cpus that ignored both NMI and ping */ | |
305 | static void uv_nmi_cleanup_mask(void) | |
306 | { | |
307 | int cpu; | |
308 | ||
309 | for_each_cpu(cpu, uv_nmi_cpu_mask) { | |
310 | atomic_set(&uv_cpu_nmi_per(cpu).pinging, 0); | |
311 | atomic_set(&uv_cpu_nmi_per(cpu).state, UV_NMI_STATE_OUT); | |
312 | cpumask_clear_cpu(cpu, uv_nmi_cpu_mask); | |
313 | } | |
314 | } | |
315 | ||
316 | /* Loop waiting as cpus enter nmi handler */ | |
317 | static int uv_nmi_wait_cpus(int first) | |
318 | { | |
319 | int i, j, k, n = num_online_cpus(); | |
320 | int last_k = 0, waiting = 0; | |
321 | ||
322 | if (first) { | |
323 | cpumask_copy(uv_nmi_cpu_mask, cpu_online_mask); | |
324 | k = 0; | |
325 | } else { | |
326 | k = n - cpumask_weight(uv_nmi_cpu_mask); | |
327 | } | |
328 | ||
329 | udelay(uv_nmi_initial_delay); | |
330 | for (i = 0; i < uv_nmi_retry_count; i++) { | |
331 | int loop_delay = uv_nmi_loop_delay; | |
332 | ||
333 | for_each_cpu(j, uv_nmi_cpu_mask) { | |
334 | if (atomic_read(&uv_cpu_nmi_per(j).state)) { | |
335 | cpumask_clear_cpu(j, uv_nmi_cpu_mask); | |
336 | if (++k >= n) | |
337 | break; | |
338 | } | |
339 | } | |
340 | if (k >= n) { /* all in? */ | |
341 | k = n; | |
342 | break; | |
343 | } | |
344 | if (last_k != k) { /* abort if no new cpus coming in */ | |
345 | last_k = k; | |
346 | waiting = 0; | |
347 | } else if (++waiting > uv_nmi_wait_count) | |
348 | break; | |
349 | ||
350 | /* extend delay if waiting only for cpu 0 */ | |
351 | if (waiting && (n - k) == 1 && | |
352 | cpumask_test_cpu(0, uv_nmi_cpu_mask)) | |
353 | loop_delay *= 100; | |
354 | ||
355 | udelay(loop_delay); | |
356 | } | |
357 | atomic_set(&uv_nmi_cpus_in_nmi, k); | |
358 | return n - k; | |
359 | } | |
360 | ||
361 | /* Wait until all slave cpus have entered UV NMI handler */ | |
362 | static void uv_nmi_wait(int master) | |
363 | { | |
364 | /* indicate this cpu is in */ | |
365 | atomic_set(&uv_cpu_nmi.state, UV_NMI_STATE_IN); | |
366 | ||
367 | /* if not the first cpu in (the master), then we are a slave cpu */ | |
368 | if (!master) | |
369 | return; | |
370 | ||
371 | do { | |
372 | /* wait for all other cpus to gather here */ | |
373 | if (!uv_nmi_wait_cpus(1)) | |
374 | break; | |
375 | ||
376 | /* if not all made it in, send IPI NMI to them */ | |
377 | uv_nmi_nr_cpus_pr(KERN_ALERT | |
378 | "UV: Sending NMI IPI to %d non-responding CPUs: %s\n"); | |
379 | uv_nmi_nr_cpus_ping(); | |
380 | ||
381 | /* if all cpus are in, then done */ | |
382 | if (!uv_nmi_wait_cpus(0)) | |
383 | break; | |
384 | ||
385 | uv_nmi_nr_cpus_pr(KERN_ALERT | |
386 | "UV: %d CPUs not in NMI loop: %s\n"); | |
387 | } while (0); | |
388 | ||
389 | pr_alert("UV: %d of %d CPUs in NMI\n", | |
390 | atomic_read(&uv_nmi_cpus_in_nmi), num_online_cpus()); | |
391 | } | |
392 | ||
3c121d9a MT |
393 | static void uv_nmi_dump_cpu_ip_hdr(void) |
394 | { | |
395 | printk(KERN_DEFAULT | |
396 | "\nUV: %4s %6s %-32s %s (Note: PID 0 not listed)\n", | |
397 | "CPU", "PID", "COMMAND", "IP"); | |
398 | } | |
399 | ||
400 | static void uv_nmi_dump_cpu_ip(int cpu, struct pt_regs *regs) | |
401 | { | |
402 | printk(KERN_DEFAULT "UV: %4d %6d %-32.32s ", | |
403 | cpu, current->pid, current->comm); | |
404 | ||
405 | printk_address(regs->ip, 1); | |
406 | } | |
407 | ||
0d12ef0c MT |
408 | /* Dump this cpu's state */ |
409 | static void uv_nmi_dump_state_cpu(int cpu, struct pt_regs *regs) | |
410 | { | |
411 | const char *dots = " ................................. "; | |
412 | ||
3c121d9a MT |
413 | if (uv_nmi_action_is("ips")) { |
414 | if (cpu == 0) | |
415 | uv_nmi_dump_cpu_ip_hdr(); | |
416 | ||
417 | if (current->pid != 0) | |
418 | uv_nmi_dump_cpu_ip(cpu, regs); | |
419 | ||
420 | } else if (uv_nmi_action_is("dump")) { | |
421 | printk(KERN_DEFAULT | |
422 | "UV:%sNMI process trace for CPU %d\n", dots, cpu); | |
423 | show_regs(regs); | |
424 | } | |
0d12ef0c MT |
425 | atomic_set(&uv_cpu_nmi.state, UV_NMI_STATE_DUMP_DONE); |
426 | } | |
427 | ||
428 | /* Trigger a slave cpu to dump it's state */ | |
429 | static void uv_nmi_trigger_dump(int cpu) | |
430 | { | |
431 | int retry = uv_nmi_trigger_delay; | |
432 | ||
433 | if (atomic_read(&uv_cpu_nmi_per(cpu).state) != UV_NMI_STATE_IN) | |
434 | return; | |
435 | ||
436 | atomic_set(&uv_cpu_nmi_per(cpu).state, UV_NMI_STATE_DUMP); | |
437 | do { | |
438 | cpu_relax(); | |
439 | udelay(10); | |
440 | if (atomic_read(&uv_cpu_nmi_per(cpu).state) | |
441 | != UV_NMI_STATE_DUMP) | |
442 | return; | |
443 | } while (--retry > 0); | |
444 | ||
445 | pr_crit("UV: CPU %d stuck in process dump function\n", cpu); | |
446 | atomic_set(&uv_cpu_nmi_per(cpu).state, UV_NMI_STATE_DUMP_DONE); | |
447 | } | |
448 | ||
449 | /* Wait until all cpus ready to exit */ | |
450 | static void uv_nmi_sync_exit(int master) | |
451 | { | |
452 | atomic_dec(&uv_nmi_cpus_in_nmi); | |
453 | if (master) { | |
454 | while (atomic_read(&uv_nmi_cpus_in_nmi) > 0) | |
455 | cpu_relax(); | |
456 | atomic_set(&uv_nmi_slave_continue, SLAVE_CLEAR); | |
457 | } else { | |
458 | while (atomic_read(&uv_nmi_slave_continue)) | |
459 | cpu_relax(); | |
460 | } | |
461 | } | |
462 | ||
463 | /* Walk through cpu list and dump state of each */ | |
464 | static void uv_nmi_dump_state(int cpu, struct pt_regs *regs, int master) | |
465 | { | |
466 | if (master) { | |
467 | int tcpu; | |
468 | int ignored = 0; | |
469 | int saved_console_loglevel = console_loglevel; | |
470 | ||
3c121d9a MT |
471 | pr_alert("UV: tracing %s for %d CPUs from CPU %d\n", |
472 | uv_nmi_action_is("ips") ? "IPs" : "processes", | |
0d12ef0c MT |
473 | atomic_read(&uv_nmi_cpus_in_nmi), cpu); |
474 | ||
475 | console_loglevel = uv_nmi_loglevel; | |
476 | atomic_set(&uv_nmi_slave_continue, SLAVE_EXIT); | |
477 | for_each_online_cpu(tcpu) { | |
478 | if (cpumask_test_cpu(tcpu, uv_nmi_cpu_mask)) | |
479 | ignored++; | |
480 | else if (tcpu == cpu) | |
481 | uv_nmi_dump_state_cpu(tcpu, regs); | |
482 | else | |
483 | uv_nmi_trigger_dump(tcpu); | |
1e019421 | 484 | } |
0d12ef0c MT |
485 | if (ignored) |
486 | printk(KERN_DEFAULT "UV: %d CPUs ignored NMI\n", | |
487 | ignored); | |
488 | ||
489 | console_loglevel = saved_console_loglevel; | |
490 | pr_alert("UV: process trace complete\n"); | |
491 | } else { | |
492 | while (!atomic_read(&uv_nmi_slave_continue)) | |
493 | cpu_relax(); | |
494 | while (atomic_read(&uv_cpu_nmi.state) != UV_NMI_STATE_DUMP) | |
495 | cpu_relax(); | |
496 | uv_nmi_dump_state_cpu(cpu, regs); | |
1e019421 | 497 | } |
0d12ef0c MT |
498 | uv_nmi_sync_exit(master); |
499 | } | |
1e019421 | 500 | |
0d12ef0c MT |
501 | static void uv_nmi_touch_watchdogs(void) |
502 | { | |
503 | touch_softlockup_watchdog_sync(); | |
504 | clocksource_touch_watchdog(); | |
505 | rcu_cpu_stall_reset(); | |
506 | touch_nmi_watchdog(); | |
507 | } | |
508 | ||
12ba6c99 MT |
509 | #if defined(CONFIG_KEXEC) |
510 | static void uv_nmi_kdump(int cpu, int master, struct pt_regs *regs) | |
511 | { | |
512 | /* Call crash to dump system state */ | |
513 | if (master) { | |
514 | pr_emerg("UV: NMI executing crash_kexec on CPU%d\n", cpu); | |
515 | crash_kexec(regs); | |
516 | ||
517 | pr_emerg("UV: crash_kexec unexpectedly returned, "); | |
518 | if (!kexec_crash_image) { | |
519 | pr_cont("crash kernel not loaded\n"); | |
520 | atomic_set(&uv_nmi_kexec_failed, 1); | |
521 | uv_nmi_sync_exit(1); | |
522 | return; | |
523 | } | |
524 | pr_cont("kexec busy, stalling cpus while waiting\n"); | |
525 | } | |
526 | ||
527 | /* If crash exec fails the slaves should return, otherwise stall */ | |
528 | while (atomic_read(&uv_nmi_kexec_failed) == 0) | |
529 | mdelay(10); | |
530 | ||
531 | /* Crash kernel most likely not loaded, return in an orderly fashion */ | |
532 | uv_nmi_sync_exit(0); | |
533 | } | |
534 | ||
535 | #else /* !CONFIG_KEXEC */ | |
536 | static inline void uv_nmi_kdump(int cpu, int master, struct pt_regs *regs) | |
537 | { | |
538 | if (master) | |
539 | pr_err("UV: NMI kdump: KEXEC not supported in this kernel\n"); | |
540 | } | |
541 | #endif /* !CONFIG_KEXEC */ | |
542 | ||
0d12ef0c MT |
543 | /* |
544 | * UV NMI handler | |
545 | */ | |
546 | int uv_handle_nmi(unsigned int reason, struct pt_regs *regs) | |
547 | { | |
548 | struct uv_hub_nmi_s *hub_nmi = uv_hub_nmi; | |
549 | int cpu = smp_processor_id(); | |
550 | int master = 0; | |
551 | unsigned long flags; | |
552 | ||
553 | local_irq_save(flags); | |
554 | ||
555 | /* If not a UV System NMI, ignore */ | |
556 | if (!atomic_read(&uv_cpu_nmi.pinging) && !uv_check_nmi(hub_nmi)) { | |
557 | local_irq_restore(flags); | |
1e019421 | 558 | return NMI_DONE; |
0d12ef0c | 559 | } |
1e019421 | 560 | |
8eba1842 MT |
561 | /* Call possible NMI trace function */ |
562 | if (unlikely(uv_trace_nmi_func)) | |
563 | (uv_trace_nmi_func)(reason, regs); | |
564 | ||
0d12ef0c MT |
565 | /* Indicate we are the first CPU into the NMI handler */ |
566 | master = (atomic_read(&uv_nmi_cpu) == cpu); | |
1e019421 | 567 | |
12ba6c99 MT |
568 | /* If NMI action is "kdump", then attempt to do it */ |
569 | if (uv_nmi_action_is("kdump")) | |
570 | uv_nmi_kdump(cpu, master, regs); | |
571 | ||
0d12ef0c MT |
572 | /* Pause as all cpus enter the NMI handler */ |
573 | uv_nmi_wait(master); | |
574 | ||
575 | /* Dump state of each cpu */ | |
3c121d9a MT |
576 | if (uv_nmi_action_is("ips") || uv_nmi_action_is("dump")) |
577 | uv_nmi_dump_state(cpu, regs, master); | |
0d12ef0c MT |
578 | |
579 | /* Clear per_cpu "in nmi" flag */ | |
580 | atomic_set(&uv_cpu_nmi.state, UV_NMI_STATE_OUT); | |
581 | ||
582 | /* Clear MMR NMI flag on each hub */ | |
583 | uv_clear_nmi(cpu); | |
584 | ||
585 | /* Clear global flags */ | |
586 | if (master) { | |
587 | if (cpumask_weight(uv_nmi_cpu_mask)) | |
588 | uv_nmi_cleanup_mask(); | |
589 | atomic_set(&uv_nmi_cpus_in_nmi, -1); | |
590 | atomic_set(&uv_nmi_cpu, -1); | |
591 | atomic_set(&uv_in_nmi, 0); | |
592 | } | |
593 | ||
594 | uv_nmi_touch_watchdogs(); | |
595 | local_irq_restore(flags); | |
1e019421 MT |
596 | |
597 | return NMI_HANDLED; | |
598 | } | |
599 | ||
0d12ef0c MT |
600 | /* |
601 | * NMI handler for pulling in CPUs when perf events are grabbing our NMI | |
602 | */ | |
603 | int uv_handle_nmi_ping(unsigned int reason, struct pt_regs *regs) | |
604 | { | |
605 | int ret; | |
606 | ||
607 | uv_cpu_nmi.queries++; | |
608 | if (!atomic_read(&uv_cpu_nmi.pinging)) { | |
609 | local64_inc(&uv_nmi_ping_misses); | |
610 | return NMI_DONE; | |
611 | } | |
612 | ||
613 | uv_cpu_nmi.pings++; | |
614 | local64_inc(&uv_nmi_ping_count); | |
615 | ret = uv_handle_nmi(reason, regs); | |
616 | atomic_set(&uv_cpu_nmi.pinging, 0); | |
617 | return ret; | |
618 | } | |
619 | ||
1e019421 MT |
620 | void uv_register_nmi_notifier(void) |
621 | { | |
622 | if (register_nmi_handler(NMI_UNKNOWN, uv_handle_nmi, 0, "uv")) | |
0d12ef0c MT |
623 | pr_warn("UV: NMI handler failed to register\n"); |
624 | ||
625 | if (register_nmi_handler(NMI_LOCAL, uv_handle_nmi_ping, 0, "uvping")) | |
626 | pr_warn("UV: PING NMI handler failed to register\n"); | |
1e019421 MT |
627 | } |
628 | ||
629 | void uv_nmi_init(void) | |
630 | { | |
631 | unsigned int value; | |
632 | ||
633 | /* | |
634 | * Unmask NMI on all cpus | |
635 | */ | |
636 | value = apic_read(APIC_LVT1) | APIC_DM_NMI; | |
637 | value &= ~APIC_LVT_MASKED; | |
638 | apic_write(APIC_LVT1, value); | |
639 | } | |
640 | ||
0d12ef0c MT |
641 | void uv_nmi_setup(void) |
642 | { | |
643 | int size = sizeof(void *) * (1 << NODES_SHIFT); | |
644 | int cpu, nid; | |
645 | ||
646 | /* Setup hub nmi info */ | |
647 | uv_nmi_setup_mmrs(); | |
648 | uv_hub_nmi_list = kzalloc(size, GFP_KERNEL); | |
649 | pr_info("UV: NMI hub list @ 0x%p (%d)\n", uv_hub_nmi_list, size); | |
650 | BUG_ON(!uv_hub_nmi_list); | |
651 | size = sizeof(struct uv_hub_nmi_s); | |
652 | for_each_present_cpu(cpu) { | |
653 | nid = cpu_to_node(cpu); | |
654 | if (uv_hub_nmi_list[nid] == NULL) { | |
655 | uv_hub_nmi_list[nid] = kzalloc_node(size, | |
656 | GFP_KERNEL, nid); | |
657 | BUG_ON(!uv_hub_nmi_list[nid]); | |
658 | raw_spin_lock_init(&(uv_hub_nmi_list[nid]->nmi_lock)); | |
659 | atomic_set(&uv_hub_nmi_list[nid]->cpu_owner, -1); | |
660 | } | |
661 | uv_hub_nmi_per(cpu) = uv_hub_nmi_list[nid]; | |
662 | } | |
8a1f4653 | 663 | BUG_ON(!alloc_cpumask_var(&uv_nmi_cpu_mask, GFP_KERNEL)); |
0d12ef0c MT |
664 | } |
665 | ||
666 |