Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Suspend support specific for i386. | |
3 | * | |
4 | * Distribute under GPLv2 | |
5 | * | |
6 | * Copyright (c) 2002 Pavel Machek <pavel@suse.cz> | |
7 | * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org> | |
8 | */ | |
9 | ||
1da177e4 | 10 | #include <linux/suspend.h> |
f6783d20 SL |
11 | #include <linux/smp.h> |
12 | ||
13 | #include <asm/pgtable.h> | |
14 | #include <asm/proto.h> | |
27b07da7 | 15 | #include <asm/mtrr.h> |
f6783d20 | 16 | #include <asm/page.h> |
a03a3e28 | 17 | #include <asm/mce.h> |
83b8e28b | 18 | #include <asm/xcr.h> |
a8af7898 | 19 | #include <asm/suspend.h> |
1da177e4 LT |
20 | |
21 | static struct saved_context saved_context; | |
22 | ||
23 | unsigned long saved_context_ebx; | |
24 | unsigned long saved_context_esp, saved_context_ebp; | |
25 | unsigned long saved_context_esi, saved_context_edi; | |
26 | unsigned long saved_context_eflags; | |
27 | ||
cae45957 | 28 | static void __save_processor_state(struct saved_context *ctxt) |
1da177e4 | 29 | { |
3ebad590 | 30 | mtrr_save_fixed_ranges(NULL); |
1da177e4 LT |
31 | kernel_fpu_begin(); |
32 | ||
33 | /* | |
34 | * descriptor tables | |
35 | */ | |
db965984 PC |
36 | store_gdt(&ctxt->gdt); |
37 | store_idt(&ctxt->idt); | |
38 | store_tr(ctxt->tr); | |
1da177e4 LT |
39 | |
40 | /* | |
41 | * segment registers | |
42 | */ | |
db965984 PC |
43 | savesegment(es, ctxt->es); |
44 | savesegment(fs, ctxt->fs); | |
45 | savesegment(gs, ctxt->gs); | |
46 | savesegment(ss, ctxt->ss); | |
1da177e4 LT |
47 | |
48 | /* | |
c5759124 | 49 | * control registers |
1da177e4 | 50 | */ |
4bb0d3ec ZA |
51 | ctxt->cr0 = read_cr0(); |
52 | ctxt->cr2 = read_cr2(); | |
53 | ctxt->cr3 = read_cr3(); | |
e532c06f | 54 | ctxt->cr4 = read_cr4_safe(); |
1da177e4 LT |
55 | } |
56 | ||
db965984 | 57 | /* Needed by apm.c */ |
1da177e4 LT |
58 | void save_processor_state(void) |
59 | { | |
60 | __save_processor_state(&saved_context); | |
61 | } | |
db965984 | 62 | EXPORT_SYMBOL(save_processor_state); |
1da177e4 | 63 | |
08967f94 | 64 | static void do_fpu_end(void) |
1da177e4 | 65 | { |
08967f94 SL |
66 | /* |
67 | * Restore FPU regs if necessary. | |
68 | */ | |
69 | kernel_fpu_end(); | |
1da177e4 LT |
70 | } |
71 | ||
1da177e4 LT |
72 | static void fix_processor_context(void) |
73 | { | |
74 | int cpu = smp_processor_id(); | |
db965984 | 75 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
1da177e4 | 76 | |
db965984 PC |
77 | set_tss_desc(cpu, t); /* |
78 | * This just modifies memory; should not be | |
79 | * necessary. But... This is necessary, because | |
80 | * 386 hardware has concept of busy TSS or some | |
81 | * similar stupidity. | |
82 | */ | |
1da177e4 LT |
83 | |
84 | load_TR_desc(); /* This does ltr */ | |
85 | load_LDT(¤t->active_mm->context); /* This does lldt */ | |
86 | ||
87 | /* | |
88 | * Now maybe reload the debug registers | |
89 | */ | |
0f534093 RM |
90 | if (current->thread.debugreg7) { |
91 | set_debugreg(current->thread.debugreg0, 0); | |
92 | set_debugreg(current->thread.debugreg1, 1); | |
93 | set_debugreg(current->thread.debugreg2, 2); | |
94 | set_debugreg(current->thread.debugreg3, 3); | |
1cc6f12e | 95 | /* no 4 and 5 */ |
0f534093 RM |
96 | set_debugreg(current->thread.debugreg6, 6); |
97 | set_debugreg(current->thread.debugreg7, 7); | |
1da177e4 LT |
98 | } |
99 | ||
100 | } | |
101 | ||
cae45957 | 102 | static void __restore_processor_state(struct saved_context *ctxt) |
1da177e4 | 103 | { |
1da177e4 LT |
104 | /* |
105 | * control registers | |
106 | */ | |
e532c06f DF |
107 | /* cr4 was introduced in the Pentium CPU */ |
108 | if (ctxt->cr4) | |
109 | write_cr4(ctxt->cr4); | |
4bb0d3ec ZA |
110 | write_cr3(ctxt->cr3); |
111 | write_cr2(ctxt->cr2); | |
30d6b2f3 | 112 | write_cr0(ctxt->cr0); |
1da177e4 | 113 | |
8d783b3e PM |
114 | /* |
115 | * now restore the descriptor tables to their proper values | |
116 | * ltr is done i fix_processor_context(). | |
117 | */ | |
db965984 PC |
118 | load_gdt(&ctxt->gdt); |
119 | load_idt(&ctxt->idt); | |
8d783b3e | 120 | |
1da177e4 LT |
121 | /* |
122 | * segment registers | |
123 | */ | |
db965984 PC |
124 | loadsegment(es, ctxt->es); |
125 | loadsegment(fs, ctxt->fs); | |
126 | loadsegment(gs, ctxt->gs); | |
127 | loadsegment(ss, ctxt->ss); | |
1da177e4 | 128 | |
1da177e4 LT |
129 | /* |
130 | * sysenter MSRs | |
131 | */ | |
132 | if (boot_cpu_has(X86_FEATURE_SEP)) | |
6fe940d6 | 133 | enable_sep_cpu(); |
1da177e4 | 134 | |
83b8e28b SS |
135 | /* |
136 | * restore XCR0 for xsave capable cpu's. | |
137 | */ | |
138 | if (cpu_has_xsave) | |
139 | xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask); | |
140 | ||
1da177e4 LT |
141 | fix_processor_context(); |
142 | do_fpu_end(); | |
3b520b23 | 143 | mtrr_ap_init(); |
31ab269a | 144 | mcheck_init(&boot_cpu_data); |
1da177e4 LT |
145 | } |
146 | ||
db965984 | 147 | /* Needed by apm.c */ |
1da177e4 LT |
148 | void restore_processor_state(void) |
149 | { | |
150 | __restore_processor_state(&saved_context); | |
151 | } | |
1da177e4 | 152 | EXPORT_SYMBOL(restore_processor_state); |