[deliverable/linux.git] / arch / x86 / ras / mce_amd_inj.c

/*
 * A simple MCE injection facility for testing different aspects of the RAS
 * code. This driver should be built as module so that it can be loaded
 * on production kernels for testing purposes.
 *
 * This file may be distributed under the terms of the GNU General Public
 * License version 2.
 *
 * Copyright (c) 2010-15:  Borislav Petkov <bp@alien8.de>
 *			Advanced Micro Devices Inc.
 */

#include <linux/kobject.h>
#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/cpu.h>
#include <linux/string.h>
#include <linux/uaccess.h>
#include <linux/pci.h>

#include <asm/mce.h>
#include <asm/amd_nb.h>
#include <asm/irq_vectors.h>

#include "../kernel/cpu/mcheck/mce-internal.h"

/*
 * Collect all the MCi_XXX settings
 */
static struct mce i_mce;
static struct dentry *dfs_inj;

static u8 n_banks;

#define MAX_FLAG_OPT_SIZE	3
#define NBCFG			0x44

enum injection_type {
	SW_INJ = 0,	/* SW injection, simply decode the error */
	HW_INJ,		/* Trigger a #MC */
	DFR_INT_INJ,    /* Trigger Deferred error interrupt */
	THR_INT_INJ,    /* Trigger threshold interrupt */
	N_INJ_TYPES,
};

static const char * const flags_options[] = {
	[SW_INJ] = "sw",
	[HW_INJ] = "hw",
	[DFR_INT_INJ] = "df",
	[THR_INT_INJ] = "th",
	NULL
};

/* Set default injection to SW_INJ */
static enum injection_type inj_type = SW_INJ;

#define MCE_INJECT_SET(reg)						\
static int inj_##reg##_set(void *data, u64 val)				\
{									\
	struct mce *m = (struct mce *)data;				\
									\
	m->reg = val;							\
	return 0;							\
}

MCE_INJECT_SET(status);
MCE_INJECT_SET(misc);
MCE_INJECT_SET(addr);

#define MCE_INJECT_GET(reg)						\
static int inj_##reg##_get(void *data, u64 *val)			\
{									\
	struct mce *m = (struct mce *)data;				\
									\
	*val = m->reg;							\
	return 0;							\
}

MCE_INJECT_GET(status);
MCE_INJECT_GET(misc);
MCE_INJECT_GET(addr);

DEFINE_SIMPLE_ATTRIBUTE(status_fops, inj_status_get, inj_status_set, "%llx\n");
DEFINE_SIMPLE_ATTRIBUTE(misc_fops, inj_misc_get, inj_misc_set, "%llx\n");
DEFINE_SIMPLE_ATTRIBUTE(addr_fops, inj_addr_get, inj_addr_set, "%llx\n");

/*
 * Caller needs to be make sure this cpu doesn't disappear
 * from under us, i.e.: get_cpu/put_cpu.
 */
static int toggle_hw_mce_inject(unsigned int cpu, bool enable)
{
	u32 l, h;
	int err;

	err = rdmsr_on_cpu(cpu, MSR_K7_HWCR, &l, &h);
	if (err) {
		pr_err("%s: error reading HWCR\n", __func__);
		return err;
	}

	enable ? (l |= BIT(18)) : (l &= ~BIT(18));

	err = wrmsr_on_cpu(cpu, MSR_K7_HWCR, l, h);
	if (err)
		pr_err("%s: error writing HWCR\n", __func__);

	return err;
}

static int __set_inj(const char *buf)
{
	int i;

	for (i = 0; i < N_INJ_TYPES; i++) {
		if (!strncmp(flags_options[i], buf, strlen(flags_options[i]))) {
			inj_type = i;
			return 0;
		}
	}
	return -EINVAL;
}

static ssize_t flags_read(struct file *filp, char __user *ubuf,
			  size_t cnt, loff_t *ppos)
{
	char buf[MAX_FLAG_OPT_SIZE];
	int n;

	n = sprintf(buf, "%s\n", flags_options[inj_type]);

	return simple_read_from_buffer(ubuf, cnt, ppos, buf, n);
}

static ssize_t flags_write(struct file *filp, const char __user *ubuf,
			   size_t cnt, loff_t *ppos)
{
	char buf[MAX_FLAG_OPT_SIZE], *__buf;
	int err;

	if (cnt > MAX_FLAG_OPT_SIZE)
		return -EINVAL;

	if (copy_from_user(&buf, ubuf, cnt))
		return -EFAULT;

	buf[cnt - 1] = 0;

	/* strip whitespace */
	__buf = strstrip(buf);

	err = __set_inj(__buf);
	if (err) {
		pr_err("%s: Invalid flags value: %s\n", __func__, __buf);
		return err;
	}

	*ppos += cnt;

	return cnt;
}

static const struct file_operations flags_fops = {
	.read           = flags_read,
	.write          = flags_write,
	.llseek         = generic_file_llseek,
};

/*
 * On which CPU to inject?
 */
MCE_INJECT_GET(extcpu);

static int inj_extcpu_set(void *data, u64 val)
{
	struct mce *m = (struct mce *)data;

	if (val >= nr_cpu_ids || !cpu_online(val)) {
		pr_err("%s: Invalid CPU: %llu\n", __func__, val);
		return -EINVAL;
	}
	m->extcpu = val;
	return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(extcpu_fops, inj_extcpu_get, inj_extcpu_set, "%llu\n");

static void trigger_mce(void *info)
{
	asm volatile("int $18");
}

static void trigger_dfr_int(void *info)
{
	asm volatile("int %0" :: "i" (DEFERRED_ERROR_VECTOR));
}

static void trigger_thr_int(void *info)
{
	asm volatile("int %0" :: "i" (THRESHOLD_APIC_VECTOR));
}

static u32 get_nbc_for_node(int node_id)
{
	struct cpuinfo_x86 *c = &boot_cpu_data;
	u32 cores_per_node;

	cores_per_node = c->x86_max_cores / amd_get_nodes_per_socket();

	return cores_per_node * node_id;
}

static void toggle_nb_mca_mst_cpu(u16 nid)
{
	struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
	u32 val;
	int err;

	if (!F3)
		return;

	err = pci_read_config_dword(F3, NBCFG, &val);
	if (err) {
		pr_err("%s: Error reading F%dx%03x.\n",
		       __func__, PCI_FUNC(F3->devfn), NBCFG);
		return;
	}

	if (val & BIT(27))
		return;

	pr_err("%s: Set D18F3x44[NbMcaToMstCpuEn] which BIOS hasn't done.\n",
	       __func__);

	val |= BIT(27);
	err = pci_write_config_dword(F3, NBCFG, val);
	if (err)
		pr_err("%s: Error writing F%dx%03x.\n",
		       __func__, PCI_FUNC(F3->devfn), NBCFG);
}

static void do_inject(void)
{
	u64 mcg_status = 0;
	unsigned int cpu = i_mce.extcpu;
	u8 b = i_mce.bank;

	if (i_mce.misc)
		i_mce.status |= MCI_STATUS_MISCV;

	if (inj_type == SW_INJ) {
		mce_inject_log(&i_mce);
		return;
	}

	/* prep MCE global settings for the injection */
	mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV;

	if (!(i_mce.status & MCI_STATUS_PCC))
		mcg_status |= MCG_STATUS_RIPV;

	/*
	 * Ensure necessary status bits for deferred errors:
	 * - MCx_STATUS[Deferred]: make sure it is a deferred error
	 * - MCx_STATUS[UC] cleared: deferred errors are _not_ UC
	 */
	if (inj_type == DFR_INT_INJ) {
		i_mce.status |= MCI_STATUS_DEFERRED;
		i_mce.status |= (i_mce.status & ~MCI_STATUS_UC);
	}

	/*
	 * For multi node CPUs, logging and reporting of bank 4 errors happens
	 * only on the node base core. Refer to D18F3x44[NbMcaToMstCpuEn] for
	 * Fam10h and later BKDGs.
	 */
	if (static_cpu_has(X86_FEATURE_AMD_DCM) && b == 4) {
		toggle_nb_mca_mst_cpu(amd_get_nb_id(cpu));
		cpu = get_nbc_for_node(amd_get_nb_id(cpu));
	}

	get_online_cpus();
	if (!cpu_online(cpu))
		goto err;

	toggle_hw_mce_inject(cpu, true);

	wrmsr_on_cpu(cpu, MSR_IA32_MCG_STATUS,
		     (u32)mcg_status, (u32)(mcg_status >> 32));

	wrmsr_on_cpu(cpu, MSR_IA32_MCx_STATUS(b),
		     (u32)i_mce.status, (u32)(i_mce.status >> 32));

	wrmsr_on_cpu(cpu, MSR_IA32_MCx_ADDR(b),
		     (u32)i_mce.addr, (u32)(i_mce.addr >> 32));

	wrmsr_on_cpu(cpu, MSR_IA32_MCx_MISC(b),
		     (u32)i_mce.misc, (u32)(i_mce.misc >> 32));

	toggle_hw_mce_inject(cpu, false);

	switch (inj_type) {
	case DFR_INT_INJ:
		smp_call_function_single(cpu, trigger_dfr_int, NULL, 0);
		break;
	case THR_INT_INJ:
		smp_call_function_single(cpu, trigger_thr_int, NULL, 0);
		break;
	default:
		smp_call_function_single(cpu, trigger_mce, NULL, 0);
	}

err:
	put_online_cpus();

}

/*
 * This denotes into which bank we're injecting and triggers
 * the injection, at the same time.
 */
static int inj_bank_set(void *data, u64 val)
{
	struct mce *m = (struct mce *)data;

	if (val >= n_banks) {
		pr_err("Non-existent MCE bank: %llu\n", val);
		return -EINVAL;
	}

	m->bank = val;
	do_inject();

	return 0;
}

MCE_INJECT_GET(bank);

DEFINE_SIMPLE_ATTRIBUTE(bank_fops, inj_bank_get, inj_bank_set, "%llu\n");

static const char readme_msg[] =
"Description of the files and their usages:\n"
"\n"
"Note1: i refers to the bank number below.\n"
"Note2: See respective BKDGs for the exact bit definitions of the files below\n"
"as they mirror the hardware registers.\n"
"\n"
"status:\t Set MCi_STATUS: the bits in that MSR control the error type and\n"
"\t attributes of the error which caused the MCE.\n"
"\n"
"misc:\t Set MCi_MISC: provide auxiliary info about the error. It is mostly\n"
"\t used for error thresholding purposes and its validity is indicated by\n"
"\t MCi_STATUS[MiscV].\n"
"\n"
"addr:\t Error address value to be written to MCi_ADDR. Log address information\n"
"\t associated with the error.\n"
"\n"
"cpu:\t The CPU to inject the error on.\n"
"\n"
"bank:\t Specify the bank you want to inject the error into: the number of\n"
"\t banks in a processor varies and is family/model-specific, therefore, the\n"
"\t supplied value is sanity-checked. Setting the bank value also triggers the\n"
"\t injection.\n"
"\n"
"flags:\t Injection type to be performed. Writing to this file will trigger a\n"
"\t real machine check, an APIC interrupt or invoke the error decoder routines\n"
"\t for AMD processors.\n"
"\n"
"\t Allowed error injection types:\n"
"\t  - \"sw\": Software error injection. Decode error to a human-readable \n"
"\t    format only. Safe to use.\n"
"\t  - \"hw\": Hardware error injection. Causes the #MC exception handler to \n"
"\t    handle the error. Be warned: might cause system panic if MCi_STATUS[PCC] \n"
"\t    is set. Therefore, consider setting (debugfs_mountpoint)/mce/fake_panic \n"
"\t    before injecting.\n"
"\t  - \"df\": Trigger APIC interrupt for Deferred error. Causes deferred \n"
"\t    error APIC interrupt handler to handle the error if the feature is \n"
"\t    is present in hardware. \n"
"\t  - \"th\": Trigger APIC interrupt for Threshold errors. Causes threshold \n"
"\t    APIC interrupt handler to handle the error. \n"
"\n";

static ssize_t
inj_readme_read(struct file *filp, char __user *ubuf,
		       size_t cnt, loff_t *ppos)
{
	return simple_read_from_buffer(ubuf, cnt, ppos,
					readme_msg, strlen(readme_msg));
}

static const struct file_operations readme_fops = {
	.read		= inj_readme_read,
};

static struct dfs_node {
	char *name;
	struct dentry *d;
	const struct file_operations *fops;
	umode_t perm;
} dfs_fls[] = {
	{ .name = "status",	.fops = &status_fops, .perm = S_IRUSR | S_IWUSR },
	{ .name = "misc",	.fops = &misc_fops,   .perm = S_IRUSR | S_IWUSR },
	{ .name = "addr",	.fops = &addr_fops,   .perm = S_IRUSR | S_IWUSR },
	{ .name = "bank",	.fops = &bank_fops,   .perm = S_IRUSR | S_IWUSR },
	{ .name = "flags",	.fops = &flags_fops,  .perm = S_IRUSR | S_IWUSR },
	{ .name = "cpu",	.fops = &extcpu_fops, .perm = S_IRUSR | S_IWUSR },
	{ .name = "README",	.fops = &readme_fops, .perm = S_IRUSR | S_IRGRP | S_IROTH },
};

static int __init init_mce_inject(void)
{
	int i;
	u64 cap;

	rdmsrl(MSR_IA32_MCG_CAP, cap);
	n_banks = cap & MCG_BANKCNT_MASK;

	dfs_inj = debugfs_create_dir("mce-inject", NULL);
	if (!dfs_inj)
		return -EINVAL;

	for (i = 0; i < ARRAY_SIZE(dfs_fls); i++) {
		dfs_fls[i].d = debugfs_create_file(dfs_fls[i].name,
						    dfs_fls[i].perm,
						    dfs_inj,
						    &i_mce,
						    dfs_fls[i].fops);

		if (!dfs_fls[i].d)
			goto err_dfs_add;
	}

	return 0;

err_dfs_add:
	while (--i >= 0)
		debugfs_remove(dfs_fls[i].d);

	debugfs_remove(dfs_inj);
	dfs_inj = NULL;

	return -ENOMEM;
}

static void __exit exit_mce_inject(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(dfs_fls); i++)
		debugfs_remove(dfs_fls[i].d);

	memset(&dfs_fls, 0, sizeof(dfs_fls));

	debugfs_remove(dfs_inj);
	dfs_inj = NULL;
}
module_init(init_mce_inject);
module_exit(exit_mce_inject);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Borislav Petkov <bp@alien8.de>");
MODULE_AUTHOR("AMD Inc.");
MODULE_DESCRIPTION("MCE injection facility for RAS testing");
Commit	Line	Data
9cdeb404	1	/*
fd19fcd6 BP	2	* A simple MCE injection facility for testing different aspects of the RAS
	3	* code. This driver should be built as module so that it can be loaded
	4	* on production kernels for testing purposes.
9cdeb404 BP	5	*
	6	* This file may be distributed under the terms of the GNU General Public
	7	* License version 2.
	8	*
6c36dfe9	9	* Copyright (c) 2010-15: Borislav Petkov <bp@alien8.de>
9cdeb404 BP	10	* Advanced Micro Devices Inc.
	11	*/
	12
	13	#include <linux/kobject.h>
fd19fcd6	14	#include <linux/debugfs.h>
51990e82	15	#include <linux/device.h>
80a2e2e3	16	#include <linux/module.h>
51756a50	17	#include <linux/cpu.h>
0451d14d AG	18	#include <linux/string.h>
0451d14d AG	19	#include <linux/uaccess.h>
fa20a2ed	20	#include <linux/pci.h>
a1300e50	21
9cdeb404	22	#include <asm/mce.h>
fa20a2ed	23	#include <asm/amd_nb.h>
a1300e50	24	#include <asm/irq_vectors.h>
9cdeb404	25
6c36dfe9	26	#include "../kernel/cpu/mcheck/mce-internal.h"
9cdeb404	27
9cdeb404 BP	28	/*
	29	* Collect all the MCi_XXX settings
	30	*/
	31	static struct mce i_mce;
fd19fcd6	32	static struct dentry *dfs_inj;
9cdeb404	33
685d46d7 AG	34	static u8 n_banks;
685d46d7 AG	35
0451d14d	36	#define MAX_FLAG_OPT_SIZE 3
fa20a2ed	37	#define NBCFG 0x44
0451d14d AG	38
	39	enum injection_type {
	40	SW_INJ = 0, /* SW injection, simply decode the error */
	41	HW_INJ, /* Trigger a #MC */
a1300e50 AG	42	DFR_INT_INJ, /* Trigger Deferred error interrupt */
a1300e50 AG	43	THR_INT_INJ, /* Trigger threshold interrupt */
0451d14d AG	44	N_INJ_TYPES,
	45	};
	46
	47	static const char * const flags_options[] = {
	48	[SW_INJ] = "sw",
	49	[HW_INJ] = "hw",
a1300e50 AG	50	[DFR_INT_INJ] = "df",
a1300e50 AG	51	[THR_INT_INJ] = "th",
0451d14d AG	52	NULL
	53	};
	54
	55	/* Set default injection to SW_INJ */
de277678	56	static enum injection_type inj_type = SW_INJ;
0451d14d	57
fd19fcd6 BP	58	#define MCE_INJECT_SET(reg) \
fd19fcd6 BP	59	static int inj_##reg##_set(void *data, u64 val) \
9cdeb404	60	{ \
fd19fcd6	61	struct mce m = (struct mce )data; \
9cdeb404	62	\
fd19fcd6 BP	63	m->reg = val; \
fd19fcd6 BP	64	return 0; \
9cdeb404 BP	65	}
9cdeb404 BP	66
fd19fcd6 BP	67	MCE_INJECT_SET(status);
	68	MCE_INJECT_SET(misc);
	69	MCE_INJECT_SET(addr);
9cdeb404	70
fd19fcd6 BP	71	#define MCE_INJECT_GET(reg) \
fd19fcd6 BP	72	static int inj_##reg##_get(void data, u64 val) \
9cdeb404	73	{ \
fd19fcd6 BP	74	struct mce m = (struct mce )data; \
	75	\
	76	*val = m->reg; \
	77	return 0; \
9cdeb404 BP	78	}
9cdeb404 BP	79
fd19fcd6 BP	80	MCE_INJECT_GET(status);
	81	MCE_INJECT_GET(misc);
	82	MCE_INJECT_GET(addr);
9cdeb404	83
fd19fcd6 BP	84	DEFINE_SIMPLE_ATTRIBUTE(status_fops, inj_status_get, inj_status_set, "%llx\n");
	85	DEFINE_SIMPLE_ATTRIBUTE(misc_fops, inj_misc_get, inj_misc_set, "%llx\n");
	86	DEFINE_SIMPLE_ATTRIBUTE(addr_fops, inj_addr_get, inj_addr_set, "%llx\n");
9cdeb404	87
21690934 BP	88	/*
	89	* Caller needs to be make sure this cpu doesn't disappear
	90	* from under us, i.e.: get_cpu/put_cpu.
	91	*/
	92	static int toggle_hw_mce_inject(unsigned int cpu, bool enable)
	93	{
	94	u32 l, h;
	95	int err;
	96
	97	err = rdmsr_on_cpu(cpu, MSR_K7_HWCR, &l, &h);
	98	if (err) {
	99	pr_err("%s: error reading HWCR\n", __func__);
	100	return err;
	101	}
	102
	103	enable ? (l \|= BIT(18)) : (l &= ~BIT(18));
	104
	105	err = wrmsr_on_cpu(cpu, MSR_K7_HWCR, l, h);
	106	if (err)
	107	pr_err("%s: error writing HWCR\n", __func__);
	108
	109	return err;
	110	}
	111
0451d14d	112	static int __set_inj(const char *buf)
b18f3864	113	{
0451d14d AG	114	int i;
	115
	116	for (i = 0; i < N_INJ_TYPES; i++) {
	117	if (!strncmp(flags_options[i], buf, strlen(flags_options[i]))) {
	118	inj_type = i;
	119	return 0;
	120	}
	121	}
	122	return -EINVAL;
	123	}
	124
	125	static ssize_t flags_read(struct file filp, char __user ubuf,
	126	size_t cnt, loff_t *ppos)
	127	{
	128	char buf[MAX_FLAG_OPT_SIZE];
	129	int n;
b18f3864	130
0451d14d	131	n = sprintf(buf, "%s\n", flags_options[inj_type]);
b18f3864	132
0451d14d	133	return simple_read_from_buffer(ubuf, cnt, ppos, buf, n);
b18f3864 BP	134	}
b18f3864 BP	135
0451d14d AG	136	static ssize_t flags_write(struct file filp, const char __user ubuf,
0451d14d AG	137	size_t cnt, loff_t *ppos)
b18f3864	138	{
0451d14d AG	139	char buf[MAX_FLAG_OPT_SIZE], *__buf;
0451d14d AG	140	int err;
b18f3864	141
0451d14d	142	if (cnt > MAX_FLAG_OPT_SIZE)
85c9306d	143	return -EINVAL;
0451d14d AG	144
	145	if (copy_from_user(&buf, ubuf, cnt))
	146	return -EFAULT;
	147
	148	buf[cnt - 1] = 0;
	149
	150	/* strip whitespace */
	151	__buf = strstrip(buf);
	152
	153	err = __set_inj(__buf);
	154	if (err) {
	155	pr_err("%s: Invalid flags value: %s\n", __func__, __buf);
	156	return err;
	157	}
	158
85c9306d	159	*ppos += cnt;
0451d14d	160
85c9306d	161	return cnt;
b18f3864 BP	162	}
b18f3864 BP	163
0451d14d AG	164	static const struct file_operations flags_fops = {
	165	.read = flags_read,
	166	.write = flags_write,
	167	.llseek = generic_file_llseek,
	168	};
b18f3864 BP	169
	170	/*
	171	* On which CPU to inject?
	172	*/
	173	MCE_INJECT_GET(extcpu);
	174
	175	static int inj_extcpu_set(void *data, u64 val)
	176	{
	177	struct mce m = (struct mce )data;
	178
	179	if (val >= nr_cpu_ids \|\| !cpu_online(val)) {
	180	pr_err("%s: Invalid CPU: %llu\n", __func__, val);
	181	return -EINVAL;
	182	}
	183	m->extcpu = val;
	184	return 0;
	185	}
	186
	187	DEFINE_SIMPLE_ATTRIBUTE(extcpu_fops, inj_extcpu_get, inj_extcpu_set, "%llu\n");
	188
51756a50 BP	189	static void trigger_mce(void *info)
	190	{
	191	asm volatile("int $18");
	192	}
	193
a1300e50 AG	194	static void trigger_dfr_int(void *info)
	195	{
	196	asm volatile("int %0" :: "i" (DEFERRED_ERROR_VECTOR));
	197	}
	198
	199	static void trigger_thr_int(void *info)
	200	{
	201	asm volatile("int %0" :: "i" (THRESHOLD_APIC_VECTOR));
	202	}
	203
fa20a2ed AG	204	static u32 get_nbc_for_node(int node_id)
	205	{
	206	struct cpuinfo_x86 *c = &boot_cpu_data;
	207	u32 cores_per_node;
	208
	209	cores_per_node = c->x86_max_cores / amd_get_nodes_per_socket();
	210
	211	return cores_per_node * node_id;
	212	}
	213
	214	static void toggle_nb_mca_mst_cpu(u16 nid)
	215	{
	216	struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
	217	u32 val;
	218	int err;
	219
	220	if (!F3)
	221	return;
	222
	223	err = pci_read_config_dword(F3, NBCFG, &val);
	224	if (err) {
	225	pr_err("%s: Error reading F%dx%03x.\n",
	226	__func__, PCI_FUNC(F3->devfn), NBCFG);
	227	return;
	228	}
	229
	230	if (val & BIT(27))
	231	return;
	232
	233	pr_err("%s: Set D18F3x44[NbMcaToMstCpuEn] which BIOS hasn't done.\n",
	234	__func__);
	235
	236	val \|= BIT(27);
	237	err = pci_write_config_dword(F3, NBCFG, val);
	238	if (err)
	239	pr_err("%s: Error writing F%dx%03x.\n",
	240	__func__, PCI_FUNC(F3->devfn), NBCFG);
	241	}
	242
51756a50 BP	243	static void do_inject(void)
	244	{
	245	u64 mcg_status = 0;
	246	unsigned int cpu = i_mce.extcpu;
	247	u8 b = i_mce.bank;
	248
cda9459d BP	249	if (i_mce.misc)
	250	i_mce.status \|= MCI_STATUS_MISCV;
	251
0451d14d	252	if (inj_type == SW_INJ) {
6c36dfe9	253	mce_inject_log(&i_mce);
51756a50 BP	254	return;
	255	}
	256
51756a50 BP	257	/* prep MCE global settings for the injection */
	258	mcg_status = MCG_STATUS_MCIP \| MCG_STATUS_EIPV;
	259
	260	if (!(i_mce.status & MCI_STATUS_PCC))
	261	mcg_status \|= MCG_STATUS_RIPV;
	262
a1300e50 AG	263	/*
	264	* Ensure necessary status bits for deferred errors:
	265	* - MCx_STATUS[Deferred]: make sure it is a deferred error
	266	* - MCx_STATUS[UC] cleared: deferred errors are _not_ UC
	267	*/
	268	if (inj_type == DFR_INT_INJ) {
	269	i_mce.status \|= MCI_STATUS_DEFERRED;
	270	i_mce.status \|= (i_mce.status & ~MCI_STATUS_UC);
	271	}
	272
fa20a2ed AG	273	/*
	274	* For multi node CPUs, logging and reporting of bank 4 errors happens
	275	* only on the node base core. Refer to D18F3x44[NbMcaToMstCpuEn] for
	276	* Fam10h and later BKDGs.
	277	*/
	278	if (static_cpu_has(X86_FEATURE_AMD_DCM) && b == 4) {
	279	toggle_nb_mca_mst_cpu(amd_get_nb_id(cpu));
	280	cpu = get_nbc_for_node(amd_get_nb_id(cpu));
	281	}
	282
6d1e9bf5 BP	283	get_online_cpus();
	284	if (!cpu_online(cpu))
	285	goto err;
	286
51756a50 BP	287	toggle_hw_mce_inject(cpu, true);
	288
	289	wrmsr_on_cpu(cpu, MSR_IA32_MCG_STATUS,
	290	(u32)mcg_status, (u32)(mcg_status >> 32));
	291
	292	wrmsr_on_cpu(cpu, MSR_IA32_MCx_STATUS(b),
	293	(u32)i_mce.status, (u32)(i_mce.status >> 32));
	294
	295	wrmsr_on_cpu(cpu, MSR_IA32_MCx_ADDR(b),
	296	(u32)i_mce.addr, (u32)(i_mce.addr >> 32));
	297
	298	wrmsr_on_cpu(cpu, MSR_IA32_MCx_MISC(b),
	299	(u32)i_mce.misc, (u32)(i_mce.misc >> 32));
	300
	301	toggle_hw_mce_inject(cpu, false);
	302
a1300e50 AG	303	switch (inj_type) {
	304	case DFR_INT_INJ:
	305	smp_call_function_single(cpu, trigger_dfr_int, NULL, 0);
	306	break;
	307	case THR_INT_INJ:
	308	smp_call_function_single(cpu, trigger_thr_int, NULL, 0);
	309	break;
	310	default:
	311	smp_call_function_single(cpu, trigger_mce, NULL, 0);
	312	}
51756a50 BP	313
	314	err:
	315	put_online_cpus();
	316
	317	}
	318
9cdeb404 BP	319	/*
	320	* This denotes into which bank we're injecting and triggers
	321	* the injection, at the same time.
	322	*/
fd19fcd6	323	static int inj_bank_set(void *data, u64 val)
9cdeb404	324	{
fd19fcd6	325	struct mce m = (struct mce )data;
9cdeb404	326
685d46d7 AG	327	if (val >= n_banks) {
	328	pr_err("Non-existent MCE bank: %llu\n", val);
	329	return -EINVAL;
fd19fcd6	330	}
9cdeb404	331
fd19fcd6	332	m->bank = val;
51756a50	333	do_inject();
9cdeb404	334
fd19fcd6	335	return 0;
9cdeb404 BP	336	}
9cdeb404 BP	337
e7f2ea1d	338	MCE_INJECT_GET(bank);
9cdeb404	339
fd19fcd6 BP	340	DEFINE_SIMPLE_ATTRIBUTE(bank_fops, inj_bank_get, inj_bank_set, "%llu\n");
fd19fcd6 BP	341
99e21fea	342	static const char readme_msg[] =
f2f3dca1 BP	343	"Description of the files and their usages:\n"
	344	"\n"
	345	"Note1: i refers to the bank number below.\n"
	346	"Note2: See respective BKDGs for the exact bit definitions of the files below\n"
	347	"as they mirror the hardware registers.\n"
	348	"\n"
	349	"status:\t Set MCi_STATUS: the bits in that MSR control the error type and\n"
	350	"\t attributes of the error which caused the MCE.\n"
	351	"\n"
	352	"misc:\t Set MCi_MISC: provide auxiliary info about the error. It is mostly\n"
	353	"\t used for error thresholding purposes and its validity is indicated by\n"
	354	"\t MCi_STATUS[MiscV].\n"
	355	"\n"
	356	"addr:\t Error address value to be written to MCi_ADDR. Log address information\n"
	357	"\t associated with the error.\n"
	358	"\n"
	359	"cpu:\t The CPU to inject the error on.\n"
	360	"\n"
	361	"bank:\t Specify the bank you want to inject the error into: the number of\n"
	362	"\t banks in a processor varies and is family/model-specific, therefore, the\n"
	363	"\t supplied value is sanity-checked. Setting the bank value also triggers the\n"
	364	"\t injection.\n"
	365	"\n"
	366	"flags:\t Injection type to be performed. Writing to this file will trigger a\n"
	367	"\t real machine check, an APIC interrupt or invoke the error decoder routines\n"
	368	"\t for AMD processors.\n"
	369	"\n"
	370	"\t Allowed error injection types:\n"
	371	"\t - \"sw\": Software error injection. Decode error to a human-readable \n"
	372	"\t format only. Safe to use.\n"
	373	"\t - \"hw\": Hardware error injection. Causes the #MC exception handler to \n"
	374	"\t handle the error. Be warned: might cause system panic if MCi_STATUS[PCC] \n"
	375	"\t is set. Therefore, consider setting (debugfs_mountpoint)/mce/fake_panic \n"
	376	"\t before injecting.\n"
a1300e50 AG	377	"\t - \"df\": Trigger APIC interrupt for Deferred error. Causes deferred \n"
	378	"\t error APIC interrupt handler to handle the error if the feature is \n"
	379	"\t is present in hardware. \n"
	380	"\t - \"th\": Trigger APIC interrupt for Threshold errors. Causes threshold \n"
	381	"\t APIC interrupt handler to handle the error. \n"
f2f3dca1	382	"\n";
99e21fea AG	383
	384	static ssize_t
	385	inj_readme_read(struct file filp, char __user ubuf,
	386	size_t cnt, loff_t *ppos)
	387	{
	388	return simple_read_from_buffer(ubuf, cnt, ppos,
	389	readme_msg, strlen(readme_msg));
	390	}
	391
	392	static const struct file_operations readme_fops = {
	393	.read = inj_readme_read,
	394	};
	395
8c2b117f	396	static struct dfs_node {
fd19fcd6 BP	397	char *name;
	398	struct dentry *d;
	399	const struct file_operations *fops;
4c6034e8	400	umode_t perm;
fd19fcd6	401	} dfs_fls[] = {
4c6034e8 AG	402	{ .name = "status", .fops = &status_fops, .perm = S_IRUSR \| S_IWUSR },
	403	{ .name = "misc", .fops = &misc_fops, .perm = S_IRUSR \| S_IWUSR },
	404	{ .name = "addr", .fops = &addr_fops, .perm = S_IRUSR \| S_IWUSR },
	405	{ .name = "bank", .fops = &bank_fops, .perm = S_IRUSR \| S_IWUSR },
	406	{ .name = "flags", .fops = &flags_fops, .perm = S_IRUSR \| S_IWUSR },
	407	{ .name = "cpu", .fops = &extcpu_fops, .perm = S_IRUSR \| S_IWUSR },
99e21fea	408	{ .name = "README", .fops = &readme_fops, .perm = S_IRUSR \| S_IRGRP \| S_IROTH },
9cdeb404 BP	409	};
9cdeb404 BP	410
fd19fcd6	411	static int __init init_mce_inject(void)
9cdeb404	412	{
fd19fcd6	413	int i;
685d46d7 AG	414	u64 cap;
	415
	416	rdmsrl(MSR_IA32_MCG_CAP, cap);
	417	n_banks = cap & MCG_BANKCNT_MASK;
9cdeb404	418
fd19fcd6 BP	419	dfs_inj = debugfs_create_dir("mce-inject", NULL);
fd19fcd6 BP	420	if (!dfs_inj)
9cdeb404 BP	421	return -EINVAL;
9cdeb404 BP	422
fd19fcd6 BP	423	for (i = 0; i < ARRAY_SIZE(dfs_fls); i++) {
fd19fcd6 BP	424	dfs_fls[i].d = debugfs_create_file(dfs_fls[i].name,
4c6034e8	425	dfs_fls[i].perm,
fd19fcd6 BP	426	dfs_inj,
	427	&i_mce,
	428	dfs_fls[i].fops);
9cdeb404	429
fd19fcd6 BP	430	if (!dfs_fls[i].d)
fd19fcd6 BP	431	goto err_dfs_add;
9cdeb404	432	}
fd19fcd6	433
9cdeb404 BP	434	return 0;
9cdeb404 BP	435
fd19fcd6	436	err_dfs_add:
df4b2a30	437	while (--i >= 0)
fd19fcd6	438	debugfs_remove(dfs_fls[i].d);
9cdeb404	439
fd19fcd6 BP	440	debugfs_remove(dfs_inj);
fd19fcd6 BP	441	dfs_inj = NULL;
9cdeb404	442
fd19fcd6	443	return -ENOMEM;
9cdeb404 BP	444	}
9cdeb404 BP	445
fd19fcd6	446	static void __exit exit_mce_inject(void)
9cdeb404 BP	447	{
	448	int i;
	449
fd19fcd6 BP	450	for (i = 0; i < ARRAY_SIZE(dfs_fls); i++)
fd19fcd6 BP	451	debugfs_remove(dfs_fls[i].d);
9cdeb404	452
fd19fcd6	453	memset(&dfs_fls, 0, sizeof(dfs_fls));
9cdeb404	454
fd19fcd6 BP	455	debugfs_remove(dfs_inj);
fd19fcd6 BP	456	dfs_inj = NULL;
9cdeb404	457	}
fd19fcd6 BP	458	module_init(init_mce_inject);
fd19fcd6 BP	459	module_exit(exit_mce_inject);
9cdeb404 BP	460
9cdeb404 BP	461	MODULE_LICENSE("GPL");
43aff26c	462	MODULE_AUTHOR("Borislav Petkov <bp@alien8.de>");
9cdeb404	463	MODULE_AUTHOR("AMD Inc.");
fd19fcd6	464	MODULE_DESCRIPTION("MCE injection facility for RAS testing");