[deliverable/linux.git] / arch / x86 / realmode / rm / reboot_32.S

#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/segment.h>
#include <asm/page_types.h>
#include "realmode.h"

/*
 * The following code and data reboots the machine by switching to real
 * mode and jumping to the BIOS reset entry point, as if the CPU has
 * really been reset.  The previous version asked the keyboard
 * controller to pulse the CPU reset line, which is more thorough, but
 * doesn't work with at least one type of 486 motherboard.  It is easy
 * to stop this code working; hence the copious comments.
 *
 * This code is called with the restart type (0 = BIOS, 1 = APM) in %eax.
 */
	.section ".text32", "ax"
	.code32

	.balign	16
ENTRY(machine_real_restart_asm)
	/* Set up the IDT for real mode. */
	lidtl	pa_machine_real_restart_idt

	/*
	 * Set up a GDT from which we can load segment descriptors for real
	 * mode.  The GDT is not used in real mode; it is just needed here to
	 * prepare the descriptors.
	 */
	lgdtl	pa_machine_real_restart_gdt

	/*
	 * Load the data segment registers with 16-bit compatible values
	 */
	movl	$16, %ecx
	movl	%ecx, %ds
	movl	%ecx, %es
	movl	%ecx, %fs
	movl	%ecx, %gs
	movl	%ecx, %ss
	ljmpw	$8, $1f

/*
 * This is 16-bit protected mode code to disable paging and the cache,
 * switch to real mode and jump to the BIOS reset code.
 *
 * The instruction that switches to real mode by writing to CR0 must be
 * followed immediately by a far jump instruction, which set CS to a
 * valid value for real mode, and flushes the prefetch queue to avoid
 * running instructions that have already been decoded in protected
 * mode.
 *
 * Clears all the flags except ET, especially PG (paging), PE
 * (protected-mode enable) and TS (task switch for coprocessor state
 * save).  Flushes the TLB after paging has been disabled.  Sets CD and
 * NW, to disable the cache on a 486, and invalidates the cache.  This
 * is more like the state of a 486 after reset.  I don't know if
 * something else should be done for other chips.
 *
 * More could be done here to set up the registers as if a CPU reset had
 * occurred; hopefully real BIOSs don't assume much.  This is not the
 * actual BIOS entry point, anyway (that is at 0xfffffff0).
 *
 * Most of this work is probably excessive, but it is what is tested.
 */
	.text
	.code16

	.balign	16
machine_real_restart_asm16:
1:
	xorl	%ecx, %ecx
	movl	%cr0, %edx
	andl	$0x00000011, %edx
	orl	$0x60000000, %edx
	movl	%edx, %cr0
	movl	%ecx, %cr3
	movl	%cr0, %edx
	testl	$0x60000000, %edx	/* If no cache bits -> no wbinvd */
	jz	2f
	wbinvd
2:
	andb	$0x10, %dl
	movl	%edx, %cr0
	LJMPW_RM(3f)
3:
	andw	%ax, %ax
	jz	bios

apm:
	movw	$0x1000, %ax
	movw	%ax, %ss
	movw	$0xf000, %sp
	movw	$0x5307, %ax
	movw	$0x0001, %bx
	movw	$0x0003, %cx
	int	$0x15
	/* This should never return... */

bios:
	ljmpw	$0xf000, $0xfff0

	.section ".rodata", "a"

	.balign	16
GLOBAL(machine_real_restart_idt)
	.word	0xffff		/* Length - real mode default value */
	.long	0		/* Base - real mode default value */
END(machine_real_restart_idt)

	.balign	16
GLOBAL(machine_real_restart_gdt)
	/* Self-pointer */
	.word	0xffff		/* Length - real mode default value */
	.long	pa_machine_real_restart_gdt
	.word	0

	/*
	 * 16-bit code segment pointing to real_mode_seg
	 * Selector value 8
	 */
	.word	0xffff		/* Limit */
	.long	0x9b000000 + pa_real_mode_base
	.word	0

	/*
	 * 16-bit data segment with the selector value 16 = 0x10 and
	 * base value 0x100; since this is consistent with real mode
	 * semantics we don't have to reload the segments once CR0.PE = 0.
	 */
	.quad	GDT_ENTRY(0x0093, 0x100, 0xffff)
END(machine_real_restart_gdt)
Commit	Line	Data
3d35ac34 PA	1	#include <linux/linkage.h>
	2	#include <linux/init.h>
	3	#include <asm/segment.h>
	4	#include <asm/page_types.h>
e5684ec4	5	#include "realmode.h"
3d35ac34 PA	6
	7	/*
	8	* The following code and data reboots the machine by switching to real
	9	* mode and jumping to the BIOS reset entry point, as if the CPU has
	10	* really been reset. The previous version asked the keyboard
	11	* controller to pulse the CPU reset line, which is more thorough, but
	12	* doesn't work with at least one type of 486 motherboard. It is easy
	13	* to stop this code working; hence the copious comments.
	14	*
	15	* This code is called with the restart type (0 = BIOS, 1 = APM) in %eax.
	16	*/
5a8c9aeb	17	.section ".text32", "ax"
3d35ac34	18	.code32
3d35ac34	19
8e029fcd JS	20	.balign 16
8e029fcd JS	21	ENTRY(machine_real_restart_asm)
3d35ac34	22	/* Set up the IDT for real mode. */
5a8c9aeb	23	lidtl pa_machine_real_restart_idt
3d35ac34 PA	24
	25	/*
	26	* Set up a GDT from which we can load segment descriptors for real
	27	* mode. The GDT is not used in real mode; it is just needed here to
	28	* prepare the descriptors.
	29	*/
5a8c9aeb	30	lgdtl pa_machine_real_restart_gdt
3d35ac34 PA	31
	32	/*
	33	* Load the data segment registers with 16-bit compatible values
	34	*/
	35	movl $16, %ecx
	36	movl %ecx, %ds
	37	movl %ecx, %es
	38	movl %ecx, %fs
	39	movl %ecx, %gs
	40	movl %ecx, %ss
5a8c9aeb	41	ljmpw $8, $1f
3d35ac34 PA	42
	43	/*
	44	* This is 16-bit protected mode code to disable paging and the cache,
	45	* switch to real mode and jump to the BIOS reset code.
	46	*
	47	* The instruction that switches to real mode by writing to CR0 must be
	48	* followed immediately by a far jump instruction, which set CS to a
	49	* valid value for real mode, and flushes the prefetch queue to avoid
	50	* running instructions that have already been decoded in protected
	51	* mode.
	52	*
	53	* Clears all the flags except ET, especially PG (paging), PE
	54	* (protected-mode enable) and TS (task switch for coprocessor state
	55	* save). Flushes the TLB after paging has been disabled. Sets CD and
	56	* NW, to disable the cache on a 486, and invalidates the cache. This
	57	* is more like the state of a 486 after reset. I don't know if
	58	* something else should be done for other chips.
	59	*
	60	* More could be done here to set up the registers as if a CPU reset had
	61	* occurred; hopefully real BIOSs don't assume much. This is not the
	62	* actual BIOS entry point, anyway (that is at 0xfffffff0).
	63	*
	64	* Most of this work is probably excessive, but it is what is tested.
	65	*/
5a8c9aeb	66	.text
3d35ac34	67	.code16
5a8c9aeb	68
8e029fcd	69	.balign 16
5a8c9aeb	70	machine_real_restart_asm16:
3d35ac34 PA	71	1:
3d35ac34 PA	72	xorl %ecx, %ecx
5a8c9aeb JS	73	movl %cr0, %edx
	74	andl $0x00000011, %edx
	75	orl $0x60000000, %edx
	76	movl %edx, %cr0
3d35ac34 PA	77	movl %ecx, %cr3
3d35ac34 PA	78	movl %cr0, %edx
34d0b02e	79	testl $0x60000000, %edx /* If no cache bits -> no wbinvd */
3d35ac34 PA	80	jz 2f
	81	wbinvd
	82	2:
5a8c9aeb JS	83	andb $0x10, %dl
5a8c9aeb JS	84	movl %edx, %cr0
e5684ec4	85	LJMPW_RM(3f)
5a8c9aeb	86	3:
6feb592d	87	andw %ax, %ax
5a8c9aeb	88	jz bios
3d35ac34 PA	89
	90	apm:
	91	movw $0x1000, %ax
	92	movw %ax, %ss
	93	movw $0xf000, %sp
	94	movw $0x5307, %ax
	95	movw $0x0001, %bx
	96	movw $0x0003, %cx
	97	int $0x15
5a8c9aeb	98	/* This should never return... */
3d35ac34	99
5a8c9aeb JS	100	bios:
5a8c9aeb JS	101	ljmpw $0xf000, $0xfff0
3d35ac34	102
5a8c9aeb	103	.section ".rodata", "a"
3d35ac34	104
8e029fcd JS	105	.balign 16
8e029fcd JS	106	GLOBAL(machine_real_restart_idt)
3d35ac34 PA	107	.word 0xffff /* Length - real mode default value */
3d35ac34 PA	108	.long 0 /* Base - real mode default value */
8e029fcd	109	END(machine_real_restart_idt)
3d35ac34	110
8e029fcd JS	111	.balign 16
8e029fcd JS	112	GLOBAL(machine_real_restart_gdt)
5a8c9aeb JS	113	/* Self-pointer */
	114	.word 0xffff /* Length - real mode default value */
	115	.long pa_machine_real_restart_gdt
	116	.word 0
	117
	118	/*
	119	* 16-bit code segment pointing to real_mode_seg
	120	* Selector value 8
	121	*/
	122	.word 0xffff /* Limit */
	123	.long 0x9b000000 + pa_real_mode_base
	124	.word 0
	125
3d35ac34 PA	126	/*
	127	* 16-bit data segment with the selector value 16 = 0x10 and
	128	* base value 0x100; since this is consistent with real mode
	129	* semantics we don't have to reload the segments once CR0.PE = 0.
	130	*/
	131	.quad GDT_ENTRY(0x0093, 0x100, 0xffff)
8e029fcd	132	END(machine_real_restart_gdt)