Commit | Line | Data |
---|---|---|
5ead97c8 JF |
1 | /* |
2 | * Core of Xen paravirt_ops implementation. | |
3 | * | |
4 | * This file contains the xen_paravirt_ops structure itself, and the | |
5 | * implementations for: | |
6 | * - privileged instructions | |
7 | * - interrupt flags | |
8 | * - segment operations | |
9 | * - booting and setup | |
10 | * | |
11 | * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 | |
12 | */ | |
13 | ||
38e20b07 | 14 | #include <linux/cpu.h> |
5ead97c8 JF |
15 | #include <linux/kernel.h> |
16 | #include <linux/init.h> | |
17 | #include <linux/smp.h> | |
18 | #include <linux/preempt.h> | |
f120f13e | 19 | #include <linux/hardirq.h> |
5ead97c8 JF |
20 | #include <linux/percpu.h> |
21 | #include <linux/delay.h> | |
22 | #include <linux/start_kernel.h> | |
23 | #include <linux/sched.h> | |
6cac5a92 | 24 | #include <linux/kprobes.h> |
5ead97c8 JF |
25 | #include <linux/bootmem.h> |
26 | #include <linux/module.h> | |
f4f97b3e JF |
27 | #include <linux/mm.h> |
28 | #include <linux/page-flags.h> | |
29 | #include <linux/highmem.h> | |
b8c2d3df | 30 | #include <linux/console.h> |
5d990b62 | 31 | #include <linux/pci.h> |
5a0e3ad6 | 32 | #include <linux/gfp.h> |
236260b9 | 33 | #include <linux/memblock.h> |
96f28bc6 | 34 | #include <linux/edd.h> |
5ead97c8 | 35 | |
1ccbf534 | 36 | #include <xen/xen.h> |
0ec53ecf | 37 | #include <xen/events.h> |
5ead97c8 | 38 | #include <xen/interface/xen.h> |
ecbf29cd | 39 | #include <xen/interface/version.h> |
5ead97c8 JF |
40 | #include <xen/interface/physdev.h> |
41 | #include <xen/interface/vcpu.h> | |
bee6ab53 | 42 | #include <xen/interface/memory.h> |
cef12ee5 | 43 | #include <xen/interface/xen-mca.h> |
5ead97c8 JF |
44 | #include <xen/features.h> |
45 | #include <xen/page.h> | |
38e20b07 | 46 | #include <xen/hvm.h> |
084a2a4e | 47 | #include <xen/hvc-console.h> |
211063dc | 48 | #include <xen/acpi.h> |
5ead97c8 JF |
49 | |
50 | #include <asm/paravirt.h> | |
7b6aa335 | 51 | #include <asm/apic.h> |
5ead97c8 | 52 | #include <asm/page.h> |
b5401a96 | 53 | #include <asm/xen/pci.h> |
5ead97c8 JF |
54 | #include <asm/xen/hypercall.h> |
55 | #include <asm/xen/hypervisor.h> | |
56 | #include <asm/fixmap.h> | |
57 | #include <asm/processor.h> | |
707ebbc8 | 58 | #include <asm/proto.h> |
1153968a | 59 | #include <asm/msr-index.h> |
6cac5a92 | 60 | #include <asm/traps.h> |
5ead97c8 JF |
61 | #include <asm/setup.h> |
62 | #include <asm/desc.h> | |
817a824b | 63 | #include <asm/pgalloc.h> |
5ead97c8 | 64 | #include <asm/pgtable.h> |
f87e4cac | 65 | #include <asm/tlbflush.h> |
fefa629a | 66 | #include <asm/reboot.h> |
577eebea | 67 | #include <asm/stackprotector.h> |
bee6ab53 | 68 | #include <asm/hypervisor.h> |
73c154c6 | 69 | #include <asm/mwait.h> |
76a8df7b | 70 | #include <asm/pci_x86.h> |
c79c4982 | 71 | #include <asm/pat.h> |
73c154c6 KRW |
72 | |
73 | #ifdef CONFIG_ACPI | |
74 | #include <linux/acpi.h> | |
75 | #include <asm/acpi.h> | |
76 | #include <acpi/pdc_intel.h> | |
77 | #include <acpi/processor.h> | |
78 | #include <xen/interface/platform.h> | |
79 | #endif | |
5ead97c8 JF |
80 | |
81 | #include "xen-ops.h" | |
3b827c1b | 82 | #include "mmu.h" |
f447d56d | 83 | #include "smp.h" |
5ead97c8 JF |
84 | #include "multicalls.h" |
85 | ||
86 | EXPORT_SYMBOL_GPL(hypercall_page); | |
87 | ||
a520996a KRW |
88 | /* |
89 | * Pointer to the xen_vcpu_info structure or | |
90 | * &HYPERVISOR_shared_info->vcpu_info[cpu]. See xen_hvm_init_shared_info | |
91 | * and xen_vcpu_setup for details. By default it points to share_info->vcpu_info | |
92 | * but if the hypervisor supports VCPUOP_register_vcpu_info then it can point | |
93 | * to xen_vcpu_info. The pointer is used in __xen_evtchn_do_upcall to | |
94 | * acknowledge pending events. | |
95 | * Also more subtly it is used by the patched version of irq enable/disable | |
96 | * e.g. xen_irq_enable_direct and xen_iret in PV mode. | |
97 | * | |
98 | * The desire to be able to do those mask/unmask operations as a single | |
99 | * instruction by using the per-cpu offset held in %gs is the real reason | |
100 | * vcpu info is in a per-cpu pointer and the original reason for this | |
101 | * hypercall. | |
102 | * | |
103 | */ | |
5ead97c8 | 104 | DEFINE_PER_CPU(struct vcpu_info *, xen_vcpu); |
a520996a KRW |
105 | |
106 | /* | |
107 | * Per CPU pages used if hypervisor supports VCPUOP_register_vcpu_info | |
108 | * hypercall. This can be used both in PV and PVHVM mode. The structure | |
109 | * overrides the default per_cpu(xen_vcpu, cpu) value. | |
110 | */ | |
5ead97c8 | 111 | DEFINE_PER_CPU(struct vcpu_info, xen_vcpu_info); |
9f79991d | 112 | |
6e833587 JF |
113 | enum xen_domain_type xen_domain_type = XEN_NATIVE; |
114 | EXPORT_SYMBOL_GPL(xen_domain_type); | |
115 | ||
7e77506a IC |
116 | unsigned long *machine_to_phys_mapping = (void *)MACH2PHYS_VIRT_START; |
117 | EXPORT_SYMBOL(machine_to_phys_mapping); | |
ccbcdf7c JB |
118 | unsigned long machine_to_phys_nr; |
119 | EXPORT_SYMBOL(machine_to_phys_nr); | |
7e77506a | 120 | |
5ead97c8 JF |
121 | struct start_info *xen_start_info; |
122 | EXPORT_SYMBOL_GPL(xen_start_info); | |
123 | ||
a0d695c8 | 124 | struct shared_info xen_dummy_shared_info; |
60223a32 | 125 | |
38341432 JF |
126 | void *xen_initial_gdt; |
127 | ||
bee6ab53 | 128 | RESERVE_BRK(shared_info_page_brk, PAGE_SIZE); |
38e20b07 SY |
129 | __read_mostly int xen_have_vector_callback; |
130 | EXPORT_SYMBOL_GPL(xen_have_vector_callback); | |
bee6ab53 | 131 | |
60223a32 JF |
132 | /* |
133 | * Point at some empty memory to start with. We map the real shared_info | |
134 | * page as soon as fixmap is up and running. | |
135 | */ | |
4648da7c | 136 | struct shared_info *HYPERVISOR_shared_info = &xen_dummy_shared_info; |
60223a32 JF |
137 | |
138 | /* | |
139 | * Flag to determine whether vcpu info placement is available on all | |
140 | * VCPUs. We assume it is to start with, and then set it to zero on | |
141 | * the first failure. This is because it can succeed on some VCPUs | |
142 | * and not others, since it can involve hypervisor memory allocation, | |
143 | * or because the guest failed to guarantee all the appropriate | |
144 | * constraints on all VCPUs (ie buffer can't cross a page boundary). | |
145 | * | |
146 | * Note that any particular CPU may be using a placed vcpu structure, | |
147 | * but we can only optimise if the all are. | |
148 | * | |
149 | * 0: not available, 1: available | |
150 | */ | |
e4d04071 | 151 | static int have_vcpu_info_placement = 1; |
60223a32 | 152 | |
1c32cdc6 DV |
153 | struct tls_descs { |
154 | struct desc_struct desc[3]; | |
155 | }; | |
156 | ||
157 | /* | |
158 | * Updating the 3 TLS descriptors in the GDT on every task switch is | |
159 | * surprisingly expensive so we avoid updating them if they haven't | |
160 | * changed. Since Xen writes different descriptors than the one | |
161 | * passed in the update_descriptor hypercall we keep shadow copies to | |
162 | * compare against. | |
163 | */ | |
164 | static DEFINE_PER_CPU(struct tls_descs, shadow_tls_desc); | |
165 | ||
c06ee78d MR |
166 | static void clamp_max_cpus(void) |
167 | { | |
168 | #ifdef CONFIG_SMP | |
169 | if (setup_max_cpus > MAX_VIRT_CPUS) | |
170 | setup_max_cpus = MAX_VIRT_CPUS; | |
171 | #endif | |
172 | } | |
173 | ||
9c7a7942 | 174 | static void xen_vcpu_setup(int cpu) |
5ead97c8 | 175 | { |
60223a32 JF |
176 | struct vcpu_register_vcpu_info info; |
177 | int err; | |
178 | struct vcpu_info *vcpup; | |
179 | ||
a0d695c8 | 180 | BUG_ON(HYPERVISOR_shared_info == &xen_dummy_shared_info); |
60223a32 | 181 | |
7f1fc268 KRW |
182 | /* |
183 | * This path is called twice on PVHVM - first during bootup via | |
184 | * smp_init -> xen_hvm_cpu_notify, and then if the VCPU is being | |
185 | * hotplugged: cpu_up -> xen_hvm_cpu_notify. | |
186 | * As we can only do the VCPUOP_register_vcpu_info once lets | |
187 | * not over-write its result. | |
188 | * | |
189 | * For PV it is called during restore (xen_vcpu_restore) and bootup | |
190 | * (xen_setup_vcpu_info_placement). The hotplug mechanism does not | |
191 | * use this function. | |
192 | */ | |
193 | if (xen_hvm_domain()) { | |
194 | if (per_cpu(xen_vcpu, cpu) == &per_cpu(xen_vcpu_info, cpu)) | |
195 | return; | |
196 | } | |
c06ee78d MR |
197 | if (cpu < MAX_VIRT_CPUS) |
198 | per_cpu(xen_vcpu,cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu]; | |
60223a32 | 199 | |
c06ee78d MR |
200 | if (!have_vcpu_info_placement) { |
201 | if (cpu >= MAX_VIRT_CPUS) | |
202 | clamp_max_cpus(); | |
203 | return; | |
204 | } | |
60223a32 | 205 | |
c06ee78d | 206 | vcpup = &per_cpu(xen_vcpu_info, cpu); |
9976b39b | 207 | info.mfn = arbitrary_virt_to_mfn(vcpup); |
60223a32 JF |
208 | info.offset = offset_in_page(vcpup); |
209 | ||
60223a32 JF |
210 | /* Check to see if the hypervisor will put the vcpu_info |
211 | structure where we want it, which allows direct access via | |
a520996a KRW |
212 | a percpu-variable. |
213 | N.B. This hypercall can _only_ be called once per CPU. Subsequent | |
214 | calls will error out with -EINVAL. This is due to the fact that | |
215 | hypervisor has no unregister variant and this hypercall does not | |
216 | allow to over-write info.mfn and info.offset. | |
217 | */ | |
60223a32 JF |
218 | err = HYPERVISOR_vcpu_op(VCPUOP_register_vcpu_info, cpu, &info); |
219 | ||
220 | if (err) { | |
221 | printk(KERN_DEBUG "register_vcpu_info failed: err=%d\n", err); | |
222 | have_vcpu_info_placement = 0; | |
c06ee78d | 223 | clamp_max_cpus(); |
60223a32 JF |
224 | } else { |
225 | /* This cpu is using the registered vcpu info, even if | |
226 | later ones fail to. */ | |
227 | per_cpu(xen_vcpu, cpu) = vcpup; | |
60223a32 | 228 | } |
5ead97c8 JF |
229 | } |
230 | ||
9c7a7942 JF |
231 | /* |
232 | * On restore, set the vcpu placement up again. | |
233 | * If it fails, then we're in a bad state, since | |
234 | * we can't back out from using it... | |
235 | */ | |
236 | void xen_vcpu_restore(void) | |
237 | { | |
3905bb2a | 238 | int cpu; |
9c7a7942 | 239 | |
9d328a94 | 240 | for_each_possible_cpu(cpu) { |
3905bb2a | 241 | bool other_cpu = (cpu != smp_processor_id()); |
9d328a94 | 242 | bool is_up = HYPERVISOR_vcpu_op(VCPUOP_is_up, cpu, NULL); |
9c7a7942 | 243 | |
9d328a94 | 244 | if (other_cpu && is_up && |
3905bb2a JF |
245 | HYPERVISOR_vcpu_op(VCPUOP_down, cpu, NULL)) |
246 | BUG(); | |
9c7a7942 | 247 | |
3905bb2a | 248 | xen_setup_runstate_info(cpu); |
9c7a7942 | 249 | |
3905bb2a | 250 | if (have_vcpu_info_placement) |
9c7a7942 | 251 | xen_vcpu_setup(cpu); |
9c7a7942 | 252 | |
9d328a94 | 253 | if (other_cpu && is_up && |
3905bb2a JF |
254 | HYPERVISOR_vcpu_op(VCPUOP_up, cpu, NULL)) |
255 | BUG(); | |
9c7a7942 JF |
256 | } |
257 | } | |
258 | ||
5ead97c8 JF |
259 | static void __init xen_banner(void) |
260 | { | |
95c7c23b JF |
261 | unsigned version = HYPERVISOR_xen_version(XENVER_version, NULL); |
262 | struct xen_extraversion extra; | |
263 | HYPERVISOR_xen_version(XENVER_extraversion, &extra); | |
264 | ||
d285d683 MR |
265 | pr_info("Booting paravirtualized kernel %son %s\n", |
266 | xen_feature(XENFEAT_auto_translated_physmap) ? | |
267 | "with PVH extensions " : "", pv_info.name); | |
95c7c23b JF |
268 | printk(KERN_INFO "Xen version: %d.%d%s%s\n", |
269 | version >> 16, version & 0xffff, extra.extraversion, | |
e57778a1 | 270 | xen_feature(XENFEAT_mmu_pt_update_preserve_ad) ? " (preserve-AD)" : ""); |
5ead97c8 | 271 | } |
394b40f6 KRW |
272 | /* Check if running on Xen version (major, minor) or later */ |
273 | bool | |
274 | xen_running_on_version_or_later(unsigned int major, unsigned int minor) | |
275 | { | |
276 | unsigned int version; | |
277 | ||
278 | if (!xen_domain()) | |
279 | return false; | |
280 | ||
281 | version = HYPERVISOR_xen_version(XENVER_version, NULL); | |
282 | if ((((version >> 16) == major) && ((version & 0xffff) >= minor)) || | |
283 | ((version >> 16) > major)) | |
284 | return true; | |
285 | return false; | |
286 | } | |
5ead97c8 | 287 | |
5e626254 AP |
288 | #define CPUID_THERM_POWER_LEAF 6 |
289 | #define APERFMPERF_PRESENT 0 | |
290 | ||
e826fe1b JF |
291 | static __read_mostly unsigned int cpuid_leaf1_edx_mask = ~0; |
292 | static __read_mostly unsigned int cpuid_leaf1_ecx_mask = ~0; | |
293 | ||
73c154c6 KRW |
294 | static __read_mostly unsigned int cpuid_leaf1_ecx_set_mask; |
295 | static __read_mostly unsigned int cpuid_leaf5_ecx_val; | |
296 | static __read_mostly unsigned int cpuid_leaf5_edx_val; | |
297 | ||
65ea5b03 PA |
298 | static void xen_cpuid(unsigned int *ax, unsigned int *bx, |
299 | unsigned int *cx, unsigned int *dx) | |
5ead97c8 | 300 | { |
82d64699 | 301 | unsigned maskebx = ~0; |
e826fe1b | 302 | unsigned maskecx = ~0; |
5ead97c8 | 303 | unsigned maskedx = ~0; |
73c154c6 | 304 | unsigned setecx = 0; |
5ead97c8 JF |
305 | /* |
306 | * Mask out inconvenient features, to try and disable as many | |
307 | * unsupported kernel subsystems as possible. | |
308 | */ | |
82d64699 JF |
309 | switch (*ax) { |
310 | case 1: | |
e826fe1b | 311 | maskecx = cpuid_leaf1_ecx_mask; |
73c154c6 | 312 | setecx = cpuid_leaf1_ecx_set_mask; |
e826fe1b | 313 | maskedx = cpuid_leaf1_edx_mask; |
82d64699 JF |
314 | break; |
315 | ||
73c154c6 KRW |
316 | case CPUID_MWAIT_LEAF: |
317 | /* Synthesize the values.. */ | |
318 | *ax = 0; | |
319 | *bx = 0; | |
320 | *cx = cpuid_leaf5_ecx_val; | |
321 | *dx = cpuid_leaf5_edx_val; | |
322 | return; | |
323 | ||
5e626254 AP |
324 | case CPUID_THERM_POWER_LEAF: |
325 | /* Disabling APERFMPERF for kernel usage */ | |
326 | maskecx = ~(1 << APERFMPERF_PRESENT); | |
327 | break; | |
328 | ||
82d64699 JF |
329 | case 0xb: |
330 | /* Suppress extended topology stuff */ | |
331 | maskebx = 0; | |
332 | break; | |
e826fe1b | 333 | } |
5ead97c8 JF |
334 | |
335 | asm(XEN_EMULATE_PREFIX "cpuid" | |
65ea5b03 PA |
336 | : "=a" (*ax), |
337 | "=b" (*bx), | |
338 | "=c" (*cx), | |
339 | "=d" (*dx) | |
340 | : "0" (*ax), "2" (*cx)); | |
e826fe1b | 341 | |
82d64699 | 342 | *bx &= maskebx; |
e826fe1b | 343 | *cx &= maskecx; |
73c154c6 | 344 | *cx |= setecx; |
65ea5b03 | 345 | *dx &= maskedx; |
73c154c6 | 346 | |
5ead97c8 JF |
347 | } |
348 | ||
73c154c6 KRW |
349 | static bool __init xen_check_mwait(void) |
350 | { | |
e3aa4e61 | 351 | #ifdef CONFIG_ACPI |
73c154c6 KRW |
352 | struct xen_platform_op op = { |
353 | .cmd = XENPF_set_processor_pminfo, | |
354 | .u.set_pminfo.id = -1, | |
355 | .u.set_pminfo.type = XEN_PM_PDC, | |
356 | }; | |
357 | uint32_t buf[3]; | |
358 | unsigned int ax, bx, cx, dx; | |
359 | unsigned int mwait_mask; | |
360 | ||
361 | /* We need to determine whether it is OK to expose the MWAIT | |
362 | * capability to the kernel to harvest deeper than C3 states from ACPI | |
363 | * _CST using the processor_harvest_xen.c module. For this to work, we | |
364 | * need to gather the MWAIT_LEAF values (which the cstate.c code | |
365 | * checks against). The hypervisor won't expose the MWAIT flag because | |
366 | * it would break backwards compatibility; so we will find out directly | |
367 | * from the hardware and hypercall. | |
368 | */ | |
369 | if (!xen_initial_domain()) | |
370 | return false; | |
371 | ||
e3aa4e61 LJ |
372 | /* |
373 | * When running under platform earlier than Xen4.2, do not expose | |
374 | * mwait, to avoid the risk of loading native acpi pad driver | |
375 | */ | |
376 | if (!xen_running_on_version_or_later(4, 2)) | |
377 | return false; | |
378 | ||
73c154c6 KRW |
379 | ax = 1; |
380 | cx = 0; | |
381 | ||
382 | native_cpuid(&ax, &bx, &cx, &dx); | |
383 | ||
384 | mwait_mask = (1 << (X86_FEATURE_EST % 32)) | | |
385 | (1 << (X86_FEATURE_MWAIT % 32)); | |
386 | ||
387 | if ((cx & mwait_mask) != mwait_mask) | |
388 | return false; | |
389 | ||
390 | /* We need to emulate the MWAIT_LEAF and for that we need both | |
391 | * ecx and edx. The hypercall provides only partial information. | |
392 | */ | |
393 | ||
394 | ax = CPUID_MWAIT_LEAF; | |
395 | bx = 0; | |
396 | cx = 0; | |
397 | dx = 0; | |
398 | ||
399 | native_cpuid(&ax, &bx, &cx, &dx); | |
400 | ||
401 | /* Ask the Hypervisor whether to clear ACPI_PDC_C_C2C3_FFH. If so, | |
402 | * don't expose MWAIT_LEAF and let ACPI pick the IOPORT version of C3. | |
403 | */ | |
404 | buf[0] = ACPI_PDC_REVISION_ID; | |
405 | buf[1] = 1; | |
406 | buf[2] = (ACPI_PDC_C_CAPABILITY_SMP | ACPI_PDC_EST_CAPABILITY_SWSMP); | |
407 | ||
408 | set_xen_guest_handle(op.u.set_pminfo.pdc, buf); | |
409 | ||
410 | if ((HYPERVISOR_dom0_op(&op) == 0) && | |
411 | (buf[2] & (ACPI_PDC_C_C1_FFH | ACPI_PDC_C_C2C3_FFH))) { | |
412 | cpuid_leaf5_ecx_val = cx; | |
413 | cpuid_leaf5_edx_val = dx; | |
414 | } | |
415 | return true; | |
416 | #else | |
417 | return false; | |
418 | #endif | |
419 | } | |
ad3062a0 | 420 | static void __init xen_init_cpuid_mask(void) |
e826fe1b JF |
421 | { |
422 | unsigned int ax, bx, cx, dx; | |
947ccf9c | 423 | unsigned int xsave_mask; |
e826fe1b JF |
424 | |
425 | cpuid_leaf1_edx_mask = | |
cef12ee5 | 426 | ~((1 << X86_FEATURE_MTRR) | /* disable MTRR */ |
e826fe1b JF |
427 | (1 << X86_FEATURE_ACC)); /* thermal monitoring */ |
428 | ||
429 | if (!xen_initial_domain()) | |
430 | cpuid_leaf1_edx_mask &= | |
6efa20e4 | 431 | ~((1 << X86_FEATURE_ACPI)); /* disable ACPI */ |
4ea9b9ac ZD |
432 | |
433 | cpuid_leaf1_ecx_mask &= ~(1 << (X86_FEATURE_X2APIC % 32)); | |
434 | ||
947ccf9c | 435 | ax = 1; |
5e287830 | 436 | cx = 0; |
d285d683 | 437 | cpuid(1, &ax, &bx, &cx, &dx); |
e826fe1b | 438 | |
947ccf9c SH |
439 | xsave_mask = |
440 | (1 << (X86_FEATURE_XSAVE % 32)) | | |
441 | (1 << (X86_FEATURE_OSXSAVE % 32)); | |
442 | ||
443 | /* Xen will set CR4.OSXSAVE if supported and not disabled by force */ | |
444 | if ((cx & xsave_mask) != xsave_mask) | |
445 | cpuid_leaf1_ecx_mask &= ~xsave_mask; /* disable XSAVE & OSXSAVE */ | |
73c154c6 KRW |
446 | if (xen_check_mwait()) |
447 | cpuid_leaf1_ecx_set_mask = (1 << (X86_FEATURE_MWAIT % 32)); | |
e826fe1b JF |
448 | } |
449 | ||
5ead97c8 JF |
450 | static void xen_set_debugreg(int reg, unsigned long val) |
451 | { | |
452 | HYPERVISOR_set_debugreg(reg, val); | |
453 | } | |
454 | ||
455 | static unsigned long xen_get_debugreg(int reg) | |
456 | { | |
457 | return HYPERVISOR_get_debugreg(reg); | |
458 | } | |
459 | ||
224101ed | 460 | static void xen_end_context_switch(struct task_struct *next) |
5ead97c8 | 461 | { |
5ead97c8 | 462 | xen_mc_flush(); |
224101ed | 463 | paravirt_end_context_switch(next); |
5ead97c8 JF |
464 | } |
465 | ||
466 | static unsigned long xen_store_tr(void) | |
467 | { | |
468 | return 0; | |
469 | } | |
470 | ||
a05d2eba | 471 | /* |
cef43bf6 JF |
472 | * Set the page permissions for a particular virtual address. If the |
473 | * address is a vmalloc mapping (or other non-linear mapping), then | |
474 | * find the linear mapping of the page and also set its protections to | |
475 | * match. | |
a05d2eba JF |
476 | */ |
477 | static void set_aliased_prot(void *v, pgprot_t prot) | |
478 | { | |
479 | int level; | |
480 | pte_t *ptep; | |
481 | pte_t pte; | |
482 | unsigned long pfn; | |
483 | struct page *page; | |
484 | ||
485 | ptep = lookup_address((unsigned long)v, &level); | |
486 | BUG_ON(ptep == NULL); | |
487 | ||
488 | pfn = pte_pfn(*ptep); | |
489 | page = pfn_to_page(pfn); | |
490 | ||
491 | pte = pfn_pte(pfn, prot); | |
492 | ||
493 | if (HYPERVISOR_update_va_mapping((unsigned long)v, pte, 0)) | |
494 | BUG(); | |
495 | ||
496 | if (!PageHighMem(page)) { | |
497 | void *av = __va(PFN_PHYS(pfn)); | |
498 | ||
499 | if (av != v) | |
500 | if (HYPERVISOR_update_va_mapping((unsigned long)av, pte, 0)) | |
501 | BUG(); | |
502 | } else | |
503 | kmap_flush_unused(); | |
504 | } | |
505 | ||
38ffbe66 JF |
506 | static void xen_alloc_ldt(struct desc_struct *ldt, unsigned entries) |
507 | { | |
a05d2eba | 508 | const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE; |
38ffbe66 JF |
509 | int i; |
510 | ||
a05d2eba JF |
511 | for(i = 0; i < entries; i += entries_per_page) |
512 | set_aliased_prot(ldt + i, PAGE_KERNEL_RO); | |
38ffbe66 JF |
513 | } |
514 | ||
515 | static void xen_free_ldt(struct desc_struct *ldt, unsigned entries) | |
516 | { | |
a05d2eba | 517 | const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE; |
38ffbe66 JF |
518 | int i; |
519 | ||
a05d2eba JF |
520 | for(i = 0; i < entries; i += entries_per_page) |
521 | set_aliased_prot(ldt + i, PAGE_KERNEL); | |
38ffbe66 JF |
522 | } |
523 | ||
5ead97c8 JF |
524 | static void xen_set_ldt(const void *addr, unsigned entries) |
525 | { | |
5ead97c8 JF |
526 | struct mmuext_op *op; |
527 | struct multicall_space mcs = xen_mc_entry(sizeof(*op)); | |
528 | ||
ab78f7ad JF |
529 | trace_xen_cpu_set_ldt(addr, entries); |
530 | ||
5ead97c8 JF |
531 | op = mcs.args; |
532 | op->cmd = MMUEXT_SET_LDT; | |
4dbf7af6 | 533 | op->arg1.linear_addr = (unsigned long)addr; |
5ead97c8 JF |
534 | op->arg2.nr_ents = entries; |
535 | ||
536 | MULTI_mmuext_op(mcs.mc, op, 1, NULL, DOMID_SELF); | |
537 | ||
538 | xen_mc_issue(PARAVIRT_LAZY_CPU); | |
539 | } | |
540 | ||
6b68f01b | 541 | static void xen_load_gdt(const struct desc_ptr *dtr) |
5ead97c8 | 542 | { |
5ead97c8 JF |
543 | unsigned long va = dtr->address; |
544 | unsigned int size = dtr->size + 1; | |
545 | unsigned pages = (size + PAGE_SIZE - 1) / PAGE_SIZE; | |
3ce5fa7e | 546 | unsigned long frames[pages]; |
5ead97c8 | 547 | int f; |
5ead97c8 | 548 | |
577eebea JF |
549 | /* |
550 | * A GDT can be up to 64k in size, which corresponds to 8192 | |
551 | * 8-byte entries, or 16 4k pages.. | |
552 | */ | |
5ead97c8 JF |
553 | |
554 | BUG_ON(size > 65536); | |
555 | BUG_ON(va & ~PAGE_MASK); | |
556 | ||
5ead97c8 | 557 | for (f = 0; va < dtr->address + size; va += PAGE_SIZE, f++) { |
6ed6bf42 | 558 | int level; |
577eebea | 559 | pte_t *ptep; |
6ed6bf42 JF |
560 | unsigned long pfn, mfn; |
561 | void *virt; | |
562 | ||
577eebea JF |
563 | /* |
564 | * The GDT is per-cpu and is in the percpu data area. | |
565 | * That can be virtually mapped, so we need to do a | |
566 | * page-walk to get the underlying MFN for the | |
567 | * hypercall. The page can also be in the kernel's | |
568 | * linear range, so we need to RO that mapping too. | |
569 | */ | |
570 | ptep = lookup_address(va, &level); | |
6ed6bf42 JF |
571 | BUG_ON(ptep == NULL); |
572 | ||
573 | pfn = pte_pfn(*ptep); | |
574 | mfn = pfn_to_mfn(pfn); | |
575 | virt = __va(PFN_PHYS(pfn)); | |
576 | ||
577 | frames[f] = mfn; | |
9976b39b | 578 | |
5ead97c8 | 579 | make_lowmem_page_readonly((void *)va); |
6ed6bf42 | 580 | make_lowmem_page_readonly(virt); |
5ead97c8 JF |
581 | } |
582 | ||
3ce5fa7e JF |
583 | if (HYPERVISOR_set_gdt(frames, size / sizeof(struct desc_struct))) |
584 | BUG(); | |
5ead97c8 JF |
585 | } |
586 | ||
577eebea JF |
587 | /* |
588 | * load_gdt for early boot, when the gdt is only mapped once | |
589 | */ | |
ad3062a0 | 590 | static void __init xen_load_gdt_boot(const struct desc_ptr *dtr) |
577eebea JF |
591 | { |
592 | unsigned long va = dtr->address; | |
593 | unsigned int size = dtr->size + 1; | |
594 | unsigned pages = (size + PAGE_SIZE - 1) / PAGE_SIZE; | |
595 | unsigned long frames[pages]; | |
596 | int f; | |
597 | ||
598 | /* | |
599 | * A GDT can be up to 64k in size, which corresponds to 8192 | |
600 | * 8-byte entries, or 16 4k pages.. | |
601 | */ | |
602 | ||
603 | BUG_ON(size > 65536); | |
604 | BUG_ON(va & ~PAGE_MASK); | |
605 | ||
606 | for (f = 0; va < dtr->address + size; va += PAGE_SIZE, f++) { | |
607 | pte_t pte; | |
608 | unsigned long pfn, mfn; | |
609 | ||
610 | pfn = virt_to_pfn(va); | |
611 | mfn = pfn_to_mfn(pfn); | |
612 | ||
613 | pte = pfn_pte(pfn, PAGE_KERNEL_RO); | |
614 | ||
615 | if (HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0)) | |
616 | BUG(); | |
617 | ||
618 | frames[f] = mfn; | |
619 | } | |
620 | ||
621 | if (HYPERVISOR_set_gdt(frames, size / sizeof(struct desc_struct))) | |
622 | BUG(); | |
623 | } | |
624 | ||
59290362 DV |
625 | static inline bool desc_equal(const struct desc_struct *d1, |
626 | const struct desc_struct *d2) | |
627 | { | |
628 | return d1->a == d2->a && d1->b == d2->b; | |
629 | } | |
630 | ||
5ead97c8 JF |
631 | static void load_TLS_descriptor(struct thread_struct *t, |
632 | unsigned int cpu, unsigned int i) | |
633 | { | |
1c32cdc6 DV |
634 | struct desc_struct *shadow = &per_cpu(shadow_tls_desc, cpu).desc[i]; |
635 | struct desc_struct *gdt; | |
636 | xmaddr_t maddr; | |
637 | struct multicall_space mc; | |
638 | ||
639 | if (desc_equal(shadow, &t->tls_array[i])) | |
640 | return; | |
641 | ||
642 | *shadow = t->tls_array[i]; | |
643 | ||
644 | gdt = get_cpu_gdt_table(cpu); | |
645 | maddr = arbitrary_virt_to_machine(&gdt[GDT_ENTRY_TLS_MIN+i]); | |
646 | mc = __xen_mc_entry(0); | |
5ead97c8 JF |
647 | |
648 | MULTI_update_descriptor(mc.mc, maddr.maddr, t->tls_array[i]); | |
649 | } | |
650 | ||
651 | static void xen_load_tls(struct thread_struct *t, unsigned int cpu) | |
652 | { | |
8b84ad94 | 653 | /* |
ccbeed3a TH |
654 | * XXX sleazy hack: If we're being called in a lazy-cpu zone |
655 | * and lazy gs handling is enabled, it means we're in a | |
656 | * context switch, and %gs has just been saved. This means we | |
657 | * can zero it out to prevent faults on exit from the | |
658 | * hypervisor if the next process has no %gs. Either way, it | |
659 | * has been saved, and the new value will get loaded properly. | |
660 | * This will go away as soon as Xen has been modified to not | |
661 | * save/restore %gs for normal hypercalls. | |
8a95408e EH |
662 | * |
663 | * On x86_64, this hack is not used for %gs, because gs points | |
664 | * to KERNEL_GS_BASE (and uses it for PDA references), so we | |
665 | * must not zero %gs on x86_64 | |
666 | * | |
667 | * For x86_64, we need to zero %fs, otherwise we may get an | |
668 | * exception between the new %fs descriptor being loaded and | |
669 | * %fs being effectively cleared at __switch_to(). | |
8b84ad94 | 670 | */ |
8a95408e EH |
671 | if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU) { |
672 | #ifdef CONFIG_X86_32 | |
ccbeed3a | 673 | lazy_load_gs(0); |
8a95408e EH |
674 | #else |
675 | loadsegment(fs, 0); | |
676 | #endif | |
677 | } | |
678 | ||
679 | xen_mc_batch(); | |
680 | ||
681 | load_TLS_descriptor(t, cpu, 0); | |
682 | load_TLS_descriptor(t, cpu, 1); | |
683 | load_TLS_descriptor(t, cpu, 2); | |
684 | ||
685 | xen_mc_issue(PARAVIRT_LAZY_CPU); | |
5ead97c8 JF |
686 | } |
687 | ||
a8fc1089 EH |
688 | #ifdef CONFIG_X86_64 |
689 | static void xen_load_gs_index(unsigned int idx) | |
690 | { | |
691 | if (HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, idx)) | |
692 | BUG(); | |
5ead97c8 | 693 | } |
a8fc1089 | 694 | #endif |
5ead97c8 JF |
695 | |
696 | static void xen_write_ldt_entry(struct desc_struct *dt, int entrynum, | |
75b8bb3e | 697 | const void *ptr) |
5ead97c8 | 698 | { |
cef43bf6 | 699 | xmaddr_t mach_lp = arbitrary_virt_to_machine(&dt[entrynum]); |
75b8bb3e | 700 | u64 entry = *(u64 *)ptr; |
5ead97c8 | 701 | |
ab78f7ad JF |
702 | trace_xen_cpu_write_ldt_entry(dt, entrynum, entry); |
703 | ||
f120f13e JF |
704 | preempt_disable(); |
705 | ||
5ead97c8 JF |
706 | xen_mc_flush(); |
707 | if (HYPERVISOR_update_descriptor(mach_lp.maddr, entry)) | |
708 | BUG(); | |
f120f13e JF |
709 | |
710 | preempt_enable(); | |
5ead97c8 JF |
711 | } |
712 | ||
e176d367 | 713 | static int cvt_gate_to_trap(int vector, const gate_desc *val, |
5ead97c8 JF |
714 | struct trap_info *info) |
715 | { | |
6cac5a92 JF |
716 | unsigned long addr; |
717 | ||
6d02c426 | 718 | if (val->type != GATE_TRAP && val->type != GATE_INTERRUPT) |
5ead97c8 JF |
719 | return 0; |
720 | ||
721 | info->vector = vector; | |
6cac5a92 JF |
722 | |
723 | addr = gate_offset(*val); | |
724 | #ifdef CONFIG_X86_64 | |
b80119bb JF |
725 | /* |
726 | * Look for known traps using IST, and substitute them | |
727 | * appropriately. The debugger ones are the only ones we care | |
05e36006 LJ |
728 | * about. Xen will handle faults like double_fault, |
729 | * so we should never see them. Warn if | |
b80119bb JF |
730 | * there's an unexpected IST-using fault handler. |
731 | */ | |
6cac5a92 JF |
732 | if (addr == (unsigned long)debug) |
733 | addr = (unsigned long)xen_debug; | |
734 | else if (addr == (unsigned long)int3) | |
735 | addr = (unsigned long)xen_int3; | |
736 | else if (addr == (unsigned long)stack_segment) | |
737 | addr = (unsigned long)xen_stack_segment; | |
6efa20e4 | 738 | else if (addr == (unsigned long)double_fault) { |
b80119bb JF |
739 | /* Don't need to handle these */ |
740 | return 0; | |
741 | #ifdef CONFIG_X86_MCE | |
742 | } else if (addr == (unsigned long)machine_check) { | |
05e36006 LJ |
743 | /* |
744 | * when xen hypervisor inject vMCE to guest, | |
745 | * use native mce handler to handle it | |
746 | */ | |
747 | ; | |
b80119bb | 748 | #endif |
6efa20e4 KRW |
749 | } else if (addr == (unsigned long)nmi) |
750 | /* | |
751 | * Use the native version as well. | |
752 | */ | |
753 | ; | |
754 | else { | |
b80119bb JF |
755 | /* Some other trap using IST? */ |
756 | if (WARN_ON(val->ist != 0)) | |
757 | return 0; | |
758 | } | |
6cac5a92 JF |
759 | #endif /* CONFIG_X86_64 */ |
760 | info->address = addr; | |
761 | ||
e176d367 EH |
762 | info->cs = gate_segment(*val); |
763 | info->flags = val->dpl; | |
5ead97c8 | 764 | /* interrupt gates clear IF */ |
6d02c426 JF |
765 | if (val->type == GATE_INTERRUPT) |
766 | info->flags |= 1 << 2; | |
5ead97c8 JF |
767 | |
768 | return 1; | |
769 | } | |
770 | ||
771 | /* Locations of each CPU's IDT */ | |
6b68f01b | 772 | static DEFINE_PER_CPU(struct desc_ptr, idt_desc); |
5ead97c8 JF |
773 | |
774 | /* Set an IDT entry. If the entry is part of the current IDT, then | |
775 | also update Xen. */ | |
8d947344 | 776 | static void xen_write_idt_entry(gate_desc *dt, int entrynum, const gate_desc *g) |
5ead97c8 | 777 | { |
5ead97c8 | 778 | unsigned long p = (unsigned long)&dt[entrynum]; |
f120f13e JF |
779 | unsigned long start, end; |
780 | ||
ab78f7ad JF |
781 | trace_xen_cpu_write_idt_entry(dt, entrynum, g); |
782 | ||
f120f13e JF |
783 | preempt_disable(); |
784 | ||
780f36d8 CL |
785 | start = __this_cpu_read(idt_desc.address); |
786 | end = start + __this_cpu_read(idt_desc.size) + 1; | |
5ead97c8 JF |
787 | |
788 | xen_mc_flush(); | |
789 | ||
8d947344 | 790 | native_write_idt_entry(dt, entrynum, g); |
5ead97c8 JF |
791 | |
792 | if (p >= start && (p + 8) <= end) { | |
793 | struct trap_info info[2]; | |
794 | ||
795 | info[1].address = 0; | |
796 | ||
e176d367 | 797 | if (cvt_gate_to_trap(entrynum, g, &info[0])) |
5ead97c8 JF |
798 | if (HYPERVISOR_set_trap_table(info)) |
799 | BUG(); | |
800 | } | |
f120f13e JF |
801 | |
802 | preempt_enable(); | |
5ead97c8 JF |
803 | } |
804 | ||
6b68f01b | 805 | static void xen_convert_trap_info(const struct desc_ptr *desc, |
f87e4cac | 806 | struct trap_info *traps) |
5ead97c8 | 807 | { |
5ead97c8 JF |
808 | unsigned in, out, count; |
809 | ||
e176d367 | 810 | count = (desc->size+1) / sizeof(gate_desc); |
5ead97c8 JF |
811 | BUG_ON(count > 256); |
812 | ||
5ead97c8 | 813 | for (in = out = 0; in < count; in++) { |
e176d367 | 814 | gate_desc *entry = (gate_desc*)(desc->address) + in; |
5ead97c8 | 815 | |
e176d367 | 816 | if (cvt_gate_to_trap(in, entry, &traps[out])) |
5ead97c8 JF |
817 | out++; |
818 | } | |
819 | traps[out].address = 0; | |
f87e4cac JF |
820 | } |
821 | ||
822 | void xen_copy_trap_info(struct trap_info *traps) | |
823 | { | |
6b68f01b | 824 | const struct desc_ptr *desc = &__get_cpu_var(idt_desc); |
f87e4cac JF |
825 | |
826 | xen_convert_trap_info(desc, traps); | |
f87e4cac JF |
827 | } |
828 | ||
829 | /* Load a new IDT into Xen. In principle this can be per-CPU, so we | |
830 | hold a spinlock to protect the static traps[] array (static because | |
831 | it avoids allocation, and saves stack space). */ | |
6b68f01b | 832 | static void xen_load_idt(const struct desc_ptr *desc) |
f87e4cac JF |
833 | { |
834 | static DEFINE_SPINLOCK(lock); | |
835 | static struct trap_info traps[257]; | |
f87e4cac | 836 | |
ab78f7ad JF |
837 | trace_xen_cpu_load_idt(desc); |
838 | ||
f87e4cac JF |
839 | spin_lock(&lock); |
840 | ||
f120f13e JF |
841 | __get_cpu_var(idt_desc) = *desc; |
842 | ||
f87e4cac | 843 | xen_convert_trap_info(desc, traps); |
5ead97c8 JF |
844 | |
845 | xen_mc_flush(); | |
846 | if (HYPERVISOR_set_trap_table(traps)) | |
847 | BUG(); | |
848 | ||
849 | spin_unlock(&lock); | |
850 | } | |
851 | ||
852 | /* Write a GDT descriptor entry. Ignore LDT descriptors, since | |
853 | they're handled differently. */ | |
854 | static void xen_write_gdt_entry(struct desc_struct *dt, int entry, | |
014b15be | 855 | const void *desc, int type) |
5ead97c8 | 856 | { |
ab78f7ad JF |
857 | trace_xen_cpu_write_gdt_entry(dt, entry, desc, type); |
858 | ||
f120f13e JF |
859 | preempt_disable(); |
860 | ||
014b15be GOC |
861 | switch (type) { |
862 | case DESC_LDT: | |
863 | case DESC_TSS: | |
5ead97c8 JF |
864 | /* ignore */ |
865 | break; | |
866 | ||
867 | default: { | |
9976b39b | 868 | xmaddr_t maddr = arbitrary_virt_to_machine(&dt[entry]); |
5ead97c8 JF |
869 | |
870 | xen_mc_flush(); | |
014b15be | 871 | if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc)) |
5ead97c8 JF |
872 | BUG(); |
873 | } | |
874 | ||
875 | } | |
f120f13e JF |
876 | |
877 | preempt_enable(); | |
5ead97c8 JF |
878 | } |
879 | ||
577eebea JF |
880 | /* |
881 | * Version of write_gdt_entry for use at early boot-time needed to | |
882 | * update an entry as simply as possible. | |
883 | */ | |
ad3062a0 | 884 | static void __init xen_write_gdt_entry_boot(struct desc_struct *dt, int entry, |
577eebea JF |
885 | const void *desc, int type) |
886 | { | |
ab78f7ad JF |
887 | trace_xen_cpu_write_gdt_entry(dt, entry, desc, type); |
888 | ||
577eebea JF |
889 | switch (type) { |
890 | case DESC_LDT: | |
891 | case DESC_TSS: | |
892 | /* ignore */ | |
893 | break; | |
894 | ||
895 | default: { | |
896 | xmaddr_t maddr = virt_to_machine(&dt[entry]); | |
897 | ||
898 | if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc)) | |
899 | dt[entry] = *(struct desc_struct *)desc; | |
900 | } | |
901 | ||
902 | } | |
903 | } | |
904 | ||
faca6227 | 905 | static void xen_load_sp0(struct tss_struct *tss, |
a05d2eba | 906 | struct thread_struct *thread) |
5ead97c8 | 907 | { |
ab78f7ad JF |
908 | struct multicall_space mcs; |
909 | ||
910 | mcs = xen_mc_entry(0); | |
faca6227 | 911 | MULTI_stack_switch(mcs.mc, __KERNEL_DS, thread->sp0); |
5ead97c8 JF |
912 | xen_mc_issue(PARAVIRT_LAZY_CPU); |
913 | } | |
914 | ||
915 | static void xen_set_iopl_mask(unsigned mask) | |
916 | { | |
917 | struct physdev_set_iopl set_iopl; | |
918 | ||
919 | /* Force the change at ring 0. */ | |
920 | set_iopl.iopl = (mask == 0) ? 1 : (mask >> 12) & 3; | |
921 | HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl); | |
922 | } | |
923 | ||
924 | static void xen_io_delay(void) | |
925 | { | |
926 | } | |
927 | ||
928 | #ifdef CONFIG_X86_LOCAL_APIC | |
558daa28 KRW |
929 | static unsigned long xen_set_apic_id(unsigned int x) |
930 | { | |
931 | WARN_ON(1); | |
932 | return x; | |
933 | } | |
934 | static unsigned int xen_get_apic_id(unsigned long x) | |
935 | { | |
936 | return ((x)>>24) & 0xFFu; | |
937 | } | |
ad66dd34 | 938 | static u32 xen_apic_read(u32 reg) |
5ead97c8 | 939 | { |
558daa28 KRW |
940 | struct xen_platform_op op = { |
941 | .cmd = XENPF_get_cpuinfo, | |
942 | .interface_version = XENPF_INTERFACE_VERSION, | |
943 | .u.pcpu_info.xen_cpuid = 0, | |
944 | }; | |
945 | int ret = 0; | |
946 | ||
947 | /* Shouldn't need this as APIC is turned off for PV, and we only | |
948 | * get called on the bootup processor. But just in case. */ | |
949 | if (!xen_initial_domain() || smp_processor_id()) | |
950 | return 0; | |
951 | ||
952 | if (reg == APIC_LVR) | |
953 | return 0x10; | |
954 | ||
955 | if (reg != APIC_ID) | |
956 | return 0; | |
957 | ||
958 | ret = HYPERVISOR_dom0_op(&op); | |
959 | if (ret) | |
960 | return 0; | |
961 | ||
962 | return op.u.pcpu_info.apic_id << 24; | |
5ead97c8 | 963 | } |
f87e4cac | 964 | |
ad66dd34 | 965 | static void xen_apic_write(u32 reg, u32 val) |
f87e4cac JF |
966 | { |
967 | /* Warn to see if there's any stray references */ | |
968 | WARN_ON(1); | |
969 | } | |
ad66dd34 | 970 | |
ad66dd34 SS |
971 | static u64 xen_apic_icr_read(void) |
972 | { | |
973 | return 0; | |
974 | } | |
975 | ||
976 | static void xen_apic_icr_write(u32 low, u32 id) | |
977 | { | |
978 | /* Warn to see if there's any stray references */ | |
979 | WARN_ON(1); | |
980 | } | |
981 | ||
982 | static void xen_apic_wait_icr_idle(void) | |
983 | { | |
984 | return; | |
985 | } | |
986 | ||
94a8c3c2 YL |
987 | static u32 xen_safe_apic_wait_icr_idle(void) |
988 | { | |
989 | return 0; | |
990 | } | |
991 | ||
c1eeb2de YL |
992 | static void set_xen_basic_apic_ops(void) |
993 | { | |
994 | apic->read = xen_apic_read; | |
995 | apic->write = xen_apic_write; | |
996 | apic->icr_read = xen_apic_icr_read; | |
997 | apic->icr_write = xen_apic_icr_write; | |
998 | apic->wait_icr_idle = xen_apic_wait_icr_idle; | |
999 | apic->safe_wait_icr_idle = xen_safe_apic_wait_icr_idle; | |
558daa28 KRW |
1000 | apic->set_apic_id = xen_set_apic_id; |
1001 | apic->get_apic_id = xen_get_apic_id; | |
f447d56d BG |
1002 | |
1003 | #ifdef CONFIG_SMP | |
1004 | apic->send_IPI_allbutself = xen_send_IPI_allbutself; | |
1005 | apic->send_IPI_mask_allbutself = xen_send_IPI_mask_allbutself; | |
1006 | apic->send_IPI_mask = xen_send_IPI_mask; | |
1007 | apic->send_IPI_all = xen_send_IPI_all; | |
1008 | apic->send_IPI_self = xen_send_IPI_self; | |
1009 | #endif | |
c1eeb2de | 1010 | } |
ad66dd34 | 1011 | |
5ead97c8 JF |
1012 | #endif |
1013 | ||
7b1333aa JF |
1014 | static void xen_clts(void) |
1015 | { | |
1016 | struct multicall_space mcs; | |
1017 | ||
1018 | mcs = xen_mc_entry(0); | |
1019 | ||
1020 | MULTI_fpu_taskswitch(mcs.mc, 0); | |
1021 | ||
1022 | xen_mc_issue(PARAVIRT_LAZY_CPU); | |
1023 | } | |
1024 | ||
a789ed5f JF |
1025 | static DEFINE_PER_CPU(unsigned long, xen_cr0_value); |
1026 | ||
1027 | static unsigned long xen_read_cr0(void) | |
1028 | { | |
2113f469 | 1029 | unsigned long cr0 = this_cpu_read(xen_cr0_value); |
a789ed5f JF |
1030 | |
1031 | if (unlikely(cr0 == 0)) { | |
1032 | cr0 = native_read_cr0(); | |
2113f469 | 1033 | this_cpu_write(xen_cr0_value, cr0); |
a789ed5f JF |
1034 | } |
1035 | ||
1036 | return cr0; | |
1037 | } | |
1038 | ||
7b1333aa JF |
1039 | static void xen_write_cr0(unsigned long cr0) |
1040 | { | |
1041 | struct multicall_space mcs; | |
1042 | ||
2113f469 | 1043 | this_cpu_write(xen_cr0_value, cr0); |
a789ed5f | 1044 | |
7b1333aa JF |
1045 | /* Only pay attention to cr0.TS; everything else is |
1046 | ignored. */ | |
1047 | mcs = xen_mc_entry(0); | |
1048 | ||
1049 | MULTI_fpu_taskswitch(mcs.mc, (cr0 & X86_CR0_TS) != 0); | |
1050 | ||
1051 | xen_mc_issue(PARAVIRT_LAZY_CPU); | |
1052 | } | |
1053 | ||
5ead97c8 JF |
1054 | static void xen_write_cr4(unsigned long cr4) |
1055 | { | |
2956a351 JF |
1056 | cr4 &= ~X86_CR4_PGE; |
1057 | cr4 &= ~X86_CR4_PSE; | |
1058 | ||
1059 | native_write_cr4(cr4); | |
5ead97c8 | 1060 | } |
1a7bbda5 KRW |
1061 | #ifdef CONFIG_X86_64 |
1062 | static inline unsigned long xen_read_cr8(void) | |
1063 | { | |
1064 | return 0; | |
1065 | } | |
1066 | static inline void xen_write_cr8(unsigned long val) | |
1067 | { | |
1068 | BUG_ON(val); | |
1069 | } | |
1070 | #endif | |
1153968a JF |
1071 | static int xen_write_msr_safe(unsigned int msr, unsigned low, unsigned high) |
1072 | { | |
1073 | int ret; | |
1074 | ||
1075 | ret = 0; | |
1076 | ||
f63c2f24 | 1077 | switch (msr) { |
1153968a JF |
1078 | #ifdef CONFIG_X86_64 |
1079 | unsigned which; | |
1080 | u64 base; | |
1081 | ||
1082 | case MSR_FS_BASE: which = SEGBASE_FS; goto set; | |
1083 | case MSR_KERNEL_GS_BASE: which = SEGBASE_GS_USER; goto set; | |
1084 | case MSR_GS_BASE: which = SEGBASE_GS_KERNEL; goto set; | |
1085 | ||
1086 | set: | |
1087 | base = ((u64)high << 32) | low; | |
1088 | if (HYPERVISOR_set_segment_base(which, base) != 0) | |
0cc0213e | 1089 | ret = -EIO; |
1153968a JF |
1090 | break; |
1091 | #endif | |
d89961e2 JF |
1092 | |
1093 | case MSR_STAR: | |
1094 | case MSR_CSTAR: | |
1095 | case MSR_LSTAR: | |
1096 | case MSR_SYSCALL_MASK: | |
1097 | case MSR_IA32_SYSENTER_CS: | |
1098 | case MSR_IA32_SYSENTER_ESP: | |
1099 | case MSR_IA32_SYSENTER_EIP: | |
1100 | /* Fast syscall setup is all done in hypercalls, so | |
1101 | these are all ignored. Stub them out here to stop | |
1102 | Xen console noise. */ | |
1103 | break; | |
1104 | ||
41f2e477 JF |
1105 | case MSR_IA32_CR_PAT: |
1106 | if (smp_processor_id() == 0) | |
1107 | xen_set_pat(((u64)high << 32) | low); | |
1108 | break; | |
1109 | ||
1153968a JF |
1110 | default: |
1111 | ret = native_write_msr_safe(msr, low, high); | |
1112 | } | |
1113 | ||
1114 | return ret; | |
1115 | } | |
1116 | ||
0e91398f | 1117 | void xen_setup_shared_info(void) |
5ead97c8 JF |
1118 | { |
1119 | if (!xen_feature(XENFEAT_auto_translated_physmap)) { | |
15664f96 JF |
1120 | set_fixmap(FIX_PARAVIRT_BOOTMAP, |
1121 | xen_start_info->shared_info); | |
1122 | ||
1123 | HYPERVISOR_shared_info = | |
1124 | (struct shared_info *)fix_to_virt(FIX_PARAVIRT_BOOTMAP); | |
5ead97c8 JF |
1125 | } else |
1126 | HYPERVISOR_shared_info = | |
1127 | (struct shared_info *)__va(xen_start_info->shared_info); | |
1128 | ||
2e8fe719 JF |
1129 | #ifndef CONFIG_SMP |
1130 | /* In UP this is as good a place as any to set up shared info */ | |
1131 | xen_setup_vcpu_info_placement(); | |
1132 | #endif | |
d5edbc1f JF |
1133 | |
1134 | xen_setup_mfn_list_list(); | |
2e8fe719 JF |
1135 | } |
1136 | ||
5f054e31 | 1137 | /* This is called once we have the cpu_possible_mask */ |
0e91398f | 1138 | void xen_setup_vcpu_info_placement(void) |
60223a32 JF |
1139 | { |
1140 | int cpu; | |
1141 | ||
1142 | for_each_possible_cpu(cpu) | |
1143 | xen_vcpu_setup(cpu); | |
1144 | ||
1145 | /* xen_vcpu_setup managed to place the vcpu_info within the | |
2771374d MR |
1146 | * percpu area for all cpus, so make use of it. Note that for |
1147 | * PVH we want to use native IRQ mechanism. */ | |
1148 | if (have_vcpu_info_placement && !xen_pvh_domain()) { | |
ecb93d1c JF |
1149 | pv_irq_ops.save_fl = __PV_IS_CALLEE_SAVE(xen_save_fl_direct); |
1150 | pv_irq_ops.restore_fl = __PV_IS_CALLEE_SAVE(xen_restore_fl_direct); | |
1151 | pv_irq_ops.irq_disable = __PV_IS_CALLEE_SAVE(xen_irq_disable_direct); | |
1152 | pv_irq_ops.irq_enable = __PV_IS_CALLEE_SAVE(xen_irq_enable_direct); | |
93b1eab3 | 1153 | pv_mmu_ops.read_cr2 = xen_read_cr2_direct; |
60223a32 | 1154 | } |
5ead97c8 JF |
1155 | } |
1156 | ||
ab144f5e AK |
1157 | static unsigned xen_patch(u8 type, u16 clobbers, void *insnbuf, |
1158 | unsigned long addr, unsigned len) | |
6487673b JF |
1159 | { |
1160 | char *start, *end, *reloc; | |
1161 | unsigned ret; | |
1162 | ||
1163 | start = end = reloc = NULL; | |
1164 | ||
93b1eab3 JF |
1165 | #define SITE(op, x) \ |
1166 | case PARAVIRT_PATCH(op.x): \ | |
6487673b JF |
1167 | if (have_vcpu_info_placement) { \ |
1168 | start = (char *)xen_##x##_direct; \ | |
1169 | end = xen_##x##_direct_end; \ | |
1170 | reloc = xen_##x##_direct_reloc; \ | |
1171 | } \ | |
1172 | goto patch_site | |
1173 | ||
1174 | switch (type) { | |
93b1eab3 JF |
1175 | SITE(pv_irq_ops, irq_enable); |
1176 | SITE(pv_irq_ops, irq_disable); | |
1177 | SITE(pv_irq_ops, save_fl); | |
1178 | SITE(pv_irq_ops, restore_fl); | |
6487673b JF |
1179 | #undef SITE |
1180 | ||
1181 | patch_site: | |
1182 | if (start == NULL || (end-start) > len) | |
1183 | goto default_patch; | |
1184 | ||
ab144f5e | 1185 | ret = paravirt_patch_insns(insnbuf, len, start, end); |
6487673b JF |
1186 | |
1187 | /* Note: because reloc is assigned from something that | |
1188 | appears to be an array, gcc assumes it's non-null, | |
1189 | but doesn't know its relationship with start and | |
1190 | end. */ | |
1191 | if (reloc > start && reloc < end) { | |
1192 | int reloc_off = reloc - start; | |
ab144f5e AK |
1193 | long *relocp = (long *)(insnbuf + reloc_off); |
1194 | long delta = start - (char *)addr; | |
6487673b JF |
1195 | |
1196 | *relocp += delta; | |
1197 | } | |
1198 | break; | |
1199 | ||
1200 | default_patch: | |
1201 | default: | |
ab144f5e AK |
1202 | ret = paravirt_patch_default(type, clobbers, insnbuf, |
1203 | addr, len); | |
6487673b JF |
1204 | break; |
1205 | } | |
1206 | ||
1207 | return ret; | |
1208 | } | |
1209 | ||
ad3062a0 | 1210 | static const struct pv_info xen_info __initconst = { |
5ead97c8 JF |
1211 | .paravirt_enabled = 1, |
1212 | .shared_kernel_pmd = 0, | |
1213 | ||
318f5a2a AL |
1214 | #ifdef CONFIG_X86_64 |
1215 | .extra_user_64bit_cs = FLAT_USER_CS64, | |
1216 | #endif | |
1217 | ||
5ead97c8 | 1218 | .name = "Xen", |
93b1eab3 | 1219 | }; |
5ead97c8 | 1220 | |
ad3062a0 | 1221 | static const struct pv_init_ops xen_init_ops __initconst = { |
6487673b | 1222 | .patch = xen_patch, |
93b1eab3 | 1223 | }; |
5ead97c8 | 1224 | |
ad3062a0 | 1225 | static const struct pv_cpu_ops xen_cpu_ops __initconst = { |
5ead97c8 JF |
1226 | .cpuid = xen_cpuid, |
1227 | ||
1228 | .set_debugreg = xen_set_debugreg, | |
1229 | .get_debugreg = xen_get_debugreg, | |
1230 | ||
7b1333aa | 1231 | .clts = xen_clts, |
5ead97c8 | 1232 | |
a789ed5f | 1233 | .read_cr0 = xen_read_cr0, |
7b1333aa | 1234 | .write_cr0 = xen_write_cr0, |
5ead97c8 | 1235 | |
5ead97c8 JF |
1236 | .read_cr4 = native_read_cr4, |
1237 | .read_cr4_safe = native_read_cr4_safe, | |
1238 | .write_cr4 = xen_write_cr4, | |
1239 | ||
1a7bbda5 KRW |
1240 | #ifdef CONFIG_X86_64 |
1241 | .read_cr8 = xen_read_cr8, | |
1242 | .write_cr8 = xen_write_cr8, | |
1243 | #endif | |
1244 | ||
5ead97c8 JF |
1245 | .wbinvd = native_wbinvd, |
1246 | ||
1247 | .read_msr = native_read_msr_safe, | |
1153968a | 1248 | .write_msr = xen_write_msr_safe, |
1ab46fd3 | 1249 | |
5ead97c8 JF |
1250 | .read_tsc = native_read_tsc, |
1251 | .read_pmc = native_read_pmc, | |
1252 | ||
cd0608e7 KRW |
1253 | .read_tscp = native_read_tscp, |
1254 | ||
81e103f1 | 1255 | .iret = xen_iret, |
d75cd22f | 1256 | .irq_enable_sysexit = xen_sysexit, |
6fcac6d3 JF |
1257 | #ifdef CONFIG_X86_64 |
1258 | .usergs_sysret32 = xen_sysret32, | |
1259 | .usergs_sysret64 = xen_sysret64, | |
1260 | #endif | |
5ead97c8 JF |
1261 | |
1262 | .load_tr_desc = paravirt_nop, | |
1263 | .set_ldt = xen_set_ldt, | |
1264 | .load_gdt = xen_load_gdt, | |
1265 | .load_idt = xen_load_idt, | |
1266 | .load_tls = xen_load_tls, | |
a8fc1089 EH |
1267 | #ifdef CONFIG_X86_64 |
1268 | .load_gs_index = xen_load_gs_index, | |
1269 | #endif | |
5ead97c8 | 1270 | |
38ffbe66 JF |
1271 | .alloc_ldt = xen_alloc_ldt, |
1272 | .free_ldt = xen_free_ldt, | |
1273 | ||
5ead97c8 JF |
1274 | .store_idt = native_store_idt, |
1275 | .store_tr = xen_store_tr, | |
1276 | ||
1277 | .write_ldt_entry = xen_write_ldt_entry, | |
1278 | .write_gdt_entry = xen_write_gdt_entry, | |
1279 | .write_idt_entry = xen_write_idt_entry, | |
faca6227 | 1280 | .load_sp0 = xen_load_sp0, |
5ead97c8 JF |
1281 | |
1282 | .set_iopl_mask = xen_set_iopl_mask, | |
1283 | .io_delay = xen_io_delay, | |
1284 | ||
952d1d70 JF |
1285 | /* Xen takes care of %gs when switching to usermode for us */ |
1286 | .swapgs = paravirt_nop, | |
1287 | ||
224101ed JF |
1288 | .start_context_switch = paravirt_start_context_switch, |
1289 | .end_context_switch = xen_end_context_switch, | |
93b1eab3 JF |
1290 | }; |
1291 | ||
ad3062a0 | 1292 | static const struct pv_apic_ops xen_apic_ops __initconst = { |
5ead97c8 | 1293 | #ifdef CONFIG_X86_LOCAL_APIC |
5ead97c8 JF |
1294 | .startup_ipi_hook = paravirt_nop, |
1295 | #endif | |
93b1eab3 JF |
1296 | }; |
1297 | ||
fefa629a JF |
1298 | static void xen_reboot(int reason) |
1299 | { | |
349c709f JF |
1300 | struct sched_shutdown r = { .reason = reason }; |
1301 | ||
349c709f | 1302 | if (HYPERVISOR_sched_op(SCHEDOP_shutdown, &r)) |
fefa629a JF |
1303 | BUG(); |
1304 | } | |
1305 | ||
1306 | static void xen_restart(char *msg) | |
1307 | { | |
1308 | xen_reboot(SHUTDOWN_reboot); | |
1309 | } | |
1310 | ||
1311 | static void xen_emergency_restart(void) | |
1312 | { | |
1313 | xen_reboot(SHUTDOWN_reboot); | |
1314 | } | |
1315 | ||
1316 | static void xen_machine_halt(void) | |
1317 | { | |
1318 | xen_reboot(SHUTDOWN_poweroff); | |
1319 | } | |
1320 | ||
b2abe506 TG |
1321 | static void xen_machine_power_off(void) |
1322 | { | |
1323 | if (pm_power_off) | |
1324 | pm_power_off(); | |
1325 | xen_reboot(SHUTDOWN_poweroff); | |
1326 | } | |
1327 | ||
fefa629a JF |
1328 | static void xen_crash_shutdown(struct pt_regs *regs) |
1329 | { | |
1330 | xen_reboot(SHUTDOWN_crash); | |
1331 | } | |
1332 | ||
f09f6d19 DD |
1333 | static int |
1334 | xen_panic_event(struct notifier_block *this, unsigned long event, void *ptr) | |
1335 | { | |
086748e5 | 1336 | xen_reboot(SHUTDOWN_crash); |
f09f6d19 DD |
1337 | return NOTIFY_DONE; |
1338 | } | |
1339 | ||
1340 | static struct notifier_block xen_panic_block = { | |
1341 | .notifier_call= xen_panic_event, | |
bc5eb201 | 1342 | .priority = INT_MIN |
f09f6d19 DD |
1343 | }; |
1344 | ||
1345 | int xen_panic_handler_init(void) | |
1346 | { | |
1347 | atomic_notifier_chain_register(&panic_notifier_list, &xen_panic_block); | |
1348 | return 0; | |
1349 | } | |
1350 | ||
ad3062a0 | 1351 | static const struct machine_ops xen_machine_ops __initconst = { |
fefa629a JF |
1352 | .restart = xen_restart, |
1353 | .halt = xen_machine_halt, | |
b2abe506 | 1354 | .power_off = xen_machine_power_off, |
fefa629a JF |
1355 | .shutdown = xen_machine_halt, |
1356 | .crash_shutdown = xen_crash_shutdown, | |
1357 | .emergency_restart = xen_emergency_restart, | |
1358 | }; | |
1359 | ||
96f28bc6 DV |
1360 | static void __init xen_boot_params_init_edd(void) |
1361 | { | |
1362 | #if IS_ENABLED(CONFIG_EDD) | |
1363 | struct xen_platform_op op; | |
1364 | struct edd_info *edd_info; | |
1365 | u32 *mbr_signature; | |
1366 | unsigned nr; | |
1367 | int ret; | |
1368 | ||
1369 | edd_info = boot_params.eddbuf; | |
1370 | mbr_signature = boot_params.edd_mbr_sig_buffer; | |
1371 | ||
1372 | op.cmd = XENPF_firmware_info; | |
1373 | ||
1374 | op.u.firmware_info.type = XEN_FW_DISK_INFO; | |
1375 | for (nr = 0; nr < EDDMAXNR; nr++) { | |
1376 | struct edd_info *info = edd_info + nr; | |
1377 | ||
1378 | op.u.firmware_info.index = nr; | |
1379 | info->params.length = sizeof(info->params); | |
1380 | set_xen_guest_handle(op.u.firmware_info.u.disk_info.edd_params, | |
1381 | &info->params); | |
1382 | ret = HYPERVISOR_dom0_op(&op); | |
1383 | if (ret) | |
1384 | break; | |
1385 | ||
1386 | #define C(x) info->x = op.u.firmware_info.u.disk_info.x | |
1387 | C(device); | |
1388 | C(version); | |
1389 | C(interface_support); | |
1390 | C(legacy_max_cylinder); | |
1391 | C(legacy_max_head); | |
1392 | C(legacy_sectors_per_track); | |
1393 | #undef C | |
1394 | } | |
1395 | boot_params.eddbuf_entries = nr; | |
1396 | ||
1397 | op.u.firmware_info.type = XEN_FW_DISK_MBR_SIGNATURE; | |
1398 | for (nr = 0; nr < EDD_MBR_SIG_MAX; nr++) { | |
1399 | op.u.firmware_info.index = nr; | |
1400 | ret = HYPERVISOR_dom0_op(&op); | |
1401 | if (ret) | |
1402 | break; | |
1403 | mbr_signature[nr] = op.u.firmware_info.u.disk_mbr_signature.mbr_signature; | |
1404 | } | |
1405 | boot_params.edd_mbr_sig_buf_entries = nr; | |
1406 | #endif | |
1407 | } | |
1408 | ||
577eebea JF |
1409 | /* |
1410 | * Set up the GDT and segment registers for -fstack-protector. Until | |
1411 | * we do this, we have to be careful not to call any stack-protected | |
1412 | * function, which is most of the kernel. | |
5840c84b MR |
1413 | * |
1414 | * Note, that it is __ref because the only caller of this after init | |
1415 | * is PVH which is not going to use xen_load_gdt_boot or other | |
1416 | * __init functions. | |
577eebea | 1417 | */ |
c9f6e997 | 1418 | static void __ref xen_setup_gdt(int cpu) |
577eebea | 1419 | { |
8d656bbe MR |
1420 | if (xen_feature(XENFEAT_auto_translated_physmap)) { |
1421 | #ifdef CONFIG_X86_64 | |
1422 | unsigned long dummy; | |
1423 | ||
5840c84b MR |
1424 | load_percpu_segment(cpu); /* We need to access per-cpu area */ |
1425 | switch_to_new_gdt(cpu); /* GDT and GS set */ | |
8d656bbe MR |
1426 | |
1427 | /* We are switching of the Xen provided GDT to our HVM mode | |
1428 | * GDT. The new GDT has __KERNEL_CS with CS.L = 1 | |
1429 | * and we are jumping to reload it. | |
1430 | */ | |
1431 | asm volatile ("pushq %0\n" | |
1432 | "leaq 1f(%%rip),%0\n" | |
1433 | "pushq %0\n" | |
1434 | "lretq\n" | |
1435 | "1:\n" | |
1436 | : "=&r" (dummy) : "0" (__KERNEL_CS)); | |
1437 | ||
1438 | /* | |
1439 | * While not needed, we also set the %es, %ds, and %fs | |
1440 | * to zero. We don't care about %ss as it is NULL. | |
1441 | * Strictly speaking this is not needed as Xen zeros those | |
1442 | * out (and also MSR_FS_BASE, MSR_GS_BASE, MSR_KERNEL_GS_BASE) | |
1443 | * | |
1444 | * Linux zeros them in cpu_init() and in secondary_startup_64 | |
1445 | * (for BSP). | |
1446 | */ | |
1447 | loadsegment(es, 0); | |
1448 | loadsegment(ds, 0); | |
1449 | loadsegment(fs, 0); | |
1450 | #else | |
1451 | /* PVH: TODO Implement. */ | |
1452 | BUG(); | |
1453 | #endif | |
1454 | return; /* PVH does not need any PV GDT ops. */ | |
1455 | } | |
577eebea JF |
1456 | pv_cpu_ops.write_gdt_entry = xen_write_gdt_entry_boot; |
1457 | pv_cpu_ops.load_gdt = xen_load_gdt_boot; | |
1458 | ||
1459 | setup_stack_canary_segment(0); | |
1460 | switch_to_new_gdt(0); | |
1461 | ||
1462 | pv_cpu_ops.write_gdt_entry = xen_write_gdt_entry; | |
1463 | pv_cpu_ops.load_gdt = xen_load_gdt; | |
1464 | } | |
1465 | ||
c9f6e997 RPM |
1466 | /* |
1467 | * A PV guest starts with default flags that are not set for PVH, set them | |
1468 | * here asap. | |
1469 | */ | |
1470 | static void xen_pvh_set_cr_flags(int cpu) | |
1471 | { | |
1472 | ||
1473 | /* Some of these are setup in 'secondary_startup_64'. The others: | |
1474 | * X86_CR0_TS, X86_CR0_PE, X86_CR0_ET are set by Xen for HVM guests | |
1475 | * (which PVH shared codepaths), while X86_CR0_PG is for PVH. */ | |
1476 | write_cr0(read_cr0() | X86_CR0_MP | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM); | |
afca5013 MR |
1477 | |
1478 | if (!cpu) | |
1479 | return; | |
1480 | /* | |
1481 | * For BSP, PSE PGE are set in probe_page_size_mask(), for APs | |
1482 | * set them here. For all, OSFXSR OSXMMEXCPT are set in fpu_init. | |
1483 | */ | |
1484 | if (cpu_has_pse) | |
1485 | set_in_cr4(X86_CR4_PSE); | |
1486 | ||
1487 | if (cpu_has_pge) | |
1488 | set_in_cr4(X86_CR4_PGE); | |
c9f6e997 RPM |
1489 | } |
1490 | ||
1491 | /* | |
1492 | * Note, that it is ref - because the only caller of this after init | |
1493 | * is PVH which is not going to use xen_load_gdt_boot or other | |
1494 | * __init functions. | |
1495 | */ | |
1496 | void __ref xen_pvh_secondary_vcpu_init(int cpu) | |
1497 | { | |
1498 | xen_setup_gdt(cpu); | |
1499 | xen_pvh_set_cr_flags(cpu); | |
1500 | } | |
1501 | ||
d285d683 MR |
1502 | static void __init xen_pvh_early_guest_init(void) |
1503 | { | |
1504 | if (!xen_feature(XENFEAT_auto_translated_physmap)) | |
1505 | return; | |
1506 | ||
c9f6e997 RPM |
1507 | if (!xen_feature(XENFEAT_hvm_callback_vector)) |
1508 | return; | |
1509 | ||
1510 | xen_have_vector_callback = 1; | |
1511 | xen_pvh_set_cr_flags(0); | |
d285d683 MR |
1512 | |
1513 | #ifdef CONFIG_X86_32 | |
1514 | BUG(); /* PVH: Implement proper support. */ | |
1515 | #endif | |
1516 | } | |
1517 | ||
5ead97c8 | 1518 | /* First C function to be called on Xen boot */ |
2605fc21 | 1519 | asmlinkage __visible void __init xen_start_kernel(void) |
5ead97c8 | 1520 | { |
ec35a69c KRW |
1521 | struct physdev_set_iopl set_iopl; |
1522 | int rc; | |
5ead97c8 JF |
1523 | |
1524 | if (!xen_start_info) | |
1525 | return; | |
1526 | ||
6e833587 JF |
1527 | xen_domain_type = XEN_PV_DOMAIN; |
1528 | ||
d285d683 MR |
1529 | xen_setup_features(); |
1530 | xen_pvh_early_guest_init(); | |
7e77506a IC |
1531 | xen_setup_machphys_mapping(); |
1532 | ||
5ead97c8 | 1533 | /* Install Xen paravirt ops */ |
93b1eab3 JF |
1534 | pv_info = xen_info; |
1535 | pv_init_ops = xen_init_ops; | |
93b1eab3 | 1536 | pv_apic_ops = xen_apic_ops; |
d285d683 MR |
1537 | if (!xen_pvh_domain()) |
1538 | pv_cpu_ops = xen_cpu_ops; | |
93b1eab3 | 1539 | |
abacaadc DV |
1540 | if (xen_feature(XENFEAT_auto_translated_physmap)) |
1541 | x86_init.resources.memory_setup = xen_auto_xlated_memory_setup; | |
1542 | else | |
1543 | x86_init.resources.memory_setup = xen_memory_setup; | |
42bbdb43 | 1544 | x86_init.oem.arch_setup = xen_arch_setup; |
6f30c1ac | 1545 | x86_init.oem.banner = xen_banner; |
845b3944 | 1546 | |
409771d2 | 1547 | xen_init_time_ops(); |
93b1eab3 | 1548 | |
ce2eef33 | 1549 | /* |
577eebea | 1550 | * Set up some pagetable state before starting to set any ptes. |
ce2eef33 | 1551 | */ |
577eebea | 1552 | |
973df35e JF |
1553 | xen_init_mmu_ops(); |
1554 | ||
577eebea JF |
1555 | /* Prevent unwanted bits from being set in PTEs. */ |
1556 | __supported_pte_mask &= ~_PAGE_GLOBAL; | |
8eaffa67 | 1557 | #if 0 |
577eebea | 1558 | if (!xen_initial_domain()) |
8eaffa67 | 1559 | #endif |
577eebea JF |
1560 | __supported_pte_mask &= ~(_PAGE_PWT | _PAGE_PCD); |
1561 | ||
1562 | __supported_pte_mask |= _PAGE_IOMAP; | |
1563 | ||
817a824b IC |
1564 | /* |
1565 | * Prevent page tables from being allocated in highmem, even | |
1566 | * if CONFIG_HIGHPTE is enabled. | |
1567 | */ | |
1568 | __userpte_alloc_gfp &= ~__GFP_HIGHMEM; | |
1569 | ||
b75fe4e5 | 1570 | /* Work out if we support NX */ |
4763ed4d | 1571 | x86_configure_nx(); |
b75fe4e5 | 1572 | |
577eebea | 1573 | /* Get mfn list */ |
696fd7c5 | 1574 | xen_build_dynamic_phys_to_machine(); |
577eebea JF |
1575 | |
1576 | /* | |
1577 | * Set up kernel GDT and segment registers, mainly so that | |
1578 | * -fstack-protector code can be executed. | |
1579 | */ | |
5840c84b | 1580 | xen_setup_gdt(0); |
0d1edf46 | 1581 | |
ce2eef33 | 1582 | xen_init_irq_ops(); |
e826fe1b JF |
1583 | xen_init_cpuid_mask(); |
1584 | ||
94a8c3c2 | 1585 | #ifdef CONFIG_X86_LOCAL_APIC |
ad66dd34 | 1586 | /* |
94a8c3c2 | 1587 | * set up the basic apic ops. |
ad66dd34 | 1588 | */ |
c1eeb2de | 1589 | set_xen_basic_apic_ops(); |
ad66dd34 | 1590 | #endif |
93b1eab3 | 1591 | |
e57778a1 JF |
1592 | if (xen_feature(XENFEAT_mmu_pt_update_preserve_ad)) { |
1593 | pv_mmu_ops.ptep_modify_prot_start = xen_ptep_modify_prot_start; | |
1594 | pv_mmu_ops.ptep_modify_prot_commit = xen_ptep_modify_prot_commit; | |
1595 | } | |
1596 | ||
fefa629a JF |
1597 | machine_ops = xen_machine_ops; |
1598 | ||
38341432 JF |
1599 | /* |
1600 | * The only reliable way to retain the initial address of the | |
1601 | * percpu gdt_page is to remember it here, so we can go and | |
1602 | * mark it RW later, when the initial percpu area is freed. | |
1603 | */ | |
1604 | xen_initial_gdt = &per_cpu(gdt_page, 0); | |
795f99b6 | 1605 | |
a9e7062d | 1606 | xen_smp_init(); |
5ead97c8 | 1607 | |
c1f5db1a IC |
1608 | #ifdef CONFIG_ACPI_NUMA |
1609 | /* | |
1610 | * The pages we from Xen are not related to machine pages, so | |
1611 | * any NUMA information the kernel tries to get from ACPI will | |
1612 | * be meaningless. Prevent it from trying. | |
1613 | */ | |
1614 | acpi_numa = -1; | |
1615 | #endif | |
c79c4982 KRW |
1616 | #ifdef CONFIG_X86_PAT |
1617 | /* | |
1618 | * For right now disable the PAT. We should remove this once | |
1619 | * git commit 8eaffa67b43e99ae581622c5133e20b0f48bcef1 | |
1620 | * (xen/pat: Disable PAT support for now) is reverted. | |
1621 | */ | |
1622 | pat_enabled = 0; | |
1623 | #endif | |
60223a32 | 1624 | /* Don't do the full vcpu_info placement stuff until we have a |
2e8fe719 | 1625 | possible map and a non-dummy shared_info. */ |
60223a32 | 1626 | per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0]; |
5ead97c8 | 1627 | |
55d80856 | 1628 | local_irq_disable(); |
2ce802f6 | 1629 | early_boot_irqs_disabled = true; |
55d80856 | 1630 | |
084a2a4e | 1631 | xen_raw_console_write("mapping kernel into physical memory\n"); |
3699aad0 | 1632 | xen_setup_kernel_pagetable((pgd_t *)xen_start_info->pt_base, xen_start_info->nr_pages); |
5ead97c8 | 1633 | |
33a84750 JF |
1634 | /* Allocate and initialize top and mid mfn levels for p2m structure */ |
1635 | xen_build_mfn_list_list(); | |
1636 | ||
5ead97c8 JF |
1637 | /* keep using Xen gdt for now; no urgent need to change it */ |
1638 | ||
e68266b7 | 1639 | #ifdef CONFIG_X86_32 |
93b1eab3 | 1640 | pv_info.kernel_rpl = 1; |
5ead97c8 | 1641 | if (xen_feature(XENFEAT_supervisor_mode_kernel)) |
93b1eab3 | 1642 | pv_info.kernel_rpl = 0; |
e68266b7 IC |
1643 | #else |
1644 | pv_info.kernel_rpl = 0; | |
1645 | #endif | |
5ead97c8 | 1646 | /* set the limit of our address space */ |
fb1d8404 | 1647 | xen_reserve_top(); |
5ead97c8 | 1648 | |
d285d683 MR |
1649 | /* PVH: runs at default kernel iopl of 0 */ |
1650 | if (!xen_pvh_domain()) { | |
1651 | /* | |
1652 | * We used to do this in xen_arch_setup, but that is too late | |
1653 | * on AMD were early_cpu_init (run before ->arch_setup()) calls | |
1654 | * early_amd_init which pokes 0xcf8 port. | |
1655 | */ | |
1656 | set_iopl.iopl = 1; | |
1657 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl); | |
1658 | if (rc != 0) | |
1659 | xen_raw_printk("physdev_op failed %d\n", rc); | |
1660 | } | |
ec35a69c | 1661 | |
7d087b68 | 1662 | #ifdef CONFIG_X86_32 |
5ead97c8 JF |
1663 | /* set up basic CPUID stuff */ |
1664 | cpu_detect(&new_cpu_data); | |
60e019eb | 1665 | set_cpu_cap(&new_cpu_data, X86_FEATURE_FPU); |
d560bc61 | 1666 | new_cpu_data.wp_works_ok = 1; |
5ead97c8 | 1667 | new_cpu_data.x86_capability[0] = cpuid_edx(1); |
7d087b68 | 1668 | #endif |
5ead97c8 JF |
1669 | |
1670 | /* Poke various useful things into boot_params */ | |
30c82645 PA |
1671 | boot_params.hdr.type_of_loader = (9 << 4) | 0; |
1672 | boot_params.hdr.ramdisk_image = xen_start_info->mod_start | |
1673 | ? __pa(xen_start_info->mod_start) : 0; | |
1674 | boot_params.hdr.ramdisk_size = xen_start_info->mod_len; | |
b7c3c5c1 | 1675 | boot_params.hdr.cmd_line_ptr = __pa(xen_start_info->cmd_line); |
5ead97c8 | 1676 | |
6e833587 | 1677 | if (!xen_initial_domain()) { |
83abc70a | 1678 | add_preferred_console("xenboot", 0, NULL); |
9e124fe1 | 1679 | add_preferred_console("tty", 0, NULL); |
b8c2d3df | 1680 | add_preferred_console("hvc", 0, NULL); |
b5401a96 AN |
1681 | if (pci_xen) |
1682 | x86_init.pci.arch_init = pci_xen_init; | |
5d990b62 | 1683 | } else { |
c2419b4a JF |
1684 | const struct dom0_vga_console_info *info = |
1685 | (void *)((char *)xen_start_info + | |
1686 | xen_start_info->console.dom0.info_off); | |
ffb8b233 KRW |
1687 | struct xen_platform_op op = { |
1688 | .cmd = XENPF_firmware_info, | |
1689 | .interface_version = XENPF_INTERFACE_VERSION, | |
1690 | .u.firmware_info.type = XEN_FW_KBD_SHIFT_FLAGS, | |
1691 | }; | |
c2419b4a JF |
1692 | |
1693 | xen_init_vga(info, xen_start_info->console.dom0.info_size); | |
1694 | xen_start_info->console.domU.mfn = 0; | |
1695 | xen_start_info->console.domU.evtchn = 0; | |
1696 | ||
ffb8b233 KRW |
1697 | if (HYPERVISOR_dom0_op(&op) == 0) |
1698 | boot_params.kbd_status = op.u.firmware_info.u.kbd_shift_flags; | |
1699 | ||
31b3c9d7 KRW |
1700 | xen_init_apic(); |
1701 | ||
5d990b62 CW |
1702 | /* Make sure ACS will be enabled */ |
1703 | pci_request_acs(); | |
211063dc KRW |
1704 | |
1705 | xen_acpi_sleep_register(); | |
bd49940a KRW |
1706 | |
1707 | /* Avoid searching for BIOS MP tables */ | |
1708 | x86_init.mpparse.find_smp_config = x86_init_noop; | |
1709 | x86_init.mpparse.get_smp_config = x86_init_uint_noop; | |
96f28bc6 DV |
1710 | |
1711 | xen_boot_params_init_edd(); | |
9e124fe1 | 1712 | } |
76a8df7b DV |
1713 | #ifdef CONFIG_PCI |
1714 | /* PCI BIOS service won't work from a PV guest. */ | |
1715 | pci_probe &= ~PCI_PROBE_BIOS; | |
1716 | #endif | |
084a2a4e JF |
1717 | xen_raw_console_write("about to get started...\n"); |
1718 | ||
499d19b8 JF |
1719 | xen_setup_runstate_info(0); |
1720 | ||
c7341d6a | 1721 | xen_efi_init(); |
be81c8a1 | 1722 | |
5ead97c8 | 1723 | /* Start the world */ |
f5d36de0 | 1724 | #ifdef CONFIG_X86_32 |
f0d43100 | 1725 | i386_start_kernel(); |
f5d36de0 | 1726 | #else |
084a2a4e | 1727 | x86_64_start_reservations((char *)__pa_symbol(&boot_params)); |
f5d36de0 | 1728 | #endif |
5ead97c8 | 1729 | } |
bee6ab53 | 1730 | |
e9daff24 | 1731 | void __ref xen_hvm_init_shared_info(void) |
bee6ab53 | 1732 | { |
e9daff24 | 1733 | int cpu; |
bee6ab53 | 1734 | struct xen_add_to_physmap xatp; |
e9daff24 | 1735 | static struct shared_info *shared_info_page = 0; |
bee6ab53 | 1736 | |
e9daff24 KRW |
1737 | if (!shared_info_page) |
1738 | shared_info_page = (struct shared_info *) | |
1739 | extend_brk(PAGE_SIZE, PAGE_SIZE); | |
bee6ab53 SY |
1740 | xatp.domid = DOMID_SELF; |
1741 | xatp.idx = 0; | |
1742 | xatp.space = XENMAPSPACE_shared_info; | |
e9daff24 | 1743 | xatp.gpfn = __pa(shared_info_page) >> PAGE_SHIFT; |
bee6ab53 SY |
1744 | if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp)) |
1745 | BUG(); | |
1746 | ||
e9daff24 | 1747 | HYPERVISOR_shared_info = (struct shared_info *)shared_info_page; |
bee6ab53 | 1748 | |
016b6f5f SS |
1749 | /* xen_vcpu is a pointer to the vcpu_info struct in the shared_info |
1750 | * page, we use it in the event channel upcall and in some pvclock | |
1751 | * related functions. We don't need the vcpu_info placement | |
1752 | * optimizations because we don't use any pv_mmu or pv_irq op on | |
e9daff24 KRW |
1753 | * HVM. |
1754 | * When xen_hvm_init_shared_info is run at boot time only vcpu 0 is | |
1755 | * online but xen_hvm_init_shared_info is run at resume time too and | |
1756 | * in that case multiple vcpus might be online. */ | |
1757 | for_each_online_cpu(cpu) { | |
d5b17dbf KRW |
1758 | /* Leave it to be NULL. */ |
1759 | if (cpu >= MAX_VIRT_CPUS) | |
1760 | continue; | |
016b6f5f SS |
1761 | per_cpu(xen_vcpu, cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu]; |
1762 | } | |
bee6ab53 SY |
1763 | } |
1764 | ||
e9daff24 | 1765 | #ifdef CONFIG_XEN_PVHVM |
4ff2d062 OH |
1766 | static void __init init_hvm_pv_info(void) |
1767 | { | |
e9daff24 | 1768 | int major, minor; |
5eb65be2 | 1769 | uint32_t eax, ebx, ecx, edx, pages, msr, base; |
4ff2d062 OH |
1770 | u64 pfn; |
1771 | ||
1772 | base = xen_cpuid_base(); | |
e9daff24 KRW |
1773 | cpuid(base + 1, &eax, &ebx, &ecx, &edx); |
1774 | ||
1775 | major = eax >> 16; | |
1776 | minor = eax & 0xffff; | |
1777 | printk(KERN_INFO "Xen version %d.%d.\n", major, minor); | |
1778 | ||
4ff2d062 OH |
1779 | cpuid(base + 2, &pages, &msr, &ecx, &edx); |
1780 | ||
1781 | pfn = __pa(hypercall_page); | |
1782 | wrmsr_safe(msr, (u32)pfn, (u32)(pfn >> 32)); | |
1783 | ||
1784 | xen_setup_features(); | |
1785 | ||
1786 | pv_info.name = "Xen HVM"; | |
1787 | ||
1788 | xen_domain_type = XEN_HVM_DOMAIN; | |
1789 | } | |
1790 | ||
148f9bb8 PG |
1791 | static int xen_hvm_cpu_notify(struct notifier_block *self, unsigned long action, |
1792 | void *hcpu) | |
38e20b07 SY |
1793 | { |
1794 | int cpu = (long)hcpu; | |
1795 | switch (action) { | |
1796 | case CPU_UP_PREPARE: | |
90d4f553 | 1797 | xen_vcpu_setup(cpu); |
7918c92a | 1798 | if (xen_have_vector_callback) { |
7918c92a KRW |
1799 | if (xen_feature(XENFEAT_hvm_safe_pvclock)) |
1800 | xen_setup_timer(cpu); | |
1801 | } | |
38e20b07 SY |
1802 | break; |
1803 | default: | |
1804 | break; | |
1805 | } | |
1806 | return NOTIFY_OK; | |
1807 | } | |
1808 | ||
148f9bb8 | 1809 | static struct notifier_block xen_hvm_cpu_notifier = { |
38e20b07 SY |
1810 | .notifier_call = xen_hvm_cpu_notify, |
1811 | }; | |
1812 | ||
bee6ab53 SY |
1813 | static void __init xen_hvm_guest_init(void) |
1814 | { | |
4ff2d062 | 1815 | init_hvm_pv_info(); |
bee6ab53 | 1816 | |
016b6f5f | 1817 | xen_hvm_init_shared_info(); |
38e20b07 | 1818 | |
669b0ae9 VC |
1819 | xen_panic_handler_init(); |
1820 | ||
38e20b07 SY |
1821 | if (xen_feature(XENFEAT_hvm_callback_vector)) |
1822 | xen_have_vector_callback = 1; | |
99bbb3a8 | 1823 | xen_hvm_smp_init(); |
38e20b07 | 1824 | register_cpu_notifier(&xen_hvm_cpu_notifier); |
c1c5413a | 1825 | xen_unplug_emulated_devices(); |
38e20b07 | 1826 | x86_init.irqs.intr_init = xen_init_IRQ; |
409771d2 | 1827 | xen_hvm_init_time_ops(); |
59151001 | 1828 | xen_hvm_init_mmu_ops(); |
bee6ab53 SY |
1829 | } |
1830 | ||
8d693b91 KRW |
1831 | static bool xen_nopv = false; |
1832 | static __init int xen_parse_nopv(char *arg) | |
1833 | { | |
1834 | xen_nopv = true; | |
1835 | return 0; | |
1836 | } | |
1837 | early_param("xen_nopv", xen_parse_nopv); | |
1838 | ||
9df56f19 | 1839 | static uint32_t __init xen_hvm_platform(void) |
bee6ab53 | 1840 | { |
8d693b91 KRW |
1841 | if (xen_nopv) |
1842 | return 0; | |
1843 | ||
bee6ab53 | 1844 | if (xen_pv_domain()) |
9df56f19 | 1845 | return 0; |
bee6ab53 | 1846 | |
9df56f19 | 1847 | return xen_cpuid_base(); |
bee6ab53 SY |
1848 | } |
1849 | ||
d9b8ca84 SY |
1850 | bool xen_hvm_need_lapic(void) |
1851 | { | |
8d693b91 KRW |
1852 | if (xen_nopv) |
1853 | return false; | |
d9b8ca84 SY |
1854 | if (xen_pv_domain()) |
1855 | return false; | |
1856 | if (!xen_hvm_domain()) | |
1857 | return false; | |
1858 | if (xen_feature(XENFEAT_hvm_pirqs) && xen_have_vector_callback) | |
1859 | return false; | |
1860 | return true; | |
1861 | } | |
1862 | EXPORT_SYMBOL_GPL(xen_hvm_need_lapic); | |
1863 | ||
ad3062a0 | 1864 | const struct hypervisor_x86 x86_hyper_xen_hvm __refconst = { |
bee6ab53 SY |
1865 | .name = "Xen HVM", |
1866 | .detect = xen_hvm_platform, | |
1867 | .init_platform = xen_hvm_guest_init, | |
4cca6ea0 | 1868 | .x2apic_available = xen_x2apic_para_available, |
bee6ab53 SY |
1869 | }; |
1870 | EXPORT_SYMBOL(x86_hyper_xen_hvm); | |
ca65f9fc | 1871 | #endif |