Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
17 | #include <linux/config.h> | |
18 | #include <linux/init.h> | |
19 | ||
20 | #include <linux/mm.h> | |
1da177e4 LT |
21 | #include <linux/delay.h> |
22 | #include <linux/bootmem.h> | |
23 | #include <linux/smp_lock.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/mc146818rtc.h> | |
26 | #include <linux/kernel_stat.h> | |
27 | #include <linux/sysdev.h> | |
d25bf7e5 | 28 | #include <linux/module.h> |
1da177e4 LT |
29 | |
30 | #include <asm/atomic.h> | |
31 | #include <asm/smp.h> | |
32 | #include <asm/mtrr.h> | |
33 | #include <asm/mpspec.h> | |
34 | #include <asm/pgalloc.h> | |
35 | #include <asm/mach_apic.h> | |
75152114 | 36 | #include <asm/nmi.h> |
95833c83 | 37 | #include <asm/idle.h> |
73dea47f AK |
38 | #include <asm/proto.h> |
39 | #include <asm/timex.h> | |
1da177e4 LT |
40 | |
41 | int apic_verbosity; | |
73dea47f | 42 | int apic_runs_main_timer; |
1da177e4 LT |
43 | |
44 | int disable_apic_timer __initdata; | |
45 | ||
d25bf7e5 VP |
46 | /* |
47 | * cpu_mask that denotes the CPUs that needs timer interrupt coming in as | |
48 | * IPIs in place of local APIC timers | |
49 | */ | |
50 | static cpumask_t timer_interrupt_broadcast_ipi_mask; | |
51 | ||
1da177e4 LT |
52 | /* Using APIC to generate smp_local_timer_interrupt? */ |
53 | int using_apic_timer = 0; | |
54 | ||
1da177e4 LT |
55 | static void apic_pm_activate(void); |
56 | ||
57 | void enable_NMI_through_LVT0 (void * dummy) | |
58 | { | |
11a8e778 | 59 | unsigned int v; |
1da177e4 | 60 | |
1da177e4 | 61 | v = APIC_DM_NMI; /* unmask and set to NMI */ |
11a8e778 | 62 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
63 | } |
64 | ||
65 | int get_maxlvt(void) | |
66 | { | |
11a8e778 | 67 | unsigned int v, maxlvt; |
1da177e4 LT |
68 | |
69 | v = apic_read(APIC_LVR); | |
1da177e4 LT |
70 | maxlvt = GET_APIC_MAXLVT(v); |
71 | return maxlvt; | |
72 | } | |
73 | ||
74 | void clear_local_APIC(void) | |
75 | { | |
76 | int maxlvt; | |
77 | unsigned int v; | |
78 | ||
79 | maxlvt = get_maxlvt(); | |
80 | ||
81 | /* | |
82 | * Masking an LVT entry on a P6 can trigger a local APIC error | |
83 | * if the vector is zero. Mask LVTERR first to prevent this. | |
84 | */ | |
85 | if (maxlvt >= 3) { | |
86 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
11a8e778 | 87 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
1da177e4 LT |
88 | } |
89 | /* | |
90 | * Careful: we have to set masks only first to deassert | |
91 | * any level-triggered sources. | |
92 | */ | |
93 | v = apic_read(APIC_LVTT); | |
11a8e778 | 94 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
1da177e4 | 95 | v = apic_read(APIC_LVT0); |
11a8e778 | 96 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 | 97 | v = apic_read(APIC_LVT1); |
11a8e778 | 98 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); |
1da177e4 LT |
99 | if (maxlvt >= 4) { |
100 | v = apic_read(APIC_LVTPC); | |
11a8e778 | 101 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); |
1da177e4 LT |
102 | } |
103 | ||
104 | /* | |
105 | * Clean APIC state for other OSs: | |
106 | */ | |
11a8e778 AK |
107 | apic_write(APIC_LVTT, APIC_LVT_MASKED); |
108 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
109 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
1da177e4 | 110 | if (maxlvt >= 3) |
11a8e778 | 111 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); |
1da177e4 | 112 | if (maxlvt >= 4) |
11a8e778 | 113 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); |
1da177e4 | 114 | v = GET_APIC_VERSION(apic_read(APIC_LVR)); |
5a40b7c2 AK |
115 | apic_write(APIC_ESR, 0); |
116 | apic_read(APIC_ESR); | |
1da177e4 LT |
117 | } |
118 | ||
119 | void __init connect_bsp_APIC(void) | |
120 | { | |
121 | if (pic_mode) { | |
122 | /* | |
123 | * Do not trust the local APIC being empty at bootup. | |
124 | */ | |
125 | clear_local_APIC(); | |
126 | /* | |
127 | * PIC mode, enable APIC mode in the IMCR, i.e. | |
128 | * connect BSP's local APIC to INT and NMI lines. | |
129 | */ | |
130 | apic_printk(APIC_VERBOSE, "leaving PIC mode, enabling APIC mode.\n"); | |
131 | outb(0x70, 0x22); | |
132 | outb(0x01, 0x23); | |
133 | } | |
134 | } | |
135 | ||
208fb931 | 136 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 LT |
137 | { |
138 | if (pic_mode) { | |
139 | /* | |
140 | * Put the board back into PIC mode (has an effect | |
141 | * only on certain older boards). Note that APIC | |
142 | * interrupts, including IPIs, won't work beyond | |
143 | * this point! The only exception are INIT IPIs. | |
144 | */ | |
145 | apic_printk(APIC_QUIET, "disabling APIC mode, entering PIC mode.\n"); | |
146 | outb(0x70, 0x22); | |
147 | outb(0x00, 0x23); | |
148 | } | |
208fb931 EB |
149 | else { |
150 | /* Go back to Virtual Wire compatibility mode */ | |
151 | unsigned long value; | |
152 | ||
153 | /* For the spurious interrupt use vector F, and enable it */ | |
154 | value = apic_read(APIC_SPIV); | |
155 | value &= ~APIC_VECTOR_MASK; | |
156 | value |= APIC_SPIV_APIC_ENABLED; | |
157 | value |= 0xf; | |
11a8e778 | 158 | apic_write(APIC_SPIV, value); |
208fb931 EB |
159 | |
160 | if (!virt_wire_setup) { | |
161 | /* For LVT0 make it edge triggered, active high, external and enabled */ | |
162 | value = apic_read(APIC_LVT0); | |
163 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
164 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
165 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED ); | |
166 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
167 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
11a8e778 | 168 | apic_write(APIC_LVT0, value); |
208fb931 EB |
169 | } |
170 | else { | |
171 | /* Disable LVT0 */ | |
11a8e778 | 172 | apic_write(APIC_LVT0, APIC_LVT_MASKED); |
208fb931 EB |
173 | } |
174 | ||
175 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ | |
176 | value = apic_read(APIC_LVT1); | |
177 | value &= ~( | |
178 | APIC_MODE_MASK | APIC_SEND_PENDING | | |
179 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
180 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
181 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
182 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
11a8e778 | 183 | apic_write(APIC_LVT1, value); |
208fb931 | 184 | } |
1da177e4 LT |
185 | } |
186 | ||
187 | void disable_local_APIC(void) | |
188 | { | |
189 | unsigned int value; | |
190 | ||
191 | clear_local_APIC(); | |
192 | ||
193 | /* | |
194 | * Disable APIC (implies clearing of registers | |
195 | * for 82489DX!). | |
196 | */ | |
197 | value = apic_read(APIC_SPIV); | |
198 | value &= ~APIC_SPIV_APIC_ENABLED; | |
11a8e778 | 199 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
200 | } |
201 | ||
202 | /* | |
203 | * This is to verify that we're looking at a real local APIC. | |
204 | * Check these against your board if the CPUs aren't getting | |
205 | * started for no apparent reason. | |
206 | */ | |
207 | int __init verify_local_APIC(void) | |
208 | { | |
209 | unsigned int reg0, reg1; | |
210 | ||
211 | /* | |
212 | * The version register is read-only in a real APIC. | |
213 | */ | |
214 | reg0 = apic_read(APIC_LVR); | |
215 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
216 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
217 | reg1 = apic_read(APIC_LVR); | |
218 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
219 | ||
220 | /* | |
221 | * The two version reads above should print the same | |
222 | * numbers. If the second one is different, then we | |
223 | * poke at a non-APIC. | |
224 | */ | |
225 | if (reg1 != reg0) | |
226 | return 0; | |
227 | ||
228 | /* | |
229 | * Check if the version looks reasonably. | |
230 | */ | |
231 | reg1 = GET_APIC_VERSION(reg0); | |
232 | if (reg1 == 0x00 || reg1 == 0xff) | |
233 | return 0; | |
234 | reg1 = get_maxlvt(); | |
235 | if (reg1 < 0x02 || reg1 == 0xff) | |
236 | return 0; | |
237 | ||
238 | /* | |
239 | * The ID register is read/write in a real APIC. | |
240 | */ | |
241 | reg0 = apic_read(APIC_ID); | |
242 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
243 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
244 | reg1 = apic_read(APIC_ID); | |
245 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); | |
246 | apic_write(APIC_ID, reg0); | |
247 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
248 | return 0; | |
249 | ||
250 | /* | |
251 | * The next two are just to see if we have sane values. | |
252 | * They're only really relevant if we're in Virtual Wire | |
253 | * compatibility mode, but most boxes are anymore. | |
254 | */ | |
255 | reg0 = apic_read(APIC_LVT0); | |
256 | apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0); | |
257 | reg1 = apic_read(APIC_LVT1); | |
258 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
259 | ||
260 | return 1; | |
261 | } | |
262 | ||
263 | void __init sync_Arb_IDs(void) | |
264 | { | |
265 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */ | |
266 | unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
267 | if (ver >= 0x14) /* P4 or higher */ | |
268 | return; | |
269 | ||
270 | /* | |
271 | * Wait for idle. | |
272 | */ | |
273 | apic_wait_icr_idle(); | |
274 | ||
275 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
11a8e778 | 276 | apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG |
1da177e4 LT |
277 | | APIC_DM_INIT); |
278 | } | |
279 | ||
280 | extern void __error_in_apic_c (void); | |
281 | ||
282 | /* | |
283 | * An initial setup of the virtual wire mode. | |
284 | */ | |
285 | void __init init_bsp_APIC(void) | |
286 | { | |
11a8e778 | 287 | unsigned int value; |
1da177e4 LT |
288 | |
289 | /* | |
290 | * Don't do the setup now if we have a SMP BIOS as the | |
291 | * through-I/O-APIC virtual wire mode might be active. | |
292 | */ | |
293 | if (smp_found_config || !cpu_has_apic) | |
294 | return; | |
295 | ||
296 | value = apic_read(APIC_LVR); | |
1da177e4 LT |
297 | |
298 | /* | |
299 | * Do not trust the local APIC being empty at bootup. | |
300 | */ | |
301 | clear_local_APIC(); | |
302 | ||
303 | /* | |
304 | * Enable APIC. | |
305 | */ | |
306 | value = apic_read(APIC_SPIV); | |
307 | value &= ~APIC_VECTOR_MASK; | |
308 | value |= APIC_SPIV_APIC_ENABLED; | |
309 | value |= APIC_SPIV_FOCUS_DISABLED; | |
310 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 311 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
312 | |
313 | /* | |
314 | * Set up the virtual wire mode. | |
315 | */ | |
11a8e778 | 316 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 317 | value = APIC_DM_NMI; |
11a8e778 | 318 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
319 | } |
320 | ||
e6982c67 | 321 | void __cpuinit setup_local_APIC (void) |
1da177e4 | 322 | { |
11a8e778 | 323 | unsigned int value, maxlvt; |
1da177e4 | 324 | |
1da177e4 | 325 | value = apic_read(APIC_LVR); |
1da177e4 LT |
326 | |
327 | if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f) | |
328 | __error_in_apic_c(); | |
329 | ||
330 | /* | |
331 | * Double-check whether this APIC is really registered. | |
332 | * This is meaningless in clustered apic mode, so we skip it. | |
333 | */ | |
334 | if (!apic_id_registered()) | |
335 | BUG(); | |
336 | ||
337 | /* | |
338 | * Intel recommends to set DFR, LDR and TPR before enabling | |
339 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
340 | * document number 292116). So here it goes... | |
341 | */ | |
342 | init_apic_ldr(); | |
343 | ||
344 | /* | |
345 | * Set Task Priority to 'accept all'. We never change this | |
346 | * later on. | |
347 | */ | |
348 | value = apic_read(APIC_TASKPRI); | |
349 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 350 | apic_write(APIC_TASKPRI, value); |
1da177e4 LT |
351 | |
352 | /* | |
353 | * Now that we are all set up, enable the APIC | |
354 | */ | |
355 | value = apic_read(APIC_SPIV); | |
356 | value &= ~APIC_VECTOR_MASK; | |
357 | /* | |
358 | * Enable APIC | |
359 | */ | |
360 | value |= APIC_SPIV_APIC_ENABLED; | |
361 | ||
362 | /* | |
363 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
364 | * certain networking cards. If high frequency interrupts are | |
365 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
366 | * entry is masked/unmasked at a high rate as well then sooner or | |
367 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
368 | * from the device. If focus CPU is disabled then the hang goes | |
369 | * away, oh well :-( | |
370 | * | |
371 | * [ This bug can be reproduced easily with a level-triggered | |
372 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
373 | * BX chipset. ] | |
374 | */ | |
375 | /* | |
376 | * Actually disabling the focus CPU check just makes the hang less | |
377 | * frequent as it makes the interrupt distributon model be more | |
378 | * like LRU than MRU (the short-term load is more even across CPUs). | |
379 | * See also the comment in end_level_ioapic_irq(). --macro | |
380 | */ | |
381 | #if 1 | |
382 | /* Enable focus processor (bit==0) */ | |
383 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
384 | #else | |
385 | /* Disable focus processor (bit==1) */ | |
386 | value |= APIC_SPIV_FOCUS_DISABLED; | |
387 | #endif | |
388 | /* | |
389 | * Set spurious IRQ vector | |
390 | */ | |
391 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 392 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
393 | |
394 | /* | |
395 | * Set up LVT0, LVT1: | |
396 | * | |
397 | * set up through-local-APIC on the BP's LINT0. This is not | |
398 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
399 | * we delegate interrupts to the 8259A. | |
400 | */ | |
401 | /* | |
402 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
403 | */ | |
404 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
405 | if (!smp_processor_id() && (pic_mode || !value)) { | |
406 | value = APIC_DM_EXTINT; | |
407 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id()); | |
408 | } else { | |
409 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
410 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id()); | |
411 | } | |
11a8e778 | 412 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
413 | |
414 | /* | |
415 | * only the BP should see the LINT1 NMI signal, obviously. | |
416 | */ | |
417 | if (!smp_processor_id()) | |
418 | value = APIC_DM_NMI; | |
419 | else | |
420 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
11a8e778 | 421 | apic_write(APIC_LVT1, value); |
1da177e4 | 422 | |
61c11341 | 423 | { |
1da177e4 LT |
424 | unsigned oldvalue; |
425 | maxlvt = get_maxlvt(); | |
1da177e4 LT |
426 | oldvalue = apic_read(APIC_ESR); |
427 | value = ERROR_APIC_VECTOR; // enables sending errors | |
11a8e778 | 428 | apic_write(APIC_LVTERR, value); |
1da177e4 LT |
429 | /* |
430 | * spec says clear errors after enabling vector. | |
431 | */ | |
432 | if (maxlvt > 3) | |
433 | apic_write(APIC_ESR, 0); | |
434 | value = apic_read(APIC_ESR); | |
435 | if (value != oldvalue) | |
436 | apic_printk(APIC_VERBOSE, | |
437 | "ESR value after enabling vector: %08x, after %08x\n", | |
438 | oldvalue, value); | |
1da177e4 LT |
439 | } |
440 | ||
441 | nmi_watchdog_default(); | |
442 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
443 | setup_apic_nmi_watchdog(); | |
444 | apic_pm_activate(); | |
445 | } | |
446 | ||
447 | #ifdef CONFIG_PM | |
448 | ||
449 | static struct { | |
450 | /* 'active' is true if the local APIC was enabled by us and | |
451 | not the BIOS; this signifies that we are also responsible | |
452 | for disabling it before entering apm/acpi suspend */ | |
453 | int active; | |
454 | /* r/w apic fields */ | |
455 | unsigned int apic_id; | |
456 | unsigned int apic_taskpri; | |
457 | unsigned int apic_ldr; | |
458 | unsigned int apic_dfr; | |
459 | unsigned int apic_spiv; | |
460 | unsigned int apic_lvtt; | |
461 | unsigned int apic_lvtpc; | |
462 | unsigned int apic_lvt0; | |
463 | unsigned int apic_lvt1; | |
464 | unsigned int apic_lvterr; | |
465 | unsigned int apic_tmict; | |
466 | unsigned int apic_tdcr; | |
467 | unsigned int apic_thmr; | |
468 | } apic_pm_state; | |
469 | ||
0b9c33a7 | 470 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
471 | { |
472 | unsigned long flags; | |
473 | ||
474 | if (!apic_pm_state.active) | |
475 | return 0; | |
476 | ||
477 | apic_pm_state.apic_id = apic_read(APIC_ID); | |
478 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
479 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
480 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
481 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
482 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
483 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
484 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
485 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
486 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
487 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
488 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
489 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
490 | local_save_flags(flags); | |
491 | local_irq_disable(); | |
492 | disable_local_APIC(); | |
493 | local_irq_restore(flags); | |
494 | return 0; | |
495 | } | |
496 | ||
497 | static int lapic_resume(struct sys_device *dev) | |
498 | { | |
499 | unsigned int l, h; | |
500 | unsigned long flags; | |
501 | ||
502 | if (!apic_pm_state.active) | |
503 | return 0; | |
504 | ||
1da177e4 LT |
505 | local_irq_save(flags); |
506 | rdmsr(MSR_IA32_APICBASE, l, h); | |
507 | l &= ~MSR_IA32_APICBASE_BASE; | |
5b743573 | 508 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; |
1da177e4 LT |
509 | wrmsr(MSR_IA32_APICBASE, l, h); |
510 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
511 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
512 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
513 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
514 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
515 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
516 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
517 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
518 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
519 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
520 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
521 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
522 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
523 | apic_write(APIC_ESR, 0); | |
524 | apic_read(APIC_ESR); | |
525 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
526 | apic_write(APIC_ESR, 0); | |
527 | apic_read(APIC_ESR); | |
528 | local_irq_restore(flags); | |
529 | return 0; | |
530 | } | |
531 | ||
532 | static struct sysdev_class lapic_sysclass = { | |
533 | set_kset_name("lapic"), | |
534 | .resume = lapic_resume, | |
535 | .suspend = lapic_suspend, | |
536 | }; | |
537 | ||
538 | static struct sys_device device_lapic = { | |
539 | .id = 0, | |
540 | .cls = &lapic_sysclass, | |
541 | }; | |
542 | ||
e6982c67 | 543 | static void __cpuinit apic_pm_activate(void) |
1da177e4 LT |
544 | { |
545 | apic_pm_state.active = 1; | |
546 | } | |
547 | ||
548 | static int __init init_lapic_sysfs(void) | |
549 | { | |
550 | int error; | |
551 | if (!cpu_has_apic) | |
552 | return 0; | |
553 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
554 | error = sysdev_class_register(&lapic_sysclass); | |
555 | if (!error) | |
556 | error = sysdev_register(&device_lapic); | |
557 | return error; | |
558 | } | |
559 | device_initcall(init_lapic_sysfs); | |
560 | ||
561 | #else /* CONFIG_PM */ | |
562 | ||
563 | static void apic_pm_activate(void) { } | |
564 | ||
565 | #endif /* CONFIG_PM */ | |
566 | ||
567 | static int __init apic_set_verbosity(char *str) | |
568 | { | |
569 | if (strcmp("debug", str) == 0) | |
570 | apic_verbosity = APIC_DEBUG; | |
571 | else if (strcmp("verbose", str) == 0) | |
572 | apic_verbosity = APIC_VERBOSE; | |
573 | else | |
574 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
575 | " use apic=verbose or apic=debug", str); | |
576 | ||
577 | return 0; | |
578 | } | |
579 | ||
580 | __setup("apic=", apic_set_verbosity); | |
581 | ||
582 | /* | |
583 | * Detect and enable local APICs on non-SMP boards. | |
584 | * Original code written by Keir Fraser. | |
585 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
586 | * not correctly set up (usually the APIC timer won't work etc.) | |
587 | */ | |
588 | ||
589 | static int __init detect_init_APIC (void) | |
590 | { | |
591 | if (!cpu_has_apic) { | |
592 | printk(KERN_INFO "No local APIC present\n"); | |
593 | return -1; | |
594 | } | |
595 | ||
596 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
597 | boot_cpu_id = 0; | |
598 | return 0; | |
599 | } | |
600 | ||
601 | void __init init_apic_mappings(void) | |
602 | { | |
603 | unsigned long apic_phys; | |
604 | ||
605 | /* | |
606 | * If no local APIC can be found then set up a fake all | |
607 | * zeroes page to simulate the local APIC and another | |
608 | * one for the IO-APIC. | |
609 | */ | |
610 | if (!smp_found_config && detect_init_APIC()) { | |
611 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
612 | apic_phys = __pa(apic_phys); | |
613 | } else | |
614 | apic_phys = mp_lapic_addr; | |
615 | ||
616 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
617 | apic_printk(APIC_VERBOSE,"mapped APIC to %16lx (%16lx)\n", APIC_BASE, apic_phys); | |
618 | ||
619 | /* | |
620 | * Fetch the APIC ID of the BSP in case we have a | |
621 | * default configuration (or the MP table is broken). | |
622 | */ | |
1d3fbbf9 | 623 | boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID)); |
1da177e4 LT |
624 | |
625 | #ifdef CONFIG_X86_IO_APIC | |
626 | { | |
627 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
628 | int i; | |
629 | ||
630 | for (i = 0; i < nr_ioapics; i++) { | |
631 | if (smp_found_config) { | |
632 | ioapic_phys = mp_ioapics[i].mpc_apicaddr; | |
633 | } else { | |
634 | ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
635 | ioapic_phys = __pa(ioapic_phys); | |
636 | } | |
637 | set_fixmap_nocache(idx, ioapic_phys); | |
638 | apic_printk(APIC_VERBOSE,"mapped IOAPIC to %016lx (%016lx)\n", | |
639 | __fix_to_virt(idx), ioapic_phys); | |
640 | idx++; | |
641 | } | |
642 | } | |
643 | #endif | |
644 | } | |
645 | ||
646 | /* | |
647 | * This function sets up the local APIC timer, with a timeout of | |
648 | * 'clocks' APIC bus clock. During calibration we actually call | |
649 | * this function twice on the boot CPU, once with a bogus timeout | |
650 | * value, second time for real. The other (noncalibrating) CPUs | |
651 | * call this function only once, with the real, calibrated value. | |
652 | * | |
653 | * We do reads before writes even if unnecessary, to get around the | |
654 | * P5 APIC double write bug. | |
655 | */ | |
656 | ||
657 | #define APIC_DIVISOR 16 | |
658 | ||
659 | static void __setup_APIC_LVTT(unsigned int clocks) | |
660 | { | |
661 | unsigned int lvtt_value, tmp_value, ver; | |
d25bf7e5 | 662 | int cpu = smp_processor_id(); |
1da177e4 LT |
663 | |
664 | ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
665 | lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR; | |
d25bf7e5 VP |
666 | |
667 | if (cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) | |
668 | lvtt_value |= APIC_LVT_MASKED; | |
669 | ||
11a8e778 | 670 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
671 | |
672 | /* | |
673 | * Divide PICLK by 16 | |
674 | */ | |
675 | tmp_value = apic_read(APIC_TDCR); | |
11a8e778 | 676 | apic_write(APIC_TDCR, (tmp_value |
1da177e4 LT |
677 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
678 | | APIC_TDR_DIV_16); | |
679 | ||
11a8e778 | 680 | apic_write(APIC_TMICT, clocks/APIC_DIVISOR); |
1da177e4 LT |
681 | } |
682 | ||
683 | static void setup_APIC_timer(unsigned int clocks) | |
684 | { | |
685 | unsigned long flags; | |
686 | ||
687 | local_irq_save(flags); | |
688 | ||
1da177e4 LT |
689 | /* wait for irq slice */ |
690 | if (vxtime.hpet_address) { | |
691 | int trigger = hpet_readl(HPET_T0_CMP); | |
692 | while (hpet_readl(HPET_COUNTER) >= trigger) | |
693 | /* do nothing */ ; | |
694 | while (hpet_readl(HPET_COUNTER) < trigger) | |
695 | /* do nothing */ ; | |
696 | } else { | |
697 | int c1, c2; | |
698 | outb_p(0x00, 0x43); | |
699 | c2 = inb_p(0x40); | |
700 | c2 |= inb_p(0x40) << 8; | |
11a8e778 | 701 | do { |
1da177e4 LT |
702 | c1 = c2; |
703 | outb_p(0x00, 0x43); | |
704 | c2 = inb_p(0x40); | |
705 | c2 |= inb_p(0x40) << 8; | |
706 | } while (c2 - c1 < 300); | |
707 | } | |
1da177e4 | 708 | __setup_APIC_LVTT(clocks); |
73dea47f AK |
709 | /* Turn off PIT interrupt if we use APIC timer as main timer. |
710 | Only works with the PM timer right now | |
711 | TBD fix it for HPET too. */ | |
712 | if (vxtime.mode == VXTIME_PMTMR && | |
713 | smp_processor_id() == boot_cpu_id && | |
714 | apic_runs_main_timer == 1 && | |
715 | !cpu_isset(boot_cpu_id, timer_interrupt_broadcast_ipi_mask)) { | |
716 | stop_timer_interrupt(); | |
717 | apic_runs_main_timer++; | |
718 | } | |
1da177e4 LT |
719 | local_irq_restore(flags); |
720 | } | |
721 | ||
722 | /* | |
723 | * In this function we calibrate APIC bus clocks to the external | |
724 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
725 | * to calibrate, since some later bootup code depends on getting | |
726 | * the first irq? Ugh. | |
727 | * | |
728 | * We want to do the calibration only once since we | |
729 | * want to have local timer irqs syncron. CPUs connected | |
730 | * by the same APIC bus have the very same bus frequency. | |
731 | * And we want to have irqs off anyways, no accidental | |
732 | * APIC irq that way. | |
733 | */ | |
734 | ||
735 | #define TICK_COUNT 100000000 | |
736 | ||
737 | static int __init calibrate_APIC_clock(void) | |
738 | { | |
739 | int apic, apic_start, tsc, tsc_start; | |
740 | int result; | |
741 | /* | |
742 | * Put whatever arbitrary (but long enough) timeout | |
743 | * value into the APIC clock, we just want to get the | |
744 | * counter running for calibration. | |
745 | */ | |
746 | __setup_APIC_LVTT(1000000000); | |
747 | ||
748 | apic_start = apic_read(APIC_TMCCT); | |
749 | rdtscl(tsc_start); | |
750 | ||
751 | do { | |
752 | apic = apic_read(APIC_TMCCT); | |
753 | rdtscl(tsc); | |
754 | } while ((tsc - tsc_start) < TICK_COUNT && (apic - apic_start) < TICK_COUNT); | |
755 | ||
756 | result = (apic_start - apic) * 1000L * cpu_khz / (tsc - tsc_start); | |
757 | ||
758 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
759 | result / 1000 / 1000, result / 1000 % 1000); | |
760 | ||
761 | return result * APIC_DIVISOR / HZ; | |
762 | } | |
763 | ||
764 | static unsigned int calibration_result; | |
765 | ||
766 | void __init setup_boot_APIC_clock (void) | |
767 | { | |
768 | if (disable_apic_timer) { | |
769 | printk(KERN_INFO "Disabling APIC timer\n"); | |
770 | return; | |
771 | } | |
772 | ||
773 | printk(KERN_INFO "Using local APIC timer interrupts.\n"); | |
774 | using_apic_timer = 1; | |
775 | ||
776 | local_irq_disable(); | |
777 | ||
778 | calibration_result = calibrate_APIC_clock(); | |
779 | /* | |
780 | * Now set up the timer for real. | |
781 | */ | |
782 | setup_APIC_timer(calibration_result); | |
783 | ||
784 | local_irq_enable(); | |
785 | } | |
786 | ||
e6982c67 | 787 | void __cpuinit setup_secondary_APIC_clock(void) |
1da177e4 LT |
788 | { |
789 | local_irq_disable(); /* FIXME: Do we need this? --RR */ | |
790 | setup_APIC_timer(calibration_result); | |
791 | local_irq_enable(); | |
792 | } | |
793 | ||
d25bf7e5 | 794 | void disable_APIC_timer(void) |
1da177e4 LT |
795 | { |
796 | if (using_apic_timer) { | |
797 | unsigned long v; | |
798 | ||
799 | v = apic_read(APIC_LVTT); | |
11a8e778 | 800 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
1da177e4 LT |
801 | } |
802 | } | |
803 | ||
804 | void enable_APIC_timer(void) | |
805 | { | |
d25bf7e5 VP |
806 | int cpu = smp_processor_id(); |
807 | ||
808 | if (using_apic_timer && | |
809 | !cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) { | |
1da177e4 LT |
810 | unsigned long v; |
811 | ||
812 | v = apic_read(APIC_LVTT); | |
11a8e778 | 813 | apic_write(APIC_LVTT, v & ~APIC_LVT_MASKED); |
1da177e4 LT |
814 | } |
815 | } | |
816 | ||
d25bf7e5 VP |
817 | void switch_APIC_timer_to_ipi(void *cpumask) |
818 | { | |
819 | cpumask_t mask = *(cpumask_t *)cpumask; | |
820 | int cpu = smp_processor_id(); | |
821 | ||
822 | if (cpu_isset(cpu, mask) && | |
823 | !cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) { | |
824 | disable_APIC_timer(); | |
825 | cpu_set(cpu, timer_interrupt_broadcast_ipi_mask); | |
826 | } | |
827 | } | |
828 | EXPORT_SYMBOL(switch_APIC_timer_to_ipi); | |
829 | ||
830 | void smp_send_timer_broadcast_ipi(void) | |
831 | { | |
832 | cpumask_t mask; | |
833 | ||
834 | cpus_and(mask, cpu_online_map, timer_interrupt_broadcast_ipi_mask); | |
835 | if (!cpus_empty(mask)) { | |
836 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
837 | } | |
838 | } | |
839 | ||
840 | void switch_ipi_to_APIC_timer(void *cpumask) | |
841 | { | |
842 | cpumask_t mask = *(cpumask_t *)cpumask; | |
843 | int cpu = smp_processor_id(); | |
844 | ||
845 | if (cpu_isset(cpu, mask) && | |
846 | cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) { | |
847 | cpu_clear(cpu, timer_interrupt_broadcast_ipi_mask); | |
848 | enable_APIC_timer(); | |
849 | } | |
850 | } | |
851 | EXPORT_SYMBOL(switch_ipi_to_APIC_timer); | |
852 | ||
1da177e4 LT |
853 | int setup_profiling_timer(unsigned int multiplier) |
854 | { | |
5a07a30c | 855 | return -EINVAL; |
1da177e4 LT |
856 | } |
857 | ||
89b831ef JS |
858 | #ifdef CONFIG_X86_MCE_AMD |
859 | void setup_threshold_lvt(unsigned long lvt_off) | |
860 | { | |
861 | unsigned int v = 0; | |
862 | unsigned long reg = (lvt_off << 4) + 0x500; | |
863 | v |= THRESHOLD_APIC_VECTOR; | |
864 | apic_write(reg, v); | |
865 | } | |
866 | #endif /* CONFIG_X86_MCE_AMD */ | |
867 | ||
1da177e4 LT |
868 | #undef APIC_DIVISOR |
869 | ||
870 | /* | |
871 | * Local timer interrupt handler. It does both profiling and | |
872 | * process statistics/rescheduling. | |
873 | * | |
874 | * We do profiling in every local tick, statistics/rescheduling | |
875 | * happen only every 'profiling multiplier' ticks. The default | |
876 | * multiplier is 1 and it can be changed by writing the new multiplier | |
877 | * value into /proc/profile. | |
878 | */ | |
879 | ||
880 | void smp_local_timer_interrupt(struct pt_regs *regs) | |
881 | { | |
1da177e4 | 882 | profile_tick(CPU_PROFILING, regs); |
1da177e4 | 883 | #ifdef CONFIG_SMP |
5a07a30c | 884 | update_process_times(user_mode(regs)); |
1da177e4 | 885 | #endif |
73dea47f AK |
886 | if (apic_runs_main_timer > 1 && smp_processor_id() == boot_cpu_id) |
887 | main_timer_handler(regs); | |
1da177e4 LT |
888 | /* |
889 | * We take the 'long' return path, and there every subsystem | |
890 | * grabs the appropriate locks (kernel lock/ irq lock). | |
891 | * | |
892 | * we might want to decouple profiling from the 'long path', | |
893 | * and do the profiling totally in assembly. | |
894 | * | |
895 | * Currently this isn't too much of an issue (performance wise), | |
896 | * we can take more than 100K local irqs per second on a 100 MHz P5. | |
897 | */ | |
898 | } | |
899 | ||
900 | /* | |
901 | * Local APIC timer interrupt. This is the most natural way for doing | |
902 | * local interrupts, but local timer interrupts can be emulated by | |
903 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
904 | * | |
905 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
906 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
907 | */ | |
908 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
909 | { | |
910 | /* | |
911 | * the NMI deadlock-detector uses this. | |
912 | */ | |
913 | add_pda(apic_timer_irqs, 1); | |
914 | ||
915 | /* | |
916 | * NOTE! We'd better ACK the irq immediately, | |
917 | * because timer handling can be slow. | |
918 | */ | |
919 | ack_APIC_irq(); | |
920 | /* | |
921 | * update_process_times() expects us to have done irq_enter(). | |
922 | * Besides, if we don't timer interrupts ignore the global | |
923 | * interrupt lock, which is the WrongThing (tm) to do. | |
924 | */ | |
95833c83 | 925 | exit_idle(); |
1da177e4 LT |
926 | irq_enter(); |
927 | smp_local_timer_interrupt(regs); | |
928 | irq_exit(); | |
929 | } | |
930 | ||
931 | /* | |
932 | * oem_force_hpet_timer -- force HPET mode for some boxes. | |
933 | * | |
934 | * Thus far, the major user of this is IBM's Summit2 series: | |
935 | * | |
936 | * Clustered boxes may have unsynced TSC problems if they are | |
937 | * multi-chassis. Use available data to take a good guess. | |
938 | * If in doubt, go HPET. | |
939 | */ | |
396bd50f | 940 | __cpuinit int oem_force_hpet_timer(void) |
1da177e4 LT |
941 | { |
942 | int i, clusters, zeros; | |
943 | unsigned id; | |
944 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); | |
945 | ||
376ec33f | 946 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
947 | |
948 | for (i = 0; i < NR_CPUS; i++) { | |
949 | id = bios_cpu_apicid[i]; | |
950 | if (id != BAD_APICID) | |
951 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
952 | } | |
953 | ||
954 | /* Problem: Partially populated chassis may not have CPUs in some of | |
955 | * the APIC clusters they have been allocated. Only present CPUs have | |
956 | * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since | |
957 | * clusters are allocated sequentially, count zeros only if they are | |
958 | * bounded by ones. | |
959 | */ | |
960 | clusters = 0; | |
961 | zeros = 0; | |
962 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
963 | if (test_bit(i, clustermap)) { | |
964 | clusters += 1 + zeros; | |
965 | zeros = 0; | |
966 | } else | |
967 | ++zeros; | |
968 | } | |
969 | ||
970 | /* | |
971 | * If clusters > 2, then should be multi-chassis. Return 1 for HPET. | |
972 | * Else return 0 to use TSC. | |
973 | * May have to revisit this when multi-core + hyperthreaded CPUs come | |
974 | * out, but AFAIK this will work even for them. | |
975 | */ | |
976 | return (clusters > 2); | |
977 | } | |
978 | ||
979 | /* | |
980 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
981 | */ | |
982 | asmlinkage void smp_spurious_interrupt(void) | |
983 | { | |
984 | unsigned int v; | |
95833c83 | 985 | exit_idle(); |
1da177e4 LT |
986 | irq_enter(); |
987 | /* | |
988 | * Check if this really is a spurious interrupt and ACK it | |
989 | * if it is a vectored one. Just in case... | |
990 | * Spurious interrupts should not be ACKed. | |
991 | */ | |
992 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
993 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
994 | ack_APIC_irq(); | |
995 | ||
996 | #if 0 | |
997 | static unsigned long last_warning; | |
998 | static unsigned long skipped; | |
999 | ||
1000 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
1001 | if (time_before(last_warning+30*HZ,jiffies)) { | |
1002 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, %ld skipped.\n", | |
1003 | smp_processor_id(), skipped); | |
1004 | last_warning = jiffies; | |
1005 | skipped = 0; | |
1006 | } else { | |
1007 | skipped++; | |
1008 | } | |
1009 | #endif | |
1010 | irq_exit(); | |
1011 | } | |
1012 | ||
1013 | /* | |
1014 | * This interrupt should never happen with our APIC/SMP architecture | |
1015 | */ | |
1016 | ||
1017 | asmlinkage void smp_error_interrupt(void) | |
1018 | { | |
1019 | unsigned int v, v1; | |
1020 | ||
95833c83 | 1021 | exit_idle(); |
1da177e4 LT |
1022 | irq_enter(); |
1023 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1024 | v = apic_read(APIC_ESR); | |
1025 | apic_write(APIC_ESR, 0); | |
1026 | v1 = apic_read(APIC_ESR); | |
1027 | ack_APIC_irq(); | |
1028 | atomic_inc(&irq_err_count); | |
1029 | ||
1030 | /* Here is what the APIC error bits mean: | |
1031 | 0: Send CS error | |
1032 | 1: Receive CS error | |
1033 | 2: Send accept error | |
1034 | 3: Receive accept error | |
1035 | 4: Reserved | |
1036 | 5: Send illegal vector | |
1037 | 6: Received illegal vector | |
1038 | 7: Illegal register address | |
1039 | */ | |
1040 | printk (KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1041 | smp_processor_id(), v , v1); | |
1042 | irq_exit(); | |
1043 | } | |
1044 | ||
1045 | int disable_apic; | |
1046 | ||
1047 | /* | |
1048 | * This initializes the IO-APIC and APIC hardware if this is | |
1049 | * a UP kernel. | |
1050 | */ | |
1051 | int __init APIC_init_uniprocessor (void) | |
1052 | { | |
1053 | if (disable_apic) { | |
1054 | printk(KERN_INFO "Apic disabled\n"); | |
1055 | return -1; | |
1056 | } | |
1057 | if (!cpu_has_apic) { | |
1058 | disable_apic = 1; | |
1059 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
1060 | return -1; | |
1061 | } | |
1062 | ||
1063 | verify_local_APIC(); | |
1064 | ||
1065 | connect_bsp_APIC(); | |
1066 | ||
357e11d4 | 1067 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id); |
11a8e778 | 1068 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_id)); |
1da177e4 LT |
1069 | |
1070 | setup_local_APIC(); | |
1071 | ||
1072 | #ifdef CONFIG_X86_IO_APIC | |
1073 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) | |
1074 | setup_IO_APIC(); | |
1075 | else | |
1076 | nr_ioapics = 0; | |
1077 | #endif | |
1078 | setup_boot_APIC_clock(); | |
75152114 | 1079 | check_nmi_watchdog(); |
1da177e4 LT |
1080 | return 0; |
1081 | } | |
1082 | ||
1083 | static __init int setup_disableapic(char *str) | |
1084 | { | |
1085 | disable_apic = 1; | |
1086 | return 0; | |
1087 | } | |
1088 | ||
1089 | static __init int setup_nolapic(char *str) | |
1090 | { | |
1091 | disable_apic = 1; | |
1092 | return 0; | |
1093 | } | |
1094 | ||
1095 | static __init int setup_noapictimer(char *str) | |
1096 | { | |
73dea47f AK |
1097 | if (str[0] != ' ' && str[0] != 0) |
1098 | return -1; | |
1da177e4 LT |
1099 | disable_apic_timer = 1; |
1100 | return 0; | |
1101 | } | |
1102 | ||
73dea47f AK |
1103 | static __init int setup_apicmaintimer(char *str) |
1104 | { | |
1105 | apic_runs_main_timer = 1; | |
1106 | nohpet = 1; | |
1107 | return 0; | |
1108 | } | |
1109 | __setup("apicmaintimer", setup_apicmaintimer); | |
1110 | ||
1111 | static __init int setup_noapicmaintimer(char *str) | |
1112 | { | |
1113 | apic_runs_main_timer = -1; | |
1114 | return 0; | |
1115 | } | |
1116 | __setup("noapicmaintimer", setup_noapicmaintimer); | |
1117 | ||
1da177e4 LT |
1118 | /* dummy parsing: see setup.c */ |
1119 | ||
1120 | __setup("disableapic", setup_disableapic); | |
1121 | __setup("nolapic", setup_nolapic); /* same as disableapic, for compatibility */ | |
1122 | ||
1123 | __setup("noapictimer", setup_noapictimer); | |
1124 | ||
1125 | /* no "lapic" flag - we only use the lapic when the BIOS tells us so. */ |