Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
22 | #include <linux/smp_lock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/mc146818rtc.h> | |
25 | #include <linux/kernel_stat.h> | |
26 | #include <linux/sysdev.h> | |
d25bf7e5 | 27 | #include <linux/module.h> |
1da177e4 LT |
28 | |
29 | #include <asm/atomic.h> | |
30 | #include <asm/smp.h> | |
31 | #include <asm/mtrr.h> | |
32 | #include <asm/mpspec.h> | |
33 | #include <asm/pgalloc.h> | |
34 | #include <asm/mach_apic.h> | |
75152114 | 35 | #include <asm/nmi.h> |
95833c83 | 36 | #include <asm/idle.h> |
73dea47f AK |
37 | #include <asm/proto.h> |
38 | #include <asm/timex.h> | |
1da177e4 LT |
39 | |
40 | int apic_verbosity; | |
73dea47f | 41 | int apic_runs_main_timer; |
0c3749c4 | 42 | int apic_calibrate_pmtmr __initdata; |
1da177e4 LT |
43 | |
44 | int disable_apic_timer __initdata; | |
45 | ||
d25bf7e5 VP |
46 | /* |
47 | * cpu_mask that denotes the CPUs that needs timer interrupt coming in as | |
48 | * IPIs in place of local APIC timers | |
49 | */ | |
50 | static cpumask_t timer_interrupt_broadcast_ipi_mask; | |
51 | ||
1da177e4 | 52 | /* Using APIC to generate smp_local_timer_interrupt? */ |
acae9d32 | 53 | int using_apic_timer __read_mostly = 0; |
1da177e4 | 54 | |
1da177e4 LT |
55 | static void apic_pm_activate(void); |
56 | ||
57 | void enable_NMI_through_LVT0 (void * dummy) | |
58 | { | |
11a8e778 | 59 | unsigned int v; |
1da177e4 | 60 | |
1da177e4 | 61 | v = APIC_DM_NMI; /* unmask and set to NMI */ |
11a8e778 | 62 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
63 | } |
64 | ||
65 | int get_maxlvt(void) | |
66 | { | |
11a8e778 | 67 | unsigned int v, maxlvt; |
1da177e4 LT |
68 | |
69 | v = apic_read(APIC_LVR); | |
1da177e4 LT |
70 | maxlvt = GET_APIC_MAXLVT(v); |
71 | return maxlvt; | |
72 | } | |
73 | ||
3777a959 AK |
74 | /* |
75 | * 'what should we do if we get a hw irq event on an illegal vector'. | |
76 | * each architecture has to answer this themselves. | |
77 | */ | |
78 | void ack_bad_irq(unsigned int irq) | |
79 | { | |
80 | printk("unexpected IRQ trap at vector %02x\n", irq); | |
81 | /* | |
82 | * Currently unexpected vectors happen only on SMP and APIC. | |
83 | * We _must_ ack these because every local APIC has only N | |
84 | * irq slots per priority level, and a 'hanging, unacked' IRQ | |
85 | * holds up an irq slot - in excessive cases (when multiple | |
86 | * unexpected vectors occur) that might lock up the APIC | |
87 | * completely. | |
88 | * But don't ack when the APIC is disabled. -AK | |
89 | */ | |
90 | if (!disable_apic) | |
91 | ack_APIC_irq(); | |
92 | } | |
93 | ||
1da177e4 LT |
94 | void clear_local_APIC(void) |
95 | { | |
96 | int maxlvt; | |
97 | unsigned int v; | |
98 | ||
99 | maxlvt = get_maxlvt(); | |
100 | ||
101 | /* | |
704fc59e | 102 | * Masking an LVT entry can trigger a local APIC error |
1da177e4 LT |
103 | * if the vector is zero. Mask LVTERR first to prevent this. |
104 | */ | |
105 | if (maxlvt >= 3) { | |
106 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
11a8e778 | 107 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
1da177e4 LT |
108 | } |
109 | /* | |
110 | * Careful: we have to set masks only first to deassert | |
111 | * any level-triggered sources. | |
112 | */ | |
113 | v = apic_read(APIC_LVTT); | |
11a8e778 | 114 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
1da177e4 | 115 | v = apic_read(APIC_LVT0); |
11a8e778 | 116 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 | 117 | v = apic_read(APIC_LVT1); |
11a8e778 | 118 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); |
1da177e4 LT |
119 | if (maxlvt >= 4) { |
120 | v = apic_read(APIC_LVTPC); | |
11a8e778 | 121 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); |
1da177e4 LT |
122 | } |
123 | ||
124 | /* | |
125 | * Clean APIC state for other OSs: | |
126 | */ | |
11a8e778 AK |
127 | apic_write(APIC_LVTT, APIC_LVT_MASKED); |
128 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
129 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
1da177e4 | 130 | if (maxlvt >= 3) |
11a8e778 | 131 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); |
1da177e4 | 132 | if (maxlvt >= 4) |
11a8e778 | 133 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); |
1da177e4 | 134 | v = GET_APIC_VERSION(apic_read(APIC_LVR)); |
5a40b7c2 AK |
135 | apic_write(APIC_ESR, 0); |
136 | apic_read(APIC_ESR); | |
1da177e4 LT |
137 | } |
138 | ||
208fb931 | 139 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 140 | { |
a8fcf1a2 AK |
141 | /* Go back to Virtual Wire compatibility mode */ |
142 | unsigned long value; | |
208fb931 | 143 | |
a8fcf1a2 AK |
144 | /* For the spurious interrupt use vector F, and enable it */ |
145 | value = apic_read(APIC_SPIV); | |
146 | value &= ~APIC_VECTOR_MASK; | |
147 | value |= APIC_SPIV_APIC_ENABLED; | |
148 | value |= 0xf; | |
149 | apic_write(APIC_SPIV, value); | |
150 | ||
151 | if (!virt_wire_setup) { | |
152 | /* For LVT0 make it edge triggered, active high, external and enabled */ | |
153 | value = apic_read(APIC_LVT0); | |
154 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
208fb931 | 155 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | |
a8fcf1a2 | 156 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED ); |
208fb931 | 157 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
a8fcf1a2 AK |
158 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); |
159 | apic_write(APIC_LVT0, value); | |
160 | } else { | |
161 | /* Disable LVT0 */ | |
162 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
208fb931 | 163 | } |
a8fcf1a2 AK |
164 | |
165 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ | |
166 | value = apic_read(APIC_LVT1); | |
167 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
168 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
169 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
170 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
171 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
172 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
173 | } |
174 | ||
175 | void disable_local_APIC(void) | |
176 | { | |
177 | unsigned int value; | |
178 | ||
179 | clear_local_APIC(); | |
180 | ||
181 | /* | |
182 | * Disable APIC (implies clearing of registers | |
183 | * for 82489DX!). | |
184 | */ | |
185 | value = apic_read(APIC_SPIV); | |
186 | value &= ~APIC_SPIV_APIC_ENABLED; | |
11a8e778 | 187 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
188 | } |
189 | ||
190 | /* | |
191 | * This is to verify that we're looking at a real local APIC. | |
192 | * Check these against your board if the CPUs aren't getting | |
193 | * started for no apparent reason. | |
194 | */ | |
195 | int __init verify_local_APIC(void) | |
196 | { | |
197 | unsigned int reg0, reg1; | |
198 | ||
199 | /* | |
200 | * The version register is read-only in a real APIC. | |
201 | */ | |
202 | reg0 = apic_read(APIC_LVR); | |
203 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
204 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
205 | reg1 = apic_read(APIC_LVR); | |
206 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
207 | ||
208 | /* | |
209 | * The two version reads above should print the same | |
210 | * numbers. If the second one is different, then we | |
211 | * poke at a non-APIC. | |
212 | */ | |
213 | if (reg1 != reg0) | |
214 | return 0; | |
215 | ||
216 | /* | |
217 | * Check if the version looks reasonably. | |
218 | */ | |
219 | reg1 = GET_APIC_VERSION(reg0); | |
220 | if (reg1 == 0x00 || reg1 == 0xff) | |
221 | return 0; | |
222 | reg1 = get_maxlvt(); | |
223 | if (reg1 < 0x02 || reg1 == 0xff) | |
224 | return 0; | |
225 | ||
226 | /* | |
227 | * The ID register is read/write in a real APIC. | |
228 | */ | |
229 | reg0 = apic_read(APIC_ID); | |
230 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
231 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
232 | reg1 = apic_read(APIC_ID); | |
233 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); | |
234 | apic_write(APIC_ID, reg0); | |
235 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
236 | return 0; | |
237 | ||
238 | /* | |
239 | * The next two are just to see if we have sane values. | |
240 | * They're only really relevant if we're in Virtual Wire | |
241 | * compatibility mode, but most boxes are anymore. | |
242 | */ | |
243 | reg0 = apic_read(APIC_LVT0); | |
244 | apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0); | |
245 | reg1 = apic_read(APIC_LVT1); | |
246 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
247 | ||
248 | return 1; | |
249 | } | |
250 | ||
251 | void __init sync_Arb_IDs(void) | |
252 | { | |
253 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */ | |
254 | unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
255 | if (ver >= 0x14) /* P4 or higher */ | |
256 | return; | |
257 | ||
258 | /* | |
259 | * Wait for idle. | |
260 | */ | |
261 | apic_wait_icr_idle(); | |
262 | ||
263 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
11a8e778 | 264 | apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG |
1da177e4 LT |
265 | | APIC_DM_INIT); |
266 | } | |
267 | ||
268 | extern void __error_in_apic_c (void); | |
269 | ||
270 | /* | |
271 | * An initial setup of the virtual wire mode. | |
272 | */ | |
273 | void __init init_bsp_APIC(void) | |
274 | { | |
11a8e778 | 275 | unsigned int value; |
1da177e4 LT |
276 | |
277 | /* | |
278 | * Don't do the setup now if we have a SMP BIOS as the | |
279 | * through-I/O-APIC virtual wire mode might be active. | |
280 | */ | |
281 | if (smp_found_config || !cpu_has_apic) | |
282 | return; | |
283 | ||
284 | value = apic_read(APIC_LVR); | |
1da177e4 LT |
285 | |
286 | /* | |
287 | * Do not trust the local APIC being empty at bootup. | |
288 | */ | |
289 | clear_local_APIC(); | |
290 | ||
291 | /* | |
292 | * Enable APIC. | |
293 | */ | |
294 | value = apic_read(APIC_SPIV); | |
295 | value &= ~APIC_VECTOR_MASK; | |
296 | value |= APIC_SPIV_APIC_ENABLED; | |
297 | value |= APIC_SPIV_FOCUS_DISABLED; | |
298 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 299 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
300 | |
301 | /* | |
302 | * Set up the virtual wire mode. | |
303 | */ | |
11a8e778 | 304 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 305 | value = APIC_DM_NMI; |
11a8e778 | 306 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
307 | } |
308 | ||
e6982c67 | 309 | void __cpuinit setup_local_APIC (void) |
1da177e4 | 310 | { |
11a8e778 | 311 | unsigned int value, maxlvt; |
da7ed9f9 | 312 | int i, j; |
1da177e4 | 313 | |
1da177e4 | 314 | value = apic_read(APIC_LVR); |
1da177e4 LT |
315 | |
316 | if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f) | |
317 | __error_in_apic_c(); | |
318 | ||
319 | /* | |
320 | * Double-check whether this APIC is really registered. | |
321 | * This is meaningless in clustered apic mode, so we skip it. | |
322 | */ | |
323 | if (!apic_id_registered()) | |
324 | BUG(); | |
325 | ||
326 | /* | |
327 | * Intel recommends to set DFR, LDR and TPR before enabling | |
328 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
329 | * document number 292116). So here it goes... | |
330 | */ | |
331 | init_apic_ldr(); | |
332 | ||
333 | /* | |
334 | * Set Task Priority to 'accept all'. We never change this | |
335 | * later on. | |
336 | */ | |
337 | value = apic_read(APIC_TASKPRI); | |
338 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 339 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 340 | |
da7ed9f9 VG |
341 | /* |
342 | * After a crash, we no longer service the interrupts and a pending | |
343 | * interrupt from previous kernel might still have ISR bit set. | |
344 | * | |
345 | * Most probably by now CPU has serviced that pending interrupt and | |
346 | * it might not have done the ack_APIC_irq() because it thought, | |
347 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
348 | * does not clear the ISR bit and cpu thinks it has already serivced | |
349 | * the interrupt. Hence a vector might get locked. It was noticed | |
350 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
351 | */ | |
352 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
353 | value = apic_read(APIC_ISR + i*0x10); | |
354 | for (j = 31; j >= 0; j--) { | |
355 | if (value & (1<<j)) | |
356 | ack_APIC_irq(); | |
357 | } | |
358 | } | |
359 | ||
1da177e4 LT |
360 | /* |
361 | * Now that we are all set up, enable the APIC | |
362 | */ | |
363 | value = apic_read(APIC_SPIV); | |
364 | value &= ~APIC_VECTOR_MASK; | |
365 | /* | |
366 | * Enable APIC | |
367 | */ | |
368 | value |= APIC_SPIV_APIC_ENABLED; | |
369 | ||
3f14c746 AK |
370 | /* We always use processor focus */ |
371 | ||
1da177e4 LT |
372 | /* |
373 | * Set spurious IRQ vector | |
374 | */ | |
375 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 376 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
377 | |
378 | /* | |
379 | * Set up LVT0, LVT1: | |
380 | * | |
381 | * set up through-local-APIC on the BP's LINT0. This is not | |
382 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
383 | * we delegate interrupts to the 8259A. | |
384 | */ | |
385 | /* | |
386 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
387 | */ | |
388 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
a8fcf1a2 | 389 | if (!smp_processor_id() && !value) { |
1da177e4 LT |
390 | value = APIC_DM_EXTINT; |
391 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id()); | |
392 | } else { | |
393 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
394 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id()); | |
395 | } | |
11a8e778 | 396 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
397 | |
398 | /* | |
399 | * only the BP should see the LINT1 NMI signal, obviously. | |
400 | */ | |
401 | if (!smp_processor_id()) | |
402 | value = APIC_DM_NMI; | |
403 | else | |
404 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
11a8e778 | 405 | apic_write(APIC_LVT1, value); |
1da177e4 | 406 | |
61c11341 | 407 | { |
1da177e4 LT |
408 | unsigned oldvalue; |
409 | maxlvt = get_maxlvt(); | |
1da177e4 LT |
410 | oldvalue = apic_read(APIC_ESR); |
411 | value = ERROR_APIC_VECTOR; // enables sending errors | |
11a8e778 | 412 | apic_write(APIC_LVTERR, value); |
1da177e4 LT |
413 | /* |
414 | * spec says clear errors after enabling vector. | |
415 | */ | |
416 | if (maxlvt > 3) | |
417 | apic_write(APIC_ESR, 0); | |
418 | value = apic_read(APIC_ESR); | |
419 | if (value != oldvalue) | |
420 | apic_printk(APIC_VERBOSE, | |
421 | "ESR value after enabling vector: %08x, after %08x\n", | |
422 | oldvalue, value); | |
1da177e4 LT |
423 | } |
424 | ||
425 | nmi_watchdog_default(); | |
f2802e7f | 426 | setup_apic_nmi_watchdog(NULL); |
1da177e4 LT |
427 | apic_pm_activate(); |
428 | } | |
429 | ||
430 | #ifdef CONFIG_PM | |
431 | ||
432 | static struct { | |
433 | /* 'active' is true if the local APIC was enabled by us and | |
434 | not the BIOS; this signifies that we are also responsible | |
435 | for disabling it before entering apm/acpi suspend */ | |
436 | int active; | |
437 | /* r/w apic fields */ | |
438 | unsigned int apic_id; | |
439 | unsigned int apic_taskpri; | |
440 | unsigned int apic_ldr; | |
441 | unsigned int apic_dfr; | |
442 | unsigned int apic_spiv; | |
443 | unsigned int apic_lvtt; | |
444 | unsigned int apic_lvtpc; | |
445 | unsigned int apic_lvt0; | |
446 | unsigned int apic_lvt1; | |
447 | unsigned int apic_lvterr; | |
448 | unsigned int apic_tmict; | |
449 | unsigned int apic_tdcr; | |
450 | unsigned int apic_thmr; | |
451 | } apic_pm_state; | |
452 | ||
0b9c33a7 | 453 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
454 | { |
455 | unsigned long flags; | |
456 | ||
457 | if (!apic_pm_state.active) | |
458 | return 0; | |
459 | ||
460 | apic_pm_state.apic_id = apic_read(APIC_ID); | |
461 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
462 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
463 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
464 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
465 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
466 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
467 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
468 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
469 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
470 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
471 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
472 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
473 | local_save_flags(flags); | |
474 | local_irq_disable(); | |
475 | disable_local_APIC(); | |
476 | local_irq_restore(flags); | |
477 | return 0; | |
478 | } | |
479 | ||
480 | static int lapic_resume(struct sys_device *dev) | |
481 | { | |
482 | unsigned int l, h; | |
483 | unsigned long flags; | |
484 | ||
485 | if (!apic_pm_state.active) | |
486 | return 0; | |
487 | ||
1da177e4 LT |
488 | local_irq_save(flags); |
489 | rdmsr(MSR_IA32_APICBASE, l, h); | |
490 | l &= ~MSR_IA32_APICBASE_BASE; | |
5b743573 | 491 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; |
1da177e4 LT |
492 | wrmsr(MSR_IA32_APICBASE, l, h); |
493 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
494 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
495 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
496 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
497 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
498 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
499 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
500 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
501 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
502 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
503 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
504 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
505 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
506 | apic_write(APIC_ESR, 0); | |
507 | apic_read(APIC_ESR); | |
508 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
509 | apic_write(APIC_ESR, 0); | |
510 | apic_read(APIC_ESR); | |
511 | local_irq_restore(flags); | |
512 | return 0; | |
513 | } | |
514 | ||
515 | static struct sysdev_class lapic_sysclass = { | |
516 | set_kset_name("lapic"), | |
517 | .resume = lapic_resume, | |
518 | .suspend = lapic_suspend, | |
519 | }; | |
520 | ||
521 | static struct sys_device device_lapic = { | |
522 | .id = 0, | |
523 | .cls = &lapic_sysclass, | |
524 | }; | |
525 | ||
e6982c67 | 526 | static void __cpuinit apic_pm_activate(void) |
1da177e4 LT |
527 | { |
528 | apic_pm_state.active = 1; | |
529 | } | |
530 | ||
531 | static int __init init_lapic_sysfs(void) | |
532 | { | |
533 | int error; | |
534 | if (!cpu_has_apic) | |
535 | return 0; | |
536 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
537 | error = sysdev_class_register(&lapic_sysclass); | |
538 | if (!error) | |
539 | error = sysdev_register(&device_lapic); | |
540 | return error; | |
541 | } | |
542 | device_initcall(init_lapic_sysfs); | |
543 | ||
544 | #else /* CONFIG_PM */ | |
545 | ||
546 | static void apic_pm_activate(void) { } | |
547 | ||
548 | #endif /* CONFIG_PM */ | |
549 | ||
550 | static int __init apic_set_verbosity(char *str) | |
551 | { | |
552 | if (strcmp("debug", str) == 0) | |
553 | apic_verbosity = APIC_DEBUG; | |
554 | else if (strcmp("verbose", str) == 0) | |
555 | apic_verbosity = APIC_VERBOSE; | |
556 | else | |
557 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
558 | " use apic=verbose or apic=debug", str); | |
559 | ||
9b41046c | 560 | return 1; |
1da177e4 LT |
561 | } |
562 | ||
563 | __setup("apic=", apic_set_verbosity); | |
564 | ||
565 | /* | |
566 | * Detect and enable local APICs on non-SMP boards. | |
567 | * Original code written by Keir Fraser. | |
568 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
569 | * not correctly set up (usually the APIC timer won't work etc.) | |
570 | */ | |
571 | ||
572 | static int __init detect_init_APIC (void) | |
573 | { | |
574 | if (!cpu_has_apic) { | |
575 | printk(KERN_INFO "No local APIC present\n"); | |
576 | return -1; | |
577 | } | |
578 | ||
579 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
580 | boot_cpu_id = 0; | |
581 | return 0; | |
582 | } | |
583 | ||
584 | void __init init_apic_mappings(void) | |
585 | { | |
586 | unsigned long apic_phys; | |
587 | ||
588 | /* | |
589 | * If no local APIC can be found then set up a fake all | |
590 | * zeroes page to simulate the local APIC and another | |
591 | * one for the IO-APIC. | |
592 | */ | |
593 | if (!smp_found_config && detect_init_APIC()) { | |
594 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
595 | apic_phys = __pa(apic_phys); | |
596 | } else | |
597 | apic_phys = mp_lapic_addr; | |
598 | ||
599 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
600 | apic_printk(APIC_VERBOSE,"mapped APIC to %16lx (%16lx)\n", APIC_BASE, apic_phys); | |
601 | ||
602 | /* | |
603 | * Fetch the APIC ID of the BSP in case we have a | |
604 | * default configuration (or the MP table is broken). | |
605 | */ | |
1d3fbbf9 | 606 | boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID)); |
1da177e4 | 607 | |
1da177e4 LT |
608 | { |
609 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
610 | int i; | |
611 | ||
612 | for (i = 0; i < nr_ioapics; i++) { | |
613 | if (smp_found_config) { | |
614 | ioapic_phys = mp_ioapics[i].mpc_apicaddr; | |
615 | } else { | |
616 | ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
617 | ioapic_phys = __pa(ioapic_phys); | |
618 | } | |
619 | set_fixmap_nocache(idx, ioapic_phys); | |
620 | apic_printk(APIC_VERBOSE,"mapped IOAPIC to %016lx (%016lx)\n", | |
621 | __fix_to_virt(idx), ioapic_phys); | |
622 | idx++; | |
623 | } | |
624 | } | |
1da177e4 LT |
625 | } |
626 | ||
627 | /* | |
628 | * This function sets up the local APIC timer, with a timeout of | |
629 | * 'clocks' APIC bus clock. During calibration we actually call | |
630 | * this function twice on the boot CPU, once with a bogus timeout | |
631 | * value, second time for real. The other (noncalibrating) CPUs | |
632 | * call this function only once, with the real, calibrated value. | |
633 | * | |
634 | * We do reads before writes even if unnecessary, to get around the | |
635 | * P5 APIC double write bug. | |
636 | */ | |
637 | ||
638 | #define APIC_DIVISOR 16 | |
639 | ||
640 | static void __setup_APIC_LVTT(unsigned int clocks) | |
641 | { | |
642 | unsigned int lvtt_value, tmp_value, ver; | |
d25bf7e5 | 643 | int cpu = smp_processor_id(); |
1da177e4 LT |
644 | |
645 | ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
646 | lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR; | |
d25bf7e5 VP |
647 | |
648 | if (cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) | |
649 | lvtt_value |= APIC_LVT_MASKED; | |
650 | ||
11a8e778 | 651 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
652 | |
653 | /* | |
654 | * Divide PICLK by 16 | |
655 | */ | |
656 | tmp_value = apic_read(APIC_TDCR); | |
11a8e778 | 657 | apic_write(APIC_TDCR, (tmp_value |
1da177e4 LT |
658 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
659 | | APIC_TDR_DIV_16); | |
660 | ||
11a8e778 | 661 | apic_write(APIC_TMICT, clocks/APIC_DIVISOR); |
1da177e4 LT |
662 | } |
663 | ||
664 | static void setup_APIC_timer(unsigned int clocks) | |
665 | { | |
666 | unsigned long flags; | |
667 | ||
668 | local_irq_save(flags); | |
669 | ||
1da177e4 | 670 | /* wait for irq slice */ |
33042a9f | 671 | if (vxtime.hpet_address && hpet_use_timer) { |
1da177e4 LT |
672 | int trigger = hpet_readl(HPET_T0_CMP); |
673 | while (hpet_readl(HPET_COUNTER) >= trigger) | |
674 | /* do nothing */ ; | |
675 | while (hpet_readl(HPET_COUNTER) < trigger) | |
676 | /* do nothing */ ; | |
677 | } else { | |
678 | int c1, c2; | |
679 | outb_p(0x00, 0x43); | |
680 | c2 = inb_p(0x40); | |
681 | c2 |= inb_p(0x40) << 8; | |
11a8e778 | 682 | do { |
1da177e4 LT |
683 | c1 = c2; |
684 | outb_p(0x00, 0x43); | |
685 | c2 = inb_p(0x40); | |
686 | c2 |= inb_p(0x40) << 8; | |
687 | } while (c2 - c1 < 300); | |
688 | } | |
1da177e4 | 689 | __setup_APIC_LVTT(clocks); |
73dea47f AK |
690 | /* Turn off PIT interrupt if we use APIC timer as main timer. |
691 | Only works with the PM timer right now | |
692 | TBD fix it for HPET too. */ | |
693 | if (vxtime.mode == VXTIME_PMTMR && | |
694 | smp_processor_id() == boot_cpu_id && | |
695 | apic_runs_main_timer == 1 && | |
696 | !cpu_isset(boot_cpu_id, timer_interrupt_broadcast_ipi_mask)) { | |
697 | stop_timer_interrupt(); | |
698 | apic_runs_main_timer++; | |
699 | } | |
1da177e4 LT |
700 | local_irq_restore(flags); |
701 | } | |
702 | ||
703 | /* | |
704 | * In this function we calibrate APIC bus clocks to the external | |
705 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
706 | * to calibrate, since some later bootup code depends on getting | |
707 | * the first irq? Ugh. | |
708 | * | |
709 | * We want to do the calibration only once since we | |
710 | * want to have local timer irqs syncron. CPUs connected | |
711 | * by the same APIC bus have the very same bus frequency. | |
712 | * And we want to have irqs off anyways, no accidental | |
713 | * APIC irq that way. | |
714 | */ | |
715 | ||
716 | #define TICK_COUNT 100000000 | |
717 | ||
718 | static int __init calibrate_APIC_clock(void) | |
719 | { | |
720 | int apic, apic_start, tsc, tsc_start; | |
721 | int result; | |
722 | /* | |
723 | * Put whatever arbitrary (but long enough) timeout | |
724 | * value into the APIC clock, we just want to get the | |
725 | * counter running for calibration. | |
726 | */ | |
727 | __setup_APIC_LVTT(1000000000); | |
728 | ||
729 | apic_start = apic_read(APIC_TMCCT); | |
0c3749c4 AK |
730 | #ifdef CONFIG_X86_PM_TIMER |
731 | if (apic_calibrate_pmtmr && pmtmr_ioport) { | |
732 | pmtimer_wait(5000); /* 5ms wait */ | |
1da177e4 | 733 | apic = apic_read(APIC_TMCCT); |
0c3749c4 AK |
734 | result = (apic_start - apic) * 1000L / 5; |
735 | } else | |
736 | #endif | |
737 | { | |
738 | rdtscl(tsc_start); | |
739 | ||
740 | do { | |
741 | apic = apic_read(APIC_TMCCT); | |
742 | rdtscl(tsc); | |
743 | } while ((tsc - tsc_start) < TICK_COUNT && | |
744 | (apic - apic_start) < TICK_COUNT); | |
745 | ||
746 | result = (apic_start - apic) * 1000L * cpu_khz / | |
747 | (tsc - tsc_start); | |
748 | } | |
749 | printk("result %d\n", result); | |
1da177e4 | 750 | |
1da177e4 LT |
751 | |
752 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
753 | result / 1000 / 1000, result / 1000 % 1000); | |
754 | ||
755 | return result * APIC_DIVISOR / HZ; | |
756 | } | |
757 | ||
758 | static unsigned int calibration_result; | |
759 | ||
760 | void __init setup_boot_APIC_clock (void) | |
761 | { | |
762 | if (disable_apic_timer) { | |
763 | printk(KERN_INFO "Disabling APIC timer\n"); | |
764 | return; | |
765 | } | |
766 | ||
767 | printk(KERN_INFO "Using local APIC timer interrupts.\n"); | |
768 | using_apic_timer = 1; | |
769 | ||
770 | local_irq_disable(); | |
771 | ||
772 | calibration_result = calibrate_APIC_clock(); | |
773 | /* | |
774 | * Now set up the timer for real. | |
775 | */ | |
776 | setup_APIC_timer(calibration_result); | |
777 | ||
778 | local_irq_enable(); | |
779 | } | |
780 | ||
e6982c67 | 781 | void __cpuinit setup_secondary_APIC_clock(void) |
1da177e4 LT |
782 | { |
783 | local_irq_disable(); /* FIXME: Do we need this? --RR */ | |
784 | setup_APIC_timer(calibration_result); | |
785 | local_irq_enable(); | |
786 | } | |
787 | ||
d25bf7e5 | 788 | void disable_APIC_timer(void) |
1da177e4 LT |
789 | { |
790 | if (using_apic_timer) { | |
791 | unsigned long v; | |
792 | ||
793 | v = apic_read(APIC_LVTT); | |
704fc59e SS |
794 | /* |
795 | * When an illegal vector value (0-15) is written to an LVT | |
796 | * entry and delivery mode is Fixed, the APIC may signal an | |
797 | * illegal vector error, with out regard to whether the mask | |
798 | * bit is set or whether an interrupt is actually seen on input. | |
799 | * | |
800 | * Boot sequence might call this function when the LVTT has | |
801 | * '0' vector value. So make sure vector field is set to | |
802 | * valid value. | |
803 | */ | |
804 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
805 | apic_write(APIC_LVTT, v); | |
1da177e4 LT |
806 | } |
807 | } | |
808 | ||
809 | void enable_APIC_timer(void) | |
810 | { | |
d25bf7e5 VP |
811 | int cpu = smp_processor_id(); |
812 | ||
813 | if (using_apic_timer && | |
814 | !cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) { | |
1da177e4 LT |
815 | unsigned long v; |
816 | ||
817 | v = apic_read(APIC_LVTT); | |
11a8e778 | 818 | apic_write(APIC_LVTT, v & ~APIC_LVT_MASKED); |
1da177e4 LT |
819 | } |
820 | } | |
821 | ||
d25bf7e5 VP |
822 | void switch_APIC_timer_to_ipi(void *cpumask) |
823 | { | |
824 | cpumask_t mask = *(cpumask_t *)cpumask; | |
825 | int cpu = smp_processor_id(); | |
826 | ||
827 | if (cpu_isset(cpu, mask) && | |
828 | !cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) { | |
829 | disable_APIC_timer(); | |
830 | cpu_set(cpu, timer_interrupt_broadcast_ipi_mask); | |
831 | } | |
832 | } | |
833 | EXPORT_SYMBOL(switch_APIC_timer_to_ipi); | |
834 | ||
835 | void smp_send_timer_broadcast_ipi(void) | |
836 | { | |
837 | cpumask_t mask; | |
838 | ||
839 | cpus_and(mask, cpu_online_map, timer_interrupt_broadcast_ipi_mask); | |
840 | if (!cpus_empty(mask)) { | |
841 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
842 | } | |
843 | } | |
844 | ||
845 | void switch_ipi_to_APIC_timer(void *cpumask) | |
846 | { | |
847 | cpumask_t mask = *(cpumask_t *)cpumask; | |
848 | int cpu = smp_processor_id(); | |
849 | ||
850 | if (cpu_isset(cpu, mask) && | |
851 | cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) { | |
852 | cpu_clear(cpu, timer_interrupt_broadcast_ipi_mask); | |
853 | enable_APIC_timer(); | |
854 | } | |
855 | } | |
856 | EXPORT_SYMBOL(switch_ipi_to_APIC_timer); | |
857 | ||
1da177e4 LT |
858 | int setup_profiling_timer(unsigned int multiplier) |
859 | { | |
5a07a30c | 860 | return -EINVAL; |
1da177e4 LT |
861 | } |
862 | ||
17fc14ff JS |
863 | void setup_APIC_extened_lvt(unsigned char lvt_off, unsigned char vector, |
864 | unsigned char msg_type, unsigned char mask) | |
89b831ef | 865 | { |
17fc14ff JS |
866 | unsigned long reg = (lvt_off << 4) + K8_APIC_EXT_LVT_BASE; |
867 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; | |
89b831ef JS |
868 | apic_write(reg, v); |
869 | } | |
89b831ef | 870 | |
1da177e4 LT |
871 | #undef APIC_DIVISOR |
872 | ||
873 | /* | |
874 | * Local timer interrupt handler. It does both profiling and | |
875 | * process statistics/rescheduling. | |
876 | * | |
877 | * We do profiling in every local tick, statistics/rescheduling | |
878 | * happen only every 'profiling multiplier' ticks. The default | |
879 | * multiplier is 1 and it can be changed by writing the new multiplier | |
880 | * value into /proc/profile. | |
881 | */ | |
882 | ||
883 | void smp_local_timer_interrupt(struct pt_regs *regs) | |
884 | { | |
1da177e4 | 885 | profile_tick(CPU_PROFILING, regs); |
1da177e4 | 886 | #ifdef CONFIG_SMP |
5a07a30c | 887 | update_process_times(user_mode(regs)); |
1da177e4 | 888 | #endif |
73dea47f AK |
889 | if (apic_runs_main_timer > 1 && smp_processor_id() == boot_cpu_id) |
890 | main_timer_handler(regs); | |
1da177e4 LT |
891 | /* |
892 | * We take the 'long' return path, and there every subsystem | |
893 | * grabs the appropriate locks (kernel lock/ irq lock). | |
894 | * | |
d5d9ca6d | 895 | * We might want to decouple profiling from the 'long path', |
1da177e4 LT |
896 | * and do the profiling totally in assembly. |
897 | * | |
898 | * Currently this isn't too much of an issue (performance wise), | |
899 | * we can take more than 100K local irqs per second on a 100 MHz P5. | |
900 | */ | |
901 | } | |
902 | ||
903 | /* | |
904 | * Local APIC timer interrupt. This is the most natural way for doing | |
905 | * local interrupts, but local timer interrupts can be emulated by | |
906 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
907 | * | |
908 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
909 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
910 | */ | |
911 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
912 | { | |
913 | /* | |
914 | * the NMI deadlock-detector uses this. | |
915 | */ | |
916 | add_pda(apic_timer_irqs, 1); | |
917 | ||
918 | /* | |
919 | * NOTE! We'd better ACK the irq immediately, | |
920 | * because timer handling can be slow. | |
921 | */ | |
922 | ack_APIC_irq(); | |
923 | /* | |
924 | * update_process_times() expects us to have done irq_enter(). | |
925 | * Besides, if we don't timer interrupts ignore the global | |
926 | * interrupt lock, which is the WrongThing (tm) to do. | |
927 | */ | |
95833c83 | 928 | exit_idle(); |
1da177e4 LT |
929 | irq_enter(); |
930 | smp_local_timer_interrupt(regs); | |
931 | irq_exit(); | |
932 | } | |
933 | ||
934 | /* | |
f8bf3c65 | 935 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
936 | * |
937 | * Thus far, the major user of this is IBM's Summit2 series: | |
938 | * | |
637029c6 | 939 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
940 | * multi-chassis. Use available data to take a good guess. |
941 | * If in doubt, go HPET. | |
942 | */ | |
f8bf3c65 | 943 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
944 | { |
945 | int i, clusters, zeros; | |
946 | unsigned id; | |
947 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); | |
948 | ||
376ec33f | 949 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
950 | |
951 | for (i = 0; i < NR_CPUS; i++) { | |
952 | id = bios_cpu_apicid[i]; | |
953 | if (id != BAD_APICID) | |
954 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
955 | } | |
956 | ||
957 | /* Problem: Partially populated chassis may not have CPUs in some of | |
958 | * the APIC clusters they have been allocated. Only present CPUs have | |
959 | * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since | |
960 | * clusters are allocated sequentially, count zeros only if they are | |
961 | * bounded by ones. | |
962 | */ | |
963 | clusters = 0; | |
964 | zeros = 0; | |
965 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
966 | if (test_bit(i, clustermap)) { | |
967 | clusters += 1 + zeros; | |
968 | zeros = 0; | |
969 | } else | |
970 | ++zeros; | |
971 | } | |
972 | ||
973 | /* | |
f8bf3c65 | 974 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
975 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
976 | * out, but AFAIK this will work even for them. | |
977 | */ | |
978 | return (clusters > 2); | |
979 | } | |
980 | ||
981 | /* | |
982 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
983 | */ | |
984 | asmlinkage void smp_spurious_interrupt(void) | |
985 | { | |
986 | unsigned int v; | |
95833c83 | 987 | exit_idle(); |
1da177e4 LT |
988 | irq_enter(); |
989 | /* | |
990 | * Check if this really is a spurious interrupt and ACK it | |
991 | * if it is a vectored one. Just in case... | |
992 | * Spurious interrupts should not be ACKed. | |
993 | */ | |
994 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
995 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
996 | ack_APIC_irq(); | |
997 | ||
998 | #if 0 | |
999 | static unsigned long last_warning; | |
1000 | static unsigned long skipped; | |
1001 | ||
1002 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
1003 | if (time_before(last_warning+30*HZ,jiffies)) { | |
1004 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, %ld skipped.\n", | |
1005 | smp_processor_id(), skipped); | |
1006 | last_warning = jiffies; | |
1007 | skipped = 0; | |
1008 | } else { | |
1009 | skipped++; | |
1010 | } | |
1011 | #endif | |
1012 | irq_exit(); | |
1013 | } | |
1014 | ||
1015 | /* | |
1016 | * This interrupt should never happen with our APIC/SMP architecture | |
1017 | */ | |
1018 | ||
1019 | asmlinkage void smp_error_interrupt(void) | |
1020 | { | |
1021 | unsigned int v, v1; | |
1022 | ||
95833c83 | 1023 | exit_idle(); |
1da177e4 LT |
1024 | irq_enter(); |
1025 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1026 | v = apic_read(APIC_ESR); | |
1027 | apic_write(APIC_ESR, 0); | |
1028 | v1 = apic_read(APIC_ESR); | |
1029 | ack_APIC_irq(); | |
1030 | atomic_inc(&irq_err_count); | |
1031 | ||
1032 | /* Here is what the APIC error bits mean: | |
1033 | 0: Send CS error | |
1034 | 1: Receive CS error | |
1035 | 2: Send accept error | |
1036 | 3: Receive accept error | |
1037 | 4: Reserved | |
1038 | 5: Send illegal vector | |
1039 | 6: Received illegal vector | |
1040 | 7: Illegal register address | |
1041 | */ | |
1042 | printk (KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1043 | smp_processor_id(), v , v1); | |
1044 | irq_exit(); | |
1045 | } | |
1046 | ||
1047 | int disable_apic; | |
1048 | ||
1049 | /* | |
1050 | * This initializes the IO-APIC and APIC hardware if this is | |
1051 | * a UP kernel. | |
1052 | */ | |
1053 | int __init APIC_init_uniprocessor (void) | |
1054 | { | |
1055 | if (disable_apic) { | |
1056 | printk(KERN_INFO "Apic disabled\n"); | |
1057 | return -1; | |
1058 | } | |
1059 | if (!cpu_has_apic) { | |
1060 | disable_apic = 1; | |
1061 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
1062 | return -1; | |
1063 | } | |
1064 | ||
1065 | verify_local_APIC(); | |
1066 | ||
357e11d4 | 1067 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id); |
11a8e778 | 1068 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_id)); |
1da177e4 LT |
1069 | |
1070 | setup_local_APIC(); | |
1071 | ||
1da177e4 | 1072 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
7f11d8a5 | 1073 | setup_IO_APIC(); |
1da177e4 LT |
1074 | else |
1075 | nr_ioapics = 0; | |
1da177e4 | 1076 | setup_boot_APIC_clock(); |
75152114 | 1077 | check_nmi_watchdog(); |
1da177e4 LT |
1078 | return 0; |
1079 | } | |
1080 | ||
1081 | static __init int setup_disableapic(char *str) | |
1082 | { | |
1083 | disable_apic = 1; | |
9b41046c | 1084 | return 1; |
1da177e4 LT |
1085 | } |
1086 | ||
1087 | static __init int setup_nolapic(char *str) | |
1088 | { | |
1089 | disable_apic = 1; | |
9b41046c | 1090 | return 1; |
1da177e4 LT |
1091 | } |
1092 | ||
1093 | static __init int setup_noapictimer(char *str) | |
1094 | { | |
73dea47f | 1095 | if (str[0] != ' ' && str[0] != 0) |
9b41046c | 1096 | return 0; |
1da177e4 | 1097 | disable_apic_timer = 1; |
9b41046c | 1098 | return 1; |
1da177e4 LT |
1099 | } |
1100 | ||
73dea47f AK |
1101 | static __init int setup_apicmaintimer(char *str) |
1102 | { | |
1103 | apic_runs_main_timer = 1; | |
1104 | nohpet = 1; | |
9b41046c | 1105 | return 1; |
73dea47f AK |
1106 | } |
1107 | __setup("apicmaintimer", setup_apicmaintimer); | |
1108 | ||
1109 | static __init int setup_noapicmaintimer(char *str) | |
1110 | { | |
1111 | apic_runs_main_timer = -1; | |
9b41046c | 1112 | return 1; |
73dea47f AK |
1113 | } |
1114 | __setup("noapicmaintimer", setup_noapicmaintimer); | |
1115 | ||
0c3749c4 AK |
1116 | static __init int setup_apicpmtimer(char *s) |
1117 | { | |
1118 | apic_calibrate_pmtmr = 1; | |
7fd67843 | 1119 | notsc_setup(NULL); |
0c3749c4 AK |
1120 | return setup_apicmaintimer(NULL); |
1121 | } | |
1122 | __setup("apicpmtimer", setup_apicpmtimer); | |
1123 | ||
1da177e4 LT |
1124 | /* dummy parsing: see setup.c */ |
1125 | ||
1126 | __setup("disableapic", setup_disableapic); | |
1127 | __setup("nolapic", setup_nolapic); /* same as disableapic, for compatibility */ | |
1128 | ||
1129 | __setup("noapictimer", setup_noapictimer); | |
1130 | ||
1131 | /* no "lapic" flag - we only use the lapic when the BIOS tells us so. */ |