[deliverable/linux.git] / arch / x86_64 / kernel / apic.c

/*
 *	Local APIC handling, local APIC timers
 *
 *	(c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
 *
 *	Fixes
 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
 *					thanks to Eric Gilmore
 *					and Rolf G. Tews
 *					for testing these extensively.
 *	Maciej W. Rozycki	:	Various updates and fixes.
 *	Mikael Pettersson	:	Power Management for UP-APIC.
 *	Pavel Machek and
 *	Mikael Pettersson	:	PM converted to driver model.
 */

#include <linux/init.h>

#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/bootmem.h>
#include <linux/smp_lock.h>
#include <linux/interrupt.h>
#include <linux/mc146818rtc.h>
#include <linux/kernel_stat.h>
#include <linux/sysdev.h>
#include <linux/module.h>
#include <linux/ioport.h>

#include <asm/atomic.h>
#include <asm/smp.h>
#include <asm/mtrr.h>
#include <asm/mpspec.h>
#include <asm/pgalloc.h>
#include <asm/mach_apic.h>
#include <asm/nmi.h>
#include <asm/idle.h>
#include <asm/proto.h>
#include <asm/timex.h>
#include <asm/apic.h>

int apic_mapped;
int apic_verbosity;
int apic_runs_main_timer;
int apic_calibrate_pmtmr __initdata;

int disable_apic_timer __initdata;

static struct resource *ioapic_resources;
static struct resource lapic_resource = {
	.name = "Local APIC",
	.flags = IORESOURCE_MEM | IORESOURCE_BUSY,
};

/*
 * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
 * IPIs in place of local APIC timers
 */
static cpumask_t timer_interrupt_broadcast_ipi_mask;

/* Using APIC to generate smp_local_timer_interrupt? */
int using_apic_timer __read_mostly = 0;

static void apic_pm_activate(void);

void enable_NMI_through_LVT0 (void * dummy)
{
	unsigned int v;
	
	v = APIC_DM_NMI;                        /* unmask and set to NMI */
	apic_write(APIC_LVT0, v);
}

int get_maxlvt(void)
{
	unsigned int v, maxlvt;

	v = apic_read(APIC_LVR);
	maxlvt = GET_APIC_MAXLVT(v);
	return maxlvt;
}

/*
 * 'what should we do if we get a hw irq event on an illegal vector'.
 * each architecture has to answer this themselves.
 */
void ack_bad_irq(unsigned int irq)
{
	printk("unexpected IRQ trap at vector %02x\n", irq);
	/*
	 * Currently unexpected vectors happen only on SMP and APIC.
	 * We _must_ ack these because every local APIC has only N
	 * irq slots per priority level, and a 'hanging, unacked' IRQ
	 * holds up an irq slot - in excessive cases (when multiple
	 * unexpected vectors occur) that might lock up the APIC
	 * completely.
  	 * But don't ack when the APIC is disabled. -AK
	 */
	if (!disable_apic)
		ack_APIC_irq();
}

void clear_local_APIC(void)
{
	int maxlvt;
	unsigned int v;

	maxlvt = get_maxlvt();

	/*
	 * Masking an LVT entry can trigger a local APIC error
	 * if the vector is zero. Mask LVTERR first to prevent this.
	 */
	if (maxlvt >= 3) {
		v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
		apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	}
	/*
	 * Careful: we have to set masks only first to deassert
	 * any level-triggered sources.
	 */
	v = apic_read(APIC_LVTT);
	apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT0);
	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT1);
	apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
	if (maxlvt >= 4) {
		v = apic_read(APIC_LVTPC);
		apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
	}

	/*
	 * Clean APIC state for other OSs:
	 */
	apic_write(APIC_LVTT, APIC_LVT_MASKED);
	apic_write(APIC_LVT0, APIC_LVT_MASKED);
	apic_write(APIC_LVT1, APIC_LVT_MASKED);
	if (maxlvt >= 3)
		apic_write(APIC_LVTERR, APIC_LVT_MASKED);
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, APIC_LVT_MASKED);
	v = GET_APIC_VERSION(apic_read(APIC_LVR));
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
}

void disconnect_bsp_APIC(int virt_wire_setup)
{
	/* Go back to Virtual Wire compatibility mode */
	unsigned long value;

	/* For the spurious interrupt use vector F, and enable it */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= 0xf;
	apic_write(APIC_SPIV, value);

	if (!virt_wire_setup) {
		/* For LVT0 make it edge triggered, active high, external and enabled */
		value = apic_read(APIC_LVT0);
		value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
		value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
		value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
		apic_write(APIC_LVT0, value);
	} else {
		/* Disable LVT0 */
		apic_write(APIC_LVT0, APIC_LVT_MASKED);
	}

	/* For LVT1 make it edge triggered, active high, nmi and enabled */
	value = apic_read(APIC_LVT1);
	value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
	value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
	apic_write(APIC_LVT1, value);
}

void disable_local_APIC(void)
{
	unsigned int value;

	clear_local_APIC();

	/*
	 * Disable APIC (implies clearing of registers
	 * for 82489DX!).
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_SPIV_APIC_ENABLED;
	apic_write(APIC_SPIV, value);
}

/*
 * This is to verify that we're looking at a real local APIC.
 * Check these against your board if the CPUs aren't getting
 * started for no apparent reason.
 */
int __init verify_local_APIC(void)
{
	unsigned int reg0, reg1;

	/*
	 * The version register is read-only in a real APIC.
	 */
	reg0 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
	apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
	reg1 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);

	/*
	 * The two version reads above should print the same
	 * numbers.  If the second one is different, then we
	 * poke at a non-APIC.
	 */
	if (reg1 != reg0)
		return 0;

	/*
	 * Check if the version looks reasonably.
	 */
	reg1 = GET_APIC_VERSION(reg0);
	if (reg1 == 0x00 || reg1 == 0xff)
		return 0;
	reg1 = get_maxlvt();
	if (reg1 < 0x02 || reg1 == 0xff)
		return 0;

	/*
	 * The ID register is read/write in a real APIC.
	 */
	reg0 = apic_read(APIC_ID);
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
	apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
	reg1 = apic_read(APIC_ID);
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
	apic_write(APIC_ID, reg0);
	if (reg1 != (reg0 ^ APIC_ID_MASK))
		return 0;

	/*
	 * The next two are just to see if we have sane values.
	 * They're only really relevant if we're in Virtual Wire
	 * compatibility mode, but most boxes are anymore.
	 */
	reg0 = apic_read(APIC_LVT0);
	apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
	reg1 = apic_read(APIC_LVT1);
	apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);

	return 1;
}

void __init sync_Arb_IDs(void)
{
	/* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
	if (ver >= 0x14)	/* P4 or higher */
		return;

	/*
	 * Wait for idle.
	 */
	apic_wait_icr_idle();

	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
	apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
				| APIC_DM_INIT);
}

/*
 * An initial setup of the virtual wire mode.
 */
void __init init_bsp_APIC(void)
{
	unsigned int value;

	/*
	 * Don't do the setup now if we have a SMP BIOS as the
	 * through-I/O-APIC virtual wire mode might be active.
	 */
	if (smp_found_config || !cpu_has_apic)
		return;

	value = apic_read(APIC_LVR);

	/*
	 * Do not trust the local APIC being empty at bootup.
	 */
	clear_local_APIC();

	/*
	 * Enable APIC.
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= APIC_SPIV_FOCUS_DISABLED;
	value |= SPURIOUS_APIC_VECTOR;
	apic_write(APIC_SPIV, value);

	/*
	 * Set up the virtual wire mode.
	 */
	apic_write(APIC_LVT0, APIC_DM_EXTINT);
	value = APIC_DM_NMI;
	apic_write(APIC_LVT1, value);
}

void __cpuinit setup_local_APIC (void)
{
	unsigned int value, maxlvt;
	int i, j;

	value = apic_read(APIC_LVR);

	BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);

	/*
	 * Double-check whether this APIC is really registered.
	 * This is meaningless in clustered apic mode, so we skip it.
	 */
	if (!apic_id_registered())
		BUG();

	/*
	 * Intel recommends to set DFR, LDR and TPR before enabling
	 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
	 * document number 292116).  So here it goes...
	 */
	init_apic_ldr();

	/*
	 * Set Task Priority to 'accept all'. We never change this
	 * later on.
	 */
	value = apic_read(APIC_TASKPRI);
	value &= ~APIC_TPRI_MASK;
	apic_write(APIC_TASKPRI, value);

	/*
	 * After a crash, we no longer service the interrupts and a pending
	 * interrupt from previous kernel might still have ISR bit set.
	 *
	 * Most probably by now CPU has serviced that pending interrupt and
	 * it might not have done the ack_APIC_irq() because it thought,
	 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
	 * does not clear the ISR bit and cpu thinks it has already serivced
	 * the interrupt. Hence a vector might get locked. It was noticed
	 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
	 */
	for (i = APIC_ISR_NR - 1; i >= 0; i--) {
		value = apic_read(APIC_ISR + i*0x10);
		for (j = 31; j >= 0; j--) {
			if (value & (1<<j))
				ack_APIC_irq();
		}
	}

	/*
	 * Now that we are all set up, enable the APIC
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	/*
	 * Enable APIC
	 */
	value |= APIC_SPIV_APIC_ENABLED;

	/* We always use processor focus */

	/*
	 * Set spurious IRQ vector
	 */
	value |= SPURIOUS_APIC_VECTOR;
	apic_write(APIC_SPIV, value);

	/*
	 * Set up LVT0, LVT1:
	 *
	 * set up through-local-APIC on the BP's LINT0. This is not
	 * strictly necessary in pure symmetric-IO mode, but sometimes
	 * we delegate interrupts to the 8259A.
	 */
	/*
	 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
	 */
	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
	if (!smp_processor_id() && !value) {
		value = APIC_DM_EXTINT;
		apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
	} else {
		value = APIC_DM_EXTINT | APIC_LVT_MASKED;
		apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
	}
	apic_write(APIC_LVT0, value);

	/*
	 * only the BP should see the LINT1 NMI signal, obviously.
	 */
	if (!smp_processor_id())
		value = APIC_DM_NMI;
	else
		value = APIC_DM_NMI | APIC_LVT_MASKED;
	apic_write(APIC_LVT1, value);

	{
		unsigned oldvalue;
		maxlvt = get_maxlvt();
		oldvalue = apic_read(APIC_ESR);
		value = ERROR_APIC_VECTOR;      // enables sending errors
		apic_write(APIC_LVTERR, value);
		/*
		 * spec says clear errors after enabling vector.
		 */
		if (maxlvt > 3)
			apic_write(APIC_ESR, 0);
		value = apic_read(APIC_ESR);
		if (value != oldvalue)
			apic_printk(APIC_VERBOSE,
			"ESR value after enabling vector: %08x, after %08x\n",
			oldvalue, value);
	}

	nmi_watchdog_default();
	setup_apic_nmi_watchdog(NULL);
	apic_pm_activate();
}

#ifdef CONFIG_PM

static struct {
	/* 'active' is true if the local APIC was enabled by us and
	   not the BIOS; this signifies that we are also responsible
	   for disabling it before entering apm/acpi suspend */
	int active;
	/* r/w apic fields */
	unsigned int apic_id;
	unsigned int apic_taskpri;
	unsigned int apic_ldr;
	unsigned int apic_dfr;
	unsigned int apic_spiv;
	unsigned int apic_lvtt;
	unsigned int apic_lvtpc;
	unsigned int apic_lvt0;
	unsigned int apic_lvt1;
	unsigned int apic_lvterr;
	unsigned int apic_tmict;
	unsigned int apic_tdcr;
	unsigned int apic_thmr;
} apic_pm_state;

static int lapic_suspend(struct sys_device *dev, pm_message_t state)
{
	unsigned long flags;

	if (!apic_pm_state.active)
		return 0;

	apic_pm_state.apic_id = apic_read(APIC_ID);
	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
	apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
	apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Local APIC handling, local APIC timers
	3	*
	4	* (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
	5	*
	6	* Fixes
	7	* Maciej W. Rozycki : Bits for genuine 82489DX APICs;
	8	* thanks to Eric Gilmore
	9	* and Rolf G. Tews
	10	* for testing these extensively.
	11	* Maciej W. Rozycki : Various updates and fixes.
	12	* Mikael Pettersson : Power Management for UP-APIC.
	13	* Pavel Machek and
	14	* Mikael Pettersson : PM converted to driver model.
	15	*/
	16
1da177e4 LT	17	#include <linux/init.h>
	18
	19	#include <linux/mm.h>
1da177e4 LT	20	#include <linux/delay.h>
	21	#include <linux/bootmem.h>
	22	#include <linux/smp_lock.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/mc146818rtc.h>
	25	#include <linux/kernel_stat.h>
	26	#include <linux/sysdev.h>
d25bf7e5	27	#include <linux/module.h>
39928722	28	#include <linux/ioport.h>
1da177e4 LT	29
	30	#include <asm/atomic.h>
	31	#include <asm/smp.h>
	32	#include <asm/mtrr.h>
	33	#include <asm/mpspec.h>
	34	#include <asm/pgalloc.h>
	35	#include <asm/mach_apic.h>
75152114	36	#include <asm/nmi.h>
95833c83	37	#include <asm/idle.h>
73dea47f AK	38	#include <asm/proto.h>
73dea47f AK	39	#include <asm/timex.h>
2c8c0e6b	40	#include <asm/apic.h>
1da177e4	41
b7f5e3c7	42	int apic_mapped;
1da177e4	43	int apic_verbosity;
73dea47f	44	int apic_runs_main_timer;
0c3749c4	45	int apic_calibrate_pmtmr __initdata;
1da177e4 LT	46
	47	int disable_apic_timer __initdata;
	48
39928722 AD	49	static struct resource *ioapic_resources;
	50	static struct resource lapic_resource = {
	51	.name = "Local APIC",
	52	.flags = IORESOURCE_MEM \| IORESOURCE_BUSY,
	53	};
	54
d25bf7e5 VP	55	/*
	56	* cpu_mask that denotes the CPUs that needs timer interrupt coming in as
	57	* IPIs in place of local APIC timers
	58	*/
	59	static cpumask_t timer_interrupt_broadcast_ipi_mask;
	60
1da177e4	61	/* Using APIC to generate smp_local_timer_interrupt? */
acae9d32	62	int using_apic_timer __read_mostly = 0;
1da177e4	63
1da177e4 LT	64	static void apic_pm_activate(void);
	65
	66	void enable_NMI_through_LVT0 (void * dummy)
	67	{
11a8e778	68	unsigned int v;
1da177e4	69
1da177e4	70	v = APIC_DM_NMI; /* unmask and set to NMI */
11a8e778	71	apic_write(APIC_LVT0, v);
1da177e4 LT	72	}
	73
	74	int get_maxlvt(void)
	75	{
11a8e778	76	unsigned int v, maxlvt;
1da177e4 LT	77
1da177e4 LT	78	v = apic_read(APIC_LVR);
1da177e4 LT	79	maxlvt = GET_APIC_MAXLVT(v);
	80	return maxlvt;
	81	}
	82
3777a959 AK	83	/*
	84	* 'what should we do if we get a hw irq event on an illegal vector'.
	85	* each architecture has to answer this themselves.
	86	*/
	87	void ack_bad_irq(unsigned int irq)
	88	{
	89	printk("unexpected IRQ trap at vector %02x\n", irq);
	90	/*
	91	* Currently unexpected vectors happen only on SMP and APIC.
	92	* We _must_ ack these because every local APIC has only N
	93	* irq slots per priority level, and a 'hanging, unacked' IRQ
	94	* holds up an irq slot - in excessive cases (when multiple
	95	* unexpected vectors occur) that might lock up the APIC
	96	* completely.
	97	* But don't ack when the APIC is disabled. -AK
	98	*/
	99	if (!disable_apic)
	100	ack_APIC_irq();
	101	}
	102
1da177e4 LT	103	void clear_local_APIC(void)
	104	{
	105	int maxlvt;
	106	unsigned int v;
	107
	108	maxlvt = get_maxlvt();
	109
	110	/*
704fc59e	111	* Masking an LVT entry can trigger a local APIC error
1da177e4 LT	112	* if the vector is zero. Mask LVTERR first to prevent this.
	113	*/
	114	if (maxlvt >= 3) {
	115	v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
11a8e778	116	apic_write(APIC_LVTERR, v \| APIC_LVT_MASKED);
1da177e4 LT	117	}
	118	/*
	119	* Careful: we have to set masks only first to deassert
	120	* any level-triggered sources.
	121	*/
	122	v = apic_read(APIC_LVTT);
11a8e778	123	apic_write(APIC_LVTT, v \| APIC_LVT_MASKED);
1da177e4	124	v = apic_read(APIC_LVT0);
11a8e778	125	apic_write(APIC_LVT0, v \| APIC_LVT_MASKED);
1da177e4	126	v = apic_read(APIC_LVT1);
11a8e778	127	apic_write(APIC_LVT1, v \| APIC_LVT_MASKED);
1da177e4 LT	128	if (maxlvt >= 4) {
1da177e4 LT	129	v = apic_read(APIC_LVTPC);
11a8e778	130	apic_write(APIC_LVTPC, v \| APIC_LVT_MASKED);
1da177e4 LT	131	}
	132
	133	/*
	134	* Clean APIC state for other OSs:
	135	*/
11a8e778 AK	136	apic_write(APIC_LVTT, APIC_LVT_MASKED);
	137	apic_write(APIC_LVT0, APIC_LVT_MASKED);
	138	apic_write(APIC_LVT1, APIC_LVT_MASKED);
1da177e4	139	if (maxlvt >= 3)
11a8e778	140	apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1da177e4	141	if (maxlvt >= 4)
11a8e778	142	apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1da177e4	143	v = GET_APIC_VERSION(apic_read(APIC_LVR));
5a40b7c2 AK	144	apic_write(APIC_ESR, 0);
5a40b7c2 AK	145	apic_read(APIC_ESR);
1da177e4 LT	146	}
1da177e4 LT	147
208fb931	148	void disconnect_bsp_APIC(int virt_wire_setup)
1da177e4	149	{
a8fcf1a2 AK	150	/* Go back to Virtual Wire compatibility mode */
a8fcf1a2 AK	151	unsigned long value;
208fb931	152
a8fcf1a2 AK	153	/* For the spurious interrupt use vector F, and enable it */
	154	value = apic_read(APIC_SPIV);
	155	value &= ~APIC_VECTOR_MASK;
	156	value \|= APIC_SPIV_APIC_ENABLED;
	157	value \|= 0xf;
	158	apic_write(APIC_SPIV, value);
	159
	160	if (!virt_wire_setup) {
	161	/* For LVT0 make it edge triggered, active high, external and enabled */
	162	value = apic_read(APIC_LVT0);
	163	value &= ~(APIC_MODE_MASK \| APIC_SEND_PENDING \|
208fb931	164	APIC_INPUT_POLARITY \| APIC_LVT_REMOTE_IRR \|
a8fcf1a2	165	APIC_LVT_LEVEL_TRIGGER \| APIC_LVT_MASKED );
208fb931	166	value \|= APIC_LVT_REMOTE_IRR \| APIC_SEND_PENDING;
a8fcf1a2 AK	167	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
	168	apic_write(APIC_LVT0, value);
	169	} else {
	170	/* Disable LVT0 */
	171	apic_write(APIC_LVT0, APIC_LVT_MASKED);
208fb931	172	}
a8fcf1a2 AK	173
	174	/* For LVT1 make it edge triggered, active high, nmi and enabled */
	175	value = apic_read(APIC_LVT1);
	176	value &= ~(APIC_MODE_MASK \| APIC_SEND_PENDING \|
	177	APIC_INPUT_POLARITY \| APIC_LVT_REMOTE_IRR \|
	178	APIC_LVT_LEVEL_TRIGGER \| APIC_LVT_MASKED);
	179	value \|= APIC_LVT_REMOTE_IRR \| APIC_SEND_PENDING;
	180	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
	181	apic_write(APIC_LVT1, value);
1da177e4 LT	182	}
	183
	184	void disable_local_APIC(void)
	185	{
	186	unsigned int value;
	187
	188	clear_local_APIC();
	189
	190	/*
	191	* Disable APIC (implies clearing of registers
	192	* for 82489DX!).
	193	*/
	194	value = apic_read(APIC_SPIV);
	195	value &= ~APIC_SPIV_APIC_ENABLED;
11a8e778	196	apic_write(APIC_SPIV, value);
1da177e4 LT	197	}
	198
	199	/*
	200	* This is to verify that we're looking at a real local APIC.
	201	* Check these against your board if the CPUs aren't getting
	202	* started for no apparent reason.
	203	*/
	204	int __init verify_local_APIC(void)
	205	{
	206	unsigned int reg0, reg1;
	207
	208	/*
	209	* The version register is read-only in a real APIC.
	210	*/
	211	reg0 = apic_read(APIC_LVR);
	212	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
	213	apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
	214	reg1 = apic_read(APIC_LVR);
	215	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
	216
	217	/*
	218	* The two version reads above should print the same
	219	* numbers. If the second one is different, then we
	220	* poke at a non-APIC.
	221	*/
	222	if (reg1 != reg0)
	223	return 0;
	224
	225	/*
	226	* Check if the version looks reasonably.
	227	*/
	228	reg1 = GET_APIC_VERSION(reg0);
	229	if (reg1 == 0x00 \|\| reg1 == 0xff)
	230	return 0;
	231	reg1 = get_maxlvt();
	232	if (reg1 < 0x02 \|\| reg1 == 0xff)
	233	return 0;
	234
	235	/*
	236	* The ID register is read/write in a real APIC.
	237	*/
	238	reg0 = apic_read(APIC_ID);
	239	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
	240	apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
	241	reg1 = apic_read(APIC_ID);
	242	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
	243	apic_write(APIC_ID, reg0);
	244	if (reg1 != (reg0 ^ APIC_ID_MASK))
	245	return 0;
	246
	247	/*
	248	* The next two are just to see if we have sane values.
	249	* They're only really relevant if we're in Virtual Wire
	250	* compatibility mode, but most boxes are anymore.
	251	*/
	252	reg0 = apic_read(APIC_LVT0);
	253	apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
	254	reg1 = apic_read(APIC_LVT1);
	255	apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
	256
	257	return 1;
	258	}
	259
	260	void __init sync_Arb_IDs(void)
261	{
262	/* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
263	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
264	if (ver >= 0x14) /* P4 or higher */
265	return;
266
267	/*
268	* Wait for idle.
269	*/
270	apic_wait_icr_idle();
271
272	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
11a8e778	273	apic_write(APIC_ICR, APIC_DEST_ALLINC \| APIC_INT_LEVELTRIG
1da177e4 LT	274	\| APIC_DM_INIT);
	275	}
	276
1da177e4 LT	277	/*
	278	* An initial setup of the virtual wire mode.
	279	*/
	280	void __init init_bsp_APIC(void)
	281	{
11a8e778	282	unsigned int value;
1da177e4 LT	283
	284	/*
	285	* Don't do the setup now if we have a SMP BIOS as the
	286	* through-I/O-APIC virtual wire mode might be active.
	287	*/
	288	if (smp_found_config \|\| !cpu_has_apic)
	289	return;
	290
	291	value = apic_read(APIC_LVR);
1da177e4 LT	292
	293	/*
	294	* Do not trust the local APIC being empty at bootup.
	295	*/
	296	clear_local_APIC();
	297
	298	/*
	299	* Enable APIC.
	300	*/
	301	value = apic_read(APIC_SPIV);
	302	value &= ~APIC_VECTOR_MASK;
	303	value \|= APIC_SPIV_APIC_ENABLED;
	304	value \|= APIC_SPIV_FOCUS_DISABLED;
	305	value \|= SPURIOUS_APIC_VECTOR;
11a8e778	306	apic_write(APIC_SPIV, value);
1da177e4 LT	307
	308	/*
	309	* Set up the virtual wire mode.
	310	*/
11a8e778	311	apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4	312	value = APIC_DM_NMI;
11a8e778	313	apic_write(APIC_LVT1, value);
1da177e4 LT	314	}
1da177e4 LT	315
e6982c67	316	void __cpuinit setup_local_APIC (void)
1da177e4	317	{
11a8e778	318	unsigned int value, maxlvt;
da7ed9f9	319	int i, j;
1da177e4	320
1da177e4	321	value = apic_read(APIC_LVR);
1da177e4	322
fe7414a2	323	BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
1da177e4 LT	324
	325	/*
	326	* Double-check whether this APIC is really registered.
	327	* This is meaningless in clustered apic mode, so we skip it.
	328	*/
	329	if (!apic_id_registered())
	330	BUG();
	331
	332	/*
	333	* Intel recommends to set DFR, LDR and TPR before enabling
	334	* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
	335	* document number 292116). So here it goes...
	336	*/
	337	init_apic_ldr();
	338
	339	/*
	340	* Set Task Priority to 'accept all'. We never change this
	341	* later on.
	342	*/
	343	value = apic_read(APIC_TASKPRI);
	344	value &= ~APIC_TPRI_MASK;
11a8e778	345	apic_write(APIC_TASKPRI, value);
1da177e4	346
da7ed9f9 VG	347	/*
	348	* After a crash, we no longer service the interrupts and a pending
	349	* interrupt from previous kernel might still have ISR bit set.
	350	*
	351	* Most probably by now CPU has serviced that pending interrupt and
	352	* it might not have done the ack_APIC_irq() because it thought,
	353	* interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
	354	* does not clear the ISR bit and cpu thinks it has already serivced
	355	* the interrupt. Hence a vector might get locked. It was noticed
	356	* for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
	357	*/
	358	for (i = APIC_ISR_NR - 1; i >= 0; i--) {
	359	value = apic_read(APIC_ISR + i*0x10);
	360	for (j = 31; j >= 0; j--) {
	361	if (value & (1<<j))
	362	ack_APIC_irq();
	363	}
	364	}
	365
1da177e4 LT	366	/*
	367	* Now that we are all set up, enable the APIC
	368	*/
	369	value = apic_read(APIC_SPIV);
	370	value &= ~APIC_VECTOR_MASK;
	371	/*
	372	* Enable APIC
	373	*/
	374	value \|= APIC_SPIV_APIC_ENABLED;
	375
3f14c746 AK	376	/* We always use processor focus */
3f14c746 AK	377
1da177e4 LT	378	/*
	379	* Set spurious IRQ vector
	380	*/
	381	value \|= SPURIOUS_APIC_VECTOR;
11a8e778	382	apic_write(APIC_SPIV, value);
1da177e4 LT	383
	384	/*
	385	* Set up LVT0, LVT1:
	386	*
	387	* set up through-local-APIC on the BP's LINT0. This is not
	388	* strictly necessary in pure symmetric-IO mode, but sometimes
	389	* we delegate interrupts to the 8259A.
	390	*/
	391	/*
	392	* TODO: set up through-local-APIC from through-I/O-APIC? --macro
	393	*/
	394	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
a8fcf1a2	395	if (!smp_processor_id() && !value) {
1da177e4 LT	396	value = APIC_DM_EXTINT;
	397	apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
	398	} else {
	399	value = APIC_DM_EXTINT \| APIC_LVT_MASKED;
	400	apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
	401	}
11a8e778	402	apic_write(APIC_LVT0, value);
1da177e4 LT	403
	404	/*
	405	* only the BP should see the LINT1 NMI signal, obviously.
	406	*/
	407	if (!smp_processor_id())
	408	value = APIC_DM_NMI;
	409	else
	410	value = APIC_DM_NMI \| APIC_LVT_MASKED;
11a8e778	411	apic_write(APIC_LVT1, value);
1da177e4	412
61c11341	413	{
1da177e4 LT	414	unsigned oldvalue;
1da177e4 LT	415	maxlvt = get_maxlvt();
1da177e4 LT	416	oldvalue = apic_read(APIC_ESR);
1da177e4 LT	417	value = ERROR_APIC_VECTOR; // enables sending errors
11a8e778	418	apic_write(APIC_LVTERR, value);
1da177e4 LT	419	/*
	420	* spec says clear errors after enabling vector.
	421	*/
	422	if (maxlvt > 3)
	423	apic_write(APIC_ESR, 0);
	424	value = apic_read(APIC_ESR);
	425	if (value != oldvalue)
	426	apic_printk(APIC_VERBOSE,
	427	"ESR value after enabling vector: %08x, after %08x\n",
	428	oldvalue, value);
1da177e4 LT	429	}
	430
	431	nmi_watchdog_default();
f2802e7f	432	setup_apic_nmi_watchdog(NULL);
1da177e4 LT	433	apic_pm_activate();
	434	}
	435
	436	#ifdef CONFIG_PM
	437
	438	static struct {
	439	/* 'active' is true if the local APIC was enabled by us and
	440	not the BIOS; this signifies that we are also responsible
	441	for disabling it before entering apm/acpi suspend */
	442	int active;
	443	/* r/w apic fields */
	444	unsigned int apic_id;
	445	unsigned int apic_taskpri;
	446	unsigned int apic_ldr;
	447	unsigned int apic_dfr;
	448	unsigned int apic_spiv;
	449	unsigned int apic_lvtt;
	450	unsigned int apic_lvtpc;
	451	unsigned int apic_lvt0;
	452	unsigned int apic_lvt1;
	453	unsigned int apic_lvterr;
	454	unsigned int apic_tmict;
	455	unsigned int apic_tdcr;
	456	unsigned int apic_thmr;
	457	} apic_pm_state;
	458
0b9c33a7	459	static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4 LT	460	{
	461	unsigned long flags;
	462
	463	if (!apic_pm_state.active)
	464	return 0;
	465
	466	apic_pm_state.apic_id = apic_read(APIC_ID);
	467	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
	468	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
	469	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
	470	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
	471	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
	472	apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
	473	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
	474	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
	475	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
	476	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
	477	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
	478	apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);