Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
17 | #include <linux/config.h> | |
18 | #include <linux/init.h> | |
19 | ||
20 | #include <linux/mm.h> | |
21 | #include <linux/irq.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/bootmem.h> | |
24 | #include <linux/smp_lock.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/mc146818rtc.h> | |
27 | #include <linux/kernel_stat.h> | |
28 | #include <linux/sysdev.h> | |
29 | ||
30 | #include <asm/atomic.h> | |
31 | #include <asm/smp.h> | |
32 | #include <asm/mtrr.h> | |
33 | #include <asm/mpspec.h> | |
34 | #include <asm/pgalloc.h> | |
35 | #include <asm/mach_apic.h> | |
75152114 | 36 | #include <asm/nmi.h> |
1da177e4 LT |
37 | |
38 | int apic_verbosity; | |
39 | ||
40 | int disable_apic_timer __initdata; | |
41 | ||
42 | /* Using APIC to generate smp_local_timer_interrupt? */ | |
43 | int using_apic_timer = 0; | |
44 | ||
45 | static DEFINE_PER_CPU(int, prof_multiplier) = 1; | |
46 | static DEFINE_PER_CPU(int, prof_old_multiplier) = 1; | |
47 | static DEFINE_PER_CPU(int, prof_counter) = 1; | |
48 | ||
49 | static void apic_pm_activate(void); | |
50 | ||
51 | void enable_NMI_through_LVT0 (void * dummy) | |
52 | { | |
53 | unsigned int v, ver; | |
54 | ||
55 | ver = apic_read(APIC_LVR); | |
56 | ver = GET_APIC_VERSION(ver); | |
57 | v = APIC_DM_NMI; /* unmask and set to NMI */ | |
58 | apic_write_around(APIC_LVT0, v); | |
59 | } | |
60 | ||
61 | int get_maxlvt(void) | |
62 | { | |
63 | unsigned int v, ver, maxlvt; | |
64 | ||
65 | v = apic_read(APIC_LVR); | |
66 | ver = GET_APIC_VERSION(v); | |
67 | maxlvt = GET_APIC_MAXLVT(v); | |
68 | return maxlvt; | |
69 | } | |
70 | ||
71 | void clear_local_APIC(void) | |
72 | { | |
73 | int maxlvt; | |
74 | unsigned int v; | |
75 | ||
76 | maxlvt = get_maxlvt(); | |
77 | ||
78 | /* | |
79 | * Masking an LVT entry on a P6 can trigger a local APIC error | |
80 | * if the vector is zero. Mask LVTERR first to prevent this. | |
81 | */ | |
82 | if (maxlvt >= 3) { | |
83 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
84 | apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED); | |
85 | } | |
86 | /* | |
87 | * Careful: we have to set masks only first to deassert | |
88 | * any level-triggered sources. | |
89 | */ | |
90 | v = apic_read(APIC_LVTT); | |
91 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); | |
92 | v = apic_read(APIC_LVT0); | |
93 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); | |
94 | v = apic_read(APIC_LVT1); | |
95 | apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED); | |
96 | if (maxlvt >= 4) { | |
97 | v = apic_read(APIC_LVTPC); | |
98 | apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED); | |
99 | } | |
100 | ||
101 | /* | |
102 | * Clean APIC state for other OSs: | |
103 | */ | |
104 | apic_write_around(APIC_LVTT, APIC_LVT_MASKED); | |
105 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
106 | apic_write_around(APIC_LVT1, APIC_LVT_MASKED); | |
107 | if (maxlvt >= 3) | |
108 | apic_write_around(APIC_LVTERR, APIC_LVT_MASKED); | |
109 | if (maxlvt >= 4) | |
110 | apic_write_around(APIC_LVTPC, APIC_LVT_MASKED); | |
111 | v = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
112 | if (APIC_INTEGRATED(v)) { /* !82489DX */ | |
113 | if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */ | |
114 | apic_write(APIC_ESR, 0); | |
115 | apic_read(APIC_ESR); | |
116 | } | |
117 | } | |
118 | ||
119 | void __init connect_bsp_APIC(void) | |
120 | { | |
121 | if (pic_mode) { | |
122 | /* | |
123 | * Do not trust the local APIC being empty at bootup. | |
124 | */ | |
125 | clear_local_APIC(); | |
126 | /* | |
127 | * PIC mode, enable APIC mode in the IMCR, i.e. | |
128 | * connect BSP's local APIC to INT and NMI lines. | |
129 | */ | |
130 | apic_printk(APIC_VERBOSE, "leaving PIC mode, enabling APIC mode.\n"); | |
131 | outb(0x70, 0x22); | |
132 | outb(0x01, 0x23); | |
133 | } | |
134 | } | |
135 | ||
208fb931 | 136 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 LT |
137 | { |
138 | if (pic_mode) { | |
139 | /* | |
140 | * Put the board back into PIC mode (has an effect | |
141 | * only on certain older boards). Note that APIC | |
142 | * interrupts, including IPIs, won't work beyond | |
143 | * this point! The only exception are INIT IPIs. | |
144 | */ | |
145 | apic_printk(APIC_QUIET, "disabling APIC mode, entering PIC mode.\n"); | |
146 | outb(0x70, 0x22); | |
147 | outb(0x00, 0x23); | |
148 | } | |
208fb931 EB |
149 | else { |
150 | /* Go back to Virtual Wire compatibility mode */ | |
151 | unsigned long value; | |
152 | ||
153 | /* For the spurious interrupt use vector F, and enable it */ | |
154 | value = apic_read(APIC_SPIV); | |
155 | value &= ~APIC_VECTOR_MASK; | |
156 | value |= APIC_SPIV_APIC_ENABLED; | |
157 | value |= 0xf; | |
158 | apic_write_around(APIC_SPIV, value); | |
159 | ||
160 | if (!virt_wire_setup) { | |
161 | /* For LVT0 make it edge triggered, active high, external and enabled */ | |
162 | value = apic_read(APIC_LVT0); | |
163 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
164 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
165 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED ); | |
166 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
167 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
168 | apic_write_around(APIC_LVT0, value); | |
169 | } | |
170 | else { | |
171 | /* Disable LVT0 */ | |
172 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
173 | } | |
174 | ||
175 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ | |
176 | value = apic_read(APIC_LVT1); | |
177 | value &= ~( | |
178 | APIC_MODE_MASK | APIC_SEND_PENDING | | |
179 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
180 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
181 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
182 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
183 | apic_write_around(APIC_LVT1, value); | |
184 | } | |
1da177e4 LT |
185 | } |
186 | ||
187 | void disable_local_APIC(void) | |
188 | { | |
189 | unsigned int value; | |
190 | ||
191 | clear_local_APIC(); | |
192 | ||
193 | /* | |
194 | * Disable APIC (implies clearing of registers | |
195 | * for 82489DX!). | |
196 | */ | |
197 | value = apic_read(APIC_SPIV); | |
198 | value &= ~APIC_SPIV_APIC_ENABLED; | |
199 | apic_write_around(APIC_SPIV, value); | |
200 | } | |
201 | ||
202 | /* | |
203 | * This is to verify that we're looking at a real local APIC. | |
204 | * Check these against your board if the CPUs aren't getting | |
205 | * started for no apparent reason. | |
206 | */ | |
207 | int __init verify_local_APIC(void) | |
208 | { | |
209 | unsigned int reg0, reg1; | |
210 | ||
211 | /* | |
212 | * The version register is read-only in a real APIC. | |
213 | */ | |
214 | reg0 = apic_read(APIC_LVR); | |
215 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
216 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
217 | reg1 = apic_read(APIC_LVR); | |
218 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
219 | ||
220 | /* | |
221 | * The two version reads above should print the same | |
222 | * numbers. If the second one is different, then we | |
223 | * poke at a non-APIC. | |
224 | */ | |
225 | if (reg1 != reg0) | |
226 | return 0; | |
227 | ||
228 | /* | |
229 | * Check if the version looks reasonably. | |
230 | */ | |
231 | reg1 = GET_APIC_VERSION(reg0); | |
232 | if (reg1 == 0x00 || reg1 == 0xff) | |
233 | return 0; | |
234 | reg1 = get_maxlvt(); | |
235 | if (reg1 < 0x02 || reg1 == 0xff) | |
236 | return 0; | |
237 | ||
238 | /* | |
239 | * The ID register is read/write in a real APIC. | |
240 | */ | |
241 | reg0 = apic_read(APIC_ID); | |
242 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
243 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
244 | reg1 = apic_read(APIC_ID); | |
245 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); | |
246 | apic_write(APIC_ID, reg0); | |
247 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
248 | return 0; | |
249 | ||
250 | /* | |
251 | * The next two are just to see if we have sane values. | |
252 | * They're only really relevant if we're in Virtual Wire | |
253 | * compatibility mode, but most boxes are anymore. | |
254 | */ | |
255 | reg0 = apic_read(APIC_LVT0); | |
256 | apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0); | |
257 | reg1 = apic_read(APIC_LVT1); | |
258 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
259 | ||
260 | return 1; | |
261 | } | |
262 | ||
263 | void __init sync_Arb_IDs(void) | |
264 | { | |
265 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */ | |
266 | unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
267 | if (ver >= 0x14) /* P4 or higher */ | |
268 | return; | |
269 | ||
270 | /* | |
271 | * Wait for idle. | |
272 | */ | |
273 | apic_wait_icr_idle(); | |
274 | ||
275 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
276 | apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | |
277 | | APIC_DM_INIT); | |
278 | } | |
279 | ||
280 | extern void __error_in_apic_c (void); | |
281 | ||
282 | /* | |
283 | * An initial setup of the virtual wire mode. | |
284 | */ | |
285 | void __init init_bsp_APIC(void) | |
286 | { | |
287 | unsigned int value, ver; | |
288 | ||
289 | /* | |
290 | * Don't do the setup now if we have a SMP BIOS as the | |
291 | * through-I/O-APIC virtual wire mode might be active. | |
292 | */ | |
293 | if (smp_found_config || !cpu_has_apic) | |
294 | return; | |
295 | ||
296 | value = apic_read(APIC_LVR); | |
297 | ver = GET_APIC_VERSION(value); | |
298 | ||
299 | /* | |
300 | * Do not trust the local APIC being empty at bootup. | |
301 | */ | |
302 | clear_local_APIC(); | |
303 | ||
304 | /* | |
305 | * Enable APIC. | |
306 | */ | |
307 | value = apic_read(APIC_SPIV); | |
308 | value &= ~APIC_VECTOR_MASK; | |
309 | value |= APIC_SPIV_APIC_ENABLED; | |
310 | value |= APIC_SPIV_FOCUS_DISABLED; | |
311 | value |= SPURIOUS_APIC_VECTOR; | |
312 | apic_write_around(APIC_SPIV, value); | |
313 | ||
314 | /* | |
315 | * Set up the virtual wire mode. | |
316 | */ | |
317 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); | |
318 | value = APIC_DM_NMI; | |
319 | if (!APIC_INTEGRATED(ver)) /* 82489DX */ | |
320 | value |= APIC_LVT_LEVEL_TRIGGER; | |
321 | apic_write_around(APIC_LVT1, value); | |
322 | } | |
323 | ||
e6982c67 | 324 | void __cpuinit setup_local_APIC (void) |
1da177e4 LT |
325 | { |
326 | unsigned int value, ver, maxlvt; | |
327 | ||
328 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
329 | if (esr_disable) { | |
330 | apic_write(APIC_ESR, 0); | |
331 | apic_write(APIC_ESR, 0); | |
332 | apic_write(APIC_ESR, 0); | |
333 | apic_write(APIC_ESR, 0); | |
334 | } | |
335 | ||
336 | value = apic_read(APIC_LVR); | |
337 | ver = GET_APIC_VERSION(value); | |
338 | ||
339 | if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f) | |
340 | __error_in_apic_c(); | |
341 | ||
342 | /* | |
343 | * Double-check whether this APIC is really registered. | |
344 | * This is meaningless in clustered apic mode, so we skip it. | |
345 | */ | |
346 | if (!apic_id_registered()) | |
347 | BUG(); | |
348 | ||
349 | /* | |
350 | * Intel recommends to set DFR, LDR and TPR before enabling | |
351 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
352 | * document number 292116). So here it goes... | |
353 | */ | |
354 | init_apic_ldr(); | |
355 | ||
356 | /* | |
357 | * Set Task Priority to 'accept all'. We never change this | |
358 | * later on. | |
359 | */ | |
360 | value = apic_read(APIC_TASKPRI); | |
361 | value &= ~APIC_TPRI_MASK; | |
362 | apic_write_around(APIC_TASKPRI, value); | |
363 | ||
364 | /* | |
365 | * Now that we are all set up, enable the APIC | |
366 | */ | |
367 | value = apic_read(APIC_SPIV); | |
368 | value &= ~APIC_VECTOR_MASK; | |
369 | /* | |
370 | * Enable APIC | |
371 | */ | |
372 | value |= APIC_SPIV_APIC_ENABLED; | |
373 | ||
374 | /* | |
375 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
376 | * certain networking cards. If high frequency interrupts are | |
377 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
378 | * entry is masked/unmasked at a high rate as well then sooner or | |
379 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
380 | * from the device. If focus CPU is disabled then the hang goes | |
381 | * away, oh well :-( | |
382 | * | |
383 | * [ This bug can be reproduced easily with a level-triggered | |
384 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
385 | * BX chipset. ] | |
386 | */ | |
387 | /* | |
388 | * Actually disabling the focus CPU check just makes the hang less | |
389 | * frequent as it makes the interrupt distributon model be more | |
390 | * like LRU than MRU (the short-term load is more even across CPUs). | |
391 | * See also the comment in end_level_ioapic_irq(). --macro | |
392 | */ | |
393 | #if 1 | |
394 | /* Enable focus processor (bit==0) */ | |
395 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
396 | #else | |
397 | /* Disable focus processor (bit==1) */ | |
398 | value |= APIC_SPIV_FOCUS_DISABLED; | |
399 | #endif | |
400 | /* | |
401 | * Set spurious IRQ vector | |
402 | */ | |
403 | value |= SPURIOUS_APIC_VECTOR; | |
404 | apic_write_around(APIC_SPIV, value); | |
405 | ||
406 | /* | |
407 | * Set up LVT0, LVT1: | |
408 | * | |
409 | * set up through-local-APIC on the BP's LINT0. This is not | |
410 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
411 | * we delegate interrupts to the 8259A. | |
412 | */ | |
413 | /* | |
414 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
415 | */ | |
416 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
417 | if (!smp_processor_id() && (pic_mode || !value)) { | |
418 | value = APIC_DM_EXTINT; | |
419 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id()); | |
420 | } else { | |
421 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
422 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id()); | |
423 | } | |
424 | apic_write_around(APIC_LVT0, value); | |
425 | ||
426 | /* | |
427 | * only the BP should see the LINT1 NMI signal, obviously. | |
428 | */ | |
429 | if (!smp_processor_id()) | |
430 | value = APIC_DM_NMI; | |
431 | else | |
432 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
433 | if (!APIC_INTEGRATED(ver)) /* 82489DX */ | |
434 | value |= APIC_LVT_LEVEL_TRIGGER; | |
435 | apic_write_around(APIC_LVT1, value); | |
436 | ||
437 | if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */ | |
438 | unsigned oldvalue; | |
439 | maxlvt = get_maxlvt(); | |
440 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
441 | apic_write(APIC_ESR, 0); | |
442 | oldvalue = apic_read(APIC_ESR); | |
443 | value = ERROR_APIC_VECTOR; // enables sending errors | |
444 | apic_write_around(APIC_LVTERR, value); | |
445 | /* | |
446 | * spec says clear errors after enabling vector. | |
447 | */ | |
448 | if (maxlvt > 3) | |
449 | apic_write(APIC_ESR, 0); | |
450 | value = apic_read(APIC_ESR); | |
451 | if (value != oldvalue) | |
452 | apic_printk(APIC_VERBOSE, | |
453 | "ESR value after enabling vector: %08x, after %08x\n", | |
454 | oldvalue, value); | |
455 | } else { | |
456 | if (esr_disable) | |
457 | /* | |
458 | * Something untraceble is creating bad interrupts on | |
459 | * secondary quads ... for the moment, just leave the | |
460 | * ESR disabled - we can't do anything useful with the | |
461 | * errors anyway - mbligh | |
462 | */ | |
463 | apic_printk(APIC_DEBUG, "Leaving ESR disabled.\n"); | |
464 | else | |
465 | apic_printk(APIC_DEBUG, "No ESR for 82489DX.\n"); | |
466 | } | |
467 | ||
468 | nmi_watchdog_default(); | |
469 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
470 | setup_apic_nmi_watchdog(); | |
471 | apic_pm_activate(); | |
472 | } | |
473 | ||
474 | #ifdef CONFIG_PM | |
475 | ||
476 | static struct { | |
477 | /* 'active' is true if the local APIC was enabled by us and | |
478 | not the BIOS; this signifies that we are also responsible | |
479 | for disabling it before entering apm/acpi suspend */ | |
480 | int active; | |
481 | /* r/w apic fields */ | |
482 | unsigned int apic_id; | |
483 | unsigned int apic_taskpri; | |
484 | unsigned int apic_ldr; | |
485 | unsigned int apic_dfr; | |
486 | unsigned int apic_spiv; | |
487 | unsigned int apic_lvtt; | |
488 | unsigned int apic_lvtpc; | |
489 | unsigned int apic_lvt0; | |
490 | unsigned int apic_lvt1; | |
491 | unsigned int apic_lvterr; | |
492 | unsigned int apic_tmict; | |
493 | unsigned int apic_tdcr; | |
494 | unsigned int apic_thmr; | |
495 | } apic_pm_state; | |
496 | ||
0b9c33a7 | 497 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
498 | { |
499 | unsigned long flags; | |
500 | ||
501 | if (!apic_pm_state.active) | |
502 | return 0; | |
503 | ||
504 | apic_pm_state.apic_id = apic_read(APIC_ID); | |
505 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
506 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
507 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
508 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
509 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
510 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
511 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
512 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
513 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
514 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
515 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
516 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
517 | local_save_flags(flags); | |
518 | local_irq_disable(); | |
519 | disable_local_APIC(); | |
520 | local_irq_restore(flags); | |
521 | return 0; | |
522 | } | |
523 | ||
524 | static int lapic_resume(struct sys_device *dev) | |
525 | { | |
526 | unsigned int l, h; | |
527 | unsigned long flags; | |
528 | ||
529 | if (!apic_pm_state.active) | |
530 | return 0; | |
531 | ||
532 | /* XXX: Pavel needs this for S3 resume, but can't explain why */ | |
533 | set_fixmap_nocache(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE); | |
534 | ||
535 | local_irq_save(flags); | |
536 | rdmsr(MSR_IA32_APICBASE, l, h); | |
537 | l &= ~MSR_IA32_APICBASE_BASE; | |
538 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
539 | wrmsr(MSR_IA32_APICBASE, l, h); | |
540 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
541 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
542 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
543 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
544 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
545 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
546 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
547 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
548 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
549 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
550 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
551 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
552 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
553 | apic_write(APIC_ESR, 0); | |
554 | apic_read(APIC_ESR); | |
555 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
556 | apic_write(APIC_ESR, 0); | |
557 | apic_read(APIC_ESR); | |
558 | local_irq_restore(flags); | |
559 | return 0; | |
560 | } | |
561 | ||
562 | static struct sysdev_class lapic_sysclass = { | |
563 | set_kset_name("lapic"), | |
564 | .resume = lapic_resume, | |
565 | .suspend = lapic_suspend, | |
566 | }; | |
567 | ||
568 | static struct sys_device device_lapic = { | |
569 | .id = 0, | |
570 | .cls = &lapic_sysclass, | |
571 | }; | |
572 | ||
e6982c67 | 573 | static void __cpuinit apic_pm_activate(void) |
1da177e4 LT |
574 | { |
575 | apic_pm_state.active = 1; | |
576 | } | |
577 | ||
578 | static int __init init_lapic_sysfs(void) | |
579 | { | |
580 | int error; | |
581 | if (!cpu_has_apic) | |
582 | return 0; | |
583 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
584 | error = sysdev_class_register(&lapic_sysclass); | |
585 | if (!error) | |
586 | error = sysdev_register(&device_lapic); | |
587 | return error; | |
588 | } | |
589 | device_initcall(init_lapic_sysfs); | |
590 | ||
591 | #else /* CONFIG_PM */ | |
592 | ||
593 | static void apic_pm_activate(void) { } | |
594 | ||
595 | #endif /* CONFIG_PM */ | |
596 | ||
597 | static int __init apic_set_verbosity(char *str) | |
598 | { | |
599 | if (strcmp("debug", str) == 0) | |
600 | apic_verbosity = APIC_DEBUG; | |
601 | else if (strcmp("verbose", str) == 0) | |
602 | apic_verbosity = APIC_VERBOSE; | |
603 | else | |
604 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
605 | " use apic=verbose or apic=debug", str); | |
606 | ||
607 | return 0; | |
608 | } | |
609 | ||
610 | __setup("apic=", apic_set_verbosity); | |
611 | ||
612 | /* | |
613 | * Detect and enable local APICs on non-SMP boards. | |
614 | * Original code written by Keir Fraser. | |
615 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
616 | * not correctly set up (usually the APIC timer won't work etc.) | |
617 | */ | |
618 | ||
619 | static int __init detect_init_APIC (void) | |
620 | { | |
621 | if (!cpu_has_apic) { | |
622 | printk(KERN_INFO "No local APIC present\n"); | |
623 | return -1; | |
624 | } | |
625 | ||
626 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
627 | boot_cpu_id = 0; | |
628 | return 0; | |
629 | } | |
630 | ||
631 | void __init init_apic_mappings(void) | |
632 | { | |
633 | unsigned long apic_phys; | |
634 | ||
635 | /* | |
636 | * If no local APIC can be found then set up a fake all | |
637 | * zeroes page to simulate the local APIC and another | |
638 | * one for the IO-APIC. | |
639 | */ | |
640 | if (!smp_found_config && detect_init_APIC()) { | |
641 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
642 | apic_phys = __pa(apic_phys); | |
643 | } else | |
644 | apic_phys = mp_lapic_addr; | |
645 | ||
646 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
647 | apic_printk(APIC_VERBOSE,"mapped APIC to %16lx (%16lx)\n", APIC_BASE, apic_phys); | |
648 | ||
649 | /* | |
650 | * Fetch the APIC ID of the BSP in case we have a | |
651 | * default configuration (or the MP table is broken). | |
652 | */ | |
653 | if (boot_cpu_id == -1U) | |
654 | boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID)); | |
655 | ||
656 | #ifdef CONFIG_X86_IO_APIC | |
657 | { | |
658 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
659 | int i; | |
660 | ||
661 | for (i = 0; i < nr_ioapics; i++) { | |
662 | if (smp_found_config) { | |
663 | ioapic_phys = mp_ioapics[i].mpc_apicaddr; | |
664 | } else { | |
665 | ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
666 | ioapic_phys = __pa(ioapic_phys); | |
667 | } | |
668 | set_fixmap_nocache(idx, ioapic_phys); | |
669 | apic_printk(APIC_VERBOSE,"mapped IOAPIC to %016lx (%016lx)\n", | |
670 | __fix_to_virt(idx), ioapic_phys); | |
671 | idx++; | |
672 | } | |
673 | } | |
674 | #endif | |
675 | } | |
676 | ||
677 | /* | |
678 | * This function sets up the local APIC timer, with a timeout of | |
679 | * 'clocks' APIC bus clock. During calibration we actually call | |
680 | * this function twice on the boot CPU, once with a bogus timeout | |
681 | * value, second time for real. The other (noncalibrating) CPUs | |
682 | * call this function only once, with the real, calibrated value. | |
683 | * | |
684 | * We do reads before writes even if unnecessary, to get around the | |
685 | * P5 APIC double write bug. | |
686 | */ | |
687 | ||
688 | #define APIC_DIVISOR 16 | |
689 | ||
690 | static void __setup_APIC_LVTT(unsigned int clocks) | |
691 | { | |
692 | unsigned int lvtt_value, tmp_value, ver; | |
693 | ||
694 | ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
695 | lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR; | |
696 | if (!APIC_INTEGRATED(ver)) | |
697 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
698 | apic_write_around(APIC_LVTT, lvtt_value); | |
699 | ||
700 | /* | |
701 | * Divide PICLK by 16 | |
702 | */ | |
703 | tmp_value = apic_read(APIC_TDCR); | |
704 | apic_write_around(APIC_TDCR, (tmp_value | |
705 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
706 | | APIC_TDR_DIV_16); | |
707 | ||
708 | apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR); | |
709 | } | |
710 | ||
711 | static void setup_APIC_timer(unsigned int clocks) | |
712 | { | |
713 | unsigned long flags; | |
714 | ||
715 | local_irq_save(flags); | |
716 | ||
717 | /* For some reasons this doesn't work on Simics, so fake it for now */ | |
718 | if (!strstr(boot_cpu_data.x86_model_id, "Screwdriver")) { | |
719 | __setup_APIC_LVTT(clocks); | |
720 | return; | |
721 | } | |
722 | ||
723 | /* wait for irq slice */ | |
724 | if (vxtime.hpet_address) { | |
725 | int trigger = hpet_readl(HPET_T0_CMP); | |
726 | while (hpet_readl(HPET_COUNTER) >= trigger) | |
727 | /* do nothing */ ; | |
728 | while (hpet_readl(HPET_COUNTER) < trigger) | |
729 | /* do nothing */ ; | |
730 | } else { | |
731 | int c1, c2; | |
732 | outb_p(0x00, 0x43); | |
733 | c2 = inb_p(0x40); | |
734 | c2 |= inb_p(0x40) << 8; | |
735 | do { | |
736 | c1 = c2; | |
737 | outb_p(0x00, 0x43); | |
738 | c2 = inb_p(0x40); | |
739 | c2 |= inb_p(0x40) << 8; | |
740 | } while (c2 - c1 < 300); | |
741 | } | |
742 | ||
743 | __setup_APIC_LVTT(clocks); | |
744 | ||
745 | local_irq_restore(flags); | |
746 | } | |
747 | ||
748 | /* | |
749 | * In this function we calibrate APIC bus clocks to the external | |
750 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
751 | * to calibrate, since some later bootup code depends on getting | |
752 | * the first irq? Ugh. | |
753 | * | |
754 | * We want to do the calibration only once since we | |
755 | * want to have local timer irqs syncron. CPUs connected | |
756 | * by the same APIC bus have the very same bus frequency. | |
757 | * And we want to have irqs off anyways, no accidental | |
758 | * APIC irq that way. | |
759 | */ | |
760 | ||
761 | #define TICK_COUNT 100000000 | |
762 | ||
763 | static int __init calibrate_APIC_clock(void) | |
764 | { | |
765 | int apic, apic_start, tsc, tsc_start; | |
766 | int result; | |
767 | /* | |
768 | * Put whatever arbitrary (but long enough) timeout | |
769 | * value into the APIC clock, we just want to get the | |
770 | * counter running for calibration. | |
771 | */ | |
772 | __setup_APIC_LVTT(1000000000); | |
773 | ||
774 | apic_start = apic_read(APIC_TMCCT); | |
775 | rdtscl(tsc_start); | |
776 | ||
777 | do { | |
778 | apic = apic_read(APIC_TMCCT); | |
779 | rdtscl(tsc); | |
780 | } while ((tsc - tsc_start) < TICK_COUNT && (apic - apic_start) < TICK_COUNT); | |
781 | ||
782 | result = (apic_start - apic) * 1000L * cpu_khz / (tsc - tsc_start); | |
783 | ||
784 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
785 | result / 1000 / 1000, result / 1000 % 1000); | |
786 | ||
787 | return result * APIC_DIVISOR / HZ; | |
788 | } | |
789 | ||
790 | static unsigned int calibration_result; | |
791 | ||
792 | void __init setup_boot_APIC_clock (void) | |
793 | { | |
794 | if (disable_apic_timer) { | |
795 | printk(KERN_INFO "Disabling APIC timer\n"); | |
796 | return; | |
797 | } | |
798 | ||
799 | printk(KERN_INFO "Using local APIC timer interrupts.\n"); | |
800 | using_apic_timer = 1; | |
801 | ||
802 | local_irq_disable(); | |
803 | ||
804 | calibration_result = calibrate_APIC_clock(); | |
805 | /* | |
806 | * Now set up the timer for real. | |
807 | */ | |
808 | setup_APIC_timer(calibration_result); | |
809 | ||
810 | local_irq_enable(); | |
811 | } | |
812 | ||
e6982c67 | 813 | void __cpuinit setup_secondary_APIC_clock(void) |
1da177e4 LT |
814 | { |
815 | local_irq_disable(); /* FIXME: Do we need this? --RR */ | |
816 | setup_APIC_timer(calibration_result); | |
817 | local_irq_enable(); | |
818 | } | |
819 | ||
e6982c67 | 820 | void __cpuinit disable_APIC_timer(void) |
1da177e4 LT |
821 | { |
822 | if (using_apic_timer) { | |
823 | unsigned long v; | |
824 | ||
825 | v = apic_read(APIC_LVTT); | |
826 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); | |
827 | } | |
828 | } | |
829 | ||
830 | void enable_APIC_timer(void) | |
831 | { | |
832 | if (using_apic_timer) { | |
833 | unsigned long v; | |
834 | ||
835 | v = apic_read(APIC_LVTT); | |
836 | apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED); | |
837 | } | |
838 | } | |
839 | ||
840 | /* | |
841 | * the frequency of the profiling timer can be changed | |
842 | * by writing a multiplier value into /proc/profile. | |
843 | */ | |
844 | int setup_profiling_timer(unsigned int multiplier) | |
845 | { | |
846 | int i; | |
847 | ||
848 | /* | |
849 | * Sanity check. [at least 500 APIC cycles should be | |
850 | * between APIC interrupts as a rule of thumb, to avoid | |
851 | * irqs flooding us] | |
852 | */ | |
853 | if ( (!multiplier) || (calibration_result/multiplier < 500)) | |
854 | return -EINVAL; | |
855 | ||
856 | /* | |
857 | * Set the new multiplier for each CPU. CPUs don't start using the | |
858 | * new values until the next timer interrupt in which they do process | |
859 | * accounting. At that time they also adjust their APIC timers | |
860 | * accordingly. | |
861 | */ | |
862 | for (i = 0; i < NR_CPUS; ++i) | |
863 | per_cpu(prof_multiplier, i) = multiplier; | |
864 | ||
865 | return 0; | |
866 | } | |
867 | ||
868 | #undef APIC_DIVISOR | |
869 | ||
870 | /* | |
871 | * Local timer interrupt handler. It does both profiling and | |
872 | * process statistics/rescheduling. | |
873 | * | |
874 | * We do profiling in every local tick, statistics/rescheduling | |
875 | * happen only every 'profiling multiplier' ticks. The default | |
876 | * multiplier is 1 and it can be changed by writing the new multiplier | |
877 | * value into /proc/profile. | |
878 | */ | |
879 | ||
880 | void smp_local_timer_interrupt(struct pt_regs *regs) | |
881 | { | |
882 | int cpu = smp_processor_id(); | |
883 | ||
884 | profile_tick(CPU_PROFILING, regs); | |
885 | if (--per_cpu(prof_counter, cpu) <= 0) { | |
886 | /* | |
887 | * The multiplier may have changed since the last time we got | |
888 | * to this point as a result of the user writing to | |
889 | * /proc/profile. In this case we need to adjust the APIC | |
890 | * timer accordingly. | |
891 | * | |
892 | * Interrupts are already masked off at this point. | |
893 | */ | |
894 | per_cpu(prof_counter, cpu) = per_cpu(prof_multiplier, cpu); | |
895 | if (per_cpu(prof_counter, cpu) != | |
896 | per_cpu(prof_old_multiplier, cpu)) { | |
897 | __setup_APIC_LVTT(calibration_result/ | |
898 | per_cpu(prof_counter, cpu)); | |
899 | per_cpu(prof_old_multiplier, cpu) = | |
900 | per_cpu(prof_counter, cpu); | |
901 | } | |
902 | ||
903 | #ifdef CONFIG_SMP | |
904 | update_process_times(user_mode(regs)); | |
905 | #endif | |
906 | } | |
907 | ||
908 | /* | |
909 | * We take the 'long' return path, and there every subsystem | |
910 | * grabs the appropriate locks (kernel lock/ irq lock). | |
911 | * | |
912 | * we might want to decouple profiling from the 'long path', | |
913 | * and do the profiling totally in assembly. | |
914 | * | |
915 | * Currently this isn't too much of an issue (performance wise), | |
916 | * we can take more than 100K local irqs per second on a 100 MHz P5. | |
917 | */ | |
918 | } | |
919 | ||
920 | /* | |
921 | * Local APIC timer interrupt. This is the most natural way for doing | |
922 | * local interrupts, but local timer interrupts can be emulated by | |
923 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
924 | * | |
925 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
926 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
927 | */ | |
928 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
929 | { | |
930 | /* | |
931 | * the NMI deadlock-detector uses this. | |
932 | */ | |
933 | add_pda(apic_timer_irqs, 1); | |
934 | ||
935 | /* | |
936 | * NOTE! We'd better ACK the irq immediately, | |
937 | * because timer handling can be slow. | |
938 | */ | |
939 | ack_APIC_irq(); | |
940 | /* | |
941 | * update_process_times() expects us to have done irq_enter(). | |
942 | * Besides, if we don't timer interrupts ignore the global | |
943 | * interrupt lock, which is the WrongThing (tm) to do. | |
944 | */ | |
945 | irq_enter(); | |
946 | smp_local_timer_interrupt(regs); | |
947 | irq_exit(); | |
948 | } | |
949 | ||
950 | /* | |
951 | * oem_force_hpet_timer -- force HPET mode for some boxes. | |
952 | * | |
953 | * Thus far, the major user of this is IBM's Summit2 series: | |
954 | * | |
955 | * Clustered boxes may have unsynced TSC problems if they are | |
956 | * multi-chassis. Use available data to take a good guess. | |
957 | * If in doubt, go HPET. | |
958 | */ | |
959 | __init int oem_force_hpet_timer(void) | |
960 | { | |
961 | int i, clusters, zeros; | |
962 | unsigned id; | |
963 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); | |
964 | ||
376ec33f | 965 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
966 | |
967 | for (i = 0; i < NR_CPUS; i++) { | |
968 | id = bios_cpu_apicid[i]; | |
969 | if (id != BAD_APICID) | |
970 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
971 | } | |
972 | ||
973 | /* Problem: Partially populated chassis may not have CPUs in some of | |
974 | * the APIC clusters they have been allocated. Only present CPUs have | |
975 | * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since | |
976 | * clusters are allocated sequentially, count zeros only if they are | |
977 | * bounded by ones. | |
978 | */ | |
979 | clusters = 0; | |
980 | zeros = 0; | |
981 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
982 | if (test_bit(i, clustermap)) { | |
983 | clusters += 1 + zeros; | |
984 | zeros = 0; | |
985 | } else | |
986 | ++zeros; | |
987 | } | |
988 | ||
989 | /* | |
990 | * If clusters > 2, then should be multi-chassis. Return 1 for HPET. | |
991 | * Else return 0 to use TSC. | |
992 | * May have to revisit this when multi-core + hyperthreaded CPUs come | |
993 | * out, but AFAIK this will work even for them. | |
994 | */ | |
995 | return (clusters > 2); | |
996 | } | |
997 | ||
998 | /* | |
999 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1000 | */ | |
1001 | asmlinkage void smp_spurious_interrupt(void) | |
1002 | { | |
1003 | unsigned int v; | |
1004 | irq_enter(); | |
1005 | /* | |
1006 | * Check if this really is a spurious interrupt and ACK it | |
1007 | * if it is a vectored one. Just in case... | |
1008 | * Spurious interrupts should not be ACKed. | |
1009 | */ | |
1010 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
1011 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1012 | ack_APIC_irq(); | |
1013 | ||
1014 | #if 0 | |
1015 | static unsigned long last_warning; | |
1016 | static unsigned long skipped; | |
1017 | ||
1018 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
1019 | if (time_before(last_warning+30*HZ,jiffies)) { | |
1020 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, %ld skipped.\n", | |
1021 | smp_processor_id(), skipped); | |
1022 | last_warning = jiffies; | |
1023 | skipped = 0; | |
1024 | } else { | |
1025 | skipped++; | |
1026 | } | |
1027 | #endif | |
1028 | irq_exit(); | |
1029 | } | |
1030 | ||
1031 | /* | |
1032 | * This interrupt should never happen with our APIC/SMP architecture | |
1033 | */ | |
1034 | ||
1035 | asmlinkage void smp_error_interrupt(void) | |
1036 | { | |
1037 | unsigned int v, v1; | |
1038 | ||
1039 | irq_enter(); | |
1040 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1041 | v = apic_read(APIC_ESR); | |
1042 | apic_write(APIC_ESR, 0); | |
1043 | v1 = apic_read(APIC_ESR); | |
1044 | ack_APIC_irq(); | |
1045 | atomic_inc(&irq_err_count); | |
1046 | ||
1047 | /* Here is what the APIC error bits mean: | |
1048 | 0: Send CS error | |
1049 | 1: Receive CS error | |
1050 | 2: Send accept error | |
1051 | 3: Receive accept error | |
1052 | 4: Reserved | |
1053 | 5: Send illegal vector | |
1054 | 6: Received illegal vector | |
1055 | 7: Illegal register address | |
1056 | */ | |
1057 | printk (KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1058 | smp_processor_id(), v , v1); | |
1059 | irq_exit(); | |
1060 | } | |
1061 | ||
1062 | int disable_apic; | |
1063 | ||
1064 | /* | |
1065 | * This initializes the IO-APIC and APIC hardware if this is | |
1066 | * a UP kernel. | |
1067 | */ | |
1068 | int __init APIC_init_uniprocessor (void) | |
1069 | { | |
1070 | if (disable_apic) { | |
1071 | printk(KERN_INFO "Apic disabled\n"); | |
1072 | return -1; | |
1073 | } | |
1074 | if (!cpu_has_apic) { | |
1075 | disable_apic = 1; | |
1076 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
1077 | return -1; | |
1078 | } | |
1079 | ||
1080 | verify_local_APIC(); | |
1081 | ||
1082 | connect_bsp_APIC(); | |
1083 | ||
1084 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1085 | apic_write_around(APIC_ID, boot_cpu_id); | |
1086 | ||
1087 | setup_local_APIC(); | |
1088 | ||
1089 | #ifdef CONFIG_X86_IO_APIC | |
1090 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) | |
1091 | setup_IO_APIC(); | |
1092 | else | |
1093 | nr_ioapics = 0; | |
1094 | #endif | |
1095 | setup_boot_APIC_clock(); | |
75152114 | 1096 | check_nmi_watchdog(); |
1da177e4 LT |
1097 | return 0; |
1098 | } | |
1099 | ||
1100 | static __init int setup_disableapic(char *str) | |
1101 | { | |
1102 | disable_apic = 1; | |
1103 | return 0; | |
1104 | } | |
1105 | ||
1106 | static __init int setup_nolapic(char *str) | |
1107 | { | |
1108 | disable_apic = 1; | |
1109 | return 0; | |
1110 | } | |
1111 | ||
1112 | static __init int setup_noapictimer(char *str) | |
1113 | { | |
1114 | disable_apic_timer = 1; | |
1115 | return 0; | |
1116 | } | |
1117 | ||
1118 | /* dummy parsing: see setup.c */ | |
1119 | ||
1120 | __setup("disableapic", setup_disableapic); | |
1121 | __setup("nolapic", setup_nolapic); /* same as disableapic, for compatibility */ | |
1122 | ||
1123 | __setup("noapictimer", setup_noapictimer); | |
1124 | ||
1125 | /* no "lapic" flag - we only use the lapic when the BIOS tells us so. */ |