Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit | |
3 | * | |
4 | * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE | |
5 | * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> | |
6 | * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> | |
7 | * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> | |
1da177e4 LT |
8 | */ |
9 | ||
10 | ||
11 | #include <linux/linkage.h> | |
12 | #include <linux/threads.h> | |
f6c2e333 | 13 | #include <linux/init.h> |
1da177e4 LT |
14 | #include <asm/desc.h> |
15 | #include <asm/segment.h> | |
67dcbb6b | 16 | #include <asm/pgtable.h> |
1da177e4 LT |
17 | #include <asm/page.h> |
18 | #include <asm/msr.h> | |
19 | #include <asm/cache.h> | |
20 | ||
21 | /* we are not able to switch in one step to the final KERNEL ADRESS SPACE | |
22 | * because we need identity-mapped pages on setup so define __START_KERNEL to | |
23 | * 0x100000 for this stage | |
24 | * | |
25 | */ | |
26 | ||
27 | .text | |
eaeae0cc | 28 | .section .bootstrap.text |
1da177e4 LT |
29 | .code32 |
30 | .globl startup_32 | |
31 | /* %bx: 1 if coming from smp trampoline on secondary cpu */ | |
32 | startup_32: | |
33 | ||
34 | /* | |
35 | * At this point the CPU runs in 32bit protected mode (CS.D = 1) with | |
36 | * paging disabled and the point of this file is to switch to 64bit | |
37 | * long mode with a kernel mapping for kerneland to jump into the | |
38 | * kernel virtual addresses. | |
39 | * There is no stack until we set one up. | |
40 | */ | |
41 | ||
42 | /* Initialize the %ds segment register */ | |
43 | movl $__KERNEL_DS,%eax | |
44 | movl %eax,%ds | |
45 | ||
46 | /* Load new GDT with the 64bit segments using 32bit descriptor */ | |
47 | lgdt pGDT32 - __START_KERNEL_map | |
48 | ||
49 | /* If the CPU doesn't support CPUID this will double fault. | |
50 | * Unfortunately it is hard to check for CPUID without a stack. | |
51 | */ | |
52 | ||
53 | /* Check if extended functions are implemented */ | |
54 | movl $0x80000000, %eax | |
55 | cpuid | |
56 | cmpl $0x80000000, %eax | |
57 | jbe no_long_mode | |
58 | /* Check if long mode is implemented */ | |
59 | mov $0x80000001, %eax | |
60 | cpuid | |
61 | btl $29, %edx | |
62 | jnc no_long_mode | |
63 | ||
64 | /* | |
65 | * Prepare for entering 64bits mode | |
66 | */ | |
67 | ||
68 | /* Enable PAE mode */ | |
69 | xorl %eax, %eax | |
70 | btsl $5, %eax | |
71 | movl %eax, %cr4 | |
72 | ||
73 | /* Setup early boot stage 4 level pagetables */ | |
cfd243d4 | 74 | movl $(init_level4_pgt - __START_KERNEL_map), %eax |
1da177e4 LT |
75 | movl %eax, %cr3 |
76 | ||
77 | /* Setup EFER (Extended Feature Enable Register) */ | |
78 | movl $MSR_EFER, %ecx | |
79 | rdmsr | |
80 | ||
81 | /* Enable Long Mode */ | |
82 | btsl $_EFER_LME, %eax | |
83 | ||
84 | /* Make changes effective */ | |
85 | wrmsr | |
86 | ||
87 | xorl %eax, %eax | |
88 | btsl $31, %eax /* Enable paging and in turn activate Long Mode */ | |
89 | btsl $0, %eax /* Enable protected mode */ | |
90 | /* Make changes effective */ | |
91 | movl %eax, %cr0 | |
92 | /* | |
93 | * At this point we're in long mode but in 32bit compatibility mode | |
94 | * with EFER.LME = 1, CS.L = 0, CS.D = 1 (and in turn | |
95 | * EFER.LMA = 1). Now we want to jump in 64bit mode, to do that we use | |
96 | * the new gdt/idt that has __KERNEL_CS with CS.L = 1. | |
97 | */ | |
98 | ljmp $__KERNEL_CS, $(startup_64 - __START_KERNEL_map) | |
99 | ||
100 | .code64 | |
101 | .org 0x100 | |
102 | .globl startup_64 | |
103 | startup_64: | |
90b1c208 | 104 | ENTRY(secondary_startup_64) |
1da177e4 LT |
105 | /* We come here either from startup_32 |
106 | * or directly from a 64bit bootloader. | |
107 | * Since we may have come directly from a bootloader we | |
108 | * reload the page tables here. | |
109 | */ | |
110 | ||
111 | /* Enable PAE mode and PGE */ | |
112 | xorq %rax, %rax | |
113 | btsq $5, %rax | |
114 | btsq $7, %rax | |
115 | movq %rax, %cr4 | |
116 | ||
117 | /* Setup early boot stage 4 level pagetables. */ | |
cfd243d4 | 118 | movq $(init_level4_pgt - __START_KERNEL_map), %rax |
1da177e4 LT |
119 | movq %rax, %cr3 |
120 | ||
121 | /* Check if nx is implemented */ | |
122 | movl $0x80000001, %eax | |
123 | cpuid | |
124 | movl %edx,%edi | |
125 | ||
126 | /* Setup EFER (Extended Feature Enable Register) */ | |
127 | movl $MSR_EFER, %ecx | |
128 | rdmsr | |
129 | ||
130 | /* Enable System Call */ | |
131 | btsl $_EFER_SCE, %eax | |
132 | ||
133 | /* No Execute supported? */ | |
134 | btl $20,%edi | |
135 | jnc 1f | |
136 | btsl $_EFER_NX, %eax | |
137 | 1: | |
138 | /* Make changes effective */ | |
139 | wrmsr | |
140 | ||
141 | /* Setup cr0 */ | |
3829ee6b AK |
142 | #define CR0_PM 1 /* protected mode */ |
143 | #define CR0_MP (1<<1) | |
144 | #define CR0_ET (1<<4) | |
145 | #define CR0_NE (1<<5) | |
146 | #define CR0_WP (1<<16) | |
147 | #define CR0_AM (1<<18) | |
148 | #define CR0_PAGING (1<<31) | |
149 | movl $CR0_PM|CR0_MP|CR0_ET|CR0_NE|CR0_WP|CR0_AM|CR0_PAGING,%eax | |
1da177e4 LT |
150 | /* Make changes effective */ |
151 | movq %rax, %cr0 | |
152 | ||
153 | /* Setup a boot time stack */ | |
154 | movq init_rsp(%rip),%rsp | |
155 | ||
156 | /* zero EFLAGS after setting rsp */ | |
157 | pushq $0 | |
158 | popfq | |
159 | ||
160 | /* | |
161 | * We must switch to a new descriptor in kernel space for the GDT | |
162 | * because soon the kernel won't have access anymore to the userspace | |
163 | * addresses where we're currently running on. We have to do that here | |
164 | * because in 32bit we couldn't load a 64bit linear address. | |
165 | */ | |
166 | lgdt cpu_gdt_descr | |
167 | ||
ffb60175 ZA |
168 | /* set up data segments. actually 0 would do too */ |
169 | movl $__KERNEL_DS,%eax | |
170 | movl %eax,%ds | |
171 | movl %eax,%ss | |
172 | movl %eax,%es | |
173 | ||
174 | /* | |
175 | * We don't really need to load %fs or %gs, but load them anyway | |
176 | * to kill any stale realmode selectors. This allows execution | |
177 | * under VT hardware. | |
178 | */ | |
179 | movl %eax,%fs | |
180 | movl %eax,%gs | |
181 | ||
1da177e4 LT |
182 | /* |
183 | * Setup up a dummy PDA. this is just for some early bootup code | |
184 | * that does in_interrupt() | |
185 | */ | |
186 | movl $MSR_GS_BASE,%ecx | |
187 | movq $empty_zero_page,%rax | |
188 | movq %rax,%rdx | |
189 | shrq $32,%rdx | |
190 | wrmsr | |
191 | ||
1da177e4 LT |
192 | /* esi is pointer to real mode structure with interesting info. |
193 | pass it to C */ | |
194 | movl %esi, %edi | |
195 | ||
196 | /* Finally jump to run C code and to be on real kernel address | |
197 | * Since we are running on identity-mapped space we have to jump | |
26374c7b EB |
198 | * to the full 64bit address, this is only possible as indirect |
199 | * jump. In addition we need to ensure %cs is set so we make this | |
200 | * a far return. | |
1da177e4 LT |
201 | */ |
202 | movq initial_code(%rip),%rax | |
26374c7b EB |
203 | pushq $0 # fake return address to stop unwinder |
204 | pushq $__KERNEL_CS # set correct cs | |
205 | pushq %rax # target address in negative space | |
206 | lretq | |
1da177e4 | 207 | |
e57113bc JB |
208 | /* SMP bootup changes these two */ |
209 | .align 8 | |
1da177e4 LT |
210 | .globl initial_code |
211 | initial_code: | |
212 | .quad x86_64_start_kernel | |
213 | .globl init_rsp | |
214 | init_rsp: | |
215 | .quad init_thread_union+THREAD_SIZE-8 | |
216 | ||
217 | ENTRY(early_idt_handler) | |
b957591f AK |
218 | cmpl $2,early_recursion_flag(%rip) |
219 | jz 1f | |
220 | incl early_recursion_flag(%rip) | |
1da177e4 LT |
221 | xorl %eax,%eax |
222 | movq 8(%rsp),%rsi # get rip | |
223 | movq (%rsp),%rdx | |
224 | movq %cr2,%rcx | |
225 | leaq early_idt_msg(%rip),%rdi | |
226 | call early_printk | |
b957591f AK |
227 | cmpl $2,early_recursion_flag(%rip) |
228 | jz 1f | |
229 | call dump_stack | |
6574ffd7 AK |
230 | #ifdef CONFIG_KALLSYMS |
231 | leaq early_idt_ripmsg(%rip),%rdi | |
232 | movq 8(%rsp),%rsi # get rip again | |
233 | call __print_symbol | |
234 | #endif | |
1da177e4 LT |
235 | 1: hlt |
236 | jmp 1b | |
b957591f AK |
237 | early_recursion_flag: |
238 | .long 0 | |
1da177e4 LT |
239 | |
240 | early_idt_msg: | |
241 | .asciz "PANIC: early exception rip %lx error %lx cr2 %lx\n" | |
6574ffd7 AK |
242 | early_idt_ripmsg: |
243 | .asciz "RIP %s\n" | |
1da177e4 LT |
244 | |
245 | .code32 | |
246 | ENTRY(no_long_mode) | |
247 | /* This isn't an x86-64 CPU so hang */ | |
248 | 1: | |
249 | jmp 1b | |
250 | ||
251 | .org 0xf00 | |
252 | .globl pGDT32 | |
253 | pGDT32: | |
e57113bc | 254 | .word gdt_end-cpu_gdt_table-1 |
1da177e4 LT |
255 | .long cpu_gdt_table-__START_KERNEL_map |
256 | ||
257 | .org 0xf10 | |
258 | ljumpvector: | |
259 | .long startup_64-__START_KERNEL_map | |
260 | .word __KERNEL_CS | |
261 | ||
262 | ENTRY(stext) | |
263 | ENTRY(_stext) | |
264 | ||
f0cf5d1a | 265 | #define NEXT_PAGE(name) \ |
67dcbb6b | 266 | .balign PAGE_SIZE; \ |
f0cf5d1a JB |
267 | ENTRY(name) |
268 | ||
67dcbb6b VG |
269 | /* Automate the creation of 1 to 1 mapping pmd entries */ |
270 | #define PMDS(START, PERM, COUNT) \ | |
271 | i = 0 ; \ | |
272 | .rept (COUNT) ; \ | |
273 | .quad (START) + (i << 21) + (PERM) ; \ | |
274 | i = i + 1 ; \ | |
275 | .endr | |
276 | ||
cfd243d4 VG |
277 | /* |
278 | * This default setting generates an ident mapping at address 0x100000 | |
279 | * and a mapping for the kernel that precisely maps virtual address | |
280 | * 0xffffffff80000000 to physical address 0x000000. (always using | |
281 | * 2Mbyte large pages provided by PAE mode) | |
282 | */ | |
f0cf5d1a | 283 | NEXT_PAGE(init_level4_pgt) |
cfd243d4 VG |
284 | .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE |
285 | .fill 257,8,0 | |
286 | .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE | |
287 | .fill 252,8,0 | |
288 | /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ | |
289 | .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE | |
1da177e4 | 290 | |
f0cf5d1a | 291 | NEXT_PAGE(level3_ident_pgt) |
67dcbb6b | 292 | .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE |
1da177e4 LT |
293 | .fill 511,8,0 |
294 | ||
f0cf5d1a | 295 | NEXT_PAGE(level3_kernel_pgt) |
1da177e4 LT |
296 | .fill 510,8,0 |
297 | /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ | |
67dcbb6b | 298 | .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE |
1da177e4 LT |
299 | .fill 1,8,0 |
300 | ||
f0cf5d1a | 301 | NEXT_PAGE(level2_ident_pgt) |
67dcbb6b VG |
302 | /* Since I easily can, map the first 1G. |
303 | * Don't set NX because code runs from these pages. | |
304 | */ | |
305 | PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC, PTRS_PER_PMD) | |
1da177e4 | 306 | |
f0cf5d1a | 307 | NEXT_PAGE(level2_kernel_pgt) |
1da177e4 LT |
308 | /* 40MB kernel mapping. The kernel code cannot be bigger than that. |
309 | When you change this change KERNEL_TEXT_SIZE in page.h too. */ | |
310 | /* (2^48-(2*1024*1024*1024)-((2^39)*511)-((2^30)*510)) = 0 */ | |
67dcbb6b VG |
311 | PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC|_PAGE_GLOBAL, |
312 | KERNEL_TEXT_SIZE/PMD_SIZE) | |
1da177e4 | 313 | /* Module mapping starts here */ |
67dcbb6b | 314 | .fill (PTRS_PER_PMD - (KERNEL_TEXT_SIZE/PMD_SIZE)),8,0 |
1da177e4 | 315 | |
67dcbb6b | 316 | #undef PMDS |
f0cf5d1a | 317 | #undef NEXT_PAGE |
1da177e4 | 318 | |
f0cf5d1a | 319 | .data |
1da177e4 LT |
320 | .align 16 |
321 | .globl cpu_gdt_descr | |
322 | cpu_gdt_descr: | |
e57113bc | 323 | .word gdt_end-cpu_gdt_table-1 |
1da177e4 LT |
324 | gdt: |
325 | .quad cpu_gdt_table | |
326 | #ifdef CONFIG_SMP | |
327 | .rept NR_CPUS-1 | |
328 | .word 0 | |
329 | .quad 0 | |
330 | .endr | |
331 | #endif | |
332 | ||
333 | /* We need valid kernel segments for data and code in long mode too | |
334 | * IRET will check the segment types kkeil 2000/10/28 | |
335 | * Also sysret mandates a special GDT layout | |
336 | */ | |
337 | ||
e57113bc JB |
338 | .section .data.page_aligned, "aw" |
339 | .align PAGE_SIZE | |
1da177e4 LT |
340 | |
341 | /* The TLS descriptors are currently at a different place compared to i386. | |
342 | Hopefully nobody expects them at a fixed place (Wine?) */ | |
343 | ||
344 | ENTRY(cpu_gdt_table) | |
345 | .quad 0x0000000000000000 /* NULL descriptor */ | |
30f47289 VG |
346 | .quad 0x00cf9b000000ffff /* __KERNEL32_CS */ |
347 | .quad 0x00af9b000000ffff /* __KERNEL_CS */ | |
348 | .quad 0x00cf93000000ffff /* __KERNEL_DS */ | |
349 | .quad 0x00cffb000000ffff /* __USER32_CS */ | |
350 | .quad 0x00cff3000000ffff /* __USER_DS, __USER32_DS */ | |
351 | .quad 0x00affb000000ffff /* __USER_CS */ | |
cdc4b9c0 | 352 | .quad 0x0 /* unused */ |
1da177e4 LT |
353 | .quad 0,0 /* TSS */ |
354 | .quad 0,0 /* LDT */ | |
355 | .quad 0,0,0 /* three TLS descriptors */ | |
c08c8205 | 356 | .quad 0x0000f40000000000 /* node/CPU stored in limit */ |
1da177e4 LT |
357 | gdt_end: |
358 | /* asm/segment.h:GDT_ENTRIES must match this */ | |
359 | /* This should be a multiple of the cache line size */ | |
c11efdf9 RT |
360 | /* GDTs of other CPUs are now dynamically allocated */ |
361 | ||
362 | /* zero the remaining page */ | |
363 | .fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0 | |
1da177e4 | 364 | |
e57113bc JB |
365 | .section .bss, "aw", @nobits |
366 | .align L1_CACHE_BYTES | |
367 | ENTRY(idt_table) | |
368 | .skip 256 * 16 | |
1da177e4 | 369 | |
e57113bc JB |
370 | .section .bss.page_aligned, "aw", @nobits |
371 | .align PAGE_SIZE | |
372 | ENTRY(empty_zero_page) | |
373 | .skip PAGE_SIZE |