[deliverable/linux.git] / arch / x86_64 / kernel / head.S

/*
 *  linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
 *
 *  Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
 *  Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
 *  Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
 *  Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
 *  Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
 */


#include <linux/linkage.h>
#include <linux/threads.h>
#include <linux/init.h>
#include <asm/desc.h>
#include <asm/segment.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/msr.h>
#include <asm/cache.h>

/* we are not able to switch in one step to the final KERNEL ADRESS SPACE
 * because we need identity-mapped pages.
 *
 */

	.text
	.section .bootstrap.text
	.code64
	.globl startup_64
startup_64:

	/*
	 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
	 * and someone has loaded an identity mapped page table
	 * for us.  These identity mapped page tables map all of the
	 * kernel pages and possibly all of memory.
	 *
	 * %esi holds a physical pointer to real_mode_data.
	 *
	 * We come here either directly from a 64bit bootloader, or from
	 * arch/x86_64/boot/compressed/head.S.
	 *
	 * We only come here initially at boot nothing else comes here.
	 *
	 * Since we may be loaded at an address different from what we were
	 * compiled to run at we first fixup the physical addresses in our page
	 * tables and then reload them.
	 */

	/* Compute the delta between the address I am compiled to run at and the
	 * address I am actually running at.
	 */
	leaq	_text(%rip), %rbp
	subq	$_text - __START_KERNEL_map, %rbp

	/* Is the address not 2M aligned? */
	movq	%rbp, %rax
	andl	$~LARGE_PAGE_MASK, %eax
	testl	%eax, %eax
	jnz	bad_address

	/* Is the address too large? */
	leaq	_text(%rip), %rdx
	movq	$PGDIR_SIZE, %rax
	cmpq	%rax, %rdx
	jae	bad_address

	/* Fixup the physical addresses in the page table
	 */
	addq	%rbp, init_level4_pgt + 0(%rip)
	addq	%rbp, init_level4_pgt + (258*8)(%rip)
	addq	%rbp, init_level4_pgt + (511*8)(%rip)

	addq	%rbp, level3_ident_pgt + 0(%rip)
	addq	%rbp, level3_kernel_pgt + (510*8)(%rip)

	/* Add an Identity mapping if I am above 1G */
	leaq	_text(%rip), %rdi
	andq	$LARGE_PAGE_MASK, %rdi

	movq	%rdi, %rax
	shrq	$PUD_SHIFT, %rax
	andq	$(PTRS_PER_PUD - 1), %rax
	jz	ident_complete

	leaq	(level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx
	leaq	level3_ident_pgt(%rip), %rbx
	movq	%rdx, 0(%rbx, %rax, 8)

	movq	%rdi, %rax
	shrq	$PMD_SHIFT, %rax
	andq	$(PTRS_PER_PMD - 1), %rax
	leaq	__PAGE_KERNEL_LARGE_EXEC(%rdi), %rdx
	leaq	level2_spare_pgt(%rip), %rbx
	movq	%rdx, 0(%rbx, %rax, 8)
ident_complete:

	/* Fixup the kernel text+data virtual addresses
	 */
	leaq	level2_kernel_pgt(%rip), %rdi
	leaq	4096(%rdi), %r8
	/* See if it is a valid page table entry */
1:	testq	$1, 0(%rdi)
	jz	2f
	addq	%rbp, 0(%rdi)
	/* Go to the next page */
2:	addq	$8, %rdi
	cmp	%r8, %rdi
	jne	1b

	/* Fixup phys_base */
	addq	%rbp, phys_base(%rip)

#ifdef CONFIG_SMP
	addq	%rbp, trampoline_level4_pgt + 0(%rip)
	addq	%rbp, trampoline_level4_pgt + (511*8)(%rip)
#endif
#ifdef CONFIG_ACPI_SLEEP
	addq	%rbp, wakeup_level4_pgt + 0(%rip)
	addq	%rbp, wakeup_level4_pgt + (511*8)(%rip)
#endif

	/* Due to ENTRY(), sometimes the empty space gets filled with
	 * zeros. Better take a jmp than relying on empty space being
	 * filled with 0x90 (nop)
	 */
	jmp secondary_startup_64
ENTRY(secondary_startup_64)
	/*
	 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
	 * and someone has loaded a mapped page table.
	 *
	 * %esi holds a physical pointer to real_mode_data.
	 *
	 * We come here either from startup_64 (using physical addresses)
	 * or from trampoline.S (using virtual addresses).
	 *
	 * Using virtual addresses from trampoline.S removes the need
	 * to have any identity mapped pages in the kernel page table
	 * after the boot processor executes this code.
	 */

	/* Enable PAE mode and PGE */
	xorq	%rax, %rax
	btsq	$5, %rax
	btsq	$7, %rax
	movq	%rax, %cr4

	/* Setup early boot stage 4 level pagetables. */
	movq	$(init_level4_pgt - __START_KERNEL_map), %rax
	addq	phys_base(%rip), %rax
	movq	%rax, %cr3

	/* Ensure I am executing from virtual addresses */
	movq	$1f, %rax
	jmp	*%rax
1:

	/* Check if nx is implemented */
	movl	$0x80000001, %eax
	cpuid
	movl	%edx,%edi

	/* Setup EFER (Extended Feature Enable Register) */
	movl	$MSR_EFER, %ecx
	rdmsr
	btsl	$_EFER_SCE, %eax	/* Enable System Call */
	btl	$20,%edi		/* No Execute supported? */
	jnc     1f
	btsl	$_EFER_NX, %eax
1:	wrmsr				/* Make changes effective */

	/* Setup cr0 */
#define CR0_PM				1		/* protected mode */
#define CR0_MP				(1<<1)
#define CR0_ET				(1<<4)
#define CR0_NE				(1<<5)
#define CR0_WP				(1<<16)
#define CR0_AM				(1<<18)
#define CR0_PAGING 			(1<<31)
	movl $CR0_PM|CR0_MP|CR0_ET|CR0_NE|CR0_WP|CR0_AM|CR0_PAGING,%eax
	/* Make changes effective */
	movq	%rax, %cr0

	/* Setup a boot time stack */
	movq init_rsp(%rip),%rsp

	/* zero EFLAGS after setting rsp */
	pushq $0
	popfq

	/*
	 * We must switch to a new descriptor in kernel space for the GDT
	 * because soon the kernel won't have access anymore to the userspace
	 * addresses where we're currently running on. We have to do that here
	 * because in 32bit we couldn't load a 64bit linear address.
	 */
	lgdt	cpu_gdt_descr(%rip)

	/* set up data segments. actually 0 would do too */
	movl $__KERNEL_DS,%eax
	movl %eax,%ds
	movl %eax,%ss
	movl %eax,%es

	/*
	 * We don't really need to load %fs or %gs, but load them anyway
	 * to kill any stale realmode selectors.  This allows execution
	 * under VT hardware.
	 */
	movl %eax,%fs
	movl %eax,%gs

	/* 
	 * Setup up a dummy PDA. this is just for some early bootup code
	 * that does in_interrupt() 
	 */ 
	movl	$MSR_GS_BASE,%ecx
	movq	$empty_zero_page,%rax
	movq    %rax,%rdx
	shrq	$32,%rdx
	wrmsr	

	/* esi is pointer to real mode structure with interesting info.
	   pass it to C */
	movl	%esi, %edi
	
	/* Finally jump to run C code and to be on real kernel address
	 * Since we are running on identity-mapped space we have to jump
	 * to the full 64bit address, this is only possible as indirect
	 * jump.  In addition we need to ensure %cs is set so we make this
	 * a far return.
	 */
	movq	initial_code(%rip),%rax
	pushq	$0		# fake return address to stop unwinder
	pushq	$__KERNEL_CS	# set correct cs
	pushq	%rax		# target address in negative space
	lretq

	/* SMP bootup changes these two */
	.align	8
	.globl	initial_code
initial_code:
	.quad	x86_64_start_kernel
	.globl init_rsp
init_rsp:
	.quad  init_thread_union+THREAD_SIZE-8

bad_address:
	jmp bad_address

ENTRY(early_idt_handler)
	cmpl $2,early_recursion_flag(%rip)
	jz  1f
	incl early_recursion_flag(%rip)
	xorl %eax,%eax
	movq 8(%rsp),%rsi	# get rip
	movq (%rsp),%rdx
	movq %cr2,%rcx
	leaq early_idt_msg(%rip),%rdi
	call early_printk
	cmpl $2,early_recursion_flag(%rip)
	jz  1f
	call dump_stack
#ifdef CONFIG_KALLSYMS	
	leaq early_idt_ripmsg(%rip),%rdi
	movq 8(%rsp),%rsi	# get rip again
	call __print_symbol
#endif
1:	hlt
	jmp 1b
early_recursion_flag:
	.long 0

early_idt_msg:
	.asciz "PANIC: early exception rip %lx error %lx cr2 %lx\n"
early_idt_ripmsg:
	.asciz "RIP %s\n"

.balign PAGE_SIZE
ENTRY(stext)
ENTRY(_stext)

#define NEXT_PAGE(name) \
	.balign	PAGE_SIZE; \
ENTRY(name)

/* Automate the creation of 1 to 1 mapping pmd entries */
#define PMDS(START, PERM, COUNT)		\
	i = 0 ;					\
	.rept (COUNT) ;				\
	.quad	(START) + (i << 21) + (PERM) ;	\
	i = i + 1 ;				\
	.endr

	/*
	 * This default setting generates an ident mapping at address 0x100000
	 * and a mapping for the kernel that precisely maps virtual address
	 * 0xffffffff80000000 to physical address 0x000000. (always using
	 * 2Mbyte large pages provided by PAE mode)
	 */
NEXT_PAGE(init_level4_pgt)
	.quad	level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	.fill	257,8,0
	.quad	level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	.fill	252,8,0
	/* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
	.quad	level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE

NEXT_PAGE(level3_ident_pgt)
	.quad	level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	.fill	511,8,0

NEXT_PAGE(level3_kernel_pgt)
	.fill	510,8,0
	/* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
	.quad	level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
	.fill	1,8,0

NEXT_PAGE(level2_ident_pgt)
	/* Since I easily can, map the first 1G.
	 * Don't set NX because code runs from these pages.
	 */
	PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC, PTRS_PER_PMD)

NEXT_PAGE(level2_kernel_pgt)
	/* 40MB kernel mapping. The kernel code cannot be bigger than that.
	   When you change this change KERNEL_TEXT_SIZE in page.h too. */
	/* (2^48-(2*1024*1024*1024)-((2^39)*511)-((2^30)*510)) = 0 */
	PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC|_PAGE_GLOBAL,
		KERNEL_TEXT_SIZE/PMD_SIZE)
	/* Module mapping starts here */
	.fill	(PTRS_PER_PMD - (KERNEL_TEXT_SIZE/PMD_SIZE)),8,0

NEXT_PAGE(level2_spare_pgt)
	.fill   512,8,0

#undef PMDS
#undef NEXT_PAGE

	.data
	.align 16
	.globl cpu_gdt_descr
cpu_gdt_descr:
	.word	gdt_end-cpu_gdt_table-1
gdt:
	.quad	cpu_gdt_table
#ifdef CONFIG_SMP
	.rept	NR_CPUS-1
	.word	0
	.quad	0
	.endr
#endif

ENTRY(phys_base)
	/* This must match the first entry in level2_kernel_pgt */
	.quad   0x0000000000000000

/* We need valid kernel segments for data and code in long mode too
 * IRET will check the segment types  kkeil 2000/10/28
 * Also sysret mandates a special GDT layout 
 */
		 		
	.section .data.page_aligned, "aw"
	.align PAGE_SIZE

/* The TLS descriptors are currently at a different place compared to i386.
   Hopefully nobody expects them at a fixed place (Wine?) */
	
ENTRY(cpu_gdt_table)
	.quad	0x0000000000000000	/* NULL descriptor */
	.quad	0x00cf9b000000ffff	/* __KERNEL32_CS */
	.quad	0x00af9b000000ffff	/* __KERNEL_CS */
	.quad	0x00cf93000000ffff	/* __KERNEL_DS */
	.quad	0x00cffb000000ffff	/* __USER32_CS */
	.quad	0x00cff3000000ffff	/* __USER_DS, __USER32_DS  */
	.quad	0x00affb000000ffff	/* __USER_CS */
	.quad	0x0			/* unused */
	.quad	0,0			/* TSS */
	.quad	0,0			/* LDT */
	.quad   0,0,0			/* three TLS descriptors */ 
	.quad	0x0000f40000000000	/* node/CPU stored in limit */
gdt_end:	
	/* asm/segment.h:GDT_ENTRIES must match this */	
	/* This should be a multiple of the cache line size */
	/* GDTs of other CPUs are now dynamically allocated */

	/* zero the remaining page */
	.fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0

	.section .bss, "aw", @nobits
	.align L1_CACHE_BYTES
ENTRY(idt_table)
	.skip 256 * 16

	.section .bss.page_aligned, "aw", @nobits
	.align PAGE_SIZE
ENTRY(empty_zero_page)
	.skip PAGE_SIZE
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
	3	*
	4	* Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
	5	* Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
	6	* Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
	7	* Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
1ab60e0f	8	* Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
1da177e4 LT	9	*/
	10
	11
	12	#include <linux/linkage.h>
	13	#include <linux/threads.h>
f6c2e333	14	#include <linux/init.h>
1da177e4 LT	15	#include <asm/desc.h>
1da177e4 LT	16	#include <asm/segment.h>
67dcbb6b	17	#include <asm/pgtable.h>
1da177e4 LT	18	#include <asm/page.h>
	19	#include <asm/msr.h>
	20	#include <asm/cache.h>
1ab60e0f	21
1da177e4	22	/* we are not able to switch in one step to the final KERNEL ADRESS SPACE
1ab60e0f VG	23	* because we need identity-mapped pages.
1ab60e0f VG	24	*
1da177e4 LT	25	*/
	26
	27	.text
eaeae0cc	28	.section .bootstrap.text
1ab60e0f VG	29	.code64
	30	.globl startup_64
	31	startup_64:
	32
1da177e4	33	/*
1ab60e0f VG	34	* At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
	35	* and someone has loaded an identity mapped page table
	36	* for us. These identity mapped page tables map all of the
	37	* kernel pages and possibly all of memory.
	38	*
	39	* %esi holds a physical pointer to real_mode_data.
	40	*
	41	* We come here either directly from a 64bit bootloader, or from
	42	* arch/x86_64/boot/compressed/head.S.
	43	*
	44	* We only come here initially at boot nothing else comes here.
	45	*
	46	* Since we may be loaded at an address different from what we were
	47	* compiled to run at we first fixup the physical addresses in our page
	48	* tables and then reload them.
1da177e4 LT	49	*/
1da177e4 LT	50
1ab60e0f VG	51	/* Compute the delta between the address I am compiled to run at and the
1ab60e0f VG	52	* address I am actually running at.
1da177e4	53	*/
1ab60e0f VG	54	leaq _text(%rip), %rbp
	55	subq $_text - __START_KERNEL_map, %rbp
	56
	57	/* Is the address not 2M aligned? */
	58	movq %rbp, %rax
	59	andl $~LARGE_PAGE_MASK, %eax
	60	testl %eax, %eax
	61	jnz bad_address
	62
	63	/* Is the address too large? */
	64	leaq _text(%rip), %rdx
	65	movq $PGDIR_SIZE, %rax
	66	cmpq %rax, %rdx
	67	jae bad_address
	68
	69	/* Fixup the physical addresses in the page table
1da177e4	70	*/
1ab60e0f VG	71	addq %rbp, init_level4_pgt + 0(%rip)
	72	addq %rbp, init_level4_pgt + (258*8)(%rip)
	73	addq %rbp, init_level4_pgt + (511*8)(%rip)
	74
	75	addq %rbp, level3_ident_pgt + 0(%rip)
	76	addq %rbp, level3_kernel_pgt + (510*8)(%rip)
	77
	78	/* Add an Identity mapping if I am above 1G */
	79	leaq _text(%rip), %rdi
	80	andq $LARGE_PAGE_MASK, %rdi
	81
	82	movq %rdi, %rax
	83	shrq $PUD_SHIFT, %rax
	84	andq $(PTRS_PER_PUD - 1), %rax
	85	jz ident_complete
	86
	87	leaq (level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx
	88	leaq level3_ident_pgt(%rip), %rbx
	89	movq %rdx, 0(%rbx, %rax, 8)
	90
	91	movq %rdi, %rax
	92	shrq $PMD_SHIFT, %rax
	93	andq $(PTRS_PER_PMD - 1), %rax
	94	leaq __PAGE_KERNEL_LARGE_EXEC(%rdi), %rdx
	95	leaq level2_spare_pgt(%rip), %rbx
	96	movq %rdx, 0(%rbx, %rax, 8)
	97	ident_complete:
	98
	99	/* Fixup the kernel text+data virtual addresses
	100	*/
	101	leaq level2_kernel_pgt(%rip), %rdi
	102	leaq 4096(%rdi), %r8
	103	/* See if it is a valid page table entry */
	104	1: testq $1, 0(%rdi)
	105	jz 2f
	106	addq %rbp, 0(%rdi)
	107	/* Go to the next page */
	108	2: addq $8, %rdi
	109	cmp %r8, %rdi
	110	jne 1b
	111
	112	/* Fixup phys_base */
	113	addq %rbp, phys_base(%rip)
1da177e4	114
1ab60e0f VG	115	#ifdef CONFIG_SMP
	116	addq %rbp, trampoline_level4_pgt + 0(%rip)
	117	addq %rbp, trampoline_level4_pgt + (511*8)(%rip)
	118	#endif
	119	#ifdef CONFIG_ACPI_SLEEP
	120	addq %rbp, wakeup_level4_pgt + 0(%rip)
	121	addq %rbp, wakeup_level4_pgt + (511*8)(%rip)
	122	#endif
1da177e4	123
1ab60e0f VG	124	/* Due to ENTRY(), sometimes the empty space gets filled with
	125	* zeros. Better take a jmp than relying on empty space being
	126	* filled with 0x90 (nop)
1da177e4	127	*/
1ab60e0f	128	jmp secondary_startup_64
90b1c208	129	ENTRY(secondary_startup_64)
1ab60e0f VG	130	/*
	131	* At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
	132	* and someone has loaded a mapped page table.
	133	*
	134	* %esi holds a physical pointer to real_mode_data.
	135	*
	136	* We come here either from startup_64 (using physical addresses)
	137	* or from trampoline.S (using virtual addresses).
	138	*
	139	* Using virtual addresses from trampoline.S removes the need
	140	* to have any identity mapped pages in the kernel page table
	141	* after the boot processor executes this code.
1da177e4 LT	142	*/
	143
	144	/* Enable PAE mode and PGE */
	145	xorq %rax, %rax
	146	btsq $5, %rax
	147	btsq $7, %rax
	148	movq %rax, %cr4
	149
	150	/* Setup early boot stage 4 level pagetables. */
cfd243d4	151	movq $(init_level4_pgt - __START_KERNEL_map), %rax
1ab60e0f	152	addq phys_base(%rip), %rax
1da177e4 LT	153	movq %rax, %cr3
1da177e4 LT	154
1ab60e0f VG	155	/* Ensure I am executing from virtual addresses */
	156	movq $1f, %rax
	157	jmp *%rax
	158	1:
	159
1da177e4 LT	160	/* Check if nx is implemented */
	161	movl $0x80000001, %eax
	162	cpuid
	163	movl %edx,%edi
	164
	165	/* Setup EFER (Extended Feature Enable Register) */
	166	movl $MSR_EFER, %ecx
	167	rdmsr
1ab60e0f VG	168	btsl $_EFER_SCE, %eax /* Enable System Call */
1ab60e0f VG	169	btl $20,%edi /* No Execute supported? */
1da177e4 LT	170	jnc 1f
1da177e4 LT	171	btsl $_EFER_NX, %eax
1ab60e0f	172	1: wrmsr /* Make changes effective */
1da177e4 LT	173
1da177e4 LT	174	/* Setup cr0 */
3829ee6b AK	175	#define CR0_PM 1 /* protected mode */
	176	#define CR0_MP (1<<1)
	177	#define CR0_ET (1<<4)
	178	#define CR0_NE (1<<5)
	179	#define CR0_WP (1<<16)
	180	#define CR0_AM (1<<18)
	181	#define CR0_PAGING (1<<31)
	182	movl $CR0_PM\|CR0_MP\|CR0_ET\|CR0_NE\|CR0_WP\|CR0_AM\|CR0_PAGING,%eax
1da177e4 LT	183	/* Make changes effective */
	184	movq %rax, %cr0
	185
	186	/* Setup a boot time stack */
	187	movq init_rsp(%rip),%rsp
	188
	189	/* zero EFLAGS after setting rsp */
	190	pushq $0
	191	popfq
	192
	193	/*
	194	* We must switch to a new descriptor in kernel space for the GDT
	195	* because soon the kernel won't have access anymore to the userspace
	196	* addresses where we're currently running on. We have to do that here
	197	* because in 32bit we couldn't load a 64bit linear address.
	198	*/
1ab60e0f	199	lgdt cpu_gdt_descr(%rip)
1da177e4	200
ffb60175 ZA	201	/* set up data segments. actually 0 would do too */
	202	movl $__KERNEL_DS,%eax
	203	movl %eax,%ds
	204	movl %eax,%ss
	205	movl %eax,%es
	206
	207	/*
	208	* We don't really need to load %fs or %gs, but load them anyway
	209	* to kill any stale realmode selectors. This allows execution
	210	* under VT hardware.
	211	*/
	212	movl %eax,%fs
	213	movl %eax,%gs
	214
1da177e4 LT	215	/*
	216	* Setup up a dummy PDA. this is just for some early bootup code
	217	* that does in_interrupt()
	218	*/
	219	movl $MSR_GS_BASE,%ecx
	220	movq $empty_zero_page,%rax
	221	movq %rax,%rdx
	222	shrq $32,%rdx
	223	wrmsr
	224
1da177e4 LT	225	/* esi is pointer to real mode structure with interesting info.
	226	pass it to C */
	227	movl %esi, %edi
	228
	229	/* Finally jump to run C code and to be on real kernel address
	230	* Since we are running on identity-mapped space we have to jump
26374c7b EB	231	* to the full 64bit address, this is only possible as indirect
	232	* jump. In addition we need to ensure %cs is set so we make this
	233	* a far return.
1da177e4 LT	234	*/
1da177e4 LT	235	movq initial_code(%rip),%rax
26374c7b EB	236	pushq $0 # fake return address to stop unwinder
	237	pushq $__KERNEL_CS # set correct cs
	238	pushq %rax # target address in negative space
	239	lretq
1da177e4	240
e57113bc JB	241	/* SMP bootup changes these two */
e57113bc JB	242	.align 8
1da177e4 LT	243	.globl initial_code
	244	initial_code:
	245	.quad x86_64_start_kernel
	246	.globl init_rsp
	247	init_rsp:
	248	.quad init_thread_union+THREAD_SIZE-8
	249
1ab60e0f VG	250	bad_address:
	251	jmp bad_address
	252
1da177e4	253	ENTRY(early_idt_handler)
b957591f AK	254	cmpl $2,early_recursion_flag(%rip)
	255	jz 1f
	256	incl early_recursion_flag(%rip)
1da177e4 LT	257	xorl %eax,%eax
	258	movq 8(%rsp),%rsi # get rip
	259	movq (%rsp),%rdx
	260	movq %cr2,%rcx
	261	leaq early_idt_msg(%rip),%rdi
	262	call early_printk
b957591f AK	263	cmpl $2,early_recursion_flag(%rip)
	264	jz 1f
	265	call dump_stack
6574ffd7 AK	266	#ifdef CONFIG_KALLSYMS
	267	leaq early_idt_ripmsg(%rip),%rdi
	268	movq 8(%rsp),%rsi # get rip again
	269	call __print_symbol
	270	#endif
1da177e4 LT	271	1: hlt
1da177e4 LT	272	jmp 1b
b957591f AK	273	early_recursion_flag:
b957591f AK	274	.long 0
1da177e4 LT	275
	276	early_idt_msg:
	277	.asciz "PANIC: early exception rip %lx error %lx cr2 %lx\n"
6574ffd7 AK	278	early_idt_ripmsg:
6574ffd7 AK	279	.asciz "RIP %s\n"
1da177e4	280
1ab60e0f	281	.balign PAGE_SIZE
1da177e4 LT	282	ENTRY(stext)
	283	ENTRY(_stext)
	284
f0cf5d1a	285	#define NEXT_PAGE(name) \
67dcbb6b	286	.balign PAGE_SIZE; \
f0cf5d1a JB	287	ENTRY(name)
f0cf5d1a JB	288
67dcbb6b VG	289	/* Automate the creation of 1 to 1 mapping pmd entries */
	290	#define PMDS(START, PERM, COUNT) \
	291	i = 0 ; \
	292	.rept (COUNT) ; \
	293	.quad (START) + (i << 21) + (PERM) ; \
	294	i = i + 1 ; \
	295	.endr
	296
cfd243d4 VG	297	/*
	298	* This default setting generates an ident mapping at address 0x100000
	299	* and a mapping for the kernel that precisely maps virtual address
	300	* 0xffffffff80000000 to physical address 0x000000. (always using
	301	* 2Mbyte large pages provided by PAE mode)
	302	*/
f0cf5d1a	303	NEXT_PAGE(init_level4_pgt)
cfd243d4 VG	304	.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	305	.fill 257,8,0
	306	.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	307	.fill 252,8,0
	308	/* (2^48-(2102410241024))/(2^39) = 511 /
	309	.quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
1da177e4	310
f0cf5d1a	311	NEXT_PAGE(level3_ident_pgt)
67dcbb6b	312	.quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
1da177e4 LT	313	.fill 511,8,0
1da177e4 LT	314
f0cf5d1a	315	NEXT_PAGE(level3_kernel_pgt)
1da177e4 LT	316	.fill 510,8,0
1da177e4 LT	317	/* (2^48-(2102410241024)-((2^39)511))/(2^30) = 510 */
67dcbb6b	318	.quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
1da177e4 LT	319	.fill 1,8,0
1da177e4 LT	320
f0cf5d1a	321	NEXT_PAGE(level2_ident_pgt)
67dcbb6b VG	322	/* Since I easily can, map the first 1G.
	323	* Don't set NX because code runs from these pages.
	324	*/
	325	PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC, PTRS_PER_PMD)
1ab60e0f	326
f0cf5d1a	327	NEXT_PAGE(level2_kernel_pgt)
1da177e4 LT	328	/* 40MB kernel mapping. The kernel code cannot be bigger than that.
	329	When you change this change KERNEL_TEXT_SIZE in page.h too. */
	330	/* (2^48-(2102410241024)-((2^39)511)-((2^30)510)) = 0 /
67dcbb6b VG	331	PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC\|_PAGE_GLOBAL,
67dcbb6b VG	332	KERNEL_TEXT_SIZE/PMD_SIZE)
1da177e4	333	/* Module mapping starts here */
67dcbb6b	334	.fill (PTRS_PER_PMD - (KERNEL_TEXT_SIZE/PMD_SIZE)),8,0
1da177e4	335
1ab60e0f VG	336	NEXT_PAGE(level2_spare_pgt)
	337	.fill 512,8,0
	338
67dcbb6b	339	#undef PMDS
f0cf5d1a	340	#undef NEXT_PAGE
1da177e4	341
f0cf5d1a	342	.data
1da177e4 LT	343	.align 16
	344	.globl cpu_gdt_descr
	345	cpu_gdt_descr:
e57113bc	346	.word gdt_end-cpu_gdt_table-1
1da177e4 LT	347	gdt:
	348	.quad cpu_gdt_table
	349	#ifdef CONFIG_SMP
	350	.rept NR_CPUS-1
	351	.word 0
	352	.quad 0
	353	.endr
	354	#endif
	355
1ab60e0f VG	356	ENTRY(phys_base)
	357	/* This must match the first entry in level2_kernel_pgt */
	358	.quad 0x0000000000000000
	359
1da177e4 LT	360	/* We need valid kernel segments for data and code in long mode too
	361	* IRET will check the segment types kkeil 2000/10/28
	362	* Also sysret mandates a special GDT layout
	363	*/
	364
e57113bc JB	365	.section .data.page_aligned, "aw"
e57113bc JB	366	.align PAGE_SIZE
1da177e4 LT	367
	368	/* The TLS descriptors are currently at a different place compared to i386.
	369	Hopefully nobody expects them at a fixed place (Wine?) */
	370
	371	ENTRY(cpu_gdt_table)
	372	.quad 0x0000000000000000 /* NULL descriptor */
30f47289 VG	373	.quad 0x00cf9b000000ffff /* __KERNEL32_CS */
	374	.quad 0x00af9b000000ffff /* __KERNEL_CS */
	375	.quad 0x00cf93000000ffff /* __KERNEL_DS */
	376	.quad 0x00cffb000000ffff /* __USER32_CS */
	377	.quad 0x00cff3000000ffff /* __USER_DS, __USER32_DS */
	378	.quad 0x00affb000000ffff /* __USER_CS */
cdc4b9c0	379	.quad 0x0 /* unused */
1da177e4 LT	380	.quad 0,0 /* TSS */
	381	.quad 0,0 /* LDT */
	382	.quad 0,0,0 /* three TLS descriptors */
c08c8205	383	.quad 0x0000f40000000000 /* node/CPU stored in limit */
1da177e4 LT	384	gdt_end:
	385	/* asm/segment.h:GDT_ENTRIES must match this */
	386	/* This should be a multiple of the cache line size */
c11efdf9 RT	387	/* GDTs of other CPUs are now dynamically allocated */
	388
	389	/* zero the remaining page */
	390	.fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0
1da177e4	391
e57113bc JB	392	.section .bss, "aw", @nobits
	393	.align L1_CACHE_BYTES
	394	ENTRY(idt_table)
	395	.skip 256 * 16
1da177e4	396
e57113bc JB	397	.section .bss.page_aligned, "aw", @nobits
	398	.align PAGE_SIZE
	399	ENTRY(empty_zero_page)
	400	.skip PAGE_SIZE