[deliverable/linux.git] / arch / x86_64 / kernel / head.S

/*
 *  linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
 *
 *  Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
 *  Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
 *  Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
 *  Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
 *
 *  $Id: head.S,v 1.49 2002/03/19 17:39:25 ak Exp $
 */


#include <linux/linkage.h>
#include <linux/threads.h>
#include <asm/desc.h>
#include <asm/segment.h>
#include <asm/page.h>
#include <asm/msr.h>
#include <asm/cache.h>
	
/* we are not able to switch in one step to the final KERNEL ADRESS SPACE
 * because we need identity-mapped pages on setup so define __START_KERNEL to
 * 0x100000 for this stage
 * 
 */

	.text
	.code32
	.globl startup_32
/* %bx:	 1 if coming from smp trampoline on secondary cpu */ 
startup_32:
	
	/*
	 * At this point the CPU runs in 32bit protected mode (CS.D = 1) with
	 * paging disabled and the point of this file is to switch to 64bit
	 * long mode with a kernel mapping for kerneland to jump into the
	 * kernel virtual addresses.
 	 * There is no stack until we set one up.
	 */

	/* Initialize the %ds segment register */
	movl $__KERNEL_DS,%eax
	movl %eax,%ds

	/* Load new GDT with the 64bit segments using 32bit descriptor */
	lgdt	pGDT32 - __START_KERNEL_map

	/* If the CPU doesn't support CPUID this will double fault.
	 * Unfortunately it is hard to check for CPUID without a stack. 
	 */
	
	/* Check if extended functions are implemented */		
	movl	$0x80000000, %eax
	cpuid
	cmpl	$0x80000000, %eax
	jbe	no_long_mode
	/* Check if long mode is implemented */
	mov	$0x80000001, %eax
	cpuid
	btl	$29, %edx
	jnc	no_long_mode

	/*
	 * Prepare for entering 64bits mode
	 */

	/* Enable PAE mode */
	xorl	%eax, %eax
	btsl	$5, %eax
	movl	%eax, %cr4

	/* Setup early boot stage 4 level pagetables */
	movl	$(init_level4_pgt - __START_KERNEL_map), %eax
	movl	%eax, %cr3

	/* Setup EFER (Extended Feature Enable Register) */
	movl	$MSR_EFER, %ecx
	rdmsr

	/* Enable Long Mode */
	btsl	$_EFER_LME, %eax
				
	/* Make changes effective */
	wrmsr

	xorl	%eax, %eax
	btsl	$31, %eax			/* Enable paging and in turn activate Long Mode */
	btsl	$0, %eax			/* Enable protected mode */
	/* Make changes effective */
	movl	%eax, %cr0
	/*
	 * At this point we're in long mode but in 32bit compatibility mode
	 * with EFER.LME = 1, CS.L = 0, CS.D = 1 (and in turn
	 * EFER.LMA = 1). Now we want to jump in 64bit mode, to do that we use
	 * the new gdt/idt that has __KERNEL_CS with CS.L = 1.
	 */
	ljmp	$__KERNEL_CS, $(startup_64 - __START_KERNEL_map)

	.code64
	.org 0x100	
	.globl startup_64
startup_64:
	/* We come here either from startup_32
	 * or directly from a 64bit bootloader.
	 * Since we may have come directly from a bootloader we
	 * reload the page tables here.
	 */

	/* Enable PAE mode and PGE */
	xorq	%rax, %rax
	btsq	$5, %rax
	btsq	$7, %rax
	movq	%rax, %cr4

	/* Setup early boot stage 4 level pagetables. */
	movq	$(init_level4_pgt - __START_KERNEL_map), %rax
	movq	%rax, %cr3

	/* Check if nx is implemented */
	movl	$0x80000001, %eax
	cpuid
	movl	%edx,%edi

	/* Setup EFER (Extended Feature Enable Register) */
	movl	$MSR_EFER, %ecx
	rdmsr

	/* Enable System Call */
	btsl	$_EFER_SCE, %eax

	/* No Execute supported? */
	btl	$20,%edi
	jnc     1f
	btsl	$_EFER_NX, %eax
1:
	/* Make changes effective */
	wrmsr

	/* Setup cr0 */
	xorq	%rax, %rax
	btsq	$31, %rax			/* Enable paging */
	btsq	$0, %rax			/* Enable protected mode */
	btsq	$1, %rax			/* Enable MP */
	btsq	$4, %rax			/* Enable ET */
	btsq	$5, %rax			/* Enable NE */
	btsq	$16, %rax			/* Enable WP */
	btsq	$18, %rax			/* Enable AM */
	/* Make changes effective */
	movq	%rax, %cr0

	/* Setup a boot time stack */
	movq init_rsp(%rip),%rsp

	/* zero EFLAGS after setting rsp */
	pushq $0
	popfq

	/*
	 * We must switch to a new descriptor in kernel space for the GDT
	 * because soon the kernel won't have access anymore to the userspace
	 * addresses where we're currently running on. We have to do that here
	 * because in 32bit we couldn't load a 64bit linear address.
	 */
	lgdt	cpu_gdt_descr

	/* 
	 * Setup up a dummy PDA. this is just for some early bootup code
	 * that does in_interrupt() 
	 */ 
	movl	$MSR_GS_BASE,%ecx
	movq	$empty_zero_page,%rax
	movq    %rax,%rdx
	shrq	$32,%rdx
	wrmsr	

	/* set up data segments. actually 0 would do too */
	movl $__KERNEL_DS,%eax
	movl %eax,%ds	
	movl %eax,%ss
	movl %eax,%es
			
	/* esi is pointer to real mode structure with interesting info.
	   pass it to C */
	movl	%esi, %edi
	
	/* Finally jump to run C code and to be on real kernel address
	 * Since we are running on identity-mapped space we have to jump
	 * to the full 64bit address , this is only possible as indirect
	 * jump
	 */
	movq	initial_code(%rip),%rax
	jmp	*%rax

	/* SMP bootup changes these two */	
	.globl	initial_code
initial_code:
	.quad	x86_64_start_kernel
	.globl init_rsp
init_rsp:
	.quad  init_thread_union+THREAD_SIZE-8

ENTRY(early_idt_handler)
	cmpl $2,early_recursion_flag(%rip)
	jz  1f
	incl early_recursion_flag(%rip)
	xorl %eax,%eax
	movq 8(%rsp),%rsi	# get rip
	movq (%rsp),%rdx
	movq %cr2,%rcx
	leaq early_idt_msg(%rip),%rdi
	call early_printk
	cmpl $2,early_recursion_flag(%rip)
	jz  1f
	call dump_stack
1:	hlt
	jmp 1b
early_recursion_flag:
	.long 0

early_idt_msg:
	.asciz "PANIC: early exception rip %lx error %lx cr2 %lx\n"

.code32
ENTRY(no_long_mode)
	/* This isn't an x86-64 CPU so hang */
1:
	jmp	1b

.org 0xf00
	.globl pGDT32
pGDT32:
	.word	gdt_end-cpu_gdt_table
	.long	cpu_gdt_table-__START_KERNEL_map

.org 0xf10	
ljumpvector:
	.long	startup_64-__START_KERNEL_map
	.word	__KERNEL_CS

ENTRY(stext)
ENTRY(_stext)

	/*
	 * This default setting generates an ident mapping at address 0x100000
	 * and a mapping for the kernel that precisely maps virtual address
	 * 0xffffffff80000000 to physical address 0x000000. (always using
	 * 2Mbyte large pages provided by PAE mode)
	 */
.org 0x1000
ENTRY(init_level4_pgt)
	.quad	0x0000000000002007 + __PHYSICAL_START	/* -> level3_ident_pgt */
	.fill	255,8,0
	.quad	0x000000000000a007 + __PHYSICAL_START
	.fill	254,8,0
	/* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
	.quad	0x0000000000003007 + __PHYSICAL_START	/* -> level3_kernel_pgt */

.org 0x2000
ENTRY(level3_ident_pgt)
	.quad	0x0000000000004007 + __PHYSICAL_START
	.fill	511,8,0

.org 0x3000
ENTRY(level3_kernel_pgt)
	.fill	510,8,0
	/* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
	.quad	0x0000000000005007 + __PHYSICAL_START	/* -> level2_kernel_pgt */
	.fill	1,8,0

.org 0x4000
ENTRY(level2_ident_pgt)
	/* 40MB for bootup. 	*/
	.quad	0x0000000000000283
	.quad	0x0000000000200183
	.quad	0x0000000000400183
	.quad	0x0000000000600183
	.quad	0x0000000000800183
	.quad	0x0000000000A00183
	.quad	0x0000000000C00183
	.quad	0x0000000000E00183
	.quad	0x0000000001000183
	.quad	0x0000000001200183
	.quad	0x0000000001400183
	.quad	0x0000000001600183
	.quad	0x0000000001800183
	.quad	0x0000000001A00183
	.quad	0x0000000001C00183
	.quad	0x0000000001E00183
	.quad	0x0000000002000183
	.quad	0x0000000002200183
	.quad	0x0000000002400183
	.quad	0x0000000002600183
	/* Temporary mappings for the super early allocator in arch/x86_64/mm/init.c */
	.globl temp_boot_pmds
temp_boot_pmds:
	.fill	492,8,0
	
.org 0x5000
ENTRY(level2_kernel_pgt)
	/* 40MB kernel mapping. The kernel code cannot be bigger than that.
	   When you change this change KERNEL_TEXT_SIZE in page.h too. */
	/* (2^48-(2*1024*1024*1024)-((2^39)*511)-((2^30)*510)) = 0 */
	.quad	0x0000000000000183
	.quad	0x0000000000200183
	.quad	0x0000000000400183
	.quad	0x0000000000600183
	.quad	0x0000000000800183
	.quad	0x0000000000A00183
	.quad	0x0000000000C00183
	.quad	0x0000000000E00183
	.quad	0x0000000001000183
	.quad	0x0000000001200183
	.quad	0x0000000001400183
	.quad	0x0000000001600183
	.quad	0x0000000001800183
	.quad	0x0000000001A00183
	.quad	0x0000000001C00183
	.quad	0x0000000001E00183
	.quad	0x0000000002000183
	.quad	0x0000000002200183
	.quad	0x0000000002400183
	.quad	0x0000000002600183
	/* Module mapping starts here */
	.fill	492,8,0

.org 0x6000
ENTRY(empty_zero_page)

.org 0x7000
ENTRY(empty_bad_page)

.org 0x8000
ENTRY(empty_bad_pte_table)

.org 0x9000
ENTRY(empty_bad_pmd_table)

.org 0xa000
ENTRY(level3_physmem_pgt)
	.quad	0x0000000000005007 + __PHYSICAL_START	/* -> level2_kernel_pgt (so that __va works even before pagetable_init) */

	.org 0xb000
#ifdef CONFIG_ACPI_SLEEP
ENTRY(wakeup_level4_pgt)
	.quad	0x0000000000002007 + __PHYSICAL_START	/* -> level3_ident_pgt */
	.fill	255,8,0
	.quad	0x000000000000a007 + __PHYSICAL_START
	.fill	254,8,0
	/* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
	.quad	0x0000000000003007 + __PHYSICAL_START	/* -> level3_kernel_pgt */
#endif

	.data

	.align 16
	.globl cpu_gdt_descr
cpu_gdt_descr:
	.word	gdt_end-cpu_gdt_table
gdt:
	.quad	cpu_gdt_table
#ifdef CONFIG_SMP
	.rept	NR_CPUS-1
	.word	0
	.quad	0
	.endr
#endif

/* We need valid kernel segments for data and code in long mode too
 * IRET will check the segment types  kkeil 2000/10/28
 * Also sysret mandates a special GDT layout 
 */
		 		
.align L1_CACHE_BYTES

/* The TLS descriptors are currently at a different place compared to i386.
   Hopefully nobody expects them at a fixed place (Wine?) */
	
ENTRY(cpu_gdt_table)
	.quad	0x0000000000000000	/* NULL descriptor */
	.quad	0x008f9a000000ffff	/* __KERNEL_COMPAT32_CS */	
	.quad	0x00af9a000000ffff	/* __KERNEL_CS */
	.quad	0x00cf92000000ffff	/* __KERNEL_DS */
	.quad	0x00cffa000000ffff	/* __USER32_CS */
	.quad	0x00cff2000000ffff	/* __USER_DS, __USER32_DS  */		
	.quad	0x00affa000000ffff	/* __USER_CS */
	.quad	0x00cf9a000000ffff	/* __KERNEL32_CS */
	.quad	0,0			/* TSS */
	.quad	0,0			/* LDT */
	.quad   0,0,0			/* three TLS descriptors */ 
	.quad	0x00009a000000ffff	/* __KERNEL16_CS - 16bit PM for S3 wakeup. */
					/* base must be patched for real base address. */
gdt_end:	
	/* asm/segment.h:GDT_ENTRIES must match this */	
	/* This should be a multiple of the cache line size */
	/* GDTs of other CPUs: */	
	.fill (GDT_SIZE * NR_CPUS) - (gdt_end - cpu_gdt_table)

	.align  L1_CACHE_BYTES
ENTRY(idt_table)	
	.rept   256
	.quad   0
	.quad 	0
	.endr
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
	3	*
	4	* Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
	5	* Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
	6	* Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
	7	* Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
	8	*
	9	* $Id: head.S,v 1.49 2002/03/19 17:39:25 ak Exp $
	10	*/
	11
	12
	13	#include <linux/linkage.h>
	14	#include <linux/threads.h>
	15	#include <asm/desc.h>
	16	#include <asm/segment.h>
	17	#include <asm/page.h>
	18	#include <asm/msr.h>
	19	#include <asm/cache.h>
	20
	21	/* we are not able to switch in one step to the final KERNEL ADRESS SPACE
	22	* because we need identity-mapped pages on setup so define __START_KERNEL to
	23	* 0x100000 for this stage
	24	*
	25	*/
	26
	27	.text
	28	.code32
	29	.globl startup_32
	30	/* %bx: 1 if coming from smp trampoline on secondary cpu */
	31	startup_32:
	32
	33	/*
	34	* At this point the CPU runs in 32bit protected mode (CS.D = 1) with
	35	* paging disabled and the point of this file is to switch to 64bit
	36	* long mode with a kernel mapping for kerneland to jump into the
	37	* kernel virtual addresses.
	38	* There is no stack until we set one up.
	39	*/
	40
	41	/* Initialize the %ds segment register */
	42	movl $__KERNEL_DS,%eax
	43	movl %eax,%ds
	44
	45	/* Load new GDT with the 64bit segments using 32bit descriptor */
	46	lgdt pGDT32 - __START_KERNEL_map
	47
	48	/* If the CPU doesn't support CPUID this will double fault.
	49	* Unfortunately it is hard to check for CPUID without a stack.
	50	*/
	51
	52	/* Check if extended functions are implemented */
	53	movl $0x80000000, %eax
	54	cpuid
	55	cmpl $0x80000000, %eax
	56	jbe no_long_mode
	57	/* Check if long mode is implemented */
	58	mov $0x80000001, %eax
	59	cpuid
	60	btl $29, %edx
	61	jnc no_long_mode
	62
	63	/*
	64	* Prepare for entering 64bits mode
65	*/
66
67	/* Enable PAE mode */
68	xorl %eax, %eax
69	btsl $5, %eax
70	movl %eax, %cr4
71
72	/* Setup early boot stage 4 level pagetables */
73	movl $(init_level4_pgt - __START_KERNEL_map), %eax
74	movl %eax, %cr3
75
76	/* Setup EFER (Extended Feature Enable Register) */
77	movl $MSR_EFER, %ecx
78	rdmsr
79
80	/* Enable Long Mode */
81	btsl $_EFER_LME, %eax
82
83	/* Make changes effective */
84	wrmsr
85
86	xorl %eax, %eax
87	btsl $31, %eax /* Enable paging and in turn activate Long Mode */
88	btsl $0, %eax /* Enable protected mode */
89	/* Make changes effective */
90	movl %eax, %cr0
91	/*
92	* At this point we're in long mode but in 32bit compatibility mode
93	* with EFER.LME = 1, CS.L = 0, CS.D = 1 (and in turn
94	* EFER.LMA = 1). Now we want to jump in 64bit mode, to do that we use
95	* the new gdt/idt that has __KERNEL_CS with CS.L = 1.
96	*/
97	ljmp $__KERNEL_CS, $(startup_64 - __START_KERNEL_map)
98
99	.code64
100	.org 0x100
101	.globl startup_64
102	startup_64:
103	/* We come here either from startup_32
104	* or directly from a 64bit bootloader.
105	* Since we may have come directly from a bootloader we
106	* reload the page tables here.
107	*/
108
109	/* Enable PAE mode and PGE */
110	xorq %rax, %rax
111	btsq $5, %rax
112	btsq $7, %rax
113	movq %rax, %cr4
114
115	/* Setup early boot stage 4 level pagetables. */
116	movq $(init_level4_pgt - __START_KERNEL_map), %rax
117	movq %rax, %cr3
118
119	/* Check if nx is implemented */
120	movl $0x80000001, %eax
121	cpuid
122	movl %edx,%edi
123
124	/* Setup EFER (Extended Feature Enable Register) */
125	movl $MSR_EFER, %ecx
126	rdmsr
127
128	/* Enable System Call */
129	btsl $_EFER_SCE, %eax
130
131	/* No Execute supported? */
132	btl $20,%edi
133	jnc 1f
134	btsl $_EFER_NX, %eax
135	1:
136	/* Make changes effective */
137	wrmsr
138
139	/* Setup cr0 */
140	xorq %rax, %rax
141	btsq $31, %rax /* Enable paging */
142	btsq $0, %rax /* Enable protected mode */
143	btsq $1, %rax /* Enable MP */
144	btsq $4, %rax /* Enable ET */
145	btsq $5, %rax /* Enable NE */
146	btsq $16, %rax /* Enable WP */
147	btsq $18, %rax /* Enable AM */
148	/* Make changes effective */
149	movq %rax, %cr0
150
151	/* Setup a boot time stack */
152	movq init_rsp(%rip),%rsp
153
154	/* zero EFLAGS after setting rsp */
155	pushq $0
156	popfq
157
158	/*
159	* We must switch to a new descriptor in kernel space for the GDT
160	* because soon the kernel won't have access anymore to the userspace
161	* addresses where we're currently running on. We have to do that here
162	* because in 32bit we couldn't load a 64bit linear address.
163	*/
164	lgdt cpu_gdt_descr
165
166	/*
167	* Setup up a dummy PDA. this is just for some early bootup code
168	* that does in_interrupt()
169	*/
170	movl $MSR_GS_BASE,%ecx
171	movq $empty_zero_page,%rax
172	movq %rax,%rdx
173	shrq $32,%rdx
174	wrmsr
175
176	/* set up data segments. actually 0 would do too */
177	movl $__KERNEL_DS,%eax
178	movl %eax,%ds
179	movl %eax,%ss
180	movl %eax,%es
181
182	/* esi is pointer to real mode structure with interesting info.
183	pass it to C */
184	movl %esi, %edi
185
186	/* Finally jump to run C code and to be on real kernel address
187	* Since we are running on identity-mapped space we have to jump
188	* to the full 64bit address , this is only possible as indirect
189	* jump
190	*/
191	movq initial_code(%rip),%rax
192	jmp *%rax
193
194	/* SMP bootup changes these two */
195	.globl initial_code
196	initial_code:
197	.quad x86_64_start_kernel
198	.globl init_rsp
199	init_rsp:
200	.quad init_thread_union+THREAD_SIZE-8
201
202	ENTRY(early_idt_handler)
b957591f AK	203	cmpl $2,early_recursion_flag(%rip)
	204	jz 1f
	205	incl early_recursion_flag(%rip)
1da177e4 LT	206	xorl %eax,%eax
	207	movq 8(%rsp),%rsi # get rip
	208	movq (%rsp),%rdx
	209	movq %cr2,%rcx
	210	leaq early_idt_msg(%rip),%rdi
	211	call early_printk
b957591f AK	212	cmpl $2,early_recursion_flag(%rip)
	213	jz 1f
	214	call dump_stack
1da177e4 LT	215	1: hlt
1da177e4 LT	216	jmp 1b
b957591f AK	217	early_recursion_flag:
b957591f AK	218	.long 0
1da177e4 LT	219
	220	early_idt_msg:
	221	.asciz "PANIC: early exception rip %lx error %lx cr2 %lx\n"
	222
	223	.code32
	224	ENTRY(no_long_mode)
	225	/* This isn't an x86-64 CPU so hang */
	226	1:
	227	jmp 1b
	228
	229	.org 0xf00
	230	.globl pGDT32
	231	pGDT32:
	232	.word gdt_end-cpu_gdt_table
	233	.long cpu_gdt_table-__START_KERNEL_map
	234
	235	.org 0xf10
	236	ljumpvector:
	237	.long startup_64-__START_KERNEL_map
	238	.word __KERNEL_CS
	239
	240	ENTRY(stext)
	241	ENTRY(_stext)
	242
	243	/*
	244	* This default setting generates an ident mapping at address 0x100000
	245	* and a mapping for the kernel that precisely maps virtual address
	246	* 0xffffffff80000000 to physical address 0x000000. (always using
	247	* 2Mbyte large pages provided by PAE mode)
	248	*/
	249	.org 0x1000
	250	ENTRY(init_level4_pgt)
d0537508	251	.quad 0x0000000000002007 + __PHYSICAL_START /* -> level3_ident_pgt */
1da177e4	252	.fill 255,8,0
d0537508	253	.quad 0x000000000000a007 + __PHYSICAL_START
1da177e4 LT	254	.fill 254,8,0
1da177e4 LT	255	/* (2^48-(2102410241024))/(2^39) = 511 /
d0537508	256	.quad 0x0000000000003007 + __PHYSICAL_START /* -> level3_kernel_pgt */
1da177e4 LT	257
	258	.org 0x2000
	259	ENTRY(level3_ident_pgt)
d0537508	260	.quad 0x0000000000004007 + __PHYSICAL_START
1da177e4 LT	261	.fill 511,8,0
	262
	263	.org 0x3000
	264	ENTRY(level3_kernel_pgt)
	265	.fill 510,8,0
	266	/* (2^48-(2102410241024)-((2^39)511))/(2^30) = 510 */
d0537508	267	.quad 0x0000000000005007 + __PHYSICAL_START /* -> level2_kernel_pgt */
1da177e4 LT	268	.fill 1,8,0
	269
	270	.org 0x4000
	271	ENTRY(level2_ident_pgt)
	272	/* 40MB for bootup. */
	273	.quad 0x0000000000000283
	274	.quad 0x0000000000200183
	275	.quad 0x0000000000400183
	276	.quad 0x0000000000600183
	277	.quad 0x0000000000800183
	278	.quad 0x0000000000A00183
	279	.quad 0x0000000000C00183
	280	.quad 0x0000000000E00183
	281	.quad 0x0000000001000183
	282	.quad 0x0000000001200183
	283	.quad 0x0000000001400183
	284	.quad 0x0000000001600183
	285	.quad 0x0000000001800183
	286	.quad 0x0000000001A00183
	287	.quad 0x0000000001C00183
	288	.quad 0x0000000001E00183
	289	.quad 0x0000000002000183
	290	.quad 0x0000000002200183
	291	.quad 0x0000000002400183
	292	.quad 0x0000000002600183
	293	/* Temporary mappings for the super early allocator in arch/x86_64/mm/init.c */
	294	.globl temp_boot_pmds
	295	temp_boot_pmds:
	296	.fill 492,8,0
	297
	298	.org 0x5000
	299	ENTRY(level2_kernel_pgt)
	300	/* 40MB kernel mapping. The kernel code cannot be bigger than that.
	301	When you change this change KERNEL_TEXT_SIZE in page.h too. */
	302	/* (2^48-(2102410241024)-((2^39)511)-((2^30)510)) = 0 /
	303	.quad 0x0000000000000183
	304	.quad 0x0000000000200183
	305	.quad 0x0000000000400183
	306	.quad 0x0000000000600183
	307	.quad 0x0000000000800183
	308	.quad 0x0000000000A00183
	309	.quad 0x0000000000C00183
	310	.quad 0x0000000000E00183
	311	.quad 0x0000000001000183
	312	.quad 0x0000000001200183
	313	.quad 0x0000000001400183
	314	.quad 0x0000000001600183
	315	.quad 0x0000000001800183
	316	.quad 0x0000000001A00183
	317	.quad 0x0000000001C00183
	318	.quad 0x0000000001E00183
	319	.quad 0x0000000002000183
	320	.quad 0x0000000002200183
	321	.quad 0x0000000002400183
	322	.quad 0x0000000002600183
	323	/* Module mapping starts here */
	324	.fill 492,8,0
	325
	326	.org 0x6000
	327	ENTRY(empty_zero_page)
	328
	329	.org 0x7000
	330	ENTRY(empty_bad_page)
	331
332	.org 0x8000
333	ENTRY(empty_bad_pte_table)
334
335	.org 0x9000
336	ENTRY(empty_bad_pmd_table)
337
338	.org 0xa000
339	ENTRY(level3_physmem_pgt)
d0537508	340	.quad 0x0000000000005007 + __PHYSICAL_START /* -> level2_kernel_pgt (so that __va works even before pagetable_init) */
1da177e4 LT	341
	342	.org 0xb000
	343	#ifdef CONFIG_ACPI_SLEEP
	344	ENTRY(wakeup_level4_pgt)
d0537508	345	.quad 0x0000000000002007 + __PHYSICAL_START /* -> level3_ident_pgt */
1da177e4	346	.fill 255,8,0
d0537508	347	.quad 0x000000000000a007 + __PHYSICAL_START
1da177e4 LT	348	.fill 254,8,0
1da177e4 LT	349	/* (2^48-(2102410241024))/(2^39) = 511 /
d0537508	350	.quad 0x0000000000003007 + __PHYSICAL_START /* -> level3_kernel_pgt */
1da177e4 LT	351	#endif
	352
	353	.data
	354
	355	.align 16
	356	.globl cpu_gdt_descr
	357	cpu_gdt_descr:
	358	.word gdt_end-cpu_gdt_table
	359	gdt:
	360	.quad cpu_gdt_table
	361	#ifdef CONFIG_SMP
	362	.rept NR_CPUS-1
	363	.word 0
	364	.quad 0
	365	.endr
	366	#endif
	367
	368	/* We need valid kernel segments for data and code in long mode too
	369	* IRET will check the segment types kkeil 2000/10/28
	370	* Also sysret mandates a special GDT layout
	371	*/
	372
	373	.align L1_CACHE_BYTES
	374
	375	/* The TLS descriptors are currently at a different place compared to i386.
	376	Hopefully nobody expects them at a fixed place (Wine?) */
	377
	378	ENTRY(cpu_gdt_table)
	379	.quad 0x0000000000000000 /* NULL descriptor */
	380	.quad 0x008f9a000000ffff /* __KERNEL_COMPAT32_CS */
	381	.quad 0x00af9a000000ffff /* __KERNEL_CS */
	382	.quad 0x00cf92000000ffff /* __KERNEL_DS */
	383	.quad 0x00cffa000000ffff /* __USER32_CS */
	384	.quad 0x00cff2000000ffff /* __USER_DS, __USER32_DS */
	385	.quad 0x00affa000000ffff /* __USER_CS */
	386	.quad 0x00cf9a000000ffff /* __KERNEL32_CS */
	387	.quad 0,0 /* TSS */
	388	.quad 0,0 /* LDT */
	389	.quad 0,0,0 /* three TLS descriptors */
	390	.quad 0x00009a000000ffff /* __KERNEL16_CS - 16bit PM for S3 wakeup. */
	391	/* base must be patched for real base address. */
	392	gdt_end:
	393	/* asm/segment.h:GDT_ENTRIES must match this */
	394	/* This should be a multiple of the cache line size */
	395	/* GDTs of other CPUs: */
	396	.fill (GDT_SIZE * NR_CPUS) - (gdt_end - cpu_gdt_table)
	397
	398	.align L1_CACHE_BYTES
	399	ENTRY(idt_table)
	400	.rept 256
	401	.quad 0
	402	.quad 0
	403	.endr
	404