c37e7bb5 |
1 | #include <linux/kernel.h> |
2 | #include <linux/sched.h> |
3 | #include <linux/init.h> |
4 | #include <linux/mc146818rtc.h> |
5 | #include <linux/time.h> |
6 | #include <linux/clocksource.h> |
7 | #include <linux/ioport.h> |
8 | #include <linux/acpi.h> |
9 | #include <linux/hpet.h> |
10 | #include <asm/pgtable.h> |
11 | #include <asm/vsyscall.h> |
12 | #include <asm/timex.h> |
13 | #include <asm/hpet.h> |
14 | |
15 | int nohpet __initdata; |
16 | |
17 | unsigned long hpet_address; |
18 | unsigned long hpet_period; /* fsecs / HPET clock */ |
19 | unsigned long hpet_tick; /* HPET clocks / interrupt */ |
20 | |
21 | int hpet_use_timer; /* Use counter of hpet for time keeping, |
22 | * otherwise PIT |
23 | */ |
c37e7bb5 |
24 | |
25 | #ifdef CONFIG_HPET |
26 | static __init int late_hpet_init(void) |
27 | { |
28 | struct hpet_data hd; |
29 | unsigned int ntimer; |
30 | |
31 | if (!hpet_address) |
32 | return 0; |
33 | |
34 | memset(&hd, 0, sizeof(hd)); |
35 | |
36 | ntimer = hpet_readl(HPET_ID); |
37 | ntimer = (ntimer & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT; |
38 | ntimer++; |
39 | |
40 | /* |
41 | * Register with driver. |
42 | * Timer0 and Timer1 is used by platform. |
43 | */ |
44 | hd.hd_phys_address = hpet_address; |
45 | hd.hd_address = (void __iomem *)fix_to_virt(FIX_HPET_BASE); |
46 | hd.hd_nirqs = ntimer; |
47 | hd.hd_flags = HPET_DATA_PLATFORM; |
48 | hpet_reserve_timer(&hd, 0); |
49 | #ifdef CONFIG_HPET_EMULATE_RTC |
50 | hpet_reserve_timer(&hd, 1); |
51 | #endif |
52 | hd.hd_irq[0] = HPET_LEGACY_8254; |
53 | hd.hd_irq[1] = HPET_LEGACY_RTC; |
54 | if (ntimer > 2) { |
55 | struct hpet *hpet; |
56 | struct hpet_timer *timer; |
57 | int i; |
58 | |
59 | hpet = (struct hpet *) fix_to_virt(FIX_HPET_BASE); |
60 | timer = &hpet->hpet_timers[2]; |
61 | for (i = 2; i < ntimer; timer++, i++) |
62 | hd.hd_irq[i] = (timer->hpet_config & |
63 | Tn_INT_ROUTE_CNF_MASK) >> |
64 | Tn_INT_ROUTE_CNF_SHIFT; |
65 | |
66 | } |
67 | |
68 | hpet_alloc(&hd); |
69 | return 0; |
70 | } |
71 | fs_initcall(late_hpet_init); |
72 | #endif |
73 | |
74 | int hpet_timer_stop_set_go(unsigned long tick) |
75 | { |
76 | unsigned int cfg; |
77 | |
78 | /* |
79 | * Stop the timers and reset the main counter. |
80 | */ |
81 | |
82 | cfg = hpet_readl(HPET_CFG); |
83 | cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY); |
84 | hpet_writel(cfg, HPET_CFG); |
85 | hpet_writel(0, HPET_COUNTER); |
86 | hpet_writel(0, HPET_COUNTER + 4); |
87 | |
88 | /* |
89 | * Set up timer 0, as periodic with first interrupt to happen at hpet_tick, |
90 | * and period also hpet_tick. |
91 | */ |
92 | if (hpet_use_timer) { |
93 | hpet_writel(HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL | |
94 | HPET_TN_32BIT, HPET_T0_CFG); |
95 | hpet_writel(hpet_tick, HPET_T0_CMP); /* next interrupt */ |
96 | hpet_writel(hpet_tick, HPET_T0_CMP); /* period */ |
97 | cfg |= HPET_CFG_LEGACY; |
98 | } |
99 | /* |
100 | * Go! |
101 | */ |
102 | |
103 | cfg |= HPET_CFG_ENABLE; |
104 | hpet_writel(cfg, HPET_CFG); |
105 | |
106 | return 0; |
107 | } |
108 | |
109 | int hpet_arch_init(void) |
110 | { |
111 | unsigned int id; |
112 | |
113 | if (!hpet_address) |
114 | return -1; |
115 | set_fixmap_nocache(FIX_HPET_BASE, hpet_address); |
116 | __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE); |
117 | |
118 | /* |
119 | * Read the period, compute tick and quotient. |
120 | */ |
121 | |
122 | id = hpet_readl(HPET_ID); |
123 | |
124 | if (!(id & HPET_ID_VENDOR) || !(id & HPET_ID_NUMBER)) |
125 | return -1; |
126 | |
127 | hpet_period = hpet_readl(HPET_PERIOD); |
128 | if (hpet_period < 100000 || hpet_period > 100000000) |
129 | return -1; |
130 | |
131 | hpet_tick = (FSEC_PER_TICK + hpet_period / 2) / hpet_period; |
132 | |
133 | hpet_use_timer = (id & HPET_ID_LEGSUP); |
134 | |
135 | return hpet_timer_stop_set_go(hpet_tick); |
136 | } |
137 | |
138 | int hpet_reenable(void) |
139 | { |
140 | return hpet_timer_stop_set_go(hpet_tick); |
141 | } |
142 | |
143 | /* |
144 | * calibrate_tsc() calibrates the processor TSC in a very simple way, comparing |
145 | * it to the HPET timer of known frequency. |
146 | */ |
147 | |
148 | #define TICK_COUNT 100000000 |
149 | #define TICK_MIN 5000 |
150 | |
151 | /* |
152 | * Some platforms take periodic SMI interrupts with 5ms duration. Make sure none |
153 | * occurs between the reads of the hpet & TSC. |
154 | */ |
155 | static void __init read_hpet_tsc(int *hpet, int *tsc) |
156 | { |
157 | int tsc1, tsc2, hpet1; |
158 | |
159 | do { |
160 | tsc1 = get_cycles_sync(); |
161 | hpet1 = hpet_readl(HPET_COUNTER); |
162 | tsc2 = get_cycles_sync(); |
163 | } while (tsc2 - tsc1 > TICK_MIN); |
164 | *hpet = hpet1; |
165 | *tsc = tsc2; |
166 | } |
167 | |
168 | unsigned int __init hpet_calibrate_tsc(void) |
169 | { |
170 | int tsc_start, hpet_start; |
171 | int tsc_now, hpet_now; |
172 | unsigned long flags; |
173 | |
174 | local_irq_save(flags); |
175 | |
176 | read_hpet_tsc(&hpet_start, &tsc_start); |
177 | |
178 | do { |
179 | local_irq_disable(); |
180 | read_hpet_tsc(&hpet_now, &tsc_now); |
181 | local_irq_restore(flags); |
182 | } while ((tsc_now - tsc_start) < TICK_COUNT && |
183 | (hpet_now - hpet_start) < TICK_COUNT); |
184 | |
185 | return (tsc_now - tsc_start) * 1000000000L |
186 | / ((hpet_now - hpet_start) * hpet_period / 1000); |
187 | } |
188 | |
189 | #ifdef CONFIG_HPET_EMULATE_RTC |
190 | /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET |
191 | * is enabled, we support RTC interrupt functionality in software. |
192 | * RTC has 3 kinds of interrupts: |
193 | * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock |
194 | * is updated |
195 | * 2) Alarm Interrupt - generate an interrupt at a specific time of day |
196 | * 3) Periodic Interrupt - generate periodic interrupt, with frequencies |
197 | * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) |
198 | * (1) and (2) above are implemented using polling at a frequency of |
199 | * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt |
200 | * overhead. (DEFAULT_RTC_INT_FREQ) |
201 | * For (3), we use interrupts at 64Hz or user specified periodic |
202 | * frequency, whichever is higher. |
203 | */ |
204 | #include <linux/rtc.h> |
205 | |
206 | #define DEFAULT_RTC_INT_FREQ 64 |
207 | #define RTC_NUM_INTS 1 |
208 | |
209 | static unsigned long UIE_on; |
210 | static unsigned long prev_update_sec; |
211 | |
212 | static unsigned long AIE_on; |
213 | static struct rtc_time alarm_time; |
214 | |
215 | static unsigned long PIE_on; |
216 | static unsigned long PIE_freq = DEFAULT_RTC_INT_FREQ; |
217 | static unsigned long PIE_count; |
218 | |
219 | static unsigned long hpet_rtc_int_freq; /* RTC interrupt frequency */ |
220 | static unsigned int hpet_t1_cmp; /* cached comparator register */ |
221 | |
222 | int is_hpet_enabled(void) |
223 | { |
224 | return hpet_address != 0; |
225 | } |
226 | |
227 | /* |
228 | * Timer 1 for RTC, we do not use periodic interrupt feature, |
229 | * even if HPET supports periodic interrupts on Timer 1. |
230 | * The reason being, to set up a periodic interrupt in HPET, we need to |
231 | * stop the main counter. And if we do that everytime someone diables/enables |
232 | * RTC, we will have adverse effect on main kernel timer running on Timer 0. |
233 | * So, for the time being, simulate the periodic interrupt in software. |
234 | * |
235 | * hpet_rtc_timer_init() is called for the first time and during subsequent |
236 | * interuppts reinit happens through hpet_rtc_timer_reinit(). |
237 | */ |
238 | int hpet_rtc_timer_init(void) |
239 | { |
240 | unsigned int cfg, cnt; |
241 | unsigned long flags; |
242 | |
243 | if (!is_hpet_enabled()) |
244 | return 0; |
245 | /* |
246 | * Set the counter 1 and enable the interrupts. |
247 | */ |
248 | if (PIE_on && (PIE_freq > DEFAULT_RTC_INT_FREQ)) |
249 | hpet_rtc_int_freq = PIE_freq; |
250 | else |
251 | hpet_rtc_int_freq = DEFAULT_RTC_INT_FREQ; |
252 | |
253 | local_irq_save(flags); |
254 | |
255 | cnt = hpet_readl(HPET_COUNTER); |
256 | cnt += ((hpet_tick*HZ)/hpet_rtc_int_freq); |
257 | hpet_writel(cnt, HPET_T1_CMP); |
258 | hpet_t1_cmp = cnt; |
259 | |
260 | cfg = hpet_readl(HPET_T1_CFG); |
261 | cfg &= ~HPET_TN_PERIODIC; |
262 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; |
263 | hpet_writel(cfg, HPET_T1_CFG); |
264 | |
265 | local_irq_restore(flags); |
266 | |
267 | return 1; |
268 | } |
269 | |
270 | static void hpet_rtc_timer_reinit(void) |
271 | { |
272 | unsigned int cfg, cnt, ticks_per_int, lost_ints; |
273 | |
274 | if (unlikely(!(PIE_on | AIE_on | UIE_on))) { |
275 | cfg = hpet_readl(HPET_T1_CFG); |
276 | cfg &= ~HPET_TN_ENABLE; |
277 | hpet_writel(cfg, HPET_T1_CFG); |
278 | return; |
279 | } |
280 | |
281 | if (PIE_on && (PIE_freq > DEFAULT_RTC_INT_FREQ)) |
282 | hpet_rtc_int_freq = PIE_freq; |
283 | else |
284 | hpet_rtc_int_freq = DEFAULT_RTC_INT_FREQ; |
285 | |
286 | /* It is more accurate to use the comparator value than current count.*/ |
287 | ticks_per_int = hpet_tick * HZ / hpet_rtc_int_freq; |
288 | hpet_t1_cmp += ticks_per_int; |
289 | hpet_writel(hpet_t1_cmp, HPET_T1_CMP); |
290 | |
291 | /* |
292 | * If the interrupt handler was delayed too long, the write above tries |
293 | * to schedule the next interrupt in the past and the hardware would |
294 | * not interrupt until the counter had wrapped around. |
295 | * So we have to check that the comparator wasn't set to a past time. |
296 | */ |
297 | cnt = hpet_readl(HPET_COUNTER); |
298 | if (unlikely((int)(cnt - hpet_t1_cmp) > 0)) { |
299 | lost_ints = (cnt - hpet_t1_cmp) / ticks_per_int + 1; |
300 | /* Make sure that, even with the time needed to execute |
301 | * this code, the next scheduled interrupt has been moved |
302 | * back to the future: */ |
303 | lost_ints++; |
304 | |
305 | hpet_t1_cmp += lost_ints * ticks_per_int; |
306 | hpet_writel(hpet_t1_cmp, HPET_T1_CMP); |
307 | |
308 | if (PIE_on) |
309 | PIE_count += lost_ints; |
310 | |
311 | if (printk_ratelimit()) |
312 | printk(KERN_WARNING "rtc: lost some interrupts at %ldHz.\n", |
313 | hpet_rtc_int_freq); |
314 | } |
315 | } |
316 | |
317 | /* |
318 | * The functions below are called from rtc driver. |
319 | * Return 0 if HPET is not being used. |
320 | * Otherwise do the necessary changes and return 1. |
321 | */ |
322 | int hpet_mask_rtc_irq_bit(unsigned long bit_mask) |
323 | { |
324 | if (!is_hpet_enabled()) |
325 | return 0; |
326 | |
327 | if (bit_mask & RTC_UIE) |
328 | UIE_on = 0; |
329 | if (bit_mask & RTC_PIE) |
330 | PIE_on = 0; |
331 | if (bit_mask & RTC_AIE) |
332 | AIE_on = 0; |
333 | |
334 | return 1; |
335 | } |
336 | |
337 | int hpet_set_rtc_irq_bit(unsigned long bit_mask) |
338 | { |
339 | int timer_init_reqd = 0; |
340 | |
341 | if (!is_hpet_enabled()) |
342 | return 0; |
343 | |
344 | if (!(PIE_on | AIE_on | UIE_on)) |
345 | timer_init_reqd = 1; |
346 | |
347 | if (bit_mask & RTC_UIE) { |
348 | UIE_on = 1; |
349 | } |
350 | if (bit_mask & RTC_PIE) { |
351 | PIE_on = 1; |
352 | PIE_count = 0; |
353 | } |
354 | if (bit_mask & RTC_AIE) { |
355 | AIE_on = 1; |
356 | } |
357 | |
358 | if (timer_init_reqd) |
359 | hpet_rtc_timer_init(); |
360 | |
361 | return 1; |
362 | } |
363 | |
364 | int hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec) |
365 | { |
366 | if (!is_hpet_enabled()) |
367 | return 0; |
368 | |
369 | alarm_time.tm_hour = hrs; |
370 | alarm_time.tm_min = min; |
371 | alarm_time.tm_sec = sec; |
372 | |
373 | return 1; |
374 | } |
375 | |
376 | int hpet_set_periodic_freq(unsigned long freq) |
377 | { |
378 | if (!is_hpet_enabled()) |
379 | return 0; |
380 | |
381 | PIE_freq = freq; |
382 | PIE_count = 0; |
383 | |
384 | return 1; |
385 | } |
386 | |
387 | int hpet_rtc_dropped_irq(void) |
388 | { |
389 | if (!is_hpet_enabled()) |
390 | return 0; |
391 | |
392 | return 1; |
393 | } |
394 | |
395 | irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id, struct pt_regs *regs) |
396 | { |
397 | struct rtc_time curr_time; |
398 | unsigned long rtc_int_flag = 0; |
399 | int call_rtc_interrupt = 0; |
400 | |
401 | hpet_rtc_timer_reinit(); |
402 | |
403 | if (UIE_on | AIE_on) { |
404 | rtc_get_rtc_time(&curr_time); |
405 | } |
406 | if (UIE_on) { |
407 | if (curr_time.tm_sec != prev_update_sec) { |
408 | /* Set update int info, call real rtc int routine */ |
409 | call_rtc_interrupt = 1; |
410 | rtc_int_flag = RTC_UF; |
411 | prev_update_sec = curr_time.tm_sec; |
412 | } |
413 | } |
414 | if (PIE_on) { |
415 | PIE_count++; |
416 | if (PIE_count >= hpet_rtc_int_freq/PIE_freq) { |
417 | /* Set periodic int info, call real rtc int routine */ |
418 | call_rtc_interrupt = 1; |
419 | rtc_int_flag |= RTC_PF; |
420 | PIE_count = 0; |
421 | } |
422 | } |
423 | if (AIE_on) { |
424 | if ((curr_time.tm_sec == alarm_time.tm_sec) && |
425 | (curr_time.tm_min == alarm_time.tm_min) && |
426 | (curr_time.tm_hour == alarm_time.tm_hour)) { |
427 | /* Set alarm int info, call real rtc int routine */ |
428 | call_rtc_interrupt = 1; |
429 | rtc_int_flag |= RTC_AF; |
430 | } |
431 | } |
432 | if (call_rtc_interrupt) { |
433 | rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); |
434 | rtc_interrupt(rtc_int_flag, dev_id); |
435 | } |
436 | return IRQ_HANDLED; |
437 | } |
438 | #endif |
439 | |
440 | static int __init nohpet_setup(char *s) |
441 | { |
442 | nohpet = 1; |
443 | return 1; |
444 | } |
445 | |
446 | __setup("nohpet", nohpet_setup); |
447 | |
1489939f |
448 | #define HPET_MASK 0xFFFFFFFF |
449 | #define HPET_SHIFT 22 |
450 | |
451 | /* FSEC = 10^-15 NSEC = 10^-9 */ |
452 | #define FSEC_PER_NSEC 1000000 |
453 | |
454 | static void *hpet_ptr; |
455 | |
456 | static cycle_t read_hpet(void) |
457 | { |
458 | return (cycle_t)readl(hpet_ptr); |
459 | } |
460 | |
7460ed28 |
461 | static cycle_t __vsyscall_fn vread_hpet(void) |
462 | { |
463 | return readl((void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0); |
464 | } |
465 | |
1489939f |
466 | struct clocksource clocksource_hpet = { |
467 | .name = "hpet", |
468 | .rating = 250, |
469 | .read = read_hpet, |
470 | .mask = (cycle_t)HPET_MASK, |
471 | .mult = 0, /* set below */ |
472 | .shift = HPET_SHIFT, |
473 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
7460ed28 |
474 | .vread = vread_hpet, |
1489939f |
475 | }; |
476 | |
477 | static int __init init_hpet_clocksource(void) |
478 | { |
479 | unsigned long hpet_period; |
480 | void __iomem *hpet_base; |
481 | u64 tmp; |
482 | |
483 | if (!hpet_address) |
484 | return -ENODEV; |
485 | |
486 | /* calculate the hpet address: */ |
487 | hpet_base = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); |
488 | hpet_ptr = hpet_base + HPET_COUNTER; |
489 | |
490 | /* calculate the frequency: */ |
491 | hpet_period = readl(hpet_base + HPET_PERIOD); |
492 | |
493 | /* |
494 | * hpet period is in femto seconds per cycle |
495 | * so we need to convert this to ns/cyc units |
496 | * aproximated by mult/2^shift |
497 | * |
498 | * fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift |
499 | * fsec/cyc * 1ns/1000000fsec * 2^shift = mult |
500 | * fsec/cyc * 2^shift * 1nsec/1000000fsec = mult |
501 | * (fsec/cyc << shift)/1000000 = mult |
502 | * (hpet_period << shift)/FSEC_PER_NSEC = mult |
503 | */ |
504 | tmp = (u64)hpet_period << HPET_SHIFT; |
505 | do_div(tmp, FSEC_PER_NSEC); |
506 | clocksource_hpet.mult = (u32)tmp; |
507 | |
508 | return clocksource_register(&clocksource_hpet); |
509 | } |
510 | |
511 | module_init(init_hpet_clocksource); |