Commit | Line | Data |
---|---|---|
1da177e4 | 1 | #include <linux/linkage.h> |
1da177e4 LT |
2 | #include <linux/errno.h> |
3 | #include <linux/signal.h> | |
4 | #include <linux/sched.h> | |
5 | #include <linux/ioport.h> | |
6 | #include <linux/interrupt.h> | |
7 | #include <linux/timex.h> | |
8 | #include <linux/slab.h> | |
9 | #include <linux/random.h> | |
10 | #include <linux/smp_lock.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/kernel_stat.h> | |
13 | #include <linux/sysdev.h> | |
14 | #include <linux/bitops.h> | |
15 | ||
16 | #include <asm/acpi.h> | |
17 | #include <asm/atomic.h> | |
18 | #include <asm/system.h> | |
19 | #include <asm/io.h> | |
1da177e4 LT |
20 | #include <asm/hw_irq.h> |
21 | #include <asm/pgtable.h> | |
22 | #include <asm/delay.h> | |
23 | #include <asm/desc.h> | |
24 | #include <asm/apic.h> | |
25 | ||
1da177e4 LT |
26 | /* |
27 | * Common place to define all x86 IRQ vectors | |
28 | * | |
29 | * This builds up the IRQ handler stubs using some ugly macros in irq.h | |
30 | * | |
31 | * These macros create the low-level assembly IRQ routines that save | |
32 | * register context and call do_IRQ(). do_IRQ() then does all the | |
33 | * operations that are needed to keep the AT (or SMP IOAPIC) | |
34 | * interrupt-controller happy. | |
35 | */ | |
36 | ||
37 | #define BI(x,y) \ | |
38 | BUILD_IRQ(x##y) | |
39 | ||
40 | #define BUILD_16_IRQS(x) \ | |
41 | BI(x,0) BI(x,1) BI(x,2) BI(x,3) \ | |
42 | BI(x,4) BI(x,5) BI(x,6) BI(x,7) \ | |
43 | BI(x,8) BI(x,9) BI(x,a) BI(x,b) \ | |
44 | BI(x,c) BI(x,d) BI(x,e) BI(x,f) | |
45 | ||
2b28592b | 46 | #define BUILD_15_IRQS(x) \ |
1da177e4 LT |
47 | BI(x,0) BI(x,1) BI(x,2) BI(x,3) \ |
48 | BI(x,4) BI(x,5) BI(x,6) BI(x,7) \ | |
49 | BI(x,8) BI(x,9) BI(x,a) BI(x,b) \ | |
2b28592b | 50 | BI(x,c) BI(x,d) BI(x,e) |
1da177e4 LT |
51 | |
52 | /* | |
53 | * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts: | |
54 | * (these are usually mapped to vectors 0x20-0x2f) | |
55 | */ | |
56 | BUILD_16_IRQS(0x0) | |
57 | ||
1da177e4 LT |
58 | /* |
59 | * The IO-APIC gives us many more interrupt sources. Most of these | |
60 | * are unused but an SMP system is supposed to have enough memory ... | |
61 | * sometimes (mostly wrt. hw bugs) we get corrupted vectors all | |
62 | * across the spectrum, so we really want to be prepared to get all | |
63 | * of these. Plus, more powerful systems might have more than 64 | |
64 | * IO-APIC registers. | |
65 | * | |
66 | * (these are usually mapped into the 0x30-0xff vector range) | |
67 | */ | |
68 | BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3) | |
69 | BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7) | |
70 | BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb) | |
71 | BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) | |
72 | ||
73 | #ifdef CONFIG_PCI_MSI | |
2b28592b | 74 | BUILD_15_IRQS(0xe) |
1da177e4 LT |
75 | #endif |
76 | ||
1da177e4 | 77 | #undef BUILD_16_IRQS |
2b28592b | 78 | #undef BUILD_15_IRQS |
1da177e4 LT |
79 | #undef BI |
80 | ||
81 | ||
82 | #define IRQ(x,y) \ | |
83 | IRQ##x##y##_interrupt | |
84 | ||
85 | #define IRQLIST_16(x) \ | |
86 | IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \ | |
87 | IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \ | |
88 | IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \ | |
89 | IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f) | |
90 | ||
2b28592b | 91 | #define IRQLIST_15(x) \ |
1da177e4 LT |
92 | IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \ |
93 | IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \ | |
94 | IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \ | |
2b28592b | 95 | IRQ(x,c), IRQ(x,d), IRQ(x,e) |
1da177e4 LT |
96 | |
97 | void (*interrupt[NR_IRQS])(void) = { | |
98 | IRQLIST_16(0x0), | |
99 | ||
1da177e4 LT |
100 | IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3), |
101 | IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7), | |
102 | IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb), | |
103 | IRQLIST_16(0xc), IRQLIST_16(0xd) | |
104 | ||
105 | #ifdef CONFIG_PCI_MSI | |
2b28592b | 106 | , IRQLIST_15(0xe) |
1da177e4 LT |
107 | #endif |
108 | ||
1da177e4 LT |
109 | }; |
110 | ||
111 | #undef IRQ | |
112 | #undef IRQLIST_16 | |
113 | #undef IRQLIST_14 | |
114 | ||
115 | /* | |
116 | * This is the 'legacy' 8259A Programmable Interrupt Controller, | |
117 | * present in the majority of PC/AT boxes. | |
118 | * plus some generic x86 specific things if generic specifics makes | |
119 | * any sense at all. | |
120 | * this file should become arch/i386/kernel/irq.c when the old irq.c | |
121 | * moves to arch independent land | |
122 | */ | |
123 | ||
35d534a3 | 124 | static int i8259A_auto_eoi; |
f29bd1ba | 125 | DEFINE_SPINLOCK(i8259A_lock); |
1da177e4 LT |
126 | static void mask_and_ack_8259A(unsigned int); |
127 | ||
f29bd1ba IM |
128 | static struct irq_chip i8259A_chip = { |
129 | .name = "XT-PIC", | |
130 | .mask = disable_8259A_irq, | |
131 | .unmask = enable_8259A_irq, | |
132 | .mask_ack = mask_and_ack_8259A, | |
1da177e4 LT |
133 | }; |
134 | ||
135 | /* | |
136 | * 8259A PIC functions to handle ISA devices: | |
137 | */ | |
138 | ||
139 | /* | |
140 | * This contains the irq mask for both 8259A irq controllers, | |
141 | */ | |
142 | static unsigned int cached_irq_mask = 0xffff; | |
143 | ||
144 | #define __byte(x,y) (((unsigned char *)&(y))[x]) | |
145 | #define cached_21 (__byte(0,cached_irq_mask)) | |
146 | #define cached_A1 (__byte(1,cached_irq_mask)) | |
147 | ||
148 | /* | |
149 | * Not all IRQs can be routed through the IO-APIC, eg. on certain (older) | |
150 | * boards the timer interrupt is not really connected to any IO-APIC pin, | |
151 | * it's fed to the master 8259A's IR0 line only. | |
152 | * | |
153 | * Any '1' bit in this mask means the IRQ is routed through the IO-APIC. | |
154 | * this 'mixed mode' IRQ handling costs nothing because it's only used | |
155 | * at IRQ setup time. | |
156 | */ | |
157 | unsigned long io_apic_irqs; | |
158 | ||
159 | void disable_8259A_irq(unsigned int irq) | |
160 | { | |
161 | unsigned int mask = 1 << irq; | |
162 | unsigned long flags; | |
163 | ||
164 | spin_lock_irqsave(&i8259A_lock, flags); | |
165 | cached_irq_mask |= mask; | |
166 | if (irq & 8) | |
167 | outb(cached_A1,0xA1); | |
168 | else | |
169 | outb(cached_21,0x21); | |
170 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
171 | } | |
172 | ||
173 | void enable_8259A_irq(unsigned int irq) | |
174 | { | |
175 | unsigned int mask = ~(1 << irq); | |
176 | unsigned long flags; | |
177 | ||
178 | spin_lock_irqsave(&i8259A_lock, flags); | |
179 | cached_irq_mask &= mask; | |
180 | if (irq & 8) | |
181 | outb(cached_A1,0xA1); | |
182 | else | |
183 | outb(cached_21,0x21); | |
184 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
185 | } | |
186 | ||
187 | int i8259A_irq_pending(unsigned int irq) | |
188 | { | |
189 | unsigned int mask = 1<<irq; | |
190 | unsigned long flags; | |
191 | int ret; | |
192 | ||
193 | spin_lock_irqsave(&i8259A_lock, flags); | |
194 | if (irq < 8) | |
195 | ret = inb(0x20) & mask; | |
196 | else | |
197 | ret = inb(0xA0) & (mask >> 8); | |
198 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
199 | ||
200 | return ret; | |
201 | } | |
202 | ||
203 | void make_8259A_irq(unsigned int irq) | |
204 | { | |
205 | disable_irq_nosync(irq); | |
206 | io_apic_irqs &= ~(1<<irq); | |
f29bd1ba | 207 | set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq); |
1da177e4 LT |
208 | enable_irq(irq); |
209 | } | |
210 | ||
211 | /* | |
212 | * This function assumes to be called rarely. Switching between | |
213 | * 8259A registers is slow. | |
214 | * This has to be protected by the irq controller spinlock | |
215 | * before being called. | |
216 | */ | |
217 | static inline int i8259A_irq_real(unsigned int irq) | |
218 | { | |
219 | int value; | |
220 | int irqmask = 1<<irq; | |
221 | ||
222 | if (irq < 8) { | |
223 | outb(0x0B,0x20); /* ISR register */ | |
224 | value = inb(0x20) & irqmask; | |
225 | outb(0x0A,0x20); /* back to the IRR register */ | |
226 | return value; | |
227 | } | |
228 | outb(0x0B,0xA0); /* ISR register */ | |
229 | value = inb(0xA0) & (irqmask >> 8); | |
230 | outb(0x0A,0xA0); /* back to the IRR register */ | |
231 | return value; | |
232 | } | |
233 | ||
234 | /* | |
235 | * Careful! The 8259A is a fragile beast, it pretty | |
236 | * much _has_ to be done exactly like this (mask it | |
237 | * first, _then_ send the EOI, and the order of EOI | |
238 | * to the two 8259s is important! | |
239 | */ | |
240 | static void mask_and_ack_8259A(unsigned int irq) | |
241 | { | |
242 | unsigned int irqmask = 1 << irq; | |
243 | unsigned long flags; | |
244 | ||
245 | spin_lock_irqsave(&i8259A_lock, flags); | |
246 | /* | |
247 | * Lightweight spurious IRQ detection. We do not want | |
248 | * to overdo spurious IRQ handling - it's usually a sign | |
249 | * of hardware problems, so we only do the checks we can | |
d6e05edc | 250 | * do without slowing down good hardware unnecessarily. |
1da177e4 LT |
251 | * |
252 | * Note that IRQ7 and IRQ15 (the two spurious IRQs | |
253 | * usually resulting from the 8259A-1|2 PICs) occur | |
254 | * even if the IRQ is masked in the 8259A. Thus we | |
255 | * can check spurious 8259A IRQs without doing the | |
256 | * quite slow i8259A_irq_real() call for every IRQ. | |
257 | * This does not cover 100% of spurious interrupts, | |
258 | * but should be enough to warn the user that there | |
259 | * is something bad going on ... | |
260 | */ | |
261 | if (cached_irq_mask & irqmask) | |
262 | goto spurious_8259A_irq; | |
263 | cached_irq_mask |= irqmask; | |
264 | ||
265 | handle_real_irq: | |
266 | if (irq & 8) { | |
267 | inb(0xA1); /* DUMMY - (do we need this?) */ | |
268 | outb(cached_A1,0xA1); | |
269 | outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */ | |
270 | outb(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */ | |
271 | } else { | |
272 | inb(0x21); /* DUMMY - (do we need this?) */ | |
273 | outb(cached_21,0x21); | |
274 | outb(0x60+irq,0x20); /* 'Specific EOI' to master */ | |
275 | } | |
276 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
277 | return; | |
278 | ||
279 | spurious_8259A_irq: | |
280 | /* | |
281 | * this is the slow path - should happen rarely. | |
282 | */ | |
283 | if (i8259A_irq_real(irq)) | |
284 | /* | |
285 | * oops, the IRQ _is_ in service according to the | |
286 | * 8259A - not spurious, go handle it. | |
287 | */ | |
288 | goto handle_real_irq; | |
289 | ||
290 | { | |
291 | static int spurious_irq_mask; | |
292 | /* | |
293 | * At this point we can be sure the IRQ is spurious, | |
294 | * lets ACK and report it. [once per IRQ] | |
295 | */ | |
296 | if (!(spurious_irq_mask & irqmask)) { | |
297 | printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq); | |
298 | spurious_irq_mask |= irqmask; | |
299 | } | |
300 | atomic_inc(&irq_err_count); | |
301 | /* | |
302 | * Theoretically we do not have to handle this IRQ, | |
303 | * but in Linux this does not cause problems and is | |
304 | * simpler for us. | |
305 | */ | |
306 | goto handle_real_irq; | |
307 | } | |
308 | } | |
309 | ||
310 | void init_8259A(int auto_eoi) | |
311 | { | |
312 | unsigned long flags; | |
313 | ||
35d534a3 MG |
314 | i8259A_auto_eoi = auto_eoi; |
315 | ||
1da177e4 LT |
316 | spin_lock_irqsave(&i8259A_lock, flags); |
317 | ||
318 | outb(0xff, 0x21); /* mask all of 8259A-1 */ | |
319 | outb(0xff, 0xA1); /* mask all of 8259A-2 */ | |
320 | ||
321 | /* | |
322 | * outb_p - this has to work on a wide range of PC hardware. | |
323 | */ | |
324 | outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */ | |
325 | outb_p(0x20 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */ | |
326 | outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */ | |
327 | if (auto_eoi) | |
328 | outb_p(0x03, 0x21); /* master does Auto EOI */ | |
329 | else | |
330 | outb_p(0x01, 0x21); /* master expects normal EOI */ | |
331 | ||
332 | outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */ | |
333 | outb_p(0x20 + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */ | |
334 | outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */ | |
335 | outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode | |
336 | is to be investigated) */ | |
337 | ||
338 | if (auto_eoi) | |
339 | /* | |
340 | * in AEOI mode we just have to mask the interrupt | |
341 | * when acking. | |
342 | */ | |
f29bd1ba | 343 | i8259A_chip.mask_ack = disable_8259A_irq; |
1da177e4 | 344 | else |
f29bd1ba | 345 | i8259A_chip.mask_ack = mask_and_ack_8259A; |
1da177e4 LT |
346 | |
347 | udelay(100); /* wait for 8259A to initialize */ | |
348 | ||
349 | outb(cached_21, 0x21); /* restore master IRQ mask */ | |
350 | outb(cached_A1, 0xA1); /* restore slave IRQ mask */ | |
351 | ||
352 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
353 | } | |
354 | ||
355 | static char irq_trigger[2]; | |
356 | /** | |
357 | * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ | |
358 | */ | |
359 | static void restore_ELCR(char *trigger) | |
360 | { | |
361 | outb(trigger[0], 0x4d0); | |
362 | outb(trigger[1], 0x4d1); | |
363 | } | |
364 | ||
365 | static void save_ELCR(char *trigger) | |
366 | { | |
367 | /* IRQ 0,1,2,8,13 are marked as reserved */ | |
368 | trigger[0] = inb(0x4d0) & 0xF8; | |
369 | trigger[1] = inb(0x4d1) & 0xDE; | |
370 | } | |
371 | ||
372 | static int i8259A_resume(struct sys_device *dev) | |
373 | { | |
35d534a3 | 374 | init_8259A(i8259A_auto_eoi); |
1da177e4 LT |
375 | restore_ELCR(irq_trigger); |
376 | return 0; | |
377 | } | |
378 | ||
0b9c33a7 | 379 | static int i8259A_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
380 | { |
381 | save_ELCR(irq_trigger); | |
382 | return 0; | |
383 | } | |
384 | ||
719e7110 EB |
385 | static int i8259A_shutdown(struct sys_device *dev) |
386 | { | |
387 | /* Put the i8259A into a quiescent state that | |
388 | * the kernel initialization code can get it | |
389 | * out of. | |
390 | */ | |
391 | outb(0xff, 0x21); /* mask all of 8259A-1 */ | |
392 | outb(0xff, 0xA1); /* mask all of 8259A-1 */ | |
393 | return 0; | |
394 | } | |
395 | ||
1da177e4 LT |
396 | static struct sysdev_class i8259_sysdev_class = { |
397 | set_kset_name("i8259"), | |
398 | .suspend = i8259A_suspend, | |
399 | .resume = i8259A_resume, | |
719e7110 | 400 | .shutdown = i8259A_shutdown, |
1da177e4 LT |
401 | }; |
402 | ||
403 | static struct sys_device device_i8259A = { | |
404 | .id = 0, | |
405 | .cls = &i8259_sysdev_class, | |
406 | }; | |
407 | ||
408 | static int __init i8259A_init_sysfs(void) | |
409 | { | |
410 | int error = sysdev_class_register(&i8259_sysdev_class); | |
411 | if (!error) | |
412 | error = sysdev_register(&device_i8259A); | |
413 | return error; | |
414 | } | |
415 | ||
416 | device_initcall(i8259A_init_sysfs); | |
417 | ||
418 | /* | |
419 | * IRQ2 is cascade interrupt to second interrupt controller | |
420 | */ | |
421 | ||
422 | static struct irqaction irq2 = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL}; | |
423 | ||
424 | void __init init_ISA_irqs (void) | |
425 | { | |
426 | int i; | |
427 | ||
1da177e4 | 428 | init_bsp_APIC(); |
1da177e4 LT |
429 | init_8259A(0); |
430 | ||
431 | for (i = 0; i < NR_IRQS; i++) { | |
432 | irq_desc[i].status = IRQ_DISABLED; | |
433 | irq_desc[i].action = NULL; | |
434 | irq_desc[i].depth = 1; | |
435 | ||
436 | if (i < 16) { | |
437 | /* | |
438 | * 16 old-style INTA-cycle interrupts: | |
439 | */ | |
f29bd1ba IM |
440 | set_irq_chip_and_handler(i, &i8259A_chip, |
441 | handle_level_irq); | |
1da177e4 LT |
442 | } else { |
443 | /* | |
444 | * 'high' PCI IRQs filled in on demand | |
445 | */ | |
f29bd1ba | 446 | irq_desc[i].chip = &no_irq_chip; |
1da177e4 LT |
447 | } |
448 | } | |
449 | } | |
450 | ||
451 | void apic_timer_interrupt(void); | |
452 | void spurious_interrupt(void); | |
453 | void error_interrupt(void); | |
454 | void reschedule_interrupt(void); | |
455 | void call_function_interrupt(void); | |
e5bc8b6b AK |
456 | void invalidate_interrupt0(void); |
457 | void invalidate_interrupt1(void); | |
458 | void invalidate_interrupt2(void); | |
459 | void invalidate_interrupt3(void); | |
460 | void invalidate_interrupt4(void); | |
461 | void invalidate_interrupt5(void); | |
462 | void invalidate_interrupt6(void); | |
463 | void invalidate_interrupt7(void); | |
1da177e4 | 464 | void thermal_interrupt(void); |
89b831ef | 465 | void threshold_interrupt(void); |
1da177e4 LT |
466 | void i8254_timer_resume(void); |
467 | ||
a8db2db1 | 468 | static void setup_timer_hardware(void) |
1da177e4 LT |
469 | { |
470 | outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */ | |
471 | udelay(10); | |
472 | outb_p(LATCH & 0xff , 0x40); /* LSB */ | |
473 | udelay(10); | |
474 | outb(LATCH >> 8 , 0x40); /* MSB */ | |
475 | } | |
476 | ||
477 | static int timer_resume(struct sys_device *dev) | |
478 | { | |
a8db2db1 | 479 | setup_timer_hardware(); |
1da177e4 LT |
480 | return 0; |
481 | } | |
482 | ||
483 | void i8254_timer_resume(void) | |
484 | { | |
a8db2db1 | 485 | setup_timer_hardware(); |
1da177e4 LT |
486 | } |
487 | ||
488 | static struct sysdev_class timer_sysclass = { | |
d6c7ac08 | 489 | set_kset_name("timer_pit"), |
1da177e4 LT |
490 | .resume = timer_resume, |
491 | }; | |
492 | ||
493 | static struct sys_device device_timer = { | |
494 | .id = 0, | |
495 | .cls = &timer_sysclass, | |
496 | }; | |
497 | ||
498 | static int __init init_timer_sysfs(void) | |
499 | { | |
500 | int error = sysdev_class_register(&timer_sysclass); | |
501 | if (!error) | |
502 | error = sysdev_register(&device_timer); | |
503 | return error; | |
504 | } | |
505 | ||
506 | device_initcall(init_timer_sysfs); | |
507 | ||
508 | void __init init_IRQ(void) | |
509 | { | |
510 | int i; | |
511 | ||
512 | init_ISA_irqs(); | |
513 | /* | |
514 | * Cover the whole vector space, no vector can escape | |
515 | * us. (some of these will be overridden and become | |
516 | * 'special' SMP interrupts) | |
517 | */ | |
518 | for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) { | |
519 | int vector = FIRST_EXTERNAL_VECTOR + i; | |
520 | if (i >= NR_IRQS) | |
521 | break; | |
915f34e2 | 522 | if (vector != IA32_SYSCALL_VECTOR) |
1da177e4 LT |
523 | set_intr_gate(vector, interrupt[i]); |
524 | } | |
1da177e4 LT |
525 | |
526 | #ifdef CONFIG_SMP | |
527 | /* | |
528 | * IRQ0 must be given a fixed assignment and initialized, | |
529 | * because it's used before the IO-APIC is set up. | |
530 | */ | |
531 | set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]); | |
532 | ||
533 | /* | |
534 | * The reschedule interrupt is a CPU-to-CPU reschedule-helper | |
535 | * IPI, driven by wakeup. | |
536 | */ | |
537 | set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); | |
538 | ||
e5bc8b6b AK |
539 | /* IPIs for invalidation */ |
540 | set_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0); | |
541 | set_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1); | |
542 | set_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2); | |
543 | set_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3); | |
544 | set_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4); | |
545 | set_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5); | |
546 | set_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6); | |
547 | set_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7); | |
1da177e4 LT |
548 | |
549 | /* IPI for generic function call */ | |
550 | set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); | |
551 | #endif | |
552 | set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); | |
89b831ef | 553 | set_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt); |
1da177e4 | 554 | |
1da177e4 LT |
555 | /* self generated IPI for local APIC timer */ |
556 | set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); | |
557 | ||
558 | /* IPI vectors for APIC spurious and error interrupts */ | |
559 | set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); | |
560 | set_intr_gate(ERROR_APIC_VECTOR, error_interrupt); | |
1da177e4 LT |
561 | |
562 | /* | |
563 | * Set the clock to HZ Hz, we already have a valid | |
564 | * vector now: | |
565 | */ | |
a8db2db1 | 566 | setup_timer_hardware(); |
1da177e4 LT |
567 | |
568 | if (!acpi_ioapic) | |
569 | setup_irq(2, &irq2); | |
570 | } |