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x86-64: write IO APIC irq routing entries in correct order
[deliverable/linux.git] / arch / x86_64 / kernel / io_apic.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
1da177e4
LT		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
1da177e4 28#include <linux/smp_lock.h>
589e367f 29#include <linux/pci.h>
1da177e4
LT		 30#include <linux/mc146818rtc.h>
31#include <linux/acpi.h>
32#include <linux/sysdev.h>
3b7d1921 33#include <linux/msi.h>
95d77884 34#include <linux/htirq.h>
ab688059
AK		 35#ifdef CONFIG_ACPI
36#include <acpi/acpi_bus.h>
37#endif
1da177e4
LT		 38
39#include <asm/io.h>
40#include <asm/smp.h>
41#include <asm/desc.h>
42#include <asm/proto.h>
43#include <asm/mach_apic.h>
8d916406 44#include <asm/acpi.h>
ca8642f6 45#include <asm/dma.h>
3e4ff115 46#include <asm/nmi.h>
589e367f 47#include <asm/msidef.h>
8b955b0d 48#include <asm/hypertransport.h>
1da177e4 49
c7111c13 50static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result);
04b9267b 51
1da177e4
LT		 52#define __apicdebuginit __init
53
54int sis_apic_bug; /* not actually supported, dummy for compile */
55
14d98cad
AK		 56static int no_timer_check;
57
2c8c0e6b 58static int disable_timer_pin_1 __initdata;
66759a01 59
e70ea8c0 60int timer_over_8254 __initdata = 1;
ab9b32ee 61
1008fddc
EB		 62/* Where if anywhere is the i8259 connect in external int mode */
63static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
64
1da177e4 65static DEFINE_SPINLOCK(ioapic_lock);
70a0a535 66DEFINE_SPINLOCK(vector_lock);
1da177e4
LT		 67
68/*
69 * # of IRQ routing registers
70 */
71int nr_ioapic_registers[MAX_IO_APICS];
72
73/*
74 * Rough estimation of how many shared IRQs there are, can
75 * be changed anytime.
76 */
6004e1b7 77#define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
1da177e4
LT		 78#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
79
80/*
81 * This is performance-critical, we want to do it O(1)
82 *
83 * the indexing order of this array favors 1:1 mappings
84 * between pins and IRQs.
85 */
86
87static struct irq_pin_list {
88 short apic, pin, next;
89} irq_2_pin[PIN_MAP_SIZE];
90
6c0ffb9d
LT		 91struct io_apic {
92 unsigned int index;
93 unsigned int unused[3];
94 unsigned int data;
95};
96
97static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
98{
99 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
100 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
101}
102
103static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
104{
105 struct io_apic __iomem *io_apic = io_apic_base(apic);
106 writel(reg, &io_apic->index);
107 return readl(&io_apic->data);
108}
109
110static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
111{
112 struct io_apic __iomem *io_apic = io_apic_base(apic);
113 writel(reg, &io_apic->index);
114 writel(value, &io_apic->data);
115}
116
117/*
118 * Re-write a value: to be used for read-modify-write
119 * cycles where the read already set up the index register.
120 */
121static inline void io_apic_modify(unsigned int apic, unsigned int value)
122{
123 struct io_apic __iomem *io_apic = io_apic_base(apic);
124 writel(value, &io_apic->data);
125}
126
127/*
128 * Synchronize the IO-APIC and the CPU by doing
129 * a dummy read from the IO-APIC
130 */
131static inline void io_apic_sync(unsigned int apic)
132{
133 struct io_apic __iomem *io_apic = io_apic_base(apic);
134 readl(&io_apic->data);
135}
136
54d5d424
AR		 137#define __DO_ACTION(R, ACTION, FINAL) \
138 \
139{ \
140 int pin; \
141 struct irq_pin_list *entry = irq_2_pin + irq; \
142 \
6004e1b7 143 BUG_ON(irq >= NR_IRQS); \
54d5d424
AR		 144 for (;;) { \
145 unsigned int reg; \
146 pin = entry->pin; \
147 if (pin == -1) \
148 break; \
149 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
150 reg ACTION; \
151 io_apic_modify(entry->apic, reg); \
152 if (!entry->next) \
153 break; \
154 entry = irq_2_pin + entry->next; \
155 } \
156 FINAL; \
157}
158
eea0e11c
AK		 159union entry_union {
160 struct { u32 w1, w2; };
161 struct IO_APIC_route_entry entry;
162};
163
164static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
165{
166 union entry_union eu;
167 unsigned long flags;
168 spin_lock_irqsave(&ioapic_lock, flags);
169 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
170 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
171 spin_unlock_irqrestore(&ioapic_lock, flags);
172 return eu.entry;
173}
174
48797ebd
LT		 175/*
176 * When we write a new IO APIC routing entry, we need to write the high
177 * word first! If the mask bit in the low word is clear, we will enable
178 * the interrupt, and we need to make sure the entry is fully populated
179 * before that happens.
180 */
eea0e11c
AK		 181static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
182{
183 unsigned long flags;
184 union entry_union eu;
185 eu.entry = e;
48797ebd
LT		 186 spin_lock_irqsave(&ioapic_lock, flags);
187 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
188 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
189 spin_unlock_irqrestore(&ioapic_lock, flags);
190}
191
192/*
193 * When we mask an IO APIC routing entry, we need to write the low
194 * word first, in order to set the mask bit before we change the
195 * high bits!
196 */
197static void ioapic_mask_entry(int apic, int pin)
198{
199 unsigned long flags;
200 union entry_union eu = { .entry.mask = 1 };
201
eea0e11c
AK		 202 spin_lock_irqsave(&ioapic_lock, flags);
203 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
204 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
205 spin_unlock_irqrestore(&ioapic_lock, flags);
206}
207
54d5d424 208#ifdef CONFIG_SMP
550f2299
EB		 209static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
210{
211 int apic, pin;
212 struct irq_pin_list *entry = irq_2_pin + irq;
213
214 BUG_ON(irq >= NR_IRQS);
215 for (;;) {
216 unsigned int reg;
217 apic = entry->apic;
218 pin = entry->pin;
219 if (pin == -1)
220 break;
221 io_apic_write(apic, 0x11 + pin*2, dest);
222 reg = io_apic_read(apic, 0x10 + pin*2);
223 reg &= ~0x000000ff;
224 reg |= vector;
225 io_apic_modify(apic, reg);
226 if (!entry->next)
227 break;
228 entry = irq_2_pin + entry->next;
229 }
230}
231
54d5d424
AR		 232static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
233{
234 unsigned long flags;
235 unsigned int dest;
236 cpumask_t tmp;
550f2299 237 int vector;
54d5d424
AR		 238
239 cpus_and(tmp, mask, cpu_online_map);
240 if (cpus_empty(tmp))
241 tmp = TARGET_CPUS;
242
243 cpus_and(mask, tmp, CPU_MASK_ALL);
244
c7111c13 245 vector = assign_irq_vector(irq, mask, &tmp);
550f2299
EB		 246 if (vector < 0)
247 return;
248
550f2299 249 dest = cpu_mask_to_apicid(tmp);
54d5d424
AR		 250
251 /*
252 * Only the high 8 bits are valid.
253 */
254 dest = SET_APIC_LOGICAL_ID(dest);
255
256 spin_lock_irqsave(&ioapic_lock, flags);
c7111c13 257 __target_IO_APIC_irq(irq, dest, vector);
04b9267b 258 set_native_irq_info(irq, mask);
54d5d424
AR		 259 spin_unlock_irqrestore(&ioapic_lock, flags);
260}
261#endif
262
1da177e4
LT		 263/*
264 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
265 * shared ISA-space IRQs, so we have to support them. We are super
266 * fast in the common case, and fast for shared ISA-space IRQs.
267 */
268static void add_pin_to_irq(unsigned int irq, int apic, int pin)
269{
270 static int first_free_entry = NR_IRQS;
271 struct irq_pin_list *entry = irq_2_pin + irq;
272
6004e1b7 273 BUG_ON(irq >= NR_IRQS);
1da177e4
LT		 274 while (entry->next)
275 entry = irq_2_pin + entry->next;
276
277 if (entry->pin != -1) {
278 entry->next = first_free_entry;
279 entry = irq_2_pin + entry->next;
280 if (++first_free_entry >= PIN_MAP_SIZE)
6004e1b7 281 panic("io_apic.c: ran out of irq_2_pin entries!");
1da177e4
LT		 282 }
283 entry->apic = apic;
284 entry->pin = pin;
285}
286
1da177e4
LT		 287
288#define DO_ACTION(name,R,ACTION, FINAL) \
289 \
290 static void name##_IO_APIC_irq (unsigned int irq) \
291 __DO_ACTION(R, ACTION, FINAL)
292
293DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
294 /* mask = 1 */
295DO_ACTION( __unmask, 0, &= 0xfffeffff, )
296 /* mask = 0 */
297
298static void mask_IO_APIC_irq (unsigned int irq)
299{
300 unsigned long flags;
301
302 spin_lock_irqsave(&ioapic_lock, flags);
303 __mask_IO_APIC_irq(irq);
304 spin_unlock_irqrestore(&ioapic_lock, flags);
305}
306
307static void unmask_IO_APIC_irq (unsigned int irq)
308{
309 unsigned long flags;
310
311 spin_lock_irqsave(&ioapic_lock, flags);
312 __unmask_IO_APIC_irq(irq);
313 spin_unlock_irqrestore(&ioapic_lock, flags);
314}
315
316static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
317{
318 struct IO_APIC_route_entry entry;
1da177e4
LT		 319
320 /* Check delivery_mode to be sure we're not clearing an SMI pin */
eea0e11c 321 entry = ioapic_read_entry(apic, pin);
1da177e4
LT		 322 if (entry.delivery_mode == dest_SMI)
323 return;
324 /*
325 * Disable it in the IO-APIC irq-routing table:
326 */
48797ebd 327 ioapic_mask_entry(apic, pin);
1da177e4
LT		 328}
329
330static void clear_IO_APIC (void)
331{
332 int apic, pin;
333
334 for (apic = 0; apic < nr_ioapics; apic++)
335 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
336 clear_IO_APIC_pin(apic, pin);
337}
338
1da177e4
LT		 339int skip_ioapic_setup;
340int ioapic_force;
341
342/* dummy parsing: see setup.c */
343
344static int __init disable_ioapic_setup(char *str)
345{
346 skip_ioapic_setup = 1;
2c8c0e6b 347 return 0;
1da177e4 348}
2c8c0e6b 349early_param("noapic", disable_ioapic_setup);
1da177e4 350
2c8c0e6b
AK		 351/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
352static int __init disable_timer_pin_setup(char *arg)
1da177e4 353{
2c8c0e6b 354 disable_timer_pin_1 = 1;
1da177e4
LT		 355 return 1;
356}
2c8c0e6b 357__setup("disable_timer_pin_1", disable_timer_pin_setup);
1da177e4 358
ab9b32ee
AK		 359static int __init setup_disable_8254_timer(char *s)
360{
361 timer_over_8254 = -1;
362 return 1;
363}
364static int __init setup_enable_8254_timer(char *s)
365{
366 timer_over_8254 = 2;
367 return 1;
368}
369
370__setup("disable_8254_timer", setup_disable_8254_timer);
371__setup("enable_8254_timer", setup_enable_8254_timer);
372
1da177e4 373
1da177e4
LT		 374/*
375 * Find the IRQ entry number of a certain pin.
376 */
377static int find_irq_entry(int apic, int pin, int type)
378{
379 int i;
380
381 for (i = 0; i < mp_irq_entries; i++)
382 if (mp_irqs[i].mpc_irqtype == type &&
383 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
384 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
385 mp_irqs[i].mpc_dstirq == pin)
386 return i;
387
388 return -1;
389}
390
391/*
392 * Find the pin to which IRQ[irq] (ISA) is connected
393 */
1008fddc 394static int __init find_isa_irq_pin(int irq, int type)
1da177e4
LT		 395{
396 int i;
397
398 for (i = 0; i < mp_irq_entries; i++) {
399 int lbus = mp_irqs[i].mpc_srcbus;
400
55f05ffa 401 if (test_bit(lbus, mp_bus_not_pci) &&
1da177e4
LT		 402 (mp_irqs[i].mpc_irqtype == type) &&
403 (mp_irqs[i].mpc_srcbusirq == irq))
404
405 return mp_irqs[i].mpc_dstirq;
406 }
407 return -1;
408}
409
1008fddc
EB		 410static int __init find_isa_irq_apic(int irq, int type)
411{
412 int i;
413
414 for (i = 0; i < mp_irq_entries; i++) {
415 int lbus = mp_irqs[i].mpc_srcbus;
416
55f05ffa 417 if (test_bit(lbus, mp_bus_not_pci) &&
1008fddc
EB		 418 (mp_irqs[i].mpc_irqtype == type) &&
419 (mp_irqs[i].mpc_srcbusirq == irq))
420 break;
421 }
422 if (i < mp_irq_entries) {
423 int apic;
424 for(apic = 0; apic < nr_ioapics; apic++) {
425 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
426 return apic;
427 }
428 }
429
430 return -1;
431}
432
1da177e4
LT		 433/*
434 * Find a specific PCI IRQ entry.
435 * Not an __init, possibly needed by modules
436 */
437static int pin_2_irq(int idx, int apic, int pin);
438
439int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
440{
441 int apic, i, best_guess = -1;
442
443 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
444 bus, slot, pin);
445 if (mp_bus_id_to_pci_bus[bus] == -1) {
446 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
447 return -1;
448 }
449 for (i = 0; i < mp_irq_entries; i++) {
450 int lbus = mp_irqs[i].mpc_srcbus;
451
452 for (apic = 0; apic < nr_ioapics; apic++)
453 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
454 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
455 break;
456
55f05ffa 457 if (!test_bit(lbus, mp_bus_not_pci) &&
1da177e4
LT		 458 !mp_irqs[i].mpc_irqtype &&
459 (bus == lbus) &&
460 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
461 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
462
463 if (!(apic || IO_APIC_IRQ(irq)))
464 continue;
465
466 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
467 return irq;
468 /*
469 * Use the first all-but-pin matching entry as a
470 * best-guess fuzzy result for broken mptables.
471 */
472 if (best_guess < 0)
473 best_guess = irq;
474 }
475 }
6004e1b7 476 BUG_ON(best_guess >= NR_IRQS);
1da177e4
LT		 477 return best_guess;
478}
479
1da177e4
LT		 480/* ISA interrupts are always polarity zero edge triggered,
481 * when listed as conforming in the MP table. */
482
483#define default_ISA_trigger(idx) (0)
484#define default_ISA_polarity(idx) (0)
485
486/* PCI interrupts are always polarity one level triggered,
487 * when listed as conforming in the MP table. */
488
489#define default_PCI_trigger(idx) (1)
490#define default_PCI_polarity(idx) (1)
491
1da177e4
LT		 492static int __init MPBIOS_polarity(int idx)
493{
494 int bus = mp_irqs[idx].mpc_srcbus;
495 int polarity;
496
497 /*
498 * Determine IRQ line polarity (high active or low active):
499 */
500 switch (mp_irqs[idx].mpc_irqflag & 3)
501 {
502 case 0: /* conforms, ie. bus-type dependent polarity */
55f05ffa
AK		 503 if (test_bit(bus, mp_bus_not_pci))
504 polarity = default_ISA_polarity(idx);
505 else
506 polarity = default_PCI_polarity(idx);
1da177e4 507 break;
1da177e4
LT		 508 case 1: /* high active */
509 {
510 polarity = 0;
511 break;
512 }
513 case 2: /* reserved */
514 {
515 printk(KERN_WARNING "broken BIOS!!\n");
516 polarity = 1;
517 break;
518 }
519 case 3: /* low active */
520 {
521 polarity = 1;
522 break;
523 }
524 default: /* invalid */
525 {
526 printk(KERN_WARNING "broken BIOS!!\n");
527 polarity = 1;
528 break;
529 }
530 }
531 return polarity;
532}
533
534static int MPBIOS_trigger(int idx)
535{
536 int bus = mp_irqs[idx].mpc_srcbus;
537 int trigger;
538
539 /*
540 * Determine IRQ trigger mode (edge or level sensitive):
541 */
542 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
543 {
544 case 0: /* conforms, ie. bus-type dependent */
55f05ffa
AK		 545 if (test_bit(bus, mp_bus_not_pci))
546 trigger = default_ISA_trigger(idx);
547 else
548 trigger = default_PCI_trigger(idx);
1da177e4 549 break;
1da177e4
LT		 550 case 1: /* edge */
551 {
552 trigger = 0;
553 break;
554 }
555 case 2: /* reserved */
556 {
557 printk(KERN_WARNING "broken BIOS!!\n");
558 trigger = 1;
559 break;
560 }
561 case 3: /* level */
562 {
563 trigger = 1;
564 break;
565 }
566 default: /* invalid */
567 {
568 printk(KERN_WARNING "broken BIOS!!\n");
569 trigger = 0;
570 break;
571 }
572 }
573 return trigger;
574}
575
576static inline int irq_polarity(int idx)
577{
578 return MPBIOS_polarity(idx);
579}
580
581static inline int irq_trigger(int idx)
582{
583 return MPBIOS_trigger(idx);
584}
585
586static int pin_2_irq(int idx, int apic, int pin)
587{
588 int irq, i;
589 int bus = mp_irqs[idx].mpc_srcbus;
590
591 /*
592 * Debugging check, we are in big trouble if this message pops up!
593 */
594 if (mp_irqs[idx].mpc_dstirq != pin)
595 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
596
55f05ffa
AK		 597 if (test_bit(bus, mp_bus_not_pci)) {
598 irq = mp_irqs[idx].mpc_srcbusirq;
599 } else {
600 /*
601 * PCI IRQs are mapped in order
602 */
603 i = irq = 0;
604 while (i < apic)
605 irq += nr_ioapic_registers[i++];
606 irq += pin;
1da177e4 607 }
6004e1b7 608 BUG_ON(irq >= NR_IRQS);
1da177e4
LT		 609 return irq;
610}
611
612static inline int IO_APIC_irq_trigger(int irq)
613{
614 int apic, idx, pin;
615
616 for (apic = 0; apic < nr_ioapics; apic++) {
617 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
618 idx = find_irq_entry(apic,pin,mp_INT);
619 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
620 return irq_trigger(idx);
621 }
622 }
623 /*
624 * nonexistent IRQs are edge default
625 */
626 return 0;
627}
628
629/* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
c7111c13
EB		 630static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = {
631 [0] = FIRST_EXTERNAL_VECTOR + 0,
632 [1] = FIRST_EXTERNAL_VECTOR + 1,
633 [2] = FIRST_EXTERNAL_VECTOR + 2,
634 [3] = FIRST_EXTERNAL_VECTOR + 3,
635 [4] = FIRST_EXTERNAL_VECTOR + 4,
636 [5] = FIRST_EXTERNAL_VECTOR + 5,
637 [6] = FIRST_EXTERNAL_VECTOR + 6,
638 [7] = FIRST_EXTERNAL_VECTOR + 7,
639 [8] = FIRST_EXTERNAL_VECTOR + 8,
640 [9] = FIRST_EXTERNAL_VECTOR + 9,
641 [10] = FIRST_EXTERNAL_VECTOR + 10,
642 [11] = FIRST_EXTERNAL_VECTOR + 11,
643 [12] = FIRST_EXTERNAL_VECTOR + 12,
644 [13] = FIRST_EXTERNAL_VECTOR + 13,
645 [14] = FIRST_EXTERNAL_VECTOR + 14,
646 [15] = FIRST_EXTERNAL_VECTOR + 15,
647};
648
649static cpumask_t irq_domain[NR_IRQ_VECTORS] __read_mostly = {
650 [0] = CPU_MASK_ALL,
651 [1] = CPU_MASK_ALL,
652 [2] = CPU_MASK_ALL,
653 [3] = CPU_MASK_ALL,
654 [4] = CPU_MASK_ALL,
655 [5] = CPU_MASK_ALL,
656 [6] = CPU_MASK_ALL,
657 [7] = CPU_MASK_ALL,
658 [8] = CPU_MASK_ALL,
659 [9] = CPU_MASK_ALL,
660 [10] = CPU_MASK_ALL,
661 [11] = CPU_MASK_ALL,
662 [12] = CPU_MASK_ALL,
663 [13] = CPU_MASK_ALL,
664 [14] = CPU_MASK_ALL,
665 [15] = CPU_MASK_ALL,
666};
1da177e4 667
c7111c13 668static int __assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
1da177e4 669{
550f2299
EB		 670 /*
671 * NOTE! The local APIC isn't very good at handling
672 * multiple interrupts at the same interrupt level.
673 * As the interrupt level is determined by taking the
674 * vector number and shifting that right by 4, we
675 * want to spread these out a bit so that they don't
676 * all fall in the same interrupt level.
677 *
678 * Also, we've got to be careful not to trash gate
679 * 0x80, because int 0x80 is hm, kind of importantish. ;)
680 */
d1752aa8 681 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
550f2299
EB		 682 int old_vector = -1;
683 int cpu;
1da177e4 684
04b9267b 685 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
0a1ad60d 686
70a0a535
EB		 687 /* Only try and allocate irqs on cpus that are present */
688 cpus_and(mask, mask, cpu_online_map);
689
b940d22d
EB		 690 if (irq_vector[irq] > 0)
691 old_vector = irq_vector[irq];
c7111c13
EB		 692 if (old_vector > 0) {
693 cpus_and(*result, irq_domain[irq], mask);
694 if (!cpus_empty(*result))
695 return old_vector;
0a1ad60d 696 }
550f2299
EB		 697
698 for_each_cpu_mask(cpu, mask) {
70a0a535 699 cpumask_t domain, new_mask;
d1752aa8 700 int new_cpu;
550f2299 701 int vector, offset;
c7111c13
EB		 702
703 domain = vector_allocation_domain(cpu);
70a0a535 704 cpus_and(new_mask, domain, cpu_online_map);
c7111c13 705
d1752aa8
EB		 706 vector = current_vector;
707 offset = current_offset;
1da177e4 708next:
550f2299
EB		 709 vector += 8;
710 if (vector >= FIRST_SYSTEM_VECTOR) {
711 /* If we run out of vectors on large boxen, must share them. */
712 offset = (offset + 1) % 8;
713 vector = FIRST_DEVICE_VECTOR + offset;
714 }
d1752aa8 715 if (unlikely(current_vector == vector))
550f2299
EB		 716 continue;
717 if (vector == IA32_SYSCALL_VECTOR)
718 goto next;
70a0a535 719 for_each_cpu_mask(new_cpu, new_mask)
45edfd1d 720 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
c7111c13 721 goto next;
550f2299 722 /* Found one! */
d1752aa8
EB		 723 current_vector = vector;
724 current_offset = offset;
550f2299 725 if (old_vector >= 0) {
70a0a535 726 cpumask_t old_mask;
c7111c13 727 int old_cpu;
70a0a535
EB		 728 cpus_and(old_mask, irq_domain[irq], cpu_online_map);
729 for_each_cpu_mask(old_cpu, old_mask)
c7111c13 730 per_cpu(vector_irq, old_cpu)[old_vector] = -1;
550f2299 731 }
70a0a535 732 for_each_cpu_mask(new_cpu, new_mask)
c7111c13 733 per_cpu(vector_irq, new_cpu)[vector] = irq;
b940d22d 734 irq_vector[irq] = vector;
c7111c13
EB		 735 irq_domain[irq] = domain;
736 cpus_and(*result, domain, mask);
550f2299 737 return vector;
1da177e4 738 }
550f2299 739 return -ENOSPC;
04b9267b
EB		 740}
741
c7111c13 742static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
04b9267b
EB		 743{
744 int vector;
745 unsigned long flags;
0a1ad60d 746
04b9267b 747 spin_lock_irqsave(&vector_lock, flags);
c7111c13 748 vector = __assign_irq_vector(irq, mask, result);
26a3c49c 749 spin_unlock_irqrestore(&vector_lock, flags);
0a1ad60d 750 return vector;
1da177e4
LT		 751}
752
70a0a535
EB		 753void __setup_vector_irq(int cpu)
754{
755 /* Initialize vector_irq on a new cpu */
756 /* This function must be called with vector_lock held */
757 unsigned long flags;
758 int irq, vector;
759
760
761 /* Mark the inuse vectors */
762 for (irq = 0; irq < NR_IRQ_VECTORS; ++irq) {
763 if (!cpu_isset(cpu, irq_domain[irq]))
764 continue;
765 vector = irq_vector[irq];
766 per_cpu(vector_irq, cpu)[vector] = irq;
767 }
768 /* Mark the free vectors */
769 for (vector = 0; vector < NR_VECTORS; ++vector) {
770 irq = per_cpu(vector_irq, cpu)[vector];
771 if (irq < 0)
772 continue;
773 if (!cpu_isset(cpu, irq_domain[irq]))
774 per_cpu(vector_irq, cpu)[vector] = -1;
775 }
776}
777
778
1da177e4 779extern void (*interrupt[NR_IRQS])(void);
f29bd1ba
IM		 780
781static struct irq_chip ioapic_chip;
1da177e4
LT		 782
783#define IOAPIC_AUTO -1
784#define IOAPIC_EDGE 0
785#define IOAPIC_LEVEL 1
786
d1bef4ed 787static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1da177e4 788{
6ebcc00e
JB		 789 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
790 trigger == IOAPIC_LEVEL)
a460e745
IM		 791 set_irq_chip_and_handler_name(irq, &ioapic_chip,
792 handle_fasteoi_irq, "fasteoi");
6ebcc00e 793 else
a460e745
IM		 794 set_irq_chip_and_handler_name(irq, &ioapic_chip,
795 handle_edge_irq, "edge");
1da177e4
LT		 796}
797
798static void __init setup_IO_APIC_irqs(void)
799{
800 struct IO_APIC_route_entry entry;
801 int apic, pin, idx, irq, first_notcon = 1, vector;
802 unsigned long flags;
803
804 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
805
806 for (apic = 0; apic < nr_ioapics; apic++) {
807 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
808
809 /*
810 * add it to the IO-APIC irq-routing table:
811 */
812 memset(&entry,0,sizeof(entry));
813
814 entry.delivery_mode = INT_DELIVERY_MODE;
815 entry.dest_mode = INT_DEST_MODE;
816 entry.mask = 0; /* enable IRQ */
817 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
818
819 idx = find_irq_entry(apic,pin,mp_INT);
820 if (idx == -1) {
821 if (first_notcon) {
822 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
823 first_notcon = 0;
824 } else
825 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
826 continue;
827 }
828
829 entry.trigger = irq_trigger(idx);
830 entry.polarity = irq_polarity(idx);
831
832 if (irq_trigger(idx)) {
833 entry.trigger = 1;
834 entry.mask = 1;
835 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
836 }
837
838 irq = pin_2_irq(idx, apic, pin);
839 add_pin_to_irq(irq, apic, pin);
840
841 if (!apic && !IO_APIC_IRQ(irq))
842 continue;
843
844 if (IO_APIC_IRQ(irq)) {
550f2299 845 cpumask_t mask;
c7111c13 846 vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
550f2299
EB		 847 if (vector < 0)
848 continue;
849
550f2299 850 entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
c7111c13 851 entry.vector = vector;
1da177e4
LT		 852
853 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
854 if (!apic && (irq < 16))
855 disable_8259A_irq(irq);
856 }
eea0e11c
AK		 857 ioapic_write_entry(apic, pin, entry);
858
1da177e4 859 spin_lock_irqsave(&ioapic_lock, flags);
54d5d424 860 set_native_irq_info(irq, TARGET_CPUS);
1da177e4
LT		 861 spin_unlock_irqrestore(&ioapic_lock, flags);
862 }
863 }
864
865 if (!first_notcon)
866 apic_printk(APIC_VERBOSE," not connected.\n");
867}
868
869/*
870 * Set up the 8259A-master output pin as broadcast to all
871 * CPUs.
872 */
1008fddc 873static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1da177e4
LT		 874{
875 struct IO_APIC_route_entry entry;
876 unsigned long flags;
877
878 memset(&entry,0,sizeof(entry));
879
880 disable_8259A_irq(0);
881
882 /* mask LVT0 */
11a8e778 883 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4
LT		 884
885 /*
886 * We use logical delivery to get the timer IRQ
887 * to the first CPU.
888 */
889 entry.dest_mode = INT_DEST_MODE;
890 entry.mask = 0; /* unmask IRQ now */
891 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
892 entry.delivery_mode = INT_DELIVERY_MODE;
893 entry.polarity = 0;
894 entry.trigger = 0;
895 entry.vector = vector;
896
897 /*
898 * The timer IRQ doesn't have to know that behind the
899 * scene we have a 8259A-master in AEOI mode ...
900 */
a460e745 901 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1da177e4
LT		 902
903 /*
904 * Add it to the IO-APIC irq-routing table:
905 */
906 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 907 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
908 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1da177e4
LT		 909 spin_unlock_irqrestore(&ioapic_lock, flags);
910
911 enable_8259A_irq(0);
912}
913
914void __init UNEXPECTED_IO_APIC(void)
915{
916}
917
918void __apicdebuginit print_IO_APIC(void)
919{
920 int apic, i;
921 union IO_APIC_reg_00 reg_00;
922 union IO_APIC_reg_01 reg_01;
923 union IO_APIC_reg_02 reg_02;
924 unsigned long flags;
925
926 if (apic_verbosity == APIC_QUIET)
927 return;
928
929 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
930 for (i = 0; i < nr_ioapics; i++)
931 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
932 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
933
934 /*
935 * We are a bit conservative about what we expect. We have to
936 * know about every hardware change ASAP.
937 */
938 printk(KERN_INFO "testing the IO APIC.......................\n");
939
940 for (apic = 0; apic < nr_ioapics; apic++) {
941
942 spin_lock_irqsave(&ioapic_lock, flags);
943 reg_00.raw = io_apic_read(apic, 0);
944 reg_01.raw = io_apic_read(apic, 1);
945 if (reg_01.bits.version >= 0x10)
946 reg_02.raw = io_apic_read(apic, 2);
947 spin_unlock_irqrestore(&ioapic_lock, flags);
948
949 printk("\n");
950 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
951 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
952 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
953 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
954 UNEXPECTED_IO_APIC();
955
956 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
957 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
958 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
959 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
960 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
961 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
962 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
963 (reg_01.bits.entries != 0x2E) &&
964 (reg_01.bits.entries != 0x3F) &&
965 (reg_01.bits.entries != 0x03)
966 )
967 UNEXPECTED_IO_APIC();
968
969 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
970 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
971 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
972 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
973 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
974 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
975 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
976 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
977 )
978 UNEXPECTED_IO_APIC();
979 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
980 UNEXPECTED_IO_APIC();
981
982 if (reg_01.bits.version >= 0x10) {
983 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
984 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
985 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
986 UNEXPECTED_IO_APIC();
987 }
988
989 printk(KERN_DEBUG ".... IRQ redirection table:\n");
990
991 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
992 " Stat Dest Deli Vect: \n");
993
994 for (i = 0; i <= reg_01.bits.entries; i++) {
995 struct IO_APIC_route_entry entry;
996
eea0e11c 997 entry = ioapic_read_entry(apic, i);
1da177e4
LT		 998
999 printk(KERN_DEBUG " %02x %03X %02X ",
1000 i,
1001 entry.dest.logical.logical_dest,
1002 entry.dest.physical.physical_dest
1003 );
1004
1005 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1006 entry.mask,
1007 entry.trigger,
1008 entry.irr,
1009 entry.polarity,
1010 entry.delivery_status,
1011 entry.dest_mode,
1012 entry.delivery_mode,
1013 entry.vector
1014 );
1015 }
1016 }
1da177e4
LT		 1017 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1018 for (i = 0; i < NR_IRQS; i++) {
1019 struct irq_pin_list *entry = irq_2_pin + i;
1020 if (entry->pin < 0)
1021 continue;
04b9267b 1022 printk(KERN_DEBUG "IRQ%d ", i);
1da177e4
LT		 1023 for (;;) {
1024 printk("-> %d:%d", entry->apic, entry->pin);
1025 if (!entry->next)
1026 break;
1027 entry = irq_2_pin + entry->next;
1028 }
1029 printk("\n");
1030 }
1031
1032 printk(KERN_INFO ".................................... done.\n");
1033
1034 return;
1035}
1036
1037#if 0
1038
1039static __apicdebuginit void print_APIC_bitfield (int base)
1040{
1041 unsigned int v;
1042 int i, j;
1043
1044 if (apic_verbosity == APIC_QUIET)
1045 return;
1046
1047 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1048 for (i = 0; i < 8; i++) {
1049 v = apic_read(base + i*0x10);
1050 for (j = 0; j < 32; j++) {
1051 if (v & (1<<j))
1052 printk("1");
1053 else
1054 printk("0");
1055 }
1056 printk("\n");
1057 }
1058}
1059
1060void __apicdebuginit print_local_APIC(void * dummy)
1061{
1062 unsigned int v, ver, maxlvt;
1063
1064 if (apic_verbosity == APIC_QUIET)
1065 return;
1066
1067 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1068 smp_processor_id(), hard_smp_processor_id());
1069 v = apic_read(APIC_ID);
1070 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1071 v = apic_read(APIC_LVR);
1072 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1073 ver = GET_APIC_VERSION(v);
1074 maxlvt = get_maxlvt();
1075
1076 v = apic_read(APIC_TASKPRI);
1077 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1078
5a40b7c2
AK		 1079 v = apic_read(APIC_ARBPRI);
1080 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1081 v & APIC_ARBPRI_MASK);
1082 v = apic_read(APIC_PROCPRI);
1083 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1da177e4
LT		 1084
1085 v = apic_read(APIC_EOI);
1086 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1087 v = apic_read(APIC_RRR);
1088 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1089 v = apic_read(APIC_LDR);
1090 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1091 v = apic_read(APIC_DFR);
1092 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1093 v = apic_read(APIC_SPIV);
1094 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1095
1096 printk(KERN_DEBUG "... APIC ISR field:\n");
1097 print_APIC_bitfield(APIC_ISR);
1098 printk(KERN_DEBUG "... APIC TMR field:\n");
1099 print_APIC_bitfield(APIC_TMR);
1100 printk(KERN_DEBUG "... APIC IRR field:\n");
1101 print_APIC_bitfield(APIC_IRR);
1102
5a40b7c2
AK		 1103 v = apic_read(APIC_ESR);
1104 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1da177e4
LT		 1105
1106 v = apic_read(APIC_ICR);
1107 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1108 v = apic_read(APIC_ICR2);
1109 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1110
1111 v = apic_read(APIC_LVTT);
1112 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1113
1114 if (maxlvt > 3) { /* PC is LVT#4. */
1115 v = apic_read(APIC_LVTPC);
1116 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1117 }
1118 v = apic_read(APIC_LVT0);
1119 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1120 v = apic_read(APIC_LVT1);
1121 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1122
1123 if (maxlvt > 2) { /* ERR is LVT#3. */
1124 v = apic_read(APIC_LVTERR);
1125 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1126 }
1127
1128 v = apic_read(APIC_TMICT);
1129 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1130 v = apic_read(APIC_TMCCT);
1131 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1132 v = apic_read(APIC_TDCR);
1133 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1134 printk("\n");
1135}
1136
1137void print_all_local_APICs (void)
1138{
1139 on_each_cpu(print_local_APIC, NULL, 1, 1);
1140}
1141
1142void __apicdebuginit print_PIC(void)
1143{
1da177e4
LT		 1144 unsigned int v;
1145 unsigned long flags;
1146
1147 if (apic_verbosity == APIC_QUIET)
1148 return;
1149
1150 printk(KERN_DEBUG "\nprinting PIC contents\n");
1151
1152 spin_lock_irqsave(&i8259A_lock, flags);
1153
1154 v = inb(0xa1) << 8 | inb(0x21);
1155 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1156
1157 v = inb(0xa0) << 8 | inb(0x20);
1158 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1159
1160 outb(0x0b,0xa0);
1161 outb(0x0b,0x20);
1162 v = inb(0xa0) << 8 | inb(0x20);
1163 outb(0x0a,0xa0);
1164 outb(0x0a,0x20);
1165
1166 spin_unlock_irqrestore(&i8259A_lock, flags);
1167
1168 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1169
1170 v = inb(0x4d1) << 8 | inb(0x4d0);
1171 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1172}
1173
1174#endif /* 0 */
1175
1176static void __init enable_IO_APIC(void)
1177{
1178 union IO_APIC_reg_01 reg_01;
1008fddc
EB		 1179 int i8259_apic, i8259_pin;
1180 int i, apic;
1da177e4
LT		 1181 unsigned long flags;
1182
1183 for (i = 0; i < PIN_MAP_SIZE; i++) {
1184 irq_2_pin[i].pin = -1;
1185 irq_2_pin[i].next = 0;
1186 }
1da177e4
LT		 1187
1188 /*
1189 * The number of IO-APIC IRQ registers (== #pins):
1190 */
1008fddc 1191 for (apic = 0; apic < nr_ioapics; apic++) {
1da177e4 1192 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc 1193 reg_01.raw = io_apic_read(apic, 1);
1da177e4 1194 spin_unlock_irqrestore(&ioapic_lock, flags);
1008fddc
EB		 1195 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1196 }
1197 for(apic = 0; apic < nr_ioapics; apic++) {
1198 int pin;
1199 /* See if any of the pins is in ExtINT mode */
1200 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1201 struct IO_APIC_route_entry entry;
eea0e11c 1202 entry = ioapic_read_entry(apic, pin);
1008fddc
EB		 1203
1204 /* If the interrupt line is enabled and in ExtInt mode
1205 * I have found the pin where the i8259 is connected.
1206 */
1207 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1208 ioapic_i8259.apic = apic;
1209 ioapic_i8259.pin = pin;
1210 goto found_i8259;
1211 }
1212 }
1213 }
1214 found_i8259:
1215 /* Look to see what if the MP table has reported the ExtINT */
1216 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1217 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1218 /* Trust the MP table if nothing is setup in the hardware */
1219 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1220 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1221 ioapic_i8259.pin = i8259_pin;
1222 ioapic_i8259.apic = i8259_apic;
1223 }
1224 /* Complain if the MP table and the hardware disagree */
1225 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1226 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1227 {
1228 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1da177e4
LT		 1229 }
1230
1231 /*
1232 * Do not trust the IO-APIC being empty at bootup
1233 */
1234 clear_IO_APIC();
1235}
1236
1237/*
1238 * Not an __init, needed by the reboot code
1239 */
1240void disable_IO_APIC(void)
1241{
1242 /*
1243 * Clear the IO-APIC before rebooting:
1244 */
1245 clear_IO_APIC();
1246
208fb931 1247 /*
0b968d23 1248 * If the i8259 is routed through an IOAPIC
208fb931 1249 * Put that IOAPIC in virtual wire mode
0b968d23 1250 * so legacy interrupts can be delivered.
208fb931 1251 */
1008fddc 1252 if (ioapic_i8259.pin != -1) {
208fb931 1253 struct IO_APIC_route_entry entry;
208fb931
EB		 1254
1255 memset(&entry, 0, sizeof(entry));
1256 entry.mask = 0; /* Enabled */
1257 entry.trigger = 0; /* Edge */
1258 entry.irr = 0;
1259 entry.polarity = 0; /* High */
1260 entry.delivery_status = 0;
1261 entry.dest_mode = 0; /* Physical */
1008fddc 1262 entry.delivery_mode = dest_ExtINT; /* ExtInt */
208fb931 1263 entry.vector = 0;
af5b9804
VG		 1264 entry.dest.physical.physical_dest =
1265 GET_APIC_ID(apic_read(APIC_ID));
208fb931 1266
208fb931
EB		 1267 /*
1268 * Add it to the IO-APIC irq-routing table:
1269 */
eea0e11c 1270 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
208fb931
EB		 1271 }
1272
1008fddc 1273 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1da177e4
LT		 1274}
1275
1da177e4
LT		 1276/*
1277 * There is a nasty bug in some older SMP boards, their mptable lies
1278 * about the timer IRQ. We do the following to work around the situation:
1279 *
1280 * - timer IRQ defaults to IO-APIC IRQ
1281 * - if this function detects that timer IRQs are defunct, then we fall
1282 * back to ISA timer IRQs
1283 */
1284static int __init timer_irq_works(void)
1285{
1286 unsigned long t1 = jiffies;
1287
1288 local_irq_enable();
1289 /* Let ten ticks pass... */
1290 mdelay((10 * 1000) / HZ);
1291
1292 /*
1293 * Expect a few ticks at least, to be sure some possible
1294 * glue logic does not lock up after one or two first
1295 * ticks in a non-ExtINT mode. Also the local APIC
1296 * might have cached one ExtINT interrupt. Finally, at
1297 * least one tick may be lost due to delays.
1298 */
1299
1300 /* jiffies wrap? */
1301 if (jiffies - t1 > 4)
1302 return 1;
1303 return 0;
1304}
1305
1306/*
1307 * In the SMP+IOAPIC case it might happen that there are an unspecified
1308 * number of pending IRQ events unhandled. These cases are very rare,
1309 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1310 * better to do it this way as thus we do not have to be aware of
1311 * 'pending' interrupts in the IRQ path, except at this point.
1312 */
1313/*
1314 * Edge triggered needs to resend any interrupt
1315 * that was delayed but this is now handled in the device
1316 * independent code.
1317 */
1318
1319/*
1320 * Starting up a edge-triggered IO-APIC interrupt is
1321 * nasty - we need to make sure that we get the edge.
1322 * If it is already asserted for some reason, we need
1323 * return 1 to indicate that is was pending.
1324 *
1325 * This is not complete - we should be able to fake
1326 * an edge even if it isn't on the 8259A...
1327 */
1328
f29bd1ba 1329static unsigned int startup_ioapic_irq(unsigned int irq)
1da177e4
LT		 1330{
1331 int was_pending = 0;
1332 unsigned long flags;
1333
1334 spin_lock_irqsave(&ioapic_lock, flags);
1335 if (irq < 16) {
1336 disable_8259A_irq(irq);
1337 if (i8259A_irq_pending(irq))
1338 was_pending = 1;
1339 }
1340 __unmask_IO_APIC_irq(irq);
1341 spin_unlock_irqrestore(&ioapic_lock, flags);
1342
1343 return was_pending;
1344}
1345
04b9267b 1346static int ioapic_retrigger_irq(unsigned int irq)
c0ad90a3 1347{
550f2299
EB		 1348 cpumask_t mask;
1349 unsigned vector;
6bf2dafa 1350 unsigned long flags;
550f2299 1351
6bf2dafa 1352 spin_lock_irqsave(&vector_lock, flags);
550f2299
EB		 1353 vector = irq_vector[irq];
1354 cpus_clear(mask);
6bf2dafa 1355 cpu_set(first_cpu(irq_domain[irq]), mask);
550f2299 1356
6bf2dafa
EB		 1357 send_IPI_mask(mask, vector);
1358 spin_unlock_irqrestore(&vector_lock, flags);
c0ad90a3
IM		 1359
1360 return 1;
1361}
1362
1da177e4
LT		 1363/*
1364 * Level and edge triggered IO-APIC interrupts need different handling,
1365 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1366 * handled with the level-triggered descriptor, but that one has slightly
1367 * more overhead. Level-triggered interrupts cannot be handled with the
1368 * edge-triggered handler, without risking IRQ storms and other ugly
1369 * races.
1370 */
1371
0be6652f
EB		 1372static void ack_apic_edge(unsigned int irq)
1373{
1374 move_native_irq(irq);
1375 ack_APIC_irq();
1376}
1377
1378static void ack_apic_level(unsigned int irq)
1379{
1380 int do_unmask_irq = 0;
1381
1382#if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1383 /* If we are moving the irq we need to mask it */
1384 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1385 do_unmask_irq = 1;
1386 mask_IO_APIC_irq(irq);
1387 }
1388#endif
1389
1390 /*
1391 * We must acknowledge the irq before we move it or the acknowledge will
1392 * not propogate properly.
1393 */
1394 ack_APIC_irq();
1395
1396 /* Now we can move and renable the irq */
1397 move_masked_irq(irq);
1398 if (unlikely(do_unmask_irq))
1399 unmask_IO_APIC_irq(irq);
1400}
1401
f29bd1ba
IM		 1402static struct irq_chip ioapic_chip __read_mostly = {
1403 .name = "IO-APIC",
04b9267b
EB		 1404 .startup = startup_ioapic_irq,
1405 .mask = mask_IO_APIC_irq,
1406 .unmask = unmask_IO_APIC_irq,
0be6652f
EB		 1407 .ack = ack_apic_edge,
1408 .eoi = ack_apic_level,
54d5d424 1409#ifdef CONFIG_SMP
04b9267b 1410 .set_affinity = set_ioapic_affinity_irq,
54d5d424 1411#endif
04b9267b 1412 .retrigger = ioapic_retrigger_irq,
1da177e4
LT		 1413};
1414
1415static inline void init_IO_APIC_traps(void)
1416{
1417 int irq;
1418
1419 /*
1420 * NOTE! The local APIC isn't very good at handling
1421 * multiple interrupts at the same interrupt level.
1422 * As the interrupt level is determined by taking the
1423 * vector number and shifting that right by 4, we
1424 * want to spread these out a bit so that they don't
1425 * all fall in the same interrupt level.
1426 *
1427 * Also, we've got to be careful not to trash gate
1428 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1429 */
1430 for (irq = 0; irq < NR_IRQS ; irq++) {
1431 int tmp = irq;
b940d22d 1432 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
1da177e4
LT		 1433 /*
1434 * Hmm.. We don't have an entry for this,
1435 * so default to an old-fashioned 8259
1436 * interrupt if we can..
1437 */
1438 if (irq < 16)
1439 make_8259A_irq(irq);
1440 else
1441 /* Strange. Oh, well.. */
f29bd1ba 1442 irq_desc[irq].chip = &no_irq_chip;
1da177e4
LT		 1443 }
1444 }
1445}
1446
1447static void enable_lapic_irq (unsigned int irq)
1448{
1449 unsigned long v;
1450
1451 v = apic_read(APIC_LVT0);
11a8e778 1452 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1da177e4
LT		 1453}
1454
1455static void disable_lapic_irq (unsigned int irq)
1456{
1457 unsigned long v;
1458
1459 v = apic_read(APIC_LVT0);
11a8e778 1460 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1da177e4
LT		 1461}
1462
1463static void ack_lapic_irq (unsigned int irq)
1464{
1465 ack_APIC_irq();
1466}
1467
1468static void end_lapic_irq (unsigned int i) { /* nothing */ }
1469
6c231b7b 1470static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1da177e4
LT		 1471 .typename = "local-APIC-edge",
1472 .startup = NULL, /* startup_irq() not used for IRQ0 */
1473 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1474 .enable = enable_lapic_irq,
1475 .disable = disable_lapic_irq,
1476 .ack = ack_lapic_irq,
1477 .end = end_lapic_irq,
1478};
1479
1480static void setup_nmi (void)
1481{
1482 /*
1483 * Dirty trick to enable the NMI watchdog ...
1484 * We put the 8259A master into AEOI mode and
1485 * unmask on all local APICs LVT0 as NMI.
1486 *
1487 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1488 * is from Maciej W. Rozycki - so we do not have to EOI from
1489 * the NMI handler or the timer interrupt.
1490 */
1491 printk(KERN_INFO "activating NMI Watchdog ...");
1492
1493 enable_NMI_through_LVT0(NULL);
1494
1495 printk(" done.\n");
1496}
1497
1498/*
1499 * This looks a bit hackish but it's about the only one way of sending
1500 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1501 * not support the ExtINT mode, unfortunately. We need to send these
1502 * cycles as some i82489DX-based boards have glue logic that keeps the
1503 * 8259A interrupt line asserted until INTA. --macro
1504 */
1505static inline void unlock_ExtINT_logic(void)
1506{
1008fddc 1507 int apic, pin, i;
1da177e4
LT		 1508 struct IO_APIC_route_entry entry0, entry1;
1509 unsigned char save_control, save_freq_select;
1510 unsigned long flags;
1511
1008fddc
EB		 1512 pin = find_isa_irq_pin(8, mp_INT);
1513 apic = find_isa_irq_apic(8, mp_INT);
1da177e4
LT		 1514 if (pin == -1)
1515 return;
1516
1517 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 1518 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1519 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1da177e4 1520 spin_unlock_irqrestore(&ioapic_lock, flags);
1008fddc 1521 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 1522
1523 memset(&entry1, 0, sizeof(entry1));
1524
1525 entry1.dest_mode = 0; /* physical delivery */
1526 entry1.mask = 0; /* unmask IRQ now */
1527 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1528 entry1.delivery_mode = dest_ExtINT;
1529 entry1.polarity = entry0.polarity;
1530 entry1.trigger = 0;
1531 entry1.vector = 0;
1532
1533 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 1534 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1535 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1da177e4
LT		 1536 spin_unlock_irqrestore(&ioapic_lock, flags);
1537
1538 save_control = CMOS_READ(RTC_CONTROL);
1539 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1540 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1541 RTC_FREQ_SELECT);
1542 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1543
1544 i = 100;
1545 while (i-- > 0) {
1546 mdelay(10);
1547 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1548 i -= 10;
1549 }
1550
1551 CMOS_WRITE(save_control, RTC_CONTROL);
1552 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1008fddc 1553 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 1554
1555 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 1556 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1557 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1da177e4
LT		 1558 spin_unlock_irqrestore(&ioapic_lock, flags);
1559}
1560
1561/*
1562 * This code may look a bit paranoid, but it's supposed to cooperate with
1563 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1564 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1565 * fanatically on his truly buggy board.
ab9b32ee
AK		 1566 *
1567 * FIXME: really need to revamp this for modern platforms only.
1da177e4
LT		 1568 */
1569static inline void check_timer(void)
1570{
1008fddc 1571 int apic1, pin1, apic2, pin2;
1da177e4 1572 int vector;
c7111c13 1573 cpumask_t mask;
1da177e4
LT		 1574
1575 /*
1576 * get/set the timer IRQ vector:
1577 */
1578 disable_8259A_irq(0);
c7111c13 1579 vector = assign_irq_vector(0, TARGET_CPUS, &mask);
1da177e4
LT		 1580
1581 /*
1582 * Subtle, code in do_timer_interrupt() expects an AEOI
1583 * mode for the 8259A whenever interrupts are routed
1584 * through I/O APICs. Also IRQ0 has to be enabled in
1585 * the 8259A which implies the virtual wire has to be
1586 * disabled in the local APIC.
1587 */
11a8e778 1588 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4 1589 init_8259A(1);
ab9b32ee
AK		 1590 if (timer_over_8254 > 0)
1591 enable_8259A_irq(0);
1da177e4 1592
1008fddc
EB		 1593 pin1 = find_isa_irq_pin(0, mp_INT);
1594 apic1 = find_isa_irq_apic(0, mp_INT);
1595 pin2 = ioapic_i8259.pin;
1596 apic2 = ioapic_i8259.apic;
1da177e4 1597
1008fddc
EB		 1598 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1599 vector, apic1, pin1, apic2, pin2);
1da177e4
LT		 1600
1601 if (pin1 != -1) {
1602 /*
1603 * Ok, does IRQ0 through the IOAPIC work?
1604 */
1605 unmask_IO_APIC_irq(0);
14d98cad 1606 if (!no_timer_check && timer_irq_works()) {
1da177e4
LT		 1607 nmi_watchdog_default();
1608 if (nmi_watchdog == NMI_IO_APIC) {
1609 disable_8259A_irq(0);
1610 setup_nmi();
1611 enable_8259A_irq(0);
1da177e4 1612 }
66759a01
CE		 1613 if (disable_timer_pin_1 > 0)
1614 clear_IO_APIC_pin(0, pin1);
1da177e4
LT		 1615 return;
1616 }
1008fddc
EB		 1617 clear_IO_APIC_pin(apic1, pin1);
1618 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1619 "connected to IO-APIC\n");
1da177e4
LT		 1620 }
1621
1008fddc
EB		 1622 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1623 "through the 8259A ... ");
1da177e4 1624 if (pin2 != -1) {
1008fddc
EB		 1625 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1626 apic2, pin2);
1da177e4
LT		 1627 /*
1628 * legacy devices should be connected to IO APIC #0
1629 */
1008fddc 1630 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1da177e4 1631 if (timer_irq_works()) {
5b922cd4 1632 apic_printk(APIC_VERBOSE," works.\n");
1da177e4
LT		 1633 nmi_watchdog_default();
1634 if (nmi_watchdog == NMI_IO_APIC) {
1635 setup_nmi();
1da177e4
LT		 1636 }
1637 return;
1638 }
1639 /*
1640 * Cleanup, just in case ...
1641 */
1008fddc 1642 clear_IO_APIC_pin(apic2, pin2);
1da177e4 1643 }
5b922cd4 1644 apic_printk(APIC_VERBOSE," failed.\n");
1da177e4 1645
1f992153 1646 if (nmi_watchdog == NMI_IO_APIC) {
1da177e4
LT		 1647 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1648 nmi_watchdog = 0;
1649 }
1650
1651 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1652
1653 disable_8259A_irq(0);
d1bef4ed 1654 irq_desc[0].chip = &lapic_irq_type;
11a8e778 1655 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1da177e4
LT		 1656 enable_8259A_irq(0);
1657
1658 if (timer_irq_works()) {
5b922cd4 1659 apic_printk(APIC_VERBOSE," works.\n");
1da177e4
LT		 1660 return;
1661 }
11a8e778 1662 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1da177e4
LT		 1663 apic_printk(APIC_VERBOSE," failed.\n");
1664
1665 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1666
1667 init_8259A(0);
1668 make_8259A_irq(0);
11a8e778 1669 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4
LT		 1670
1671 unlock_ExtINT_logic();
1672
1673 if (timer_irq_works()) {
1674 apic_printk(APIC_VERBOSE," works.\n");
1675 return;
1676 }
1677 apic_printk(APIC_VERBOSE," failed :(.\n");
1678 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1679}
1680
14d98cad
AK		 1681static int __init notimercheck(char *s)
1682{
1683 no_timer_check = 1;
1684 return 1;
1685}
1686__setup("no_timer_check", notimercheck);
1687
1da177e4
LT		 1688/*
1689 *
1690 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1691 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1692 * Linux doesn't really care, as it's not actually used
1693 * for any interrupt handling anyway.
1694 */
1695#define PIC_IRQS (1<<2)
1696
1697void __init setup_IO_APIC(void)
1698{
1699 enable_IO_APIC();
1700
1701 if (acpi_ioapic)
1702 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1703 else
1704 io_apic_irqs = ~PIC_IRQS;
1705
1706 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1707
1da177e4
LT		 1708 sync_Arb_IDs();
1709 setup_IO_APIC_irqs();
1710 init_IO_APIC_traps();
1711 check_timer();
1712 if (!acpi_ioapic)
1713 print_IO_APIC();
1714}
1715
1716struct sysfs_ioapic_data {
1717 struct sys_device dev;
1718 struct IO_APIC_route_entry entry[0];
1719};
1720static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1721
0b9c33a7 1722static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4
LT		 1723{
1724 struct IO_APIC_route_entry *entry;
1725 struct sysfs_ioapic_data *data;
1da177e4
LT		 1726 int i;
1727
1728 data = container_of(dev, struct sysfs_ioapic_data, dev);
1729 entry = data->entry;
eea0e11c
AK		 1730 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1731 *entry = ioapic_read_entry(dev->id, i);
1da177e4
LT		 1732
1733 return 0;
1734}
1735
1736static int ioapic_resume(struct sys_device *dev)
1737{
1738 struct IO_APIC_route_entry *entry;
1739 struct sysfs_ioapic_data *data;
1740 unsigned long flags;
1741 union IO_APIC_reg_00 reg_00;
1742 int i;
1743
1744 data = container_of(dev, struct sysfs_ioapic_data, dev);
1745 entry = data->entry;
1746
1747 spin_lock_irqsave(&ioapic_lock, flags);
1748 reg_00.raw = io_apic_read(dev->id, 0);
1749 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1750 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1751 io_apic_write(dev->id, 0, reg_00.raw);
1752 }
1da177e4 1753 spin_unlock_irqrestore(&ioapic_lock, flags);
eea0e11c
AK		 1754 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1755 ioapic_write_entry(dev->id, i, entry[i]);
1da177e4
LT		 1756
1757 return 0;
1758}
1759
1760static struct sysdev_class ioapic_sysdev_class = {
1761 set_kset_name("ioapic"),
1762 .suspend = ioapic_suspend,
1763 .resume = ioapic_resume,
1764};
1765
1766static int __init ioapic_init_sysfs(void)
1767{
1768 struct sys_device * dev;
1769 int i, size, error = 0;
1770
1771 error = sysdev_class_register(&ioapic_sysdev_class);
1772 if (error)
1773 return error;
1774
1775 for (i = 0; i < nr_ioapics; i++ ) {
1776 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1777 * sizeof(struct IO_APIC_route_entry);
1778 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1779 if (!mp_ioapic_data[i]) {
1780 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1781 continue;
1782 }
1783 memset(mp_ioapic_data[i], 0, size);
1784 dev = &mp_ioapic_data[i]->dev;
1785 dev->id = i;
1786 dev->cls = &ioapic_sysdev_class;
1787 error = sysdev_register(dev);
1788 if (error) {
1789 kfree(mp_ioapic_data[i]);
1790 mp_ioapic_data[i] = NULL;
1791 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1792 continue;
1793 }
1794 }
1795
1796 return 0;
1797}
1798
1799device_initcall(ioapic_init_sysfs);
1800
c4fa0bbf 1801/*
04b9267b 1802 * Dynamic irq allocate and deallocation
c4fa0bbf
EB		 1803 */
1804int create_irq(void)
1805{
04b9267b
EB		 1806 /* Allocate an unused irq */
1807 int irq;
1808 int new;
1809 int vector = 0;
c4fa0bbf 1810 unsigned long flags;
c7111c13 1811 cpumask_t mask;
c4fa0bbf 1812
04b9267b
EB		 1813 irq = -ENOSPC;
1814 spin_lock_irqsave(&vector_lock, flags);
1815 for (new = (NR_IRQS - 1); new >= 0; new--) {
1816 if (platform_legacy_irq(new))
1817 continue;
1818 if (irq_vector[new] != 0)
1819 continue;
c7111c13 1820 vector = __assign_irq_vector(new, TARGET_CPUS, &mask);
04b9267b
EB		 1821 if (likely(vector > 0))
1822 irq = new;
1823 break;
1824 }
1825 spin_unlock_irqrestore(&vector_lock, flags);
c4fa0bbf 1826
04b9267b 1827 if (irq >= 0) {
c4fa0bbf
EB		 1828 dynamic_irq_init(irq);
1829 }
1830 return irq;
1831}
1832
1833void destroy_irq(unsigned int irq)
1834{
1835 unsigned long flags;
c4fa0bbf
EB		 1836
1837 dynamic_irq_cleanup(irq);
1838
1839 spin_lock_irqsave(&vector_lock, flags);
c4fa0bbf
EB		 1840 irq_vector[irq] = 0;
1841 spin_unlock_irqrestore(&vector_lock, flags);
1842}
c4fa0bbf 1843
589e367f
EB		 1844/*
1845 * MSI mesage composition
1846 */
1847#ifdef CONFIG_PCI_MSI
3b7d1921 1848static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
589e367f 1849{
589e367f
EB		 1850 int vector;
1851 unsigned dest;
c7111c13 1852 cpumask_t tmp;
589e367f 1853
c7111c13 1854 vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
589e367f 1855 if (vector >= 0) {
589e367f
EB		 1856 dest = cpu_mask_to_apicid(tmp);
1857
1858 msg->address_hi = MSI_ADDR_BASE_HI;
1859 msg->address_lo =
1860 MSI_ADDR_BASE_LO |
1861 ((INT_DEST_MODE == 0) ?
1862 MSI_ADDR_DEST_MODE_PHYSICAL:
1863 MSI_ADDR_DEST_MODE_LOGICAL) |
1864 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1865 MSI_ADDR_REDIRECTION_CPU:
1866 MSI_ADDR_REDIRECTION_LOWPRI) |
1867 MSI_ADDR_DEST_ID(dest);
1868
1869 msg->data =
1870 MSI_DATA_TRIGGER_EDGE |
1871 MSI_DATA_LEVEL_ASSERT |
1872 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1873 MSI_DATA_DELIVERY_FIXED:
1874 MSI_DATA_DELIVERY_LOWPRI) |
1875 MSI_DATA_VECTOR(vector);
1876 }
1877 return vector;
1878}
1879
3b7d1921
EB		 1880#ifdef CONFIG_SMP
1881static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
589e367f 1882{
3b7d1921
EB		 1883 struct msi_msg msg;
1884 unsigned int dest;
1885 cpumask_t tmp;
589e367f 1886 int vector;
3b7d1921
EB		 1887
1888 cpus_and(tmp, mask, cpu_online_map);
1889 if (cpus_empty(tmp))
1890 tmp = TARGET_CPUS;
1891
1892 cpus_and(mask, tmp, CPU_MASK_ALL);
589e367f 1893
c7111c13 1894 vector = assign_irq_vector(irq, mask, &tmp);
3b7d1921
EB		 1895 if (vector < 0)
1896 return;
550f2299 1897
3b7d1921 1898 dest = cpu_mask_to_apicid(tmp);
589e367f 1899
3b7d1921
EB		 1900 read_msi_msg(irq, &msg);
1901
1902 msg.data &= ~MSI_DATA_VECTOR_MASK;
1903 msg.data |= MSI_DATA_VECTOR(vector);
1904 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1905 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1906
1907 write_msi_msg(irq, &msg);
1908 set_native_irq_info(irq, mask);
589e367f 1909}
3b7d1921 1910#endif /* CONFIG_SMP */
589e367f 1911
3b7d1921
EB		 1912/*
1913 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1914 * which implement the MSI or MSI-X Capability Structure.
1915 */
1916static struct irq_chip msi_chip = {
1917 .name = "PCI-MSI",
1918 .unmask = unmask_msi_irq,
1919 .mask = mask_msi_irq,
1920 .ack = ack_apic_edge,
1921#ifdef CONFIG_SMP
1922 .set_affinity = set_msi_irq_affinity,
1923#endif
1924 .retrigger = ioapic_retrigger_irq,
589e367f
EB		 1925};
1926
3b7d1921
EB		 1927int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev)
1928{
1929 struct msi_msg msg;
1930 int ret;
1931 ret = msi_compose_msg(dev, irq, &msg);
1932 if (ret < 0)
1933 return ret;
1934
1935 write_msi_msg(irq, &msg);
1936
a460e745 1937 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3b7d1921
EB		 1938
1939 return 0;
1940}
1941
1942void arch_teardown_msi_irq(unsigned int irq)
1943{
1944 return;
1945}
1946
1947#endif /* CONFIG_PCI_MSI */
589e367f 1948
8b955b0d
EB		 1949/*
1950 * Hypertransport interrupt support
1951 */
1952#ifdef CONFIG_HT_IRQ
1953
1954#ifdef CONFIG_SMP
1955
1956static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1957{
1958 u32 low, high;
1959 low = read_ht_irq_low(irq);
1960 high = read_ht_irq_high(irq);
1961
1962 low &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
1963 high &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
1964
1965 low |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
1966 high |= HT_IRQ_HIGH_DEST_ID(dest);
1967
1968 write_ht_irq_low(irq, low);
1969 write_ht_irq_high(irq, high);
1970}
1971
1972static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
1973{
1974 unsigned int dest;
1975 cpumask_t tmp;
1976 int vector;
1977
1978 cpus_and(tmp, mask, cpu_online_map);
1979 if (cpus_empty(tmp))
1980 tmp = TARGET_CPUS;
1981
1982 cpus_and(mask, tmp, CPU_MASK_ALL);
1983
c7111c13 1984 vector = assign_irq_vector(irq, mask, &tmp);
8b955b0d
EB		 1985 if (vector < 0)
1986 return;
1987
8b955b0d
EB		 1988 dest = cpu_mask_to_apicid(tmp);
1989
1990 target_ht_irq(irq, dest, vector & 0xff);
1991 set_native_irq_info(irq, mask);
1992}
1993#endif
1994
c37e108d 1995static struct irq_chip ht_irq_chip = {
8b955b0d
EB		 1996 .name = "PCI-HT",
1997 .mask = mask_ht_irq,
1998 .unmask = unmask_ht_irq,
1999 .ack = ack_apic_edge,
2000#ifdef CONFIG_SMP
2001 .set_affinity = set_ht_irq_affinity,
2002#endif
2003 .retrigger = ioapic_retrigger_irq,
2004};
2005
2006int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2007{
2008 int vector;
c7111c13 2009 cpumask_t tmp;
8b955b0d 2010
c7111c13 2011 vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
8b955b0d
EB		 2012 if (vector >= 0) {
2013 u32 low, high;
2014 unsigned dest;
8b955b0d 2015
8b955b0d
EB		 2016 dest = cpu_mask_to_apicid(tmp);
2017
2018 high = HT_IRQ_HIGH_DEST_ID(dest);
2019
2020 low = HT_IRQ_LOW_BASE |
2021 HT_IRQ_LOW_DEST_ID(dest) |
2022 HT_IRQ_LOW_VECTOR(vector) |
2023 ((INT_DEST_MODE == 0) ?
2024 HT_IRQ_LOW_DM_PHYSICAL :
2025 HT_IRQ_LOW_DM_LOGICAL) |
2026 HT_IRQ_LOW_RQEOI_EDGE |
2027 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2028 HT_IRQ_LOW_MT_FIXED :
2029 HT_IRQ_LOW_MT_ARBITRATED);
2030
2031 write_ht_irq_low(irq, low);
2032 write_ht_irq_high(irq, high);
2033
a460e745
IM		 2034 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2035 handle_edge_irq, "edge");
8b955b0d
EB		 2036 }
2037 return vector;
2038}
2039#endif /* CONFIG_HT_IRQ */
2040
1da177e4
LT		 2041/* --------------------------------------------------------------------------
2042 ACPI-based IOAPIC Configuration
2043 -------------------------------------------------------------------------- */
2044
888ba6c6 2045#ifdef CONFIG_ACPI
1da177e4
LT		 2046
2047#define IO_APIC_MAX_ID 0xFE
2048
1da177e4
LT		 2049int __init io_apic_get_redir_entries (int ioapic)
2050{
2051 union IO_APIC_reg_01 reg_01;
2052 unsigned long flags;
2053
2054 spin_lock_irqsave(&ioapic_lock, flags);
2055 reg_01.raw = io_apic_read(ioapic, 1);
2056 spin_unlock_irqrestore(&ioapic_lock, flags);
2057
2058 return reg_01.bits.entries;
2059}
2060
2061
50eca3eb 2062int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1da177e4
LT		 2063{
2064 struct IO_APIC_route_entry entry;
2065 unsigned long flags;
550f2299
EB		 2066 int vector;
2067 cpumask_t mask;
1da177e4
LT		 2068
2069 if (!IO_APIC_IRQ(irq)) {
2070 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2071 ioapic);
2072 return -EINVAL;
2073 }
2074
550f2299
EB		 2075 /*
2076 * IRQs < 16 are already in the irq_2_pin[] map
2077 */
2078 if (irq >= 16)
2079 add_pin_to_irq(irq, ioapic, pin);
2080
2081
c7111c13 2082 vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
550f2299
EB		 2083 if (vector < 0)
2084 return vector;
2085
1da177e4
LT		 2086 /*
2087 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2088 * Note that we mask (disable) IRQs now -- these get enabled when the
2089 * corresponding device driver registers for this IRQ.
2090 */
2091
2092 memset(&entry,0,sizeof(entry));
2093
2094 entry.delivery_mode = INT_DELIVERY_MODE;
2095 entry.dest_mode = INT_DEST_MODE;
550f2299 2096 entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
50eca3eb
BM		 2097 entry.trigger = triggering;
2098 entry.polarity = polarity;
1da177e4 2099 entry.mask = 1; /* Disabled (masked) */
550f2299 2100 entry.vector = vector & 0xff;
1da177e4
LT		 2101
2102 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2103 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2104 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
50eca3eb 2105 triggering, polarity);
1da177e4 2106
50eca3eb 2107 ioapic_register_intr(irq, entry.vector, triggering);
1da177e4
LT		 2108
2109 if (!ioapic && (irq < 16))
2110 disable_8259A_irq(irq);
2111
eea0e11c
AK		 2112 ioapic_write_entry(ioapic, pin, entry);
2113
1da177e4 2114 spin_lock_irqsave(&ioapic_lock, flags);
04b9267b 2115 set_native_irq_info(irq, TARGET_CPUS);
1da177e4
LT		 2116 spin_unlock_irqrestore(&ioapic_lock, flags);
2117
2118 return 0;
2119}
2120
888ba6c6 2121#endif /* CONFIG_ACPI */
1da177e4
LT		 2122
2123
2124/*
2125 * This function currently is only a helper for the i386 smp boot process where
2126 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2127 * so mask in all cases should simply be TARGET_CPUS
2128 */
54d5d424 2129#ifdef CONFIG_SMP
1da177e4
LT		 2130void __init setup_ioapic_dest(void)
2131{
2132 int pin, ioapic, irq, irq_entry;
2133
2134 if (skip_ioapic_setup == 1)
2135 return;
2136
2137 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2138 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2139 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2140 if (irq_entry == -1)
2141 continue;
2142 irq = pin_2_irq(irq_entry, ioapic, pin);
2143 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2144 }
2145
2146 }
2147}
54d5d424 2148#endif
Linux kernel - Deliverables
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