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ACPI: boot correctly with "nosmp" or "maxcpus=0"
[deliverable/linux.git] / arch / x86_64 / kernel / io_apic.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
1da177e4
LT		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
589e367f 28#include <linux/pci.h>
1da177e4
LT		 29#include <linux/mc146818rtc.h>
30#include <linux/acpi.h>
31#include <linux/sysdev.h>
3b7d1921 32#include <linux/msi.h>
95d77884 33#include <linux/htirq.h>
ab688059
AK		 34#ifdef CONFIG_ACPI
35#include <acpi/acpi_bus.h>
36#endif
1da177e4 37
61014292 38#include <asm/idle.h>
1da177e4
LT		 39#include <asm/io.h>
40#include <asm/smp.h>
41#include <asm/desc.h>
42#include <asm/proto.h>
43#include <asm/mach_apic.h>
8d916406 44#include <asm/acpi.h>
ca8642f6 45#include <asm/dma.h>
3e4ff115 46#include <asm/nmi.h>
589e367f 47#include <asm/msidef.h>
8b955b0d 48#include <asm/hypertransport.h>
1da177e4 49
13a79503
EB		 50struct irq_cfg {
51 cpumask_t domain;
61014292
EB		 52 cpumask_t old_domain;
53 unsigned move_cleanup_count;
13a79503 54 u8 vector;
61014292 55 u8 move_in_progress : 1;
13a79503
EB		 56};
57
58/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
59struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
bc5e81a1
EB		 60 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
61 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
62 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
63 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
64 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
65 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
66 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
67 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
68 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
69 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
70 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
71 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
72 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
73 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
74 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
75 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
13a79503
EB		 76};
77
dfbffdd8 78static int assign_irq_vector(int irq, cpumask_t mask);
04b9267b 79
1da177e4
LT		 80#define __apicdebuginit __init
81
82int sis_apic_bug; /* not actually supported, dummy for compile */
83
14d98cad
AK		 84static int no_timer_check;
85
fea5f1e1
LT		 86static int disable_timer_pin_1 __initdata;
87
88int timer_over_8254 __initdata = 1;
89
1008fddc
EB		 90/* Where if anywhere is the i8259 connect in external int mode */
91static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
92
1da177e4 93static DEFINE_SPINLOCK(ioapic_lock);
70a0a535 94DEFINE_SPINLOCK(vector_lock);
1da177e4
LT		 95
96/*
97 * # of IRQ routing registers
98 */
99int nr_ioapic_registers[MAX_IO_APICS];
100
101/*
102 * Rough estimation of how many shared IRQs there are, can
103 * be changed anytime.
104 */
e273d140 105#define MAX_PLUS_SHARED_IRQS NR_IRQS
1da177e4
LT		 106#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
107
108/*
109 * This is performance-critical, we want to do it O(1)
110 *
111 * the indexing order of this array favors 1:1 mappings
112 * between pins and IRQs.
113 */
114
115static struct irq_pin_list {
116 short apic, pin, next;
117} irq_2_pin[PIN_MAP_SIZE];
118
6c0ffb9d
LT		 119struct io_apic {
120 unsigned int index;
121 unsigned int unused[3];
122 unsigned int data;
123};
124
125static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
126{
127 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
128 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
129}
130
131static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
132{
133 struct io_apic __iomem *io_apic = io_apic_base(apic);
134 writel(reg, &io_apic->index);
135 return readl(&io_apic->data);
136}
137
138static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
139{
140 struct io_apic __iomem *io_apic = io_apic_base(apic);
141 writel(reg, &io_apic->index);
142 writel(value, &io_apic->data);
143}
144
145/*
146 * Re-write a value: to be used for read-modify-write
147 * cycles where the read already set up the index register.
148 */
149static inline void io_apic_modify(unsigned int apic, unsigned int value)
150{
151 struct io_apic __iomem *io_apic = io_apic_base(apic);
152 writel(value, &io_apic->data);
153}
154
ef3e28c5
EB		 155static int io_apic_level_ack_pending(unsigned int irq)
156{
157 struct irq_pin_list *entry;
158 unsigned long flags;
159 int pending = 0;
160
161 spin_lock_irqsave(&ioapic_lock, flags);
162 entry = irq_2_pin + irq;
163 for (;;) {
164 unsigned int reg;
165 int pin;
166
167 pin = entry->pin;
168 if (pin == -1)
169 break;
170 reg = io_apic_read(entry->apic, 0x10 + pin*2);
171 /* Is the remote IRR bit set? */
172 pending |= (reg >> 14) & 1;
173 if (!entry->next)
174 break;
175 entry = irq_2_pin + entry->next;
176 }
177 spin_unlock_irqrestore(&ioapic_lock, flags);
178 return pending;
179}
180
6c0ffb9d
LT		 181/*
182 * Synchronize the IO-APIC and the CPU by doing
183 * a dummy read from the IO-APIC
184 */
185static inline void io_apic_sync(unsigned int apic)
186{
187 struct io_apic __iomem *io_apic = io_apic_base(apic);
188 readl(&io_apic->data);
189}
190
54d5d424
AR		 191#define __DO_ACTION(R, ACTION, FINAL) \
192 \
193{ \
194 int pin; \
195 struct irq_pin_list *entry = irq_2_pin + irq; \
196 \
6004e1b7 197 BUG_ON(irq >= NR_IRQS); \
54d5d424
AR		 198 for (;;) { \
199 unsigned int reg; \
200 pin = entry->pin; \
201 if (pin == -1) \
202 break; \
203 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
204 reg ACTION; \
205 io_apic_modify(entry->apic, reg); \
f45bcd70 206 FINAL; \
54d5d424
AR		 207 if (!entry->next) \
208 break; \
209 entry = irq_2_pin + entry->next; \
210 } \
54d5d424
AR		 211}
212
eea0e11c
AK		 213union entry_union {
214 struct { u32 w1, w2; };
215 struct IO_APIC_route_entry entry;
216};
217
218static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
219{
220 union entry_union eu;
221 unsigned long flags;
222 spin_lock_irqsave(&ioapic_lock, flags);
223 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
224 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
225 spin_unlock_irqrestore(&ioapic_lock, flags);
226 return eu.entry;
227}
228
48797ebd
LT		 229/*
230 * When we write a new IO APIC routing entry, we need to write the high
231 * word first! If the mask bit in the low word is clear, we will enable
232 * the interrupt, and we need to make sure the entry is fully populated
233 * before that happens.
234 */
516d2836
AK		 235static void
236__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
eea0e11c 237{
eea0e11c
AK		 238 union entry_union eu;
239 eu.entry = e;
48797ebd
LT		 240 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
241 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
516d2836
AK		 242}
243
244static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
245{
246 unsigned long flags;
247 spin_lock_irqsave(&ioapic_lock, flags);
248 __ioapic_write_entry(apic, pin, e);
48797ebd
LT		 249 spin_unlock_irqrestore(&ioapic_lock, flags);
250}
251
252/*
253 * When we mask an IO APIC routing entry, we need to write the low
254 * word first, in order to set the mask bit before we change the
255 * high bits!
256 */
257static void ioapic_mask_entry(int apic, int pin)
258{
259 unsigned long flags;
260 union entry_union eu = { .entry.mask = 1 };
261
eea0e11c
AK		 262 spin_lock_irqsave(&ioapic_lock, flags);
263 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
264 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
265 spin_unlock_irqrestore(&ioapic_lock, flags);
266}
267
54d5d424 268#ifdef CONFIG_SMP
550f2299
EB		 269static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
270{
271 int apic, pin;
272 struct irq_pin_list *entry = irq_2_pin + irq;
273
274 BUG_ON(irq >= NR_IRQS);
275 for (;;) {
276 unsigned int reg;
277 apic = entry->apic;
278 pin = entry->pin;
279 if (pin == -1)
280 break;
281 io_apic_write(apic, 0x11 + pin*2, dest);
282 reg = io_apic_read(apic, 0x10 + pin*2);
283 reg &= ~0x000000ff;
284 reg |= vector;
285 io_apic_modify(apic, reg);
286 if (!entry->next)
287 break;
288 entry = irq_2_pin + entry->next;
289 }
290}
291
54d5d424
AR		 292static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
293{
dfbffdd8 294 struct irq_cfg *cfg = irq_cfg + irq;
54d5d424
AR		 295 unsigned long flags;
296 unsigned int dest;
297 cpumask_t tmp;
298
299 cpus_and(tmp, mask, cpu_online_map);
300 if (cpus_empty(tmp))
5ff5115e 301 return;
54d5d424 302
dfbffdd8 303 if (assign_irq_vector(irq, mask))
550f2299
EB		 304 return;
305
dfbffdd8 306 cpus_and(tmp, cfg->domain, mask);
550f2299 307 dest = cpu_mask_to_apicid(tmp);
54d5d424
AR		 308
309 /*
310 * Only the high 8 bits are valid.
311 */
312 dest = SET_APIC_LOGICAL_ID(dest);
313
314 spin_lock_irqsave(&ioapic_lock, flags);
dfbffdd8 315 __target_IO_APIC_irq(irq, dest, cfg->vector);
9f0a5ba5 316 irq_desc[irq].affinity = mask;
54d5d424
AR		 317 spin_unlock_irqrestore(&ioapic_lock, flags);
318}
319#endif
320
1da177e4
LT		 321/*
322 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
323 * shared ISA-space IRQs, so we have to support them. We are super
324 * fast in the common case, and fast for shared ISA-space IRQs.
325 */
326static void add_pin_to_irq(unsigned int irq, int apic, int pin)
327{
328 static int first_free_entry = NR_IRQS;
329 struct irq_pin_list *entry = irq_2_pin + irq;
330
6004e1b7 331 BUG_ON(irq >= NR_IRQS);
1da177e4
LT		 332 while (entry->next)
333 entry = irq_2_pin + entry->next;
334
335 if (entry->pin != -1) {
336 entry->next = first_free_entry;
337 entry = irq_2_pin + entry->next;
338 if (++first_free_entry >= PIN_MAP_SIZE)
6004e1b7 339 panic("io_apic.c: ran out of irq_2_pin entries!");
1da177e4
LT		 340 }
341 entry->apic = apic;
342 entry->pin = pin;
343}
344
1da177e4
LT		 345
346#define DO_ACTION(name,R,ACTION, FINAL) \
347 \
348 static void name##_IO_APIC_irq (unsigned int irq) \
349 __DO_ACTION(R, ACTION, FINAL)
350
351DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
352 /* mask = 1 */
353DO_ACTION( __unmask, 0, &= 0xfffeffff, )
354 /* mask = 0 */
355
356static void mask_IO_APIC_irq (unsigned int irq)
357{
358 unsigned long flags;
359
360 spin_lock_irqsave(&ioapic_lock, flags);
361 __mask_IO_APIC_irq(irq);
362 spin_unlock_irqrestore(&ioapic_lock, flags);
363}
364
365static void unmask_IO_APIC_irq (unsigned int irq)
366{
367 unsigned long flags;
368
369 spin_lock_irqsave(&ioapic_lock, flags);
370 __unmask_IO_APIC_irq(irq);
371 spin_unlock_irqrestore(&ioapic_lock, flags);
372}
373
374static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
375{
376 struct IO_APIC_route_entry entry;
1da177e4
LT		 377
378 /* Check delivery_mode to be sure we're not clearing an SMI pin */
eea0e11c 379 entry = ioapic_read_entry(apic, pin);
1da177e4
LT		 380 if (entry.delivery_mode == dest_SMI)
381 return;
382 /*
383 * Disable it in the IO-APIC irq-routing table:
384 */
48797ebd 385 ioapic_mask_entry(apic, pin);
1da177e4
LT		 386}
387
388static void clear_IO_APIC (void)
389{
390 int apic, pin;
391
392 for (apic = 0; apic < nr_ioapics; apic++)
393 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
394 clear_IO_APIC_pin(apic, pin);
395}
396
1da177e4
LT		 397int skip_ioapic_setup;
398int ioapic_force;
399
61ec7567 400static int __init parse_noapic(char *str)
1da177e4 401{
61ec7567 402 disable_ioapic_setup();
2c8c0e6b 403 return 0;
1da177e4 404}
61ec7567 405early_param("noapic", parse_noapic);
1da177e4 406
fea5f1e1
LT		 407/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
408static int __init disable_timer_pin_setup(char *arg)
409{
410 disable_timer_pin_1 = 1;
411 return 1;
412}
413__setup("disable_timer_pin_1", disable_timer_pin_setup);
414
415static int __init setup_disable_8254_timer(char *s)
416{
417 timer_over_8254 = -1;
418 return 1;
419}
420static int __init setup_enable_8254_timer(char *s)
421{
422 timer_over_8254 = 2;
423 return 1;
424}
425
426__setup("disable_8254_timer", setup_disable_8254_timer);
427__setup("enable_8254_timer", setup_enable_8254_timer);
428
429
1da177e4
LT		 430/*
431 * Find the IRQ entry number of a certain pin.
432 */
433static int find_irq_entry(int apic, int pin, int type)
434{
435 int i;
436
437 for (i = 0; i < mp_irq_entries; i++)
438 if (mp_irqs[i].mpc_irqtype == type &&
439 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
440 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
441 mp_irqs[i].mpc_dstirq == pin)
442 return i;
443
444 return -1;
445}
446
447/*
448 * Find the pin to which IRQ[irq] (ISA) is connected
449 */
1008fddc 450static int __init find_isa_irq_pin(int irq, int type)
1da177e4
LT		 451{
452 int i;
453
454 for (i = 0; i < mp_irq_entries; i++) {
455 int lbus = mp_irqs[i].mpc_srcbus;
456
55f05ffa 457 if (test_bit(lbus, mp_bus_not_pci) &&
1da177e4
LT		 458 (mp_irqs[i].mpc_irqtype == type) &&
459 (mp_irqs[i].mpc_srcbusirq == irq))
460
461 return mp_irqs[i].mpc_dstirq;
462 }
463 return -1;
464}
465
1008fddc
EB		 466static int __init find_isa_irq_apic(int irq, int type)
467{
468 int i;
469
470 for (i = 0; i < mp_irq_entries; i++) {
471 int lbus = mp_irqs[i].mpc_srcbus;
472
55f05ffa 473 if (test_bit(lbus, mp_bus_not_pci) &&
1008fddc
EB		 474 (mp_irqs[i].mpc_irqtype == type) &&
475 (mp_irqs[i].mpc_srcbusirq == irq))
476 break;
477 }
478 if (i < mp_irq_entries) {
479 int apic;
480 for(apic = 0; apic < nr_ioapics; apic++) {
481 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
482 return apic;
483 }
484 }
485
486 return -1;
487}
488
1da177e4
LT		 489/*
490 * Find a specific PCI IRQ entry.
491 * Not an __init, possibly needed by modules
492 */
493static int pin_2_irq(int idx, int apic, int pin);
494
495int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
496{
497 int apic, i, best_guess = -1;
498
499 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
500 bus, slot, pin);
501 if (mp_bus_id_to_pci_bus[bus] == -1) {
502 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
503 return -1;
504 }
505 for (i = 0; i < mp_irq_entries; i++) {
506 int lbus = mp_irqs[i].mpc_srcbus;
507
508 for (apic = 0; apic < nr_ioapics; apic++)
509 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
510 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
511 break;
512
55f05ffa 513 if (!test_bit(lbus, mp_bus_not_pci) &&
1da177e4
LT		 514 !mp_irqs[i].mpc_irqtype &&
515 (bus == lbus) &&
516 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
517 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
518
519 if (!(apic || IO_APIC_IRQ(irq)))
520 continue;
521
522 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
523 return irq;
524 /*
525 * Use the first all-but-pin matching entry as a
526 * best-guess fuzzy result for broken mptables.
527 */
528 if (best_guess < 0)
529 best_guess = irq;
530 }
531 }
6004e1b7 532 BUG_ON(best_guess >= NR_IRQS);
1da177e4
LT		 533 return best_guess;
534}
535
1da177e4
LT		 536/* ISA interrupts are always polarity zero edge triggered,
537 * when listed as conforming in the MP table. */
538
539#define default_ISA_trigger(idx) (0)
540#define default_ISA_polarity(idx) (0)
541
542/* PCI interrupts are always polarity one level triggered,
543 * when listed as conforming in the MP table. */
544
545#define default_PCI_trigger(idx) (1)
546#define default_PCI_polarity(idx) (1)
547
1da177e4
LT		 548static int __init MPBIOS_polarity(int idx)
549{
550 int bus = mp_irqs[idx].mpc_srcbus;
551 int polarity;
552
553 /*
554 * Determine IRQ line polarity (high active or low active):
555 */
556 switch (mp_irqs[idx].mpc_irqflag & 3)
557 {
558 case 0: /* conforms, ie. bus-type dependent polarity */
55f05ffa
AK		 559 if (test_bit(bus, mp_bus_not_pci))
560 polarity = default_ISA_polarity(idx);
561 else
562 polarity = default_PCI_polarity(idx);
1da177e4 563 break;
1da177e4
LT		 564 case 1: /* high active */
565 {
566 polarity = 0;
567 break;
568 }
569 case 2: /* reserved */
570 {
571 printk(KERN_WARNING "broken BIOS!!\n");
572 polarity = 1;
573 break;
574 }
575 case 3: /* low active */
576 {
577 polarity = 1;
578 break;
579 }
580 default: /* invalid */
581 {
582 printk(KERN_WARNING "broken BIOS!!\n");
583 polarity = 1;
584 break;
585 }
586 }
587 return polarity;
588}
589
590static int MPBIOS_trigger(int idx)
591{
592 int bus = mp_irqs[idx].mpc_srcbus;
593 int trigger;
594
595 /*
596 * Determine IRQ trigger mode (edge or level sensitive):
597 */
598 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
599 {
600 case 0: /* conforms, ie. bus-type dependent */
55f05ffa
AK		 601 if (test_bit(bus, mp_bus_not_pci))
602 trigger = default_ISA_trigger(idx);
603 else
604 trigger = default_PCI_trigger(idx);
1da177e4 605 break;
1da177e4
LT		 606 case 1: /* edge */
607 {
608 trigger = 0;
609 break;
610 }
611 case 2: /* reserved */
612 {
613 printk(KERN_WARNING "broken BIOS!!\n");
614 trigger = 1;
615 break;
616 }
617 case 3: /* level */
618 {
619 trigger = 1;
620 break;
621 }
622 default: /* invalid */
623 {
624 printk(KERN_WARNING "broken BIOS!!\n");
625 trigger = 0;
626 break;
627 }
628 }
629 return trigger;
630}
631
632static inline int irq_polarity(int idx)
633{
634 return MPBIOS_polarity(idx);
635}
636
637static inline int irq_trigger(int idx)
638{
639 return MPBIOS_trigger(idx);
640}
641
642static int pin_2_irq(int idx, int apic, int pin)
643{
644 int irq, i;
645 int bus = mp_irqs[idx].mpc_srcbus;
646
647 /*
648 * Debugging check, we are in big trouble if this message pops up!
649 */
650 if (mp_irqs[idx].mpc_dstirq != pin)
651 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
652
55f05ffa
AK		 653 if (test_bit(bus, mp_bus_not_pci)) {
654 irq = mp_irqs[idx].mpc_srcbusirq;
655 } else {
656 /*
657 * PCI IRQs are mapped in order
658 */
659 i = irq = 0;
660 while (i < apic)
661 irq += nr_ioapic_registers[i++];
662 irq += pin;
1da177e4 663 }
6004e1b7 664 BUG_ON(irq >= NR_IRQS);
1da177e4
LT		 665 return irq;
666}
667
dfbffdd8 668static int __assign_irq_vector(int irq, cpumask_t mask)
1da177e4 669{
550f2299
EB		 670 /*
671 * NOTE! The local APIC isn't very good at handling
672 * multiple interrupts at the same interrupt level.
673 * As the interrupt level is determined by taking the
674 * vector number and shifting that right by 4, we
675 * want to spread these out a bit so that they don't
676 * all fall in the same interrupt level.
677 *
678 * Also, we've got to be careful not to trash gate
679 * 0x80, because int 0x80 is hm, kind of importantish. ;)
680 */
d1752aa8 681 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
dfbffdd8 682 unsigned int old_vector;
550f2299 683 int cpu;
13a79503 684 struct irq_cfg *cfg;
1da177e4 685
e273d140 686 BUG_ON((unsigned)irq >= NR_IRQS);
13a79503 687 cfg = &irq_cfg[irq];
0a1ad60d 688
70a0a535
EB		 689 /* Only try and allocate irqs on cpus that are present */
690 cpus_and(mask, mask, cpu_online_map);
691
61014292
EB		 692 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
693 return -EBUSY;
694
dfbffdd8
EB		 695 old_vector = cfg->vector;
696 if (old_vector) {
697 cpumask_t tmp;
698 cpus_and(tmp, cfg->domain, mask);
699 if (!cpus_empty(tmp))
700 return 0;
0a1ad60d 701 }
550f2299
EB		 702
703 for_each_cpu_mask(cpu, mask) {
70a0a535 704 cpumask_t domain, new_mask;
61014292 705 int new_cpu;
550f2299 706 int vector, offset;
c7111c13
EB		 707
708 domain = vector_allocation_domain(cpu);
70a0a535 709 cpus_and(new_mask, domain, cpu_online_map);
c7111c13 710
d1752aa8
EB		 711 vector = current_vector;
712 offset = current_offset;
1da177e4 713next:
550f2299
EB		 714 vector += 8;
715 if (vector >= FIRST_SYSTEM_VECTOR) {
716 /* If we run out of vectors on large boxen, must share them. */
717 offset = (offset + 1) % 8;
718 vector = FIRST_DEVICE_VECTOR + offset;
719 }
d1752aa8 720 if (unlikely(current_vector == vector))
550f2299
EB		 721 continue;
722 if (vector == IA32_SYSCALL_VECTOR)
723 goto next;
70a0a535 724 for_each_cpu_mask(new_cpu, new_mask)
45edfd1d 725 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
c7111c13 726 goto next;
550f2299 727 /* Found one! */
d1752aa8
EB		 728 current_vector = vector;
729 current_offset = offset;
61014292
EB		 730 if (old_vector) {
731 cfg->move_in_progress = 1;
732 cfg->old_domain = cfg->domain;
733 }
70a0a535 734 for_each_cpu_mask(new_cpu, new_mask)
c7111c13 735 per_cpu(vector_irq, new_cpu)[vector] = irq;
13a79503
EB		 736 cfg->vector = vector;
737 cfg->domain = domain;
dfbffdd8 738 return 0;
1da177e4 739 }
550f2299 740 return -ENOSPC;
04b9267b
EB		 741}
742
dfbffdd8 743static int assign_irq_vector(int irq, cpumask_t mask)
04b9267b 744{
dfbffdd8 745 int err;
04b9267b 746 unsigned long flags;
0a1ad60d 747
04b9267b 748 spin_lock_irqsave(&vector_lock, flags);
dfbffdd8 749 err = __assign_irq_vector(irq, mask);
26a3c49c 750 spin_unlock_irqrestore(&vector_lock, flags);
dfbffdd8 751 return err;
1da177e4
LT		 752}
753
5df0287e
YL		 754static void __clear_irq_vector(int irq)
755{
13a79503 756 struct irq_cfg *cfg;
5df0287e
YL		 757 cpumask_t mask;
758 int cpu, vector;
759
13a79503
EB		 760 BUG_ON((unsigned)irq >= NR_IRQS);
761 cfg = &irq_cfg[irq];
762 BUG_ON(!cfg->vector);
5df0287e 763
13a79503
EB		 764 vector = cfg->vector;
765 cpus_and(mask, cfg->domain, cpu_online_map);
5df0287e
YL		 766 for_each_cpu_mask(cpu, mask)
767 per_cpu(vector_irq, cpu)[vector] = -1;
768
13a79503
EB		 769 cfg->vector = 0;
770 cfg->domain = CPU_MASK_NONE;
5df0287e
YL		 771}
772
70a0a535
EB		 773void __setup_vector_irq(int cpu)
774{
775 /* Initialize vector_irq on a new cpu */
776 /* This function must be called with vector_lock held */
70a0a535
EB		 777 int irq, vector;
778
70a0a535 779 /* Mark the inuse vectors */
e273d140 780 for (irq = 0; irq < NR_IRQS; ++irq) {
13a79503 781 if (!cpu_isset(cpu, irq_cfg[irq].domain))
70a0a535 782 continue;
13a79503 783 vector = irq_cfg[irq].vector;
70a0a535
EB		 784 per_cpu(vector_irq, cpu)[vector] = irq;
785 }
786 /* Mark the free vectors */
787 for (vector = 0; vector < NR_VECTORS; ++vector) {
788 irq = per_cpu(vector_irq, cpu)[vector];
789 if (irq < 0)
790 continue;
13a79503 791 if (!cpu_isset(cpu, irq_cfg[irq].domain))
70a0a535
EB		 792 per_cpu(vector_irq, cpu)[vector] = -1;
793 }
794}
795
796
f29bd1ba 797static struct irq_chip ioapic_chip;
1da177e4 798
a27bc06d 799static void ioapic_register_intr(int irq, unsigned long trigger)
1da177e4 800{
cc75b92d
TG		 801 if (trigger) {
802 irq_desc[irq].status |= IRQ_LEVEL;
a460e745
IM		 803 set_irq_chip_and_handler_name(irq, &ioapic_chip,
804 handle_fasteoi_irq, "fasteoi");
cc75b92d
TG		 805 } else {
806 irq_desc[irq].status &= ~IRQ_LEVEL;
a460e745
IM		 807 set_irq_chip_and_handler_name(irq, &ioapic_chip,
808 handle_edge_irq, "edge");
cc75b92d 809 }
1da177e4 810}
a8c8a367
EB		 811
812static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
813 int trigger, int polarity)
1da177e4 814{
dfbffdd8 815 struct irq_cfg *cfg = irq_cfg + irq;
1da177e4 816 struct IO_APIC_route_entry entry;
a8c8a367 817 cpumask_t mask;
1da177e4 818
a8c8a367
EB		 819 if (!IO_APIC_IRQ(irq))
820 return;
821
dfbffdd8
EB		 822 mask = TARGET_CPUS;
823 if (assign_irq_vector(irq, mask))
a8c8a367
EB		 824 return;
825
dfbffdd8
EB		 826 cpus_and(mask, cfg->domain, mask);
827
a8c8a367
EB		 828 apic_printk(APIC_VERBOSE,KERN_DEBUG
829 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
830 "IRQ %d Mode:%i Active:%i)\n",
dfbffdd8 831 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
a8c8a367 832 irq, trigger, polarity);
1da177e4 833
ad892f5e
YL		 834 /*
835 * add it to the IO-APIC irq-routing table:
836 */
837 memset(&entry,0,sizeof(entry));
1da177e4 838
ad892f5e
YL		 839 entry.delivery_mode = INT_DELIVERY_MODE;
840 entry.dest_mode = INT_DEST_MODE;
a8c8a367 841 entry.dest = cpu_mask_to_apicid(mask);
ad892f5e 842 entry.mask = 0; /* enable IRQ */
a8c8a367
EB		 843 entry.trigger = trigger;
844 entry.polarity = polarity;
dfbffdd8 845 entry.vector = cfg->vector;
1da177e4 846
a8c8a367
EB		 847 /* Mask level triggered irqs.
848 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
849 */
850 if (trigger)
ad892f5e 851 entry.mask = 1;
ad892f5e 852
a8c8a367
EB		 853 ioapic_register_intr(irq, trigger);
854 if (irq < 16)
855 disable_8259A_irq(irq);
ad892f5e
YL		 856
857 ioapic_write_entry(apic, pin, entry);
ad892f5e
YL		 858}
859
860static void __init setup_IO_APIC_irqs(void)
861{
862 int apic, pin, idx, irq, first_notcon = 1;
863
864 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
865
866 for (apic = 0; apic < nr_ioapics; apic++) {
867 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1da177e4
LT		 868
869 idx = find_irq_entry(apic,pin,mp_INT);
870 if (idx == -1) {
871 if (first_notcon) {
872 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
873 first_notcon = 0;
874 } else
875 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
876 continue;
877 }
878
1da177e4
LT		 879 irq = pin_2_irq(idx, apic, pin);
880 add_pin_to_irq(irq, apic, pin);
881
a8c8a367
EB		 882 setup_IO_APIC_irq(apic, pin, irq,
883 irq_trigger(idx), irq_polarity(idx));
1da177e4
LT		 884 }
885 }
886
887 if (!first_notcon)
888 apic_printk(APIC_VERBOSE," not connected.\n");
889}
890
891/*
892 * Set up the 8259A-master output pin as broadcast to all
893 * CPUs.
894 */
1008fddc 895static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1da177e4
LT		 896{
897 struct IO_APIC_route_entry entry;
898 unsigned long flags;
899
900 memset(&entry,0,sizeof(entry));
901
902 disable_8259A_irq(0);
903
904 /* mask LVT0 */
11a8e778 905 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4
LT		 906
907 /*
908 * We use logical delivery to get the timer IRQ
909 * to the first CPU.
910 */
911 entry.dest_mode = INT_DEST_MODE;
912 entry.mask = 0; /* unmask IRQ now */
ee4eff6f 913 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1da177e4
LT		 914 entry.delivery_mode = INT_DELIVERY_MODE;
915 entry.polarity = 0;
916 entry.trigger = 0;
917 entry.vector = vector;
918
919 /*
920 * The timer IRQ doesn't have to know that behind the
921 * scene we have a 8259A-master in AEOI mode ...
922 */
a460e745 923 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1da177e4
LT		 924
925 /*
926 * Add it to the IO-APIC irq-routing table:
927 */
928 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 929 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
930 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1da177e4
LT		 931 spin_unlock_irqrestore(&ioapic_lock, flags);
932
933 enable_8259A_irq(0);
934}
935
1da177e4
LT		 936void __apicdebuginit print_IO_APIC(void)
937{
938 int apic, i;
939 union IO_APIC_reg_00 reg_00;
940 union IO_APIC_reg_01 reg_01;
941 union IO_APIC_reg_02 reg_02;
942 unsigned long flags;
943
944 if (apic_verbosity == APIC_QUIET)
945 return;
946
947 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
948 for (i = 0; i < nr_ioapics; i++)
949 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
950 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
951
952 /*
953 * We are a bit conservative about what we expect. We have to
954 * know about every hardware change ASAP.
955 */
956 printk(KERN_INFO "testing the IO APIC.......................\n");
957
958 for (apic = 0; apic < nr_ioapics; apic++) {
959
960 spin_lock_irqsave(&ioapic_lock, flags);
961 reg_00.raw = io_apic_read(apic, 0);
962 reg_01.raw = io_apic_read(apic, 1);
963 if (reg_01.bits.version >= 0x10)
964 reg_02.raw = io_apic_read(apic, 2);
965 spin_unlock_irqrestore(&ioapic_lock, flags);
966
967 printk("\n");
968 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
969 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
970 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1da177e4
LT		 971
972 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
973 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1da177e4
LT		 974
975 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
976 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1da177e4
LT		 977
978 if (reg_01.bits.version >= 0x10) {
979 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
980 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1da177e4
LT		 981 }
982
983 printk(KERN_DEBUG ".... IRQ redirection table:\n");
984
ee4eff6f
BR		 985 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
986 " Stat Dmod Deli Vect: \n");
1da177e4
LT		 987
988 for (i = 0; i <= reg_01.bits.entries; i++) {
989 struct IO_APIC_route_entry entry;
990
eea0e11c 991 entry = ioapic_read_entry(apic, i);
1da177e4 992
ee4eff6f 993 printk(KERN_DEBUG " %02x %03X ",
1da177e4 994 i,
ee4eff6f 995 entry.dest
1da177e4
LT		 996 );
997
998 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
999 entry.mask,
1000 entry.trigger,
1001 entry.irr,
1002 entry.polarity,
1003 entry.delivery_status,
1004 entry.dest_mode,
1005 entry.delivery_mode,
1006 entry.vector
1007 );
1008 }
1009 }
1da177e4
LT		 1010 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1011 for (i = 0; i < NR_IRQS; i++) {
1012 struct irq_pin_list *entry = irq_2_pin + i;
1013 if (entry->pin < 0)
1014 continue;
04b9267b 1015 printk(KERN_DEBUG "IRQ%d ", i);
1da177e4
LT		 1016 for (;;) {
1017 printk("-> %d:%d", entry->apic, entry->pin);
1018 if (!entry->next)
1019 break;
1020 entry = irq_2_pin + entry->next;
1021 }
1022 printk("\n");
1023 }
1024
1025 printk(KERN_INFO ".................................... done.\n");
1026
1027 return;
1028}
1029
1030#if 0
1031
1032static __apicdebuginit void print_APIC_bitfield (int base)
1033{
1034 unsigned int v;
1035 int i, j;
1036
1037 if (apic_verbosity == APIC_QUIET)
1038 return;
1039
1040 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1041 for (i = 0; i < 8; i++) {
1042 v = apic_read(base + i*0x10);
1043 for (j = 0; j < 32; j++) {
1044 if (v & (1<<j))
1045 printk("1");
1046 else
1047 printk("0");
1048 }
1049 printk("\n");
1050 }
1051}
1052
1053void __apicdebuginit print_local_APIC(void * dummy)
1054{
1055 unsigned int v, ver, maxlvt;
1056
1057 if (apic_verbosity == APIC_QUIET)
1058 return;
1059
1060 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1061 smp_processor_id(), hard_smp_processor_id());
1062 v = apic_read(APIC_ID);
1063 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1064 v = apic_read(APIC_LVR);
1065 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1066 ver = GET_APIC_VERSION(v);
1067 maxlvt = get_maxlvt();
1068
1069 v = apic_read(APIC_TASKPRI);
1070 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1071
5a40b7c2
AK		 1072 v = apic_read(APIC_ARBPRI);
1073 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1074 v & APIC_ARBPRI_MASK);
1075 v = apic_read(APIC_PROCPRI);
1076 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1da177e4
LT		 1077
1078 v = apic_read(APIC_EOI);
1079 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1080 v = apic_read(APIC_RRR);
1081 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1082 v = apic_read(APIC_LDR);
1083 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1084 v = apic_read(APIC_DFR);
1085 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1086 v = apic_read(APIC_SPIV);
1087 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1088
1089 printk(KERN_DEBUG "... APIC ISR field:\n");
1090 print_APIC_bitfield(APIC_ISR);
1091 printk(KERN_DEBUG "... APIC TMR field:\n");
1092 print_APIC_bitfield(APIC_TMR);
1093 printk(KERN_DEBUG "... APIC IRR field:\n");
1094 print_APIC_bitfield(APIC_IRR);
1095
5a40b7c2
AK		 1096 v = apic_read(APIC_ESR);
1097 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1da177e4
LT		 1098
1099 v = apic_read(APIC_ICR);
1100 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1101 v = apic_read(APIC_ICR2);
1102 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1103
1104 v = apic_read(APIC_LVTT);
1105 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1106
1107 if (maxlvt > 3) { /* PC is LVT#4. */
1108 v = apic_read(APIC_LVTPC);
1109 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1110 }
1111 v = apic_read(APIC_LVT0);
1112 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1113 v = apic_read(APIC_LVT1);
1114 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1115
1116 if (maxlvt > 2) { /* ERR is LVT#3. */
1117 v = apic_read(APIC_LVTERR);
1118 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1119 }
1120
1121 v = apic_read(APIC_TMICT);
1122 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1123 v = apic_read(APIC_TMCCT);
1124 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1125 v = apic_read(APIC_TDCR);
1126 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1127 printk("\n");
1128}
1129
1130void print_all_local_APICs (void)
1131{
1132 on_each_cpu(print_local_APIC, NULL, 1, 1);
1133}
1134
1135void __apicdebuginit print_PIC(void)
1136{
1da177e4
LT		 1137 unsigned int v;
1138 unsigned long flags;
1139
1140 if (apic_verbosity == APIC_QUIET)
1141 return;
1142
1143 printk(KERN_DEBUG "\nprinting PIC contents\n");
1144
1145 spin_lock_irqsave(&i8259A_lock, flags);
1146
1147 v = inb(0xa1) << 8 | inb(0x21);
1148 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1149
1150 v = inb(0xa0) << 8 | inb(0x20);
1151 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1152
1153 outb(0x0b,0xa0);
1154 outb(0x0b,0x20);
1155 v = inb(0xa0) << 8 | inb(0x20);
1156 outb(0x0a,0xa0);
1157 outb(0x0a,0x20);
1158
1159 spin_unlock_irqrestore(&i8259A_lock, flags);
1160
1161 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1162
1163 v = inb(0x4d1) << 8 | inb(0x4d0);
1164 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1165}
1166
1167#endif /* 0 */
1168
1169static void __init enable_IO_APIC(void)
1170{
1171 union IO_APIC_reg_01 reg_01;
1008fddc
EB		 1172 int i8259_apic, i8259_pin;
1173 int i, apic;
1da177e4
LT		 1174 unsigned long flags;
1175
1176 for (i = 0; i < PIN_MAP_SIZE; i++) {
1177 irq_2_pin[i].pin = -1;
1178 irq_2_pin[i].next = 0;
1179 }
1da177e4
LT		 1180
1181 /*
1182 * The number of IO-APIC IRQ registers (== #pins):
1183 */
1008fddc 1184 for (apic = 0; apic < nr_ioapics; apic++) {
1da177e4 1185 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc 1186 reg_01.raw = io_apic_read(apic, 1);
1da177e4 1187 spin_unlock_irqrestore(&ioapic_lock, flags);
1008fddc
EB		 1188 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1189 }
1190 for(apic = 0; apic < nr_ioapics; apic++) {
1191 int pin;
1192 /* See if any of the pins is in ExtINT mode */
1193 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1194 struct IO_APIC_route_entry entry;
eea0e11c 1195 entry = ioapic_read_entry(apic, pin);
1008fddc
EB		 1196
1197 /* If the interrupt line is enabled and in ExtInt mode
1198 * I have found the pin where the i8259 is connected.
1199 */
1200 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1201 ioapic_i8259.apic = apic;
1202 ioapic_i8259.pin = pin;
1203 goto found_i8259;
1204 }
1205 }
1206 }
1207 found_i8259:
1208 /* Look to see what if the MP table has reported the ExtINT */
1209 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1210 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1211 /* Trust the MP table if nothing is setup in the hardware */
1212 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1213 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1214 ioapic_i8259.pin = i8259_pin;
1215 ioapic_i8259.apic = i8259_apic;
1216 }
1217 /* Complain if the MP table and the hardware disagree */
1218 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1219 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1220 {
1221 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1da177e4
LT		 1222 }
1223
1224 /*
1225 * Do not trust the IO-APIC being empty at bootup
1226 */
1227 clear_IO_APIC();
1228}
1229
1230/*
1231 * Not an __init, needed by the reboot code
1232 */
1233void disable_IO_APIC(void)
1234{
1235 /*
1236 * Clear the IO-APIC before rebooting:
1237 */
1238 clear_IO_APIC();
1239
208fb931 1240 /*
0b968d23 1241 * If the i8259 is routed through an IOAPIC
208fb931 1242 * Put that IOAPIC in virtual wire mode
0b968d23 1243 * so legacy interrupts can be delivered.
208fb931 1244 */
1008fddc 1245 if (ioapic_i8259.pin != -1) {
208fb931 1246 struct IO_APIC_route_entry entry;
208fb931
EB		 1247
1248 memset(&entry, 0, sizeof(entry));
1249 entry.mask = 0; /* Enabled */
1250 entry.trigger = 0; /* Edge */
1251 entry.irr = 0;
1252 entry.polarity = 0; /* High */
1253 entry.delivery_status = 0;
1254 entry.dest_mode = 0; /* Physical */
1008fddc 1255 entry.delivery_mode = dest_ExtINT; /* ExtInt */
208fb931 1256 entry.vector = 0;
ee4eff6f 1257 entry.dest = GET_APIC_ID(apic_read(APIC_ID));
208fb931 1258
208fb931
EB		 1259 /*
1260 * Add it to the IO-APIC irq-routing table:
1261 */
eea0e11c 1262 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
208fb931
EB		 1263 }
1264
1008fddc 1265 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1da177e4
LT		 1266}
1267
1da177e4
LT		 1268/*
1269 * There is a nasty bug in some older SMP boards, their mptable lies
1270 * about the timer IRQ. We do the following to work around the situation:
1271 *
1272 * - timer IRQ defaults to IO-APIC IRQ
1273 * - if this function detects that timer IRQs are defunct, then we fall
1274 * back to ISA timer IRQs
1275 */
1276static int __init timer_irq_works(void)
1277{
1278 unsigned long t1 = jiffies;
1279
1280 local_irq_enable();
1281 /* Let ten ticks pass... */
1282 mdelay((10 * 1000) / HZ);
1283
1284 /*
1285 * Expect a few ticks at least, to be sure some possible
1286 * glue logic does not lock up after one or two first
1287 * ticks in a non-ExtINT mode. Also the local APIC
1288 * might have cached one ExtINT interrupt. Finally, at
1289 * least one tick may be lost due to delays.
1290 */
1291
1292 /* jiffies wrap? */
1293 if (jiffies - t1 > 4)
1294 return 1;
1295 return 0;
1296}
1297
1298/*
1299 * In the SMP+IOAPIC case it might happen that there are an unspecified
1300 * number of pending IRQ events unhandled. These cases are very rare,
1301 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1302 * better to do it this way as thus we do not have to be aware of
1303 * 'pending' interrupts in the IRQ path, except at this point.
1304 */
1305/*
1306 * Edge triggered needs to resend any interrupt
1307 * that was delayed but this is now handled in the device
1308 * independent code.
1309 */
1310
1311/*
1312 * Starting up a edge-triggered IO-APIC interrupt is
1313 * nasty - we need to make sure that we get the edge.
1314 * If it is already asserted for some reason, we need
1315 * return 1 to indicate that is was pending.
1316 *
1317 * This is not complete - we should be able to fake
1318 * an edge even if it isn't on the 8259A...
1319 */
1320
f29bd1ba 1321static unsigned int startup_ioapic_irq(unsigned int irq)
1da177e4
LT		 1322{
1323 int was_pending = 0;
1324 unsigned long flags;
1325
1326 spin_lock_irqsave(&ioapic_lock, flags);
1327 if (irq < 16) {
1328 disable_8259A_irq(irq);
1329 if (i8259A_irq_pending(irq))
1330 was_pending = 1;
1331 }
1332 __unmask_IO_APIC_irq(irq);
1333 spin_unlock_irqrestore(&ioapic_lock, flags);
1334
1335 return was_pending;
1336}
1337
04b9267b 1338static int ioapic_retrigger_irq(unsigned int irq)
c0ad90a3 1339{
13a79503 1340 struct irq_cfg *cfg = &irq_cfg[irq];
550f2299 1341 cpumask_t mask;
6bf2dafa 1342 unsigned long flags;
550f2299 1343
6bf2dafa 1344 spin_lock_irqsave(&vector_lock, flags);
550f2299 1345 cpus_clear(mask);
13a79503 1346 cpu_set(first_cpu(cfg->domain), mask);
550f2299 1347
13a79503 1348 send_IPI_mask(mask, cfg->vector);
6bf2dafa 1349 spin_unlock_irqrestore(&vector_lock, flags);
c0ad90a3
IM		 1350
1351 return 1;
1352}
1353
1da177e4
LT		 1354/*
1355 * Level and edge triggered IO-APIC interrupts need different handling,
1356 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1357 * handled with the level-triggered descriptor, but that one has slightly
1358 * more overhead. Level-triggered interrupts cannot be handled with the
1359 * edge-triggered handler, without risking IRQ storms and other ugly
1360 * races.
1361 */
1362
61014292
EB		 1363#ifdef CONFIG_SMP
1364asmlinkage void smp_irq_move_cleanup_interrupt(void)
1365{
1366 unsigned vector, me;
1367 ack_APIC_irq();
1368 exit_idle();
1369 irq_enter();
1370
1371 me = smp_processor_id();
1372 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1373 unsigned int irq;
1374 struct irq_desc *desc;
1375 struct irq_cfg *cfg;
1376 irq = __get_cpu_var(vector_irq)[vector];
1377 if (irq >= NR_IRQS)
1378 continue;
1379
1380 desc = irq_desc + irq;
1381 cfg = irq_cfg + irq;
1382 spin_lock(&desc->lock);
1383 if (!cfg->move_cleanup_count)
1384 goto unlock;
1385
1386 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1387 goto unlock;
1388
1389 __get_cpu_var(vector_irq)[vector] = -1;
1390 cfg->move_cleanup_count--;
1391unlock:
1392 spin_unlock(&desc->lock);
1393 }
1394
1395 irq_exit();
1396}
1397
1398static void irq_complete_move(unsigned int irq)
1399{
1400 struct irq_cfg *cfg = irq_cfg + irq;
1401 unsigned vector, me;
1402
1403 if (likely(!cfg->move_in_progress))
1404 return;
1405
1406 vector = ~get_irq_regs()->orig_rax;
1407 me = smp_processor_id();
f0e13ae7 1408 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
61014292
EB		 1409 cpumask_t cleanup_mask;
1410
1411 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1412 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1413 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1414 cfg->move_in_progress = 0;
1415 }
1416}
1417#else
1418static inline void irq_complete_move(unsigned int irq) {}
1419#endif
1420
0be6652f
EB		 1421static void ack_apic_edge(unsigned int irq)
1422{
61014292 1423 irq_complete_move(irq);
0be6652f
EB		 1424 move_native_irq(irq);
1425 ack_APIC_irq();
1426}
1427
1428static void ack_apic_level(unsigned int irq)
1429{
1430 int do_unmask_irq = 0;
1431
61014292 1432 irq_complete_move(irq);
0be6652f
EB		 1433#if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1434 /* If we are moving the irq we need to mask it */
1435 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1436 do_unmask_irq = 1;
1437 mask_IO_APIC_irq(irq);
1438 }
1439#endif
1440
1441 /*
1442 * We must acknowledge the irq before we move it or the acknowledge will
beb7dd86 1443 * not propagate properly.
0be6652f
EB		 1444 */
1445 ack_APIC_irq();
1446
1447 /* Now we can move and renable the irq */
ef3e28c5
EB		 1448 if (unlikely(do_unmask_irq)) {
1449 /* Only migrate the irq if the ack has been received.
1450 *
1451 * On rare occasions the broadcast level triggered ack gets
1452 * delayed going to ioapics, and if we reprogram the
1453 * vector while Remote IRR is still set the irq will never
1454 * fire again.
1455 *
1456 * To prevent this scenario we read the Remote IRR bit
1457 * of the ioapic. This has two effects.
1458 * - On any sane system the read of the ioapic will
1459 * flush writes (and acks) going to the ioapic from
1460 * this cpu.
1461 * - We get to see if the ACK has actually been delivered.
1462 *
1463 * Based on failed experiments of reprogramming the
1464 * ioapic entry from outside of irq context starting
1465 * with masking the ioapic entry and then polling until
1466 * Remote IRR was clear before reprogramming the
1467 * ioapic I don't trust the Remote IRR bit to be
1468 * completey accurate.
1469 *
1470 * However there appears to be no other way to plug
1471 * this race, so if the Remote IRR bit is not
1472 * accurate and is causing problems then it is a hardware bug
1473 * and you can go talk to the chipset vendor about it.
1474 */
1475 if (!io_apic_level_ack_pending(irq))
1476 move_masked_irq(irq);
0be6652f 1477 unmask_IO_APIC_irq(irq);
ef3e28c5 1478 }
0be6652f
EB		 1479}
1480
f29bd1ba
IM		 1481static struct irq_chip ioapic_chip __read_mostly = {
1482 .name = "IO-APIC",
04b9267b
EB		 1483 .startup = startup_ioapic_irq,
1484 .mask = mask_IO_APIC_irq,
1485 .unmask = unmask_IO_APIC_irq,
0be6652f
EB		 1486 .ack = ack_apic_edge,
1487 .eoi = ack_apic_level,
54d5d424 1488#ifdef CONFIG_SMP
04b9267b 1489 .set_affinity = set_ioapic_affinity_irq,
54d5d424 1490#endif
04b9267b 1491 .retrigger = ioapic_retrigger_irq,
1da177e4
LT		 1492};
1493
1494static inline void init_IO_APIC_traps(void)
1495{
1496 int irq;
1497
1498 /*
1499 * NOTE! The local APIC isn't very good at handling
1500 * multiple interrupts at the same interrupt level.
1501 * As the interrupt level is determined by taking the
1502 * vector number and shifting that right by 4, we
1503 * want to spread these out a bit so that they don't
1504 * all fall in the same interrupt level.
1505 *
1506 * Also, we've got to be careful not to trash gate
1507 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1508 */
1509 for (irq = 0; irq < NR_IRQS ; irq++) {
1510 int tmp = irq;
13a79503 1511 if (IO_APIC_IRQ(tmp) && !irq_cfg[tmp].vector) {
1da177e4
LT		 1512 /*
1513 * Hmm.. We don't have an entry for this,
1514 * so default to an old-fashioned 8259
1515 * interrupt if we can..
1516 */
1517 if (irq < 16)
1518 make_8259A_irq(irq);
1519 else
1520 /* Strange. Oh, well.. */
f29bd1ba 1521 irq_desc[irq].chip = &no_irq_chip;
1da177e4
LT		 1522 }
1523 }
1524}
1525
1526static void enable_lapic_irq (unsigned int irq)
1527{
1528 unsigned long v;
1529
1530 v = apic_read(APIC_LVT0);
11a8e778 1531 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1da177e4
LT		 1532}
1533
1534static void disable_lapic_irq (unsigned int irq)
1535{
1536 unsigned long v;
1537
1538 v = apic_read(APIC_LVT0);
11a8e778 1539 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1da177e4
LT		 1540}
1541
1542static void ack_lapic_irq (unsigned int irq)
1543{
1544 ack_APIC_irq();
1545}
1546
1547static void end_lapic_irq (unsigned int i) { /* nothing */ }
1548
6c231b7b 1549static struct hw_interrupt_type lapic_irq_type __read_mostly = {
c47e285d 1550 .name = "local-APIC",
1da177e4
LT		 1551 .typename = "local-APIC-edge",
1552 .startup = NULL, /* startup_irq() not used for IRQ0 */
1553 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1554 .enable = enable_lapic_irq,
1555 .disable = disable_lapic_irq,
1556 .ack = ack_lapic_irq,
1557 .end = end_lapic_irq,
1558};
1559
1560static void setup_nmi (void)
1561{
1562 /*
1563 * Dirty trick to enable the NMI watchdog ...
1564 * We put the 8259A master into AEOI mode and
1565 * unmask on all local APICs LVT0 as NMI.
1566 *
1567 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1568 * is from Maciej W. Rozycki - so we do not have to EOI from
1569 * the NMI handler or the timer interrupt.
1570 */
1571 printk(KERN_INFO "activating NMI Watchdog ...");
1572
1573 enable_NMI_through_LVT0(NULL);
1574
1575 printk(" done.\n");
1576}
1577
1578/*
1579 * This looks a bit hackish but it's about the only one way of sending
1580 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1581 * not support the ExtINT mode, unfortunately. We need to send these
1582 * cycles as some i82489DX-based boards have glue logic that keeps the
1583 * 8259A interrupt line asserted until INTA. --macro
1584 */
1585static inline void unlock_ExtINT_logic(void)
1586{
1008fddc 1587 int apic, pin, i;
1da177e4
LT		 1588 struct IO_APIC_route_entry entry0, entry1;
1589 unsigned char save_control, save_freq_select;
1590 unsigned long flags;
1591
1008fddc
EB		 1592 pin = find_isa_irq_pin(8, mp_INT);
1593 apic = find_isa_irq_apic(8, mp_INT);
1da177e4
LT		 1594 if (pin == -1)
1595 return;
1596
1597 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 1598 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1599 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1da177e4 1600 spin_unlock_irqrestore(&ioapic_lock, flags);
1008fddc 1601 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 1602
1603 memset(&entry1, 0, sizeof(entry1));
1604
1605 entry1.dest_mode = 0; /* physical delivery */
1606 entry1.mask = 0; /* unmask IRQ now */
ee4eff6f 1607 entry1.dest = hard_smp_processor_id();
1da177e4
LT		 1608 entry1.delivery_mode = dest_ExtINT;
1609 entry1.polarity = entry0.polarity;
1610 entry1.trigger = 0;
1611 entry1.vector = 0;
1612
1613 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 1614 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1615 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1da177e4
LT		 1616 spin_unlock_irqrestore(&ioapic_lock, flags);
1617
1618 save_control = CMOS_READ(RTC_CONTROL);
1619 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1620 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1621 RTC_FREQ_SELECT);
1622 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1623
1624 i = 100;
1625 while (i-- > 0) {
1626 mdelay(10);
1627 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1628 i -= 10;
1629 }
1630
1631 CMOS_WRITE(save_control, RTC_CONTROL);
1632 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1008fddc 1633 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 1634
1635 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 1636 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1637 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1da177e4
LT		 1638 spin_unlock_irqrestore(&ioapic_lock, flags);
1639}
1640
1641/*
1642 * This code may look a bit paranoid, but it's supposed to cooperate with
1643 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1644 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1645 * fanatically on his truly buggy board.
fea5f1e1
LT		 1646 *
1647 * FIXME: really need to revamp this for modern platforms only.
1da177e4 1648 */
fea5f1e1 1649static inline void check_timer(void)
1da177e4 1650{
dfbffdd8 1651 struct irq_cfg *cfg = irq_cfg + 0;
1008fddc 1652 int apic1, pin1, apic2, pin2;
1da177e4
LT		 1653
1654 /*
1655 * get/set the timer IRQ vector:
1656 */
1657 disable_8259A_irq(0);
dfbffdd8 1658 assign_irq_vector(0, TARGET_CPUS);
1da177e4
LT		 1659
1660 /*
1661 * Subtle, code in do_timer_interrupt() expects an AEOI
1662 * mode for the 8259A whenever interrupts are routed
1663 * through I/O APICs. Also IRQ0 has to be enabled in
1664 * the 8259A which implies the virtual wire has to be
1665 * disabled in the local APIC.
1666 */
11a8e778 1667 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4 1668 init_8259A(1);
fea5f1e1
LT		 1669 if (timer_over_8254 > 0)
1670 enable_8259A_irq(0);
1da177e4 1671
1008fddc
EB		 1672 pin1 = find_isa_irq_pin(0, mp_INT);
1673 apic1 = find_isa_irq_apic(0, mp_INT);
1674 pin2 = ioapic_i8259.pin;
1675 apic2 = ioapic_i8259.apic;
1da177e4 1676
fea5f1e1 1677 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
dfbffdd8 1678 cfg->vector, apic1, pin1, apic2, pin2);
b0268726 1679
fea5f1e1
LT		 1680 if (pin1 != -1) {
1681 /*
1682 * Ok, does IRQ0 through the IOAPIC work?
1683 */
1684 unmask_IO_APIC_irq(0);
1685 if (!no_timer_check && timer_irq_works()) {
1686 nmi_watchdog_default();
1687 if (nmi_watchdog == NMI_IO_APIC) {
1688 disable_8259A_irq(0);
1689 setup_nmi();
1690 enable_8259A_irq(0);
1691 }
1692 if (disable_timer_pin_1 > 0)
1693 clear_IO_APIC_pin(0, pin1);
1694 return;
1695 }
1696 clear_IO_APIC_pin(apic1, pin1);
1697 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1698 "connected to IO-APIC\n");
1699 }
1da177e4 1700
fea5f1e1
LT		 1701 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1702 "through the 8259A ... ");
1da177e4 1703 if (pin2 != -1) {
fea5f1e1
LT		 1704 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1705 apic2, pin2);
1706 /*
1707 * legacy devices should be connected to IO APIC #0
1708 */
dfbffdd8 1709 setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
fea5f1e1
LT		 1710 if (timer_irq_works()) {
1711 apic_printk(APIC_VERBOSE," works.\n");
1712 nmi_watchdog_default();
1713 if (nmi_watchdog == NMI_IO_APIC) {
1714 setup_nmi();
1715 }
1da177e4 1716 return;
fea5f1e1
LT		 1717 }
1718 /*
1719 * Cleanup, just in case ...
1720 */
1721 clear_IO_APIC_pin(apic2, pin2);
1da177e4 1722 }
fea5f1e1 1723 apic_printk(APIC_VERBOSE," failed.\n");
1da177e4 1724
1f992153 1725 if (nmi_watchdog == NMI_IO_APIC) {
1da177e4
LT		 1726 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1727 nmi_watchdog = 0;
1728 }
1729
1730 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1731
1732 disable_8259A_irq(0);
d1bef4ed 1733 irq_desc[0].chip = &lapic_irq_type;
dfbffdd8 1734 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1da177e4
LT		 1735 enable_8259A_irq(0);
1736
1737 if (timer_irq_works()) {
5b922cd4 1738 apic_printk(APIC_VERBOSE," works.\n");
1da177e4
LT		 1739 return;
1740 }
dfbffdd8 1741 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1da177e4
LT		 1742 apic_printk(APIC_VERBOSE," failed.\n");
1743
1744 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1745
1746 init_8259A(0);
1747 make_8259A_irq(0);
11a8e778 1748 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4
LT		 1749
1750 unlock_ExtINT_logic();
1751
1752 if (timer_irq_works()) {
1753 apic_printk(APIC_VERBOSE," works.\n");
1754 return;
1755 }
1756 apic_printk(APIC_VERBOSE," failed :(.\n");
1757 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1758}
1759
14d98cad
AK		 1760static int __init notimercheck(char *s)
1761{
1762 no_timer_check = 1;
1763 return 1;
1764}
1765__setup("no_timer_check", notimercheck);
1766
1da177e4
LT		 1767/*
1768 *
1769 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1770 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1771 * Linux doesn't really care, as it's not actually used
1772 * for any interrupt handling anyway.
1773 */
1774#define PIC_IRQS (1<<2)
1775
1776void __init setup_IO_APIC(void)
1777{
1778 enable_IO_APIC();
1779
1780 if (acpi_ioapic)
1781 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1782 else
1783 io_apic_irqs = ~PIC_IRQS;
1784
1785 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1786
1da177e4
LT		 1787 sync_Arb_IDs();
1788 setup_IO_APIC_irqs();
1789 init_IO_APIC_traps();
1790 check_timer();
1791 if (!acpi_ioapic)
1792 print_IO_APIC();
1793}
1794
1795struct sysfs_ioapic_data {
1796 struct sys_device dev;
1797 struct IO_APIC_route_entry entry[0];
1798};
1799static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1800
0b9c33a7 1801static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4
LT		 1802{
1803 struct IO_APIC_route_entry *entry;
1804 struct sysfs_ioapic_data *data;
1da177e4
LT		 1805 int i;
1806
1807 data = container_of(dev, struct sysfs_ioapic_data, dev);
1808 entry = data->entry;
eea0e11c
AK		 1809 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1810 *entry = ioapic_read_entry(dev->id, i);
1da177e4
LT		 1811
1812 return 0;
1813}
1814
1815static int ioapic_resume(struct sys_device *dev)
1816{
1817 struct IO_APIC_route_entry *entry;
1818 struct sysfs_ioapic_data *data;
1819 unsigned long flags;
1820 union IO_APIC_reg_00 reg_00;
1821 int i;
1822
1823 data = container_of(dev, struct sysfs_ioapic_data, dev);
1824 entry = data->entry;
1825
1826 spin_lock_irqsave(&ioapic_lock, flags);
1827 reg_00.raw = io_apic_read(dev->id, 0);
1828 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1829 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1830 io_apic_write(dev->id, 0, reg_00.raw);
1831 }
1da177e4 1832 spin_unlock_irqrestore(&ioapic_lock, flags);
eea0e11c
AK		 1833 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1834 ioapic_write_entry(dev->id, i, entry[i]);
1da177e4
LT		 1835
1836 return 0;
1837}
1838
1839static struct sysdev_class ioapic_sysdev_class = {
1840 set_kset_name("ioapic"),
1841 .suspend = ioapic_suspend,
1842 .resume = ioapic_resume,
1843};
1844
1845static int __init ioapic_init_sysfs(void)
1846{
1847 struct sys_device * dev;
1848 int i, size, error = 0;
1849
1850 error = sysdev_class_register(&ioapic_sysdev_class);
1851 if (error)
1852 return error;
1853
1854 for (i = 0; i < nr_ioapics; i++ ) {
1855 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1856 * sizeof(struct IO_APIC_route_entry);
1857 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1858 if (!mp_ioapic_data[i]) {
1859 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1860 continue;
1861 }
1862 memset(mp_ioapic_data[i], 0, size);
1863 dev = &mp_ioapic_data[i]->dev;
1864 dev->id = i;
1865 dev->cls = &ioapic_sysdev_class;
1866 error = sysdev_register(dev);
1867 if (error) {
1868 kfree(mp_ioapic_data[i]);
1869 mp_ioapic_data[i] = NULL;
1870 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1871 continue;
1872 }
1873 }
1874
1875 return 0;
1876}
1877
1878device_initcall(ioapic_init_sysfs);
1879
c4fa0bbf 1880/*
04b9267b 1881 * Dynamic irq allocate and deallocation
c4fa0bbf
EB		 1882 */
1883int create_irq(void)
1884{
04b9267b
EB		 1885 /* Allocate an unused irq */
1886 int irq;
1887 int new;
c4fa0bbf 1888 unsigned long flags;
c4fa0bbf 1889
04b9267b
EB		 1890 irq = -ENOSPC;
1891 spin_lock_irqsave(&vector_lock, flags);
1892 for (new = (NR_IRQS - 1); new >= 0; new--) {
1893 if (platform_legacy_irq(new))
1894 continue;
13a79503 1895 if (irq_cfg[new].vector != 0)
04b9267b 1896 continue;
dfbffdd8 1897 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
04b9267b
EB		 1898 irq = new;
1899 break;
1900 }
1901 spin_unlock_irqrestore(&vector_lock, flags);
c4fa0bbf 1902
04b9267b 1903 if (irq >= 0) {
c4fa0bbf
EB		 1904 dynamic_irq_init(irq);
1905 }
1906 return irq;
1907}
1908
1909void destroy_irq(unsigned int irq)
1910{
1911 unsigned long flags;
c4fa0bbf
EB		 1912
1913 dynamic_irq_cleanup(irq);
1914
1915 spin_lock_irqsave(&vector_lock, flags);
5df0287e 1916 __clear_irq_vector(irq);
c4fa0bbf
EB		 1917 spin_unlock_irqrestore(&vector_lock, flags);
1918}
c4fa0bbf 1919
589e367f
EB		 1920/*
1921 * MSI mesage composition
1922 */
1923#ifdef CONFIG_PCI_MSI
3b7d1921 1924static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
589e367f 1925{
dfbffdd8
EB		 1926 struct irq_cfg *cfg = irq_cfg + irq;
1927 int err;
589e367f 1928 unsigned dest;
c7111c13 1929 cpumask_t tmp;
589e367f 1930
dfbffdd8
EB		 1931 tmp = TARGET_CPUS;
1932 err = assign_irq_vector(irq, tmp);
1933 if (!err) {
1934 cpus_and(tmp, cfg->domain, tmp);
589e367f
EB		 1935 dest = cpu_mask_to_apicid(tmp);
1936
1937 msg->address_hi = MSI_ADDR_BASE_HI;
1938 msg->address_lo =
1939 MSI_ADDR_BASE_LO |
1940 ((INT_DEST_MODE == 0) ?
1941 MSI_ADDR_DEST_MODE_PHYSICAL:
1942 MSI_ADDR_DEST_MODE_LOGICAL) |
1943 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1944 MSI_ADDR_REDIRECTION_CPU:
1945 MSI_ADDR_REDIRECTION_LOWPRI) |
1946 MSI_ADDR_DEST_ID(dest);
1947
1948 msg->data =
1949 MSI_DATA_TRIGGER_EDGE |
1950 MSI_DATA_LEVEL_ASSERT |
1951 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1952 MSI_DATA_DELIVERY_FIXED:
1953 MSI_DATA_DELIVERY_LOWPRI) |
dfbffdd8 1954 MSI_DATA_VECTOR(cfg->vector);
589e367f 1955 }
dfbffdd8 1956 return err;
589e367f
EB		 1957}
1958
3b7d1921
EB		 1959#ifdef CONFIG_SMP
1960static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
589e367f 1961{
dfbffdd8 1962 struct irq_cfg *cfg = irq_cfg + irq;
3b7d1921
EB		 1963 struct msi_msg msg;
1964 unsigned int dest;
1965 cpumask_t tmp;
3b7d1921
EB		 1966
1967 cpus_and(tmp, mask, cpu_online_map);
1968 if (cpus_empty(tmp))
5ff5115e 1969 return;
589e367f 1970
dfbffdd8 1971 if (assign_irq_vector(irq, mask))
3b7d1921 1972 return;
550f2299 1973
dfbffdd8 1974 cpus_and(tmp, cfg->domain, mask);
3b7d1921 1975 dest = cpu_mask_to_apicid(tmp);
589e367f 1976
3b7d1921
EB		 1977 read_msi_msg(irq, &msg);
1978
1979 msg.data &= ~MSI_DATA_VECTOR_MASK;
dfbffdd8 1980 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3b7d1921
EB		 1981 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1982 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1983
1984 write_msi_msg(irq, &msg);
9f0a5ba5 1985 irq_desc[irq].affinity = mask;
589e367f 1986}
3b7d1921 1987#endif /* CONFIG_SMP */
589e367f 1988
3b7d1921
EB		 1989/*
1990 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1991 * which implement the MSI or MSI-X Capability Structure.
1992 */
1993static struct irq_chip msi_chip = {
1994 .name = "PCI-MSI",
1995 .unmask = unmask_msi_irq,
1996 .mask = mask_msi_irq,
1997 .ack = ack_apic_edge,
1998#ifdef CONFIG_SMP
1999 .set_affinity = set_msi_irq_affinity,
2000#endif
2001 .retrigger = ioapic_retrigger_irq,
589e367f
EB		 2002};
2003
f7feaca7 2004int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
3b7d1921
EB		 2005{
2006 struct msi_msg msg;
f7feaca7
EB		 2007 int irq, ret;
2008 irq = create_irq();
2009 if (irq < 0)
2010 return irq;
2011
3b7d1921 2012 ret = msi_compose_msg(dev, irq, &msg);
f7feaca7
EB		 2013 if (ret < 0) {
2014 destroy_irq(irq);
3b7d1921 2015 return ret;
f7feaca7 2016 }
3b7d1921 2017
7fe3730d 2018 set_irq_msi(irq, desc);
3b7d1921
EB		 2019 write_msi_msg(irq, &msg);
2020
a460e745 2021 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3b7d1921 2022
7fe3730d 2023 return 0;
3b7d1921
EB		 2024}
2025
2026void arch_teardown_msi_irq(unsigned int irq)
2027{
f7feaca7 2028 destroy_irq(irq);
3b7d1921
EB		 2029}
2030
2031#endif /* CONFIG_PCI_MSI */
589e367f 2032
8b955b0d
EB		 2033/*
2034 * Hypertransport interrupt support
2035 */
2036#ifdef CONFIG_HT_IRQ
2037
2038#ifdef CONFIG_SMP
2039
2040static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2041{
ec68307c
EB		 2042 struct ht_irq_msg msg;
2043 fetch_ht_irq_msg(irq, &msg);
8b955b0d 2044
ec68307c
EB		 2045 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2046 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
8b955b0d 2047
ec68307c
EB		 2048 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2049 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 2050
ec68307c 2051 write_ht_irq_msg(irq, &msg);
8b955b0d
EB		 2052}
2053
2054static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2055{
dfbffdd8 2056 struct irq_cfg *cfg = irq_cfg + irq;
8b955b0d
EB		 2057 unsigned int dest;
2058 cpumask_t tmp;
8b955b0d
EB		 2059
2060 cpus_and(tmp, mask, cpu_online_map);
2061 if (cpus_empty(tmp))
5ff5115e 2062 return;
8b955b0d 2063
dfbffdd8 2064 if (assign_irq_vector(irq, mask))
8b955b0d
EB		 2065 return;
2066
dfbffdd8 2067 cpus_and(tmp, cfg->domain, mask);
8b955b0d
EB		 2068 dest = cpu_mask_to_apicid(tmp);
2069
dfbffdd8 2070 target_ht_irq(irq, dest, cfg->vector);
9f0a5ba5 2071 irq_desc[irq].affinity = mask;
8b955b0d
EB		 2072}
2073#endif
2074
c37e108d 2075static struct irq_chip ht_irq_chip = {
8b955b0d
EB		 2076 .name = "PCI-HT",
2077 .mask = mask_ht_irq,
2078 .unmask = unmask_ht_irq,
2079 .ack = ack_apic_edge,
2080#ifdef CONFIG_SMP
2081 .set_affinity = set_ht_irq_affinity,
2082#endif
2083 .retrigger = ioapic_retrigger_irq,
2084};
2085
2086int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2087{
dfbffdd8
EB		 2088 struct irq_cfg *cfg = irq_cfg + irq;
2089 int err;
c7111c13 2090 cpumask_t tmp;
8b955b0d 2091
dfbffdd8
EB		 2092 tmp = TARGET_CPUS;
2093 err = assign_irq_vector(irq, tmp);
2094 if (!err) {
ec68307c 2095 struct ht_irq_msg msg;
8b955b0d 2096 unsigned dest;
8b955b0d 2097
dfbffdd8 2098 cpus_and(tmp, cfg->domain, tmp);
8b955b0d
EB		 2099 dest = cpu_mask_to_apicid(tmp);
2100
ec68307c 2101 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 2102
ec68307c
EB		 2103 msg.address_lo =
2104 HT_IRQ_LOW_BASE |
8b955b0d 2105 HT_IRQ_LOW_DEST_ID(dest) |
dfbffdd8 2106 HT_IRQ_LOW_VECTOR(cfg->vector) |
8b955b0d
EB		 2107 ((INT_DEST_MODE == 0) ?
2108 HT_IRQ_LOW_DM_PHYSICAL :
2109 HT_IRQ_LOW_DM_LOGICAL) |
2110 HT_IRQ_LOW_RQEOI_EDGE |
2111 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2112 HT_IRQ_LOW_MT_FIXED :
ec68307c
EB		 2113 HT_IRQ_LOW_MT_ARBITRATED) |
2114 HT_IRQ_LOW_IRQ_MASKED;
8b955b0d 2115
ec68307c 2116 write_ht_irq_msg(irq, &msg);
8b955b0d 2117
a460e745
IM		 2118 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2119 handle_edge_irq, "edge");
8b955b0d 2120 }
dfbffdd8 2121 return err;
8b955b0d
EB		 2122}
2123#endif /* CONFIG_HT_IRQ */
2124
1da177e4
LT		 2125/* --------------------------------------------------------------------------
2126 ACPI-based IOAPIC Configuration
2127 -------------------------------------------------------------------------- */
2128
888ba6c6 2129#ifdef CONFIG_ACPI
1da177e4
LT		 2130
2131#define IO_APIC_MAX_ID 0xFE
2132
1da177e4
LT		 2133int __init io_apic_get_redir_entries (int ioapic)
2134{
2135 union IO_APIC_reg_01 reg_01;
2136 unsigned long flags;
2137
2138 spin_lock_irqsave(&ioapic_lock, flags);
2139 reg_01.raw = io_apic_read(ioapic, 1);
2140 spin_unlock_irqrestore(&ioapic_lock, flags);
2141
2142 return reg_01.bits.entries;
2143}
2144
2145
50eca3eb 2146int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1da177e4 2147{
1da177e4
LT		 2148 if (!IO_APIC_IRQ(irq)) {
2149 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2150 ioapic);
2151 return -EINVAL;
2152 }
2153
550f2299
EB		 2154 /*
2155 * IRQs < 16 are already in the irq_2_pin[] map
2156 */
2157 if (irq >= 16)
2158 add_pin_to_irq(irq, ioapic, pin);
2159
a8c8a367 2160 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
1da177e4
LT		 2161
2162 return 0;
2163}
2164
888ba6c6 2165#endif /* CONFIG_ACPI */
1da177e4
LT		 2166
2167
2168/*
2169 * This function currently is only a helper for the i386 smp boot process where
2170 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2171 * so mask in all cases should simply be TARGET_CPUS
2172 */
54d5d424 2173#ifdef CONFIG_SMP
1da177e4
LT		 2174void __init setup_ioapic_dest(void)
2175{
2176 int pin, ioapic, irq, irq_entry;
2177
2178 if (skip_ioapic_setup == 1)
2179 return;
2180
2181 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2182 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2183 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2184 if (irq_entry == -1)
2185 continue;
2186 irq = pin_2_irq(irq_entry, ioapic, pin);
ad892f5e
YL		 2187
2188 /* setup_IO_APIC_irqs could fail to get vector for some device
2189 * when you have too many devices, because at that time only boot
2190 * cpu is online.
2191 */
13a79503 2192 if (!irq_cfg[irq].vector)
a8c8a367
EB		 2193 setup_IO_APIC_irq(ioapic, pin, irq,
2194 irq_trigger(irq_entry),
2195 irq_polarity(irq_entry));
ad892f5e
YL		 2196 else
2197 set_ioapic_affinity_irq(irq, TARGET_CPUS);
1da177e4
LT		 2198 }
2199
2200 }
2201}
54d5d424 2202#endif
Linux kernel - Deliverables
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