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Merge from-linus to-akpm
[deliverable/linux.git] / arch / x86_64 / kernel / io_apic.c
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1da177e4
LT		 1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
24#include <linux/irq.h>
25#include <linux/interrupt.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/sched.h>
29#include <linux/config.h>
30#include <linux/smp_lock.h>
31#include <linux/mc146818rtc.h>
32#include <linux/acpi.h>
33#include <linux/sysdev.h>
34
35#include <asm/io.h>
36#include <asm/smp.h>
37#include <asm/desc.h>
38#include <asm/proto.h>
39#include <asm/mach_apic.h>
8d916406 40#include <asm/acpi.h>
1da177e4
LT		 41
42#define __apicdebuginit __init
43
44int sis_apic_bug; /* not actually supported, dummy for compile */
45
14d98cad
AK		 46static int no_timer_check;
47
1da177e4
LT		 48static DEFINE_SPINLOCK(ioapic_lock);
49
50/*
51 * # of IRQ routing registers
52 */
53int nr_ioapic_registers[MAX_IO_APICS];
54
55/*
56 * Rough estimation of how many shared IRQs there are, can
57 * be changed anytime.
58 */
59#define MAX_PLUS_SHARED_IRQS NR_IRQS
60#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
61
62/*
63 * This is performance-critical, we want to do it O(1)
64 *
65 * the indexing order of this array favors 1:1 mappings
66 * between pins and IRQs.
67 */
68
69static struct irq_pin_list {
70 short apic, pin, next;
71} irq_2_pin[PIN_MAP_SIZE];
72
73int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
74#ifdef CONFIG_PCI_MSI
75#define vector_to_irq(vector) \
76 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
77#else
78#define vector_to_irq(vector) (vector)
79#endif
80
81/*
82 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
83 * shared ISA-space IRQs, so we have to support them. We are super
84 * fast in the common case, and fast for shared ISA-space IRQs.
85 */
86static void add_pin_to_irq(unsigned int irq, int apic, int pin)
87{
88 static int first_free_entry = NR_IRQS;
89 struct irq_pin_list *entry = irq_2_pin + irq;
90
91 while (entry->next)
92 entry = irq_2_pin + entry->next;
93
94 if (entry->pin != -1) {
95 entry->next = first_free_entry;
96 entry = irq_2_pin + entry->next;
97 if (++first_free_entry >= PIN_MAP_SIZE)
98 panic("io_apic.c: whoops");
99 }
100 entry->apic = apic;
101 entry->pin = pin;
102}
103
104#define __DO_ACTION(R, ACTION, FINAL) \
105 \
106{ \
107 int pin; \
108 struct irq_pin_list *entry = irq_2_pin + irq; \
109 \
110 for (;;) { \
111 unsigned int reg; \
112 pin = entry->pin; \
113 if (pin == -1) \
114 break; \
115 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
116 reg ACTION; \
117 io_apic_modify(entry->apic, reg); \
118 if (!entry->next) \
119 break; \
120 entry = irq_2_pin + entry->next; \
121 } \
122 FINAL; \
123}
124
125#define DO_ACTION(name,R,ACTION, FINAL) \
126 \
127 static void name##_IO_APIC_irq (unsigned int irq) \
128 __DO_ACTION(R, ACTION, FINAL)
129
130DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
131 /* mask = 1 */
132DO_ACTION( __unmask, 0, &= 0xfffeffff, )
133 /* mask = 0 */
134
135static void mask_IO_APIC_irq (unsigned int irq)
136{
137 unsigned long flags;
138
139 spin_lock_irqsave(&ioapic_lock, flags);
140 __mask_IO_APIC_irq(irq);
141 spin_unlock_irqrestore(&ioapic_lock, flags);
142}
143
144static void unmask_IO_APIC_irq (unsigned int irq)
145{
146 unsigned long flags;
147
148 spin_lock_irqsave(&ioapic_lock, flags);
149 __unmask_IO_APIC_irq(irq);
150 spin_unlock_irqrestore(&ioapic_lock, flags);
151}
152
153static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
154{
155 struct IO_APIC_route_entry entry;
156 unsigned long flags;
157
158 /* Check delivery_mode to be sure we're not clearing an SMI pin */
159 spin_lock_irqsave(&ioapic_lock, flags);
160 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
161 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
162 spin_unlock_irqrestore(&ioapic_lock, flags);
163 if (entry.delivery_mode == dest_SMI)
164 return;
165 /*
166 * Disable it in the IO-APIC irq-routing table:
167 */
168 memset(&entry, 0, sizeof(entry));
169 entry.mask = 1;
170 spin_lock_irqsave(&ioapic_lock, flags);
171 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
172 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
173 spin_unlock_irqrestore(&ioapic_lock, flags);
174}
175
176static void clear_IO_APIC (void)
177{
178 int apic, pin;
179
180 for (apic = 0; apic < nr_ioapics; apic++)
181 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
182 clear_IO_APIC_pin(apic, pin);
183}
184
185/*
186 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
187 * specific CPU-side IRQs.
188 */
189
190#define MAX_PIRQS 8
191static int pirq_entries [MAX_PIRQS];
192static int pirqs_enabled;
193int skip_ioapic_setup;
194int ioapic_force;
195
196/* dummy parsing: see setup.c */
197
198static int __init disable_ioapic_setup(char *str)
199{
200 skip_ioapic_setup = 1;
201 return 1;
202}
203
204static int __init enable_ioapic_setup(char *str)
205{
206 ioapic_force = 1;
207 skip_ioapic_setup = 0;
208 return 1;
209}
210
211__setup("noapic", disable_ioapic_setup);
212__setup("apic", enable_ioapic_setup);
213
214#include <asm/pci-direct.h>
215#include <linux/pci_ids.h>
216#include <linux/pci.h>
217
218/* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
219 off. Check for an Nvidia or VIA PCI bridge and turn it off.
220 Use pci direct infrastructure because this runs before the PCI subsystem.
221
222 Can be overwritten with "apic"
223
224 And another hack to disable the IOMMU on VIA chipsets.
225
226 Kludge-O-Rama. */
227void __init check_ioapic(void)
228{
229 int num,slot,func;
230 if (ioapic_force)
231 return;
232
233 /* Poor man's PCI discovery */
234 for (num = 0; num < 32; num++) {
235 for (slot = 0; slot < 32; slot++) {
236 for (func = 0; func < 8; func++) {
237 u32 class;
238 u32 vendor;
239 u8 type;
240 class = read_pci_config(num,slot,func,
241 PCI_CLASS_REVISION);
242 if (class == 0xffffffff)
243 break;
244
245 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
246 continue;
247
248 vendor = read_pci_config(num, slot, func,
249 PCI_VENDOR_ID);
250 vendor &= 0xffff;
251 switch (vendor) {
252 case PCI_VENDOR_ID_VIA:
253#ifdef CONFIG_GART_IOMMU
254 if ((end_pfn >= (0xffffffff>>PAGE_SHIFT) ||
255 force_iommu) &&
256 !iommu_aperture_allowed) {
257 printk(KERN_INFO
258 "Looks like a VIA chipset. Disabling IOMMU. Overwrite with \"iommu=allowed\"\n");
259 iommu_aperture_disabled = 1;
260 }
261#endif
262 return;
263 case PCI_VENDOR_ID_NVIDIA:
264#ifdef CONFIG_ACPI
265 /* All timer overrides on Nvidia
266 seem to be wrong. Skip them. */
267 acpi_skip_timer_override = 1;
268 printk(KERN_INFO
269 "Nvidia board detected. Ignoring ACPI timer override.\n");
270#endif
271 /* RED-PEN skip them on mptables too? */
272 return;
273 }
274
275 /* No multi-function device? */
276 type = read_pci_config_byte(num,slot,func,
277 PCI_HEADER_TYPE);
278 if (!(type & 0x80))
279 break;
280 }
281 }
282 }
283}
284
285static int __init ioapic_pirq_setup(char *str)
286{
287 int i, max;
288 int ints[MAX_PIRQS+1];
289
290 get_options(str, ARRAY_SIZE(ints), ints);
291
292 for (i = 0; i < MAX_PIRQS; i++)
293 pirq_entries[i] = -1;
294
295 pirqs_enabled = 1;
296 apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
297 max = MAX_PIRQS;
298 if (ints[0] < MAX_PIRQS)
299 max = ints[0];
300
301 for (i = 0; i < max; i++) {
302 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
303 /*
304 * PIRQs are mapped upside down, usually.
305 */
306 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
307 }
308 return 1;
309}
310
311__setup("pirq=", ioapic_pirq_setup);
312
313/*
314 * Find the IRQ entry number of a certain pin.
315 */
316static int find_irq_entry(int apic, int pin, int type)
317{
318 int i;
319
320 for (i = 0; i < mp_irq_entries; i++)
321 if (mp_irqs[i].mpc_irqtype == type &&
322 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
323 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
324 mp_irqs[i].mpc_dstirq == pin)
325 return i;
326
327 return -1;
328}
329
330/*
331 * Find the pin to which IRQ[irq] (ISA) is connected
332 */
208fb931 333static int find_isa_irq_pin(int irq, int type)
1da177e4
LT		 334{
335 int i;
336
337 for (i = 0; i < mp_irq_entries; i++) {
338 int lbus = mp_irqs[i].mpc_srcbus;
339
340 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
341 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
342 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
343 (mp_irqs[i].mpc_irqtype == type) &&
344 (mp_irqs[i].mpc_srcbusirq == irq))
345
346 return mp_irqs[i].mpc_dstirq;
347 }
348 return -1;
349}
350
351/*
352 * Find a specific PCI IRQ entry.
353 * Not an __init, possibly needed by modules
354 */
355static int pin_2_irq(int idx, int apic, int pin);
356
357int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
358{
359 int apic, i, best_guess = -1;
360
361 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
362 bus, slot, pin);
363 if (mp_bus_id_to_pci_bus[bus] == -1) {
364 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
365 return -1;
366 }
367 for (i = 0; i < mp_irq_entries; i++) {
368 int lbus = mp_irqs[i].mpc_srcbus;
369
370 for (apic = 0; apic < nr_ioapics; apic++)
371 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
372 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
373 break;
374
375 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
376 !mp_irqs[i].mpc_irqtype &&
377 (bus == lbus) &&
378 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
379 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
380
381 if (!(apic || IO_APIC_IRQ(irq)))
382 continue;
383
384 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
385 return irq;
386 /*
387 * Use the first all-but-pin matching entry as a
388 * best-guess fuzzy result for broken mptables.
389 */
390 if (best_guess < 0)
391 best_guess = irq;
392 }
393 }
394 return best_guess;
395}
396
397/*
398 * EISA Edge/Level control register, ELCR
399 */
400static int EISA_ELCR(unsigned int irq)
401{
402 if (irq < 16) {
403 unsigned int port = 0x4d0 + (irq >> 3);
404 return (inb(port) >> (irq & 7)) & 1;
405 }
406 apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
407 return 0;
408}
409
410/* EISA interrupts are always polarity zero and can be edge or level
411 * trigger depending on the ELCR value. If an interrupt is listed as
412 * EISA conforming in the MP table, that means its trigger type must
413 * be read in from the ELCR */
414
415#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
416#define default_EISA_polarity(idx) (0)
417
418/* ISA interrupts are always polarity zero edge triggered,
419 * when listed as conforming in the MP table. */
420
421#define default_ISA_trigger(idx) (0)
422#define default_ISA_polarity(idx) (0)
423
424/* PCI interrupts are always polarity one level triggered,
425 * when listed as conforming in the MP table. */
426
427#define default_PCI_trigger(idx) (1)
428#define default_PCI_polarity(idx) (1)
429
430/* MCA interrupts are always polarity zero level triggered,
431 * when listed as conforming in the MP table. */
432
433#define default_MCA_trigger(idx) (1)
434#define default_MCA_polarity(idx) (0)
435
436static int __init MPBIOS_polarity(int idx)
437{
438 int bus = mp_irqs[idx].mpc_srcbus;
439 int polarity;
440
441 /*
442 * Determine IRQ line polarity (high active or low active):
443 */
444 switch (mp_irqs[idx].mpc_irqflag & 3)
445 {
446 case 0: /* conforms, ie. bus-type dependent polarity */
447 {
448 switch (mp_bus_id_to_type[bus])
449 {
450 case MP_BUS_ISA: /* ISA pin */
451 {
452 polarity = default_ISA_polarity(idx);
453 break;
454 }
455 case MP_BUS_EISA: /* EISA pin */
456 {
457 polarity = default_EISA_polarity(idx);
458 break;
459 }
460 case MP_BUS_PCI: /* PCI pin */
461 {
462 polarity = default_PCI_polarity(idx);
463 break;
464 }
465 case MP_BUS_MCA: /* MCA pin */
466 {
467 polarity = default_MCA_polarity(idx);
468 break;
469 }
470 default:
471 {
472 printk(KERN_WARNING "broken BIOS!!\n");
473 polarity = 1;
474 break;
475 }
476 }
477 break;
478 }
479 case 1: /* high active */
480 {
481 polarity = 0;
482 break;
483 }
484 case 2: /* reserved */
485 {
486 printk(KERN_WARNING "broken BIOS!!\n");
487 polarity = 1;
488 break;
489 }
490 case 3: /* low active */
491 {
492 polarity = 1;
493 break;
494 }
495 default: /* invalid */
496 {
497 printk(KERN_WARNING "broken BIOS!!\n");
498 polarity = 1;
499 break;
500 }
501 }
502 return polarity;
503}
504
505static int MPBIOS_trigger(int idx)
506{
507 int bus = mp_irqs[idx].mpc_srcbus;
508 int trigger;
509
510 /*
511 * Determine IRQ trigger mode (edge or level sensitive):
512 */
513 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
514 {
515 case 0: /* conforms, ie. bus-type dependent */
516 {
517 switch (mp_bus_id_to_type[bus])
518 {
519 case MP_BUS_ISA: /* ISA pin */
520 {
521 trigger = default_ISA_trigger(idx);
522 break;
523 }
524 case MP_BUS_EISA: /* EISA pin */
525 {
526 trigger = default_EISA_trigger(idx);
527 break;
528 }
529 case MP_BUS_PCI: /* PCI pin */
530 {
531 trigger = default_PCI_trigger(idx);
532 break;
533 }
534 case MP_BUS_MCA: /* MCA pin */
535 {
536 trigger = default_MCA_trigger(idx);
537 break;
538 }
539 default:
540 {
541 printk(KERN_WARNING "broken BIOS!!\n");
542 trigger = 1;
543 break;
544 }
545 }
546 break;
547 }
548 case 1: /* edge */
549 {
550 trigger = 0;
551 break;
552 }
553 case 2: /* reserved */
554 {
555 printk(KERN_WARNING "broken BIOS!!\n");
556 trigger = 1;
557 break;
558 }
559 case 3: /* level */
560 {
561 trigger = 1;
562 break;
563 }
564 default: /* invalid */
565 {
566 printk(KERN_WARNING "broken BIOS!!\n");
567 trigger = 0;
568 break;
569 }
570 }
571 return trigger;
572}
573
574static inline int irq_polarity(int idx)
575{
576 return MPBIOS_polarity(idx);
577}
578
579static inline int irq_trigger(int idx)
580{
581 return MPBIOS_trigger(idx);
582}
583
584static int pin_2_irq(int idx, int apic, int pin)
585{
586 int irq, i;
587 int bus = mp_irqs[idx].mpc_srcbus;
588
589 /*
590 * Debugging check, we are in big trouble if this message pops up!
591 */
592 if (mp_irqs[idx].mpc_dstirq != pin)
593 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
594
595 switch (mp_bus_id_to_type[bus])
596 {
597 case MP_BUS_ISA: /* ISA pin */
598 case MP_BUS_EISA:
599 case MP_BUS_MCA:
600 {
601 irq = mp_irqs[idx].mpc_srcbusirq;
602 break;
603 }
604 case MP_BUS_PCI: /* PCI pin */
605 {
606 /*
607 * PCI IRQs are mapped in order
608 */
609 i = irq = 0;
610 while (i < apic)
611 irq += nr_ioapic_registers[i++];
612 irq += pin;
613 break;
614 }
615 default:
616 {
617 printk(KERN_ERR "unknown bus type %d.\n",bus);
618 irq = 0;
619 break;
620 }
621 }
622
623 /*
624 * PCI IRQ command line redirection. Yes, limits are hardcoded.
625 */
626 if ((pin >= 16) && (pin <= 23)) {
627 if (pirq_entries[pin-16] != -1) {
628 if (!pirq_entries[pin-16]) {
629 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
630 } else {
631 irq = pirq_entries[pin-16];
632 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
633 pin-16, irq);
634 }
635 }
636 }
637 return irq;
638}
639
640static inline int IO_APIC_irq_trigger(int irq)
641{
642 int apic, idx, pin;
643
644 for (apic = 0; apic < nr_ioapics; apic++) {
645 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
646 idx = find_irq_entry(apic,pin,mp_INT);
647 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
648 return irq_trigger(idx);
649 }
650 }
651 /*
652 * nonexistent IRQs are edge default
653 */
654 return 0;
655}
656
657/* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
658u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
659
660int assign_irq_vector(int irq)
661{
662 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
663
664 BUG_ON(irq >= NR_IRQ_VECTORS);
665 if (IO_APIC_VECTOR(irq) > 0)
666 return IO_APIC_VECTOR(irq);
667next:
668 current_vector += 8;
669 if (current_vector == IA32_SYSCALL_VECTOR)
670 goto next;
671
672 if (current_vector >= FIRST_SYSTEM_VECTOR) {
673 offset++;
674 if (!(offset%8))
675 return -ENOSPC;
676 current_vector = FIRST_DEVICE_VECTOR + offset;
677 }
678
679 vector_irq[current_vector] = irq;
680 if (irq != AUTO_ASSIGN)
681 IO_APIC_VECTOR(irq) = current_vector;
682
683 return current_vector;
684}
685
686extern void (*interrupt[NR_IRQS])(void);
687static struct hw_interrupt_type ioapic_level_type;
688static struct hw_interrupt_type ioapic_edge_type;
689
690#define IOAPIC_AUTO -1
691#define IOAPIC_EDGE 0
692#define IOAPIC_LEVEL 1
693
694static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
695{
696 if (use_pci_vector() && !platform_legacy_irq(irq)) {
697 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
698 trigger == IOAPIC_LEVEL)
699 irq_desc[vector].handler = &ioapic_level_type;
700 else
701 irq_desc[vector].handler = &ioapic_edge_type;
702 set_intr_gate(vector, interrupt[vector]);
703 } else {
704 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
705 trigger == IOAPIC_LEVEL)
706 irq_desc[irq].handler = &ioapic_level_type;
707 else
708 irq_desc[irq].handler = &ioapic_edge_type;
709 set_intr_gate(vector, interrupt[irq]);
710 }
711}
712
713static void __init setup_IO_APIC_irqs(void)
714{
715 struct IO_APIC_route_entry entry;
716 int apic, pin, idx, irq, first_notcon = 1, vector;
717 unsigned long flags;
718
719 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
720
721 for (apic = 0; apic < nr_ioapics; apic++) {
722 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
723
724 /*
725 * add it to the IO-APIC irq-routing table:
726 */
727 memset(&entry,0,sizeof(entry));
728
729 entry.delivery_mode = INT_DELIVERY_MODE;
730 entry.dest_mode = INT_DEST_MODE;
731 entry.mask = 0; /* enable IRQ */
732 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
733
734 idx = find_irq_entry(apic,pin,mp_INT);
735 if (idx == -1) {
736 if (first_notcon) {
737 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
738 first_notcon = 0;
739 } else
740 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
741 continue;
742 }
743
744 entry.trigger = irq_trigger(idx);
745 entry.polarity = irq_polarity(idx);
746
747 if (irq_trigger(idx)) {
748 entry.trigger = 1;
749 entry.mask = 1;
750 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
751 }
752
753 irq = pin_2_irq(idx, apic, pin);
754 add_pin_to_irq(irq, apic, pin);
755
756 if (!apic && !IO_APIC_IRQ(irq))
757 continue;
758
759 if (IO_APIC_IRQ(irq)) {
760 vector = assign_irq_vector(irq);
761 entry.vector = vector;
762
763 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
764 if (!apic && (irq < 16))
765 disable_8259A_irq(irq);
766 }
767 spin_lock_irqsave(&ioapic_lock, flags);
768 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
769 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
770 spin_unlock_irqrestore(&ioapic_lock, flags);
771 }
772 }
773
774 if (!first_notcon)
775 apic_printk(APIC_VERBOSE," not connected.\n");
776}
777
778/*
779 * Set up the 8259A-master output pin as broadcast to all
780 * CPUs.
781 */
782static void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
783{
784 struct IO_APIC_route_entry entry;
785 unsigned long flags;
786
787 memset(&entry,0,sizeof(entry));
788
789 disable_8259A_irq(0);
790
791 /* mask LVT0 */
792 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
793
794 /*
795 * We use logical delivery to get the timer IRQ
796 * to the first CPU.
797 */
798 entry.dest_mode = INT_DEST_MODE;
799 entry.mask = 0; /* unmask IRQ now */
800 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
801 entry.delivery_mode = INT_DELIVERY_MODE;
802 entry.polarity = 0;
803 entry.trigger = 0;
804 entry.vector = vector;
805
806 /*
807 * The timer IRQ doesn't have to know that behind the
808 * scene we have a 8259A-master in AEOI mode ...
809 */
810 irq_desc[0].handler = &ioapic_edge_type;
811
812 /*
813 * Add it to the IO-APIC irq-routing table:
814 */
815 spin_lock_irqsave(&ioapic_lock, flags);
816 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
817 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
818 spin_unlock_irqrestore(&ioapic_lock, flags);
819
820 enable_8259A_irq(0);
821}
822
823void __init UNEXPECTED_IO_APIC(void)
824{
825}
826
827void __apicdebuginit print_IO_APIC(void)
828{
829 int apic, i;
830 union IO_APIC_reg_00 reg_00;
831 union IO_APIC_reg_01 reg_01;
832 union IO_APIC_reg_02 reg_02;
833 unsigned long flags;
834
835 if (apic_verbosity == APIC_QUIET)
836 return;
837
838 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
839 for (i = 0; i < nr_ioapics; i++)
840 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
841 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
842
843 /*
844 * We are a bit conservative about what we expect. We have to
845 * know about every hardware change ASAP.
846 */
847 printk(KERN_INFO "testing the IO APIC.......................\n");
848
849 for (apic = 0; apic < nr_ioapics; apic++) {
850
851 spin_lock_irqsave(&ioapic_lock, flags);
852 reg_00.raw = io_apic_read(apic, 0);
853 reg_01.raw = io_apic_read(apic, 1);
854 if (reg_01.bits.version >= 0x10)
855 reg_02.raw = io_apic_read(apic, 2);
856 spin_unlock_irqrestore(&ioapic_lock, flags);
857
858 printk("\n");
859 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
860 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
861 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
862 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
863 UNEXPECTED_IO_APIC();
864
865 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
866 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
867 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
868 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
869 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
870 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
871 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
872 (reg_01.bits.entries != 0x2E) &&
873 (reg_01.bits.entries != 0x3F) &&
874 (reg_01.bits.entries != 0x03)
875 )
876 UNEXPECTED_IO_APIC();
877
878 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
879 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
880 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
881 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
882 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
883 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
884 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
885 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
886 )
887 UNEXPECTED_IO_APIC();
888 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
889 UNEXPECTED_IO_APIC();
890
891 if (reg_01.bits.version >= 0x10) {
892 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
893 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
894 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
895 UNEXPECTED_IO_APIC();
896 }
897
898 printk(KERN_DEBUG ".... IRQ redirection table:\n");
899
900 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
901 " Stat Dest Deli Vect: \n");
902
903 for (i = 0; i <= reg_01.bits.entries; i++) {
904 struct IO_APIC_route_entry entry;
905
906 spin_lock_irqsave(&ioapic_lock, flags);
907 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
908 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
909 spin_unlock_irqrestore(&ioapic_lock, flags);
910
911 printk(KERN_DEBUG " %02x %03X %02X ",
912 i,
913 entry.dest.logical.logical_dest,
914 entry.dest.physical.physical_dest
915 );
916
917 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
918 entry.mask,
919 entry.trigger,
920 entry.irr,
921 entry.polarity,
922 entry.delivery_status,
923 entry.dest_mode,
924 entry.delivery_mode,
925 entry.vector
926 );
927 }
928 }
929 if (use_pci_vector())
930 printk(KERN_INFO "Using vector-based indexing\n");
931 printk(KERN_DEBUG "IRQ to pin mappings:\n");
932 for (i = 0; i < NR_IRQS; i++) {
933 struct irq_pin_list *entry = irq_2_pin + i;
934 if (entry->pin < 0)
935 continue;
936 if (use_pci_vector() && !platform_legacy_irq(i))
937 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
938 else
939 printk(KERN_DEBUG "IRQ%d ", i);
940 for (;;) {
941 printk("-> %d:%d", entry->apic, entry->pin);
942 if (!entry->next)
943 break;
944 entry = irq_2_pin + entry->next;
945 }
946 printk("\n");
947 }
948
949 printk(KERN_INFO ".................................... done.\n");
950
951 return;
952}
953
954#if 0
955
956static __apicdebuginit void print_APIC_bitfield (int base)
957{
958 unsigned int v;
959 int i, j;
960
961 if (apic_verbosity == APIC_QUIET)
962 return;
963
964 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
965 for (i = 0; i < 8; i++) {
966 v = apic_read(base + i*0x10);
967 for (j = 0; j < 32; j++) {
968 if (v & (1<<j))
969 printk("1");
970 else
971 printk("0");
972 }
973 printk("\n");
974 }
975}
976
977void __apicdebuginit print_local_APIC(void * dummy)
978{
979 unsigned int v, ver, maxlvt;
980
981 if (apic_verbosity == APIC_QUIET)
982 return;
983
984 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
985 smp_processor_id(), hard_smp_processor_id());
986 v = apic_read(APIC_ID);
987 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
988 v = apic_read(APIC_LVR);
989 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
990 ver = GET_APIC_VERSION(v);
991 maxlvt = get_maxlvt();
992
993 v = apic_read(APIC_TASKPRI);
994 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
995
996 if (APIC_INTEGRATED(ver)) { /* !82489DX */
997 v = apic_read(APIC_ARBPRI);
998 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
999 v & APIC_ARBPRI_MASK);
1000 v = apic_read(APIC_PROCPRI);
1001 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1002 }
1003
1004 v = apic_read(APIC_EOI);
1005 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1006 v = apic_read(APIC_RRR);
1007 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1008 v = apic_read(APIC_LDR);
1009 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1010 v = apic_read(APIC_DFR);
1011 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1012 v = apic_read(APIC_SPIV);
1013 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1014
1015 printk(KERN_DEBUG "... APIC ISR field:\n");
1016 print_APIC_bitfield(APIC_ISR);
1017 printk(KERN_DEBUG "... APIC TMR field:\n");
1018 print_APIC_bitfield(APIC_TMR);
1019 printk(KERN_DEBUG "... APIC IRR field:\n");
1020 print_APIC_bitfield(APIC_IRR);
1021
1022 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1023 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1024 apic_write(APIC_ESR, 0);
1025 v = apic_read(APIC_ESR);
1026 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1027 }
1028
1029 v = apic_read(APIC_ICR);
1030 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1031 v = apic_read(APIC_ICR2);
1032 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1033
1034 v = apic_read(APIC_LVTT);
1035 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1036
1037 if (maxlvt > 3) { /* PC is LVT#4. */
1038 v = apic_read(APIC_LVTPC);
1039 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1040 }
1041 v = apic_read(APIC_LVT0);
1042 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1043 v = apic_read(APIC_LVT1);
1044 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1045
1046 if (maxlvt > 2) { /* ERR is LVT#3. */
1047 v = apic_read(APIC_LVTERR);
1048 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1049 }
1050
1051 v = apic_read(APIC_TMICT);
1052 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1053 v = apic_read(APIC_TMCCT);
1054 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1055 v = apic_read(APIC_TDCR);
1056 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1057 printk("\n");
1058}
1059
1060void print_all_local_APICs (void)
1061{
1062 on_each_cpu(print_local_APIC, NULL, 1, 1);
1063}
1064
1065void __apicdebuginit print_PIC(void)
1066{
1da177e4
LT		 1067 unsigned int v;
1068 unsigned long flags;
1069
1070 if (apic_verbosity == APIC_QUIET)
1071 return;
1072
1073 printk(KERN_DEBUG "\nprinting PIC contents\n");
1074
1075 spin_lock_irqsave(&i8259A_lock, flags);
1076
1077 v = inb(0xa1) << 8 | inb(0x21);
1078 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1079
1080 v = inb(0xa0) << 8 | inb(0x20);
1081 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1082
1083 outb(0x0b,0xa0);
1084 outb(0x0b,0x20);
1085 v = inb(0xa0) << 8 | inb(0x20);
1086 outb(0x0a,0xa0);
1087 outb(0x0a,0x20);
1088
1089 spin_unlock_irqrestore(&i8259A_lock, flags);
1090
1091 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1092
1093 v = inb(0x4d1) << 8 | inb(0x4d0);
1094 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1095}
1096
1097#endif /* 0 */
1098
1099static void __init enable_IO_APIC(void)
1100{
1101 union IO_APIC_reg_01 reg_01;
1102 int i;
1103 unsigned long flags;
1104
1105 for (i = 0; i < PIN_MAP_SIZE; i++) {
1106 irq_2_pin[i].pin = -1;
1107 irq_2_pin[i].next = 0;
1108 }
1109 if (!pirqs_enabled)
1110 for (i = 0; i < MAX_PIRQS; i++)
1111 pirq_entries[i] = -1;
1112
1113 /*
1114 * The number of IO-APIC IRQ registers (== #pins):
1115 */
1116 for (i = 0; i < nr_ioapics; i++) {
1117 spin_lock_irqsave(&ioapic_lock, flags);
1118 reg_01.raw = io_apic_read(i, 1);
1119 spin_unlock_irqrestore(&ioapic_lock, flags);
1120 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1121 }
1122
1123 /*
1124 * Do not trust the IO-APIC being empty at bootup
1125 */
1126 clear_IO_APIC();
1127}
1128
1129/*
1130 * Not an __init, needed by the reboot code
1131 */
1132void disable_IO_APIC(void)
1133{
208fb931 1134 int pin;
1da177e4
LT		 1135 /*
1136 * Clear the IO-APIC before rebooting:
1137 */
1138 clear_IO_APIC();
1139
208fb931
EB		 1140 /*
1141 * If the i82559 is routed through an IOAPIC
1142 * Put that IOAPIC in virtual wire mode
1143 * so legacy interrups can be delivered.
1144 */
1145 pin = find_isa_irq_pin(0, mp_ExtINT);
1146 if (pin != -1) {
1147 struct IO_APIC_route_entry entry;
1148 unsigned long flags;
1149
1150 memset(&entry, 0, sizeof(entry));
1151 entry.mask = 0; /* Enabled */
1152 entry.trigger = 0; /* Edge */
1153 entry.irr = 0;
1154 entry.polarity = 0; /* High */
1155 entry.delivery_status = 0;
1156 entry.dest_mode = 0; /* Physical */
1157 entry.delivery_mode = 7; /* ExtInt */
1158 entry.vector = 0;
1159 entry.dest.physical.physical_dest = 0;
1160
1161
1162 /*
1163 * Add it to the IO-APIC irq-routing table:
1164 */
1165 spin_lock_irqsave(&ioapic_lock, flags);
1166 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1167 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1168 spin_unlock_irqrestore(&ioapic_lock, flags);
1169 }
1170
1171 disconnect_bsp_APIC(pin != -1);
1da177e4
LT		 1172}
1173
1174/*
1175 * function to set the IO-APIC physical IDs based on the
1176 * values stored in the MPC table.
1177 *
1178 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1179 */
1180
1181static void __init setup_ioapic_ids_from_mpc (void)
1182{
1183 union IO_APIC_reg_00 reg_00;
1184 int apic;
1185 int i;
1186 unsigned char old_id;
1187 unsigned long flags;
1188
1189 /*
1190 * Set the IOAPIC ID to the value stored in the MPC table.
1191 */
1192 for (apic = 0; apic < nr_ioapics; apic++) {
1193
1194 /* Read the register 0 value */
1195 spin_lock_irqsave(&ioapic_lock, flags);
1196 reg_00.raw = io_apic_read(apic, 0);
1197 spin_unlock_irqrestore(&ioapic_lock, flags);
1198
1199 old_id = mp_ioapics[apic].mpc_apicid;
1200
1201
1202 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1203
1204
1205 /*
1206 * We need to adjust the IRQ routing table
1207 * if the ID changed.
1208 */
1209 if (old_id != mp_ioapics[apic].mpc_apicid)
1210 for (i = 0; i < mp_irq_entries; i++)
1211 if (mp_irqs[i].mpc_dstapic == old_id)
1212 mp_irqs[i].mpc_dstapic
1213 = mp_ioapics[apic].mpc_apicid;
1214
1215 /*
1216 * Read the right value from the MPC table and
1217 * write it into the ID register.
1218 */
1219 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1220 mp_ioapics[apic].mpc_apicid);
1221
1222 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1223 spin_lock_irqsave(&ioapic_lock, flags);
1224 io_apic_write(apic, 0, reg_00.raw);
1225 spin_unlock_irqrestore(&ioapic_lock, flags);
1226
1227 /*
1228 * Sanity check
1229 */
1230 spin_lock_irqsave(&ioapic_lock, flags);
1231 reg_00.raw = io_apic_read(apic, 0);
1232 spin_unlock_irqrestore(&ioapic_lock, flags);
1233 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1234 printk("could not set ID!\n");
1235 else
1236 apic_printk(APIC_VERBOSE," ok.\n");
1237 }
1238}
1239
1240/*
1241 * There is a nasty bug in some older SMP boards, their mptable lies
1242 * about the timer IRQ. We do the following to work around the situation:
1243 *
1244 * - timer IRQ defaults to IO-APIC IRQ
1245 * - if this function detects that timer IRQs are defunct, then we fall
1246 * back to ISA timer IRQs
1247 */
1248static int __init timer_irq_works(void)
1249{
1250 unsigned long t1 = jiffies;
1251
1252 local_irq_enable();
1253 /* Let ten ticks pass... */
1254 mdelay((10 * 1000) / HZ);
1255
1256 /*
1257 * Expect a few ticks at least, to be sure some possible
1258 * glue logic does not lock up after one or two first
1259 * ticks in a non-ExtINT mode. Also the local APIC
1260 * might have cached one ExtINT interrupt. Finally, at
1261 * least one tick may be lost due to delays.
1262 */
1263
1264 /* jiffies wrap? */
1265 if (jiffies - t1 > 4)
1266 return 1;
1267 return 0;
1268}
1269
1270/*
1271 * In the SMP+IOAPIC case it might happen that there are an unspecified
1272 * number of pending IRQ events unhandled. These cases are very rare,
1273 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1274 * better to do it this way as thus we do not have to be aware of
1275 * 'pending' interrupts in the IRQ path, except at this point.
1276 */
1277/*
1278 * Edge triggered needs to resend any interrupt
1279 * that was delayed but this is now handled in the device
1280 * independent code.
1281 */
1282
1283/*
1284 * Starting up a edge-triggered IO-APIC interrupt is
1285 * nasty - we need to make sure that we get the edge.
1286 * If it is already asserted for some reason, we need
1287 * return 1 to indicate that is was pending.
1288 *
1289 * This is not complete - we should be able to fake
1290 * an edge even if it isn't on the 8259A...
1291 */
1292
1293static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1294{
1295 int was_pending = 0;
1296 unsigned long flags;
1297
1298 spin_lock_irqsave(&ioapic_lock, flags);
1299 if (irq < 16) {
1300 disable_8259A_irq(irq);
1301 if (i8259A_irq_pending(irq))
1302 was_pending = 1;
1303 }
1304 __unmask_IO_APIC_irq(irq);
1305 spin_unlock_irqrestore(&ioapic_lock, flags);
1306
1307 return was_pending;
1308}
1309
1310/*
1311 * Once we have recorded IRQ_PENDING already, we can mask the
1312 * interrupt for real. This prevents IRQ storms from unhandled
1313 * devices.
1314 */
1315static void ack_edge_ioapic_irq(unsigned int irq)
1316{
1317 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1318 == (IRQ_PENDING | IRQ_DISABLED))
1319 mask_IO_APIC_irq(irq);
1320 ack_APIC_irq();
1321}
1322
1323/*
1324 * Level triggered interrupts can just be masked,
1325 * and shutting down and starting up the interrupt
1326 * is the same as enabling and disabling them -- except
1327 * with a startup need to return a "was pending" value.
1328 *
1329 * Level triggered interrupts are special because we
1330 * do not touch any IO-APIC register while handling
1331 * them. We ack the APIC in the end-IRQ handler, not
1332 * in the start-IRQ-handler. Protection against reentrance
1333 * from the same interrupt is still provided, both by the
1334 * generic IRQ layer and by the fact that an unacked local
1335 * APIC does not accept IRQs.
1336 */
1337static unsigned int startup_level_ioapic_irq (unsigned int irq)
1338{
1339 unmask_IO_APIC_irq(irq);
1340
1341 return 0; /* don't check for pending */
1342}
1343
1344static void end_level_ioapic_irq (unsigned int irq)
1345{
1346 ack_APIC_irq();
1347}
1348
1349static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1350{
1351 unsigned long flags;
1352 unsigned int dest;
1353
1354 dest = cpu_mask_to_apicid(mask);
1355
1356 /*
1357 * Only the high 8 bits are valid.
1358 */
1359 dest = SET_APIC_LOGICAL_ID(dest);
1360
1361 spin_lock_irqsave(&ioapic_lock, flags);
1362 __DO_ACTION(1, = dest, )
1363 spin_unlock_irqrestore(&ioapic_lock, flags);
1364}
1365
1366#ifdef CONFIG_PCI_MSI
1367static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1368{
1369 int irq = vector_to_irq(vector);
1370
1371 return startup_edge_ioapic_irq(irq);
1372}
1373
1374static void ack_edge_ioapic_vector(unsigned int vector)
1375{
1376 int irq = vector_to_irq(vector);
1377
1378 ack_edge_ioapic_irq(irq);
1379}
1380
1381static unsigned int startup_level_ioapic_vector (unsigned int vector)
1382{
1383 int irq = vector_to_irq(vector);
1384
1385 return startup_level_ioapic_irq (irq);
1386}
1387
1388static void end_level_ioapic_vector (unsigned int vector)
1389{
1390 int irq = vector_to_irq(vector);
1391
1392 end_level_ioapic_irq(irq);
1393}
1394
1395static void mask_IO_APIC_vector (unsigned int vector)
1396{
1397 int irq = vector_to_irq(vector);
1398
1399 mask_IO_APIC_irq(irq);
1400}
1401
1402static void unmask_IO_APIC_vector (unsigned int vector)
1403{
1404 int irq = vector_to_irq(vector);
1405
1406 unmask_IO_APIC_irq(irq);
1407}
1408
1409static void set_ioapic_affinity_vector (unsigned int vector,
1410 cpumask_t cpu_mask)
1411{
1412 int irq = vector_to_irq(vector);
1413
1414 set_ioapic_affinity_irq(irq, cpu_mask);
1415}
1416#endif
1417
1418/*
1419 * Level and edge triggered IO-APIC interrupts need different handling,
1420 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1421 * handled with the level-triggered descriptor, but that one has slightly
1422 * more overhead. Level-triggered interrupts cannot be handled with the
1423 * edge-triggered handler, without risking IRQ storms and other ugly
1424 * races.
1425 */
1426
1427static struct hw_interrupt_type ioapic_edge_type = {
1428 .typename = "IO-APIC-edge",
1429 .startup = startup_edge_ioapic,
1430 .shutdown = shutdown_edge_ioapic,
1431 .enable = enable_edge_ioapic,
1432 .disable = disable_edge_ioapic,
1433 .ack = ack_edge_ioapic,
1434 .end = end_edge_ioapic,
1435 .set_affinity = set_ioapic_affinity,
1436};
1437
1438static struct hw_interrupt_type ioapic_level_type = {
1439 .typename = "IO-APIC-level",
1440 .startup = startup_level_ioapic,
1441 .shutdown = shutdown_level_ioapic,
1442 .enable = enable_level_ioapic,
1443 .disable = disable_level_ioapic,
1444 .ack = mask_and_ack_level_ioapic,
1445 .end = end_level_ioapic,
1446 .set_affinity = set_ioapic_affinity,
1447};
1448
1449static inline void init_IO_APIC_traps(void)
1450{
1451 int irq;
1452
1453 /*
1454 * NOTE! The local APIC isn't very good at handling
1455 * multiple interrupts at the same interrupt level.
1456 * As the interrupt level is determined by taking the
1457 * vector number and shifting that right by 4, we
1458 * want to spread these out a bit so that they don't
1459 * all fall in the same interrupt level.
1460 *
1461 * Also, we've got to be careful not to trash gate
1462 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1463 */
1464 for (irq = 0; irq < NR_IRQS ; irq++) {
1465 int tmp = irq;
1466 if (use_pci_vector()) {
1467 if (!platform_legacy_irq(tmp))
1468 if ((tmp = vector_to_irq(tmp)) == -1)
1469 continue;
1470 }
1471 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1472 /*
1473 * Hmm.. We don't have an entry for this,
1474 * so default to an old-fashioned 8259
1475 * interrupt if we can..
1476 */
1477 if (irq < 16)
1478 make_8259A_irq(irq);
1479 else
1480 /* Strange. Oh, well.. */
1481 irq_desc[irq].handler = &no_irq_type;
1482 }
1483 }
1484}
1485
1486static void enable_lapic_irq (unsigned int irq)
1487{
1488 unsigned long v;
1489
1490 v = apic_read(APIC_LVT0);
1491 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1492}
1493
1494static void disable_lapic_irq (unsigned int irq)
1495{
1496 unsigned long v;
1497
1498 v = apic_read(APIC_LVT0);
1499 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1500}
1501
1502static void ack_lapic_irq (unsigned int irq)
1503{
1504 ack_APIC_irq();
1505}
1506
1507static void end_lapic_irq (unsigned int i) { /* nothing */ }
1508
1509static struct hw_interrupt_type lapic_irq_type = {
1510 .typename = "local-APIC-edge",
1511 .startup = NULL, /* startup_irq() not used for IRQ0 */
1512 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1513 .enable = enable_lapic_irq,
1514 .disable = disable_lapic_irq,
1515 .ack = ack_lapic_irq,
1516 .end = end_lapic_irq,
1517};
1518
1519static void setup_nmi (void)
1520{
1521 /*
1522 * Dirty trick to enable the NMI watchdog ...
1523 * We put the 8259A master into AEOI mode and
1524 * unmask on all local APICs LVT0 as NMI.
1525 *
1526 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1527 * is from Maciej W. Rozycki - so we do not have to EOI from
1528 * the NMI handler or the timer interrupt.
1529 */
1530 printk(KERN_INFO "activating NMI Watchdog ...");
1531
1532 enable_NMI_through_LVT0(NULL);
1533
1534 printk(" done.\n");
1535}
1536
1537/*
1538 * This looks a bit hackish but it's about the only one way of sending
1539 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1540 * not support the ExtINT mode, unfortunately. We need to send these
1541 * cycles as some i82489DX-based boards have glue logic that keeps the
1542 * 8259A interrupt line asserted until INTA. --macro
1543 */
1544static inline void unlock_ExtINT_logic(void)
1545{
1546 int pin, i;
1547 struct IO_APIC_route_entry entry0, entry1;
1548 unsigned char save_control, save_freq_select;
1549 unsigned long flags;
1550
1551 pin = find_isa_irq_pin(8, mp_INT);
1552 if (pin == -1)
1553 return;
1554
1555 spin_lock_irqsave(&ioapic_lock, flags);
1556 *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1557 *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1558 spin_unlock_irqrestore(&ioapic_lock, flags);
1559 clear_IO_APIC_pin(0, pin);
1560
1561 memset(&entry1, 0, sizeof(entry1));
1562
1563 entry1.dest_mode = 0; /* physical delivery */
1564 entry1.mask = 0; /* unmask IRQ now */
1565 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1566 entry1.delivery_mode = dest_ExtINT;
1567 entry1.polarity = entry0.polarity;
1568 entry1.trigger = 0;
1569 entry1.vector = 0;
1570
1571 spin_lock_irqsave(&ioapic_lock, flags);
1572 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1573 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1574 spin_unlock_irqrestore(&ioapic_lock, flags);
1575
1576 save_control = CMOS_READ(RTC_CONTROL);
1577 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1578 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1579 RTC_FREQ_SELECT);
1580 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1581
1582 i = 100;
1583 while (i-- > 0) {
1584 mdelay(10);
1585 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1586 i -= 10;
1587 }
1588
1589 CMOS_WRITE(save_control, RTC_CONTROL);
1590 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1591 clear_IO_APIC_pin(0, pin);
1592
1593 spin_lock_irqsave(&ioapic_lock, flags);
1594 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1595 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1596 spin_unlock_irqrestore(&ioapic_lock, flags);
1597}
1598
1599/*
1600 * This code may look a bit paranoid, but it's supposed to cooperate with
1601 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1602 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1603 * fanatically on his truly buggy board.
1604 */
1605static inline void check_timer(void)
1606{
1607 int pin1, pin2;
1608 int vector;
1609
1610 /*
1611 * get/set the timer IRQ vector:
1612 */
1613 disable_8259A_irq(0);
1614 vector = assign_irq_vector(0);
1615 set_intr_gate(vector, interrupt[0]);
1616
1617 /*
1618 * Subtle, code in do_timer_interrupt() expects an AEOI
1619 * mode for the 8259A whenever interrupts are routed
1620 * through I/O APICs. Also IRQ0 has to be enabled in
1621 * the 8259A which implies the virtual wire has to be
1622 * disabled in the local APIC.
1623 */
1624 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1625 init_8259A(1);
1626 enable_8259A_irq(0);
1627
1628 pin1 = find_isa_irq_pin(0, mp_INT);
1629 pin2 = find_isa_irq_pin(0, mp_ExtINT);
1630
1631 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1632
1633 if (pin1 != -1) {
1634 /*
1635 * Ok, does IRQ0 through the IOAPIC work?
1636 */
1637 unmask_IO_APIC_irq(0);
14d98cad 1638 if (!no_timer_check && timer_irq_works()) {
1da177e4
LT		 1639 nmi_watchdog_default();
1640 if (nmi_watchdog == NMI_IO_APIC) {
1641 disable_8259A_irq(0);
1642 setup_nmi();
1643 enable_8259A_irq(0);
1da177e4
LT		 1644 }
1645 return;
1646 }
1647 clear_IO_APIC_pin(0, pin1);
1648 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1649 }
1650
1651 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1652 if (pin2 != -1) {
1653 apic_printk(APIC_VERBOSE,"\n..... (found pin %d) ...", pin2);
1654 /*
1655 * legacy devices should be connected to IO APIC #0
1656 */
1657 setup_ExtINT_IRQ0_pin(pin2, vector);
1658 if (timer_irq_works()) {
1659 printk("works.\n");
1660 nmi_watchdog_default();
1661 if (nmi_watchdog == NMI_IO_APIC) {
1662 setup_nmi();
1da177e4
LT		 1663 }
1664 return;
1665 }
1666 /*
1667 * Cleanup, just in case ...
1668 */
1669 clear_IO_APIC_pin(0, pin2);
1670 }
1671 printk(" failed.\n");
1672
1673 if (nmi_watchdog) {
1674 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1675 nmi_watchdog = 0;
1676 }
1677
1678 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1679
1680 disable_8259A_irq(0);
1681 irq_desc[0].handler = &lapic_irq_type;
1682 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1683 enable_8259A_irq(0);
1684
1685 if (timer_irq_works()) {
1686 apic_printk(APIC_QUIET, " works.\n");
1687 return;
1688 }
1689 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1690 apic_printk(APIC_VERBOSE," failed.\n");
1691
1692 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1693
1694 init_8259A(0);
1695 make_8259A_irq(0);
1696 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1697
1698 unlock_ExtINT_logic();
1699
1700 if (timer_irq_works()) {
1701 apic_printk(APIC_VERBOSE," works.\n");
1702 return;
1703 }
1704 apic_printk(APIC_VERBOSE," failed :(.\n");
1705 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1706}
1707
14d98cad
AK		 1708static int __init notimercheck(char *s)
1709{
1710 no_timer_check = 1;
1711 return 1;
1712}
1713__setup("no_timer_check", notimercheck);
1714
1da177e4
LT		 1715/*
1716 *
1717 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1718 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1719 * Linux doesn't really care, as it's not actually used
1720 * for any interrupt handling anyway.
1721 */
1722#define PIC_IRQS (1<<2)
1723
1724void __init setup_IO_APIC(void)
1725{
1726 enable_IO_APIC();
1727
1728 if (acpi_ioapic)
1729 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1730 else
1731 io_apic_irqs = ~PIC_IRQS;
1732
1733 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1734
1735 /*
1736 * Set up the IO-APIC IRQ routing table.
1737 */
1738 if (!acpi_ioapic)
1739 setup_ioapic_ids_from_mpc();
1740 sync_Arb_IDs();
1741 setup_IO_APIC_irqs();
1742 init_IO_APIC_traps();
1743 check_timer();
1744 if (!acpi_ioapic)
1745 print_IO_APIC();
1746}
1747
1748struct sysfs_ioapic_data {
1749 struct sys_device dev;
1750 struct IO_APIC_route_entry entry[0];
1751};
1752static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1753
0b9c33a7 1754static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4
LT		 1755{
1756 struct IO_APIC_route_entry *entry;
1757 struct sysfs_ioapic_data *data;
1758 unsigned long flags;
1759 int i;
1760
1761 data = container_of(dev, struct sysfs_ioapic_data, dev);
1762 entry = data->entry;
1763 spin_lock_irqsave(&ioapic_lock, flags);
1764 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1765 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
1766 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
1767 }
1768 spin_unlock_irqrestore(&ioapic_lock, flags);
1769
1770 return 0;
1771}
1772
1773static int ioapic_resume(struct sys_device *dev)
1774{
1775 struct IO_APIC_route_entry *entry;
1776 struct sysfs_ioapic_data *data;
1777 unsigned long flags;
1778 union IO_APIC_reg_00 reg_00;
1779 int i;
1780
1781 data = container_of(dev, struct sysfs_ioapic_data, dev);
1782 entry = data->entry;
1783
1784 spin_lock_irqsave(&ioapic_lock, flags);
1785 reg_00.raw = io_apic_read(dev->id, 0);
1786 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1787 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1788 io_apic_write(dev->id, 0, reg_00.raw);
1789 }
1790 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1791 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
1792 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
1793 }
1794 spin_unlock_irqrestore(&ioapic_lock, flags);
1795
1796 return 0;
1797}
1798
1799static struct sysdev_class ioapic_sysdev_class = {
1800 set_kset_name("ioapic"),
1801 .suspend = ioapic_suspend,
1802 .resume = ioapic_resume,
1803};
1804
1805static int __init ioapic_init_sysfs(void)
1806{
1807 struct sys_device * dev;
1808 int i, size, error = 0;
1809
1810 error = sysdev_class_register(&ioapic_sysdev_class);
1811 if (error)
1812 return error;
1813
1814 for (i = 0; i < nr_ioapics; i++ ) {
1815 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1816 * sizeof(struct IO_APIC_route_entry);
1817 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1818 if (!mp_ioapic_data[i]) {
1819 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1820 continue;
1821 }
1822 memset(mp_ioapic_data[i], 0, size);
1823 dev = &mp_ioapic_data[i]->dev;
1824 dev->id = i;
1825 dev->cls = &ioapic_sysdev_class;
1826 error = sysdev_register(dev);
1827 if (error) {
1828 kfree(mp_ioapic_data[i]);
1829 mp_ioapic_data[i] = NULL;
1830 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1831 continue;
1832 }
1833 }
1834
1835 return 0;
1836}
1837
1838device_initcall(ioapic_init_sysfs);
1839
1840/* --------------------------------------------------------------------------
1841 ACPI-based IOAPIC Configuration
1842 -------------------------------------------------------------------------- */
1843
1844#ifdef CONFIG_ACPI_BOOT
1845
1846#define IO_APIC_MAX_ID 0xFE
1847
1da177e4
LT		 1848int __init io_apic_get_version (int ioapic)
1849{
1850 union IO_APIC_reg_01 reg_01;
1851 unsigned long flags;
1852
1853 spin_lock_irqsave(&ioapic_lock, flags);
1854 reg_01.raw = io_apic_read(ioapic, 1);
1855 spin_unlock_irqrestore(&ioapic_lock, flags);
1856
1857 return reg_01.bits.version;
1858}
1859
1860
1861int __init io_apic_get_redir_entries (int ioapic)
1862{
1863 union IO_APIC_reg_01 reg_01;
1864 unsigned long flags;
1865
1866 spin_lock_irqsave(&ioapic_lock, flags);
1867 reg_01.raw = io_apic_read(ioapic, 1);
1868 spin_unlock_irqrestore(&ioapic_lock, flags);
1869
1870 return reg_01.bits.entries;
1871}
1872
1873
1874int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1875{
1876 struct IO_APIC_route_entry entry;
1877 unsigned long flags;
1878
1879 if (!IO_APIC_IRQ(irq)) {
1880 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1881 ioapic);
1882 return -EINVAL;
1883 }
1884
1885 /*
1886 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1887 * Note that we mask (disable) IRQs now -- these get enabled when the
1888 * corresponding device driver registers for this IRQ.
1889 */
1890
1891 memset(&entry,0,sizeof(entry));
1892
1893 entry.delivery_mode = INT_DELIVERY_MODE;
1894 entry.dest_mode = INT_DEST_MODE;
1895 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1896 entry.trigger = edge_level;
1897 entry.polarity = active_high_low;
1898 entry.mask = 1; /* Disabled (masked) */
1899
1900 /*
1901 * IRQs < 16 are already in the irq_2_pin[] map
1902 */
1903 if (irq >= 16)
1904 add_pin_to_irq(irq, ioapic, pin);
1905
1906 entry.vector = assign_irq_vector(irq);
1907
1908 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1909 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1910 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1911 edge_level, active_high_low);
1912
1913 ioapic_register_intr(irq, entry.vector, edge_level);
1914
1915 if (!ioapic && (irq < 16))
1916 disable_8259A_irq(irq);
1917
1918 spin_lock_irqsave(&ioapic_lock, flags);
1919 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1920 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
1921 spin_unlock_irqrestore(&ioapic_lock, flags);
1922
1923 return 0;
1924}
1925
1926#endif /*CONFIG_ACPI_BOOT*/
1927
1928
1929/*
1930 * This function currently is only a helper for the i386 smp boot process where
1931 * we need to reprogram the ioredtbls to cater for the cpus which have come online
1932 * so mask in all cases should simply be TARGET_CPUS
1933 */
1934void __init setup_ioapic_dest(void)
1935{
1936 int pin, ioapic, irq, irq_entry;
1937
1938 if (skip_ioapic_setup == 1)
1939 return;
1940
1941 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
1942 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
1943 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
1944 if (irq_entry == -1)
1945 continue;
1946 irq = pin_2_irq(irq_entry, ioapic, pin);
1947 set_ioapic_affinity_irq(irq, TARGET_CPUS);
1948 }
1949
1950 }
1951}
Linux kernel - Deliverables
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