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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
1da177e4 LT |
28 | #include <linux/smp_lock.h> |
29 | #include <linux/mc146818rtc.h> | |
30 | #include <linux/acpi.h> | |
31 | #include <linux/sysdev.h> | |
ab688059 AK |
32 | #ifdef CONFIG_ACPI |
33 | #include <acpi/acpi_bus.h> | |
34 | #endif | |
1da177e4 LT |
35 | |
36 | #include <asm/io.h> | |
37 | #include <asm/smp.h> | |
38 | #include <asm/desc.h> | |
39 | #include <asm/proto.h> | |
40 | #include <asm/mach_apic.h> | |
8d916406 | 41 | #include <asm/acpi.h> |
ca8642f6 | 42 | #include <asm/dma.h> |
3e4ff115 | 43 | #include <asm/nmi.h> |
1da177e4 LT |
44 | |
45 | #define __apicdebuginit __init | |
46 | ||
47 | int sis_apic_bug; /* not actually supported, dummy for compile */ | |
48 | ||
14d98cad AK |
49 | static int no_timer_check; |
50 | ||
2c8c0e6b | 51 | static int disable_timer_pin_1 __initdata; |
66759a01 | 52 | |
9b2a13b9 | 53 | int timer_over_8254 __initdata = 0; |
ab9b32ee | 54 | |
1008fddc EB |
55 | /* Where if anywhere is the i8259 connect in external int mode */ |
56 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
57 | ||
1da177e4 | 58 | static DEFINE_SPINLOCK(ioapic_lock); |
0a1ad60d | 59 | static DEFINE_SPINLOCK(vector_lock); |
1da177e4 LT |
60 | |
61 | /* | |
62 | * # of IRQ routing registers | |
63 | */ | |
64 | int nr_ioapic_registers[MAX_IO_APICS]; | |
65 | ||
66 | /* | |
67 | * Rough estimation of how many shared IRQs there are, can | |
68 | * be changed anytime. | |
69 | */ | |
6004e1b7 | 70 | #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS |
1da177e4 LT |
71 | #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS) |
72 | ||
73 | /* | |
74 | * This is performance-critical, we want to do it O(1) | |
75 | * | |
76 | * the indexing order of this array favors 1:1 mappings | |
77 | * between pins and IRQs. | |
78 | */ | |
79 | ||
80 | static struct irq_pin_list { | |
81 | short apic, pin, next; | |
82 | } irq_2_pin[PIN_MAP_SIZE]; | |
83 | ||
6c231b7b | 84 | int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1}; |
1da177e4 LT |
85 | #ifdef CONFIG_PCI_MSI |
86 | #define vector_to_irq(vector) \ | |
87 | (platform_legacy_irq(vector) ? vector : vector_irq[vector]) | |
88 | #else | |
89 | #define vector_to_irq(vector) (vector) | |
90 | #endif | |
91 | ||
54d5d424 AR |
92 | #define __DO_ACTION(R, ACTION, FINAL) \ |
93 | \ | |
94 | { \ | |
95 | int pin; \ | |
96 | struct irq_pin_list *entry = irq_2_pin + irq; \ | |
97 | \ | |
6004e1b7 | 98 | BUG_ON(irq >= NR_IRQS); \ |
54d5d424 AR |
99 | for (;;) { \ |
100 | unsigned int reg; \ | |
101 | pin = entry->pin; \ | |
102 | if (pin == -1) \ | |
103 | break; \ | |
104 | reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \ | |
105 | reg ACTION; \ | |
106 | io_apic_modify(entry->apic, reg); \ | |
107 | if (!entry->next) \ | |
108 | break; \ | |
109 | entry = irq_2_pin + entry->next; \ | |
110 | } \ | |
111 | FINAL; \ | |
112 | } | |
113 | ||
eea0e11c AK |
114 | union entry_union { |
115 | struct { u32 w1, w2; }; | |
116 | struct IO_APIC_route_entry entry; | |
117 | }; | |
118 | ||
119 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
120 | { | |
121 | union entry_union eu; | |
122 | unsigned long flags; | |
123 | spin_lock_irqsave(&ioapic_lock, flags); | |
124 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
125 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
126 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
127 | return eu.entry; | |
128 | } | |
129 | ||
130 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
131 | { | |
132 | unsigned long flags; | |
133 | union entry_union eu; | |
134 | eu.entry = e; | |
135 | spin_lock_irqsave(&ioapic_lock, flags); | |
136 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
137 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
138 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
139 | } | |
140 | ||
54d5d424 AR |
141 | #ifdef CONFIG_SMP |
142 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) | |
143 | { | |
144 | unsigned long flags; | |
145 | unsigned int dest; | |
146 | cpumask_t tmp; | |
147 | ||
148 | cpus_and(tmp, mask, cpu_online_map); | |
149 | if (cpus_empty(tmp)) | |
150 | tmp = TARGET_CPUS; | |
151 | ||
152 | cpus_and(mask, tmp, CPU_MASK_ALL); | |
153 | ||
154 | dest = cpu_mask_to_apicid(mask); | |
155 | ||
156 | /* | |
157 | * Only the high 8 bits are valid. | |
158 | */ | |
159 | dest = SET_APIC_LOGICAL_ID(dest); | |
160 | ||
161 | spin_lock_irqsave(&ioapic_lock, flags); | |
162 | __DO_ACTION(1, = dest, ) | |
163 | set_irq_info(irq, mask); | |
164 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
165 | } | |
166 | #endif | |
167 | ||
6004e1b7 JC |
168 | static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF }; |
169 | ||
1da177e4 LT |
170 | /* |
171 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
172 | * shared ISA-space IRQs, so we have to support them. We are super | |
173 | * fast in the common case, and fast for shared ISA-space IRQs. | |
174 | */ | |
175 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) | |
176 | { | |
177 | static int first_free_entry = NR_IRQS; | |
178 | struct irq_pin_list *entry = irq_2_pin + irq; | |
179 | ||
6004e1b7 | 180 | BUG_ON(irq >= NR_IRQS); |
1da177e4 LT |
181 | while (entry->next) |
182 | entry = irq_2_pin + entry->next; | |
183 | ||
184 | if (entry->pin != -1) { | |
185 | entry->next = first_free_entry; | |
186 | entry = irq_2_pin + entry->next; | |
187 | if (++first_free_entry >= PIN_MAP_SIZE) | |
6004e1b7 | 188 | panic("io_apic.c: ran out of irq_2_pin entries!"); |
1da177e4 LT |
189 | } |
190 | entry->apic = apic; | |
191 | entry->pin = pin; | |
192 | } | |
193 | ||
1da177e4 LT |
194 | |
195 | #define DO_ACTION(name,R,ACTION, FINAL) \ | |
196 | \ | |
197 | static void name##_IO_APIC_irq (unsigned int irq) \ | |
198 | __DO_ACTION(R, ACTION, FINAL) | |
199 | ||
200 | DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) ) | |
201 | /* mask = 1 */ | |
202 | DO_ACTION( __unmask, 0, &= 0xfffeffff, ) | |
203 | /* mask = 0 */ | |
204 | ||
205 | static void mask_IO_APIC_irq (unsigned int irq) | |
206 | { | |
207 | unsigned long flags; | |
208 | ||
209 | spin_lock_irqsave(&ioapic_lock, flags); | |
210 | __mask_IO_APIC_irq(irq); | |
211 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
212 | } | |
213 | ||
214 | static void unmask_IO_APIC_irq (unsigned int irq) | |
215 | { | |
216 | unsigned long flags; | |
217 | ||
218 | spin_lock_irqsave(&ioapic_lock, flags); | |
219 | __unmask_IO_APIC_irq(irq); | |
220 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
221 | } | |
222 | ||
223 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |
224 | { | |
225 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
226 | |
227 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ | |
eea0e11c | 228 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
229 | if (entry.delivery_mode == dest_SMI) |
230 | return; | |
231 | /* | |
232 | * Disable it in the IO-APIC irq-routing table: | |
233 | */ | |
234 | memset(&entry, 0, sizeof(entry)); | |
235 | entry.mask = 1; | |
eea0e11c | 236 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
237 | } |
238 | ||
239 | static void clear_IO_APIC (void) | |
240 | { | |
241 | int apic, pin; | |
242 | ||
243 | for (apic = 0; apic < nr_ioapics; apic++) | |
244 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
245 | clear_IO_APIC_pin(apic, pin); | |
246 | } | |
247 | ||
1da177e4 LT |
248 | int skip_ioapic_setup; |
249 | int ioapic_force; | |
250 | ||
251 | /* dummy parsing: see setup.c */ | |
252 | ||
253 | static int __init disable_ioapic_setup(char *str) | |
254 | { | |
255 | skip_ioapic_setup = 1; | |
2c8c0e6b | 256 | return 0; |
1da177e4 | 257 | } |
2c8c0e6b | 258 | early_param("noapic", disable_ioapic_setup); |
1da177e4 | 259 | |
2c8c0e6b AK |
260 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
261 | static int __init disable_timer_pin_setup(char *arg) | |
1da177e4 | 262 | { |
2c8c0e6b | 263 | disable_timer_pin_1 = 1; |
1da177e4 LT |
264 | return 1; |
265 | } | |
2c8c0e6b | 266 | __setup("disable_timer_pin_1", disable_timer_pin_setup); |
1da177e4 | 267 | |
ab9b32ee AK |
268 | static int __init setup_disable_8254_timer(char *s) |
269 | { | |
270 | timer_over_8254 = -1; | |
271 | return 1; | |
272 | } | |
273 | static int __init setup_enable_8254_timer(char *s) | |
274 | { | |
275 | timer_over_8254 = 2; | |
276 | return 1; | |
277 | } | |
278 | ||
279 | __setup("disable_8254_timer", setup_disable_8254_timer); | |
280 | __setup("enable_8254_timer", setup_enable_8254_timer); | |
281 | ||
1da177e4 | 282 | |
1da177e4 LT |
283 | /* |
284 | * Find the IRQ entry number of a certain pin. | |
285 | */ | |
286 | static int find_irq_entry(int apic, int pin, int type) | |
287 | { | |
288 | int i; | |
289 | ||
290 | for (i = 0; i < mp_irq_entries; i++) | |
291 | if (mp_irqs[i].mpc_irqtype == type && | |
292 | (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid || | |
293 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) && | |
294 | mp_irqs[i].mpc_dstirq == pin) | |
295 | return i; | |
296 | ||
297 | return -1; | |
298 | } | |
299 | ||
300 | /* | |
301 | * Find the pin to which IRQ[irq] (ISA) is connected | |
302 | */ | |
1008fddc | 303 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
304 | { |
305 | int i; | |
306 | ||
307 | for (i = 0; i < mp_irq_entries; i++) { | |
308 | int lbus = mp_irqs[i].mpc_srcbus; | |
309 | ||
55f05ffa | 310 | if (test_bit(lbus, mp_bus_not_pci) && |
1da177e4 LT |
311 | (mp_irqs[i].mpc_irqtype == type) && |
312 | (mp_irqs[i].mpc_srcbusirq == irq)) | |
313 | ||
314 | return mp_irqs[i].mpc_dstirq; | |
315 | } | |
316 | return -1; | |
317 | } | |
318 | ||
1008fddc EB |
319 | static int __init find_isa_irq_apic(int irq, int type) |
320 | { | |
321 | int i; | |
322 | ||
323 | for (i = 0; i < mp_irq_entries; i++) { | |
324 | int lbus = mp_irqs[i].mpc_srcbus; | |
325 | ||
55f05ffa | 326 | if (test_bit(lbus, mp_bus_not_pci) && |
1008fddc EB |
327 | (mp_irqs[i].mpc_irqtype == type) && |
328 | (mp_irqs[i].mpc_srcbusirq == irq)) | |
329 | break; | |
330 | } | |
331 | if (i < mp_irq_entries) { | |
332 | int apic; | |
333 | for(apic = 0; apic < nr_ioapics; apic++) { | |
334 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic) | |
335 | return apic; | |
336 | } | |
337 | } | |
338 | ||
339 | return -1; | |
340 | } | |
341 | ||
1da177e4 LT |
342 | /* |
343 | * Find a specific PCI IRQ entry. | |
344 | * Not an __init, possibly needed by modules | |
345 | */ | |
346 | static int pin_2_irq(int idx, int apic, int pin); | |
347 | ||
348 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
349 | { | |
350 | int apic, i, best_guess = -1; | |
351 | ||
352 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
353 | bus, slot, pin); | |
354 | if (mp_bus_id_to_pci_bus[bus] == -1) { | |
355 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
356 | return -1; | |
357 | } | |
358 | for (i = 0; i < mp_irq_entries; i++) { | |
359 | int lbus = mp_irqs[i].mpc_srcbus; | |
360 | ||
361 | for (apic = 0; apic < nr_ioapics; apic++) | |
362 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic || | |
363 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) | |
364 | break; | |
365 | ||
55f05ffa | 366 | if (!test_bit(lbus, mp_bus_not_pci) && |
1da177e4 LT |
367 | !mp_irqs[i].mpc_irqtype && |
368 | (bus == lbus) && | |
369 | (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) { | |
370 | int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq); | |
371 | ||
372 | if (!(apic || IO_APIC_IRQ(irq))) | |
373 | continue; | |
374 | ||
375 | if (pin == (mp_irqs[i].mpc_srcbusirq & 3)) | |
376 | return irq; | |
377 | /* | |
378 | * Use the first all-but-pin matching entry as a | |
379 | * best-guess fuzzy result for broken mptables. | |
380 | */ | |
381 | if (best_guess < 0) | |
382 | best_guess = irq; | |
383 | } | |
384 | } | |
6004e1b7 | 385 | BUG_ON(best_guess >= NR_IRQS); |
1da177e4 LT |
386 | return best_guess; |
387 | } | |
388 | ||
1da177e4 LT |
389 | /* ISA interrupts are always polarity zero edge triggered, |
390 | * when listed as conforming in the MP table. */ | |
391 | ||
392 | #define default_ISA_trigger(idx) (0) | |
393 | #define default_ISA_polarity(idx) (0) | |
394 | ||
395 | /* PCI interrupts are always polarity one level triggered, | |
396 | * when listed as conforming in the MP table. */ | |
397 | ||
398 | #define default_PCI_trigger(idx) (1) | |
399 | #define default_PCI_polarity(idx) (1) | |
400 | ||
1da177e4 LT |
401 | static int __init MPBIOS_polarity(int idx) |
402 | { | |
403 | int bus = mp_irqs[idx].mpc_srcbus; | |
404 | int polarity; | |
405 | ||
406 | /* | |
407 | * Determine IRQ line polarity (high active or low active): | |
408 | */ | |
409 | switch (mp_irqs[idx].mpc_irqflag & 3) | |
410 | { | |
411 | case 0: /* conforms, ie. bus-type dependent polarity */ | |
55f05ffa AK |
412 | if (test_bit(bus, mp_bus_not_pci)) |
413 | polarity = default_ISA_polarity(idx); | |
414 | else | |
415 | polarity = default_PCI_polarity(idx); | |
1da177e4 | 416 | break; |
1da177e4 LT |
417 | case 1: /* high active */ |
418 | { | |
419 | polarity = 0; | |
420 | break; | |
421 | } | |
422 | case 2: /* reserved */ | |
423 | { | |
424 | printk(KERN_WARNING "broken BIOS!!\n"); | |
425 | polarity = 1; | |
426 | break; | |
427 | } | |
428 | case 3: /* low active */ | |
429 | { | |
430 | polarity = 1; | |
431 | break; | |
432 | } | |
433 | default: /* invalid */ | |
434 | { | |
435 | printk(KERN_WARNING "broken BIOS!!\n"); | |
436 | polarity = 1; | |
437 | break; | |
438 | } | |
439 | } | |
440 | return polarity; | |
441 | } | |
442 | ||
443 | static int MPBIOS_trigger(int idx) | |
444 | { | |
445 | int bus = mp_irqs[idx].mpc_srcbus; | |
446 | int trigger; | |
447 | ||
448 | /* | |
449 | * Determine IRQ trigger mode (edge or level sensitive): | |
450 | */ | |
451 | switch ((mp_irqs[idx].mpc_irqflag>>2) & 3) | |
452 | { | |
453 | case 0: /* conforms, ie. bus-type dependent */ | |
55f05ffa AK |
454 | if (test_bit(bus, mp_bus_not_pci)) |
455 | trigger = default_ISA_trigger(idx); | |
456 | else | |
457 | trigger = default_PCI_trigger(idx); | |
1da177e4 | 458 | break; |
1da177e4 LT |
459 | case 1: /* edge */ |
460 | { | |
461 | trigger = 0; | |
462 | break; | |
463 | } | |
464 | case 2: /* reserved */ | |
465 | { | |
466 | printk(KERN_WARNING "broken BIOS!!\n"); | |
467 | trigger = 1; | |
468 | break; | |
469 | } | |
470 | case 3: /* level */ | |
471 | { | |
472 | trigger = 1; | |
473 | break; | |
474 | } | |
475 | default: /* invalid */ | |
476 | { | |
477 | printk(KERN_WARNING "broken BIOS!!\n"); | |
478 | trigger = 0; | |
479 | break; | |
480 | } | |
481 | } | |
482 | return trigger; | |
483 | } | |
484 | ||
485 | static inline int irq_polarity(int idx) | |
486 | { | |
487 | return MPBIOS_polarity(idx); | |
488 | } | |
489 | ||
490 | static inline int irq_trigger(int idx) | |
491 | { | |
492 | return MPBIOS_trigger(idx); | |
493 | } | |
494 | ||
6004e1b7 JC |
495 | static int next_irq = 16; |
496 | ||
497 | /* | |
498 | * gsi_irq_sharing -- Name overload! "irq" can be either a legacy IRQ | |
499 | * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number | |
500 | * from ACPI, which can reach 800 in large boxen. | |
501 | * | |
502 | * Compact the sparse GSI space into a sequential IRQ series and reuse | |
503 | * vectors if possible. | |
504 | */ | |
505 | int gsi_irq_sharing(int gsi) | |
506 | { | |
507 | int i, tries, vector; | |
508 | ||
509 | BUG_ON(gsi >= NR_IRQ_VECTORS); | |
510 | ||
511 | if (platform_legacy_irq(gsi)) | |
512 | return gsi; | |
513 | ||
514 | if (gsi_2_irq[gsi] != 0xFF) | |
515 | return (int)gsi_2_irq[gsi]; | |
516 | ||
517 | tries = NR_IRQS; | |
518 | try_again: | |
519 | vector = assign_irq_vector(gsi); | |
520 | ||
521 | /* | |
522 | * Sharing vectors means sharing IRQs, so scan irq_vectors for previous | |
523 | * use of vector and if found, return that IRQ. However, we never want | |
524 | * to share legacy IRQs, which usually have a different trigger mode | |
525 | * than PCI. | |
526 | */ | |
527 | for (i = 0; i < NR_IRQS; i++) | |
528 | if (IO_APIC_VECTOR(i) == vector) | |
529 | break; | |
530 | if (platform_legacy_irq(i)) { | |
531 | if (--tries >= 0) { | |
532 | IO_APIC_VECTOR(i) = 0; | |
533 | goto try_again; | |
534 | } | |
535 | panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi); | |
536 | } | |
537 | if (i < NR_IRQS) { | |
538 | gsi_2_irq[gsi] = i; | |
539 | printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n", | |
540 | gsi, vector, i); | |
541 | return i; | |
542 | } | |
543 | ||
544 | i = next_irq++; | |
545 | BUG_ON(i >= NR_IRQS); | |
546 | gsi_2_irq[gsi] = i; | |
547 | IO_APIC_VECTOR(i) = vector; | |
548 | printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n", | |
549 | gsi, vector, i); | |
550 | return i; | |
551 | } | |
552 | ||
1da177e4 LT |
553 | static int pin_2_irq(int idx, int apic, int pin) |
554 | { | |
555 | int irq, i; | |
556 | int bus = mp_irqs[idx].mpc_srcbus; | |
557 | ||
558 | /* | |
559 | * Debugging check, we are in big trouble if this message pops up! | |
560 | */ | |
561 | if (mp_irqs[idx].mpc_dstirq != pin) | |
562 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); | |
563 | ||
55f05ffa AK |
564 | if (test_bit(bus, mp_bus_not_pci)) { |
565 | irq = mp_irqs[idx].mpc_srcbusirq; | |
566 | } else { | |
567 | /* | |
568 | * PCI IRQs are mapped in order | |
569 | */ | |
570 | i = irq = 0; | |
571 | while (i < apic) | |
572 | irq += nr_ioapic_registers[i++]; | |
573 | irq += pin; | |
574 | irq = gsi_irq_sharing(irq); | |
1da177e4 | 575 | } |
6004e1b7 | 576 | BUG_ON(irq >= NR_IRQS); |
1da177e4 LT |
577 | return irq; |
578 | } | |
579 | ||
580 | static inline int IO_APIC_irq_trigger(int irq) | |
581 | { | |
582 | int apic, idx, pin; | |
583 | ||
584 | for (apic = 0; apic < nr_ioapics; apic++) { | |
585 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
586 | idx = find_irq_entry(apic,pin,mp_INT); | |
587 | if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin))) | |
588 | return irq_trigger(idx); | |
589 | } | |
590 | } | |
591 | /* | |
592 | * nonexistent IRQs are edge default | |
593 | */ | |
594 | return 0; | |
595 | } | |
596 | ||
597 | /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */ | |
6c231b7b | 598 | u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 }; |
1da177e4 LT |
599 | |
600 | int assign_irq_vector(int irq) | |
601 | { | |
602 | static int current_vector = FIRST_DEVICE_VECTOR, offset = 0; | |
26a3c49c | 603 | unsigned long flags; |
0a1ad60d | 604 | int vector; |
1da177e4 | 605 | |
6004e1b7 | 606 | BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS); |
0a1ad60d | 607 | |
26a3c49c | 608 | spin_lock_irqsave(&vector_lock, flags); |
0a1ad60d JB |
609 | |
610 | if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) { | |
26a3c49c | 611 | spin_unlock_irqrestore(&vector_lock, flags); |
1da177e4 | 612 | return IO_APIC_VECTOR(irq); |
0a1ad60d | 613 | } |
1da177e4 LT |
614 | next: |
615 | current_vector += 8; | |
616 | if (current_vector == IA32_SYSCALL_VECTOR) | |
617 | goto next; | |
618 | ||
619 | if (current_vector >= FIRST_SYSTEM_VECTOR) { | |
6004e1b7 JC |
620 | /* If we run out of vectors on large boxen, must share them. */ |
621 | offset = (offset + 1) % 8; | |
1da177e4 LT |
622 | current_vector = FIRST_DEVICE_VECTOR + offset; |
623 | } | |
624 | ||
0a1ad60d JB |
625 | vector = current_vector; |
626 | vector_irq[vector] = irq; | |
1da177e4 | 627 | if (irq != AUTO_ASSIGN) |
0a1ad60d JB |
628 | IO_APIC_VECTOR(irq) = vector; |
629 | ||
26a3c49c | 630 | spin_unlock_irqrestore(&vector_lock, flags); |
1da177e4 | 631 | |
0a1ad60d | 632 | return vector; |
1da177e4 LT |
633 | } |
634 | ||
635 | extern void (*interrupt[NR_IRQS])(void); | |
f29bd1ba IM |
636 | |
637 | static struct irq_chip ioapic_chip; | |
1da177e4 LT |
638 | |
639 | #define IOAPIC_AUTO -1 | |
640 | #define IOAPIC_EDGE 0 | |
641 | #define IOAPIC_LEVEL 1 | |
642 | ||
d1bef4ed | 643 | static void ioapic_register_intr(int irq, int vector, unsigned long trigger) |
1da177e4 | 644 | { |
d1bef4ed IM |
645 | unsigned idx; |
646 | ||
647 | idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq; | |
6ebcc00e JB |
648 | |
649 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || | |
650 | trigger == IOAPIC_LEVEL) | |
f29bd1ba IM |
651 | set_irq_chip_and_handler(idx, &ioapic_chip, |
652 | handle_fasteoi_irq); | |
6ebcc00e | 653 | else |
f29bd1ba IM |
654 | set_irq_chip_and_handler(idx, &ioapic_chip, |
655 | handle_edge_irq); | |
6ebcc00e | 656 | set_intr_gate(vector, interrupt[idx]); |
1da177e4 LT |
657 | } |
658 | ||
659 | static void __init setup_IO_APIC_irqs(void) | |
660 | { | |
661 | struct IO_APIC_route_entry entry; | |
662 | int apic, pin, idx, irq, first_notcon = 1, vector; | |
663 | unsigned long flags; | |
664 | ||
665 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
666 | ||
667 | for (apic = 0; apic < nr_ioapics; apic++) { | |
668 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
669 | ||
670 | /* | |
671 | * add it to the IO-APIC irq-routing table: | |
672 | */ | |
673 | memset(&entry,0,sizeof(entry)); | |
674 | ||
675 | entry.delivery_mode = INT_DELIVERY_MODE; | |
676 | entry.dest_mode = INT_DEST_MODE; | |
677 | entry.mask = 0; /* enable IRQ */ | |
678 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
679 | ||
680 | idx = find_irq_entry(apic,pin,mp_INT); | |
681 | if (idx == -1) { | |
682 | if (first_notcon) { | |
683 | apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin); | |
684 | first_notcon = 0; | |
685 | } else | |
686 | apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin); | |
687 | continue; | |
688 | } | |
689 | ||
690 | entry.trigger = irq_trigger(idx); | |
691 | entry.polarity = irq_polarity(idx); | |
692 | ||
693 | if (irq_trigger(idx)) { | |
694 | entry.trigger = 1; | |
695 | entry.mask = 1; | |
696 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
697 | } | |
698 | ||
699 | irq = pin_2_irq(idx, apic, pin); | |
700 | add_pin_to_irq(irq, apic, pin); | |
701 | ||
702 | if (!apic && !IO_APIC_IRQ(irq)) | |
703 | continue; | |
704 | ||
705 | if (IO_APIC_IRQ(irq)) { | |
706 | vector = assign_irq_vector(irq); | |
707 | entry.vector = vector; | |
708 | ||
709 | ioapic_register_intr(irq, vector, IOAPIC_AUTO); | |
710 | if (!apic && (irq < 16)) | |
711 | disable_8259A_irq(irq); | |
712 | } | |
eea0e11c AK |
713 | ioapic_write_entry(apic, pin, entry); |
714 | ||
1da177e4 | 715 | spin_lock_irqsave(&ioapic_lock, flags); |
54d5d424 | 716 | set_native_irq_info(irq, TARGET_CPUS); |
1da177e4 LT |
717 | spin_unlock_irqrestore(&ioapic_lock, flags); |
718 | } | |
719 | } | |
720 | ||
721 | if (!first_notcon) | |
722 | apic_printk(APIC_VERBOSE," not connected.\n"); | |
723 | } | |
724 | ||
725 | /* | |
726 | * Set up the 8259A-master output pin as broadcast to all | |
727 | * CPUs. | |
728 | */ | |
1008fddc | 729 | static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector) |
1da177e4 LT |
730 | { |
731 | struct IO_APIC_route_entry entry; | |
732 | unsigned long flags; | |
733 | ||
734 | memset(&entry,0,sizeof(entry)); | |
735 | ||
736 | disable_8259A_irq(0); | |
737 | ||
738 | /* mask LVT0 */ | |
11a8e778 | 739 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 LT |
740 | |
741 | /* | |
742 | * We use logical delivery to get the timer IRQ | |
743 | * to the first CPU. | |
744 | */ | |
745 | entry.dest_mode = INT_DEST_MODE; | |
746 | entry.mask = 0; /* unmask IRQ now */ | |
747 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
748 | entry.delivery_mode = INT_DELIVERY_MODE; | |
749 | entry.polarity = 0; | |
750 | entry.trigger = 0; | |
751 | entry.vector = vector; | |
752 | ||
753 | /* | |
754 | * The timer IRQ doesn't have to know that behind the | |
755 | * scene we have a 8259A-master in AEOI mode ... | |
756 | */ | |
f29bd1ba | 757 | set_irq_chip_and_handler(0, &ioapic_chip, handle_edge_irq); |
1da177e4 LT |
758 | |
759 | /* | |
760 | * Add it to the IO-APIC irq-routing table: | |
761 | */ | |
762 | spin_lock_irqsave(&ioapic_lock, flags); | |
1008fddc EB |
763 | io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1)); |
764 | io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0)); | |
1da177e4 LT |
765 | spin_unlock_irqrestore(&ioapic_lock, flags); |
766 | ||
767 | enable_8259A_irq(0); | |
768 | } | |
769 | ||
770 | void __init UNEXPECTED_IO_APIC(void) | |
771 | { | |
772 | } | |
773 | ||
774 | void __apicdebuginit print_IO_APIC(void) | |
775 | { | |
776 | int apic, i; | |
777 | union IO_APIC_reg_00 reg_00; | |
778 | union IO_APIC_reg_01 reg_01; | |
779 | union IO_APIC_reg_02 reg_02; | |
780 | unsigned long flags; | |
781 | ||
782 | if (apic_verbosity == APIC_QUIET) | |
783 | return; | |
784 | ||
785 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
786 | for (i = 0; i < nr_ioapics; i++) | |
787 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
788 | mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]); | |
789 | ||
790 | /* | |
791 | * We are a bit conservative about what we expect. We have to | |
792 | * know about every hardware change ASAP. | |
793 | */ | |
794 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
795 | ||
796 | for (apic = 0; apic < nr_ioapics; apic++) { | |
797 | ||
798 | spin_lock_irqsave(&ioapic_lock, flags); | |
799 | reg_00.raw = io_apic_read(apic, 0); | |
800 | reg_01.raw = io_apic_read(apic, 1); | |
801 | if (reg_01.bits.version >= 0x10) | |
802 | reg_02.raw = io_apic_read(apic, 2); | |
803 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
804 | ||
805 | printk("\n"); | |
806 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid); | |
807 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); | |
808 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
809 | if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2) | |
810 | UNEXPECTED_IO_APIC(); | |
811 | ||
812 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); | |
813 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); | |
814 | if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */ | |
815 | (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */ | |
816 | (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */ | |
817 | (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */ | |
818 | (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */ | |
819 | (reg_01.bits.entries != 0x2E) && | |
820 | (reg_01.bits.entries != 0x3F) && | |
821 | (reg_01.bits.entries != 0x03) | |
822 | ) | |
823 | UNEXPECTED_IO_APIC(); | |
824 | ||
825 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
826 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
827 | if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */ | |
828 | (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */ | |
829 | (reg_01.bits.version != 0x10) && /* oldest IO-APICs */ | |
830 | (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */ | |
831 | (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */ | |
832 | (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */ | |
833 | ) | |
834 | UNEXPECTED_IO_APIC(); | |
835 | if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2) | |
836 | UNEXPECTED_IO_APIC(); | |
837 | ||
838 | if (reg_01.bits.version >= 0x10) { | |
839 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
840 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
841 | if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2) | |
842 | UNEXPECTED_IO_APIC(); | |
843 | } | |
844 | ||
845 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
846 | ||
847 | printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol" | |
848 | " Stat Dest Deli Vect: \n"); | |
849 | ||
850 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
851 | struct IO_APIC_route_entry entry; | |
852 | ||
eea0e11c | 853 | entry = ioapic_read_entry(apic, i); |
1da177e4 LT |
854 | |
855 | printk(KERN_DEBUG " %02x %03X %02X ", | |
856 | i, | |
857 | entry.dest.logical.logical_dest, | |
858 | entry.dest.physical.physical_dest | |
859 | ); | |
860 | ||
861 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
862 | entry.mask, | |
863 | entry.trigger, | |
864 | entry.irr, | |
865 | entry.polarity, | |
866 | entry.delivery_status, | |
867 | entry.dest_mode, | |
868 | entry.delivery_mode, | |
869 | entry.vector | |
870 | ); | |
871 | } | |
872 | } | |
873 | if (use_pci_vector()) | |
874 | printk(KERN_INFO "Using vector-based indexing\n"); | |
875 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); | |
876 | for (i = 0; i < NR_IRQS; i++) { | |
877 | struct irq_pin_list *entry = irq_2_pin + i; | |
878 | if (entry->pin < 0) | |
879 | continue; | |
880 | if (use_pci_vector() && !platform_legacy_irq(i)) | |
881 | printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i)); | |
882 | else | |
883 | printk(KERN_DEBUG "IRQ%d ", i); | |
884 | for (;;) { | |
885 | printk("-> %d:%d", entry->apic, entry->pin); | |
886 | if (!entry->next) | |
887 | break; | |
888 | entry = irq_2_pin + entry->next; | |
889 | } | |
890 | printk("\n"); | |
891 | } | |
892 | ||
893 | printk(KERN_INFO ".................................... done.\n"); | |
894 | ||
895 | return; | |
896 | } | |
897 | ||
898 | #if 0 | |
899 | ||
900 | static __apicdebuginit void print_APIC_bitfield (int base) | |
901 | { | |
902 | unsigned int v; | |
903 | int i, j; | |
904 | ||
905 | if (apic_verbosity == APIC_QUIET) | |
906 | return; | |
907 | ||
908 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
909 | for (i = 0; i < 8; i++) { | |
910 | v = apic_read(base + i*0x10); | |
911 | for (j = 0; j < 32; j++) { | |
912 | if (v & (1<<j)) | |
913 | printk("1"); | |
914 | else | |
915 | printk("0"); | |
916 | } | |
917 | printk("\n"); | |
918 | } | |
919 | } | |
920 | ||
921 | void __apicdebuginit print_local_APIC(void * dummy) | |
922 | { | |
923 | unsigned int v, ver, maxlvt; | |
924 | ||
925 | if (apic_verbosity == APIC_QUIET) | |
926 | return; | |
927 | ||
928 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
929 | smp_processor_id(), hard_smp_processor_id()); | |
930 | v = apic_read(APIC_ID); | |
931 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v)); | |
932 | v = apic_read(APIC_LVR); | |
933 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
934 | ver = GET_APIC_VERSION(v); | |
935 | maxlvt = get_maxlvt(); | |
936 | ||
937 | v = apic_read(APIC_TASKPRI); | |
938 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
939 | ||
5a40b7c2 AK |
940 | v = apic_read(APIC_ARBPRI); |
941 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
942 | v & APIC_ARBPRI_MASK); | |
943 | v = apic_read(APIC_PROCPRI); | |
944 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1da177e4 LT |
945 | |
946 | v = apic_read(APIC_EOI); | |
947 | printk(KERN_DEBUG "... APIC EOI: %08x\n", v); | |
948 | v = apic_read(APIC_RRR); | |
949 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
950 | v = apic_read(APIC_LDR); | |
951 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
952 | v = apic_read(APIC_DFR); | |
953 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
954 | v = apic_read(APIC_SPIV); | |
955 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
956 | ||
957 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
958 | print_APIC_bitfield(APIC_ISR); | |
959 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
960 | print_APIC_bitfield(APIC_TMR); | |
961 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
962 | print_APIC_bitfield(APIC_IRR); | |
963 | ||
5a40b7c2 AK |
964 | v = apic_read(APIC_ESR); |
965 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1da177e4 LT |
966 | |
967 | v = apic_read(APIC_ICR); | |
968 | printk(KERN_DEBUG "... APIC ICR: %08x\n", v); | |
969 | v = apic_read(APIC_ICR2); | |
970 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", v); | |
971 | ||
972 | v = apic_read(APIC_LVTT); | |
973 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
974 | ||
975 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
976 | v = apic_read(APIC_LVTPC); | |
977 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
978 | } | |
979 | v = apic_read(APIC_LVT0); | |
980 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
981 | v = apic_read(APIC_LVT1); | |
982 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
983 | ||
984 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
985 | v = apic_read(APIC_LVTERR); | |
986 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
987 | } | |
988 | ||
989 | v = apic_read(APIC_TMICT); | |
990 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
991 | v = apic_read(APIC_TMCCT); | |
992 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
993 | v = apic_read(APIC_TDCR); | |
994 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
995 | printk("\n"); | |
996 | } | |
997 | ||
998 | void print_all_local_APICs (void) | |
999 | { | |
1000 | on_each_cpu(print_local_APIC, NULL, 1, 1); | |
1001 | } | |
1002 | ||
1003 | void __apicdebuginit print_PIC(void) | |
1004 | { | |
1da177e4 LT |
1005 | unsigned int v; |
1006 | unsigned long flags; | |
1007 | ||
1008 | if (apic_verbosity == APIC_QUIET) | |
1009 | return; | |
1010 | ||
1011 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1012 | ||
1013 | spin_lock_irqsave(&i8259A_lock, flags); | |
1014 | ||
1015 | v = inb(0xa1) << 8 | inb(0x21); | |
1016 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1017 | ||
1018 | v = inb(0xa0) << 8 | inb(0x20); | |
1019 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1020 | ||
1021 | outb(0x0b,0xa0); | |
1022 | outb(0x0b,0x20); | |
1023 | v = inb(0xa0) << 8 | inb(0x20); | |
1024 | outb(0x0a,0xa0); | |
1025 | outb(0x0a,0x20); | |
1026 | ||
1027 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1028 | ||
1029 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1030 | ||
1031 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1032 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1033 | } | |
1034 | ||
1035 | #endif /* 0 */ | |
1036 | ||
1037 | static void __init enable_IO_APIC(void) | |
1038 | { | |
1039 | union IO_APIC_reg_01 reg_01; | |
1008fddc EB |
1040 | int i8259_apic, i8259_pin; |
1041 | int i, apic; | |
1da177e4 LT |
1042 | unsigned long flags; |
1043 | ||
1044 | for (i = 0; i < PIN_MAP_SIZE; i++) { | |
1045 | irq_2_pin[i].pin = -1; | |
1046 | irq_2_pin[i].next = 0; | |
1047 | } | |
1da177e4 LT |
1048 | |
1049 | /* | |
1050 | * The number of IO-APIC IRQ registers (== #pins): | |
1051 | */ | |
1008fddc | 1052 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1053 | spin_lock_irqsave(&ioapic_lock, flags); |
1008fddc | 1054 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1055 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1008fddc EB |
1056 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1057 | } | |
1058 | for(apic = 0; apic < nr_ioapics; apic++) { | |
1059 | int pin; | |
1060 | /* See if any of the pins is in ExtINT mode */ | |
1061 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1062 | struct IO_APIC_route_entry entry; | |
eea0e11c | 1063 | entry = ioapic_read_entry(apic, pin); |
1008fddc EB |
1064 | |
1065 | /* If the interrupt line is enabled and in ExtInt mode | |
1066 | * I have found the pin where the i8259 is connected. | |
1067 | */ | |
1068 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1069 | ioapic_i8259.apic = apic; | |
1070 | ioapic_i8259.pin = pin; | |
1071 | goto found_i8259; | |
1072 | } | |
1073 | } | |
1074 | } | |
1075 | found_i8259: | |
1076 | /* Look to see what if the MP table has reported the ExtINT */ | |
1077 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1078 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1079 | /* Trust the MP table if nothing is setup in the hardware */ | |
1080 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1081 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1082 | ioapic_i8259.pin = i8259_pin; | |
1083 | ioapic_i8259.apic = i8259_apic; | |
1084 | } | |
1085 | /* Complain if the MP table and the hardware disagree */ | |
1086 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1087 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1088 | { | |
1089 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1090 | } |
1091 | ||
1092 | /* | |
1093 | * Do not trust the IO-APIC being empty at bootup | |
1094 | */ | |
1095 | clear_IO_APIC(); | |
1096 | } | |
1097 | ||
1098 | /* | |
1099 | * Not an __init, needed by the reboot code | |
1100 | */ | |
1101 | void disable_IO_APIC(void) | |
1102 | { | |
1103 | /* | |
1104 | * Clear the IO-APIC before rebooting: | |
1105 | */ | |
1106 | clear_IO_APIC(); | |
1107 | ||
208fb931 | 1108 | /* |
0b968d23 | 1109 | * If the i8259 is routed through an IOAPIC |
208fb931 | 1110 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1111 | * so legacy interrupts can be delivered. |
208fb931 | 1112 | */ |
1008fddc | 1113 | if (ioapic_i8259.pin != -1) { |
208fb931 | 1114 | struct IO_APIC_route_entry entry; |
208fb931 EB |
1115 | |
1116 | memset(&entry, 0, sizeof(entry)); | |
1117 | entry.mask = 0; /* Enabled */ | |
1118 | entry.trigger = 0; /* Edge */ | |
1119 | entry.irr = 0; | |
1120 | entry.polarity = 0; /* High */ | |
1121 | entry.delivery_status = 0; | |
1122 | entry.dest_mode = 0; /* Physical */ | |
1008fddc | 1123 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
208fb931 | 1124 | entry.vector = 0; |
af5b9804 VG |
1125 | entry.dest.physical.physical_dest = |
1126 | GET_APIC_ID(apic_read(APIC_ID)); | |
208fb931 | 1127 | |
208fb931 EB |
1128 | /* |
1129 | * Add it to the IO-APIC irq-routing table: | |
1130 | */ | |
eea0e11c | 1131 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
208fb931 EB |
1132 | } |
1133 | ||
1008fddc | 1134 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
1135 | } |
1136 | ||
1da177e4 LT |
1137 | /* |
1138 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1139 | * about the timer IRQ. We do the following to work around the situation: | |
1140 | * | |
1141 | * - timer IRQ defaults to IO-APIC IRQ | |
1142 | * - if this function detects that timer IRQs are defunct, then we fall | |
1143 | * back to ISA timer IRQs | |
1144 | */ | |
1145 | static int __init timer_irq_works(void) | |
1146 | { | |
1147 | unsigned long t1 = jiffies; | |
1148 | ||
1149 | local_irq_enable(); | |
1150 | /* Let ten ticks pass... */ | |
1151 | mdelay((10 * 1000) / HZ); | |
1152 | ||
1153 | /* | |
1154 | * Expect a few ticks at least, to be sure some possible | |
1155 | * glue logic does not lock up after one or two first | |
1156 | * ticks in a non-ExtINT mode. Also the local APIC | |
1157 | * might have cached one ExtINT interrupt. Finally, at | |
1158 | * least one tick may be lost due to delays. | |
1159 | */ | |
1160 | ||
1161 | /* jiffies wrap? */ | |
1162 | if (jiffies - t1 > 4) | |
1163 | return 1; | |
1164 | return 0; | |
1165 | } | |
1166 | ||
1167 | /* | |
1168 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1169 | * number of pending IRQ events unhandled. These cases are very rare, | |
1170 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1171 | * better to do it this way as thus we do not have to be aware of | |
1172 | * 'pending' interrupts in the IRQ path, except at this point. | |
1173 | */ | |
1174 | /* | |
1175 | * Edge triggered needs to resend any interrupt | |
1176 | * that was delayed but this is now handled in the device | |
1177 | * independent code. | |
1178 | */ | |
1179 | ||
1180 | /* | |
1181 | * Starting up a edge-triggered IO-APIC interrupt is | |
1182 | * nasty - we need to make sure that we get the edge. | |
1183 | * If it is already asserted for some reason, we need | |
1184 | * return 1 to indicate that is was pending. | |
1185 | * | |
1186 | * This is not complete - we should be able to fake | |
1187 | * an edge even if it isn't on the 8259A... | |
1188 | */ | |
1189 | ||
f29bd1ba | 1190 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
1191 | { |
1192 | int was_pending = 0; | |
1193 | unsigned long flags; | |
1194 | ||
1195 | spin_lock_irqsave(&ioapic_lock, flags); | |
1196 | if (irq < 16) { | |
1197 | disable_8259A_irq(irq); | |
1198 | if (i8259A_irq_pending(irq)) | |
1199 | was_pending = 1; | |
1200 | } | |
1201 | __unmask_IO_APIC_irq(irq); | |
1202 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1203 | ||
1204 | return was_pending; | |
1205 | } | |
1206 | ||
f29bd1ba | 1207 | static unsigned int startup_ioapic_vector(unsigned int vector) |
1da177e4 LT |
1208 | { |
1209 | int irq = vector_to_irq(vector); | |
1210 | ||
f29bd1ba | 1211 | return startup_ioapic_irq(irq); |
1da177e4 LT |
1212 | } |
1213 | ||
f29bd1ba | 1214 | static void mask_ioapic_vector (unsigned int vector) |
1da177e4 LT |
1215 | { |
1216 | int irq = vector_to_irq(vector); | |
1217 | ||
1218 | mask_IO_APIC_irq(irq); | |
1219 | } | |
1220 | ||
f29bd1ba | 1221 | static void unmask_ioapic_vector (unsigned int vector) |
1da177e4 LT |
1222 | { |
1223 | int irq = vector_to_irq(vector); | |
1224 | ||
1225 | unmask_IO_APIC_irq(irq); | |
1226 | } | |
1227 | ||
54d5d424 | 1228 | #ifdef CONFIG_SMP |
1da177e4 LT |
1229 | static void set_ioapic_affinity_vector (unsigned int vector, |
1230 | cpumask_t cpu_mask) | |
1231 | { | |
1232 | int irq = vector_to_irq(vector); | |
1233 | ||
54d5d424 | 1234 | set_native_irq_info(vector, cpu_mask); |
1da177e4 LT |
1235 | set_ioapic_affinity_irq(irq, cpu_mask); |
1236 | } | |
54d5d424 | 1237 | #endif // CONFIG_SMP |
1da177e4 | 1238 | |
f29bd1ba | 1239 | static int ioapic_retrigger_vector(unsigned int vector) |
c0ad90a3 | 1240 | { |
f29bd1ba IM |
1241 | int irq = vector_to_irq(vector); |
1242 | ||
c0ad90a3 IM |
1243 | send_IPI_self(IO_APIC_VECTOR(irq)); |
1244 | ||
1245 | return 1; | |
1246 | } | |
1247 | ||
1da177e4 LT |
1248 | /* |
1249 | * Level and edge triggered IO-APIC interrupts need different handling, | |
1250 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
1251 | * handled with the level-triggered descriptor, but that one has slightly | |
1252 | * more overhead. Level-triggered interrupts cannot be handled with the | |
1253 | * edge-triggered handler, without risking IRQ storms and other ugly | |
1254 | * races. | |
1255 | */ | |
1256 | ||
0be6652f EB |
1257 | static void ack_apic_edge(unsigned int irq) |
1258 | { | |
1259 | move_native_irq(irq); | |
1260 | ack_APIC_irq(); | |
1261 | } | |
1262 | ||
1263 | static void ack_apic_level(unsigned int irq) | |
1264 | { | |
1265 | int do_unmask_irq = 0; | |
1266 | ||
1267 | #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE) | |
1268 | /* If we are moving the irq we need to mask it */ | |
1269 | if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) { | |
1270 | do_unmask_irq = 1; | |
1271 | mask_IO_APIC_irq(irq); | |
1272 | } | |
1273 | #endif | |
1274 | ||
1275 | /* | |
1276 | * We must acknowledge the irq before we move it or the acknowledge will | |
1277 | * not propogate properly. | |
1278 | */ | |
1279 | ack_APIC_irq(); | |
1280 | ||
1281 | /* Now we can move and renable the irq */ | |
1282 | move_masked_irq(irq); | |
1283 | if (unlikely(do_unmask_irq)) | |
1284 | unmask_IO_APIC_irq(irq); | |
1285 | } | |
1286 | ||
f29bd1ba IM |
1287 | static struct irq_chip ioapic_chip __read_mostly = { |
1288 | .name = "IO-APIC", | |
1289 | .startup = startup_ioapic_vector, | |
1290 | .mask = mask_ioapic_vector, | |
1291 | .unmask = unmask_ioapic_vector, | |
0be6652f EB |
1292 | .ack = ack_apic_edge, |
1293 | .eoi = ack_apic_level, | |
54d5d424 | 1294 | #ifdef CONFIG_SMP |
f29bd1ba | 1295 | .set_affinity = set_ioapic_affinity_vector, |
54d5d424 | 1296 | #endif |
f29bd1ba | 1297 | .retrigger = ioapic_retrigger_vector, |
1da177e4 LT |
1298 | }; |
1299 | ||
1300 | static inline void init_IO_APIC_traps(void) | |
1301 | { | |
1302 | int irq; | |
1303 | ||
1304 | /* | |
1305 | * NOTE! The local APIC isn't very good at handling | |
1306 | * multiple interrupts at the same interrupt level. | |
1307 | * As the interrupt level is determined by taking the | |
1308 | * vector number and shifting that right by 4, we | |
1309 | * want to spread these out a bit so that they don't | |
1310 | * all fall in the same interrupt level. | |
1311 | * | |
1312 | * Also, we've got to be careful not to trash gate | |
1313 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1314 | */ | |
1315 | for (irq = 0; irq < NR_IRQS ; irq++) { | |
1316 | int tmp = irq; | |
1317 | if (use_pci_vector()) { | |
1318 | if (!platform_legacy_irq(tmp)) | |
1319 | if ((tmp = vector_to_irq(tmp)) == -1) | |
1320 | continue; | |
1321 | } | |
1322 | if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) { | |
1323 | /* | |
1324 | * Hmm.. We don't have an entry for this, | |
1325 | * so default to an old-fashioned 8259 | |
1326 | * interrupt if we can.. | |
1327 | */ | |
1328 | if (irq < 16) | |
1329 | make_8259A_irq(irq); | |
1330 | else | |
1331 | /* Strange. Oh, well.. */ | |
f29bd1ba | 1332 | irq_desc[irq].chip = &no_irq_chip; |
1da177e4 LT |
1333 | } |
1334 | } | |
1335 | } | |
1336 | ||
1337 | static void enable_lapic_irq (unsigned int irq) | |
1338 | { | |
1339 | unsigned long v; | |
1340 | ||
1341 | v = apic_read(APIC_LVT0); | |
11a8e778 | 1342 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
1da177e4 LT |
1343 | } |
1344 | ||
1345 | static void disable_lapic_irq (unsigned int irq) | |
1346 | { | |
1347 | unsigned long v; | |
1348 | ||
1349 | v = apic_read(APIC_LVT0); | |
11a8e778 | 1350 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
1351 | } |
1352 | ||
1353 | static void ack_lapic_irq (unsigned int irq) | |
1354 | { | |
1355 | ack_APIC_irq(); | |
1356 | } | |
1357 | ||
1358 | static void end_lapic_irq (unsigned int i) { /* nothing */ } | |
1359 | ||
6c231b7b | 1360 | static struct hw_interrupt_type lapic_irq_type __read_mostly = { |
1da177e4 LT |
1361 | .typename = "local-APIC-edge", |
1362 | .startup = NULL, /* startup_irq() not used for IRQ0 */ | |
1363 | .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */ | |
1364 | .enable = enable_lapic_irq, | |
1365 | .disable = disable_lapic_irq, | |
1366 | .ack = ack_lapic_irq, | |
1367 | .end = end_lapic_irq, | |
1368 | }; | |
1369 | ||
1370 | static void setup_nmi (void) | |
1371 | { | |
1372 | /* | |
1373 | * Dirty trick to enable the NMI watchdog ... | |
1374 | * We put the 8259A master into AEOI mode and | |
1375 | * unmask on all local APICs LVT0 as NMI. | |
1376 | * | |
1377 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
1378 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
1379 | * the NMI handler or the timer interrupt. | |
1380 | */ | |
1381 | printk(KERN_INFO "activating NMI Watchdog ..."); | |
1382 | ||
1383 | enable_NMI_through_LVT0(NULL); | |
1384 | ||
1385 | printk(" done.\n"); | |
1386 | } | |
1387 | ||
1388 | /* | |
1389 | * This looks a bit hackish but it's about the only one way of sending | |
1390 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
1391 | * not support the ExtINT mode, unfortunately. We need to send these | |
1392 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
1393 | * 8259A interrupt line asserted until INTA. --macro | |
1394 | */ | |
1395 | static inline void unlock_ExtINT_logic(void) | |
1396 | { | |
1008fddc | 1397 | int apic, pin, i; |
1da177e4 LT |
1398 | struct IO_APIC_route_entry entry0, entry1; |
1399 | unsigned char save_control, save_freq_select; | |
1400 | unsigned long flags; | |
1401 | ||
1008fddc EB |
1402 | pin = find_isa_irq_pin(8, mp_INT); |
1403 | apic = find_isa_irq_apic(8, mp_INT); | |
1da177e4 LT |
1404 | if (pin == -1) |
1405 | return; | |
1406 | ||
1407 | spin_lock_irqsave(&ioapic_lock, flags); | |
1008fddc EB |
1408 | *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin); |
1409 | *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin); | |
1da177e4 | 1410 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1008fddc | 1411 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
1412 | |
1413 | memset(&entry1, 0, sizeof(entry1)); | |
1414 | ||
1415 | entry1.dest_mode = 0; /* physical delivery */ | |
1416 | entry1.mask = 0; /* unmask IRQ now */ | |
1417 | entry1.dest.physical.physical_dest = hard_smp_processor_id(); | |
1418 | entry1.delivery_mode = dest_ExtINT; | |
1419 | entry1.polarity = entry0.polarity; | |
1420 | entry1.trigger = 0; | |
1421 | entry1.vector = 0; | |
1422 | ||
1423 | spin_lock_irqsave(&ioapic_lock, flags); | |
1008fddc EB |
1424 | io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1)); |
1425 | io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0)); | |
1da177e4 LT |
1426 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1427 | ||
1428 | save_control = CMOS_READ(RTC_CONTROL); | |
1429 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
1430 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
1431 | RTC_FREQ_SELECT); | |
1432 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
1433 | ||
1434 | i = 100; | |
1435 | while (i-- > 0) { | |
1436 | mdelay(10); | |
1437 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
1438 | i -= 10; | |
1439 | } | |
1440 | ||
1441 | CMOS_WRITE(save_control, RTC_CONTROL); | |
1442 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
1008fddc | 1443 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
1444 | |
1445 | spin_lock_irqsave(&ioapic_lock, flags); | |
1008fddc EB |
1446 | io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1)); |
1447 | io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0)); | |
1da177e4 LT |
1448 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1449 | } | |
1450 | ||
e0c1e9bf KM |
1451 | int timer_uses_ioapic_pin_0; |
1452 | ||
1da177e4 LT |
1453 | /* |
1454 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
1455 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
1456 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
1457 | * fanatically on his truly buggy board. | |
ab9b32ee AK |
1458 | * |
1459 | * FIXME: really need to revamp this for modern platforms only. | |
1da177e4 LT |
1460 | */ |
1461 | static inline void check_timer(void) | |
1462 | { | |
1008fddc | 1463 | int apic1, pin1, apic2, pin2; |
1da177e4 LT |
1464 | int vector; |
1465 | ||
1466 | /* | |
1467 | * get/set the timer IRQ vector: | |
1468 | */ | |
1469 | disable_8259A_irq(0); | |
1470 | vector = assign_irq_vector(0); | |
1471 | set_intr_gate(vector, interrupt[0]); | |
1472 | ||
1473 | /* | |
1474 | * Subtle, code in do_timer_interrupt() expects an AEOI | |
1475 | * mode for the 8259A whenever interrupts are routed | |
1476 | * through I/O APICs. Also IRQ0 has to be enabled in | |
1477 | * the 8259A which implies the virtual wire has to be | |
1478 | * disabled in the local APIC. | |
1479 | */ | |
11a8e778 | 1480 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 1481 | init_8259A(1); |
ab9b32ee AK |
1482 | if (timer_over_8254 > 0) |
1483 | enable_8259A_irq(0); | |
1da177e4 | 1484 | |
1008fddc EB |
1485 | pin1 = find_isa_irq_pin(0, mp_INT); |
1486 | apic1 = find_isa_irq_apic(0, mp_INT); | |
1487 | pin2 = ioapic_i8259.pin; | |
1488 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 1489 | |
e0c1e9bf KM |
1490 | if (pin1 == 0) |
1491 | timer_uses_ioapic_pin_0 = 1; | |
1492 | ||
1008fddc EB |
1493 | apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n", |
1494 | vector, apic1, pin1, apic2, pin2); | |
1da177e4 LT |
1495 | |
1496 | if (pin1 != -1) { | |
1497 | /* | |
1498 | * Ok, does IRQ0 through the IOAPIC work? | |
1499 | */ | |
1500 | unmask_IO_APIC_irq(0); | |
14d98cad | 1501 | if (!no_timer_check && timer_irq_works()) { |
1da177e4 LT |
1502 | nmi_watchdog_default(); |
1503 | if (nmi_watchdog == NMI_IO_APIC) { | |
1504 | disable_8259A_irq(0); | |
1505 | setup_nmi(); | |
1506 | enable_8259A_irq(0); | |
1da177e4 | 1507 | } |
66759a01 CE |
1508 | if (disable_timer_pin_1 > 0) |
1509 | clear_IO_APIC_pin(0, pin1); | |
1da177e4 LT |
1510 | return; |
1511 | } | |
1008fddc EB |
1512 | clear_IO_APIC_pin(apic1, pin1); |
1513 | apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not " | |
1514 | "connected to IO-APIC\n"); | |
1da177e4 LT |
1515 | } |
1516 | ||
1008fddc EB |
1517 | apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) " |
1518 | "through the 8259A ... "); | |
1da177e4 | 1519 | if (pin2 != -1) { |
1008fddc EB |
1520 | apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...", |
1521 | apic2, pin2); | |
1da177e4 LT |
1522 | /* |
1523 | * legacy devices should be connected to IO APIC #0 | |
1524 | */ | |
1008fddc | 1525 | setup_ExtINT_IRQ0_pin(apic2, pin2, vector); |
1da177e4 | 1526 | if (timer_irq_works()) { |
5b922cd4 | 1527 | apic_printk(APIC_VERBOSE," works.\n"); |
1da177e4 LT |
1528 | nmi_watchdog_default(); |
1529 | if (nmi_watchdog == NMI_IO_APIC) { | |
1530 | setup_nmi(); | |
1da177e4 LT |
1531 | } |
1532 | return; | |
1533 | } | |
1534 | /* | |
1535 | * Cleanup, just in case ... | |
1536 | */ | |
1008fddc | 1537 | clear_IO_APIC_pin(apic2, pin2); |
1da177e4 | 1538 | } |
5b922cd4 | 1539 | apic_printk(APIC_VERBOSE," failed.\n"); |
1da177e4 | 1540 | |
1f992153 | 1541 | if (nmi_watchdog == NMI_IO_APIC) { |
1da177e4 LT |
1542 | printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n"); |
1543 | nmi_watchdog = 0; | |
1544 | } | |
1545 | ||
1546 | apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); | |
1547 | ||
1548 | disable_8259A_irq(0); | |
d1bef4ed | 1549 | irq_desc[0].chip = &lapic_irq_type; |
11a8e778 | 1550 | apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ |
1da177e4 LT |
1551 | enable_8259A_irq(0); |
1552 | ||
1553 | if (timer_irq_works()) { | |
5b922cd4 | 1554 | apic_printk(APIC_VERBOSE," works.\n"); |
1da177e4 LT |
1555 | return; |
1556 | } | |
11a8e778 | 1557 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector); |
1da177e4 LT |
1558 | apic_printk(APIC_VERBOSE," failed.\n"); |
1559 | ||
1560 | apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ..."); | |
1561 | ||
1562 | init_8259A(0); | |
1563 | make_8259A_irq(0); | |
11a8e778 | 1564 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
1565 | |
1566 | unlock_ExtINT_logic(); | |
1567 | ||
1568 | if (timer_irq_works()) { | |
1569 | apic_printk(APIC_VERBOSE," works.\n"); | |
1570 | return; | |
1571 | } | |
1572 | apic_printk(APIC_VERBOSE," failed :(.\n"); | |
1573 | panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n"); | |
1574 | } | |
1575 | ||
14d98cad AK |
1576 | static int __init notimercheck(char *s) |
1577 | { | |
1578 | no_timer_check = 1; | |
1579 | return 1; | |
1580 | } | |
1581 | __setup("no_timer_check", notimercheck); | |
1582 | ||
1da177e4 LT |
1583 | /* |
1584 | * | |
1585 | * IRQ's that are handled by the PIC in the MPS IOAPIC case. | |
1586 | * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ. | |
1587 | * Linux doesn't really care, as it's not actually used | |
1588 | * for any interrupt handling anyway. | |
1589 | */ | |
1590 | #define PIC_IRQS (1<<2) | |
1591 | ||
1592 | void __init setup_IO_APIC(void) | |
1593 | { | |
1594 | enable_IO_APIC(); | |
1595 | ||
1596 | if (acpi_ioapic) | |
1597 | io_apic_irqs = ~0; /* all IRQs go through IOAPIC */ | |
1598 | else | |
1599 | io_apic_irqs = ~PIC_IRQS; | |
1600 | ||
1601 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); | |
1602 | ||
1da177e4 LT |
1603 | sync_Arb_IDs(); |
1604 | setup_IO_APIC_irqs(); | |
1605 | init_IO_APIC_traps(); | |
1606 | check_timer(); | |
1607 | if (!acpi_ioapic) | |
1608 | print_IO_APIC(); | |
1609 | } | |
1610 | ||
1611 | struct sysfs_ioapic_data { | |
1612 | struct sys_device dev; | |
1613 | struct IO_APIC_route_entry entry[0]; | |
1614 | }; | |
1615 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; | |
1616 | ||
0b9c33a7 | 1617 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
1618 | { |
1619 | struct IO_APIC_route_entry *entry; | |
1620 | struct sysfs_ioapic_data *data; | |
1da177e4 LT |
1621 | int i; |
1622 | ||
1623 | data = container_of(dev, struct sysfs_ioapic_data, dev); | |
1624 | entry = data->entry; | |
eea0e11c AK |
1625 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
1626 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
1627 | |
1628 | return 0; | |
1629 | } | |
1630 | ||
1631 | static int ioapic_resume(struct sys_device *dev) | |
1632 | { | |
1633 | struct IO_APIC_route_entry *entry; | |
1634 | struct sysfs_ioapic_data *data; | |
1635 | unsigned long flags; | |
1636 | union IO_APIC_reg_00 reg_00; | |
1637 | int i; | |
1638 | ||
1639 | data = container_of(dev, struct sysfs_ioapic_data, dev); | |
1640 | entry = data->entry; | |
1641 | ||
1642 | spin_lock_irqsave(&ioapic_lock, flags); | |
1643 | reg_00.raw = io_apic_read(dev->id, 0); | |
1644 | if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) { | |
1645 | reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid; | |
1646 | io_apic_write(dev->id, 0, reg_00.raw); | |
1647 | } | |
1da177e4 | 1648 | spin_unlock_irqrestore(&ioapic_lock, flags); |
eea0e11c AK |
1649 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
1650 | ioapic_write_entry(dev->id, i, entry[i]); | |
1da177e4 LT |
1651 | |
1652 | return 0; | |
1653 | } | |
1654 | ||
1655 | static struct sysdev_class ioapic_sysdev_class = { | |
1656 | set_kset_name("ioapic"), | |
1657 | .suspend = ioapic_suspend, | |
1658 | .resume = ioapic_resume, | |
1659 | }; | |
1660 | ||
1661 | static int __init ioapic_init_sysfs(void) | |
1662 | { | |
1663 | struct sys_device * dev; | |
1664 | int i, size, error = 0; | |
1665 | ||
1666 | error = sysdev_class_register(&ioapic_sysdev_class); | |
1667 | if (error) | |
1668 | return error; | |
1669 | ||
1670 | for (i = 0; i < nr_ioapics; i++ ) { | |
1671 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] | |
1672 | * sizeof(struct IO_APIC_route_entry); | |
1673 | mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL); | |
1674 | if (!mp_ioapic_data[i]) { | |
1675 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
1676 | continue; | |
1677 | } | |
1678 | memset(mp_ioapic_data[i], 0, size); | |
1679 | dev = &mp_ioapic_data[i]->dev; | |
1680 | dev->id = i; | |
1681 | dev->cls = &ioapic_sysdev_class; | |
1682 | error = sysdev_register(dev); | |
1683 | if (error) { | |
1684 | kfree(mp_ioapic_data[i]); | |
1685 | mp_ioapic_data[i] = NULL; | |
1686 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
1687 | continue; | |
1688 | } | |
1689 | } | |
1690 | ||
1691 | return 0; | |
1692 | } | |
1693 | ||
1694 | device_initcall(ioapic_init_sysfs); | |
1695 | ||
c4fa0bbf EB |
1696 | #ifdef CONFIG_PCI_MSI |
1697 | /* | |
1698 | * Dynamic irq allocate and deallocation for MSI | |
1699 | */ | |
1700 | int create_irq(void) | |
1701 | { | |
1702 | /* Hack of the day: irq == vector. | |
1703 | * | |
1704 | * Ultimately this will be be more general, | |
1705 | * and not depend on the irq to vector identity mapping. | |
1706 | * But this version is needed until msi.c can cope with | |
1707 | * the more general form. | |
1708 | */ | |
1709 | int irq, vector; | |
1710 | unsigned long flags; | |
1711 | vector = assign_irq_vector(AUTO_ASSIGN); | |
1712 | irq = vector; | |
1713 | ||
1714 | if (vector >= 0) { | |
1715 | spin_lock_irqsave(&vector_lock, flags); | |
1716 | vector_irq[vector] = irq; | |
1717 | irq_vector[irq] = vector; | |
1718 | spin_unlock_irqrestore(&vector_lock, flags); | |
1719 | ||
1720 | set_intr_gate(vector, interrupt[irq]); | |
1721 | ||
1722 | dynamic_irq_init(irq); | |
1723 | } | |
1724 | return irq; | |
1725 | } | |
1726 | ||
1727 | void destroy_irq(unsigned int irq) | |
1728 | { | |
1729 | unsigned long flags; | |
1730 | unsigned int vector; | |
1731 | ||
1732 | dynamic_irq_cleanup(irq); | |
1733 | ||
1734 | spin_lock_irqsave(&vector_lock, flags); | |
1735 | vector = irq_vector[irq]; | |
1736 | vector_irq[vector] = -1; | |
1737 | irq_vector[irq] = 0; | |
1738 | spin_unlock_irqrestore(&vector_lock, flags); | |
1739 | } | |
1740 | #endif | |
1741 | ||
1da177e4 LT |
1742 | /* -------------------------------------------------------------------------- |
1743 | ACPI-based IOAPIC Configuration | |
1744 | -------------------------------------------------------------------------- */ | |
1745 | ||
888ba6c6 | 1746 | #ifdef CONFIG_ACPI |
1da177e4 LT |
1747 | |
1748 | #define IO_APIC_MAX_ID 0xFE | |
1749 | ||
1da177e4 LT |
1750 | int __init io_apic_get_redir_entries (int ioapic) |
1751 | { | |
1752 | union IO_APIC_reg_01 reg_01; | |
1753 | unsigned long flags; | |
1754 | ||
1755 | spin_lock_irqsave(&ioapic_lock, flags); | |
1756 | reg_01.raw = io_apic_read(ioapic, 1); | |
1757 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1758 | ||
1759 | return reg_01.bits.entries; | |
1760 | } | |
1761 | ||
1762 | ||
50eca3eb | 1763 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity) |
1da177e4 LT |
1764 | { |
1765 | struct IO_APIC_route_entry entry; | |
1766 | unsigned long flags; | |
1767 | ||
1768 | if (!IO_APIC_IRQ(irq)) { | |
1769 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
1770 | ioapic); | |
1771 | return -EINVAL; | |
1772 | } | |
1773 | ||
1774 | /* | |
1775 | * Generate a PCI IRQ routing entry and program the IOAPIC accordingly. | |
1776 | * Note that we mask (disable) IRQs now -- these get enabled when the | |
1777 | * corresponding device driver registers for this IRQ. | |
1778 | */ | |
1779 | ||
1780 | memset(&entry,0,sizeof(entry)); | |
1781 | ||
1782 | entry.delivery_mode = INT_DELIVERY_MODE; | |
1783 | entry.dest_mode = INT_DEST_MODE; | |
1784 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
50eca3eb BM |
1785 | entry.trigger = triggering; |
1786 | entry.polarity = polarity; | |
1da177e4 LT |
1787 | entry.mask = 1; /* Disabled (masked) */ |
1788 | ||
6004e1b7 | 1789 | irq = gsi_irq_sharing(irq); |
1da177e4 LT |
1790 | /* |
1791 | * IRQs < 16 are already in the irq_2_pin[] map | |
1792 | */ | |
1793 | if (irq >= 16) | |
1794 | add_pin_to_irq(irq, ioapic, pin); | |
1795 | ||
1796 | entry.vector = assign_irq_vector(irq); | |
1797 | ||
1798 | apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> " | |
1799 | "IRQ %d Mode:%i Active:%i)\n", ioapic, | |
1800 | mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq, | |
50eca3eb | 1801 | triggering, polarity); |
1da177e4 | 1802 | |
50eca3eb | 1803 | ioapic_register_intr(irq, entry.vector, triggering); |
1da177e4 LT |
1804 | |
1805 | if (!ioapic && (irq < 16)) | |
1806 | disable_8259A_irq(irq); | |
1807 | ||
eea0e11c AK |
1808 | ioapic_write_entry(ioapic, pin, entry); |
1809 | ||
1da177e4 | 1810 | spin_lock_irqsave(&ioapic_lock, flags); |
eea0e11c | 1811 | set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS); |
1da177e4 LT |
1812 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1813 | ||
1814 | return 0; | |
1815 | } | |
1816 | ||
888ba6c6 | 1817 | #endif /* CONFIG_ACPI */ |
1da177e4 LT |
1818 | |
1819 | ||
1820 | /* | |
1821 | * This function currently is only a helper for the i386 smp boot process where | |
1822 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
1823 | * so mask in all cases should simply be TARGET_CPUS | |
1824 | */ | |
54d5d424 | 1825 | #ifdef CONFIG_SMP |
1da177e4 LT |
1826 | void __init setup_ioapic_dest(void) |
1827 | { | |
1828 | int pin, ioapic, irq, irq_entry; | |
1829 | ||
1830 | if (skip_ioapic_setup == 1) | |
1831 | return; | |
1832 | ||
1833 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
1834 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
1835 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
1836 | if (irq_entry == -1) | |
1837 | continue; | |
1838 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
1839 | set_ioapic_affinity_irq(irq, TARGET_CPUS); | |
1840 | } | |
1841 | ||
1842 | } | |
1843 | } | |
54d5d424 | 1844 | #endif |