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[PATCH] i386: Fix race in IO-APIC routing entry setup.
[deliverable/linux.git] / arch / x86_64 / kernel / io_apic.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
1da177e4
LT		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
1da177e4 28#include <linux/smp_lock.h>
589e367f 29#include <linux/pci.h>
1da177e4
LT		 30#include <linux/mc146818rtc.h>
31#include <linux/acpi.h>
32#include <linux/sysdev.h>
3b7d1921 33#include <linux/msi.h>
95d77884 34#include <linux/htirq.h>
ab688059
AK		 35#ifdef CONFIG_ACPI
36#include <acpi/acpi_bus.h>
37#endif
1da177e4
LT		 38
39#include <asm/io.h>
40#include <asm/smp.h>
41#include <asm/desc.h>
42#include <asm/proto.h>
43#include <asm/mach_apic.h>
8d916406 44#include <asm/acpi.h>
ca8642f6 45#include <asm/dma.h>
3e4ff115 46#include <asm/nmi.h>
589e367f 47#include <asm/msidef.h>
8b955b0d 48#include <asm/hypertransport.h>
1da177e4 49
c7111c13 50static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result);
04b9267b 51
1da177e4
LT		 52#define __apicdebuginit __init
53
54int sis_apic_bug; /* not actually supported, dummy for compile */
55
14d98cad
AK		 56static int no_timer_check;
57
1008fddc
EB		 58/* Where if anywhere is the i8259 connect in external int mode */
59static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
60
1da177e4 61static DEFINE_SPINLOCK(ioapic_lock);
70a0a535 62DEFINE_SPINLOCK(vector_lock);
1da177e4
LT		 63
64/*
65 * # of IRQ routing registers
66 */
67int nr_ioapic_registers[MAX_IO_APICS];
68
69/*
70 * Rough estimation of how many shared IRQs there are, can
71 * be changed anytime.
72 */
6004e1b7 73#define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
1da177e4
LT		 74#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
75
76/*
77 * This is performance-critical, we want to do it O(1)
78 *
79 * the indexing order of this array favors 1:1 mappings
80 * between pins and IRQs.
81 */
82
83static struct irq_pin_list {
84 short apic, pin, next;
85} irq_2_pin[PIN_MAP_SIZE];
86
6c0ffb9d
LT		 87struct io_apic {
88 unsigned int index;
89 unsigned int unused[3];
90 unsigned int data;
91};
92
93static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
94{
95 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
96 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
97}
98
99static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
100{
101 struct io_apic __iomem *io_apic = io_apic_base(apic);
102 writel(reg, &io_apic->index);
103 return readl(&io_apic->data);
104}
105
106static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
107{
108 struct io_apic __iomem *io_apic = io_apic_base(apic);
109 writel(reg, &io_apic->index);
110 writel(value, &io_apic->data);
111}
112
113/*
114 * Re-write a value: to be used for read-modify-write
115 * cycles where the read already set up the index register.
116 */
117static inline void io_apic_modify(unsigned int apic, unsigned int value)
118{
119 struct io_apic __iomem *io_apic = io_apic_base(apic);
120 writel(value, &io_apic->data);
121}
122
123/*
124 * Synchronize the IO-APIC and the CPU by doing
125 * a dummy read from the IO-APIC
126 */
127static inline void io_apic_sync(unsigned int apic)
128{
129 struct io_apic __iomem *io_apic = io_apic_base(apic);
130 readl(&io_apic->data);
131}
132
54d5d424
AR		 133#define __DO_ACTION(R, ACTION, FINAL) \
134 \
135{ \
136 int pin; \
137 struct irq_pin_list *entry = irq_2_pin + irq; \
138 \
6004e1b7 139 BUG_ON(irq >= NR_IRQS); \
54d5d424
AR		 140 for (;;) { \
141 unsigned int reg; \
142 pin = entry->pin; \
143 if (pin == -1) \
144 break; \
145 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
146 reg ACTION; \
147 io_apic_modify(entry->apic, reg); \
148 if (!entry->next) \
149 break; \
150 entry = irq_2_pin + entry->next; \
151 } \
152 FINAL; \
153}
154
eea0e11c
AK		 155union entry_union {
156 struct { u32 w1, w2; };
157 struct IO_APIC_route_entry entry;
158};
159
160static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
161{
162 union entry_union eu;
163 unsigned long flags;
164 spin_lock_irqsave(&ioapic_lock, flags);
165 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
166 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
167 spin_unlock_irqrestore(&ioapic_lock, flags);
168 return eu.entry;
169}
170
48797ebd
LT		 171/*
172 * When we write a new IO APIC routing entry, we need to write the high
173 * word first! If the mask bit in the low word is clear, we will enable
174 * the interrupt, and we need to make sure the entry is fully populated
175 * before that happens.
176 */
eea0e11c
AK		 177static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
178{
179 unsigned long flags;
180 union entry_union eu;
181 eu.entry = e;
48797ebd
LT		 182 spin_lock_irqsave(&ioapic_lock, flags);
183 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
184 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
185 spin_unlock_irqrestore(&ioapic_lock, flags);
186}
187
188/*
189 * When we mask an IO APIC routing entry, we need to write the low
190 * word first, in order to set the mask bit before we change the
191 * high bits!
192 */
193static void ioapic_mask_entry(int apic, int pin)
194{
195 unsigned long flags;
196 union entry_union eu = { .entry.mask = 1 };
197
eea0e11c
AK		 198 spin_lock_irqsave(&ioapic_lock, flags);
199 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
200 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
201 spin_unlock_irqrestore(&ioapic_lock, flags);
202}
203
54d5d424 204#ifdef CONFIG_SMP
550f2299
EB		 205static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
206{
207 int apic, pin;
208 struct irq_pin_list *entry = irq_2_pin + irq;
209
210 BUG_ON(irq >= NR_IRQS);
211 for (;;) {
212 unsigned int reg;
213 apic = entry->apic;
214 pin = entry->pin;
215 if (pin == -1)
216 break;
217 io_apic_write(apic, 0x11 + pin*2, dest);
218 reg = io_apic_read(apic, 0x10 + pin*2);
219 reg &= ~0x000000ff;
220 reg |= vector;
221 io_apic_modify(apic, reg);
222 if (!entry->next)
223 break;
224 entry = irq_2_pin + entry->next;
225 }
226}
227
54d5d424
AR		 228static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
229{
230 unsigned long flags;
231 unsigned int dest;
232 cpumask_t tmp;
550f2299 233 int vector;
54d5d424
AR		 234
235 cpus_and(tmp, mask, cpu_online_map);
236 if (cpus_empty(tmp))
237 tmp = TARGET_CPUS;
238
239 cpus_and(mask, tmp, CPU_MASK_ALL);
240
c7111c13 241 vector = assign_irq_vector(irq, mask, &tmp);
550f2299
EB		 242 if (vector < 0)
243 return;
244
550f2299 245 dest = cpu_mask_to_apicid(tmp);
54d5d424
AR		 246
247 /*
248 * Only the high 8 bits are valid.
249 */
250 dest = SET_APIC_LOGICAL_ID(dest);
251
252 spin_lock_irqsave(&ioapic_lock, flags);
c7111c13 253 __target_IO_APIC_irq(irq, dest, vector);
04b9267b 254 set_native_irq_info(irq, mask);
54d5d424
AR		 255 spin_unlock_irqrestore(&ioapic_lock, flags);
256}
257#endif
258
1da177e4
LT		 259/*
260 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
261 * shared ISA-space IRQs, so we have to support them. We are super
262 * fast in the common case, and fast for shared ISA-space IRQs.
263 */
264static void add_pin_to_irq(unsigned int irq, int apic, int pin)
265{
266 static int first_free_entry = NR_IRQS;
267 struct irq_pin_list *entry = irq_2_pin + irq;
268
6004e1b7 269 BUG_ON(irq >= NR_IRQS);
1da177e4
LT		 270 while (entry->next)
271 entry = irq_2_pin + entry->next;
272
273 if (entry->pin != -1) {
274 entry->next = first_free_entry;
275 entry = irq_2_pin + entry->next;
276 if (++first_free_entry >= PIN_MAP_SIZE)
6004e1b7 277 panic("io_apic.c: ran out of irq_2_pin entries!");
1da177e4
LT		 278 }
279 entry->apic = apic;
280 entry->pin = pin;
281}
282
1da177e4
LT		 283
284#define DO_ACTION(name,R,ACTION, FINAL) \
285 \
286 static void name##_IO_APIC_irq (unsigned int irq) \
287 __DO_ACTION(R, ACTION, FINAL)
288
289DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
290 /* mask = 1 */
291DO_ACTION( __unmask, 0, &= 0xfffeffff, )
292 /* mask = 0 */
293
294static void mask_IO_APIC_irq (unsigned int irq)
295{
296 unsigned long flags;
297
298 spin_lock_irqsave(&ioapic_lock, flags);
299 __mask_IO_APIC_irq(irq);
300 spin_unlock_irqrestore(&ioapic_lock, flags);
301}
302
303static void unmask_IO_APIC_irq (unsigned int irq)
304{
305 unsigned long flags;
306
307 spin_lock_irqsave(&ioapic_lock, flags);
308 __unmask_IO_APIC_irq(irq);
309 spin_unlock_irqrestore(&ioapic_lock, flags);
310}
311
312static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
313{
314 struct IO_APIC_route_entry entry;
1da177e4
LT		 315
316 /* Check delivery_mode to be sure we're not clearing an SMI pin */
eea0e11c 317 entry = ioapic_read_entry(apic, pin);
1da177e4
LT		 318 if (entry.delivery_mode == dest_SMI)
319 return;
320 /*
321 * Disable it in the IO-APIC irq-routing table:
322 */
48797ebd 323 ioapic_mask_entry(apic, pin);
1da177e4
LT		 324}
325
326static void clear_IO_APIC (void)
327{
328 int apic, pin;
329
330 for (apic = 0; apic < nr_ioapics; apic++)
331 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
332 clear_IO_APIC_pin(apic, pin);
333}
334
1da177e4
LT		 335int skip_ioapic_setup;
336int ioapic_force;
337
338/* dummy parsing: see setup.c */
339
340static int __init disable_ioapic_setup(char *str)
341{
342 skip_ioapic_setup = 1;
2c8c0e6b 343 return 0;
1da177e4 344}
2c8c0e6b 345early_param("noapic", disable_ioapic_setup);
1da177e4 346
1da177e4
LT		 347/*
348 * Find the IRQ entry number of a certain pin.
349 */
350static int find_irq_entry(int apic, int pin, int type)
351{
352 int i;
353
354 for (i = 0; i < mp_irq_entries; i++)
355 if (mp_irqs[i].mpc_irqtype == type &&
356 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
357 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
358 mp_irqs[i].mpc_dstirq == pin)
359 return i;
360
361 return -1;
362}
363
364/*
365 * Find the pin to which IRQ[irq] (ISA) is connected
366 */
1008fddc 367static int __init find_isa_irq_pin(int irq, int type)
1da177e4
LT		 368{
369 int i;
370
371 for (i = 0; i < mp_irq_entries; i++) {
372 int lbus = mp_irqs[i].mpc_srcbus;
373
55f05ffa 374 if (test_bit(lbus, mp_bus_not_pci) &&
1da177e4
LT		 375 (mp_irqs[i].mpc_irqtype == type) &&
376 (mp_irqs[i].mpc_srcbusirq == irq))
377
378 return mp_irqs[i].mpc_dstirq;
379 }
380 return -1;
381}
382
1008fddc
EB		 383static int __init find_isa_irq_apic(int irq, int type)
384{
385 int i;
386
387 for (i = 0; i < mp_irq_entries; i++) {
388 int lbus = mp_irqs[i].mpc_srcbus;
389
55f05ffa 390 if (test_bit(lbus, mp_bus_not_pci) &&
1008fddc
EB		 391 (mp_irqs[i].mpc_irqtype == type) &&
392 (mp_irqs[i].mpc_srcbusirq == irq))
393 break;
394 }
395 if (i < mp_irq_entries) {
396 int apic;
397 for(apic = 0; apic < nr_ioapics; apic++) {
398 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
399 return apic;
400 }
401 }
402
403 return -1;
404}
405
1da177e4
LT		 406/*
407 * Find a specific PCI IRQ entry.
408 * Not an __init, possibly needed by modules
409 */
410static int pin_2_irq(int idx, int apic, int pin);
411
412int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
413{
414 int apic, i, best_guess = -1;
415
416 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
417 bus, slot, pin);
418 if (mp_bus_id_to_pci_bus[bus] == -1) {
419 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
420 return -1;
421 }
422 for (i = 0; i < mp_irq_entries; i++) {
423 int lbus = mp_irqs[i].mpc_srcbus;
424
425 for (apic = 0; apic < nr_ioapics; apic++)
426 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
427 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
428 break;
429
55f05ffa 430 if (!test_bit(lbus, mp_bus_not_pci) &&
1da177e4
LT		 431 !mp_irqs[i].mpc_irqtype &&
432 (bus == lbus) &&
433 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
434 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
435
436 if (!(apic || IO_APIC_IRQ(irq)))
437 continue;
438
439 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
440 return irq;
441 /*
442 * Use the first all-but-pin matching entry as a
443 * best-guess fuzzy result for broken mptables.
444 */
445 if (best_guess < 0)
446 best_guess = irq;
447 }
448 }
6004e1b7 449 BUG_ON(best_guess >= NR_IRQS);
1da177e4
LT		 450 return best_guess;
451}
452
1da177e4
LT		 453/* ISA interrupts are always polarity zero edge triggered,
454 * when listed as conforming in the MP table. */
455
456#define default_ISA_trigger(idx) (0)
457#define default_ISA_polarity(idx) (0)
458
459/* PCI interrupts are always polarity one level triggered,
460 * when listed as conforming in the MP table. */
461
462#define default_PCI_trigger(idx) (1)
463#define default_PCI_polarity(idx) (1)
464
1da177e4
LT		 465static int __init MPBIOS_polarity(int idx)
466{
467 int bus = mp_irqs[idx].mpc_srcbus;
468 int polarity;
469
470 /*
471 * Determine IRQ line polarity (high active or low active):
472 */
473 switch (mp_irqs[idx].mpc_irqflag & 3)
474 {
475 case 0: /* conforms, ie. bus-type dependent polarity */
55f05ffa
AK		 476 if (test_bit(bus, mp_bus_not_pci))
477 polarity = default_ISA_polarity(idx);
478 else
479 polarity = default_PCI_polarity(idx);
1da177e4 480 break;
1da177e4
LT		 481 case 1: /* high active */
482 {
483 polarity = 0;
484 break;
485 }
486 case 2: /* reserved */
487 {
488 printk(KERN_WARNING "broken BIOS!!\n");
489 polarity = 1;
490 break;
491 }
492 case 3: /* low active */
493 {
494 polarity = 1;
495 break;
496 }
497 default: /* invalid */
498 {
499 printk(KERN_WARNING "broken BIOS!!\n");
500 polarity = 1;
501 break;
502 }
503 }
504 return polarity;
505}
506
507static int MPBIOS_trigger(int idx)
508{
509 int bus = mp_irqs[idx].mpc_srcbus;
510 int trigger;
511
512 /*
513 * Determine IRQ trigger mode (edge or level sensitive):
514 */
515 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
516 {
517 case 0: /* conforms, ie. bus-type dependent */
55f05ffa
AK		 518 if (test_bit(bus, mp_bus_not_pci))
519 trigger = default_ISA_trigger(idx);
520 else
521 trigger = default_PCI_trigger(idx);
1da177e4 522 break;
1da177e4
LT		 523 case 1: /* edge */
524 {
525 trigger = 0;
526 break;
527 }
528 case 2: /* reserved */
529 {
530 printk(KERN_WARNING "broken BIOS!!\n");
531 trigger = 1;
532 break;
533 }
534 case 3: /* level */
535 {
536 trigger = 1;
537 break;
538 }
539 default: /* invalid */
540 {
541 printk(KERN_WARNING "broken BIOS!!\n");
542 trigger = 0;
543 break;
544 }
545 }
546 return trigger;
547}
548
549static inline int irq_polarity(int idx)
550{
551 return MPBIOS_polarity(idx);
552}
553
554static inline int irq_trigger(int idx)
555{
556 return MPBIOS_trigger(idx);
557}
558
559static int pin_2_irq(int idx, int apic, int pin)
560{
561 int irq, i;
562 int bus = mp_irqs[idx].mpc_srcbus;
563
564 /*
565 * Debugging check, we are in big trouble if this message pops up!
566 */
567 if (mp_irqs[idx].mpc_dstirq != pin)
568 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
569
55f05ffa
AK		 570 if (test_bit(bus, mp_bus_not_pci)) {
571 irq = mp_irqs[idx].mpc_srcbusirq;
572 } else {
573 /*
574 * PCI IRQs are mapped in order
575 */
576 i = irq = 0;
577 while (i < apic)
578 irq += nr_ioapic_registers[i++];
579 irq += pin;
1da177e4 580 }
6004e1b7 581 BUG_ON(irq >= NR_IRQS);
1da177e4
LT		 582 return irq;
583}
584
585static inline int IO_APIC_irq_trigger(int irq)
586{
587 int apic, idx, pin;
588
589 for (apic = 0; apic < nr_ioapics; apic++) {
590 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
591 idx = find_irq_entry(apic,pin,mp_INT);
592 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
593 return irq_trigger(idx);
594 }
595 }
596 /*
597 * nonexistent IRQs are edge default
598 */
599 return 0;
600}
601
602/* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
c7111c13
EB		 603static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = {
604 [0] = FIRST_EXTERNAL_VECTOR + 0,
605 [1] = FIRST_EXTERNAL_VECTOR + 1,
606 [2] = FIRST_EXTERNAL_VECTOR + 2,
607 [3] = FIRST_EXTERNAL_VECTOR + 3,
608 [4] = FIRST_EXTERNAL_VECTOR + 4,
609 [5] = FIRST_EXTERNAL_VECTOR + 5,
610 [6] = FIRST_EXTERNAL_VECTOR + 6,
611 [7] = FIRST_EXTERNAL_VECTOR + 7,
612 [8] = FIRST_EXTERNAL_VECTOR + 8,
613 [9] = FIRST_EXTERNAL_VECTOR + 9,
614 [10] = FIRST_EXTERNAL_VECTOR + 10,
615 [11] = FIRST_EXTERNAL_VECTOR + 11,
616 [12] = FIRST_EXTERNAL_VECTOR + 12,
617 [13] = FIRST_EXTERNAL_VECTOR + 13,
618 [14] = FIRST_EXTERNAL_VECTOR + 14,
619 [15] = FIRST_EXTERNAL_VECTOR + 15,
620};
621
622static cpumask_t irq_domain[NR_IRQ_VECTORS] __read_mostly = {
623 [0] = CPU_MASK_ALL,
624 [1] = CPU_MASK_ALL,
625 [2] = CPU_MASK_ALL,
626 [3] = CPU_MASK_ALL,
627 [4] = CPU_MASK_ALL,
628 [5] = CPU_MASK_ALL,
629 [6] = CPU_MASK_ALL,
630 [7] = CPU_MASK_ALL,
631 [8] = CPU_MASK_ALL,
632 [9] = CPU_MASK_ALL,
633 [10] = CPU_MASK_ALL,
634 [11] = CPU_MASK_ALL,
635 [12] = CPU_MASK_ALL,
636 [13] = CPU_MASK_ALL,
637 [14] = CPU_MASK_ALL,
638 [15] = CPU_MASK_ALL,
639};
1da177e4 640
c7111c13 641static int __assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
1da177e4 642{
550f2299
EB		 643 /*
644 * NOTE! The local APIC isn't very good at handling
645 * multiple interrupts at the same interrupt level.
646 * As the interrupt level is determined by taking the
647 * vector number and shifting that right by 4, we
648 * want to spread these out a bit so that they don't
649 * all fall in the same interrupt level.
650 *
651 * Also, we've got to be careful not to trash gate
652 * 0x80, because int 0x80 is hm, kind of importantish. ;)
653 */
d1752aa8 654 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
550f2299
EB		 655 int old_vector = -1;
656 int cpu;
1da177e4 657
04b9267b 658 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
0a1ad60d 659
70a0a535
EB		 660 /* Only try and allocate irqs on cpus that are present */
661 cpus_and(mask, mask, cpu_online_map);
662
b940d22d
EB		 663 if (irq_vector[irq] > 0)
664 old_vector = irq_vector[irq];
c7111c13
EB		 665 if (old_vector > 0) {
666 cpus_and(*result, irq_domain[irq], mask);
667 if (!cpus_empty(*result))
668 return old_vector;
0a1ad60d 669 }
550f2299
EB		 670
671 for_each_cpu_mask(cpu, mask) {
70a0a535 672 cpumask_t domain, new_mask;
d1752aa8 673 int new_cpu;
550f2299 674 int vector, offset;
c7111c13
EB		 675
676 domain = vector_allocation_domain(cpu);
70a0a535 677 cpus_and(new_mask, domain, cpu_online_map);
c7111c13 678
d1752aa8
EB		 679 vector = current_vector;
680 offset = current_offset;
1da177e4 681next:
550f2299
EB		 682 vector += 8;
683 if (vector >= FIRST_SYSTEM_VECTOR) {
684 /* If we run out of vectors on large boxen, must share them. */
685 offset = (offset + 1) % 8;
686 vector = FIRST_DEVICE_VECTOR + offset;
687 }
d1752aa8 688 if (unlikely(current_vector == vector))
550f2299
EB		 689 continue;
690 if (vector == IA32_SYSCALL_VECTOR)
691 goto next;
70a0a535 692 for_each_cpu_mask(new_cpu, new_mask)
45edfd1d 693 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
c7111c13 694 goto next;
550f2299 695 /* Found one! */
d1752aa8
EB		 696 current_vector = vector;
697 current_offset = offset;
550f2299 698 if (old_vector >= 0) {
70a0a535 699 cpumask_t old_mask;
c7111c13 700 int old_cpu;
70a0a535
EB		 701 cpus_and(old_mask, irq_domain[irq], cpu_online_map);
702 for_each_cpu_mask(old_cpu, old_mask)
c7111c13 703 per_cpu(vector_irq, old_cpu)[old_vector] = -1;
550f2299 704 }
70a0a535 705 for_each_cpu_mask(new_cpu, new_mask)
c7111c13 706 per_cpu(vector_irq, new_cpu)[vector] = irq;
b940d22d 707 irq_vector[irq] = vector;
c7111c13
EB		 708 irq_domain[irq] = domain;
709 cpus_and(*result, domain, mask);
550f2299 710 return vector;
1da177e4 711 }
550f2299 712 return -ENOSPC;
04b9267b
EB		 713}
714
c7111c13 715static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
04b9267b
EB		 716{
717 int vector;
718 unsigned long flags;
0a1ad60d 719
04b9267b 720 spin_lock_irqsave(&vector_lock, flags);
c7111c13 721 vector = __assign_irq_vector(irq, mask, result);
26a3c49c 722 spin_unlock_irqrestore(&vector_lock, flags);
0a1ad60d 723 return vector;
1da177e4
LT		 724}
725
5df0287e
YL		 726static void __clear_irq_vector(int irq)
727{
728 cpumask_t mask;
729 int cpu, vector;
730
731 BUG_ON(!irq_vector[irq]);
732
733 vector = irq_vector[irq];
734 cpus_and(mask, irq_domain[irq], cpu_online_map);
735 for_each_cpu_mask(cpu, mask)
736 per_cpu(vector_irq, cpu)[vector] = -1;
737
738 irq_vector[irq] = 0;
739 irq_domain[irq] = CPU_MASK_NONE;
740}
741
70a0a535
EB		 742void __setup_vector_irq(int cpu)
743{
744 /* Initialize vector_irq on a new cpu */
745 /* This function must be called with vector_lock held */
70a0a535
EB		 746 int irq, vector;
747
70a0a535
EB		 748 /* Mark the inuse vectors */
749 for (irq = 0; irq < NR_IRQ_VECTORS; ++irq) {
750 if (!cpu_isset(cpu, irq_domain[irq]))
751 continue;
752 vector = irq_vector[irq];
753 per_cpu(vector_irq, cpu)[vector] = irq;
754 }
755 /* Mark the free vectors */
756 for (vector = 0; vector < NR_VECTORS; ++vector) {
757 irq = per_cpu(vector_irq, cpu)[vector];
758 if (irq < 0)
759 continue;
760 if (!cpu_isset(cpu, irq_domain[irq]))
761 per_cpu(vector_irq, cpu)[vector] = -1;
762 }
763}
764
765
1da177e4 766extern void (*interrupt[NR_IRQS])(void);
f29bd1ba
IM		 767
768static struct irq_chip ioapic_chip;
1da177e4
LT		 769
770#define IOAPIC_AUTO -1
771#define IOAPIC_EDGE 0
772#define IOAPIC_LEVEL 1
773
d1bef4ed 774static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1da177e4 775{
6ebcc00e
JB		 776 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
777 trigger == IOAPIC_LEVEL)
a460e745
IM		 778 set_irq_chip_and_handler_name(irq, &ioapic_chip,
779 handle_fasteoi_irq, "fasteoi");
45c99533
EB		 780 else {
781 irq_desc[irq].status |= IRQ_DELAYED_DISABLE;
a460e745
IM		 782 set_irq_chip_and_handler_name(irq, &ioapic_chip,
783 handle_edge_irq, "edge");
45c99533 784 }
1da177e4
LT		 785}
786
787static void __init setup_IO_APIC_irqs(void)
788{
789 struct IO_APIC_route_entry entry;
790 int apic, pin, idx, irq, first_notcon = 1, vector;
791 unsigned long flags;
792
793 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
794
795 for (apic = 0; apic < nr_ioapics; apic++) {
796 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
797
798 /*
799 * add it to the IO-APIC irq-routing table:
800 */
801 memset(&entry,0,sizeof(entry));
802
803 entry.delivery_mode = INT_DELIVERY_MODE;
804 entry.dest_mode = INT_DEST_MODE;
805 entry.mask = 0; /* enable IRQ */
806 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
807
808 idx = find_irq_entry(apic,pin,mp_INT);
809 if (idx == -1) {
810 if (first_notcon) {
811 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
812 first_notcon = 0;
813 } else
814 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
815 continue;
816 }
817
818 entry.trigger = irq_trigger(idx);
819 entry.polarity = irq_polarity(idx);
820
821 if (irq_trigger(idx)) {
822 entry.trigger = 1;
823 entry.mask = 1;
824 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
825 }
826
827 irq = pin_2_irq(idx, apic, pin);
828 add_pin_to_irq(irq, apic, pin);
829
830 if (!apic && !IO_APIC_IRQ(irq))
831 continue;
832
833 if (IO_APIC_IRQ(irq)) {
550f2299 834 cpumask_t mask;
c7111c13 835 vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
550f2299
EB		 836 if (vector < 0)
837 continue;
838
550f2299 839 entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
c7111c13 840 entry.vector = vector;
1da177e4
LT		 841
842 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
843 if (!apic && (irq < 16))
844 disable_8259A_irq(irq);
845 }
eea0e11c
AK		 846 ioapic_write_entry(apic, pin, entry);
847
1da177e4 848 spin_lock_irqsave(&ioapic_lock, flags);
54d5d424 849 set_native_irq_info(irq, TARGET_CPUS);
1da177e4
LT		 850 spin_unlock_irqrestore(&ioapic_lock, flags);
851 }
852 }
853
854 if (!first_notcon)
855 apic_printk(APIC_VERBOSE," not connected.\n");
856}
857
858/*
859 * Set up the 8259A-master output pin as broadcast to all
860 * CPUs.
861 */
1008fddc 862static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1da177e4
LT		 863{
864 struct IO_APIC_route_entry entry;
865 unsigned long flags;
866
867 memset(&entry,0,sizeof(entry));
868
869 disable_8259A_irq(0);
870
871 /* mask LVT0 */
11a8e778 872 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4
LT		 873
874 /*
875 * We use logical delivery to get the timer IRQ
876 * to the first CPU.
877 */
878 entry.dest_mode = INT_DEST_MODE;
879 entry.mask = 0; /* unmask IRQ now */
880 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
881 entry.delivery_mode = INT_DELIVERY_MODE;
882 entry.polarity = 0;
883 entry.trigger = 0;
884 entry.vector = vector;
885
886 /*
887 * The timer IRQ doesn't have to know that behind the
888 * scene we have a 8259A-master in AEOI mode ...
889 */
a460e745 890 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1da177e4
LT		 891
892 /*
893 * Add it to the IO-APIC irq-routing table:
894 */
895 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 896 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
897 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1da177e4
LT		 898 spin_unlock_irqrestore(&ioapic_lock, flags);
899
900 enable_8259A_irq(0);
901}
902
903void __init UNEXPECTED_IO_APIC(void)
904{
905}
906
907void __apicdebuginit print_IO_APIC(void)
908{
909 int apic, i;
910 union IO_APIC_reg_00 reg_00;
911 union IO_APIC_reg_01 reg_01;
912 union IO_APIC_reg_02 reg_02;
913 unsigned long flags;
914
915 if (apic_verbosity == APIC_QUIET)
916 return;
917
918 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
919 for (i = 0; i < nr_ioapics; i++)
920 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
921 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
922
923 /*
924 * We are a bit conservative about what we expect. We have to
925 * know about every hardware change ASAP.
926 */
927 printk(KERN_INFO "testing the IO APIC.......................\n");
928
929 for (apic = 0; apic < nr_ioapics; apic++) {
930
931 spin_lock_irqsave(&ioapic_lock, flags);
932 reg_00.raw = io_apic_read(apic, 0);
933 reg_01.raw = io_apic_read(apic, 1);
934 if (reg_01.bits.version >= 0x10)
935 reg_02.raw = io_apic_read(apic, 2);
936 spin_unlock_irqrestore(&ioapic_lock, flags);
937
938 printk("\n");
939 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
940 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
941 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
942 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
943 UNEXPECTED_IO_APIC();
944
945 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
946 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
947 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
948 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
949 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
950 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
951 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
952 (reg_01.bits.entries != 0x2E) &&
953 (reg_01.bits.entries != 0x3F) &&
954 (reg_01.bits.entries != 0x03)
955 )
956 UNEXPECTED_IO_APIC();
957
958 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
959 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
960 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
961 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
962 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
963 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
964 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
965 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
966 )
967 UNEXPECTED_IO_APIC();
968 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
969 UNEXPECTED_IO_APIC();
970
971 if (reg_01.bits.version >= 0x10) {
972 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
973 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
974 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
975 UNEXPECTED_IO_APIC();
976 }
977
978 printk(KERN_DEBUG ".... IRQ redirection table:\n");
979
980 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
981 " Stat Dest Deli Vect: \n");
982
983 for (i = 0; i <= reg_01.bits.entries; i++) {
984 struct IO_APIC_route_entry entry;
985
eea0e11c 986 entry = ioapic_read_entry(apic, i);
1da177e4
LT		 987
988 printk(KERN_DEBUG " %02x %03X %02X ",
989 i,
990 entry.dest.logical.logical_dest,
991 entry.dest.physical.physical_dest
992 );
993
994 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
995 entry.mask,
996 entry.trigger,
997 entry.irr,
998 entry.polarity,
999 entry.delivery_status,
1000 entry.dest_mode,
1001 entry.delivery_mode,
1002 entry.vector
1003 );
1004 }
1005 }
1da177e4
LT		 1006 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1007 for (i = 0; i < NR_IRQS; i++) {
1008 struct irq_pin_list *entry = irq_2_pin + i;
1009 if (entry->pin < 0)
1010 continue;
04b9267b 1011 printk(KERN_DEBUG "IRQ%d ", i);
1da177e4
LT		 1012 for (;;) {
1013 printk("-> %d:%d", entry->apic, entry->pin);
1014 if (!entry->next)
1015 break;
1016 entry = irq_2_pin + entry->next;
1017 }
1018 printk("\n");
1019 }
1020
1021 printk(KERN_INFO ".................................... done.\n");
1022
1023 return;
1024}
1025
1026#if 0
1027
1028static __apicdebuginit void print_APIC_bitfield (int base)
1029{
1030 unsigned int v;
1031 int i, j;
1032
1033 if (apic_verbosity == APIC_QUIET)
1034 return;
1035
1036 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1037 for (i = 0; i < 8; i++) {
1038 v = apic_read(base + i*0x10);
1039 for (j = 0; j < 32; j++) {
1040 if (v & (1<<j))
1041 printk("1");
1042 else
1043 printk("0");
1044 }
1045 printk("\n");
1046 }
1047}
1048
1049void __apicdebuginit print_local_APIC(void * dummy)
1050{
1051 unsigned int v, ver, maxlvt;
1052
1053 if (apic_verbosity == APIC_QUIET)
1054 return;
1055
1056 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1057 smp_processor_id(), hard_smp_processor_id());
1058 v = apic_read(APIC_ID);
1059 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1060 v = apic_read(APIC_LVR);
1061 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1062 ver = GET_APIC_VERSION(v);
1063 maxlvt = get_maxlvt();
1064
1065 v = apic_read(APIC_TASKPRI);
1066 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1067
5a40b7c2
AK		 1068 v = apic_read(APIC_ARBPRI);
1069 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1070 v & APIC_ARBPRI_MASK);
1071 v = apic_read(APIC_PROCPRI);
1072 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1da177e4
LT		 1073
1074 v = apic_read(APIC_EOI);
1075 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1076 v = apic_read(APIC_RRR);
1077 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1078 v = apic_read(APIC_LDR);
1079 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1080 v = apic_read(APIC_DFR);
1081 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1082 v = apic_read(APIC_SPIV);
1083 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1084
1085 printk(KERN_DEBUG "... APIC ISR field:\n");
1086 print_APIC_bitfield(APIC_ISR);
1087 printk(KERN_DEBUG "... APIC TMR field:\n");
1088 print_APIC_bitfield(APIC_TMR);
1089 printk(KERN_DEBUG "... APIC IRR field:\n");
1090 print_APIC_bitfield(APIC_IRR);
1091
5a40b7c2
AK		 1092 v = apic_read(APIC_ESR);
1093 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1da177e4
LT		 1094
1095 v = apic_read(APIC_ICR);
1096 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1097 v = apic_read(APIC_ICR2);
1098 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1099
1100 v = apic_read(APIC_LVTT);
1101 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1102
1103 if (maxlvt > 3) { /* PC is LVT#4. */
1104 v = apic_read(APIC_LVTPC);
1105 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1106 }
1107 v = apic_read(APIC_LVT0);
1108 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1109 v = apic_read(APIC_LVT1);
1110 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1111
1112 if (maxlvt > 2) { /* ERR is LVT#3. */
1113 v = apic_read(APIC_LVTERR);
1114 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1115 }
1116
1117 v = apic_read(APIC_TMICT);
1118 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1119 v = apic_read(APIC_TMCCT);
1120 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1121 v = apic_read(APIC_TDCR);
1122 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1123 printk("\n");
1124}
1125
1126void print_all_local_APICs (void)
1127{
1128 on_each_cpu(print_local_APIC, NULL, 1, 1);
1129}
1130
1131void __apicdebuginit print_PIC(void)
1132{
1da177e4
LT		 1133 unsigned int v;
1134 unsigned long flags;
1135
1136 if (apic_verbosity == APIC_QUIET)
1137 return;
1138
1139 printk(KERN_DEBUG "\nprinting PIC contents\n");
1140
1141 spin_lock_irqsave(&i8259A_lock, flags);
1142
1143 v = inb(0xa1) << 8 | inb(0x21);
1144 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1145
1146 v = inb(0xa0) << 8 | inb(0x20);
1147 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1148
1149 outb(0x0b,0xa0);
1150 outb(0x0b,0x20);
1151 v = inb(0xa0) << 8 | inb(0x20);
1152 outb(0x0a,0xa0);
1153 outb(0x0a,0x20);
1154
1155 spin_unlock_irqrestore(&i8259A_lock, flags);
1156
1157 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1158
1159 v = inb(0x4d1) << 8 | inb(0x4d0);
1160 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1161}
1162
1163#endif /* 0 */
1164
1165static void __init enable_IO_APIC(void)
1166{
1167 union IO_APIC_reg_01 reg_01;
1008fddc
EB		 1168 int i8259_apic, i8259_pin;
1169 int i, apic;
1da177e4
LT		 1170 unsigned long flags;
1171
1172 for (i = 0; i < PIN_MAP_SIZE; i++) {
1173 irq_2_pin[i].pin = -1;
1174 irq_2_pin[i].next = 0;
1175 }
1da177e4
LT		 1176
1177 /*
1178 * The number of IO-APIC IRQ registers (== #pins):
1179 */
1008fddc 1180 for (apic = 0; apic < nr_ioapics; apic++) {
1da177e4 1181 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc 1182 reg_01.raw = io_apic_read(apic, 1);
1da177e4 1183 spin_unlock_irqrestore(&ioapic_lock, flags);
1008fddc
EB		 1184 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1185 }
1186 for(apic = 0; apic < nr_ioapics; apic++) {
1187 int pin;
1188 /* See if any of the pins is in ExtINT mode */
1189 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1190 struct IO_APIC_route_entry entry;
eea0e11c 1191 entry = ioapic_read_entry(apic, pin);
1008fddc
EB		 1192
1193 /* If the interrupt line is enabled and in ExtInt mode
1194 * I have found the pin where the i8259 is connected.
1195 */
1196 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1197 ioapic_i8259.apic = apic;
1198 ioapic_i8259.pin = pin;
1199 goto found_i8259;
1200 }
1201 }
1202 }
1203 found_i8259:
1204 /* Look to see what if the MP table has reported the ExtINT */
1205 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1206 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1207 /* Trust the MP table if nothing is setup in the hardware */
1208 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1209 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1210 ioapic_i8259.pin = i8259_pin;
1211 ioapic_i8259.apic = i8259_apic;
1212 }
1213 /* Complain if the MP table and the hardware disagree */
1214 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1215 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1216 {
1217 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1da177e4
LT		 1218 }
1219
1220 /*
1221 * Do not trust the IO-APIC being empty at bootup
1222 */
1223 clear_IO_APIC();
1224}
1225
1226/*
1227 * Not an __init, needed by the reboot code
1228 */
1229void disable_IO_APIC(void)
1230{
1231 /*
1232 * Clear the IO-APIC before rebooting:
1233 */
1234 clear_IO_APIC();
1235
208fb931 1236 /*
0b968d23 1237 * If the i8259 is routed through an IOAPIC
208fb931 1238 * Put that IOAPIC in virtual wire mode
0b968d23 1239 * so legacy interrupts can be delivered.
208fb931 1240 */
1008fddc 1241 if (ioapic_i8259.pin != -1) {
208fb931 1242 struct IO_APIC_route_entry entry;
208fb931
EB		 1243
1244 memset(&entry, 0, sizeof(entry));
1245 entry.mask = 0; /* Enabled */
1246 entry.trigger = 0; /* Edge */
1247 entry.irr = 0;
1248 entry.polarity = 0; /* High */
1249 entry.delivery_status = 0;
1250 entry.dest_mode = 0; /* Physical */
1008fddc 1251 entry.delivery_mode = dest_ExtINT; /* ExtInt */
208fb931 1252 entry.vector = 0;
af5b9804
VG		 1253 entry.dest.physical.physical_dest =
1254 GET_APIC_ID(apic_read(APIC_ID));
208fb931 1255
208fb931
EB		 1256 /*
1257 * Add it to the IO-APIC irq-routing table:
1258 */
eea0e11c 1259 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
208fb931
EB		 1260 }
1261
1008fddc 1262 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1da177e4
LT		 1263}
1264
1da177e4
LT		 1265/*
1266 * There is a nasty bug in some older SMP boards, their mptable lies
1267 * about the timer IRQ. We do the following to work around the situation:
1268 *
1269 * - timer IRQ defaults to IO-APIC IRQ
1270 * - if this function detects that timer IRQs are defunct, then we fall
1271 * back to ISA timer IRQs
1272 */
1273static int __init timer_irq_works(void)
1274{
1275 unsigned long t1 = jiffies;
1276
1277 local_irq_enable();
1278 /* Let ten ticks pass... */
1279 mdelay((10 * 1000) / HZ);
1280
1281 /*
1282 * Expect a few ticks at least, to be sure some possible
1283 * glue logic does not lock up after one or two first
1284 * ticks in a non-ExtINT mode. Also the local APIC
1285 * might have cached one ExtINT interrupt. Finally, at
1286 * least one tick may be lost due to delays.
1287 */
1288
1289 /* jiffies wrap? */
1290 if (jiffies - t1 > 4)
1291 return 1;
1292 return 0;
1293}
1294
1295/*
1296 * In the SMP+IOAPIC case it might happen that there are an unspecified
1297 * number of pending IRQ events unhandled. These cases are very rare,
1298 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1299 * better to do it this way as thus we do not have to be aware of
1300 * 'pending' interrupts in the IRQ path, except at this point.
1301 */
1302/*
1303 * Edge triggered needs to resend any interrupt
1304 * that was delayed but this is now handled in the device
1305 * independent code.
1306 */
1307
1308/*
1309 * Starting up a edge-triggered IO-APIC interrupt is
1310 * nasty - we need to make sure that we get the edge.
1311 * If it is already asserted for some reason, we need
1312 * return 1 to indicate that is was pending.
1313 *
1314 * This is not complete - we should be able to fake
1315 * an edge even if it isn't on the 8259A...
1316 */
1317
f29bd1ba 1318static unsigned int startup_ioapic_irq(unsigned int irq)
1da177e4
LT		 1319{
1320 int was_pending = 0;
1321 unsigned long flags;
1322
1323 spin_lock_irqsave(&ioapic_lock, flags);
1324 if (irq < 16) {
1325 disable_8259A_irq(irq);
1326 if (i8259A_irq_pending(irq))
1327 was_pending = 1;
1328 }
1329 __unmask_IO_APIC_irq(irq);
1330 spin_unlock_irqrestore(&ioapic_lock, flags);
1331
1332 return was_pending;
1333}
1334
04b9267b 1335static int ioapic_retrigger_irq(unsigned int irq)
c0ad90a3 1336{
550f2299
EB		 1337 cpumask_t mask;
1338 unsigned vector;
6bf2dafa 1339 unsigned long flags;
550f2299 1340
6bf2dafa 1341 spin_lock_irqsave(&vector_lock, flags);
550f2299
EB		 1342 vector = irq_vector[irq];
1343 cpus_clear(mask);
6bf2dafa 1344 cpu_set(first_cpu(irq_domain[irq]), mask);
550f2299 1345
6bf2dafa
EB		 1346 send_IPI_mask(mask, vector);
1347 spin_unlock_irqrestore(&vector_lock, flags);
c0ad90a3
IM		 1348
1349 return 1;
1350}
1351
1da177e4
LT		 1352/*
1353 * Level and edge triggered IO-APIC interrupts need different handling,
1354 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1355 * handled with the level-triggered descriptor, but that one has slightly
1356 * more overhead. Level-triggered interrupts cannot be handled with the
1357 * edge-triggered handler, without risking IRQ storms and other ugly
1358 * races.
1359 */
1360
0be6652f
EB		 1361static void ack_apic_edge(unsigned int irq)
1362{
1363 move_native_irq(irq);
1364 ack_APIC_irq();
1365}
1366
1367static void ack_apic_level(unsigned int irq)
1368{
1369 int do_unmask_irq = 0;
1370
1371#if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1372 /* If we are moving the irq we need to mask it */
1373 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1374 do_unmask_irq = 1;
1375 mask_IO_APIC_irq(irq);
1376 }
1377#endif
1378
1379 /*
1380 * We must acknowledge the irq before we move it or the acknowledge will
1381 * not propogate properly.
1382 */
1383 ack_APIC_irq();
1384
1385 /* Now we can move and renable the irq */
1386 move_masked_irq(irq);
1387 if (unlikely(do_unmask_irq))
1388 unmask_IO_APIC_irq(irq);
1389}
1390
f29bd1ba
IM		 1391static struct irq_chip ioapic_chip __read_mostly = {
1392 .name = "IO-APIC",
04b9267b
EB		 1393 .startup = startup_ioapic_irq,
1394 .mask = mask_IO_APIC_irq,
1395 .unmask = unmask_IO_APIC_irq,
0be6652f
EB		 1396 .ack = ack_apic_edge,
1397 .eoi = ack_apic_level,
54d5d424 1398#ifdef CONFIG_SMP
04b9267b 1399 .set_affinity = set_ioapic_affinity_irq,
54d5d424 1400#endif
04b9267b 1401 .retrigger = ioapic_retrigger_irq,
1da177e4
LT		 1402};
1403
1404static inline void init_IO_APIC_traps(void)
1405{
1406 int irq;
1407
1408 /*
1409 * NOTE! The local APIC isn't very good at handling
1410 * multiple interrupts at the same interrupt level.
1411 * As the interrupt level is determined by taking the
1412 * vector number and shifting that right by 4, we
1413 * want to spread these out a bit so that they don't
1414 * all fall in the same interrupt level.
1415 *
1416 * Also, we've got to be careful not to trash gate
1417 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1418 */
1419 for (irq = 0; irq < NR_IRQS ; irq++) {
1420 int tmp = irq;
b940d22d 1421 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
1da177e4
LT		 1422 /*
1423 * Hmm.. We don't have an entry for this,
1424 * so default to an old-fashioned 8259
1425 * interrupt if we can..
1426 */
1427 if (irq < 16)
1428 make_8259A_irq(irq);
1429 else
1430 /* Strange. Oh, well.. */
f29bd1ba 1431 irq_desc[irq].chip = &no_irq_chip;
1da177e4
LT		 1432 }
1433 }
1434}
1435
1436static void enable_lapic_irq (unsigned int irq)
1437{
1438 unsigned long v;
1439
1440 v = apic_read(APIC_LVT0);
11a8e778 1441 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1da177e4
LT		 1442}
1443
1444static void disable_lapic_irq (unsigned int irq)
1445{
1446 unsigned long v;
1447
1448 v = apic_read(APIC_LVT0);
11a8e778 1449 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1da177e4
LT		 1450}
1451
1452static void ack_lapic_irq (unsigned int irq)
1453{
1454 ack_APIC_irq();
1455}
1456
1457static void end_lapic_irq (unsigned int i) { /* nothing */ }
1458
6c231b7b 1459static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1da177e4
LT		 1460 .typename = "local-APIC-edge",
1461 .startup = NULL, /* startup_irq() not used for IRQ0 */
1462 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1463 .enable = enable_lapic_irq,
1464 .disable = disable_lapic_irq,
1465 .ack = ack_lapic_irq,
1466 .end = end_lapic_irq,
1467};
1468
1469static void setup_nmi (void)
1470{
1471 /*
1472 * Dirty trick to enable the NMI watchdog ...
1473 * We put the 8259A master into AEOI mode and
1474 * unmask on all local APICs LVT0 as NMI.
1475 *
1476 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1477 * is from Maciej W. Rozycki - so we do not have to EOI from
1478 * the NMI handler or the timer interrupt.
1479 */
1480 printk(KERN_INFO "activating NMI Watchdog ...");
1481
1482 enable_NMI_through_LVT0(NULL);
1483
1484 printk(" done.\n");
1485}
1486
1487/*
1488 * This looks a bit hackish but it's about the only one way of sending
1489 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1490 * not support the ExtINT mode, unfortunately. We need to send these
1491 * cycles as some i82489DX-based boards have glue logic that keeps the
1492 * 8259A interrupt line asserted until INTA. --macro
1493 */
1494static inline void unlock_ExtINT_logic(void)
1495{
1008fddc 1496 int apic, pin, i;
1da177e4
LT		 1497 struct IO_APIC_route_entry entry0, entry1;
1498 unsigned char save_control, save_freq_select;
1499 unsigned long flags;
1500
1008fddc
EB		 1501 pin = find_isa_irq_pin(8, mp_INT);
1502 apic = find_isa_irq_apic(8, mp_INT);
1da177e4
LT		 1503 if (pin == -1)
1504 return;
1505
1506 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 1507 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1508 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1da177e4 1509 spin_unlock_irqrestore(&ioapic_lock, flags);
1008fddc 1510 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 1511
1512 memset(&entry1, 0, sizeof(entry1));
1513
1514 entry1.dest_mode = 0; /* physical delivery */
1515 entry1.mask = 0; /* unmask IRQ now */
1516 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1517 entry1.delivery_mode = dest_ExtINT;
1518 entry1.polarity = entry0.polarity;
1519 entry1.trigger = 0;
1520 entry1.vector = 0;
1521
1522 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 1523 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1524 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1da177e4
LT		 1525 spin_unlock_irqrestore(&ioapic_lock, flags);
1526
1527 save_control = CMOS_READ(RTC_CONTROL);
1528 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1529 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1530 RTC_FREQ_SELECT);
1531 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1532
1533 i = 100;
1534 while (i-- > 0) {
1535 mdelay(10);
1536 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1537 i -= 10;
1538 }
1539
1540 CMOS_WRITE(save_control, RTC_CONTROL);
1541 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1008fddc 1542 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 1543
1544 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 1545 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1546 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1da177e4
LT		 1547 spin_unlock_irqrestore(&ioapic_lock, flags);
1548}
1549
1550/*
1551 * This code may look a bit paranoid, but it's supposed to cooperate with
1552 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1553 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1554 * fanatically on his truly buggy board.
1555 */
b0268726
AK		 1556
1557static int try_apic_pin(int apic, int pin, char *msg)
1558{
1559 apic_printk(APIC_VERBOSE, KERN_INFO
1560 "..TIMER: trying IO-APIC=%d PIN=%d %s",
1561 apic, pin, msg);
1562
1563 /*
1564 * Ok, does IRQ0 through the IOAPIC work?
1565 */
1566 if (!no_timer_check && timer_irq_works()) {
1567 nmi_watchdog_default();
1568 if (nmi_watchdog == NMI_IO_APIC) {
1569 disable_8259A_irq(0);
1570 setup_nmi();
1571 enable_8259A_irq(0);
1572 }
1573 return 1;
1574 }
1575 clear_IO_APIC_pin(apic, pin);
1576 apic_printk(APIC_QUIET, KERN_ERR " .. failed\n");
1577 return 0;
1578}
1579
1580/* The function from hell */
1581static void check_timer(void)
1da177e4 1582{
1008fddc 1583 int apic1, pin1, apic2, pin2;
1da177e4 1584 int vector;
c7111c13 1585 cpumask_t mask;
1da177e4
LT		 1586
1587 /*
1588 * get/set the timer IRQ vector:
1589 */
1590 disable_8259A_irq(0);
c7111c13 1591 vector = assign_irq_vector(0, TARGET_CPUS, &mask);
1da177e4
LT		 1592
1593 /*
1594 * Subtle, code in do_timer_interrupt() expects an AEOI
1595 * mode for the 8259A whenever interrupts are routed
1596 * through I/O APICs. Also IRQ0 has to be enabled in
1597 * the 8259A which implies the virtual wire has to be
1598 * disabled in the local APIC.
1599 */
11a8e778 1600 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4 1601 init_8259A(1);
1da177e4 1602
1008fddc
EB		 1603 pin1 = find_isa_irq_pin(0, mp_INT);
1604 apic1 = find_isa_irq_apic(0, mp_INT);
1605 pin2 = ioapic_i8259.pin;
1606 apic2 = ioapic_i8259.apic;
1da177e4 1607
b0268726
AK		 1608 /* Do this first, otherwise we get double interrupts on ATI boards */
1609 if ((pin1 != -1) && try_apic_pin(apic1, pin1,"with 8259 IRQ0 disabled"))
1610 return;
1da177e4 1611
b0268726
AK		 1612 /* Now try again with IRQ0 8259A enabled.
1613 Assumes timer is on IO-APIC 0 ?!? */
1614 enable_8259A_irq(0);
1615 unmask_IO_APIC_irq(0);
1616 if (try_apic_pin(apic1, pin1, "with 8259 IRQ0 enabled"))
1617 return;
1618 disable_8259A_irq(0);
1619
1620 /* Always try pin0 and pin2 on APIC 0 to handle buggy timer overrides
1621 on Nvidia boards */
1622 if (!(apic1 == 0 && pin1 == 0) &&
1623 try_apic_pin(0, 0, "fallback with 8259 IRQ0 disabled"))
1624 return;
1625 if (!(apic1 == 0 && pin1 == 2) &&
1626 try_apic_pin(0, 2, "fallback with 8259 IRQ0 disabled"))
1627 return;
1da177e4 1628
b0268726
AK		 1629 /* Then try pure 8259A routing on the 8259 as reported by BIOS*/
1630 enable_8259A_irq(0);
1da177e4 1631 if (pin2 != -1) {
1008fddc 1632 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
b0268726 1633 if (try_apic_pin(apic2,pin2,"8259A broadcast ExtINT from BIOS"))
1da177e4 1634 return;
1da177e4 1635 }
b0268726
AK		 1636
1637 /* Tried all possibilities to go through the IO-APIC. Now come the
1638 really cheesy fallbacks. */
1da177e4 1639
1f992153 1640 if (nmi_watchdog == NMI_IO_APIC) {
1da177e4
LT		 1641 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1642 nmi_watchdog = 0;
1643 }
1644
1645 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1646
1647 disable_8259A_irq(0);
d1bef4ed 1648 irq_desc[0].chip = &lapic_irq_type;
11a8e778 1649 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1da177e4
LT		 1650 enable_8259A_irq(0);
1651
1652 if (timer_irq_works()) {
5b922cd4 1653 apic_printk(APIC_VERBOSE," works.\n");
1da177e4
LT		 1654 return;
1655 }
11a8e778 1656 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1da177e4
LT		 1657 apic_printk(APIC_VERBOSE," failed.\n");
1658
1659 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1660
1661 init_8259A(0);
1662 make_8259A_irq(0);
11a8e778 1663 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4
LT		 1664
1665 unlock_ExtINT_logic();
1666
1667 if (timer_irq_works()) {
1668 apic_printk(APIC_VERBOSE," works.\n");
1669 return;
1670 }
1671 apic_printk(APIC_VERBOSE," failed :(.\n");
1672 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1673}
1674
14d98cad
AK		 1675static int __init notimercheck(char *s)
1676{
1677 no_timer_check = 1;
1678 return 1;
1679}
1680__setup("no_timer_check", notimercheck);
1681
1da177e4
LT		 1682/*
1683 *
1684 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1685 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1686 * Linux doesn't really care, as it's not actually used
1687 * for any interrupt handling anyway.
1688 */
1689#define PIC_IRQS (1<<2)
1690
1691void __init setup_IO_APIC(void)
1692{
1693 enable_IO_APIC();
1694
1695 if (acpi_ioapic)
1696 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1697 else
1698 io_apic_irqs = ~PIC_IRQS;
1699
1700 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1701
1da177e4
LT		 1702 sync_Arb_IDs();
1703 setup_IO_APIC_irqs();
1704 init_IO_APIC_traps();
1705 check_timer();
1706 if (!acpi_ioapic)
1707 print_IO_APIC();
1708}
1709
1710struct sysfs_ioapic_data {
1711 struct sys_device dev;
1712 struct IO_APIC_route_entry entry[0];
1713};
1714static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1715
0b9c33a7 1716static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4
LT		 1717{
1718 struct IO_APIC_route_entry *entry;
1719 struct sysfs_ioapic_data *data;
1da177e4
LT		 1720 int i;
1721
1722 data = container_of(dev, struct sysfs_ioapic_data, dev);
1723 entry = data->entry;
eea0e11c
AK		 1724 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1725 *entry = ioapic_read_entry(dev->id, i);
1da177e4
LT		 1726
1727 return 0;
1728}
1729
1730static int ioapic_resume(struct sys_device *dev)
1731{
1732 struct IO_APIC_route_entry *entry;
1733 struct sysfs_ioapic_data *data;
1734 unsigned long flags;
1735 union IO_APIC_reg_00 reg_00;
1736 int i;
1737
1738 data = container_of(dev, struct sysfs_ioapic_data, dev);
1739 entry = data->entry;
1740
1741 spin_lock_irqsave(&ioapic_lock, flags);
1742 reg_00.raw = io_apic_read(dev->id, 0);
1743 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1744 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1745 io_apic_write(dev->id, 0, reg_00.raw);
1746 }
1da177e4 1747 spin_unlock_irqrestore(&ioapic_lock, flags);
eea0e11c
AK		 1748 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1749 ioapic_write_entry(dev->id, i, entry[i]);
1da177e4
LT		 1750
1751 return 0;
1752}
1753
1754static struct sysdev_class ioapic_sysdev_class = {
1755 set_kset_name("ioapic"),
1756 .suspend = ioapic_suspend,
1757 .resume = ioapic_resume,
1758};
1759
1760static int __init ioapic_init_sysfs(void)
1761{
1762 struct sys_device * dev;
1763 int i, size, error = 0;
1764
1765 error = sysdev_class_register(&ioapic_sysdev_class);
1766 if (error)
1767 return error;
1768
1769 for (i = 0; i < nr_ioapics; i++ ) {
1770 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1771 * sizeof(struct IO_APIC_route_entry);
1772 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1773 if (!mp_ioapic_data[i]) {
1774 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1775 continue;
1776 }
1777 memset(mp_ioapic_data[i], 0, size);
1778 dev = &mp_ioapic_data[i]->dev;
1779 dev->id = i;
1780 dev->cls = &ioapic_sysdev_class;
1781 error = sysdev_register(dev);
1782 if (error) {
1783 kfree(mp_ioapic_data[i]);
1784 mp_ioapic_data[i] = NULL;
1785 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1786 continue;
1787 }
1788 }
1789
1790 return 0;
1791}
1792
1793device_initcall(ioapic_init_sysfs);
1794
c4fa0bbf 1795/*
04b9267b 1796 * Dynamic irq allocate and deallocation
c4fa0bbf
EB		 1797 */
1798int create_irq(void)
1799{
04b9267b
EB		 1800 /* Allocate an unused irq */
1801 int irq;
1802 int new;
1803 int vector = 0;
c4fa0bbf 1804 unsigned long flags;
c7111c13 1805 cpumask_t mask;
c4fa0bbf 1806
04b9267b
EB		 1807 irq = -ENOSPC;
1808 spin_lock_irqsave(&vector_lock, flags);
1809 for (new = (NR_IRQS - 1); new >= 0; new--) {
1810 if (platform_legacy_irq(new))
1811 continue;
1812 if (irq_vector[new] != 0)
1813 continue;
c7111c13 1814 vector = __assign_irq_vector(new, TARGET_CPUS, &mask);
04b9267b
EB		 1815 if (likely(vector > 0))
1816 irq = new;
1817 break;
1818 }
1819 spin_unlock_irqrestore(&vector_lock, flags);
c4fa0bbf 1820
04b9267b 1821 if (irq >= 0) {
c4fa0bbf
EB		 1822 dynamic_irq_init(irq);
1823 }
1824 return irq;
1825}
1826
1827void destroy_irq(unsigned int irq)
1828{
1829 unsigned long flags;
c4fa0bbf
EB		 1830
1831 dynamic_irq_cleanup(irq);
1832
1833 spin_lock_irqsave(&vector_lock, flags);
5df0287e 1834 __clear_irq_vector(irq);
c4fa0bbf
EB		 1835 spin_unlock_irqrestore(&vector_lock, flags);
1836}
c4fa0bbf 1837
589e367f
EB		 1838/*
1839 * MSI mesage composition
1840 */
1841#ifdef CONFIG_PCI_MSI
3b7d1921 1842static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
589e367f 1843{
589e367f
EB		 1844 int vector;
1845 unsigned dest;
c7111c13 1846 cpumask_t tmp;
589e367f 1847
c7111c13 1848 vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
589e367f 1849 if (vector >= 0) {
589e367f
EB		 1850 dest = cpu_mask_to_apicid(tmp);
1851
1852 msg->address_hi = MSI_ADDR_BASE_HI;
1853 msg->address_lo =
1854 MSI_ADDR_BASE_LO |
1855 ((INT_DEST_MODE == 0) ?
1856 MSI_ADDR_DEST_MODE_PHYSICAL:
1857 MSI_ADDR_DEST_MODE_LOGICAL) |
1858 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1859 MSI_ADDR_REDIRECTION_CPU:
1860 MSI_ADDR_REDIRECTION_LOWPRI) |
1861 MSI_ADDR_DEST_ID(dest);
1862
1863 msg->data =
1864 MSI_DATA_TRIGGER_EDGE |
1865 MSI_DATA_LEVEL_ASSERT |
1866 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1867 MSI_DATA_DELIVERY_FIXED:
1868 MSI_DATA_DELIVERY_LOWPRI) |
1869 MSI_DATA_VECTOR(vector);
1870 }
1871 return vector;
1872}
1873
3b7d1921
EB		 1874#ifdef CONFIG_SMP
1875static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
589e367f 1876{
3b7d1921
EB		 1877 struct msi_msg msg;
1878 unsigned int dest;
1879 cpumask_t tmp;
589e367f 1880 int vector;
3b7d1921
EB		 1881
1882 cpus_and(tmp, mask, cpu_online_map);
1883 if (cpus_empty(tmp))
1884 tmp = TARGET_CPUS;
1885
1886 cpus_and(mask, tmp, CPU_MASK_ALL);
589e367f 1887
c7111c13 1888 vector = assign_irq_vector(irq, mask, &tmp);
3b7d1921
EB		 1889 if (vector < 0)
1890 return;
550f2299 1891
3b7d1921 1892 dest = cpu_mask_to_apicid(tmp);
589e367f 1893
3b7d1921
EB		 1894 read_msi_msg(irq, &msg);
1895
1896 msg.data &= ~MSI_DATA_VECTOR_MASK;
1897 msg.data |= MSI_DATA_VECTOR(vector);
1898 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1899 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1900
1901 write_msi_msg(irq, &msg);
1902 set_native_irq_info(irq, mask);
589e367f 1903}
3b7d1921 1904#endif /* CONFIG_SMP */
589e367f 1905
3b7d1921
EB		 1906/*
1907 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1908 * which implement the MSI or MSI-X Capability Structure.
1909 */
1910static struct irq_chip msi_chip = {
1911 .name = "PCI-MSI",
1912 .unmask = unmask_msi_irq,
1913 .mask = mask_msi_irq,
1914 .ack = ack_apic_edge,
1915#ifdef CONFIG_SMP
1916 .set_affinity = set_msi_irq_affinity,
1917#endif
1918 .retrigger = ioapic_retrigger_irq,
589e367f
EB		 1919};
1920
3b7d1921
EB		 1921int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev)
1922{
1923 struct msi_msg msg;
1924 int ret;
1925 ret = msi_compose_msg(dev, irq, &msg);
1926 if (ret < 0)
1927 return ret;
1928
1929 write_msi_msg(irq, &msg);
1930
a460e745 1931 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3b7d1921
EB		 1932
1933 return 0;
1934}
1935
1936void arch_teardown_msi_irq(unsigned int irq)
1937{
1938 return;
1939}
1940
1941#endif /* CONFIG_PCI_MSI */
589e367f 1942
8b955b0d
EB		 1943/*
1944 * Hypertransport interrupt support
1945 */
1946#ifdef CONFIG_HT_IRQ
1947
1948#ifdef CONFIG_SMP
1949
1950static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1951{
ec68307c
EB		 1952 struct ht_irq_msg msg;
1953 fetch_ht_irq_msg(irq, &msg);
8b955b0d 1954
ec68307c
EB		 1955 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
1956 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
8b955b0d 1957
ec68307c
EB		 1958 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
1959 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 1960
ec68307c 1961 write_ht_irq_msg(irq, &msg);
8b955b0d
EB		 1962}
1963
1964static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
1965{
1966 unsigned int dest;
1967 cpumask_t tmp;
1968 int vector;
1969
1970 cpus_and(tmp, mask, cpu_online_map);
1971 if (cpus_empty(tmp))
1972 tmp = TARGET_CPUS;
1973
1974 cpus_and(mask, tmp, CPU_MASK_ALL);
1975
c7111c13 1976 vector = assign_irq_vector(irq, mask, &tmp);
8b955b0d
EB		 1977 if (vector < 0)
1978 return;
1979
8b955b0d
EB		 1980 dest = cpu_mask_to_apicid(tmp);
1981
ec68307c 1982 target_ht_irq(irq, dest, vector);
8b955b0d
EB		 1983 set_native_irq_info(irq, mask);
1984}
1985#endif
1986
c37e108d 1987static struct irq_chip ht_irq_chip = {
8b955b0d
EB		 1988 .name = "PCI-HT",
1989 .mask = mask_ht_irq,
1990 .unmask = unmask_ht_irq,
1991 .ack = ack_apic_edge,
1992#ifdef CONFIG_SMP
1993 .set_affinity = set_ht_irq_affinity,
1994#endif
1995 .retrigger = ioapic_retrigger_irq,
1996};
1997
1998int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
1999{
2000 int vector;
c7111c13 2001 cpumask_t tmp;
8b955b0d 2002
c7111c13 2003 vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
8b955b0d 2004 if (vector >= 0) {
ec68307c 2005 struct ht_irq_msg msg;
8b955b0d 2006 unsigned dest;
8b955b0d 2007
8b955b0d
EB		 2008 dest = cpu_mask_to_apicid(tmp);
2009
ec68307c 2010 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 2011
ec68307c
EB		 2012 msg.address_lo =
2013 HT_IRQ_LOW_BASE |
8b955b0d
EB		 2014 HT_IRQ_LOW_DEST_ID(dest) |
2015 HT_IRQ_LOW_VECTOR(vector) |
2016 ((INT_DEST_MODE == 0) ?
2017 HT_IRQ_LOW_DM_PHYSICAL :
2018 HT_IRQ_LOW_DM_LOGICAL) |
2019 HT_IRQ_LOW_RQEOI_EDGE |
2020 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2021 HT_IRQ_LOW_MT_FIXED :
ec68307c
EB		 2022 HT_IRQ_LOW_MT_ARBITRATED) |
2023 HT_IRQ_LOW_IRQ_MASKED;
8b955b0d 2024
ec68307c 2025 write_ht_irq_msg(irq, &msg);
8b955b0d 2026
a460e745
IM		 2027 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2028 handle_edge_irq, "edge");
8b955b0d
EB		 2029 }
2030 return vector;
2031}
2032#endif /* CONFIG_HT_IRQ */
2033
1da177e4
LT		 2034/* --------------------------------------------------------------------------
2035 ACPI-based IOAPIC Configuration
2036 -------------------------------------------------------------------------- */
2037
888ba6c6 2038#ifdef CONFIG_ACPI
1da177e4
LT		 2039
2040#define IO_APIC_MAX_ID 0xFE
2041
1da177e4
LT		 2042int __init io_apic_get_redir_entries (int ioapic)
2043{
2044 union IO_APIC_reg_01 reg_01;
2045 unsigned long flags;
2046
2047 spin_lock_irqsave(&ioapic_lock, flags);
2048 reg_01.raw = io_apic_read(ioapic, 1);
2049 spin_unlock_irqrestore(&ioapic_lock, flags);
2050
2051 return reg_01.bits.entries;
2052}
2053
2054
50eca3eb 2055int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1da177e4
LT		 2056{
2057 struct IO_APIC_route_entry entry;
2058 unsigned long flags;
550f2299
EB		 2059 int vector;
2060 cpumask_t mask;
1da177e4
LT		 2061
2062 if (!IO_APIC_IRQ(irq)) {
2063 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2064 ioapic);
2065 return -EINVAL;
2066 }
2067
550f2299
EB		 2068 /*
2069 * IRQs < 16 are already in the irq_2_pin[] map
2070 */
2071 if (irq >= 16)
2072 add_pin_to_irq(irq, ioapic, pin);
2073
2074
c7111c13 2075 vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
550f2299
EB		 2076 if (vector < 0)
2077 return vector;
2078
1da177e4
LT		 2079 /*
2080 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2081 * Note that we mask (disable) IRQs now -- these get enabled when the
2082 * corresponding device driver registers for this IRQ.
2083 */
2084
2085 memset(&entry,0,sizeof(entry));
2086
2087 entry.delivery_mode = INT_DELIVERY_MODE;
2088 entry.dest_mode = INT_DEST_MODE;
550f2299 2089 entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
50eca3eb
BM		 2090 entry.trigger = triggering;
2091 entry.polarity = polarity;
1da177e4 2092 entry.mask = 1; /* Disabled (masked) */
550f2299 2093 entry.vector = vector & 0xff;
1da177e4
LT		 2094
2095 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2096 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2097 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
50eca3eb 2098 triggering, polarity);
1da177e4 2099
50eca3eb 2100 ioapic_register_intr(irq, entry.vector, triggering);
1da177e4
LT		 2101
2102 if (!ioapic && (irq < 16))
2103 disable_8259A_irq(irq);
2104
eea0e11c
AK		 2105 ioapic_write_entry(ioapic, pin, entry);
2106
1da177e4 2107 spin_lock_irqsave(&ioapic_lock, flags);
04b9267b 2108 set_native_irq_info(irq, TARGET_CPUS);
1da177e4
LT		 2109 spin_unlock_irqrestore(&ioapic_lock, flags);
2110
2111 return 0;
2112}
2113
888ba6c6 2114#endif /* CONFIG_ACPI */
1da177e4
LT		 2115
2116
2117/*
2118 * This function currently is only a helper for the i386 smp boot process where
2119 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2120 * so mask in all cases should simply be TARGET_CPUS
2121 */
54d5d424 2122#ifdef CONFIG_SMP
1da177e4
LT		 2123void __init setup_ioapic_dest(void)
2124{
2125 int pin, ioapic, irq, irq_entry;
2126
2127 if (skip_ioapic_setup == 1)
2128 return;
2129
2130 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2131 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2132 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2133 if (irq_entry == -1)
2134 continue;
2135 irq = pin_2_irq(irq_entry, ioapic, pin);
2136 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2137 }
2138
2139 }
2140}
54d5d424 2141#endif
Linux kernel - Deliverables
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