Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
3 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. | |
4 | * Rest from unknown author(s). | |
5 | * 2004 Andi Kleen. Rewrote most of it. | |
6 | */ | |
7 | ||
8 | #include <linux/init.h> | |
9 | #include <linux/types.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/sched.h> | |
12 | #include <linux/string.h> | |
13 | #include <linux/rcupdate.h> | |
14 | #include <linux/kallsyms.h> | |
15 | #include <linux/sysdev.h> | |
16 | #include <linux/miscdevice.h> | |
17 | #include <linux/fs.h> | |
18 | #include <asm/processor.h> | |
19 | #include <asm/msr.h> | |
20 | #include <asm/mce.h> | |
21 | #include <asm/kdebug.h> | |
22 | #include <asm/uaccess.h> | |
23 | ||
24 | #define MISC_MCELOG_MINOR 227 | |
25 | #define NR_BANKS 5 | |
26 | ||
27 | static int mce_dont_init; | |
28 | ||
29 | /* 0: always panic, 1: panic if deadlock possible, 2: try to avoid panic, | |
30 | 3: never panic or exit (for testing only) */ | |
31 | static int tolerant = 1; | |
32 | static int banks; | |
33 | static unsigned long bank[NR_BANKS] = { [0 ... NR_BANKS-1] = ~0UL }; | |
34 | static unsigned long console_logged; | |
35 | static int notify_user; | |
94ad8474 | 36 | static int rip_msr; |
1da177e4 LT |
37 | |
38 | /* | |
39 | * Lockless MCE logging infrastructure. | |
40 | * This avoids deadlocks on printk locks without having to break locks. Also | |
41 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
42 | */ | |
43 | ||
44 | struct mce_log mcelog = { | |
45 | MCE_LOG_SIGNATURE, | |
46 | MCE_LOG_LEN, | |
47 | }; | |
48 | ||
49 | void mce_log(struct mce *mce) | |
50 | { | |
51 | unsigned next, entry; | |
52 | mce->finished = 0; | |
53 | smp_wmb(); | |
54 | for (;;) { | |
55 | entry = rcu_dereference(mcelog.next); | |
56 | /* When the buffer fills up discard new entries. Assume | |
57 | that the earlier errors are the more interesting. */ | |
58 | if (entry >= MCE_LOG_LEN) { | |
59 | set_bit(MCE_OVERFLOW, &mcelog.flags); | |
60 | return; | |
61 | } | |
62 | /* Old left over entry. Skip. */ | |
63 | if (mcelog.entry[entry].finished) | |
64 | continue; | |
65 | smp_rmb(); | |
66 | next = entry + 1; | |
67 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
68 | break; | |
69 | } | |
70 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
71 | smp_wmb(); | |
72 | mcelog.entry[entry].finished = 1; | |
73 | smp_wmb(); | |
74 | ||
75 | if (!test_and_set_bit(0, &console_logged)) | |
76 | notify_user = 1; | |
77 | } | |
78 | ||
79 | static void print_mce(struct mce *m) | |
80 | { | |
81 | printk(KERN_EMERG "\n" | |
82 | KERN_EMERG | |
83 | "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", | |
84 | m->cpu, m->mcgstatus, m->bank, m->status); | |
85 | if (m->rip) { | |
86 | printk(KERN_EMERG | |
87 | "RIP%s %02x:<%016Lx> ", | |
88 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", | |
89 | m->cs, m->rip); | |
90 | if (m->cs == __KERNEL_CS) | |
91 | print_symbol("{%s}", m->rip); | |
92 | printk("\n"); | |
93 | } | |
94 | printk(KERN_EMERG "TSC %Lx ", m->tsc); | |
95 | if (m->addr) | |
96 | printk("ADDR %Lx ", m->addr); | |
97 | if (m->misc) | |
98 | printk("MISC %Lx ", m->misc); | |
99 | printk("\n"); | |
100 | } | |
101 | ||
102 | static void mce_panic(char *msg, struct mce *backup, unsigned long start) | |
103 | { | |
104 | int i; | |
105 | oops_begin(); | |
106 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
107 | unsigned long tsc = mcelog.entry[i].tsc; | |
108 | if (time_before(tsc, start)) | |
109 | continue; | |
110 | print_mce(&mcelog.entry[i]); | |
111 | if (backup && mcelog.entry[i].tsc == backup->tsc) | |
112 | backup = NULL; | |
113 | } | |
114 | if (backup) | |
115 | print_mce(backup); | |
116 | if (tolerant >= 3) | |
117 | printk("Fake panic: %s\n", msg); | |
118 | else | |
119 | panic(msg); | |
120 | } | |
121 | ||
122 | static int mce_available(struct cpuinfo_x86 *c) | |
123 | { | |
124 | return test_bit(X86_FEATURE_MCE, &c->x86_capability) && | |
125 | test_bit(X86_FEATURE_MCA, &c->x86_capability); | |
126 | } | |
127 | ||
94ad8474 AK |
128 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
129 | { | |
130 | if (regs && (m->mcgstatus & MCG_STATUS_RIPV)) { | |
131 | m->rip = regs->rip; | |
132 | m->cs = regs->cs; | |
133 | } else { | |
134 | m->rip = 0; | |
135 | m->cs = 0; | |
136 | } | |
137 | if (rip_msr) { | |
138 | /* Assume the RIP in the MSR is exact. Is this true? */ | |
139 | m->mcgstatus |= MCG_STATUS_EIPV; | |
140 | rdmsrl(rip_msr, m->rip); | |
141 | m->cs = 0; | |
142 | } | |
143 | } | |
144 | ||
1da177e4 LT |
145 | /* |
146 | * The actual machine check handler | |
147 | */ | |
148 | ||
149 | void do_machine_check(struct pt_regs * regs, long error_code) | |
150 | { | |
151 | struct mce m, panicm; | |
152 | int nowayout = (tolerant < 1); | |
153 | int kill_it = 0; | |
154 | u64 mcestart = 0; | |
155 | int i; | |
156 | int panicm_found = 0; | |
157 | ||
158 | if (regs) | |
159 | notify_die(DIE_NMI, "machine check", regs, error_code, 255, SIGKILL); | |
160 | if (!banks) | |
161 | return; | |
162 | ||
163 | memset(&m, 0, sizeof(struct mce)); | |
164 | m.cpu = hard_smp_processor_id(); | |
165 | rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); | |
166 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
167 | kill_it = 1; | |
168 | ||
169 | rdtscll(mcestart); | |
170 | barrier(); | |
171 | ||
172 | for (i = 0; i < banks; i++) { | |
173 | if (!bank[i]) | |
174 | continue; | |
175 | ||
176 | m.misc = 0; | |
177 | m.addr = 0; | |
178 | m.bank = i; | |
179 | m.tsc = 0; | |
180 | ||
181 | rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status); | |
182 | if ((m.status & MCI_STATUS_VAL) == 0) | |
183 | continue; | |
184 | ||
185 | if (m.status & MCI_STATUS_EN) { | |
186 | /* In theory _OVER could be a nowayout too, but | |
187 | assume any overflowed errors were no fatal. */ | |
188 | nowayout |= !!(m.status & MCI_STATUS_PCC); | |
189 | kill_it |= !!(m.status & MCI_STATUS_UC); | |
190 | } | |
191 | ||
192 | if (m.status & MCI_STATUS_MISCV) | |
193 | rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc); | |
194 | if (m.status & MCI_STATUS_ADDRV) | |
195 | rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr); | |
196 | ||
94ad8474 | 197 | mce_get_rip(&m, regs); |
1da177e4 LT |
198 | if (error_code != -1) |
199 | rdtscll(m.tsc); | |
200 | wrmsrl(MSR_IA32_MC0_STATUS + i*4, 0); | |
201 | mce_log(&m); | |
202 | ||
203 | /* Did this bank cause the exception? */ | |
204 | /* Assume that the bank with uncorrectable errors did it, | |
205 | and that there is only a single one. */ | |
206 | if ((m.status & MCI_STATUS_UC) && (m.status & MCI_STATUS_EN)) { | |
207 | panicm = m; | |
208 | panicm_found = 1; | |
209 | } | |
210 | ||
211 | tainted |= TAINT_MACHINE_CHECK; | |
212 | } | |
213 | ||
214 | /* Never do anything final in the polling timer */ | |
215 | if (!regs) | |
216 | goto out; | |
217 | ||
218 | /* If we didn't find an uncorrectable error, pick | |
219 | the last one (shouldn't happen, just being safe). */ | |
220 | if (!panicm_found) | |
221 | panicm = m; | |
222 | if (nowayout) | |
223 | mce_panic("Machine check", &panicm, mcestart); | |
224 | if (kill_it) { | |
225 | int user_space = 0; | |
226 | ||
227 | if (m.mcgstatus & MCG_STATUS_RIPV) | |
228 | user_space = panicm.rip && (panicm.cs & 3); | |
229 | ||
230 | /* When the machine was in user space and the CPU didn't get | |
231 | confused it's normally not necessary to panic, unless you | |
232 | are paranoid (tolerant == 0) | |
233 | ||
234 | RED-PEN could be more tolerant for MCEs in idle, | |
235 | but most likely they occur at boot anyways, where | |
236 | it is best to just halt the machine. */ | |
237 | if ((!user_space && (panic_on_oops || tolerant < 2)) || | |
238 | (unsigned)current->pid <= 1) | |
239 | mce_panic("Uncorrected machine check", &panicm, mcestart); | |
240 | ||
241 | /* do_exit takes an awful lot of locks and has as | |
242 | slight risk of deadlocking. If you don't want that | |
243 | don't set tolerant >= 2 */ | |
244 | if (tolerant < 3) | |
245 | do_exit(SIGBUS); | |
246 | } | |
247 | ||
248 | out: | |
249 | /* Last thing done in the machine check exception to clear state. */ | |
250 | wrmsrl(MSR_IA32_MCG_STATUS, 0); | |
251 | } | |
252 | ||
253 | /* | |
254 | * Periodic polling timer for "silent" machine check errors. | |
255 | */ | |
256 | ||
257 | static int check_interval = 5 * 60; /* 5 minutes */ | |
258 | static void mcheck_timer(void *data); | |
259 | static DECLARE_WORK(mcheck_work, mcheck_timer, NULL); | |
260 | ||
261 | static void mcheck_check_cpu(void *info) | |
262 | { | |
263 | if (mce_available(¤t_cpu_data)) | |
264 | do_machine_check(NULL, 0); | |
265 | } | |
266 | ||
267 | static void mcheck_timer(void *data) | |
268 | { | |
269 | on_each_cpu(mcheck_check_cpu, NULL, 1, 1); | |
270 | schedule_delayed_work(&mcheck_work, check_interval * HZ); | |
271 | ||
272 | /* | |
273 | * It's ok to read stale data here for notify_user and | |
274 | * console_logged as we'll simply get the updated versions | |
275 | * on the next mcheck_timer execution and atomic operations | |
276 | * on console_logged act as synchronization for notify_user | |
277 | * writes. | |
278 | */ | |
279 | if (notify_user && console_logged) { | |
280 | notify_user = 0; | |
281 | clear_bit(0, &console_logged); | |
282 | printk(KERN_INFO "Machine check events logged\n"); | |
283 | } | |
284 | } | |
285 | ||
286 | ||
287 | static __init int periodic_mcheck_init(void) | |
288 | { | |
289 | if (check_interval) | |
290 | schedule_delayed_work(&mcheck_work, check_interval*HZ); | |
291 | return 0; | |
292 | } | |
293 | __initcall(periodic_mcheck_init); | |
294 | ||
295 | ||
296 | /* | |
297 | * Initialize Machine Checks for a CPU. | |
298 | */ | |
299 | static void mce_init(void *dummy) | |
300 | { | |
301 | u64 cap; | |
302 | int i; | |
303 | ||
304 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
305 | banks = cap & 0xff; | |
306 | if (banks > NR_BANKS) { | |
307 | printk(KERN_INFO "MCE: warning: using only %d banks\n", banks); | |
308 | banks = NR_BANKS; | |
309 | } | |
94ad8474 AK |
310 | /* Use accurate RIP reporting if available. */ |
311 | if ((cap & (1<<9)) && ((cap >> 16) & 0xff) >= 9) | |
312 | rip_msr = MSR_IA32_MCG_EIP; | |
1da177e4 LT |
313 | |
314 | /* Log the machine checks left over from the previous reset. | |
315 | This also clears all registers */ | |
316 | do_machine_check(NULL, -1); | |
317 | ||
318 | set_in_cr4(X86_CR4_MCE); | |
319 | ||
320 | if (cap & MCG_CTL_P) | |
321 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
322 | ||
323 | for (i = 0; i < banks; i++) { | |
324 | wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]); | |
325 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); | |
326 | } | |
327 | } | |
328 | ||
329 | /* Add per CPU specific workarounds here */ | |
e6982c67 | 330 | static void __cpuinit mce_cpu_quirks(struct cpuinfo_x86 *c) |
1da177e4 LT |
331 | { |
332 | /* This should be disabled by the BIOS, but isn't always */ | |
333 | if (c->x86_vendor == X86_VENDOR_AMD && c->x86 == 15) { | |
334 | /* disable GART TBL walk error reporting, which trips off | |
335 | incorrectly with the IOMMU & 3ware & Cerberus. */ | |
336 | clear_bit(10, &bank[4]); | |
337 | } | |
338 | } | |
339 | ||
e6982c67 | 340 | static void __cpuinit mce_cpu_features(struct cpuinfo_x86 *c) |
1da177e4 LT |
341 | { |
342 | switch (c->x86_vendor) { | |
343 | case X86_VENDOR_INTEL: | |
344 | mce_intel_feature_init(c); | |
345 | break; | |
346 | default: | |
347 | break; | |
348 | } | |
349 | } | |
350 | ||
351 | /* | |
352 | * Called for each booted CPU to set up machine checks. | |
353 | * Must be called with preempt off. | |
354 | */ | |
e6982c67 | 355 | void __cpuinit mcheck_init(struct cpuinfo_x86 *c) |
1da177e4 LT |
356 | { |
357 | static cpumask_t mce_cpus __initdata = CPU_MASK_NONE; | |
358 | ||
359 | mce_cpu_quirks(c); | |
360 | ||
361 | if (mce_dont_init || | |
362 | cpu_test_and_set(smp_processor_id(), mce_cpus) || | |
363 | !mce_available(c)) | |
364 | return; | |
365 | ||
366 | mce_init(NULL); | |
367 | mce_cpu_features(c); | |
368 | } | |
369 | ||
370 | /* | |
371 | * Character device to read and clear the MCE log. | |
372 | */ | |
373 | ||
374 | static void collect_tscs(void *data) | |
375 | { | |
376 | unsigned long *cpu_tsc = (unsigned long *)data; | |
377 | rdtscll(cpu_tsc[smp_processor_id()]); | |
378 | } | |
379 | ||
380 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, loff_t *off) | |
381 | { | |
f0de53bb | 382 | unsigned long *cpu_tsc; |
1da177e4 LT |
383 | static DECLARE_MUTEX(mce_read_sem); |
384 | unsigned next; | |
385 | char __user *buf = ubuf; | |
386 | int i, err; | |
387 | ||
f0de53bb AK |
388 | cpu_tsc = kmalloc(NR_CPUS * sizeof(long), GFP_KERNEL); |
389 | if (!cpu_tsc) | |
390 | return -ENOMEM; | |
391 | ||
1da177e4 LT |
392 | down(&mce_read_sem); |
393 | next = rcu_dereference(mcelog.next); | |
394 | ||
395 | /* Only supports full reads right now */ | |
396 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) { | |
397 | up(&mce_read_sem); | |
f0de53bb | 398 | kfree(cpu_tsc); |
1da177e4 LT |
399 | return -EINVAL; |
400 | } | |
401 | ||
402 | err = 0; | |
403 | for (i = 0; i < next; i++) { | |
404 | if (!mcelog.entry[i].finished) | |
405 | continue; | |
406 | smp_rmb(); | |
407 | err |= copy_to_user(buf, mcelog.entry + i, sizeof(struct mce)); | |
408 | buf += sizeof(struct mce); | |
409 | } | |
410 | ||
411 | memset(mcelog.entry, 0, next * sizeof(struct mce)); | |
412 | mcelog.next = 0; | |
413 | ||
414 | synchronize_kernel(); | |
415 | ||
416 | /* Collect entries that were still getting written before the synchronize. */ | |
417 | ||
418 | on_each_cpu(collect_tscs, cpu_tsc, 1, 1); | |
419 | for (i = next; i < MCE_LOG_LEN; i++) { | |
420 | if (mcelog.entry[i].finished && | |
421 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { | |
422 | err |= copy_to_user(buf, mcelog.entry+i, sizeof(struct mce)); | |
423 | smp_rmb(); | |
424 | buf += sizeof(struct mce); | |
425 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); | |
426 | } | |
427 | } | |
428 | up(&mce_read_sem); | |
f0de53bb | 429 | kfree(cpu_tsc); |
1da177e4 LT |
430 | return err ? -EFAULT : buf - ubuf; |
431 | } | |
432 | ||
433 | static int mce_ioctl(struct inode *i, struct file *f,unsigned int cmd, unsigned long arg) | |
434 | { | |
435 | int __user *p = (int __user *)arg; | |
436 | if (!capable(CAP_SYS_ADMIN)) | |
437 | return -EPERM; | |
438 | switch (cmd) { | |
439 | case MCE_GET_RECORD_LEN: | |
440 | return put_user(sizeof(struct mce), p); | |
441 | case MCE_GET_LOG_LEN: | |
442 | return put_user(MCE_LOG_LEN, p); | |
443 | case MCE_GETCLEAR_FLAGS: { | |
444 | unsigned flags; | |
445 | do { | |
446 | flags = mcelog.flags; | |
447 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); | |
448 | return put_user(flags, p); | |
449 | } | |
450 | default: | |
451 | return -ENOTTY; | |
452 | } | |
453 | } | |
454 | ||
455 | static struct file_operations mce_chrdev_ops = { | |
456 | .read = mce_read, | |
457 | .ioctl = mce_ioctl, | |
458 | }; | |
459 | ||
460 | static struct miscdevice mce_log_device = { | |
461 | MISC_MCELOG_MINOR, | |
462 | "mcelog", | |
463 | &mce_chrdev_ops, | |
464 | }; | |
465 | ||
466 | /* | |
467 | * Old style boot options parsing. Only for compatibility. | |
468 | */ | |
469 | ||
470 | static int __init mcheck_disable(char *str) | |
471 | { | |
472 | mce_dont_init = 1; | |
473 | return 0; | |
474 | } | |
475 | ||
476 | /* mce=off disables machine check. Note you can reenable it later | |
477 | using sysfs */ | |
478 | static int __init mcheck_enable(char *str) | |
479 | { | |
480 | if (!strcmp(str, "off")) | |
481 | mce_dont_init = 1; | |
482 | else | |
483 | printk("mce= argument %s ignored. Please use /sys", str); | |
484 | return 0; | |
485 | } | |
486 | ||
487 | __setup("nomce", mcheck_disable); | |
488 | __setup("mce", mcheck_enable); | |
489 | ||
490 | /* | |
491 | * Sysfs support | |
492 | */ | |
493 | ||
494 | /* On resume clear all MCE state. Don't want to see leftovers from the BIOS. */ | |
495 | static int mce_resume(struct sys_device *dev) | |
496 | { | |
497 | on_each_cpu(mce_init, NULL, 1, 1); | |
498 | return 0; | |
499 | } | |
500 | ||
501 | /* Reinit MCEs after user configuration changes */ | |
502 | static void mce_restart(void) | |
503 | { | |
504 | if (check_interval) | |
505 | cancel_delayed_work(&mcheck_work); | |
506 | /* Timer race is harmless here */ | |
507 | on_each_cpu(mce_init, NULL, 1, 1); | |
508 | if (check_interval) | |
509 | schedule_delayed_work(&mcheck_work, check_interval*HZ); | |
510 | } | |
511 | ||
512 | static struct sysdev_class mce_sysclass = { | |
513 | .resume = mce_resume, | |
514 | set_kset_name("machinecheck"), | |
515 | }; | |
516 | ||
517 | static struct sys_device device_mce = { | |
518 | .id = 0, | |
519 | .cls = &mce_sysclass, | |
520 | }; | |
521 | ||
522 | /* Why are there no generic functions for this? */ | |
523 | #define ACCESSOR(name, var, start) \ | |
524 | static ssize_t show_ ## name(struct sys_device *s, char *buf) { \ | |
525 | return sprintf(buf, "%lx\n", (unsigned long)var); \ | |
526 | } \ | |
527 | static ssize_t set_ ## name(struct sys_device *s,const char *buf,size_t siz) { \ | |
528 | char *end; \ | |
529 | unsigned long new = simple_strtoul(buf, &end, 0); \ | |
530 | if (end == buf) return -EINVAL; \ | |
531 | var = new; \ | |
532 | start; \ | |
533 | return end-buf; \ | |
534 | } \ | |
535 | static SYSDEV_ATTR(name, 0644, show_ ## name, set_ ## name); | |
536 | ||
537 | ACCESSOR(bank0ctl,bank[0],mce_restart()) | |
538 | ACCESSOR(bank1ctl,bank[1],mce_restart()) | |
539 | ACCESSOR(bank2ctl,bank[2],mce_restart()) | |
540 | ACCESSOR(bank3ctl,bank[3],mce_restart()) | |
541 | ACCESSOR(bank4ctl,bank[4],mce_restart()) | |
542 | ACCESSOR(tolerant,tolerant,) | |
543 | ACCESSOR(check_interval,check_interval,mce_restart()) | |
544 | ||
e6982c67 | 545 | static __cpuinit int mce_init_device(void) |
1da177e4 LT |
546 | { |
547 | int err; | |
548 | if (!mce_available(&boot_cpu_data)) | |
549 | return -EIO; | |
550 | err = sysdev_class_register(&mce_sysclass); | |
551 | if (!err) | |
552 | err = sysdev_register(&device_mce); | |
553 | if (!err) { | |
554 | /* could create per CPU objects, but it is not worth it. */ | |
555 | sysdev_create_file(&device_mce, &attr_bank0ctl); | |
556 | sysdev_create_file(&device_mce, &attr_bank1ctl); | |
557 | sysdev_create_file(&device_mce, &attr_bank2ctl); | |
558 | sysdev_create_file(&device_mce, &attr_bank3ctl); | |
559 | sysdev_create_file(&device_mce, &attr_bank4ctl); | |
560 | sysdev_create_file(&device_mce, &attr_tolerant); | |
561 | sysdev_create_file(&device_mce, &attr_check_interval); | |
562 | } | |
563 | ||
564 | misc_register(&mce_log_device); | |
565 | return err; | |
566 | ||
567 | } | |
568 | device_initcall(mce_init_device); |