Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/arch/x86_64/nmi.c | |
3 | * | |
4 | * NMI watchdog support on APIC systems | |
5 | * | |
6 | * Started by Ingo Molnar <mingo@redhat.com> | |
7 | * | |
8 | * Fixes: | |
9 | * Mikael Pettersson : AMD K7 support for local APIC NMI watchdog. | |
10 | * Mikael Pettersson : Power Management for local APIC NMI watchdog. | |
11 | * Pavel Machek and | |
12 | * Mikael Pettersson : PM converted to driver model. Disable/enable API. | |
13 | */ | |
14 | ||
1da177e4 | 15 | #include <linux/mm.h> |
1da177e4 | 16 | #include <linux/delay.h> |
1da177e4 | 17 | #include <linux/interrupt.h> |
1da177e4 LT |
18 | #include <linux/module.h> |
19 | #include <linux/sysdev.h> | |
20 | #include <linux/nmi.h> | |
21 | #include <linux/sysctl.h> | |
eddb6fb9 | 22 | #include <linux/kprobes.h> |
1da177e4 LT |
23 | |
24 | #include <asm/smp.h> | |
1da177e4 | 25 | #include <asm/nmi.h> |
1da177e4 LT |
26 | #include <asm/proto.h> |
27 | #include <asm/kdebug.h> | |
553f265f | 28 | #include <asm/mce.h> |
1da177e4 LT |
29 | |
30 | /* | |
31 | * lapic_nmi_owner tracks the ownership of the lapic NMI hardware: | |
32 | * - it may be reserved by some other driver, or not | |
33 | * - when not reserved by some other driver, it may be used for | |
34 | * the NMI watchdog, or not | |
35 | * | |
36 | * This is maintained separately from nmi_active because the NMI | |
37 | * watchdog may also be driven from the I/O APIC timer. | |
38 | */ | |
39 | static DEFINE_SPINLOCK(lapic_nmi_owner_lock); | |
40 | static unsigned int lapic_nmi_owner; | |
41 | #define LAPIC_NMI_WATCHDOG (1<<0) | |
42 | #define LAPIC_NMI_RESERVED (1<<1) | |
43 | ||
44 | /* nmi_active: | |
45 | * +1: the lapic NMI watchdog is active, but can be disabled | |
46 | * 0: the lapic NMI watchdog has not been set up, and cannot | |
47 | * be enabled | |
48 | * -1: the lapic NMI watchdog is disabled, but can be enabled | |
49 | */ | |
50 | int nmi_active; /* oprofile uses this */ | |
51 | int panic_on_timeout; | |
52 | ||
53 | unsigned int nmi_watchdog = NMI_DEFAULT; | |
54 | static unsigned int nmi_hz = HZ; | |
75152114 AK |
55 | static unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */ |
56 | static unsigned int nmi_p4_cccr_val; | |
1da177e4 LT |
57 | |
58 | /* Note that these events don't tick when the CPU idles. This means | |
59 | the frequency varies with CPU load. */ | |
60 | ||
61 | #define K7_EVNTSEL_ENABLE (1 << 22) | |
62 | #define K7_EVNTSEL_INT (1 << 20) | |
63 | #define K7_EVNTSEL_OS (1 << 17) | |
64 | #define K7_EVNTSEL_USR (1 << 16) | |
65 | #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76 | |
66 | #define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING | |
67 | ||
75152114 AK |
68 | #define MSR_P4_MISC_ENABLE 0x1A0 |
69 | #define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7) | |
70 | #define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12) | |
71 | #define MSR_P4_PERFCTR0 0x300 | |
72 | #define MSR_P4_CCCR0 0x360 | |
73 | #define P4_ESCR_EVENT_SELECT(N) ((N)<<25) | |
74 | #define P4_ESCR_OS (1<<3) | |
75 | #define P4_ESCR_USR (1<<2) | |
76 | #define P4_CCCR_OVF_PMI0 (1<<26) | |
77 | #define P4_CCCR_OVF_PMI1 (1<<27) | |
78 | #define P4_CCCR_THRESHOLD(N) ((N)<<20) | |
79 | #define P4_CCCR_COMPLEMENT (1<<19) | |
80 | #define P4_CCCR_COMPARE (1<<18) | |
81 | #define P4_CCCR_REQUIRED (3<<16) | |
82 | #define P4_CCCR_ESCR_SELECT(N) ((N)<<13) | |
83 | #define P4_CCCR_ENABLE (1<<12) | |
84 | /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter | |
85 | CRU_ESCR0 (with any non-null event selector) through a complemented | |
86 | max threshold. [IA32-Vol3, Section 14.9.9] */ | |
87 | #define MSR_P4_IQ_COUNTER0 0x30C | |
88 | #define P4_NMI_CRU_ESCR0 (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR) | |
89 | #define P4_NMI_IQ_CCCR0 \ | |
90 | (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \ | |
91 | P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE) | |
92 | ||
e6982c67 | 93 | static __cpuinit inline int nmi_known_cpu(void) |
75152114 AK |
94 | { |
95 | switch (boot_cpu_data.x86_vendor) { | |
96 | case X86_VENDOR_AMD: | |
97 | return boot_cpu_data.x86 == 15; | |
98 | case X86_VENDOR_INTEL: | |
b07f8915 | 99 | return boot_cpu_data.x86 == 15; |
75152114 AK |
100 | } |
101 | return 0; | |
102 | } | |
1da177e4 LT |
103 | |
104 | /* Run after command line and cpu_init init, but before all other checks */ | |
e6982c67 | 105 | void __cpuinit nmi_watchdog_default(void) |
1da177e4 LT |
106 | { |
107 | if (nmi_watchdog != NMI_DEFAULT) | |
108 | return; | |
75152114 AK |
109 | if (nmi_known_cpu()) |
110 | nmi_watchdog = NMI_LOCAL_APIC; | |
111 | else | |
1da177e4 | 112 | nmi_watchdog = NMI_IO_APIC; |
1da177e4 LT |
113 | } |
114 | ||
75152114 AK |
115 | #ifdef CONFIG_SMP |
116 | /* The performance counters used by NMI_LOCAL_APIC don't trigger when | |
117 | * the CPU is idle. To make sure the NMI watchdog really ticks on all | |
118 | * CPUs during the test make them busy. | |
119 | */ | |
120 | static __init void nmi_cpu_busy(void *data) | |
1da177e4 | 121 | { |
75152114 | 122 | volatile int *endflag = data; |
366c7f55 | 123 | local_irq_enable_in_hardirq(); |
75152114 AK |
124 | /* Intentionally don't use cpu_relax here. This is |
125 | to make sure that the performance counter really ticks, | |
126 | even if there is a simulator or similar that catches the | |
127 | pause instruction. On a real HT machine this is fine because | |
128 | all other CPUs are busy with "useless" delay loops and don't | |
129 | care if they get somewhat less cycles. */ | |
130 | while (*endflag == 0) | |
131 | barrier(); | |
1da177e4 | 132 | } |
75152114 | 133 | #endif |
1da177e4 | 134 | |
75152114 | 135 | int __init check_nmi_watchdog (void) |
1da177e4 | 136 | { |
75152114 | 137 | volatile int endflag = 0; |
ac6b931c | 138 | int *counts; |
1da177e4 LT |
139 | int cpu; |
140 | ||
75152114 AK |
141 | counts = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL); |
142 | if (!counts) | |
143 | return -1; | |
1da177e4 | 144 | |
75152114 | 145 | printk(KERN_INFO "testing NMI watchdog ... "); |
ac6b931c | 146 | |
7554c3f0 | 147 | #ifdef CONFIG_SMP |
75152114 AK |
148 | if (nmi_watchdog == NMI_LOCAL_APIC) |
149 | smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0); | |
7554c3f0 | 150 | #endif |
1da177e4 LT |
151 | |
152 | for (cpu = 0; cpu < NR_CPUS; cpu++) | |
df79efde | 153 | counts[cpu] = cpu_pda(cpu)->__nmi_count; |
1da177e4 LT |
154 | local_irq_enable(); |
155 | mdelay((10*1000)/nmi_hz); // wait 10 ticks | |
156 | ||
394e3902 | 157 | for_each_online_cpu(cpu) { |
df79efde | 158 | if (cpu_pda(cpu)->__nmi_count - counts[cpu] <= 5) { |
75152114 AK |
159 | endflag = 1; |
160 | printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n", | |
1da177e4 | 161 | cpu, |
75152114 | 162 | counts[cpu], |
df79efde | 163 | cpu_pda(cpu)->__nmi_count); |
1da177e4 LT |
164 | nmi_active = 0; |
165 | lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG; | |
75152114 | 166 | nmi_perfctr_msr = 0; |
ac6b931c | 167 | kfree(counts); |
1da177e4 LT |
168 | return -1; |
169 | } | |
170 | } | |
75152114 | 171 | endflag = 1; |
1da177e4 LT |
172 | printk("OK.\n"); |
173 | ||
174 | /* now that we know it works we can reduce NMI frequency to | |
175 | something more reasonable; makes a difference in some configs */ | |
176 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
177 | nmi_hz = 1; | |
178 | ||
ac6b931c | 179 | kfree(counts); |
1da177e4 LT |
180 | return 0; |
181 | } | |
182 | ||
183 | int __init setup_nmi_watchdog(char *str) | |
184 | { | |
185 | int nmi; | |
186 | ||
187 | if (!strncmp(str,"panic",5)) { | |
188 | panic_on_timeout = 1; | |
189 | str = strchr(str, ','); | |
190 | if (!str) | |
191 | return 1; | |
192 | ++str; | |
193 | } | |
194 | ||
195 | get_option(&str, &nmi); | |
196 | ||
197 | if (nmi >= NMI_INVALID) | |
198 | return 0; | |
75152114 | 199 | nmi_watchdog = nmi; |
1da177e4 LT |
200 | return 1; |
201 | } | |
202 | ||
203 | __setup("nmi_watchdog=", setup_nmi_watchdog); | |
204 | ||
205 | static void disable_lapic_nmi_watchdog(void) | |
206 | { | |
207 | if (nmi_active <= 0) | |
208 | return; | |
209 | switch (boot_cpu_data.x86_vendor) { | |
210 | case X86_VENDOR_AMD: | |
211 | wrmsr(MSR_K7_EVNTSEL0, 0, 0); | |
212 | break; | |
213 | case X86_VENDOR_INTEL: | |
75152114 AK |
214 | if (boot_cpu_data.x86 == 15) { |
215 | wrmsr(MSR_P4_IQ_CCCR0, 0, 0); | |
216 | wrmsr(MSR_P4_CRU_ESCR0, 0, 0); | |
217 | } | |
1da177e4 LT |
218 | break; |
219 | } | |
220 | nmi_active = -1; | |
221 | /* tell do_nmi() and others that we're not active any more */ | |
222 | nmi_watchdog = 0; | |
223 | } | |
224 | ||
225 | static void enable_lapic_nmi_watchdog(void) | |
226 | { | |
227 | if (nmi_active < 0) { | |
228 | nmi_watchdog = NMI_LOCAL_APIC; | |
99019e91 | 229 | touch_nmi_watchdog(); |
1da177e4 LT |
230 | setup_apic_nmi_watchdog(); |
231 | } | |
232 | } | |
233 | ||
234 | int reserve_lapic_nmi(void) | |
235 | { | |
236 | unsigned int old_owner; | |
237 | ||
238 | spin_lock(&lapic_nmi_owner_lock); | |
239 | old_owner = lapic_nmi_owner; | |
240 | lapic_nmi_owner |= LAPIC_NMI_RESERVED; | |
241 | spin_unlock(&lapic_nmi_owner_lock); | |
242 | if (old_owner & LAPIC_NMI_RESERVED) | |
243 | return -EBUSY; | |
244 | if (old_owner & LAPIC_NMI_WATCHDOG) | |
245 | disable_lapic_nmi_watchdog(); | |
246 | return 0; | |
247 | } | |
248 | ||
249 | void release_lapic_nmi(void) | |
250 | { | |
251 | unsigned int new_owner; | |
252 | ||
253 | spin_lock(&lapic_nmi_owner_lock); | |
254 | new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED; | |
255 | lapic_nmi_owner = new_owner; | |
256 | spin_unlock(&lapic_nmi_owner_lock); | |
257 | if (new_owner & LAPIC_NMI_WATCHDOG) | |
258 | enable_lapic_nmi_watchdog(); | |
259 | } | |
260 | ||
261 | void disable_timer_nmi_watchdog(void) | |
262 | { | |
263 | if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0)) | |
264 | return; | |
265 | ||
266 | disable_irq(0); | |
267 | unset_nmi_callback(); | |
268 | nmi_active = -1; | |
269 | nmi_watchdog = NMI_NONE; | |
270 | } | |
271 | ||
272 | void enable_timer_nmi_watchdog(void) | |
273 | { | |
274 | if (nmi_active < 0) { | |
275 | nmi_watchdog = NMI_IO_APIC; | |
276 | touch_nmi_watchdog(); | |
277 | nmi_active = 1; | |
278 | enable_irq(0); | |
279 | } | |
280 | } | |
281 | ||
282 | #ifdef CONFIG_PM | |
283 | ||
284 | static int nmi_pm_active; /* nmi_active before suspend */ | |
285 | ||
829ca9a3 | 286 | static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
287 | { |
288 | nmi_pm_active = nmi_active; | |
289 | disable_lapic_nmi_watchdog(); | |
290 | return 0; | |
291 | } | |
292 | ||
293 | static int lapic_nmi_resume(struct sys_device *dev) | |
294 | { | |
295 | if (nmi_pm_active > 0) | |
296 | enable_lapic_nmi_watchdog(); | |
297 | return 0; | |
298 | } | |
299 | ||
300 | static struct sysdev_class nmi_sysclass = { | |
301 | set_kset_name("lapic_nmi"), | |
302 | .resume = lapic_nmi_resume, | |
303 | .suspend = lapic_nmi_suspend, | |
304 | }; | |
305 | ||
306 | static struct sys_device device_lapic_nmi = { | |
307 | .id = 0, | |
308 | .cls = &nmi_sysclass, | |
309 | }; | |
310 | ||
311 | static int __init init_lapic_nmi_sysfs(void) | |
312 | { | |
313 | int error; | |
314 | ||
315 | if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC) | |
316 | return 0; | |
317 | ||
318 | error = sysdev_class_register(&nmi_sysclass); | |
319 | if (!error) | |
320 | error = sysdev_register(&device_lapic_nmi); | |
321 | return error; | |
322 | } | |
323 | /* must come after the local APIC's device_initcall() */ | |
324 | late_initcall(init_lapic_nmi_sysfs); | |
325 | ||
326 | #endif /* CONFIG_PM */ | |
327 | ||
328 | /* | |
329 | * Activate the NMI watchdog via the local APIC. | |
330 | * Original code written by Keith Owens. | |
331 | */ | |
332 | ||
75152114 AK |
333 | static void clear_msr_range(unsigned int base, unsigned int n) |
334 | { | |
335 | unsigned int i; | |
336 | ||
337 | for(i = 0; i < n; ++i) | |
338 | wrmsr(base+i, 0, 0); | |
339 | } | |
340 | ||
1da177e4 LT |
341 | static void setup_k7_watchdog(void) |
342 | { | |
343 | int i; | |
344 | unsigned int evntsel; | |
345 | ||
1da177e4 LT |
346 | nmi_perfctr_msr = MSR_K7_PERFCTR0; |
347 | ||
348 | for(i = 0; i < 4; ++i) { | |
349 | /* Simulator may not support it */ | |
75152114 AK |
350 | if (checking_wrmsrl(MSR_K7_EVNTSEL0+i, 0UL)) { |
351 | nmi_perfctr_msr = 0; | |
1da177e4 | 352 | return; |
75152114 | 353 | } |
1da177e4 LT |
354 | wrmsrl(MSR_K7_PERFCTR0+i, 0UL); |
355 | } | |
356 | ||
357 | evntsel = K7_EVNTSEL_INT | |
358 | | K7_EVNTSEL_OS | |
359 | | K7_EVNTSEL_USR | |
360 | | K7_NMI_EVENT; | |
361 | ||
362 | wrmsr(MSR_K7_EVNTSEL0, evntsel, 0); | |
42ac8ff2 | 363 | wrmsrl(MSR_K7_PERFCTR0, -((u64)cpu_khz * 1000 / nmi_hz)); |
1da177e4 LT |
364 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
365 | evntsel |= K7_EVNTSEL_ENABLE; | |
366 | wrmsr(MSR_K7_EVNTSEL0, evntsel, 0); | |
367 | } | |
368 | ||
75152114 AK |
369 | |
370 | static int setup_p4_watchdog(void) | |
371 | { | |
372 | unsigned int misc_enable, dummy; | |
373 | ||
374 | rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy); | |
375 | if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL)) | |
376 | return 0; | |
377 | ||
378 | nmi_perfctr_msr = MSR_P4_IQ_COUNTER0; | |
379 | nmi_p4_cccr_val = P4_NMI_IQ_CCCR0; | |
380 | #ifdef CONFIG_SMP | |
381 | if (smp_num_siblings == 2) | |
382 | nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1; | |
383 | #endif | |
384 | ||
385 | if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL)) | |
386 | clear_msr_range(0x3F1, 2); | |
387 | /* MSR 0x3F0 seems to have a default value of 0xFC00, but current | |
388 | docs doesn't fully define it, so leave it alone for now. */ | |
389 | if (boot_cpu_data.x86_model >= 0x3) { | |
390 | /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */ | |
391 | clear_msr_range(0x3A0, 26); | |
392 | clear_msr_range(0x3BC, 3); | |
393 | } else { | |
394 | clear_msr_range(0x3A0, 31); | |
395 | } | |
396 | clear_msr_range(0x3C0, 6); | |
397 | clear_msr_range(0x3C8, 6); | |
398 | clear_msr_range(0x3E0, 2); | |
399 | clear_msr_range(MSR_P4_CCCR0, 18); | |
400 | clear_msr_range(MSR_P4_PERFCTR0, 18); | |
401 | ||
402 | wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0); | |
403 | wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0); | |
42ac8ff2 JB |
404 | Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz * 1000UL / nmi_hz)); |
405 | wrmsrl(MSR_P4_IQ_COUNTER0, -((u64)cpu_khz * 1000 / nmi_hz)); | |
75152114 AK |
406 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
407 | wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0); | |
408 | return 1; | |
409 | } | |
410 | ||
1da177e4 LT |
411 | void setup_apic_nmi_watchdog(void) |
412 | { | |
413 | switch (boot_cpu_data.x86_vendor) { | |
414 | case X86_VENDOR_AMD: | |
72e76be2 | 415 | if (boot_cpu_data.x86 != 15) |
1da177e4 LT |
416 | return; |
417 | if (strstr(boot_cpu_data.x86_model_id, "Screwdriver")) | |
418 | return; | |
419 | setup_k7_watchdog(); | |
420 | break; | |
75152114 | 421 | case X86_VENDOR_INTEL: |
b07f8915 AK |
422 | if (boot_cpu_data.x86 != 15) |
423 | return; | |
424 | if (!setup_p4_watchdog()) | |
75152114 AK |
425 | return; |
426 | break; | |
427 | ||
1da177e4 LT |
428 | default: |
429 | return; | |
430 | } | |
431 | lapic_nmi_owner = LAPIC_NMI_WATCHDOG; | |
432 | nmi_active = 1; | |
433 | } | |
434 | ||
435 | /* | |
436 | * the best way to detect whether a CPU has a 'hard lockup' problem | |
437 | * is to check it's local APIC timer IRQ counts. If they are not | |
438 | * changing then that CPU has some problem. | |
439 | * | |
440 | * as these watchdog NMI IRQs are generated on every CPU, we only | |
441 | * have to check the current processor. | |
1da177e4 LT |
442 | */ |
443 | ||
75152114 AK |
444 | static DEFINE_PER_CPU(unsigned, last_irq_sum); |
445 | static DEFINE_PER_CPU(local_t, alert_counter); | |
446 | static DEFINE_PER_CPU(int, nmi_touch); | |
1da177e4 LT |
447 | |
448 | void touch_nmi_watchdog (void) | |
449 | { | |
99019e91 JB |
450 | if (nmi_watchdog > 0) { |
451 | unsigned cpu; | |
1da177e4 | 452 | |
99019e91 JB |
453 | /* |
454 | * Tell other CPUs to reset their alert counters. We cannot | |
455 | * do it ourselves because the alert count increase is not | |
456 | * atomic. | |
457 | */ | |
458 | for_each_present_cpu (cpu) | |
459 | per_cpu(nmi_touch, cpu) = 1; | |
460 | } | |
8446f1d3 IM |
461 | |
462 | touch_softlockup_watchdog(); | |
1da177e4 LT |
463 | } |
464 | ||
eddb6fb9 | 465 | void __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason) |
1da177e4 | 466 | { |
75152114 AK |
467 | int sum; |
468 | int touched = 0; | |
1da177e4 | 469 | |
1da177e4 | 470 | sum = read_pda(apic_timer_irqs); |
75152114 AK |
471 | if (__get_cpu_var(nmi_touch)) { |
472 | __get_cpu_var(nmi_touch) = 0; | |
473 | touched = 1; | |
474 | } | |
553f265f AK |
475 | #ifdef CONFIG_X86_MCE |
476 | /* Could check oops_in_progress here too, but it's safer | |
477 | not too */ | |
478 | if (atomic_read(&mce_entry) > 0) | |
479 | touched = 1; | |
480 | #endif | |
75152114 | 481 | if (!touched && __get_cpu_var(last_irq_sum) == sum) { |
1da177e4 LT |
482 | /* |
483 | * Ayiee, looks like this CPU is stuck ... | |
484 | * wait a few IRQs (5 seconds) before doing the oops ... | |
485 | */ | |
75152114 AK |
486 | local_inc(&__get_cpu_var(alert_counter)); |
487 | if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz) { | |
1da177e4 LT |
488 | if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT) |
489 | == NOTIFY_STOP) { | |
75152114 | 490 | local_set(&__get_cpu_var(alert_counter), 0); |
1da177e4 | 491 | return; |
84781576 CE |
492 | } |
493 | die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs); | |
1da177e4 LT |
494 | } |
495 | } else { | |
75152114 AK |
496 | __get_cpu_var(last_irq_sum) = sum; |
497 | local_set(&__get_cpu_var(alert_counter), 0); | |
1da177e4 | 498 | } |
75152114 AK |
499 | if (nmi_perfctr_msr) { |
500 | if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) { | |
501 | /* | |
502 | * P4 quirks: | |
503 | * - An overflown perfctr will assert its interrupt | |
504 | * until the OVF flag in its CCCR is cleared. | |
505 | * - LVTPC is masked on interrupt and must be | |
506 | * unmasked by the LVTPC handler. | |
507 | */ | |
508 | wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0); | |
509 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
b07f8915 | 510 | } |
42ac8ff2 | 511 | wrmsrl(nmi_perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz)); |
75152114 | 512 | } |
1da177e4 LT |
513 | } |
514 | ||
eddb6fb9 | 515 | static __kprobes int dummy_nmi_callback(struct pt_regs * regs, int cpu) |
1da177e4 LT |
516 | { |
517 | return 0; | |
518 | } | |
519 | ||
520 | static nmi_callback_t nmi_callback = dummy_nmi_callback; | |
521 | ||
eddb6fb9 | 522 | asmlinkage __kprobes void do_nmi(struct pt_regs * regs, long error_code) |
1da177e4 LT |
523 | { |
524 | int cpu = safe_smp_processor_id(); | |
525 | ||
526 | nmi_enter(); | |
527 | add_pda(__nmi_count,1); | |
19306059 | 528 | if (!rcu_dereference(nmi_callback)(regs, cpu)) |
1da177e4 LT |
529 | default_do_nmi(regs); |
530 | nmi_exit(); | |
531 | } | |
532 | ||
533 | void set_nmi_callback(nmi_callback_t callback) | |
534 | { | |
8c914cb7 | 535 | vmalloc_sync_all(); |
19306059 | 536 | rcu_assign_pointer(nmi_callback, callback); |
1da177e4 | 537 | } |
d9a56854 | 538 | EXPORT_SYMBOL_GPL(set_nmi_callback); |
1da177e4 LT |
539 | |
540 | void unset_nmi_callback(void) | |
541 | { | |
542 | nmi_callback = dummy_nmi_callback; | |
543 | } | |
d9a56854 | 544 | EXPORT_SYMBOL_GPL(unset_nmi_callback); |
1da177e4 LT |
545 | |
546 | #ifdef CONFIG_SYSCTL | |
547 | ||
548 | static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu) | |
549 | { | |
550 | unsigned char reason = get_nmi_reason(); | |
551 | char buf[64]; | |
552 | ||
553 | if (!(reason & 0xc0)) { | |
554 | sprintf(buf, "NMI received for unknown reason %02x\n", reason); | |
555 | die_nmi(buf,regs); | |
556 | } | |
557 | return 0; | |
558 | } | |
559 | ||
560 | /* | |
561 | * proc handler for /proc/sys/kernel/unknown_nmi_panic | |
562 | */ | |
563 | int proc_unknown_nmi_panic(struct ctl_table *table, int write, struct file *file, | |
564 | void __user *buffer, size_t *length, loff_t *ppos) | |
565 | { | |
566 | int old_state; | |
567 | ||
568 | old_state = unknown_nmi_panic; | |
569 | proc_dointvec(table, write, file, buffer, length, ppos); | |
570 | if (!!old_state == !!unknown_nmi_panic) | |
571 | return 0; | |
572 | ||
573 | if (unknown_nmi_panic) { | |
574 | if (reserve_lapic_nmi() < 0) { | |
575 | unknown_nmi_panic = 0; | |
576 | return -EBUSY; | |
577 | } else { | |
578 | set_nmi_callback(unknown_nmi_panic_callback); | |
579 | } | |
580 | } else { | |
581 | release_lapic_nmi(); | |
582 | unset_nmi_callback(); | |
583 | } | |
584 | return 0; | |
585 | } | |
586 | ||
587 | #endif | |
588 | ||
589 | EXPORT_SYMBOL(nmi_active); | |
590 | EXPORT_SYMBOL(nmi_watchdog); | |
591 | EXPORT_SYMBOL(reserve_lapic_nmi); | |
592 | EXPORT_SYMBOL(release_lapic_nmi); | |
593 | EXPORT_SYMBOL(disable_timer_nmi_watchdog); | |
594 | EXPORT_SYMBOL(enable_timer_nmi_watchdog); | |
595 | EXPORT_SYMBOL(touch_nmi_watchdog); |