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[PATCH] x86_64: Use X86_FEATURE_CONSTANT_TSC now to clean up Intel speedstep drivers
[deliverable/linux.git] / arch / x86_64 / kernel / setup.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/arch/x86-64/kernel/setup.c
3 *
4 * Copyright (C) 1995 Linus Torvalds
5 *
6 * Nov 2001 Dave Jones <davej@suse.de>
7 * Forked from i386 setup code.
8 *
9 * $Id$
10 */
11
12/*
13 * This file handles the architecture-dependent parts of initialization
14 */
15
16#include <linux/errno.h>
17#include <linux/sched.h>
18#include <linux/kernel.h>
19#include <linux/mm.h>
20#include <linux/stddef.h>
21#include <linux/unistd.h>
22#include <linux/ptrace.h>
23#include <linux/slab.h>
24#include <linux/user.h>
25#include <linux/a.out.h>
26#include <linux/tty.h>
27#include <linux/ioport.h>
28#include <linux/delay.h>
29#include <linux/config.h>
30#include <linux/init.h>
31#include <linux/initrd.h>
32#include <linux/highmem.h>
33#include <linux/bootmem.h>
34#include <linux/module.h>
35#include <asm/processor.h>
36#include <linux/console.h>
37#include <linux/seq_file.h>
aac04b32 38#include <linux/crash_dump.h>
1da177e4
LT		 39#include <linux/root_dev.h>
40#include <linux/pci.h>
41#include <linux/acpi.h>
42#include <linux/kallsyms.h>
43#include <linux/edd.h>
bbfceef4 44#include <linux/mmzone.h>
5f5609df 45#include <linux/kexec.h>
95235ca2 46#include <linux/cpufreq.h>
bbfceef4 47
1da177e4
LT		 48#include <asm/mtrr.h>
49#include <asm/uaccess.h>
50#include <asm/system.h>
51#include <asm/io.h>
52#include <asm/smp.h>
53#include <asm/msr.h>
54#include <asm/desc.h>
55#include <video/edid.h>
56#include <asm/e820.h>
57#include <asm/dma.h>
58#include <asm/mpspec.h>
59#include <asm/mmu_context.h>
60#include <asm/bootsetup.h>
61#include <asm/proto.h>
62#include <asm/setup.h>
63#include <asm/mach_apic.h>
64#include <asm/numa.h>
2bc0414e 65#include <asm/sections.h>
1da177e4
LT		 66
67/*
68 * Machine setup..
69 */
70
6c231b7b 71struct cpuinfo_x86 boot_cpu_data __read_mostly;
1da177e4
LT		 72
73unsigned long mmu_cr4_features;
74
75int acpi_disabled;
76EXPORT_SYMBOL(acpi_disabled);
888ba6c6 77#ifdef CONFIG_ACPI
1da177e4
LT		 78extern int __initdata acpi_ht;
79extern acpi_interrupt_flags acpi_sci_flags;
80int __initdata acpi_force = 0;
81#endif
82
83int acpi_numa __initdata;
84
1da177e4
LT		 85/* Boot loader ID as an integer, for the benefit of proc_dointvec */
86int bootloader_type;
87
88unsigned long saved_video_mode;
89
90#ifdef CONFIG_SWIOTLB
91int swiotlb;
92EXPORT_SYMBOL(swiotlb);
93#endif
94
95/*
96 * Setup options
97 */
98struct drive_info_struct { char dummy[32]; } drive_info;
99struct screen_info screen_info;
100struct sys_desc_table_struct {
101 unsigned short length;
102 unsigned char table[0];
103};
104
105struct edid_info edid_info;
106struct e820map e820;
107
108extern int root_mountflags;
1da177e4
LT		 109
110char command_line[COMMAND_LINE_SIZE];
111
112struct resource standard_io_resources[] = {
113 { .name = "dma1", .start = 0x00, .end = 0x1f,
114 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
115 { .name = "pic1", .start = 0x20, .end = 0x21,
116 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
117 { .name = "timer0", .start = 0x40, .end = 0x43,
118 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
119 { .name = "timer1", .start = 0x50, .end = 0x53,
120 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
121 { .name = "keyboard", .start = 0x60, .end = 0x6f,
122 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
123 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
124 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
125 { .name = "pic2", .start = 0xa0, .end = 0xa1,
126 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
127 { .name = "dma2", .start = 0xc0, .end = 0xdf,
128 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
129 { .name = "fpu", .start = 0xf0, .end = 0xff,
130 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
131};
132
133#define STANDARD_IO_RESOURCES \
134 (sizeof standard_io_resources / sizeof standard_io_resources[0])
135
136#define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
137
138struct resource data_resource = {
139 .name = "Kernel data",
140 .start = 0,
141 .end = 0,
142 .flags = IORESOURCE_RAM,
143};
144struct resource code_resource = {
145 .name = "Kernel code",
146 .start = 0,
147 .end = 0,
148 .flags = IORESOURCE_RAM,
149};
150
151#define IORESOURCE_ROM (IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM)
152
153static struct resource system_rom_resource = {
154 .name = "System ROM",
155 .start = 0xf0000,
156 .end = 0xfffff,
157 .flags = IORESOURCE_ROM,
158};
159
160static struct resource extension_rom_resource = {
161 .name = "Extension ROM",
162 .start = 0xe0000,
163 .end = 0xeffff,
164 .flags = IORESOURCE_ROM,
165};
166
167static struct resource adapter_rom_resources[] = {
168 { .name = "Adapter ROM", .start = 0xc8000, .end = 0,
169 .flags = IORESOURCE_ROM },
170 { .name = "Adapter ROM", .start = 0, .end = 0,
171 .flags = IORESOURCE_ROM },
172 { .name = "Adapter ROM", .start = 0, .end = 0,
173 .flags = IORESOURCE_ROM },
174 { .name = "Adapter ROM", .start = 0, .end = 0,
175 .flags = IORESOURCE_ROM },
176 { .name = "Adapter ROM", .start = 0, .end = 0,
177 .flags = IORESOURCE_ROM },
178 { .name = "Adapter ROM", .start = 0, .end = 0,
179 .flags = IORESOURCE_ROM }
180};
181
182#define ADAPTER_ROM_RESOURCES \
183 (sizeof adapter_rom_resources / sizeof adapter_rom_resources[0])
184
185static struct resource video_rom_resource = {
186 .name = "Video ROM",
187 .start = 0xc0000,
188 .end = 0xc7fff,
189 .flags = IORESOURCE_ROM,
190};
191
192static struct resource video_ram_resource = {
193 .name = "Video RAM area",
194 .start = 0xa0000,
195 .end = 0xbffff,
196 .flags = IORESOURCE_RAM,
197};
198
199#define romsignature(x) (*(unsigned short *)(x) == 0xaa55)
200
201static int __init romchecksum(unsigned char *rom, unsigned long length)
202{
203 unsigned char *p, sum = 0;
204
205 for (p = rom; p < rom + length; p++)
206 sum += *p;
207 return sum == 0;
208}
209
210static void __init probe_roms(void)
211{
212 unsigned long start, length, upper;
213 unsigned char *rom;
214 int i;
215
216 /* video rom */
217 upper = adapter_rom_resources[0].start;
218 for (start = video_rom_resource.start; start < upper; start += 2048) {
219 rom = isa_bus_to_virt(start);
220 if (!romsignature(rom))
221 continue;
222
223 video_rom_resource.start = start;
224
225 /* 0 < length <= 0x7f * 512, historically */
226 length = rom[2] * 512;
227
228 /* if checksum okay, trust length byte */
229 if (length && romchecksum(rom, length))
230 video_rom_resource.end = start + length - 1;
231
232 request_resource(&iomem_resource, &video_rom_resource);
233 break;
234 }
235
236 start = (video_rom_resource.end + 1 + 2047) & ~2047UL;
237 if (start < upper)
238 start = upper;
239
240 /* system rom */
241 request_resource(&iomem_resource, &system_rom_resource);
242 upper = system_rom_resource.start;
243
244 /* check for extension rom (ignore length byte!) */
245 rom = isa_bus_to_virt(extension_rom_resource.start);
246 if (romsignature(rom)) {
247 length = extension_rom_resource.end - extension_rom_resource.start + 1;
248 if (romchecksum(rom, length)) {
249 request_resource(&iomem_resource, &extension_rom_resource);
250 upper = extension_rom_resource.start;
251 }
252 }
253
254 /* check for adapter roms on 2k boundaries */
255 for (i = 0; i < ADAPTER_ROM_RESOURCES && start < upper; start += 2048) {
256 rom = isa_bus_to_virt(start);
257 if (!romsignature(rom))
258 continue;
259
260 /* 0 < length <= 0x7f * 512, historically */
261 length = rom[2] * 512;
262
263 /* but accept any length that fits if checksum okay */
264 if (!length || start + length > upper || !romchecksum(rom, length))
265 continue;
266
267 adapter_rom_resources[i].start = start;
268 adapter_rom_resources[i].end = start + length - 1;
269 request_resource(&iomem_resource, &adapter_rom_resources[i]);
270
271 start = adapter_rom_resources[i++].end & ~2047UL;
272 }
273}
274
275static __init void parse_cmdline_early (char ** cmdline_p)
276{
277 char c = ' ', *to = command_line, *from = COMMAND_LINE;
278 int len = 0;
69cda7b1 279 int userdef = 0;
1da177e4
LT		 280
281 /* Save unparsed command line copy for /proc/cmdline */
282 memcpy(saved_command_line, COMMAND_LINE, COMMAND_LINE_SIZE);
283 saved_command_line[COMMAND_LINE_SIZE-1] = '\0';
284
285 for (;;) {
286 if (c != ' ')
287 goto next_char;
288
289#ifdef CONFIG_SMP
290 /*
291 * If the BIOS enumerates physical processors before logical,
292 * maxcpus=N at enumeration-time can be used to disable HT.
293 */
294 else if (!memcmp(from, "maxcpus=", 8)) {
295 extern unsigned int maxcpus;
296
297 maxcpus = simple_strtoul(from + 8, NULL, 0);
298 }
299#endif
888ba6c6 300#ifdef CONFIG_ACPI
1da177e4
LT		 301 /* "acpi=off" disables both ACPI table parsing and interpreter init */
302 if (!memcmp(from, "acpi=off", 8))
303 disable_acpi();
304
305 if (!memcmp(from, "acpi=force", 10)) {
306 /* add later when we do DMI horrors: */
307 acpi_force = 1;
308 acpi_disabled = 0;
309 }
310
311 /* acpi=ht just means: do ACPI MADT parsing
312 at bootup, but don't enable the full ACPI interpreter */
313 if (!memcmp(from, "acpi=ht", 7)) {
314 if (!acpi_force)
315 disable_acpi();
316 acpi_ht = 1;
317 }
318 else if (!memcmp(from, "pci=noacpi", 10))
319 acpi_disable_pci();
320 else if (!memcmp(from, "acpi=noirq", 10))
321 acpi_noirq_set();
322
323 else if (!memcmp(from, "acpi_sci=edge", 13))
324 acpi_sci_flags.trigger = 1;
325 else if (!memcmp(from, "acpi_sci=level", 14))
326 acpi_sci_flags.trigger = 3;
327 else if (!memcmp(from, "acpi_sci=high", 13))
328 acpi_sci_flags.polarity = 1;
329 else if (!memcmp(from, "acpi_sci=low", 12))
330 acpi_sci_flags.polarity = 3;
331
332 /* acpi=strict disables out-of-spec workarounds */
333 else if (!memcmp(from, "acpi=strict", 11)) {
334 acpi_strict = 1;
335 }
22999244
AK		 336#ifdef CONFIG_X86_IO_APIC
337 else if (!memcmp(from, "acpi_skip_timer_override", 24))
338 acpi_skip_timer_override = 1;
339#endif
1da177e4
LT		 340#endif
341
66759a01
CE		 342 if (!memcmp(from, "disable_timer_pin_1", 19))
343 disable_timer_pin_1 = 1;
344 if (!memcmp(from, "enable_timer_pin_1", 18))
345 disable_timer_pin_1 = -1;
346
1da177e4
LT		 347 if (!memcmp(from, "nolapic", 7) ||
348 !memcmp(from, "disableapic", 11))
349 disable_apic = 1;
350
351 if (!memcmp(from, "noapic", 6))
352 skip_ioapic_setup = 1;
353
354 if (!memcmp(from, "apic", 4)) {
355 skip_ioapic_setup = 0;
356 ioapic_force = 1;
357 }
358
359 if (!memcmp(from, "mem=", 4))
360 parse_memopt(from+4, &from);
361
69cda7b1 362 if (!memcmp(from, "memmap=", 7)) {
363 /* exactmap option is for used defined memory */
364 if (!memcmp(from+7, "exactmap", 8)) {
365#ifdef CONFIG_CRASH_DUMP
366 /* If we are doing a crash dump, we
367 * still need to know the real mem
368 * size before original memory map is
369 * reset.
370 */
371 saved_max_pfn = e820_end_of_ram();
372#endif
373 from += 8+7;
374 end_pfn_map = 0;
375 e820.nr_map = 0;
376 userdef = 1;
377 }
378 else {
379 parse_memmapopt(from+7, &from);
380 userdef = 1;
381 }
382 }
383
2b97690f 384#ifdef CONFIG_NUMA
1da177e4
LT		 385 if (!memcmp(from, "numa=", 5))
386 numa_setup(from+5);
387#endif
388
389#ifdef CONFIG_GART_IOMMU
390 if (!memcmp(from,"iommu=",6)) {
391 iommu_setup(from+6);
392 }
393#endif
394
395 if (!memcmp(from,"oops=panic", 10))
396 panic_on_oops = 1;
397
398 if (!memcmp(from, "noexec=", 7))
399 nonx_setup(from + 7);
400
5f5609df
EB		 401#ifdef CONFIG_KEXEC
402 /* crashkernel=size@addr specifies the location to reserve for
403 * a crash kernel. By reserving this memory we guarantee
404 * that linux never set's it up as a DMA target.
405 * Useful for holding code to do something appropriate
406 * after a kernel panic.
407 */
408 else if (!memcmp(from, "crashkernel=", 12)) {
409 unsigned long size, base;
410 size = memparse(from+12, &from);
411 if (*from == '@') {
412 base = memparse(from+1, &from);
413 /* FIXME: Do I want a sanity check
414 * to validate the memory range?
415 */
416 crashk_res.start = base;
417 crashk_res.end = base + size - 1;
418 }
419 }
420#endif
421
aac04b32
VG		 422#ifdef CONFIG_PROC_VMCORE
423 /* elfcorehdr= specifies the location of elf core header
424 * stored by the crashed kernel. This option will be passed
425 * by kexec loader to the capture kernel.
426 */
427 else if(!memcmp(from, "elfcorehdr=", 11))
428 elfcorehdr_addr = memparse(from+11, &from);
429#endif
1da177e4
LT		 430 next_char:
431 c = *(from++);
432 if (!c)
433 break;
434 if (COMMAND_LINE_SIZE <= ++len)
435 break;
436 *(to++) = c;
437 }
69cda7b1 438 if (userdef) {
439 printk(KERN_INFO "user-defined physical RAM map:\n");
440 e820_print_map("user");
441 }
1da177e4
LT		 442 *to = '\0';
443 *cmdline_p = command_line;
444}
445
2b97690f 446#ifndef CONFIG_NUMA
bbfceef4
MT		 447static void __init
448contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
1da177e4 449{
bbfceef4
MT		 450 unsigned long bootmap_size, bootmap;
451
bbfceef4
MT		 452 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
453 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
454 if (bootmap == -1L)
455 panic("Cannot find bootmem map of size %ld\n",bootmap_size);
456 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
457 e820_bootmem_free(NODE_DATA(0), 0, end_pfn << PAGE_SHIFT);
458 reserve_bootmem(bootmap, bootmap_size);
1da177e4
LT		 459}
460#endif
461
462/* Use inline assembly to define this because the nops are defined
463 as inline assembly strings in the include files and we cannot
464 get them easily into strings. */
465asm("\t.data\nk8nops: "
466 K8_NOP1 K8_NOP2 K8_NOP3 K8_NOP4 K8_NOP5 K8_NOP6
467 K8_NOP7 K8_NOP8);
468
469extern unsigned char k8nops[];
470static unsigned char *k8_nops[ASM_NOP_MAX+1] = {
471 NULL,
472 k8nops,
473 k8nops + 1,
474 k8nops + 1 + 2,
475 k8nops + 1 + 2 + 3,
476 k8nops + 1 + 2 + 3 + 4,
477 k8nops + 1 + 2 + 3 + 4 + 5,
478 k8nops + 1 + 2 + 3 + 4 + 5 + 6,
479 k8nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
480};
481
482/* Replace instructions with better alternatives for this CPU type.
483
484 This runs before SMP is initialized to avoid SMP problems with
485 self modifying code. This implies that assymetric systems where
486 APs have less capabilities than the boot processor are not handled.
487 In this case boot with "noreplacement". */
488void apply_alternatives(void *start, void *end)
489{
490 struct alt_instr *a;
491 int diff, i, k;
492 for (a = start; (void *)a < end; a++) {
493 if (!boot_cpu_has(a->cpuid))
494 continue;
495
496 BUG_ON(a->replacementlen > a->instrlen);
497 __inline_memcpy(a->instr, a->replacement, a->replacementlen);
498 diff = a->instrlen - a->replacementlen;
499
500 /* Pad the rest with nops */
501 for (i = a->replacementlen; diff > 0; diff -= k, i += k) {
502 k = diff;
503 if (k > ASM_NOP_MAX)
504 k = ASM_NOP_MAX;
505 __inline_memcpy(a->instr + i, k8_nops[k], k);
506 }
507 }
508}
509
510static int no_replacement __initdata = 0;
511
512void __init alternative_instructions(void)
513{
514 extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
515 if (no_replacement)
516 return;
517 apply_alternatives(__alt_instructions, __alt_instructions_end);
518}
519
520static int __init noreplacement_setup(char *s)
521{
522 no_replacement = 1;
523 return 0;
524}
525
526__setup("noreplacement", noreplacement_setup);
527
528#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
529struct edd edd;
530#ifdef CONFIG_EDD_MODULE
531EXPORT_SYMBOL(edd);
532#endif
533/**
534 * copy_edd() - Copy the BIOS EDD information
535 * from boot_params into a safe place.
536 *
537 */
538static inline void copy_edd(void)
539{
540 memcpy(edd.mbr_signature, EDD_MBR_SIGNATURE, sizeof(edd.mbr_signature));
541 memcpy(edd.edd_info, EDD_BUF, sizeof(edd.edd_info));
542 edd.mbr_signature_nr = EDD_MBR_SIG_NR;
543 edd.edd_info_nr = EDD_NR;
544}
545#else
546static inline void copy_edd(void)
547{
548}
549#endif
550
551#define EBDA_ADDR_POINTER 0x40E
552static void __init reserve_ebda_region(void)
553{
554 unsigned int addr;
555 /**
556 * there is a real-mode segmented pointer pointing to the
557 * 4K EBDA area at 0x40E
558 */
559 addr = *(unsigned short *)phys_to_virt(EBDA_ADDR_POINTER);
560 addr <<= 4;
561 if (addr)
562 reserve_bootmem_generic(addr, PAGE_SIZE);
563}
564
565void __init setup_arch(char **cmdline_p)
566{
1da177e4
LT		 567 unsigned long kernel_end;
568
569 ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
570 drive_info = DRIVE_INFO;
571 screen_info = SCREEN_INFO;
572 edid_info = EDID_INFO;
573 saved_video_mode = SAVED_VIDEO_MODE;
574 bootloader_type = LOADER_TYPE;
575
576#ifdef CONFIG_BLK_DEV_RAM
577 rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK;
578 rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0);
579 rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0);
580#endif
581 setup_memory_region();
582 copy_edd();
583
584 if (!MOUNT_ROOT_RDONLY)
585 root_mountflags &= ~MS_RDONLY;
586 init_mm.start_code = (unsigned long) &_text;
587 init_mm.end_code = (unsigned long) &_etext;
588 init_mm.end_data = (unsigned long) &_edata;
589 init_mm.brk = (unsigned long) &_end;
590
591 code_resource.start = virt_to_phys(&_text);
592 code_resource.end = virt_to_phys(&_etext)-1;
593 data_resource.start = virt_to_phys(&_etext);
594 data_resource.end = virt_to_phys(&_edata)-1;
595
596 parse_cmdline_early(cmdline_p);
597
598 early_identify_cpu(&boot_cpu_data);
599
600 /*
601 * partially used pages are not usable - thus
602 * we are rounding upwards:
603 */
604 end_pfn = e820_end_of_ram();
605
606 check_efer();
607
608 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
609
f6c2e333
SS		 610 zap_low_mappings(0);
611
888ba6c6 612#ifdef CONFIG_ACPI
1da177e4
LT		 613 /*
614 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
615 * Call this early for SRAT node setup.
616 */
617 acpi_boot_table_init();
618#endif
619
620#ifdef CONFIG_ACPI_NUMA
621 /*
622 * Parse SRAT to discover nodes.
623 */
624 acpi_numa_init();
625#endif
626
2b97690f 627#ifdef CONFIG_NUMA
1da177e4
LT		 628 numa_initmem_init(0, end_pfn);
629#else
bbfceef4 630 contig_initmem_init(0, end_pfn);
1da177e4
LT		 631#endif
632
633 /* Reserve direct mapping */
634 reserve_bootmem_generic(table_start << PAGE_SHIFT,
635 (table_end - table_start) << PAGE_SHIFT);
636
637 /* reserve kernel */
638 kernel_end = round_up(__pa_symbol(&_end),PAGE_SIZE);
639 reserve_bootmem_generic(HIGH_MEMORY, kernel_end - HIGH_MEMORY);
640
641 /*
642 * reserve physical page 0 - it's a special BIOS page on many boxes,
643 * enabling clean reboots, SMP operation, laptop functions.
644 */
645 reserve_bootmem_generic(0, PAGE_SIZE);
646
647 /* reserve ebda region */
648 reserve_ebda_region();
649
650#ifdef CONFIG_SMP
651 /*
652 * But first pinch a few for the stack/trampoline stuff
653 * FIXME: Don't need the extra page at 4K, but need to fix
654 * trampoline before removing it. (see the GDT stuff)
655 */
656 reserve_bootmem_generic(PAGE_SIZE, PAGE_SIZE);
657
658 /* Reserve SMP trampoline */
659 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, PAGE_SIZE);
660#endif
661
662#ifdef CONFIG_ACPI_SLEEP
663 /*
664 * Reserve low memory region for sleep support.
665 */
666 acpi_reserve_bootmem();
667#endif
668#ifdef CONFIG_X86_LOCAL_APIC
669 /*
670 * Find and reserve possible boot-time SMP configuration:
671 */
672 find_smp_config();
673#endif
674#ifdef CONFIG_BLK_DEV_INITRD
675 if (LOADER_TYPE && INITRD_START) {
676 if (INITRD_START + INITRD_SIZE <= (end_pfn << PAGE_SHIFT)) {
677 reserve_bootmem_generic(INITRD_START, INITRD_SIZE);
678 initrd_start =
679 INITRD_START ? INITRD_START + PAGE_OFFSET : 0;
680 initrd_end = initrd_start+INITRD_SIZE;
681 }
682 else {
683 printk(KERN_ERR "initrd extends beyond end of memory "
684 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
685 (unsigned long)(INITRD_START + INITRD_SIZE),
686 (unsigned long)(end_pfn << PAGE_SHIFT));
687 initrd_start = 0;
688 }
689 }
690#endif
5f5609df
EB		 691#ifdef CONFIG_KEXEC
692 if (crashk_res.start != crashk_res.end) {
693 reserve_bootmem(crashk_res.start,
694 crashk_res.end - crashk_res.start + 1);
695 }
696#endif
0d317fb7 697
1da177e4
LT		 698 paging_init();
699
700 check_ioapic();
701
888ba6c6 702#ifdef CONFIG_ACPI
1da177e4
LT		 703 /*
704 * Read APIC and some other early information from ACPI tables.
705 */
706 acpi_boot_init();
707#endif
708
709#ifdef CONFIG_X86_LOCAL_APIC
710 /*
711 * get boot-time SMP configuration:
712 */
713 if (smp_found_config)
714 get_smp_config();
715 init_apic_mappings();
716#endif
717
718 /*
719 * Request address space for all standard RAM and ROM resources
720 * and also for regions reported as reserved by the e820.
721 */
722 probe_roms();
723 e820_reserve_resources();
724
725 request_resource(&iomem_resource, &video_ram_resource);
726
727 {
728 unsigned i;
729 /* request I/O space for devices used on all i[345]86 PCs */
730 for (i = 0; i < STANDARD_IO_RESOURCES; i++)
731 request_resource(&ioport_resource, &standard_io_resources[i]);
732 }
733
a1e97782 734 e820_setup_gap();
1da177e4
LT		 735
736#ifdef CONFIG_GART_IOMMU
737 iommu_hole_init();
738#endif
739
740#ifdef CONFIG_VT
741#if defined(CONFIG_VGA_CONSOLE)
742 conswitchp = &vga_con;
743#elif defined(CONFIG_DUMMY_CONSOLE)
744 conswitchp = &dummy_con;
745#endif
746#endif
747}
748
e6982c67 749static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
1da177e4
LT		 750{
751 unsigned int *v;
752
ebfcaa96 753 if (c->extended_cpuid_level < 0x80000004)
1da177e4
LT		 754 return 0;
755
756 v = (unsigned int *) c->x86_model_id;
757 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
758 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
759 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
760 c->x86_model_id[48] = 0;
761 return 1;
762}
763
764
e6982c67 765static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
1da177e4
LT		 766{
767 unsigned int n, dummy, eax, ebx, ecx, edx;
768
ebfcaa96 769 n = c->extended_cpuid_level;
1da177e4
LT		 770
771 if (n >= 0x80000005) {
772 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
773 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
774 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
775 c->x86_cache_size=(ecx>>24)+(edx>>24);
776 /* On K8 L1 TLB is inclusive, so don't count it */
777 c->x86_tlbsize = 0;
778 }
779
780 if (n >= 0x80000006) {
781 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
782 ecx = cpuid_ecx(0x80000006);
783 c->x86_cache_size = ecx >> 16;
784 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
785
786 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
787 c->x86_cache_size, ecx & 0xFF);
788 }
789
790 if (n >= 0x80000007)
791 cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
792 if (n >= 0x80000008) {
793 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
794 c->x86_virt_bits = (eax >> 8) & 0xff;
795 c->x86_phys_bits = eax & 0xff;
796 }
797}
798
3f098c26
AK		 799#ifdef CONFIG_NUMA
800static int nearby_node(int apicid)
801{
802 int i;
803 for (i = apicid - 1; i >= 0; i--) {
804 int node = apicid_to_node[i];
805 if (node != NUMA_NO_NODE && node_online(node))
806 return node;
807 }
808 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
809 int node = apicid_to_node[i];
810 if (node != NUMA_NO_NODE && node_online(node))
811 return node;
812 }
813 return first_node(node_online_map); /* Shouldn't happen */
814}
815#endif
816
63518644
AK		 817/*
818 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
819 * Assumes number of cores is a power of two.
820 */
821static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
822{
823#ifdef CONFIG_SMP
2942283e 824 int cpu = smp_processor_id();
b41e2939 825 unsigned bits;
3f098c26
AK		 826#ifdef CONFIG_NUMA
827 int node = 0;
0b07e984 828 unsigned apicid = phys_proc_id[cpu];
3f098c26 829#endif
b41e2939
AK		 830
831 bits = 0;
94605eff 832 while ((1 << bits) < c->x86_max_cores)
b41e2939
AK		 833 bits++;
834
835 /* Low order bits define the core id (index of core in socket) */
836 cpu_core_id[cpu] = phys_proc_id[cpu] & ((1 << bits)-1);
837 /* Convert the APIC ID into the socket ID */
838 phys_proc_id[cpu] >>= bits;
63518644
AK		 839
840#ifdef CONFIG_NUMA
3f098c26
AK		 841 node = phys_proc_id[cpu];
842 if (apicid_to_node[apicid] != NUMA_NO_NODE)
843 node = apicid_to_node[apicid];
844 if (!node_online(node)) {
845 /* Two possibilities here:
846 - The CPU is missing memory and no node was created.
847 In that case try picking one from a nearby CPU
848 - The APIC IDs differ from the HyperTransport node IDs
849 which the K8 northbridge parsing fills in.
850 Assume they are all increased by a constant offset,
851 but in the same order as the HT nodeids.
852 If that doesn't result in a usable node fall back to the
853 path for the previous case. */
854 int ht_nodeid = apicid - (phys_proc_id[0] << bits);
855 if (ht_nodeid >= 0 &&
856 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
857 node = apicid_to_node[ht_nodeid];
858 /* Pick a nearby node */
859 if (!node_online(node))
860 node = nearby_node(apicid);
861 }
69d81fcd 862 numa_set_node(cpu, node);
3f098c26
AK		 863
864 printk(KERN_INFO "CPU %d(%d) -> Node %d -> Core %d\n",
94605eff 865 cpu, c->x86_max_cores, node, cpu_core_id[cpu]);
63518644 866#endif
63518644
AK		 867#endif
868}
1da177e4
LT		 869
870static int __init init_amd(struct cpuinfo_x86 *c)
871{
872 int r;
873 int level;
1da177e4 874
bc5e8fdf
LT		 875#ifdef CONFIG_SMP
876 unsigned long value;
877
7d318d77
AK		 878 /*
879 * Disable TLB flush filter by setting HWCR.FFDIS on K8
880 * bit 6 of msr C001_0015
881 *
882 * Errata 63 for SH-B3 steppings
883 * Errata 122 for all steppings (F+ have it disabled by default)
884 */
885 if (c->x86 == 15) {
886 rdmsrl(MSR_K8_HWCR, value);
887 value |= 1 << 6;
888 wrmsrl(MSR_K8_HWCR, value);
889 }
bc5e8fdf
LT		 890#endif
891
1da177e4
LT		 892 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
893 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
894 clear_bit(0*32+31, &c->x86_capability);
895
896 /* C-stepping K8? */
897 level = cpuid_eax(1);
898 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
899 set_bit(X86_FEATURE_K8_C, &c->x86_capability);
900
901 r = get_model_name(c);
902 if (!r) {
903 switch (c->x86) {
904 case 15:
905 /* Should distinguish Models here, but this is only
906 a fallback anyways. */
907 strcpy(c->x86_model_id, "Hammer");
908 break;
909 }
910 }
911 display_cacheinfo(c);
912
130951cc
AK		 913 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
914 if (c->x86_power & (1<<8))
915 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
916
ebfcaa96 917 if (c->extended_cpuid_level >= 0x80000008) {
94605eff
SS		 918 c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
919 if (c->x86_max_cores & (c->x86_max_cores - 1))
920 c->x86_max_cores = 1;
1da177e4 921
63518644 922 amd_detect_cmp(c);
1da177e4
LT		 923 }
924
925 return r;
926}
927
e6982c67 928static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
1da177e4
LT		 929{
930#ifdef CONFIG_SMP
931 u32 eax, ebx, ecx, edx;
94605eff 932 int index_msb, core_bits;
1da177e4 933 int cpu = smp_processor_id();
94605eff
SS		 934
935 cpuid(1, &eax, &ebx, &ecx, &edx);
936
937 c->apicid = phys_pkg_id(0);
938
63518644 939 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
1da177e4
LT		 940 return;
941
1da177e4 942 smp_num_siblings = (ebx & 0xff0000) >> 16;
94605eff 943
1da177e4
LT		 944 if (smp_num_siblings == 1) {
945 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
94605eff
SS		 946 } else if (smp_num_siblings > 1 ) {
947
1da177e4
LT		 948 if (smp_num_siblings > NR_CPUS) {
949 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
950 smp_num_siblings = 1;
951 return;
952 }
94605eff
SS		 953
954 index_msb = get_count_order(smp_num_siblings);
1da177e4 955 phys_proc_id[cpu] = phys_pkg_id(index_msb);
94605eff 956
1da177e4
LT		 957 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
958 phys_proc_id[cpu]);
3dd9d514 959
94605eff 960 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
3dd9d514 961
94605eff
SS		 962 index_msb = get_count_order(smp_num_siblings) ;
963
964 core_bits = get_count_order(c->x86_max_cores);
3dd9d514 965
94605eff
SS		 966 cpu_core_id[cpu] = phys_pkg_id(index_msb) &
967 ((1 << core_bits) - 1);
3dd9d514 968
94605eff 969 if (c->x86_max_cores > 1)
3dd9d514
AK		 970 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
971 cpu_core_id[cpu]);
1da177e4
LT		 972 }
973#endif
974}
975
3dd9d514
AK		 976/*
977 * find out the number of processor cores on the die
978 */
e6982c67 979static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
3dd9d514
AK		 980{
981 unsigned int eax;
982
983 if (c->cpuid_level < 4)
984 return 1;
985
986 __asm__("cpuid"
987 : "=a" (eax)
988 : "0" (4), "c" (0)
989 : "bx", "dx");
990
991 if (eax & 0x1f)
992 return ((eax >> 26) + 1);
993 else
994 return 1;
995}
996
df0cc26b
AK		 997static void srat_detect_node(void)
998{
999#ifdef CONFIG_NUMA
ddea7be0 1000 unsigned node;
df0cc26b
AK		 1001 int cpu = smp_processor_id();
1002
1003 /* Don't do the funky fallback heuristics the AMD version employs
1004 for now. */
ddea7be0 1005 node = apicid_to_node[hard_smp_processor_id()];
df0cc26b
AK		 1006 if (node == NUMA_NO_NODE)
1007 node = 0;
69d81fcd 1008 numa_set_node(cpu, node);
df0cc26b
AK		 1009
1010 if (acpi_numa > 0)
1011 printk(KERN_INFO "CPU %d -> Node %d\n", cpu, node);
1012#endif
1013}
1014
e6982c67 1015static void __cpuinit init_intel(struct cpuinfo_x86 *c)
1da177e4
LT		 1016{
1017 /* Cache sizes */
1018 unsigned n;
1019
1020 init_intel_cacheinfo(c);
ebfcaa96 1021 n = c->extended_cpuid_level;
1da177e4
LT		 1022 if (n >= 0x80000008) {
1023 unsigned eax = cpuid_eax(0x80000008);
1024 c->x86_virt_bits = (eax >> 8) & 0xff;
1025 c->x86_phys_bits = eax & 0xff;
af9c142d
SL		 1026 /* CPUID workaround for Intel 0F34 CPU */
1027 if (c->x86_vendor == X86_VENDOR_INTEL &&
1028 c->x86 == 0xF && c->x86_model == 0x3 &&
1029 c->x86_mask == 0x4)
1030 c->x86_phys_bits = 36;
1da177e4
LT		 1031 }
1032
1033 if (c->x86 == 15)
1034 c->x86_cache_alignment = c->x86_clflush_size * 2;
39b3a791
AK		 1035 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
1036 (c->x86 == 0x6 && c->x86_model >= 0x0e))
c29601e9 1037 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
94605eff 1038 c->x86_max_cores = intel_num_cpu_cores(c);
df0cc26b
AK		 1039
1040 srat_detect_node();
1da177e4
LT		 1041}
1042
672289e9 1043static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
1da177e4
LT		 1044{
1045 char *v = c->x86_vendor_id;
1046
1047 if (!strcmp(v, "AuthenticAMD"))
1048 c->x86_vendor = X86_VENDOR_AMD;
1049 else if (!strcmp(v, "GenuineIntel"))
1050 c->x86_vendor = X86_VENDOR_INTEL;
1051 else
1052 c->x86_vendor = X86_VENDOR_UNKNOWN;
1053}
1054
1055struct cpu_model_info {
1056 int vendor;
1057 int family;
1058 char *model_names[16];
1059};
1060
1061/* Do some early cpuid on the boot CPU to get some parameter that are
1062 needed before check_bugs. Everything advanced is in identify_cpu
1063 below. */
e6982c67 1064void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
1da177e4
LT		 1065{
1066 u32 tfms;
1067
1068 c->loops_per_jiffy = loops_per_jiffy;
1069 c->x86_cache_size = -1;
1070 c->x86_vendor = X86_VENDOR_UNKNOWN;
1071 c->x86_model = c->x86_mask = 0; /* So far unknown... */
1072 c->x86_vendor_id[0] = '\0'; /* Unset */
1073 c->x86_model_id[0] = '\0'; /* Unset */
1074 c->x86_clflush_size = 64;
1075 c->x86_cache_alignment = c->x86_clflush_size;
94605eff 1076 c->x86_max_cores = 1;
ebfcaa96 1077 c->extended_cpuid_level = 0;
1da177e4
LT		 1078 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1079
1080 /* Get vendor name */
1081 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
1082 (unsigned int *)&c->x86_vendor_id[0],
1083 (unsigned int *)&c->x86_vendor_id[8],
1084 (unsigned int *)&c->x86_vendor_id[4]);
1085
1086 get_cpu_vendor(c);
1087
1088 /* Initialize the standard set of capabilities */
1089 /* Note that the vendor-specific code below might override */
1090
1091 /* Intel-defined flags: level 0x00000001 */
1092 if (c->cpuid_level >= 0x00000001) {
1093 __u32 misc;
1094 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
1095 &c->x86_capability[0]);
1096 c->x86 = (tfms >> 8) & 0xf;
1097 c->x86_model = (tfms >> 4) & 0xf;
1098 c->x86_mask = tfms & 0xf;
f5f786d0 1099 if (c->x86 == 0xf)
1da177e4 1100 c->x86 += (tfms >> 20) & 0xff;
f5f786d0 1101 if (c->x86 >= 0x6)
1da177e4 1102 c->x86_model += ((tfms >> 16) & 0xF) << 4;
1da177e4
LT		 1103 if (c->x86_capability[0] & (1<<19))
1104 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
1da177e4
LT		 1105 } else {
1106 /* Have CPUID level 0 only - unheard of */
1107 c->x86 = 4;
1108 }
a158608b
AK		 1109
1110#ifdef CONFIG_SMP
b41e2939 1111 phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
a158608b 1112#endif
1da177e4
LT		 1113}
1114
1115/*
1116 * This does the hard work of actually picking apart the CPU stuff...
1117 */
e6982c67 1118void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1da177e4
LT		 1119{
1120 int i;
1121 u32 xlvl;
1122
1123 early_identify_cpu(c);
1124
1125 /* AMD-defined flags: level 0x80000001 */
1126 xlvl = cpuid_eax(0x80000000);
ebfcaa96 1127 c->extended_cpuid_level = xlvl;
1da177e4
LT		 1128 if ((xlvl & 0xffff0000) == 0x80000000) {
1129 if (xlvl >= 0x80000001) {
1130 c->x86_capability[1] = cpuid_edx(0x80000001);
5b7abc6f 1131 c->x86_capability[6] = cpuid_ecx(0x80000001);
1da177e4
LT		 1132 }
1133 if (xlvl >= 0x80000004)
1134 get_model_name(c); /* Default name */
1135 }
1136
1137 /* Transmeta-defined flags: level 0x80860001 */
1138 xlvl = cpuid_eax(0x80860000);
1139 if ((xlvl & 0xffff0000) == 0x80860000) {
1140 /* Don't set x86_cpuid_level here for now to not confuse. */
1141 if (xlvl >= 0x80860001)
1142 c->x86_capability[2] = cpuid_edx(0x80860001);
1143 }
1144
1145 /*
1146 * Vendor-specific initialization. In this section we
1147 * canonicalize the feature flags, meaning if there are
1148 * features a certain CPU supports which CPUID doesn't
1149 * tell us, CPUID claiming incorrect flags, or other bugs,
1150 * we handle them here.
1151 *
1152 * At the end of this section, c->x86_capability better
1153 * indicate the features this CPU genuinely supports!
1154 */
1155 switch (c->x86_vendor) {
1156 case X86_VENDOR_AMD:
1157 init_amd(c);
1158 break;
1159
1160 case X86_VENDOR_INTEL:
1161 init_intel(c);
1162 break;
1163
1164 case X86_VENDOR_UNKNOWN:
1165 default:
1166 display_cacheinfo(c);
1167 break;
1168 }
1169
1170 select_idle_routine(c);
1171 detect_ht(c);
1da177e4
LT		 1172
1173 /*
1174 * On SMP, boot_cpu_data holds the common feature set between
1175 * all CPUs; so make sure that we indicate which features are
1176 * common between the CPUs. The first time this routine gets
1177 * executed, c == &boot_cpu_data.
1178 */
1179 if (c != &boot_cpu_data) {
1180 /* AND the already accumulated flags with these */
1181 for (i = 0 ; i < NCAPINTS ; i++)
1182 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1183 }
1184
1185#ifdef CONFIG_X86_MCE
1186 mcheck_init(c);
1187#endif
3b520b23
SL		 1188 if (c == &boot_cpu_data)
1189 mtrr_bp_init();
1190 else
1191 mtrr_ap_init();
1da177e4 1192#ifdef CONFIG_NUMA
3019e8eb 1193 numa_add_cpu(smp_processor_id());
1da177e4
LT		 1194#endif
1195}
1196
1197
e6982c67 1198void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1da177e4
LT		 1199{
1200 if (c->x86_model_id[0])
1201 printk("%s", c->x86_model_id);
1202
1203 if (c->x86_mask || c->cpuid_level >= 0)
1204 printk(" stepping %02x\n", c->x86_mask);
1205 else
1206 printk("\n");
1207}
1208
1209/*
1210 * Get CPU information for use by the procfs.
1211 */
1212
1213static int show_cpuinfo(struct seq_file *m, void *v)
1214{
1215 struct cpuinfo_x86 *c = v;
1216
1217 /*
1218 * These flag bits must match the definitions in <asm/cpufeature.h>.
1219 * NULL means this bit is undefined or reserved; either way it doesn't
1220 * have meaning as far as Linux is concerned. Note that it's important
1221 * to realize there is a difference between this table and CPUID -- if
1222 * applications want to get the raw CPUID data, they should access
1223 * /dev/cpu/<cpu_nr>/cpuid instead.
1224 */
1225 static char *x86_cap_flags[] = {
1226 /* Intel-defined */
1227 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
1228 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
1229 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
1230 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", NULL,
1231
1232 /* AMD-defined */
3c3b73b6 1233 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4
LT		 1234 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
1235 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
1236 NULL, "fxsr_opt", NULL, NULL, NULL, "lm", "3dnowext", "3dnow",
1237
1238 /* Transmeta-defined */
1239 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
1240 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1241 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1242 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1243
1244 /* Other (Linux-defined) */
622dcaf9 1245 "cxmmx", NULL, "cyrix_arr", "centaur_mcr", NULL,
c29601e9 1246 "constant_tsc", NULL, NULL,
1da177e4
LT		 1247 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1248 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1249 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1250
1251 /* Intel-defined (#2) */
daedb82d 1252 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", NULL, "est",
1da177e4
LT		 1253 "tm2", NULL, "cid", NULL, NULL, "cx16", "xtpr", NULL,
1254 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1255 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1256
5b7abc6f
PA		 1257 /* VIA/Cyrix/Centaur-defined */
1258 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
1259 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1260 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1261 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1262
1da177e4
LT		 1263 /* AMD-defined (#2) */
1264 "lahf_lm", "cmp_legacy", NULL, NULL, NULL, NULL, NULL, NULL,
1265 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1266 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
5b7abc6f 1267 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4
LT		 1268 };
1269 static char *x86_power_flags[] = {
1270 "ts", /* temperature sensor */
1271 "fid", /* frequency id control */
1272 "vid", /* voltage id control */
1273 "ttp", /* thermal trip */
1274 "tm",
1275 "stc"
130951cc 1276 "?",
39b3a791 1277 /* nothing */ /* constant_tsc - moved to flags */
1da177e4
LT		 1278 };
1279
1280
1281#ifdef CONFIG_SMP
1282 if (!cpu_online(c-cpu_data))
1283 return 0;
1284#endif
1285
1286 seq_printf(m,"processor\t: %u\n"
1287 "vendor_id\t: %s\n"
1288 "cpu family\t: %d\n"
1289 "model\t\t: %d\n"
1290 "model name\t: %s\n",
1291 (unsigned)(c-cpu_data),
1292 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1293 c->x86,
1294 (int)c->x86_model,
1295 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1296
1297 if (c->x86_mask || c->cpuid_level >= 0)
1298 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1299 else
1300 seq_printf(m, "stepping\t: unknown\n");
1301
1302 if (cpu_has(c,X86_FEATURE_TSC)) {
95235ca2
VP		 1303 unsigned int freq = cpufreq_quick_get((unsigned)(c-cpu_data));
1304 if (!freq)
1305 freq = cpu_khz;
1da177e4 1306 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
95235ca2 1307 freq / 1000, (freq % 1000));
1da177e4
LT		 1308 }
1309
1310 /* Cache size */
1311 if (c->x86_cache_size >= 0)
1312 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1313
1314#ifdef CONFIG_SMP
94605eff 1315 if (smp_num_siblings * c->x86_max_cores > 1) {
db468681
AK		 1316 int cpu = c - cpu_data;
1317 seq_printf(m, "physical id\t: %d\n", phys_proc_id[cpu]);
94605eff 1318 seq_printf(m, "siblings\t: %d\n", cpus_weight(cpu_core_map[cpu]));
d31ddaa1 1319 seq_printf(m, "core id\t\t: %d\n", cpu_core_id[cpu]);
94605eff 1320 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
db468681 1321 }
1da177e4
LT		 1322#endif
1323
1324 seq_printf(m,
1325 "fpu\t\t: yes\n"
1326 "fpu_exception\t: yes\n"
1327 "cpuid level\t: %d\n"
1328 "wp\t\t: yes\n"
1329 "flags\t\t:",
1330 c->cpuid_level);
1331
1332 {
1333 int i;
1334 for ( i = 0 ; i < 32*NCAPINTS ; i++ )
1335 if ( test_bit(i, &c->x86_capability) &&
1336 x86_cap_flags[i] != NULL )
1337 seq_printf(m, " %s", x86_cap_flags[i]);
1338 }
1339
1340 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1341 c->loops_per_jiffy/(500000/HZ),
1342 (c->loops_per_jiffy/(5000/HZ)) % 100);
1343
1344 if (c->x86_tlbsize > 0)
1345 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1346 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1347 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1348
1349 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1350 c->x86_phys_bits, c->x86_virt_bits);
1351
1352 seq_printf(m, "power management:");
1353 {
1354 unsigned i;
1355 for (i = 0; i < 32; i++)
1356 if (c->x86_power & (1 << i)) {
1357 if (i < ARRAY_SIZE(x86_power_flags))
1358 seq_printf(m, " %s", x86_power_flags[i]);
1359 else
1360 seq_printf(m, " [%d]", i);
1361 }
1362 }
1da177e4 1363
d31ddaa1 1364 seq_printf(m, "\n\n");
1da177e4
LT		 1365
1366 return 0;
1367}
1368
1369static void *c_start(struct seq_file *m, loff_t *pos)
1370{
1371 return *pos < NR_CPUS ? cpu_data + *pos : NULL;
1372}
1373
1374static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1375{
1376 ++*pos;
1377 return c_start(m, pos);
1378}
1379
1380static void c_stop(struct seq_file *m, void *v)
1381{
1382}
1383
1384struct seq_operations cpuinfo_op = {
1385 .start =c_start,
1386 .next = c_next,
1387 .stop = c_stop,
1388 .show = show_cpuinfo,
1389};
Linux kernel - Deliverables
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