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include/asm-i386/boot.h: This is <asm/boot.h>, not <linux/boot.h>
[deliverable/linux.git] / arch / x86_64 / kernel / setup.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/arch/x86-64/kernel/setup.c
3 *
4 * Copyright (C) 1995 Linus Torvalds
5 *
6 * Nov 2001 Dave Jones <davej@suse.de>
7 * Forked from i386 setup code.
1da177e4
LT		 8 */
9
10/*
11 * This file handles the architecture-dependent parts of initialization
12 */
13
14#include <linux/errno.h>
15#include <linux/sched.h>
16#include <linux/kernel.h>
17#include <linux/mm.h>
18#include <linux/stddef.h>
19#include <linux/unistd.h>
20#include <linux/ptrace.h>
21#include <linux/slab.h>
22#include <linux/user.h>
23#include <linux/a.out.h>
894673ee 24#include <linux/screen_info.h>
1da177e4
LT		 25#include <linux/ioport.h>
26#include <linux/delay.h>
1da177e4
LT		 27#include <linux/init.h>
28#include <linux/initrd.h>
29#include <linux/highmem.h>
30#include <linux/bootmem.h>
31#include <linux/module.h>
32#include <asm/processor.h>
33#include <linux/console.h>
34#include <linux/seq_file.h>
aac04b32 35#include <linux/crash_dump.h>
1da177e4
LT		 36#include <linux/root_dev.h>
37#include <linux/pci.h>
38#include <linux/acpi.h>
39#include <linux/kallsyms.h>
40#include <linux/edd.h>
bbfceef4 41#include <linux/mmzone.h>
5f5609df 42#include <linux/kexec.h>
95235ca2 43#include <linux/cpufreq.h>
e9928674 44#include <linux/dmi.h>
17a941d8 45#include <linux/dma-mapping.h>
681558fd 46#include <linux/ctype.h>
bbfceef4 47
1da177e4
LT		 48#include <asm/mtrr.h>
49#include <asm/uaccess.h>
50#include <asm/system.h>
51#include <asm/io.h>
52#include <asm/smp.h>
53#include <asm/msr.h>
54#include <asm/desc.h>
55#include <video/edid.h>
56#include <asm/e820.h>
57#include <asm/dma.h>
58#include <asm/mpspec.h>
59#include <asm/mmu_context.h>
60#include <asm/bootsetup.h>
61#include <asm/proto.h>
62#include <asm/setup.h>
63#include <asm/mach_apic.h>
64#include <asm/numa.h>
2bc0414e 65#include <asm/sections.h>
f2d3efed 66#include <asm/dmi.h>
1da177e4
LT		 67
68/*
69 * Machine setup..
70 */
71
6c231b7b 72struct cpuinfo_x86 boot_cpu_data __read_mostly;
2ee60e17 73EXPORT_SYMBOL(boot_cpu_data);
1da177e4
LT		 74
75unsigned long mmu_cr4_features;
76
1da177e4
LT		 77/* Boot loader ID as an integer, for the benefit of proc_dointvec */
78int bootloader_type;
79
80unsigned long saved_video_mode;
81
f039b754
AK		 82int force_mwait __cpuinitdata;
83
f2d3efed
AK		 84/*
85 * Early DMI memory
86 */
87int dmi_alloc_index;
88char dmi_alloc_data[DMI_MAX_DATA];
89
1da177e4
LT		 90/*
91 * Setup options
92 */
1da177e4 93struct screen_info screen_info;
2ee60e17 94EXPORT_SYMBOL(screen_info);
1da177e4
LT		 95struct sys_desc_table_struct {
96 unsigned short length;
97 unsigned char table[0];
98};
99
100struct edid_info edid_info;
ba70710e 101EXPORT_SYMBOL_GPL(edid_info);
1da177e4
LT		 102
103extern int root_mountflags;
1da177e4 104
adf48856 105char __initdata command_line[COMMAND_LINE_SIZE];
1da177e4
LT		 106
107struct resource standard_io_resources[] = {
108 { .name = "dma1", .start = 0x00, .end = 0x1f,
109 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
110 { .name = "pic1", .start = 0x20, .end = 0x21,
111 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
112 { .name = "timer0", .start = 0x40, .end = 0x43,
113 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
114 { .name = "timer1", .start = 0x50, .end = 0x53,
115 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
116 { .name = "keyboard", .start = 0x60, .end = 0x6f,
117 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
118 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
119 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
120 { .name = "pic2", .start = 0xa0, .end = 0xa1,
121 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
122 { .name = "dma2", .start = 0xc0, .end = 0xdf,
123 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
124 { .name = "fpu", .start = 0xf0, .end = 0xff,
125 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
126};
127
1da177e4
LT		 128#define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
129
130struct resource data_resource = {
131 .name = "Kernel data",
132 .start = 0,
133 .end = 0,
134 .flags = IORESOURCE_RAM,
135};
136struct resource code_resource = {
137 .name = "Kernel code",
138 .start = 0,
139 .end = 0,
140 .flags = IORESOURCE_RAM,
141};
142
2c8c0e6b
AK		 143#ifdef CONFIG_PROC_VMCORE
144/* elfcorehdr= specifies the location of elf core header
145 * stored by the crashed kernel. This option will be passed
146 * by kexec loader to the capture kernel.
147 */
148static int __init setup_elfcorehdr(char *arg)
681558fd 149{
2c8c0e6b
AK		 150 char *end;
151 if (!arg)
152 return -EINVAL;
153 elfcorehdr_addr = memparse(arg, &end);
154 return end > arg ? 0 : -EINVAL;
681558fd 155}
2c8c0e6b 156early_param("elfcorehdr", setup_elfcorehdr);
e2c03888
AK		 157#endif
158
2b97690f 159#ifndef CONFIG_NUMA
bbfceef4
MT		 160static void __init
161contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
1da177e4 162{
bbfceef4
MT		 163 unsigned long bootmap_size, bootmap;
164
bbfceef4
MT		 165 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
166 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
167 if (bootmap == -1L)
168 panic("Cannot find bootmem map of size %ld\n",bootmap_size);
169 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
5cb248ab
MG		 170 e820_register_active_regions(0, start_pfn, end_pfn);
171 free_bootmem_with_active_regions(0, end_pfn);
bbfceef4 172 reserve_bootmem(bootmap, bootmap_size);
1da177e4
LT		 173}
174#endif
175
1da177e4
LT		 176#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
177struct edd edd;
178#ifdef CONFIG_EDD_MODULE
179EXPORT_SYMBOL(edd);
180#endif
181/**
182 * copy_edd() - Copy the BIOS EDD information
183 * from boot_params into a safe place.
184 *
185 */
186static inline void copy_edd(void)
187{
188 memcpy(edd.mbr_signature, EDD_MBR_SIGNATURE, sizeof(edd.mbr_signature));
189 memcpy(edd.edd_info, EDD_BUF, sizeof(edd.edd_info));
190 edd.mbr_signature_nr = EDD_MBR_SIG_NR;
191 edd.edd_info_nr = EDD_NR;
192}
193#else
194static inline void copy_edd(void)
195{
196}
197#endif
198
199#define EBDA_ADDR_POINTER 0x40E
ac71d12c
AK		 200
201unsigned __initdata ebda_addr;
202unsigned __initdata ebda_size;
203
204static void discover_ebda(void)
1da177e4 205{
ac71d12c 206 /*
1da177e4
LT		 207 * there is a real-mode segmented pointer pointing to the
208 * 4K EBDA area at 0x40E
209 */
bdb96a66 210 ebda_addr = *(unsigned short *)__va(EBDA_ADDR_POINTER);
ac71d12c
AK		 211 ebda_addr <<= 4;
212
bdb96a66 213 ebda_size = *(unsigned short *)__va(ebda_addr);
ac71d12c
AK		 214
215 /* Round EBDA up to pages */
216 if (ebda_size == 0)
217 ebda_size = 1;
218 ebda_size <<= 10;
219 ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
220 if (ebda_size > 64*1024)
221 ebda_size = 64*1024;
1da177e4
LT		 222}
223
224void __init setup_arch(char **cmdline_p)
225{
adf48856 226 printk(KERN_INFO "Command line: %s\n", boot_command_line);
43c85c9c 227
1da177e4 228 ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
1da177e4
LT		 229 screen_info = SCREEN_INFO;
230 edid_info = EDID_INFO;
231 saved_video_mode = SAVED_VIDEO_MODE;
232 bootloader_type = LOADER_TYPE;
233
234#ifdef CONFIG_BLK_DEV_RAM
235 rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK;
236 rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0);
237 rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0);
238#endif
239 setup_memory_region();
240 copy_edd();
241
242 if (!MOUNT_ROOT_RDONLY)
243 root_mountflags &= ~MS_RDONLY;
244 init_mm.start_code = (unsigned long) &_text;
245 init_mm.end_code = (unsigned long) &_etext;
246 init_mm.end_data = (unsigned long) &_edata;
247 init_mm.brk = (unsigned long) &_end;
248
e3ebadd9
LT		 249 code_resource.start = virt_to_phys(&_text);
250 code_resource.end = virt_to_phys(&_etext)-1;
251 data_resource.start = virt_to_phys(&_etext);
252 data_resource.end = virt_to_phys(&_edata)-1;
1da177e4 253
1da177e4
LT		 254 early_identify_cpu(&boot_cpu_data);
255
adf48856 256 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
2c8c0e6b
AK		 257 *cmdline_p = command_line;
258
259 parse_early_param();
260
261 finish_e820_parsing();
9ca33eb6 262
5cb248ab 263 e820_register_active_regions(0, 0, -1UL);
1da177e4
LT		 264 /*
265 * partially used pages are not usable - thus
266 * we are rounding upwards:
267 */
268 end_pfn = e820_end_of_ram();
caff0710 269 num_physpages = end_pfn;
1da177e4
LT		 270
271 check_efer();
272
ac71d12c
AK		 273 discover_ebda();
274
1da177e4
LT		 275 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
276
f2d3efed
AK		 277 dmi_scan_machine();
278
888ba6c6 279#ifdef CONFIG_ACPI
1da177e4
LT		 280 /*
281 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
282 * Call this early for SRAT node setup.
283 */
284 acpi_boot_table_init();
285#endif
286
caff0710
JB		 287 /* How many end-of-memory variables you have, grandma! */
288 max_low_pfn = end_pfn;
289 max_pfn = end_pfn;
290 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
291
5cb248ab
MG		 292 /* Remove active ranges so rediscovery with NUMA-awareness happens */
293 remove_all_active_ranges();
294
1da177e4
LT		 295#ifdef CONFIG_ACPI_NUMA
296 /*
297 * Parse SRAT to discover nodes.
298 */
299 acpi_numa_init();
300#endif
301
2b97690f 302#ifdef CONFIG_NUMA
1da177e4
LT		 303 numa_initmem_init(0, end_pfn);
304#else
bbfceef4 305 contig_initmem_init(0, end_pfn);
1da177e4
LT		 306#endif
307
308 /* Reserve direct mapping */
309 reserve_bootmem_generic(table_start << PAGE_SHIFT,
310 (table_end - table_start) << PAGE_SHIFT);
311
312 /* reserve kernel */
ceee8822
AK		 313 reserve_bootmem_generic(__pa_symbol(&_text),
314 __pa_symbol(&_end) - __pa_symbol(&_text));
1da177e4
LT		 315
316 /*
317 * reserve physical page 0 - it's a special BIOS page on many boxes,
318 * enabling clean reboots, SMP operation, laptop functions.
319 */
320 reserve_bootmem_generic(0, PAGE_SIZE);
321
322 /* reserve ebda region */
ac71d12c
AK		 323 if (ebda_addr)
324 reserve_bootmem_generic(ebda_addr, ebda_size);
076422d2
AS		 325#ifdef CONFIG_NUMA
326 /* reserve nodemap region */
327 if (nodemap_addr)
328 reserve_bootmem_generic(nodemap_addr, nodemap_size);
329#endif
1da177e4
LT		 330
331#ifdef CONFIG_SMP
1da177e4 332 /* Reserve SMP trampoline */
90b1c208 333 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, 2*PAGE_SIZE);
1da177e4
LT		 334#endif
335
336#ifdef CONFIG_ACPI_SLEEP
337 /*
338 * Reserve low memory region for sleep support.
339 */
340 acpi_reserve_bootmem();
341#endif
1da177e4
LT		 342 /*
343 * Find and reserve possible boot-time SMP configuration:
344 */
345 find_smp_config();
1da177e4
LT		 346#ifdef CONFIG_BLK_DEV_INITRD
347 if (LOADER_TYPE && INITRD_START) {
348 if (INITRD_START + INITRD_SIZE <= (end_pfn << PAGE_SHIFT)) {
349 reserve_bootmem_generic(INITRD_START, INITRD_SIZE);
19e5d9c0 350 initrd_start = INITRD_START + PAGE_OFFSET;
1da177e4
LT		 351 initrd_end = initrd_start+INITRD_SIZE;
352 }
353 else {
354 printk(KERN_ERR "initrd extends beyond end of memory "
355 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
356 (unsigned long)(INITRD_START + INITRD_SIZE),
357 (unsigned long)(end_pfn << PAGE_SHIFT));
358 initrd_start = 0;
359 }
360 }
361#endif
5f5609df
EB		 362#ifdef CONFIG_KEXEC
363 if (crashk_res.start != crashk_res.end) {
00212fef 364 reserve_bootmem_generic(crashk_res.start,
5f5609df
EB		 365 crashk_res.end - crashk_res.start + 1);
366 }
367#endif
0d317fb7 368
1da177e4
LT		 369 paging_init();
370
f157cbb1 371#ifdef CONFIG_PCI
dfa4698c 372 early_quirks();
f157cbb1 373#endif
1da177e4 374
51f62e18
AR		 375 /*
376 * set this early, so we dont allocate cpu0
377 * if MADT list doesnt list BSP first
378 * mpparse.c/MP_processor_info() allocates logical cpu numbers.
379 */
380 cpu_set(0, cpu_present_map);
888ba6c6 381#ifdef CONFIG_ACPI
1da177e4
LT		 382 /*
383 * Read APIC and some other early information from ACPI tables.
384 */
385 acpi_boot_init();
386#endif
387
05b3cbd8
RT		 388 init_cpu_to_node();
389
1da177e4
LT		 390 /*
391 * get boot-time SMP configuration:
392 */
393 if (smp_found_config)
394 get_smp_config();
395 init_apic_mappings();
1da177e4
LT		 396
397 /*
fc986db4
AK		 398 * We trust e820 completely. No explicit ROM probing in memory.
399 */
1da177e4 400 e820_reserve_resources();
e8eff5ac 401 e820_mark_nosave_regions();
1da177e4 402
1da177e4
LT		 403 {
404 unsigned i;
405 /* request I/O space for devices used on all i[345]86 PCs */
9d0ef4fd 406 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
1da177e4
LT		 407 request_resource(&ioport_resource, &standard_io_resources[i]);
408 }
409
a1e97782 410 e820_setup_gap();
1da177e4 411
1da177e4
LT		 412#ifdef CONFIG_VT
413#if defined(CONFIG_VGA_CONSOLE)
414 conswitchp = &vga_con;
415#elif defined(CONFIG_DUMMY_CONSOLE)
416 conswitchp = &dummy_con;
417#endif
418#endif
419}
420
e6982c67 421static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
1da177e4
LT		 422{
423 unsigned int *v;
424
ebfcaa96 425 if (c->extended_cpuid_level < 0x80000004)
1da177e4
LT		 426 return 0;
427
428 v = (unsigned int *) c->x86_model_id;
429 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
430 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
431 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
432 c->x86_model_id[48] = 0;
433 return 1;
434}
435
436
e6982c67 437static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
1da177e4
LT		 438{
439 unsigned int n, dummy, eax, ebx, ecx, edx;
440
ebfcaa96 441 n = c->extended_cpuid_level;
1da177e4
LT		 442
443 if (n >= 0x80000005) {
444 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
445 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
446 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
447 c->x86_cache_size=(ecx>>24)+(edx>>24);
448 /* On K8 L1 TLB is inclusive, so don't count it */
449 c->x86_tlbsize = 0;
450 }
451
452 if (n >= 0x80000006) {
453 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
454 ecx = cpuid_ecx(0x80000006);
455 c->x86_cache_size = ecx >> 16;
456 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
457
458 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
459 c->x86_cache_size, ecx & 0xFF);
460 }
461
462 if (n >= 0x80000007)
463 cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
464 if (n >= 0x80000008) {
465 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
466 c->x86_virt_bits = (eax >> 8) & 0xff;
467 c->x86_phys_bits = eax & 0xff;
468 }
469}
470
3f098c26
AK		 471#ifdef CONFIG_NUMA
472static int nearby_node(int apicid)
473{
474 int i;
475 for (i = apicid - 1; i >= 0; i--) {
476 int node = apicid_to_node[i];
477 if (node != NUMA_NO_NODE && node_online(node))
478 return node;
479 }
480 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
481 int node = apicid_to_node[i];
482 if (node != NUMA_NO_NODE && node_online(node))
483 return node;
484 }
485 return first_node(node_online_map); /* Shouldn't happen */
486}
487#endif
488
63518644
AK		 489/*
490 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
491 * Assumes number of cores is a power of two.
492 */
493static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
494{
495#ifdef CONFIG_SMP
b41e2939 496 unsigned bits;
3f098c26 497#ifdef CONFIG_NUMA
f3fa8ebc 498 int cpu = smp_processor_id();
3f098c26 499 int node = 0;
60c1bc82 500 unsigned apicid = hard_smp_processor_id();
3f098c26 501#endif
faee9a5d 502 unsigned ecx = cpuid_ecx(0x80000008);
b41e2939 503
faee9a5d 504 c->x86_max_cores = (ecx & 0xff) + 1;
b41e2939 505
faee9a5d
AK		 506 /* CPU telling us the core id bits shift? */
507 bits = (ecx >> 12) & 0xF;
508
509 /* Otherwise recompute */
510 if (bits == 0) {
511 while ((1 << bits) < c->x86_max_cores)
512 bits++;
513 }
b41e2939
AK		 514
515 /* Low order bits define the core id (index of core in socket) */
f3fa8ebc 516 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
b41e2939 517 /* Convert the APIC ID into the socket ID */
f3fa8ebc 518 c->phys_proc_id = phys_pkg_id(bits);
63518644
AK		 519
520#ifdef CONFIG_NUMA
f3fa8ebc 521 node = c->phys_proc_id;
3f098c26
AK		 522 if (apicid_to_node[apicid] != NUMA_NO_NODE)
523 node = apicid_to_node[apicid];
524 if (!node_online(node)) {
525 /* Two possibilities here:
526 - The CPU is missing memory and no node was created.
527 In that case try picking one from a nearby CPU
528 - The APIC IDs differ from the HyperTransport node IDs
529 which the K8 northbridge parsing fills in.
530 Assume they are all increased by a constant offset,
531 but in the same order as the HT nodeids.
532 If that doesn't result in a usable node fall back to the
533 path for the previous case. */
f3fa8ebc 534 int ht_nodeid = apicid - (cpu_data[0].phys_proc_id << bits);
3f098c26
AK		 535 if (ht_nodeid >= 0 &&
536 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
537 node = apicid_to_node[ht_nodeid];
538 /* Pick a nearby node */
539 if (!node_online(node))
540 node = nearby_node(apicid);
541 }
69d81fcd 542 numa_set_node(cpu, node);
3f098c26 543
e42f9437 544 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
63518644 545#endif
63518644
AK		 546#endif
547}
1da177e4 548
ed77504b 549static void __cpuinit init_amd(struct cpuinfo_x86 *c)
1da177e4 550{
7bcd3f34 551 unsigned level;
1da177e4 552
bc5e8fdf
LT		 553#ifdef CONFIG_SMP
554 unsigned long value;
555
7d318d77
AK		 556 /*
557 * Disable TLB flush filter by setting HWCR.FFDIS on K8
558 * bit 6 of msr C001_0015
559 *
560 * Errata 63 for SH-B3 steppings
561 * Errata 122 for all steppings (F+ have it disabled by default)
562 */
563 if (c->x86 == 15) {
564 rdmsrl(MSR_K8_HWCR, value);
565 value |= 1 << 6;
566 wrmsrl(MSR_K8_HWCR, value);
567 }
bc5e8fdf
LT		 568#endif
569
1da177e4
LT		 570 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
571 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
572 clear_bit(0*32+31, &c->x86_capability);
573
7bcd3f34
AK		 574 /* On C+ stepping K8 rep microcode works well for copy/memset */
575 level = cpuid_eax(1);
576 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58))
577 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
578
18bd057b
AK		 579 /* Enable workaround for FXSAVE leak */
580 if (c->x86 >= 6)
581 set_bit(X86_FEATURE_FXSAVE_LEAK, &c->x86_capability);
582
e42f9437
RS		 583 level = get_model_name(c);
584 if (!level) {
1da177e4
LT		 585 switch (c->x86) {
586 case 15:
587 /* Should distinguish Models here, but this is only
588 a fallback anyways. */
589 strcpy(c->x86_model_id, "Hammer");
590 break;
591 }
592 }
593 display_cacheinfo(c);
594
130951cc
AK		 595 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
596 if (c->x86_power & (1<<8))
597 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
598
faee9a5d
AK		 599 /* Multi core CPU? */
600 if (c->extended_cpuid_level >= 0x80000008)
63518644 601 amd_detect_cmp(c);
1da177e4 602
240cd6a8
AK		 603 /* Fix cpuid4 emulation for more */
604 num_cache_leaves = 3;
2049336f 605
61677965
AK		 606 /* RDTSC can be speculated around */
607 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
f039b754
AK		 608
609 /* Family 10 doesn't support C states in MWAIT so don't use it */
610 if (c->x86 == 0x10 && !force_mwait)
611 clear_bit(X86_FEATURE_MWAIT, &c->x86_capability);
1da177e4
LT		 612}
613
e6982c67 614static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
1da177e4
LT		 615{
616#ifdef CONFIG_SMP
617 u32 eax, ebx, ecx, edx;
94605eff 618 int index_msb, core_bits;
94605eff
SS		 619
620 cpuid(1, &eax, &ebx, &ecx, &edx);
621
94605eff 622
e42f9437 623 if (!cpu_has(c, X86_FEATURE_HT))
1da177e4 624 return;
e42f9437
RS		 625 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
626 goto out;
1da177e4 627
1da177e4 628 smp_num_siblings = (ebx & 0xff0000) >> 16;
94605eff 629
1da177e4
LT		 630 if (smp_num_siblings == 1) {
631 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
94605eff
SS		 632 } else if (smp_num_siblings > 1 ) {
633
1da177e4
LT		 634 if (smp_num_siblings > NR_CPUS) {
635 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
636 smp_num_siblings = 1;
637 return;
638 }
94605eff
SS		 639
640 index_msb = get_count_order(smp_num_siblings);
f3fa8ebc 641 c->phys_proc_id = phys_pkg_id(index_msb);
3dd9d514 642
94605eff 643 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
3dd9d514 644
94605eff
SS		 645 index_msb = get_count_order(smp_num_siblings) ;
646
647 core_bits = get_count_order(c->x86_max_cores);
3dd9d514 648
f3fa8ebc 649 c->cpu_core_id = phys_pkg_id(index_msb) &
94605eff 650 ((1 << core_bits) - 1);
1da177e4 651 }
e42f9437
RS		 652out:
653 if ((c->x86_max_cores * smp_num_siblings) > 1) {
654 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", c->phys_proc_id);
655 printk(KERN_INFO "CPU: Processor Core ID: %d\n", c->cpu_core_id);
656 }
657
1da177e4
LT		 658#endif
659}
660
3dd9d514
AK		 661/*
662 * find out the number of processor cores on the die
663 */
e6982c67 664static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
3dd9d514 665{
2bbc419f 666 unsigned int eax, t;
3dd9d514
AK		 667
668 if (c->cpuid_level < 4)
669 return 1;
670
2bbc419f 671 cpuid_count(4, 0, &eax, &t, &t, &t);
3dd9d514
AK		 672
673 if (eax & 0x1f)
674 return ((eax >> 26) + 1);
675 else
676 return 1;
677}
678
df0cc26b
AK		 679static void srat_detect_node(void)
680{
681#ifdef CONFIG_NUMA
ddea7be0 682 unsigned node;
df0cc26b 683 int cpu = smp_processor_id();
e42f9437 684 int apicid = hard_smp_processor_id();
df0cc26b
AK		 685
686 /* Don't do the funky fallback heuristics the AMD version employs
687 for now. */
e42f9437 688 node = apicid_to_node[apicid];
df0cc26b 689 if (node == NUMA_NO_NODE)
0d015324 690 node = first_node(node_online_map);
69d81fcd 691 numa_set_node(cpu, node);
df0cc26b 692
c31fbb1a 693 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
df0cc26b
AK		 694#endif
695}
696
e6982c67 697static void __cpuinit init_intel(struct cpuinfo_x86 *c)
1da177e4
LT		 698{
699 /* Cache sizes */
700 unsigned n;
701
702 init_intel_cacheinfo(c);
0080e667
VP		 703 if (c->cpuid_level > 9 ) {
704 unsigned eax = cpuid_eax(10);
705 /* Check for version and the number of counters */
706 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
707 set_bit(X86_FEATURE_ARCH_PERFMON, &c->x86_capability);
708 }
709
36b2a8d5
SE		 710 if (cpu_has_ds) {
711 unsigned int l1, l2;
712 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
ee58fad5
SE		 713 if (!(l1 & (1<<11)))
714 set_bit(X86_FEATURE_BTS, c->x86_capability);
36b2a8d5
SE		 715 if (!(l1 & (1<<12)))
716 set_bit(X86_FEATURE_PEBS, c->x86_capability);
717 }
718
ebfcaa96 719 n = c->extended_cpuid_level;
1da177e4
LT		 720 if (n >= 0x80000008) {
721 unsigned eax = cpuid_eax(0x80000008);
722 c->x86_virt_bits = (eax >> 8) & 0xff;
723 c->x86_phys_bits = eax & 0xff;
af9c142d
SL		 724 /* CPUID workaround for Intel 0F34 CPU */
725 if (c->x86_vendor == X86_VENDOR_INTEL &&
726 c->x86 == 0xF && c->x86_model == 0x3 &&
727 c->x86_mask == 0x4)
728 c->x86_phys_bits = 36;
1da177e4
LT		 729 }
730
731 if (c->x86 == 15)
732 c->x86_cache_alignment = c->x86_clflush_size * 2;
39b3a791
AK		 733 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
734 (c->x86 == 0x6 && c->x86_model >= 0x0e))
c29601e9 735 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
27fbe5b2
AK		 736 if (c->x86 == 6)
737 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
f3d73707
AV		 738 if (c->x86 == 15)
739 set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
740 else
741 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
94605eff 742 c->x86_max_cores = intel_num_cpu_cores(c);
df0cc26b
AK		 743
744 srat_detect_node();
1da177e4
LT		 745}
746
672289e9 747static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
1da177e4
LT		 748{
749 char *v = c->x86_vendor_id;
750
751 if (!strcmp(v, "AuthenticAMD"))
752 c->x86_vendor = X86_VENDOR_AMD;
753 else if (!strcmp(v, "GenuineIntel"))
754 c->x86_vendor = X86_VENDOR_INTEL;
755 else
756 c->x86_vendor = X86_VENDOR_UNKNOWN;
757}
758
759struct cpu_model_info {
760 int vendor;
761 int family;
762 char *model_names[16];
763};
764
765/* Do some early cpuid on the boot CPU to get some parameter that are
766 needed before check_bugs. Everything advanced is in identify_cpu
767 below. */
e6982c67 768void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
1da177e4
LT		 769{
770 u32 tfms;
771
772 c->loops_per_jiffy = loops_per_jiffy;
773 c->x86_cache_size = -1;
774 c->x86_vendor = X86_VENDOR_UNKNOWN;
775 c->x86_model = c->x86_mask = 0; /* So far unknown... */
776 c->x86_vendor_id[0] = '\0'; /* Unset */
777 c->x86_model_id[0] = '\0'; /* Unset */
778 c->x86_clflush_size = 64;
779 c->x86_cache_alignment = c->x86_clflush_size;
94605eff 780 c->x86_max_cores = 1;
ebfcaa96 781 c->extended_cpuid_level = 0;
1da177e4
LT		 782 memset(&c->x86_capability, 0, sizeof c->x86_capability);
783
784 /* Get vendor name */
785 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
786 (unsigned int *)&c->x86_vendor_id[0],
787 (unsigned int *)&c->x86_vendor_id[8],
788 (unsigned int *)&c->x86_vendor_id[4]);
789
790 get_cpu_vendor(c);
791
792 /* Initialize the standard set of capabilities */
793 /* Note that the vendor-specific code below might override */
794
795 /* Intel-defined flags: level 0x00000001 */
796 if (c->cpuid_level >= 0x00000001) {
797 __u32 misc;
798 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
799 &c->x86_capability[0]);
800 c->x86 = (tfms >> 8) & 0xf;
801 c->x86_model = (tfms >> 4) & 0xf;
802 c->x86_mask = tfms & 0xf;
f5f786d0 803 if (c->x86 == 0xf)
1da177e4 804 c->x86 += (tfms >> 20) & 0xff;
f5f786d0 805 if (c->x86 >= 0x6)
1da177e4 806 c->x86_model += ((tfms >> 16) & 0xF) << 4;
1da177e4
LT		 807 if (c->x86_capability[0] & (1<<19))
808 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
1da177e4
LT		 809 } else {
810 /* Have CPUID level 0 only - unheard of */
811 c->x86 = 4;
812 }
a158608b
AK		 813
814#ifdef CONFIG_SMP
f3fa8ebc 815 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
a158608b 816#endif
1da177e4
LT		 817}
818
819/*
820 * This does the hard work of actually picking apart the CPU stuff...
821 */
e6982c67 822void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1da177e4
LT		 823{
824 int i;
825 u32 xlvl;
826
827 early_identify_cpu(c);
828
829 /* AMD-defined flags: level 0x80000001 */
830 xlvl = cpuid_eax(0x80000000);
ebfcaa96 831 c->extended_cpuid_level = xlvl;
1da177e4
LT		 832 if ((xlvl & 0xffff0000) == 0x80000000) {
833 if (xlvl >= 0x80000001) {
834 c->x86_capability[1] = cpuid_edx(0x80000001);
5b7abc6f 835 c->x86_capability[6] = cpuid_ecx(0x80000001);
1da177e4
LT		 836 }
837 if (xlvl >= 0x80000004)
838 get_model_name(c); /* Default name */
839 }
840
841 /* Transmeta-defined flags: level 0x80860001 */
842 xlvl = cpuid_eax(0x80860000);
843 if ((xlvl & 0xffff0000) == 0x80860000) {
844 /* Don't set x86_cpuid_level here for now to not confuse. */
845 if (xlvl >= 0x80860001)
846 c->x86_capability[2] = cpuid_edx(0x80860001);
847 }
848
1e9f28fa
SS		 849 c->apicid = phys_pkg_id(0);
850
1da177e4
LT		 851 /*
852 * Vendor-specific initialization. In this section we
853 * canonicalize the feature flags, meaning if there are
854 * features a certain CPU supports which CPUID doesn't
855 * tell us, CPUID claiming incorrect flags, or other bugs,
856 * we handle them here.
857 *
858 * At the end of this section, c->x86_capability better
859 * indicate the features this CPU genuinely supports!
860 */
861 switch (c->x86_vendor) {
862 case X86_VENDOR_AMD:
863 init_amd(c);
864 break;
865
866 case X86_VENDOR_INTEL:
867 init_intel(c);
868 break;
869
870 case X86_VENDOR_UNKNOWN:
871 default:
872 display_cacheinfo(c);
873 break;
874 }
875
876 select_idle_routine(c);
877 detect_ht(c);
1da177e4
LT		 878
879 /*
880 * On SMP, boot_cpu_data holds the common feature set between
881 * all CPUs; so make sure that we indicate which features are
882 * common between the CPUs. The first time this routine gets
883 * executed, c == &boot_cpu_data.
884 */
885 if (c != &boot_cpu_data) {
886 /* AND the already accumulated flags with these */
887 for (i = 0 ; i < NCAPINTS ; i++)
888 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
889 }
890
891#ifdef CONFIG_X86_MCE
892 mcheck_init(c);
893#endif
8bd99481 894 if (c != &boot_cpu_data)
3b520b23 895 mtrr_ap_init();
1da177e4 896#ifdef CONFIG_NUMA
3019e8eb 897 numa_add_cpu(smp_processor_id());
1da177e4
LT		 898#endif
899}
900
901
e6982c67 902void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1da177e4
LT		 903{
904 if (c->x86_model_id[0])
905 printk("%s", c->x86_model_id);
906
907 if (c->x86_mask || c->cpuid_level >= 0)
908 printk(" stepping %02x\n", c->x86_mask);
909 else
910 printk("\n");
911}
912
913/*
914 * Get CPU information for use by the procfs.
915 */
916
917static int show_cpuinfo(struct seq_file *m, void *v)
918{
919 struct cpuinfo_x86 *c = v;
920
921 /*
922 * These flag bits must match the definitions in <asm/cpufeature.h>.
923 * NULL means this bit is undefined or reserved; either way it doesn't
924 * have meaning as far as Linux is concerned. Note that it's important
925 * to realize there is a difference between this table and CPUID -- if
926 * applications want to get the raw CPUID data, they should access
927 * /dev/cpu/<cpu_nr>/cpuid instead.
928 */
929 static char *x86_cap_flags[] = {
930 /* Intel-defined */
931 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
932 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
933 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
934 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", NULL,
935
936 /* AMD-defined */
3c3b73b6 937 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4
LT		 938 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
939 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
f790cd30
AK		 940 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
941 "3dnowext", "3dnow",
1da177e4
LT		 942
943 /* Transmeta-defined */
944 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
945 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
946 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
947 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
948
949 /* Other (Linux-defined) */
622dcaf9 950 "cxmmx", NULL, "cyrix_arr", "centaur_mcr", NULL,
c29601e9 951 "constant_tsc", NULL, NULL,
d167a518 952 "up", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4
LT		 953 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
954 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
955
956 /* Intel-defined (#2) */
9d95dd84 957 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
dcf10307 958 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
f790cd30 959 NULL, NULL, "dca", NULL, NULL, NULL, NULL, "popcnt",
1da177e4
LT		 960 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
961
5b7abc6f
PA		 962 /* VIA/Cyrix/Centaur-defined */
963 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
964 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
965 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
966 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
967
1da177e4 968 /* AMD-defined (#2) */
f790cd30
AK		 969 "lahf_lm", "cmp_legacy", "svm", "extapic", "cr8_legacy",
970 "altmovcr8", "abm", "sse4a",
971 "misalignsse", "3dnowprefetch",
972 "osvw", "ibs", NULL, NULL, NULL, NULL,
1da177e4 973 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
5b7abc6f 974 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4
LT		 975 };
976 static char *x86_power_flags[] = {
977 "ts", /* temperature sensor */
978 "fid", /* frequency id control */
979 "vid", /* voltage id control */
980 "ttp", /* thermal trip */
981 "tm",
3f98bc49 982 "stc",
f790cd30
AK		 983 "100mhzsteps",
984 "hwpstate",
d824395c
JR		 985 "", /* tsc invariant mapped to constant_tsc */
986 /* nothing */
1da177e4
LT		 987 };
988
989
990#ifdef CONFIG_SMP
991 if (!cpu_online(c-cpu_data))
992 return 0;
993#endif
994
995 seq_printf(m,"processor\t: %u\n"
996 "vendor_id\t: %s\n"
997 "cpu family\t: %d\n"
998 "model\t\t: %d\n"
999 "model name\t: %s\n",
1000 (unsigned)(c-cpu_data),
1001 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1002 c->x86,
1003 (int)c->x86_model,
1004 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1005
1006 if (c->x86_mask || c->cpuid_level >= 0)
1007 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1008 else
1009 seq_printf(m, "stepping\t: unknown\n");
1010
1011 if (cpu_has(c,X86_FEATURE_TSC)) {
95235ca2
VP		 1012 unsigned int freq = cpufreq_quick_get((unsigned)(c-cpu_data));
1013 if (!freq)
1014 freq = cpu_khz;
1da177e4 1015 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
95235ca2 1016 freq / 1000, (freq % 1000));
1da177e4
LT		 1017 }
1018
1019 /* Cache size */
1020 if (c->x86_cache_size >= 0)
1021 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1022
1023#ifdef CONFIG_SMP
94605eff 1024 if (smp_num_siblings * c->x86_max_cores > 1) {
db468681 1025 int cpu = c - cpu_data;
f3fa8ebc 1026 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
94605eff 1027 seq_printf(m, "siblings\t: %d\n", cpus_weight(cpu_core_map[cpu]));
f3fa8ebc 1028 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
94605eff 1029 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
db468681 1030 }
1da177e4
LT		 1031#endif
1032
1033 seq_printf(m,
1034 "fpu\t\t: yes\n"
1035 "fpu_exception\t: yes\n"
1036 "cpuid level\t: %d\n"
1037 "wp\t\t: yes\n"
1038 "flags\t\t:",
1039 c->cpuid_level);
1040
1041 {
1042 int i;
1043 for ( i = 0 ; i < 32*NCAPINTS ; i++ )
3d1712c9 1044 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1da177e4
LT		 1045 seq_printf(m, " %s", x86_cap_flags[i]);
1046 }
1047
1048 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1049 c->loops_per_jiffy/(500000/HZ),
1050 (c->loops_per_jiffy/(5000/HZ)) % 100);
1051
1052 if (c->x86_tlbsize > 0)
1053 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1054 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1055 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1056
1057 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1058 c->x86_phys_bits, c->x86_virt_bits);
1059
1060 seq_printf(m, "power management:");
1061 {
1062 unsigned i;
1063 for (i = 0; i < 32; i++)
1064 if (c->x86_power & (1 << i)) {
3f98bc49
AK		 1065 if (i < ARRAY_SIZE(x86_power_flags) &&
1066 x86_power_flags[i])
1067 seq_printf(m, "%s%s",
1068 x86_power_flags[i][0]?" ":"",
1069 x86_power_flags[i]);
1da177e4
LT		 1070 else
1071 seq_printf(m, " [%d]", i);
1072 }
1073 }
1da177e4 1074
d31ddaa1 1075 seq_printf(m, "\n\n");
1da177e4
LT		 1076
1077 return 0;
1078}
1079
1080static void *c_start(struct seq_file *m, loff_t *pos)
1081{
1082 return *pos < NR_CPUS ? cpu_data + *pos : NULL;
1083}
1084
1085static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1086{
1087 ++*pos;
1088 return c_start(m, pos);
1089}
1090
1091static void c_stop(struct seq_file *m, void *v)
1092{
1093}
1094
1095struct seq_operations cpuinfo_op = {
1096 .start =c_start,
1097 .next = c_next,
1098 .stop = c_stop,
1099 .show = show_cpuinfo,
1100};
Linux kernel - Deliverables
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