Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. | |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
a8ab26fe | 15 | * This code is released under the GNU General Public License version 2 |
1da177e4 LT |
16 | * |
17 | * Fixes | |
18 | * Felix Koop : NR_CPUS used properly | |
19 | * Jose Renau : Handle single CPU case. | |
20 | * Alan Cox : By repeated request 8) - Total BogoMIP report. | |
21 | * Greg Wright : Fix for kernel stacks panic. | |
22 | * Erich Boleyn : MP v1.4 and additional changes. | |
23 | * Matthias Sattler : Changes for 2.1 kernel map. | |
24 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
25 | * Michael Chastain : Change trampoline.S to gnu as. | |
26 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
27 | * Ingo Molnar : Added APIC timers, based on code | |
28 | * from Jose Renau | |
29 | * Ingo Molnar : various cleanups and rewrites | |
30 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
31 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
32 | * Andi Kleen : Changed for SMP boot into long mode. | |
a8ab26fe AK |
33 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. |
34 | * Andi Kleen : Converted to new state machine. | |
35 | * Various cleanups. | |
36 | * Probably mostly hotplug CPU ready now. | |
76e4f660 | 37 | * Ashok Raj : CPU hotplug support |
1da177e4 LT |
38 | */ |
39 | ||
a8ab26fe | 40 | |
1da177e4 LT |
41 | #include <linux/config.h> |
42 | #include <linux/init.h> | |
43 | ||
44 | #include <linux/mm.h> | |
45 | #include <linux/kernel_stat.h> | |
46 | #include <linux/smp_lock.h> | |
1da177e4 LT |
47 | #include <linux/bootmem.h> |
48 | #include <linux/thread_info.h> | |
49 | #include <linux/module.h> | |
50 | ||
51 | #include <linux/delay.h> | |
52 | #include <linux/mc146818rtc.h> | |
53 | #include <asm/mtrr.h> | |
54 | #include <asm/pgalloc.h> | |
55 | #include <asm/desc.h> | |
56 | #include <asm/kdebug.h> | |
57 | #include <asm/tlbflush.h> | |
58 | #include <asm/proto.h> | |
75152114 | 59 | #include <asm/nmi.h> |
9cdd304b AV |
60 | #include <asm/irq.h> |
61 | #include <asm/hw_irq.h> | |
488fc08d | 62 | #include <asm/numa.h> |
1da177e4 LT |
63 | |
64 | /* Number of siblings per CPU package */ | |
65 | int smp_num_siblings = 1; | |
1da177e4 | 66 | |
1e9f28fa SS |
67 | /* Last level cache ID of each logical CPU */ |
68 | u8 cpu_llc_id[NR_CPUS] __cpuinitdata = {[0 ... NR_CPUS-1] = BAD_APICID}; | |
69 | ||
1da177e4 | 70 | /* Bitmask of currently online CPUs */ |
6c231b7b | 71 | cpumask_t cpu_online_map __read_mostly; |
1da177e4 | 72 | |
a8ab26fe AK |
73 | EXPORT_SYMBOL(cpu_online_map); |
74 | ||
75 | /* | |
76 | * Private maps to synchronize booting between AP and BP. | |
77 | * Probably not needed anymore, but it makes for easier debugging. -AK | |
78 | */ | |
1da177e4 LT |
79 | cpumask_t cpu_callin_map; |
80 | cpumask_t cpu_callout_map; | |
a8ab26fe AK |
81 | |
82 | cpumask_t cpu_possible_map; | |
83 | EXPORT_SYMBOL(cpu_possible_map); | |
1da177e4 LT |
84 | |
85 | /* Per CPU bogomips and other parameters */ | |
86 | struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned; | |
87 | ||
a8ab26fe AK |
88 | /* Set when the idlers are all forked */ |
89 | int smp_threads_ready; | |
90 | ||
94605eff | 91 | /* representing HT siblings of each logical CPU */ |
6c231b7b | 92 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; |
94605eff SS |
93 | |
94 | /* representing HT and core siblings of each logical CPU */ | |
6c231b7b | 95 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly; |
2df9fa36 | 96 | EXPORT_SYMBOL(cpu_core_map); |
1da177e4 LT |
97 | |
98 | /* | |
99 | * Trampoline 80x86 program as an array. | |
100 | */ | |
101 | ||
a8ab26fe AK |
102 | extern unsigned char trampoline_data[]; |
103 | extern unsigned char trampoline_end[]; | |
1da177e4 | 104 | |
76e4f660 AR |
105 | /* State of each CPU */ |
106 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
107 | ||
108 | /* | |
109 | * Store all idle threads, this can be reused instead of creating | |
110 | * a new thread. Also avoids complicated thread destroy functionality | |
111 | * for idle threads. | |
112 | */ | |
113 | struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; | |
114 | ||
115 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) | |
116 | #define set_idle_for_cpu(x,p) (idle_thread_array[(x)] = (p)) | |
117 | ||
1da177e4 LT |
118 | /* |
119 | * Currently trivial. Write the real->protected mode | |
120 | * bootstrap into the page concerned. The caller | |
121 | * has made sure it's suitably aligned. | |
122 | */ | |
123 | ||
a8ab26fe | 124 | static unsigned long __cpuinit setup_trampoline(void) |
1da177e4 LT |
125 | { |
126 | void *tramp = __va(SMP_TRAMPOLINE_BASE); | |
127 | memcpy(tramp, trampoline_data, trampoline_end - trampoline_data); | |
128 | return virt_to_phys(tramp); | |
129 | } | |
130 | ||
131 | /* | |
132 | * The bootstrap kernel entry code has set these up. Save them for | |
133 | * a given CPU | |
134 | */ | |
135 | ||
a8ab26fe | 136 | static void __cpuinit smp_store_cpu_info(int id) |
1da177e4 LT |
137 | { |
138 | struct cpuinfo_x86 *c = cpu_data + id; | |
139 | ||
140 | *c = boot_cpu_data; | |
141 | identify_cpu(c); | |
dda50e71 | 142 | print_cpu_info(c); |
1da177e4 LT |
143 | } |
144 | ||
145 | /* | |
dda50e71 AK |
146 | * New Funky TSC sync algorithm borrowed from IA64. |
147 | * Main advantage is that it doesn't reset the TSCs fully and | |
148 | * in general looks more robust and it works better than my earlier | |
149 | * attempts. I believe it was written by David Mosberger. Some minor | |
150 | * adjustments for x86-64 by me -AK | |
1da177e4 | 151 | * |
dda50e71 AK |
152 | * Original comment reproduced below. |
153 | * | |
154 | * Synchronize TSC of the current (slave) CPU with the TSC of the | |
155 | * MASTER CPU (normally the time-keeper CPU). We use a closed loop to | |
156 | * eliminate the possibility of unaccounted-for errors (such as | |
157 | * getting a machine check in the middle of a calibration step). The | |
158 | * basic idea is for the slave to ask the master what itc value it has | |
159 | * and to read its own itc before and after the master responds. Each | |
160 | * iteration gives us three timestamps: | |
161 | * | |
162 | * slave master | |
163 | * | |
164 | * t0 ---\ | |
165 | * ---\ | |
166 | * ---> | |
167 | * tm | |
168 | * /--- | |
169 | * /--- | |
170 | * t1 <--- | |
171 | * | |
172 | * | |
173 | * The goal is to adjust the slave's TSC such that tm falls exactly | |
174 | * half-way between t0 and t1. If we achieve this, the clocks are | |
175 | * synchronized provided the interconnect between the slave and the | |
176 | * master is symmetric. Even if the interconnect were asymmetric, we | |
177 | * would still know that the synchronization error is smaller than the | |
178 | * roundtrip latency (t0 - t1). | |
179 | * | |
180 | * When the interconnect is quiet and symmetric, this lets us | |
181 | * synchronize the TSC to within one or two cycles. However, we can | |
182 | * only *guarantee* that the synchronization is accurate to within a | |
183 | * round-trip time, which is typically in the range of several hundred | |
184 | * cycles (e.g., ~500 cycles). In practice, this means that the TSCs | |
185 | * are usually almost perfectly synchronized, but we shouldn't assume | |
186 | * that the accuracy is much better than half a micro second or so. | |
187 | * | |
188 | * [there are other errors like the latency of RDTSC and of the | |
189 | * WRMSR. These can also account to hundreds of cycles. So it's | |
190 | * probably worse. It claims 153 cycles error on a dual Opteron, | |
191 | * but I suspect the numbers are actually somewhat worse -AK] | |
1da177e4 LT |
192 | */ |
193 | ||
dda50e71 AK |
194 | #define MASTER 0 |
195 | #define SLAVE (SMP_CACHE_BYTES/8) | |
196 | ||
197 | /* Intentionally don't use cpu_relax() while TSC synchronization | |
198 | because we don't want to go into funky power save modi or cause | |
199 | hypervisors to schedule us away. Going to sleep would likely affect | |
200 | latency and low latency is the primary objective here. -AK */ | |
201 | #define no_cpu_relax() barrier() | |
202 | ||
a8ab26fe | 203 | static __cpuinitdata DEFINE_SPINLOCK(tsc_sync_lock); |
dda50e71 AK |
204 | static volatile __cpuinitdata unsigned long go[SLAVE + 1]; |
205 | static int notscsync __cpuinitdata; | |
206 | ||
207 | #undef DEBUG_TSC_SYNC | |
1da177e4 | 208 | |
dda50e71 AK |
209 | #define NUM_ROUNDS 64 /* magic value */ |
210 | #define NUM_ITERS 5 /* likewise */ | |
1da177e4 | 211 | |
dda50e71 AK |
212 | /* Callback on boot CPU */ |
213 | static __cpuinit void sync_master(void *arg) | |
1da177e4 | 214 | { |
dda50e71 AK |
215 | unsigned long flags, i; |
216 | ||
dda50e71 AK |
217 | go[MASTER] = 0; |
218 | ||
219 | local_irq_save(flags); | |
220 | { | |
221 | for (i = 0; i < NUM_ROUNDS*NUM_ITERS; ++i) { | |
222 | while (!go[MASTER]) | |
223 | no_cpu_relax(); | |
224 | go[MASTER] = 0; | |
225 | rdtscll(go[SLAVE]); | |
226 | } | |
227 | } | |
228 | local_irq_restore(flags); | |
a8ab26fe | 229 | } |
1da177e4 | 230 | |
a8ab26fe | 231 | /* |
dda50e71 AK |
232 | * Return the number of cycles by which our tsc differs from the tsc |
233 | * on the master (time-keeper) CPU. A positive number indicates our | |
234 | * tsc is ahead of the master, negative that it is behind. | |
a8ab26fe | 235 | */ |
dda50e71 AK |
236 | static inline long |
237 | get_delta(long *rt, long *master) | |
a8ab26fe | 238 | { |
dda50e71 AK |
239 | unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0; |
240 | unsigned long tcenter, t0, t1, tm; | |
241 | int i; | |
a8ab26fe | 242 | |
dda50e71 AK |
243 | for (i = 0; i < NUM_ITERS; ++i) { |
244 | rdtscll(t0); | |
245 | go[MASTER] = 1; | |
246 | while (!(tm = go[SLAVE])) | |
247 | no_cpu_relax(); | |
248 | go[SLAVE] = 0; | |
249 | rdtscll(t1); | |
250 | ||
251 | if (t1 - t0 < best_t1 - best_t0) | |
252 | best_t0 = t0, best_t1 = t1, best_tm = tm; | |
253 | } | |
254 | ||
255 | *rt = best_t1 - best_t0; | |
256 | *master = best_tm - best_t0; | |
257 | ||
258 | /* average best_t0 and best_t1 without overflow: */ | |
259 | tcenter = (best_t0/2 + best_t1/2); | |
260 | if (best_t0 % 2 + best_t1 % 2 == 2) | |
261 | ++tcenter; | |
262 | return tcenter - best_tm; | |
1da177e4 LT |
263 | } |
264 | ||
3d483f47 | 265 | static __cpuinit void sync_tsc(unsigned int master) |
1da177e4 | 266 | { |
dda50e71 AK |
267 | int i, done = 0; |
268 | long delta, adj, adjust_latency = 0; | |
269 | unsigned long flags, rt, master_time_stamp, bound; | |
44456d37 | 270 | #ifdef DEBUG_TSC_SYNC |
dda50e71 AK |
271 | static struct syncdebug { |
272 | long rt; /* roundtrip time */ | |
273 | long master; /* master's timestamp */ | |
274 | long diff; /* difference between midpoint and master's timestamp */ | |
275 | long lat; /* estimate of tsc adjustment latency */ | |
276 | } t[NUM_ROUNDS] __cpuinitdata; | |
277 | #endif | |
278 | ||
3d483f47 EB |
279 | printk(KERN_INFO "CPU %d: Syncing TSC to CPU %u.\n", |
280 | smp_processor_id(), master); | |
281 | ||
dda50e71 AK |
282 | go[MASTER] = 1; |
283 | ||
3d483f47 EB |
284 | /* It is dangerous to broadcast IPI as cpus are coming up, |
285 | * as they may not be ready to accept them. So since | |
286 | * we only need to send the ipi to the boot cpu direct | |
287 | * the message, and avoid the race. | |
288 | */ | |
289 | smp_call_function_single(master, sync_master, NULL, 1, 0); | |
dda50e71 AK |
290 | |
291 | while (go[MASTER]) /* wait for master to be ready */ | |
292 | no_cpu_relax(); | |
293 | ||
294 | spin_lock_irqsave(&tsc_sync_lock, flags); | |
295 | { | |
296 | for (i = 0; i < NUM_ROUNDS; ++i) { | |
297 | delta = get_delta(&rt, &master_time_stamp); | |
298 | if (delta == 0) { | |
299 | done = 1; /* let's lock on to this... */ | |
300 | bound = rt; | |
301 | } | |
302 | ||
303 | if (!done) { | |
304 | unsigned long t; | |
305 | if (i > 0) { | |
306 | adjust_latency += -delta; | |
307 | adj = -delta + adjust_latency/4; | |
308 | } else | |
309 | adj = -delta; | |
310 | ||
311 | rdtscll(t); | |
312 | wrmsrl(MSR_IA32_TSC, t + adj); | |
313 | } | |
44456d37 | 314 | #ifdef DEBUG_TSC_SYNC |
dda50e71 AK |
315 | t[i].rt = rt; |
316 | t[i].master = master_time_stamp; | |
317 | t[i].diff = delta; | |
318 | t[i].lat = adjust_latency/4; | |
319 | #endif | |
320 | } | |
321 | } | |
322 | spin_unlock_irqrestore(&tsc_sync_lock, flags); | |
323 | ||
44456d37 | 324 | #ifdef DEBUG_TSC_SYNC |
dda50e71 AK |
325 | for (i = 0; i < NUM_ROUNDS; ++i) |
326 | printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n", | |
327 | t[i].rt, t[i].master, t[i].diff, t[i].lat); | |
328 | #endif | |
329 | ||
330 | printk(KERN_INFO | |
331 | "CPU %d: synchronized TSC with CPU %u (last diff %ld cycles, " | |
332 | "maxerr %lu cycles)\n", | |
3d483f47 | 333 | smp_processor_id(), master, delta, rt); |
a8ab26fe | 334 | } |
1da177e4 | 335 | |
dda50e71 | 336 | static void __cpuinit tsc_sync_wait(void) |
a8ab26fe | 337 | { |
737c5c3b AK |
338 | /* |
339 | * When the CPU has synchronized TSCs assume the BIOS | |
340 | * or the hardware already synced. Otherwise we could | |
341 | * mess up a possible perfect synchronization with a | |
342 | * not-quite-perfect algorithm. | |
343 | */ | |
344 | if (notscsync || !cpu_has_tsc || !unsynchronized_tsc()) | |
a8ab26fe | 345 | return; |
349188f6 | 346 | sync_tsc(0); |
a8ab26fe | 347 | } |
1da177e4 | 348 | |
dda50e71 | 349 | static __init int notscsync_setup(char *s) |
a8ab26fe | 350 | { |
dda50e71 | 351 | notscsync = 1; |
9b41046c | 352 | return 1; |
1da177e4 | 353 | } |
dda50e71 | 354 | __setup("notscsync", notscsync_setup); |
1da177e4 | 355 | |
a8ab26fe | 356 | static atomic_t init_deasserted __cpuinitdata; |
1da177e4 | 357 | |
a8ab26fe AK |
358 | /* |
359 | * Report back to the Boot Processor. | |
360 | * Running on AP. | |
361 | */ | |
362 | void __cpuinit smp_callin(void) | |
1da177e4 LT |
363 | { |
364 | int cpuid, phys_id; | |
365 | unsigned long timeout; | |
366 | ||
367 | /* | |
368 | * If waken up by an INIT in an 82489DX configuration | |
369 | * we may get here before an INIT-deassert IPI reaches | |
370 | * our local APIC. We have to wait for the IPI or we'll | |
371 | * lock up on an APIC access. | |
372 | */ | |
a8ab26fe AK |
373 | while (!atomic_read(&init_deasserted)) |
374 | cpu_relax(); | |
1da177e4 LT |
375 | |
376 | /* | |
377 | * (This works even if the APIC is not enabled.) | |
378 | */ | |
379 | phys_id = GET_APIC_ID(apic_read(APIC_ID)); | |
380 | cpuid = smp_processor_id(); | |
381 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
382 | panic("smp_callin: phys CPU#%d, CPU#%d already present??\n", | |
383 | phys_id, cpuid); | |
384 | } | |
385 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
386 | ||
387 | /* | |
388 | * STARTUP IPIs are fragile beasts as they might sometimes | |
389 | * trigger some glue motherboard logic. Complete APIC bus | |
390 | * silence for 1 second, this overestimates the time the | |
391 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
392 | * by a factor of two. This should be enough. | |
393 | */ | |
394 | ||
395 | /* | |
396 | * Waiting 2s total for startup (udelay is not yet working) | |
397 | */ | |
398 | timeout = jiffies + 2*HZ; | |
399 | while (time_before(jiffies, timeout)) { | |
400 | /* | |
401 | * Has the boot CPU finished it's STARTUP sequence? | |
402 | */ | |
403 | if (cpu_isset(cpuid, cpu_callout_map)) | |
404 | break; | |
a8ab26fe | 405 | cpu_relax(); |
1da177e4 LT |
406 | } |
407 | ||
408 | if (!time_before(jiffies, timeout)) { | |
409 | panic("smp_callin: CPU%d started up but did not get a callout!\n", | |
410 | cpuid); | |
411 | } | |
412 | ||
413 | /* | |
414 | * the boot CPU has finished the init stage and is spinning | |
415 | * on callin_map until we finish. We are free to set up this | |
416 | * CPU, first the APIC. (this is probably redundant on most | |
417 | * boards) | |
418 | */ | |
419 | ||
420 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
421 | setup_local_APIC(); | |
422 | ||
1da177e4 LT |
423 | /* |
424 | * Get our bogomips. | |
b4452218 AK |
425 | * |
426 | * Need to enable IRQs because it can take longer and then | |
427 | * the NMI watchdog might kill us. | |
1da177e4 | 428 | */ |
b4452218 | 429 | local_irq_enable(); |
1da177e4 | 430 | calibrate_delay(); |
b4452218 | 431 | local_irq_disable(); |
1da177e4 LT |
432 | Dprintk("Stack at about %p\n",&cpuid); |
433 | ||
434 | disable_APIC_timer(); | |
435 | ||
436 | /* | |
437 | * Save our processor parameters | |
438 | */ | |
439 | smp_store_cpu_info(cpuid); | |
440 | ||
1da177e4 LT |
441 | /* |
442 | * Allow the master to continue. | |
443 | */ | |
444 | cpu_set(cpuid, cpu_callin_map); | |
1da177e4 LT |
445 | } |
446 | ||
1e9f28fa SS |
447 | /* maps the cpu to the sched domain representing multi-core */ |
448 | cpumask_t cpu_coregroup_map(int cpu) | |
449 | { | |
450 | struct cpuinfo_x86 *c = cpu_data + cpu; | |
451 | /* | |
452 | * For perf, we return last level cache shared map. | |
453 | * TBD: when power saving sched policy is added, we will return | |
454 | * cpu_core_map when power saving policy is enabled | |
455 | */ | |
456 | return c->llc_shared_map; | |
457 | } | |
458 | ||
94605eff SS |
459 | /* representing cpus for which sibling maps can be computed */ |
460 | static cpumask_t cpu_sibling_setup_map; | |
461 | ||
cb0cd8d4 AR |
462 | static inline void set_cpu_sibling_map(int cpu) |
463 | { | |
464 | int i; | |
94605eff SS |
465 | struct cpuinfo_x86 *c = cpu_data; |
466 | ||
467 | cpu_set(cpu, cpu_sibling_setup_map); | |
cb0cd8d4 AR |
468 | |
469 | if (smp_num_siblings > 1) { | |
94605eff | 470 | for_each_cpu_mask(i, cpu_sibling_setup_map) { |
f3fa8ebc RS |
471 | if (c[cpu].phys_proc_id == c[i].phys_proc_id && |
472 | c[cpu].cpu_core_id == c[i].cpu_core_id) { | |
cb0cd8d4 AR |
473 | cpu_set(i, cpu_sibling_map[cpu]); |
474 | cpu_set(cpu, cpu_sibling_map[i]); | |
94605eff SS |
475 | cpu_set(i, cpu_core_map[cpu]); |
476 | cpu_set(cpu, cpu_core_map[i]); | |
1e9f28fa SS |
477 | cpu_set(i, c[cpu].llc_shared_map); |
478 | cpu_set(cpu, c[i].llc_shared_map); | |
cb0cd8d4 AR |
479 | } |
480 | } | |
481 | } else { | |
482 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
483 | } | |
484 | ||
1e9f28fa SS |
485 | cpu_set(cpu, c[cpu].llc_shared_map); |
486 | ||
94605eff | 487 | if (current_cpu_data.x86_max_cores == 1) { |
cb0cd8d4 | 488 | cpu_core_map[cpu] = cpu_sibling_map[cpu]; |
94605eff SS |
489 | c[cpu].booted_cores = 1; |
490 | return; | |
491 | } | |
492 | ||
493 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
1e9f28fa SS |
494 | if (cpu_llc_id[cpu] != BAD_APICID && |
495 | cpu_llc_id[cpu] == cpu_llc_id[i]) { | |
496 | cpu_set(i, c[cpu].llc_shared_map); | |
497 | cpu_set(cpu, c[i].llc_shared_map); | |
498 | } | |
f3fa8ebc | 499 | if (c[cpu].phys_proc_id == c[i].phys_proc_id) { |
94605eff SS |
500 | cpu_set(i, cpu_core_map[cpu]); |
501 | cpu_set(cpu, cpu_core_map[i]); | |
502 | /* | |
503 | * Does this new cpu bringup a new core? | |
504 | */ | |
505 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) { | |
506 | /* | |
507 | * for each core in package, increment | |
508 | * the booted_cores for this new cpu | |
509 | */ | |
510 | if (first_cpu(cpu_sibling_map[i]) == i) | |
511 | c[cpu].booted_cores++; | |
512 | /* | |
513 | * increment the core count for all | |
514 | * the other cpus in this package | |
515 | */ | |
516 | if (i != cpu) | |
517 | c[i].booted_cores++; | |
518 | } else if (i != cpu && !c[cpu].booted_cores) | |
519 | c[cpu].booted_cores = c[i].booted_cores; | |
520 | } | |
cb0cd8d4 AR |
521 | } |
522 | } | |
523 | ||
1da177e4 | 524 | /* |
a8ab26fe | 525 | * Setup code on secondary processor (after comming out of the trampoline) |
1da177e4 | 526 | */ |
a8ab26fe | 527 | void __cpuinit start_secondary(void) |
1da177e4 LT |
528 | { |
529 | /* | |
530 | * Dont put anything before smp_callin(), SMP | |
531 | * booting is too fragile that we want to limit the | |
532 | * things done here to the most necessary things. | |
533 | */ | |
534 | cpu_init(); | |
5bfb5d69 | 535 | preempt_disable(); |
1da177e4 LT |
536 | smp_callin(); |
537 | ||
538 | /* otherwise gcc will move up the smp_processor_id before the cpu_init */ | |
539 | barrier(); | |
540 | ||
1da177e4 LT |
541 | Dprintk("cpu %d: setting up apic clock\n", smp_processor_id()); |
542 | setup_secondary_APIC_clock(); | |
543 | ||
a8ab26fe | 544 | Dprintk("cpu %d: enabling apic timer\n", smp_processor_id()); |
1da177e4 LT |
545 | |
546 | if (nmi_watchdog == NMI_IO_APIC) { | |
547 | disable_8259A_irq(0); | |
548 | enable_NMI_through_LVT0(NULL); | |
549 | enable_8259A_irq(0); | |
550 | } | |
551 | ||
a8ab26fe | 552 | enable_APIC_timer(); |
1da177e4 | 553 | |
cb0cd8d4 AR |
554 | /* |
555 | * The sibling maps must be set before turing the online map on for | |
556 | * this cpu | |
557 | */ | |
558 | set_cpu_sibling_map(smp_processor_id()); | |
559 | ||
1eecd73c AK |
560 | /* |
561 | * Wait for TSC sync to not schedule things before. | |
562 | * We still process interrupts, which could see an inconsistent | |
563 | * time in that window unfortunately. | |
564 | * Do this here because TSC sync has global unprotected state. | |
565 | */ | |
566 | tsc_sync_wait(); | |
567 | ||
884d9e40 AR |
568 | /* |
569 | * We need to hold call_lock, so there is no inconsistency | |
570 | * between the time smp_call_function() determines number of | |
571 | * IPI receipients, and the time when the determination is made | |
572 | * for which cpus receive the IPI in genapic_flat.c. Holding this | |
573 | * lock helps us to not include this cpu in a currently in progress | |
574 | * smp_call_function(). | |
575 | */ | |
576 | lock_ipi_call_lock(); | |
577 | ||
1da177e4 | 578 | /* |
a8ab26fe | 579 | * Allow the master to continue. |
1da177e4 | 580 | */ |
1da177e4 | 581 | cpu_set(smp_processor_id(), cpu_online_map); |
884d9e40 AR |
582 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
583 | unlock_ipi_call_lock(); | |
584 | ||
1da177e4 LT |
585 | cpu_idle(); |
586 | } | |
587 | ||
a8ab26fe | 588 | extern volatile unsigned long init_rsp; |
1da177e4 LT |
589 | extern void (*initial_code)(void); |
590 | ||
44456d37 | 591 | #ifdef APIC_DEBUG |
a8ab26fe | 592 | static void inquire_remote_apic(int apicid) |
1da177e4 LT |
593 | { |
594 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
595 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
596 | int timeout, status; | |
597 | ||
598 | printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid); | |
599 | ||
600 | for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) { | |
601 | printk("... APIC #%d %s: ", apicid, names[i]); | |
602 | ||
603 | /* | |
604 | * Wait for idle. | |
605 | */ | |
606 | apic_wait_icr_idle(); | |
607 | ||
c1507eb2 AK |
608 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); |
609 | apic_write(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
1da177e4 LT |
610 | |
611 | timeout = 0; | |
612 | do { | |
613 | udelay(100); | |
614 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
615 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
616 | ||
617 | switch (status) { | |
618 | case APIC_ICR_RR_VALID: | |
619 | status = apic_read(APIC_RRR); | |
620 | printk("%08x\n", status); | |
621 | break; | |
622 | default: | |
623 | printk("failed\n"); | |
624 | } | |
625 | } | |
626 | } | |
627 | #endif | |
628 | ||
a8ab26fe AK |
629 | /* |
630 | * Kick the secondary to wake up. | |
631 | */ | |
632 | static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int start_rip) | |
1da177e4 LT |
633 | { |
634 | unsigned long send_status = 0, accept_status = 0; | |
635 | int maxlvt, timeout, num_starts, j; | |
636 | ||
637 | Dprintk("Asserting INIT.\n"); | |
638 | ||
639 | /* | |
640 | * Turn INIT on target chip | |
641 | */ | |
c1507eb2 | 642 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
643 | |
644 | /* | |
645 | * Send IPI | |
646 | */ | |
c1507eb2 | 647 | apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT |
1da177e4 LT |
648 | | APIC_DM_INIT); |
649 | ||
650 | Dprintk("Waiting for send to finish...\n"); | |
651 | timeout = 0; | |
652 | do { | |
653 | Dprintk("+"); | |
654 | udelay(100); | |
655 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
656 | } while (send_status && (timeout++ < 1000)); | |
657 | ||
658 | mdelay(10); | |
659 | ||
660 | Dprintk("Deasserting INIT.\n"); | |
661 | ||
662 | /* Target chip */ | |
c1507eb2 | 663 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
664 | |
665 | /* Send IPI */ | |
c1507eb2 | 666 | apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); |
1da177e4 LT |
667 | |
668 | Dprintk("Waiting for send to finish...\n"); | |
669 | timeout = 0; | |
670 | do { | |
671 | Dprintk("+"); | |
672 | udelay(100); | |
673 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
674 | } while (send_status && (timeout++ < 1000)); | |
675 | ||
f2ecfab9 | 676 | mb(); |
1da177e4 LT |
677 | atomic_set(&init_deasserted, 1); |
678 | ||
5a40b7c2 | 679 | num_starts = 2; |
1da177e4 LT |
680 | |
681 | /* | |
682 | * Run STARTUP IPI loop. | |
683 | */ | |
684 | Dprintk("#startup loops: %d.\n", num_starts); | |
685 | ||
686 | maxlvt = get_maxlvt(); | |
687 | ||
688 | for (j = 1; j <= num_starts; j++) { | |
689 | Dprintk("Sending STARTUP #%d.\n",j); | |
1da177e4 LT |
690 | apic_write(APIC_ESR, 0); |
691 | apic_read(APIC_ESR); | |
692 | Dprintk("After apic_write.\n"); | |
693 | ||
694 | /* | |
695 | * STARTUP IPI | |
696 | */ | |
697 | ||
698 | /* Target chip */ | |
c1507eb2 | 699 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
700 | |
701 | /* Boot on the stack */ | |
702 | /* Kick the second */ | |
c1507eb2 | 703 | apic_write(APIC_ICR, APIC_DM_STARTUP | (start_rip >> 12)); |
1da177e4 LT |
704 | |
705 | /* | |
706 | * Give the other CPU some time to accept the IPI. | |
707 | */ | |
708 | udelay(300); | |
709 | ||
710 | Dprintk("Startup point 1.\n"); | |
711 | ||
712 | Dprintk("Waiting for send to finish...\n"); | |
713 | timeout = 0; | |
714 | do { | |
715 | Dprintk("+"); | |
716 | udelay(100); | |
717 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
718 | } while (send_status && (timeout++ < 1000)); | |
719 | ||
720 | /* | |
721 | * Give the other CPU some time to accept the IPI. | |
722 | */ | |
723 | udelay(200); | |
724 | /* | |
725 | * Due to the Pentium erratum 3AP. | |
726 | */ | |
727 | if (maxlvt > 3) { | |
1da177e4 LT |
728 | apic_write(APIC_ESR, 0); |
729 | } | |
730 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
731 | if (send_status || accept_status) | |
732 | break; | |
733 | } | |
734 | Dprintk("After Startup.\n"); | |
735 | ||
736 | if (send_status) | |
737 | printk(KERN_ERR "APIC never delivered???\n"); | |
738 | if (accept_status) | |
739 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
740 | ||
741 | return (send_status | accept_status); | |
742 | } | |
743 | ||
76e4f660 AR |
744 | struct create_idle { |
745 | struct task_struct *idle; | |
746 | struct completion done; | |
747 | int cpu; | |
748 | }; | |
749 | ||
750 | void do_fork_idle(void *_c_idle) | |
751 | { | |
752 | struct create_idle *c_idle = _c_idle; | |
753 | ||
754 | c_idle->idle = fork_idle(c_idle->cpu); | |
755 | complete(&c_idle->done); | |
756 | } | |
757 | ||
a8ab26fe AK |
758 | /* |
759 | * Boot one CPU. | |
760 | */ | |
761 | static int __cpuinit do_boot_cpu(int cpu, int apicid) | |
1da177e4 | 762 | { |
1da177e4 | 763 | unsigned long boot_error; |
a8ab26fe | 764 | int timeout; |
1da177e4 | 765 | unsigned long start_rip; |
76e4f660 AR |
766 | struct create_idle c_idle = { |
767 | .cpu = cpu, | |
768 | .done = COMPLETION_INITIALIZER(c_idle.done), | |
769 | }; | |
770 | DECLARE_WORK(work, do_fork_idle, &c_idle); | |
771 | ||
c11efdf9 RT |
772 | /* allocate memory for gdts of secondary cpus. Hotplug is considered */ |
773 | if (!cpu_gdt_descr[cpu].address && | |
774 | !(cpu_gdt_descr[cpu].address = get_zeroed_page(GFP_KERNEL))) { | |
775 | printk(KERN_ERR "Failed to allocate GDT for CPU %d\n", cpu); | |
776 | return -1; | |
777 | } | |
778 | ||
365ba917 RT |
779 | /* Allocate node local memory for AP pdas */ |
780 | if (cpu_pda(cpu) == &boot_cpu_pda[cpu]) { | |
781 | struct x8664_pda *newpda, *pda; | |
782 | int node = cpu_to_node(cpu); | |
783 | pda = cpu_pda(cpu); | |
784 | newpda = kmalloc_node(sizeof (struct x8664_pda), GFP_ATOMIC, | |
785 | node); | |
786 | if (newpda) { | |
787 | memcpy(newpda, pda, sizeof (struct x8664_pda)); | |
788 | cpu_pda(cpu) = newpda; | |
789 | } else | |
790 | printk(KERN_ERR | |
791 | "Could not allocate node local PDA for CPU %d on node %d\n", | |
792 | cpu, node); | |
793 | } | |
794 | ||
795 | ||
d167a518 GH |
796 | alternatives_smp_switch(1); |
797 | ||
76e4f660 AR |
798 | c_idle.idle = get_idle_for_cpu(cpu); |
799 | ||
800 | if (c_idle.idle) { | |
801 | c_idle.idle->thread.rsp = (unsigned long) (((struct pt_regs *) | |
57eafdc2 | 802 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); |
76e4f660 AR |
803 | init_idle(c_idle.idle, cpu); |
804 | goto do_rest; | |
805 | } | |
806 | ||
1da177e4 | 807 | /* |
76e4f660 AR |
808 | * During cold boot process, keventd thread is not spun up yet. |
809 | * When we do cpu hot-add, we create idle threads on the fly, we should | |
810 | * not acquire any attributes from the calling context. Hence the clean | |
811 | * way to create kernel_threads() is to do that from keventd(). | |
812 | * We do the current_is_keventd() due to the fact that ACPI notifier | |
813 | * was also queuing to keventd() and when the caller is already running | |
814 | * in context of keventd(), we would end up with locking up the keventd | |
815 | * thread. | |
1da177e4 | 816 | */ |
76e4f660 AR |
817 | if (!keventd_up() || current_is_keventd()) |
818 | work.func(work.data); | |
819 | else { | |
820 | schedule_work(&work); | |
821 | wait_for_completion(&c_idle.done); | |
822 | } | |
823 | ||
824 | if (IS_ERR(c_idle.idle)) { | |
a8ab26fe | 825 | printk("failed fork for CPU %d\n", cpu); |
76e4f660 | 826 | return PTR_ERR(c_idle.idle); |
a8ab26fe | 827 | } |
1da177e4 | 828 | |
76e4f660 AR |
829 | set_idle_for_cpu(cpu, c_idle.idle); |
830 | ||
831 | do_rest: | |
832 | ||
df79efde | 833 | cpu_pda(cpu)->pcurrent = c_idle.idle; |
1da177e4 LT |
834 | |
835 | start_rip = setup_trampoline(); | |
836 | ||
76e4f660 | 837 | init_rsp = c_idle.idle->thread.rsp; |
1da177e4 LT |
838 | per_cpu(init_tss,cpu).rsp0 = init_rsp; |
839 | initial_code = start_secondary; | |
e4f17c43 | 840 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
1da177e4 | 841 | |
de04f322 AK |
842 | printk(KERN_INFO "Booting processor %d/%d APIC 0x%x\n", cpu, |
843 | cpus_weight(cpu_present_map), | |
844 | apicid); | |
1da177e4 LT |
845 | |
846 | /* | |
847 | * This grunge runs the startup process for | |
848 | * the targeted processor. | |
849 | */ | |
850 | ||
851 | atomic_set(&init_deasserted, 0); | |
852 | ||
853 | Dprintk("Setting warm reset code and vector.\n"); | |
854 | ||
855 | CMOS_WRITE(0xa, 0xf); | |
856 | local_flush_tlb(); | |
857 | Dprintk("1.\n"); | |
858 | *((volatile unsigned short *) phys_to_virt(0x469)) = start_rip >> 4; | |
859 | Dprintk("2.\n"); | |
860 | *((volatile unsigned short *) phys_to_virt(0x467)) = start_rip & 0xf; | |
861 | Dprintk("3.\n"); | |
862 | ||
863 | /* | |
864 | * Be paranoid about clearing APIC errors. | |
865 | */ | |
11a8e778 AK |
866 | apic_write(APIC_ESR, 0); |
867 | apic_read(APIC_ESR); | |
1da177e4 LT |
868 | |
869 | /* | |
870 | * Status is now clean | |
871 | */ | |
872 | boot_error = 0; | |
873 | ||
874 | /* | |
875 | * Starting actual IPI sequence... | |
876 | */ | |
a8ab26fe | 877 | boot_error = wakeup_secondary_via_INIT(apicid, start_rip); |
1da177e4 LT |
878 | |
879 | if (!boot_error) { | |
880 | /* | |
881 | * allow APs to start initializing. | |
882 | */ | |
883 | Dprintk("Before Callout %d.\n", cpu); | |
884 | cpu_set(cpu, cpu_callout_map); | |
885 | Dprintk("After Callout %d.\n", cpu); | |
886 | ||
887 | /* | |
888 | * Wait 5s total for a response | |
889 | */ | |
890 | for (timeout = 0; timeout < 50000; timeout++) { | |
891 | if (cpu_isset(cpu, cpu_callin_map)) | |
892 | break; /* It has booted */ | |
893 | udelay(100); | |
894 | } | |
895 | ||
896 | if (cpu_isset(cpu, cpu_callin_map)) { | |
897 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
1da177e4 LT |
898 | Dprintk("CPU has booted.\n"); |
899 | } else { | |
900 | boot_error = 1; | |
901 | if (*((volatile unsigned char *)phys_to_virt(SMP_TRAMPOLINE_BASE)) | |
902 | == 0xA5) | |
903 | /* trampoline started but...? */ | |
904 | printk("Stuck ??\n"); | |
905 | else | |
906 | /* trampoline code not run */ | |
907 | printk("Not responding.\n"); | |
44456d37 | 908 | #ifdef APIC_DEBUG |
1da177e4 LT |
909 | inquire_remote_apic(apicid); |
910 | #endif | |
911 | } | |
912 | } | |
913 | if (boot_error) { | |
914 | cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */ | |
915 | clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */ | |
488fc08d | 916 | clear_node_cpumask(cpu); /* was set by numa_add_cpu */ |
a8ab26fe AK |
917 | cpu_clear(cpu, cpu_present_map); |
918 | cpu_clear(cpu, cpu_possible_map); | |
1da177e4 LT |
919 | x86_cpu_to_apicid[cpu] = BAD_APICID; |
920 | x86_cpu_to_log_apicid[cpu] = BAD_APICID; | |
a8ab26fe | 921 | return -EIO; |
1da177e4 | 922 | } |
a8ab26fe AK |
923 | |
924 | return 0; | |
1da177e4 LT |
925 | } |
926 | ||
a8ab26fe AK |
927 | cycles_t cacheflush_time; |
928 | unsigned long cache_decay_ticks; | |
929 | ||
1da177e4 | 930 | /* |
a8ab26fe | 931 | * Cleanup possible dangling ends... |
1da177e4 | 932 | */ |
a8ab26fe | 933 | static __cpuinit void smp_cleanup_boot(void) |
1da177e4 | 934 | { |
a8ab26fe AK |
935 | /* |
936 | * Paranoid: Set warm reset code and vector here back | |
937 | * to default values. | |
938 | */ | |
939 | CMOS_WRITE(0, 0xf); | |
1da177e4 | 940 | |
a8ab26fe AK |
941 | /* |
942 | * Reset trampoline flag | |
943 | */ | |
944 | *((volatile int *) phys_to_virt(0x467)) = 0; | |
a8ab26fe AK |
945 | } |
946 | ||
947 | /* | |
948 | * Fall back to non SMP mode after errors. | |
949 | * | |
950 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
951 | */ | |
e6982c67 | 952 | static __init void disable_smp(void) |
a8ab26fe AK |
953 | { |
954 | cpu_present_map = cpumask_of_cpu(0); | |
955 | cpu_possible_map = cpumask_of_cpu(0); | |
956 | if (smp_found_config) | |
957 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id); | |
958 | else | |
959 | phys_cpu_present_map = physid_mask_of_physid(0); | |
960 | cpu_set(0, cpu_sibling_map[0]); | |
961 | cpu_set(0, cpu_core_map[0]); | |
962 | } | |
963 | ||
61b1b2d0 | 964 | #ifdef CONFIG_HOTPLUG_CPU |
420f8f68 AK |
965 | |
966 | int additional_cpus __initdata = -1; | |
967 | ||
61b1b2d0 AK |
968 | /* |
969 | * cpu_possible_map should be static, it cannot change as cpu's | |
970 | * are onlined, or offlined. The reason is per-cpu data-structures | |
971 | * are allocated by some modules at init time, and dont expect to | |
972 | * do this dynamically on cpu arrival/departure. | |
973 | * cpu_present_map on the other hand can change dynamically. | |
974 | * In case when cpu_hotplug is not compiled, then we resort to current | |
975 | * behaviour, which is cpu_possible == cpu_present. | |
61b1b2d0 | 976 | * - Ashok Raj |
420f8f68 AK |
977 | * |
978 | * Three ways to find out the number of additional hotplug CPUs: | |
979 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
420f8f68 | 980 | * - The user can overwrite it with additional_cpus=NUM |
f62a91f6 | 981 | * - Otherwise don't reserve additional CPUs. |
420f8f68 AK |
982 | * We do this because additional CPUs waste a lot of memory. |
983 | * -AK | |
61b1b2d0 | 984 | */ |
421c7ce6 | 985 | __init void prefill_possible_map(void) |
61b1b2d0 AK |
986 | { |
987 | int i; | |
420f8f68 AK |
988 | int possible; |
989 | ||
990 | if (additional_cpus == -1) { | |
f62a91f6 | 991 | if (disabled_cpus > 0) |
420f8f68 | 992 | additional_cpus = disabled_cpus; |
f62a91f6 AK |
993 | else |
994 | additional_cpus = 0; | |
420f8f68 AK |
995 | } |
996 | possible = num_processors + additional_cpus; | |
997 | if (possible > NR_CPUS) | |
998 | possible = NR_CPUS; | |
999 | ||
1000 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", | |
1001 | possible, | |
1002 | max_t(int, possible - num_processors, 0)); | |
1003 | ||
1004 | for (i = 0; i < possible; i++) | |
61b1b2d0 AK |
1005 | cpu_set(i, cpu_possible_map); |
1006 | } | |
1007 | #endif | |
1008 | ||
a8ab26fe AK |
1009 | /* |
1010 | * Various sanity checks. | |
1011 | */ | |
e6982c67 | 1012 | static int __init smp_sanity_check(unsigned max_cpus) |
a8ab26fe | 1013 | { |
1da177e4 LT |
1014 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
1015 | printk("weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1016 | hard_smp_processor_id()); | |
1017 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1018 | } | |
1019 | ||
1020 | /* | |
1021 | * If we couldn't find an SMP configuration at boot time, | |
1022 | * get out of here now! | |
1023 | */ | |
1024 | if (!smp_found_config) { | |
1025 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | |
a8ab26fe | 1026 | disable_smp(); |
1da177e4 LT |
1027 | if (APIC_init_uniprocessor()) |
1028 | printk(KERN_NOTICE "Local APIC not detected." | |
1029 | " Using dummy APIC emulation.\n"); | |
a8ab26fe | 1030 | return -1; |
1da177e4 LT |
1031 | } |
1032 | ||
1033 | /* | |
1034 | * Should not be necessary because the MP table should list the boot | |
1035 | * CPU too, but we do it for the sake of robustness anyway. | |
1036 | */ | |
1037 | if (!physid_isset(boot_cpu_id, phys_cpu_present_map)) { | |
1038 | printk(KERN_NOTICE "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1039 | boot_cpu_id); | |
1040 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1041 | } | |
1042 | ||
1043 | /* | |
1044 | * If we couldn't find a local APIC, then get out of here now! | |
1045 | */ | |
11a8e778 | 1046 | if (!cpu_has_apic) { |
1da177e4 LT |
1047 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", |
1048 | boot_cpu_id); | |
1049 | printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n"); | |
a8ab26fe AK |
1050 | nr_ioapics = 0; |
1051 | return -1; | |
1da177e4 LT |
1052 | } |
1053 | ||
1da177e4 LT |
1054 | /* |
1055 | * If SMP should be disabled, then really disable it! | |
1056 | */ | |
1057 | if (!max_cpus) { | |
1da177e4 | 1058 | printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n"); |
a8ab26fe AK |
1059 | nr_ioapics = 0; |
1060 | return -1; | |
1da177e4 LT |
1061 | } |
1062 | ||
a8ab26fe AK |
1063 | return 0; |
1064 | } | |
1da177e4 | 1065 | |
a8ab26fe AK |
1066 | /* |
1067 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1068 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1069 | */ | |
e6982c67 | 1070 | void __init smp_prepare_cpus(unsigned int max_cpus) |
a8ab26fe | 1071 | { |
a8ab26fe AK |
1072 | nmi_watchdog_default(); |
1073 | current_cpu_data = boot_cpu_data; | |
1074 | current_thread_info()->cpu = 0; /* needed? */ | |
94605eff | 1075 | set_cpu_sibling_map(0); |
1da177e4 | 1076 | |
a8ab26fe AK |
1077 | if (smp_sanity_check(max_cpus) < 0) { |
1078 | printk(KERN_INFO "SMP disabled\n"); | |
1079 | disable_smp(); | |
1080 | return; | |
1da177e4 LT |
1081 | } |
1082 | ||
a8ab26fe | 1083 | |
1da177e4 | 1084 | /* |
a8ab26fe | 1085 | * Switch from PIC to APIC mode. |
1da177e4 | 1086 | */ |
a8ab26fe AK |
1087 | connect_bsp_APIC(); |
1088 | setup_local_APIC(); | |
1da177e4 | 1089 | |
a8ab26fe AK |
1090 | if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_id) { |
1091 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", | |
1092 | GET_APIC_ID(apic_read(APIC_ID)), boot_cpu_id); | |
1093 | /* Or can we switch back to PIC here? */ | |
1da177e4 | 1094 | } |
1da177e4 LT |
1095 | |
1096 | /* | |
a8ab26fe | 1097 | * Now start the IO-APICs |
1da177e4 LT |
1098 | */ |
1099 | if (!skip_ioapic_setup && nr_ioapics) | |
1100 | setup_IO_APIC(); | |
1101 | else | |
1102 | nr_ioapics = 0; | |
1103 | ||
1da177e4 | 1104 | /* |
a8ab26fe | 1105 | * Set up local APIC timer on boot CPU. |
1da177e4 | 1106 | */ |
1da177e4 | 1107 | |
a8ab26fe | 1108 | setup_boot_APIC_clock(); |
1da177e4 LT |
1109 | } |
1110 | ||
a8ab26fe AK |
1111 | /* |
1112 | * Early setup to make printk work. | |
1113 | */ | |
1114 | void __init smp_prepare_boot_cpu(void) | |
1da177e4 | 1115 | { |
a8ab26fe AK |
1116 | int me = smp_processor_id(); |
1117 | cpu_set(me, cpu_online_map); | |
1118 | cpu_set(me, cpu_callout_map); | |
884d9e40 | 1119 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1da177e4 LT |
1120 | } |
1121 | ||
a8ab26fe AK |
1122 | /* |
1123 | * Entry point to boot a CPU. | |
a8ab26fe AK |
1124 | */ |
1125 | int __cpuinit __cpu_up(unsigned int cpu) | |
1da177e4 | 1126 | { |
a8ab26fe AK |
1127 | int err; |
1128 | int apicid = cpu_present_to_apicid(cpu); | |
1da177e4 | 1129 | |
a8ab26fe | 1130 | WARN_ON(irqs_disabled()); |
1da177e4 | 1131 | |
a8ab26fe AK |
1132 | Dprintk("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
1133 | ||
1134 | if (apicid == BAD_APICID || apicid == boot_cpu_id || | |
1135 | !physid_isset(apicid, phys_cpu_present_map)) { | |
1136 | printk("__cpu_up: bad cpu %d\n", cpu); | |
1137 | return -EINVAL; | |
1138 | } | |
a8ab26fe | 1139 | |
76e4f660 AR |
1140 | /* |
1141 | * Already booted CPU? | |
1142 | */ | |
1143 | if (cpu_isset(cpu, cpu_callin_map)) { | |
1144 | Dprintk("do_boot_cpu %d Already started\n", cpu); | |
1145 | return -ENOSYS; | |
1146 | } | |
1147 | ||
884d9e40 | 1148 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; |
a8ab26fe AK |
1149 | /* Boot it! */ |
1150 | err = do_boot_cpu(cpu, apicid); | |
1151 | if (err < 0) { | |
a8ab26fe AK |
1152 | Dprintk("do_boot_cpu failed %d\n", err); |
1153 | return err; | |
1da177e4 | 1154 | } |
a8ab26fe | 1155 | |
1da177e4 LT |
1156 | /* Unleash the CPU! */ |
1157 | Dprintk("waiting for cpu %d\n", cpu); | |
1158 | ||
1da177e4 | 1159 | while (!cpu_isset(cpu, cpu_online_map)) |
a8ab26fe | 1160 | cpu_relax(); |
76e4f660 AR |
1161 | err = 0; |
1162 | ||
1163 | return err; | |
1da177e4 LT |
1164 | } |
1165 | ||
a8ab26fe AK |
1166 | /* |
1167 | * Finish the SMP boot. | |
1168 | */ | |
e6982c67 | 1169 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 1170 | { |
a8ab26fe AK |
1171 | smp_cleanup_boot(); |
1172 | ||
1da177e4 LT |
1173 | #ifdef CONFIG_X86_IO_APIC |
1174 | setup_ioapic_dest(); | |
1175 | #endif | |
1da177e4 | 1176 | |
75152114 | 1177 | check_nmi_watchdog(); |
a8ab26fe | 1178 | } |
76e4f660 AR |
1179 | |
1180 | #ifdef CONFIG_HOTPLUG_CPU | |
1181 | ||
cb0cd8d4 | 1182 | static void remove_siblinginfo(int cpu) |
76e4f660 AR |
1183 | { |
1184 | int sibling; | |
94605eff | 1185 | struct cpuinfo_x86 *c = cpu_data; |
76e4f660 | 1186 | |
94605eff SS |
1187 | for_each_cpu_mask(sibling, cpu_core_map[cpu]) { |
1188 | cpu_clear(cpu, cpu_core_map[sibling]); | |
1189 | /* | |
1190 | * last thread sibling in this cpu core going down | |
1191 | */ | |
1192 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) | |
1193 | c[sibling].booted_cores--; | |
1194 | } | |
1195 | ||
76e4f660 AR |
1196 | for_each_cpu_mask(sibling, cpu_sibling_map[cpu]) |
1197 | cpu_clear(cpu, cpu_sibling_map[sibling]); | |
76e4f660 AR |
1198 | cpus_clear(cpu_sibling_map[cpu]); |
1199 | cpus_clear(cpu_core_map[cpu]); | |
f3fa8ebc RS |
1200 | c[cpu].phys_proc_id = 0; |
1201 | c[cpu].cpu_core_id = 0; | |
94605eff | 1202 | cpu_clear(cpu, cpu_sibling_setup_map); |
76e4f660 AR |
1203 | } |
1204 | ||
1205 | void remove_cpu_from_maps(void) | |
1206 | { | |
1207 | int cpu = smp_processor_id(); | |
1208 | ||
1209 | cpu_clear(cpu, cpu_callout_map); | |
1210 | cpu_clear(cpu, cpu_callin_map); | |
1211 | clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */ | |
488fc08d | 1212 | clear_node_cpumask(cpu); |
76e4f660 AR |
1213 | } |
1214 | ||
1215 | int __cpu_disable(void) | |
1216 | { | |
1217 | int cpu = smp_processor_id(); | |
1218 | ||
1219 | /* | |
1220 | * Perhaps use cpufreq to drop frequency, but that could go | |
1221 | * into generic code. | |
1222 | * | |
1223 | * We won't take down the boot processor on i386 due to some | |
1224 | * interrupts only being able to be serviced by the BSP. | |
1225 | * Especially so if we're not using an IOAPIC -zwane | |
1226 | */ | |
1227 | if (cpu == 0) | |
1228 | return -EBUSY; | |
1229 | ||
5e9ef02e | 1230 | clear_local_APIC(); |
76e4f660 AR |
1231 | |
1232 | /* | |
1233 | * HACK: | |
1234 | * Allow any queued timer interrupts to get serviced | |
1235 | * This is only a temporary solution until we cleanup | |
1236 | * fixup_irqs as we do for IA64. | |
1237 | */ | |
1238 | local_irq_enable(); | |
1239 | mdelay(1); | |
1240 | ||
1241 | local_irq_disable(); | |
1242 | remove_siblinginfo(cpu); | |
1243 | ||
1244 | /* It's now safe to remove this processor from the online map */ | |
1245 | cpu_clear(cpu, cpu_online_map); | |
1246 | remove_cpu_from_maps(); | |
1247 | fixup_irqs(cpu_online_map); | |
1248 | return 0; | |
1249 | } | |
1250 | ||
1251 | void __cpu_die(unsigned int cpu) | |
1252 | { | |
1253 | /* We don't do anything here: idle task is faking death itself. */ | |
1254 | unsigned int i; | |
1255 | ||
1256 | for (i = 0; i < 10; i++) { | |
1257 | /* They ack this in play_dead by setting CPU_DEAD */ | |
884d9e40 AR |
1258 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { |
1259 | printk ("CPU %d is now offline\n", cpu); | |
d167a518 GH |
1260 | if (1 == num_online_cpus()) |
1261 | alternatives_smp_switch(0); | |
76e4f660 | 1262 | return; |
884d9e40 | 1263 | } |
ef6e5253 | 1264 | msleep(100); |
76e4f660 AR |
1265 | } |
1266 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); | |
1267 | } | |
1268 | ||
e2c03888 | 1269 | __init int setup_additional_cpus(char *s) |
420f8f68 AK |
1270 | { |
1271 | return get_option(&s, &additional_cpus); | |
1272 | } | |
1273 | __setup("additional_cpus=", setup_additional_cpus); | |
1274 | ||
76e4f660 AR |
1275 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
1276 | ||
1277 | int __cpu_disable(void) | |
1278 | { | |
1279 | return -ENOSYS; | |
1280 | } | |
1281 | ||
1282 | void __cpu_die(unsigned int cpu) | |
1283 | { | |
1284 | /* We said "no" in __cpu_disable */ | |
1285 | BUG(); | |
1286 | } | |
1287 | #endif /* CONFIG_HOTPLUG_CPU */ |