[deliverable/linux.git] / arch / x86_64 / pci / mmconfig.c

/*
 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
 * 
 * This is an 64bit optimized version that always keeps the full mmconfig
 * space mapped. This allows lockless config space operation.
 */

#include <linux/pci.h>
#include <linux/init.h>
#include <linux/acpi.h>
#include <linux/bitmap.h>
#include <asm/e820.h>

#include "pci.h"

#define MMCONFIG_APER_SIZE (256*1024*1024)
/* Verify the first 16 busses. We assume that systems with more busses
   get MCFG right. */
#define MAX_CHECK_BUS 16

static DECLARE_BITMAP(fallback_slots, 32*MAX_CHECK_BUS);

/* Static virtual mapping of the MMCONFIG aperture */
struct mmcfg_virt {
	struct acpi_table_mcfg_config *cfg;
	char __iomem *virt;
};
static struct mmcfg_virt *pci_mmcfg_virt;

static char __iomem *get_virt(unsigned int seg, unsigned bus)
{
	int cfg_num = -1;
	struct acpi_table_mcfg_config *cfg;

	while (1) {
		++cfg_num;
		if (cfg_num >= pci_mmcfg_config_num)
			break;
		cfg = pci_mmcfg_virt[cfg_num].cfg;
		if (cfg->pci_segment_group_number != seg)
			continue;
		if ((cfg->start_bus_number <= bus) &&
		    (cfg->end_bus_number >= bus))
			return pci_mmcfg_virt[cfg_num].virt;
	}

	/* Handle more broken MCFG tables on Asus etc.
	   They only contain a single entry for bus 0-0. Assume
 	   this applies to all busses. */
	cfg = &pci_mmcfg_config[0];
	if (pci_mmcfg_config_num == 1 &&
		cfg->pci_segment_group_number == 0 &&
		(cfg->start_bus_number | cfg->end_bus_number) == 0)
		return pci_mmcfg_virt[0].virt;

	/* Fall back to type 0 */
	return NULL;
}

static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
{
	char __iomem *addr;
	if (seg == 0 && bus < MAX_CHECK_BUS &&
		test_bit(32*bus + PCI_SLOT(devfn), fallback_slots))
		return NULL;
	addr = get_virt(seg, bus);
	if (!addr)
		return NULL;
 	return addr + ((bus << 20) | (devfn << 12));
}

static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
			  unsigned int devfn, int reg, int len, u32 *value)
{
	char __iomem *addr;

	/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
	if (unlikely(!value || (bus > 255) || (devfn > 255) || (reg > 4095))) {
		*value = -1;
		return -EINVAL;
	}

	addr = pci_dev_base(seg, bus, devfn);
	if (!addr)
		return pci_conf1_read(seg,bus,devfn,reg,len,value);

	switch (len) {
	case 1:
		*value = readb(addr + reg);
		break;
	case 2:
		*value = readw(addr + reg);
		break;
	case 4:
		*value = readl(addr + reg);
		break;
	}

	return 0;
}

static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
			   unsigned int devfn, int reg, int len, u32 value)
{
	char __iomem *addr;

	/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
	if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095)))
		return -EINVAL;

	addr = pci_dev_base(seg, bus, devfn);
	if (!addr)
		return pci_conf1_write(seg,bus,devfn,reg,len,value);

	switch (len) {
	case 1:
		writeb(value, addr + reg);
		break;
	case 2:
		writew(value, addr + reg);
		break;
	case 4:
		writel(value, addr + reg);
		break;
	}

	return 0;
}

static struct pci_raw_ops pci_mmcfg = {
	.read =		pci_mmcfg_read,
	.write =	pci_mmcfg_write,
};

/* K8 systems have some devices (typically in the builtin northbridge)
   that are only accessible using type1
   Normally this can be expressed in the MCFG by not listing them
   and assigning suitable _SEGs, but this isn't implemented in some BIOS.
   Instead try to discover all devices on bus 0 that are unreachable using MM
   and fallback for them. */
static __init void unreachable_devices(void)
{
	int i, k;
	/* Use the max bus number from ACPI here? */
	for (k = 0; i < MAX_CHECK_BUS; k++) {
		for (i = 0; i < 32; i++) {
			u32 val1;
			char __iomem *addr;

			pci_conf1_read(0, k, PCI_DEVFN(i,0), 0, 4, &val1);
			if (val1 == 0xffffffff)
				continue;
			addr = pci_dev_base(0, k, PCI_DEVFN(i, 0));
			if (addr == NULL|| readl(addr) != val1) {
				set_bit(i + 32*k, fallback_slots);
				printk(KERN_NOTICE
				"PCI: No mmconfig possible on device %x:%x\n",
					k, i);
			}
		}
	}
}

void __init pci_mmcfg_init(void)
{
	int i;

	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
		return;

	acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg);
	if ((pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].base_address == 0))
		return;

	if (!e820_all_mapped(pci_mmcfg_config[0].base_address,
			pci_mmcfg_config[0].base_address + MMCONFIG_APER_SIZE,
			E820_RESERVED)) {
		printk(KERN_ERR "PCI: BIOS Bug: MCFG area is not E820-reserved\n");
		printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
		return;
	}

	/* RED-PEN i386 doesn't do _nocache right now */
	pci_mmcfg_virt = kmalloc(sizeof(*pci_mmcfg_virt) * pci_mmcfg_config_num, GFP_KERNEL);
	if (pci_mmcfg_virt == NULL) {
		printk("PCI: Can not allocate memory for mmconfig structures\n");
		return;
	}
	for (i = 0; i < pci_mmcfg_config_num; ++i) {
		pci_mmcfg_virt[i].cfg = &pci_mmcfg_config[i];
		pci_mmcfg_virt[i].virt = ioremap_nocache(pci_mmcfg_config[i].base_address, MMCONFIG_APER_SIZE);
		if (!pci_mmcfg_virt[i].virt) {
			printk("PCI: Cannot map mmconfig aperture for segment %d\n",
			       pci_mmcfg_config[i].pci_segment_group_number);
			return;
		}
		printk(KERN_INFO "PCI: Using MMCONFIG at %x\n", pci_mmcfg_config[i].base_address);
	}

	unreachable_devices();

	raw_pci_ops = &pci_mmcfg;
	pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* mmconfig.c - Low-level direct PCI config space access via MMCONFIG
	3	*
	4	* This is an 64bit optimized version that always keeps the full mmconfig
	5	* space mapped. This allows lockless config space operation.
	6	*/
	7
	8	#include <linux/pci.h>
	9	#include <linux/init.h>
54549391	10	#include <linux/acpi.h>
d6ece549	11	#include <linux/bitmap.h>
946f2ee5 AV	12	#include <asm/e820.h>
946f2ee5 AV	13
1da177e4 LT	14	#include "pci.h"
	15
	16	#define MMCONFIG_APER_SIZE (25610241024)
8c30b1a7 AK	17	/* Verify the first 16 busses. We assume that systems with more busses
	18	get MCFG right. */
	19	#define MAX_CHECK_BUS 16
1da177e4	20
8c30b1a7	21	static DECLARE_BITMAP(fallback_slots, 32*MAX_CHECK_BUS);
d6ece549	22
1da177e4	23	/* Static virtual mapping of the MMCONFIG aperture */
1cde8a16 GKH	24	struct mmcfg_virt {
1cde8a16 GKH	25	struct acpi_table_mcfg_config *cfg;
8b8a4e33	26	char __iomem *virt;
1cde8a16 GKH	27	};
1cde8a16 GKH	28	static struct mmcfg_virt *pci_mmcfg_virt;
1da177e4	29
8b8a4e33	30	static char __iomem *get_virt(unsigned int seg, unsigned bus)
1da177e4	31	{
1cde8a16 GKH	32	int cfg_num = -1;
	33	struct acpi_table_mcfg_config *cfg;
	34
	35	while (1) {
	36	++cfg_num;
3103039c AK	37	if (cfg_num >= pci_mmcfg_config_num)
3103039c AK	38	break;
1cde8a16 GKH	39	cfg = pci_mmcfg_virt[cfg_num].cfg;
	40	if (cfg->pci_segment_group_number != seg)
	41	continue;
	42	if ((cfg->start_bus_number <= bus) &&
	43	(cfg->end_bus_number >= bus))
	44	return pci_mmcfg_virt[cfg_num].virt;
	45	}
3103039c AK	46
	47	/* Handle more broken MCFG tables on Asus etc.
	48	They only contain a single entry for bus 0-0. Assume
	49	this applies to all busses. */
	50	cfg = &pci_mmcfg_config[0];
	51	if (pci_mmcfg_config_num == 1 &&
	52	cfg->pci_segment_group_number == 0 &&
	53	(cfg->start_bus_number \| cfg->end_bus_number) == 0)
1de6bf33	54	return pci_mmcfg_virt[0].virt;
3103039c AK	55
3103039c AK	56	/* Fall back to type 0 */
cc59853b	57	return NULL;
1cde8a16 GKH	58	}
1cde8a16 GKH	59
8b8a4e33	60	static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
1cde8a16	61	{
8b8a4e33	62	char __iomem *addr;
8c30b1a7 AK	63	if (seg == 0 && bus < MAX_CHECK_BUS &&
8c30b1a7 AK	64	test_bit(32*bus + PCI_SLOT(devfn), fallback_slots))
d6ece549 AK	65	return NULL;
d6ece549 AK	66	addr = get_virt(seg, bus);
928cf8c6 AK	67	if (!addr)
	68	return NULL;
	69	return addr + ((bus << 20) \| (devfn << 12));
1da177e4 LT	70	}
	71
	72	static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
	73	unsigned int devfn, int reg, int len, u32 *value)
	74	{
8b8a4e33	75	char __iomem *addr;
1da177e4	76
928cf8c6	77	/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
49c93e84 AK	78	if (unlikely(!value \|\| (bus > 255) \|\| (devfn > 255) \|\| (reg > 4095))) {
49c93e84 AK	79	*value = -1;
1da177e4	80	return -EINVAL;
49c93e84	81	}
1da177e4	82
928cf8c6 AK	83	addr = pci_dev_base(seg, bus, devfn);
	84	if (!addr)
	85	return pci_conf1_read(seg,bus,devfn,reg,len,value);
	86
1da177e4 LT	87	switch (len) {
	88	case 1:
	89	*value = readb(addr + reg);
	90	break;
	91	case 2:
	92	*value = readw(addr + reg);
	93	break;
	94	case 4:
	95	*value = readl(addr + reg);
	96	break;
	97	}
	98
	99	return 0;
	100	}
	101
	102	static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
	103	unsigned int devfn, int reg, int len, u32 value)
	104	{
8b8a4e33	105	char __iomem *addr;
1da177e4	106
928cf8c6	107	/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
1da177e4 LT	108	if (unlikely((bus > 255) \|\| (devfn > 255) \|\| (reg > 4095)))
	109	return -EINVAL;
	110
928cf8c6 AK	111	addr = pci_dev_base(seg, bus, devfn);
	112	if (!addr)
	113	return pci_conf1_write(seg,bus,devfn,reg,len,value);
	114
1da177e4 LT	115	switch (len) {
	116	case 1:
	117	writeb(value, addr + reg);
	118	break;
	119	case 2:
	120	writew(value, addr + reg);
	121	break;
	122	case 4:
	123	writel(value, addr + reg);
	124	break;
	125	}
	126
	127	return 0;
	128	}
	129
	130	static struct pci_raw_ops pci_mmcfg = {
	131	.read = pci_mmcfg_read,
	132	.write = pci_mmcfg_write,
	133	};
	134
d6ece549 AK	135	/* K8 systems have some devices (typically in the builtin northbridge)
	136	that are only accessible using type1
	137	Normally this can be expressed in the MCFG by not listing them
	138	and assigning suitable _SEGs, but this isn't implemented in some BIOS.
	139	Instead try to discover all devices on bus 0 that are unreachable using MM
8c30b1a7	140	and fallback for them. */
d6ece549 AK	141	static __init void unreachable_devices(void)
d6ece549 AK	142	{
8c30b1a7 AK	143	int i, k;
	144	/* Use the max bus number from ACPI here? */
	145	for (k = 0; i < MAX_CHECK_BUS; k++) {
	146	for (i = 0; i < 32; i++) {
	147	u32 val1;
	148	char __iomem *addr;
	149
	150	pci_conf1_read(0, k, PCI_DEVFN(i,0), 0, 4, &val1);
	151	if (val1 == 0xffffffff)
	152	continue;
	153	addr = pci_dev_base(0, k, PCI_DEVFN(i, 0));
	154	if (addr == NULL\|\| readl(addr) != val1) {
	155	set_bit(i + 32*k, fallback_slots);
	156	printk(KERN_NOTICE
	157	"PCI: No mmconfig possible on device %x:%x\n",
	158	k, i);
	159	}
d6ece549 AK	160	}
	161	}
	162	}
	163
3d1712c9	164	void __init pci_mmcfg_init(void)
1da177e4	165	{
1cde8a16 GKH	166	int i;
1cde8a16 GKH	167
1da177e4	168	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
3d1712c9	169	return;
54549391 GKH	170
	171	acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg);
	172	if ((pci_mmcfg_config_num == 0) \|\|
	173	(pci_mmcfg_config == NULL) \|\|
	174	(pci_mmcfg_config[0].base_address == 0))
3d1712c9	175	return;
1da177e4	176
946f2ee5 AV	177	if (!e820_all_mapped(pci_mmcfg_config[0].base_address,
	178	pci_mmcfg_config[0].base_address + MMCONFIG_APER_SIZE,
	179	E820_RESERVED)) {
	180	printk(KERN_ERR "PCI: BIOS Bug: MCFG area is not E820-reserved\n");
	181	printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
	182	return;
	183	}
	184
1da177e4	185	/* RED-PEN i386 doesn't do _nocache right now */
1cde8a16 GKH	186	pci_mmcfg_virt = kmalloc(sizeof(pci_mmcfg_virt) pci_mmcfg_config_num, GFP_KERNEL);
	187	if (pci_mmcfg_virt == NULL) {
	188	printk("PCI: Can not allocate memory for mmconfig structures\n");
3d1712c9	189	return;
1cde8a16 GKH	190	}
	191	for (i = 0; i < pci_mmcfg_config_num; ++i) {
	192	pci_mmcfg_virt[i].cfg = &pci_mmcfg_config[i];
	193	pci_mmcfg_virt[i].virt = ioremap_nocache(pci_mmcfg_config[i].base_address, MMCONFIG_APER_SIZE);
	194	if (!pci_mmcfg_virt[i].virt) {
	195	printk("PCI: Cannot map mmconfig aperture for segment %d\n",
	196	pci_mmcfg_config[i].pci_segment_group_number);
3d1712c9	197	return;
1cde8a16 GKH	198	}
	199	printk(KERN_INFO "PCI: Using MMCONFIG at %x\n", pci_mmcfg_config[i].base_address);
	200	}
1da177e4	201
d6ece549 AK	202	unreachable_devices();
d6ece549 AK	203
1da177e4 LT	204	raw_pci_ops = &pci_mmcfg;
1da177e4 LT	205	pci_probe = (pci_probe & ~PCI_PROBE_MASK) \| PCI_PROBE_MMCONF;
1da177e4	206	}