Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * mmconfig.c - Low-level direct PCI config space access via MMCONFIG | |
3 | * | |
4 | * This is an 64bit optimized version that always keeps the full mmconfig | |
5 | * space mapped. This allows lockless config space operation. | |
6 | */ | |
7 | ||
8 | #include <linux/pci.h> | |
9 | #include <linux/init.h> | |
54549391 | 10 | #include <linux/acpi.h> |
d6ece549 | 11 | #include <linux/bitmap.h> |
946f2ee5 AV |
12 | #include <asm/e820.h> |
13 | ||
1da177e4 LT |
14 | #include "pci.h" |
15 | ||
16 | #define MMCONFIG_APER_SIZE (256*1024*1024) | |
8c30b1a7 AK |
17 | /* Verify the first 16 busses. We assume that systems with more busses |
18 | get MCFG right. */ | |
19 | #define MAX_CHECK_BUS 16 | |
1da177e4 | 20 | |
8c30b1a7 | 21 | static DECLARE_BITMAP(fallback_slots, 32*MAX_CHECK_BUS); |
d6ece549 | 22 | |
1da177e4 | 23 | /* Static virtual mapping of the MMCONFIG aperture */ |
1cde8a16 GKH |
24 | struct mmcfg_virt { |
25 | struct acpi_table_mcfg_config *cfg; | |
8b8a4e33 | 26 | char __iomem *virt; |
1cde8a16 GKH |
27 | }; |
28 | static struct mmcfg_virt *pci_mmcfg_virt; | |
1da177e4 | 29 | |
8b8a4e33 | 30 | static char __iomem *get_virt(unsigned int seg, unsigned bus) |
1da177e4 | 31 | { |
1cde8a16 GKH |
32 | int cfg_num = -1; |
33 | struct acpi_table_mcfg_config *cfg; | |
34 | ||
35 | while (1) { | |
36 | ++cfg_num; | |
3103039c AK |
37 | if (cfg_num >= pci_mmcfg_config_num) |
38 | break; | |
1cde8a16 GKH |
39 | cfg = pci_mmcfg_virt[cfg_num].cfg; |
40 | if (cfg->pci_segment_group_number != seg) | |
41 | continue; | |
42 | if ((cfg->start_bus_number <= bus) && | |
43 | (cfg->end_bus_number >= bus)) | |
44 | return pci_mmcfg_virt[cfg_num].virt; | |
45 | } | |
3103039c AK |
46 | |
47 | /* Handle more broken MCFG tables on Asus etc. | |
48 | They only contain a single entry for bus 0-0. Assume | |
49 | this applies to all busses. */ | |
50 | cfg = &pci_mmcfg_config[0]; | |
51 | if (pci_mmcfg_config_num == 1 && | |
52 | cfg->pci_segment_group_number == 0 && | |
53 | (cfg->start_bus_number | cfg->end_bus_number) == 0) | |
1de6bf33 | 54 | return pci_mmcfg_virt[0].virt; |
3103039c AK |
55 | |
56 | /* Fall back to type 0 */ | |
cc59853b | 57 | return NULL; |
1cde8a16 GKH |
58 | } |
59 | ||
8b8a4e33 | 60 | static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn) |
1cde8a16 | 61 | { |
8b8a4e33 | 62 | char __iomem *addr; |
8c30b1a7 AK |
63 | if (seg == 0 && bus < MAX_CHECK_BUS && |
64 | test_bit(32*bus + PCI_SLOT(devfn), fallback_slots)) | |
d6ece549 AK |
65 | return NULL; |
66 | addr = get_virt(seg, bus); | |
928cf8c6 AK |
67 | if (!addr) |
68 | return NULL; | |
69 | return addr + ((bus << 20) | (devfn << 12)); | |
1da177e4 LT |
70 | } |
71 | ||
72 | static int pci_mmcfg_read(unsigned int seg, unsigned int bus, | |
73 | unsigned int devfn, int reg, int len, u32 *value) | |
74 | { | |
8b8a4e33 | 75 | char __iomem *addr; |
1da177e4 | 76 | |
928cf8c6 | 77 | /* Why do we have this when nobody checks it. How about a BUG()!? -AK */ |
1da177e4 LT |
78 | if (unlikely(!value || (bus > 255) || (devfn > 255) || (reg > 4095))) |
79 | return -EINVAL; | |
80 | ||
928cf8c6 AK |
81 | addr = pci_dev_base(seg, bus, devfn); |
82 | if (!addr) | |
83 | return pci_conf1_read(seg,bus,devfn,reg,len,value); | |
84 | ||
1da177e4 LT |
85 | switch (len) { |
86 | case 1: | |
87 | *value = readb(addr + reg); | |
88 | break; | |
89 | case 2: | |
90 | *value = readw(addr + reg); | |
91 | break; | |
92 | case 4: | |
93 | *value = readl(addr + reg); | |
94 | break; | |
95 | } | |
96 | ||
97 | return 0; | |
98 | } | |
99 | ||
100 | static int pci_mmcfg_write(unsigned int seg, unsigned int bus, | |
101 | unsigned int devfn, int reg, int len, u32 value) | |
102 | { | |
8b8a4e33 | 103 | char __iomem *addr; |
1da177e4 | 104 | |
928cf8c6 | 105 | /* Why do we have this when nobody checks it. How about a BUG()!? -AK */ |
1da177e4 LT |
106 | if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) |
107 | return -EINVAL; | |
108 | ||
928cf8c6 AK |
109 | addr = pci_dev_base(seg, bus, devfn); |
110 | if (!addr) | |
111 | return pci_conf1_write(seg,bus,devfn,reg,len,value); | |
112 | ||
1da177e4 LT |
113 | switch (len) { |
114 | case 1: | |
115 | writeb(value, addr + reg); | |
116 | break; | |
117 | case 2: | |
118 | writew(value, addr + reg); | |
119 | break; | |
120 | case 4: | |
121 | writel(value, addr + reg); | |
122 | break; | |
123 | } | |
124 | ||
125 | return 0; | |
126 | } | |
127 | ||
128 | static struct pci_raw_ops pci_mmcfg = { | |
129 | .read = pci_mmcfg_read, | |
130 | .write = pci_mmcfg_write, | |
131 | }; | |
132 | ||
d6ece549 AK |
133 | /* K8 systems have some devices (typically in the builtin northbridge) |
134 | that are only accessible using type1 | |
135 | Normally this can be expressed in the MCFG by not listing them | |
136 | and assigning suitable _SEGs, but this isn't implemented in some BIOS. | |
137 | Instead try to discover all devices on bus 0 that are unreachable using MM | |
8c30b1a7 | 138 | and fallback for them. */ |
d6ece549 AK |
139 | static __init void unreachable_devices(void) |
140 | { | |
8c30b1a7 AK |
141 | int i, k; |
142 | /* Use the max bus number from ACPI here? */ | |
143 | for (k = 0; i < MAX_CHECK_BUS; k++) { | |
144 | for (i = 0; i < 32; i++) { | |
145 | u32 val1; | |
146 | char __iomem *addr; | |
147 | ||
148 | pci_conf1_read(0, k, PCI_DEVFN(i,0), 0, 4, &val1); | |
149 | if (val1 == 0xffffffff) | |
150 | continue; | |
151 | addr = pci_dev_base(0, k, PCI_DEVFN(i, 0)); | |
152 | if (addr == NULL|| readl(addr) != val1) { | |
153 | set_bit(i + 32*k, fallback_slots); | |
154 | printk(KERN_NOTICE | |
155 | "PCI: No mmconfig possible on device %x:%x\n", | |
156 | k, i); | |
157 | } | |
d6ece549 AK |
158 | } |
159 | } | |
160 | } | |
161 | ||
3d1712c9 | 162 | void __init pci_mmcfg_init(void) |
1da177e4 | 163 | { |
1cde8a16 GKH |
164 | int i; |
165 | ||
1da177e4 | 166 | if ((pci_probe & PCI_PROBE_MMCONF) == 0) |
3d1712c9 | 167 | return; |
54549391 GKH |
168 | |
169 | acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg); | |
170 | if ((pci_mmcfg_config_num == 0) || | |
171 | (pci_mmcfg_config == NULL) || | |
172 | (pci_mmcfg_config[0].base_address == 0)) | |
3d1712c9 | 173 | return; |
1da177e4 | 174 | |
946f2ee5 AV |
175 | if (!e820_all_mapped(pci_mmcfg_config[0].base_address, |
176 | pci_mmcfg_config[0].base_address + MMCONFIG_APER_SIZE, | |
177 | E820_RESERVED)) { | |
178 | printk(KERN_ERR "PCI: BIOS Bug: MCFG area is not E820-reserved\n"); | |
179 | printk(KERN_ERR "PCI: Not using MMCONFIG.\n"); | |
180 | return; | |
181 | } | |
182 | ||
1da177e4 | 183 | /* RED-PEN i386 doesn't do _nocache right now */ |
1cde8a16 GKH |
184 | pci_mmcfg_virt = kmalloc(sizeof(*pci_mmcfg_virt) * pci_mmcfg_config_num, GFP_KERNEL); |
185 | if (pci_mmcfg_virt == NULL) { | |
186 | printk("PCI: Can not allocate memory for mmconfig structures\n"); | |
3d1712c9 | 187 | return; |
1cde8a16 GKH |
188 | } |
189 | for (i = 0; i < pci_mmcfg_config_num; ++i) { | |
190 | pci_mmcfg_virt[i].cfg = &pci_mmcfg_config[i]; | |
191 | pci_mmcfg_virt[i].virt = ioremap_nocache(pci_mmcfg_config[i].base_address, MMCONFIG_APER_SIZE); | |
192 | if (!pci_mmcfg_virt[i].virt) { | |
193 | printk("PCI: Cannot map mmconfig aperture for segment %d\n", | |
194 | pci_mmcfg_config[i].pci_segment_group_number); | |
3d1712c9 | 195 | return; |
1cde8a16 GKH |
196 | } |
197 | printk(KERN_INFO "PCI: Using MMCONFIG at %x\n", pci_mmcfg_config[i].base_address); | |
198 | } | |
1da177e4 | 199 | |
d6ece549 AK |
200 | unreachable_devices(); |
201 | ||
1da177e4 LT |
202 | raw_pci_ops = &pci_mmcfg; |
203 | pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; | |
1da177e4 | 204 | } |