[deliverable/linux.git] / arch / x86_64 / pci / mmconfig.c

/*
 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
 * 
 * This is an 64bit optimized version that always keeps the full mmconfig
 * space mapped. This allows lockless config space operation.
 */

#include <linux/pci.h>
#include <linux/init.h>
#include <linux/acpi.h>
#include <linux/bitmap.h>
#include <asm/e820.h>

#include "pci.h"

#define MMCONFIG_APER_SIZE (256*1024*1024)

static DECLARE_BITMAP(fallback_slots, 32);

/* Static virtual mapping of the MMCONFIG aperture */
struct mmcfg_virt {
	struct acpi_table_mcfg_config *cfg;
	char __iomem *virt;
};
static struct mmcfg_virt *pci_mmcfg_virt;

static char __iomem *get_virt(unsigned int seg, unsigned bus)
{
	int cfg_num = -1;
	struct acpi_table_mcfg_config *cfg;

	while (1) {
		++cfg_num;
		if (cfg_num >= pci_mmcfg_config_num)
			break;
		cfg = pci_mmcfg_virt[cfg_num].cfg;
		if (cfg->pci_segment_group_number != seg)
			continue;
		if ((cfg->start_bus_number <= bus) &&
		    (cfg->end_bus_number >= bus))
			return pci_mmcfg_virt[cfg_num].virt;
	}

	/* Handle more broken MCFG tables on Asus etc.
	   They only contain a single entry for bus 0-0. Assume
 	   this applies to all busses. */
	cfg = &pci_mmcfg_config[0];
	if (pci_mmcfg_config_num == 1 &&
		cfg->pci_segment_group_number == 0 &&
		(cfg->start_bus_number | cfg->end_bus_number) == 0)
		return pci_mmcfg_virt[0].virt;

	/* Fall back to type 0 */
	return NULL;
}

static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
{
	char __iomem *addr;
	if (seg == 0 && bus == 0 && test_bit(PCI_SLOT(devfn), fallback_slots))
		return NULL;
	addr = get_virt(seg, bus);
	if (!addr)
		return NULL;
 	return addr + ((bus << 20) | (devfn << 12));
}

static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
			  unsigned int devfn, int reg, int len, u32 *value)
{
	char __iomem *addr;

	/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
	if (unlikely(!value || (bus > 255) || (devfn > 255) || (reg > 4095)))
		return -EINVAL;

	addr = pci_dev_base(seg, bus, devfn);
	if (!addr)
		return pci_conf1_read(seg,bus,devfn,reg,len,value);

	switch (len) {
	case 1:
		*value = readb(addr + reg);
		break;
	case 2:
		*value = readw(addr + reg);
		break;
	case 4:
		*value = readl(addr + reg);
		break;
	}

	return 0;
}

static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
			   unsigned int devfn, int reg, int len, u32 value)
{
	char __iomem *addr;

	/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
	if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095)))
		return -EINVAL;

	addr = pci_dev_base(seg, bus, devfn);
	if (!addr)
		return pci_conf1_write(seg,bus,devfn,reg,len,value);

	switch (len) {
	case 1:
		writeb(value, addr + reg);
		break;
	case 2:
		writew(value, addr + reg);
		break;
	case 4:
		writel(value, addr + reg);
		break;
	}

	return 0;
}

static struct pci_raw_ops pci_mmcfg = {
	.read =		pci_mmcfg_read,
	.write =	pci_mmcfg_write,
};

/* K8 systems have some devices (typically in the builtin northbridge)
   that are only accessible using type1
   Normally this can be expressed in the MCFG by not listing them
   and assigning suitable _SEGs, but this isn't implemented in some BIOS.
   Instead try to discover all devices on bus 0 that are unreachable using MM
   and fallback for them.
   We only do this for bus 0/seg 0 */
static __init void unreachable_devices(void)
{
	int i;
	for (i = 0; i < 32; i++) {
		u32 val1;
		char __iomem *addr;

		pci_conf1_read(0, 0, PCI_DEVFN(i,0), 0, 4, &val1);
		if (val1 == 0xffffffff)
			continue;
		addr = pci_dev_base(0, 0, PCI_DEVFN(i, 0));
		if (addr == NULL|| readl(addr) != val1) {
			set_bit(i, fallback_slots);
		}
	}
}

void __init pci_mmcfg_init(void)
{
	int i;

	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
		return;

	acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg);
	if ((pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].base_address == 0))
		return;

	if (!e820_all_mapped(pci_mmcfg_config[0].base_address,
			pci_mmcfg_config[0].base_address + MMCONFIG_APER_SIZE,
			E820_RESERVED)) {
		printk(KERN_ERR "PCI: BIOS Bug: MCFG area is not E820-reserved\n");
		printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
		return;
	}

	/* RED-PEN i386 doesn't do _nocache right now */
	pci_mmcfg_virt = kmalloc(sizeof(*pci_mmcfg_virt) * pci_mmcfg_config_num, GFP_KERNEL);
	if (pci_mmcfg_virt == NULL) {
		printk("PCI: Can not allocate memory for mmconfig structures\n");
		return;
	}
	for (i = 0; i < pci_mmcfg_config_num; ++i) {
		pci_mmcfg_virt[i].cfg = &pci_mmcfg_config[i];
		pci_mmcfg_virt[i].virt = ioremap_nocache(pci_mmcfg_config[i].base_address, MMCONFIG_APER_SIZE);
		if (!pci_mmcfg_virt[i].virt) {
			printk("PCI: Cannot map mmconfig aperture for segment %d\n",
			       pci_mmcfg_config[i].pci_segment_group_number);
			return;
		}
		printk(KERN_INFO "PCI: Using MMCONFIG at %x\n", pci_mmcfg_config[i].base_address);
	}

	unreachable_devices();

	raw_pci_ops = &pci_mmcfg;
	pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* mmconfig.c - Low-level direct PCI config space access via MMCONFIG
	3	*
	4	* This is an 64bit optimized version that always keeps the full mmconfig
	5	* space mapped. This allows lockless config space operation.
	6	*/
	7
	8	#include <linux/pci.h>
	9	#include <linux/init.h>
54549391	10	#include <linux/acpi.h>
d6ece549	11	#include <linux/bitmap.h>
946f2ee5 AV	12	#include <asm/e820.h>
946f2ee5 AV	13
1da177e4 LT	14	#include "pci.h"
	15
	16	#define MMCONFIG_APER_SIZE (25610241024)
	17
d6ece549 AK	18	static DECLARE_BITMAP(fallback_slots, 32);
d6ece549 AK	19
1da177e4	20	/* Static virtual mapping of the MMCONFIG aperture */
1cde8a16 GKH	21	struct mmcfg_virt {
1cde8a16 GKH	22	struct acpi_table_mcfg_config *cfg;
8b8a4e33	23	char __iomem *virt;
1cde8a16 GKH	24	};
1cde8a16 GKH	25	static struct mmcfg_virt *pci_mmcfg_virt;
1da177e4	26
8b8a4e33	27	static char __iomem *get_virt(unsigned int seg, unsigned bus)
1da177e4	28	{
1cde8a16 GKH	29	int cfg_num = -1;
	30	struct acpi_table_mcfg_config *cfg;
	31
	32	while (1) {
	33	++cfg_num;
3103039c AK	34	if (cfg_num >= pci_mmcfg_config_num)
3103039c AK	35	break;
1cde8a16 GKH	36	cfg = pci_mmcfg_virt[cfg_num].cfg;
	37	if (cfg->pci_segment_group_number != seg)
	38	continue;
	39	if ((cfg->start_bus_number <= bus) &&
	40	(cfg->end_bus_number >= bus))
	41	return pci_mmcfg_virt[cfg_num].virt;
	42	}
3103039c AK	43
	44	/* Handle more broken MCFG tables on Asus etc.
	45	They only contain a single entry for bus 0-0. Assume
	46	this applies to all busses. */
	47	cfg = &pci_mmcfg_config[0];
	48	if (pci_mmcfg_config_num == 1 &&
	49	cfg->pci_segment_group_number == 0 &&
	50	(cfg->start_bus_number \| cfg->end_bus_number) == 0)
1de6bf33	51	return pci_mmcfg_virt[0].virt;
3103039c AK	52
3103039c AK	53	/* Fall back to type 0 */
cc59853b	54	return NULL;
1cde8a16 GKH	55	}
1cde8a16 GKH	56
8b8a4e33	57	static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
1cde8a16	58	{
8b8a4e33	59	char __iomem *addr;
3d1712c9	60	if (seg == 0 && bus == 0 && test_bit(PCI_SLOT(devfn), fallback_slots))
d6ece549 AK	61	return NULL;
d6ece549 AK	62	addr = get_virt(seg, bus);
928cf8c6 AK	63	if (!addr)
	64	return NULL;
	65	return addr + ((bus << 20) \| (devfn << 12));
1da177e4 LT	66	}
	67
	68	static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
	69	unsigned int devfn, int reg, int len, u32 *value)
	70	{
8b8a4e33	71	char __iomem *addr;
1da177e4	72
928cf8c6	73	/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
1da177e4 LT	74	if (unlikely(!value \|\| (bus > 255) \|\| (devfn > 255) \|\| (reg > 4095)))
	75	return -EINVAL;
	76
928cf8c6 AK	77	addr = pci_dev_base(seg, bus, devfn);
	78	if (!addr)
	79	return pci_conf1_read(seg,bus,devfn,reg,len,value);
	80
1da177e4 LT	81	switch (len) {
	82	case 1:
	83	*value = readb(addr + reg);
	84	break;
	85	case 2:
	86	*value = readw(addr + reg);
	87	break;
	88	case 4:
	89	*value = readl(addr + reg);
	90	break;
	91	}
	92
	93	return 0;
	94	}
	95
	96	static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
	97	unsigned int devfn, int reg, int len, u32 value)
	98	{
8b8a4e33	99	char __iomem *addr;
1da177e4	100
928cf8c6	101	/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
1da177e4 LT	102	if (unlikely((bus > 255) \|\| (devfn > 255) \|\| (reg > 4095)))
	103	return -EINVAL;
	104
928cf8c6 AK	105	addr = pci_dev_base(seg, bus, devfn);
	106	if (!addr)
	107	return pci_conf1_write(seg,bus,devfn,reg,len,value);
	108
1da177e4 LT	109	switch (len) {
	110	case 1:
	111	writeb(value, addr + reg);
	112	break;
	113	case 2:
	114	writew(value, addr + reg);
	115	break;
	116	case 4:
	117	writel(value, addr + reg);
	118	break;
	119	}
	120
	121	return 0;
	122	}
	123
	124	static struct pci_raw_ops pci_mmcfg = {
	125	.read = pci_mmcfg_read,
	126	.write = pci_mmcfg_write,
	127	};
	128
d6ece549 AK	129	/* K8 systems have some devices (typically in the builtin northbridge)
	130	that are only accessible using type1
	131	Normally this can be expressed in the MCFG by not listing them
	132	and assigning suitable _SEGs, but this isn't implemented in some BIOS.
	133	Instead try to discover all devices on bus 0 that are unreachable using MM
	134	and fallback for them.
	135	We only do this for bus 0/seg 0 */
	136	static __init void unreachable_devices(void)
	137	{
	138	int i;
	139	for (i = 0; i < 32; i++) {
	140	u32 val1;
8b8a4e33	141	char __iomem *addr;
d6ece549 AK	142
	143	pci_conf1_read(0, 0, PCI_DEVFN(i,0), 0, 4, &val1);
	144	if (val1 == 0xffffffff)
	145	continue;
	146	addr = pci_dev_base(0, 0, PCI_DEVFN(i, 0));
	147	if (addr == NULL\|\| readl(addr) != val1) {
3d1712c9	148	set_bit(i, fallback_slots);
d6ece549 AK	149	}
	150	}
	151	}
	152
3d1712c9	153	void __init pci_mmcfg_init(void)
1da177e4	154	{
1cde8a16 GKH	155	int i;
1cde8a16 GKH	156
1da177e4	157	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
3d1712c9	158	return;
54549391 GKH	159
	160	acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg);
	161	if ((pci_mmcfg_config_num == 0) \|\|
	162	(pci_mmcfg_config == NULL) \|\|
	163	(pci_mmcfg_config[0].base_address == 0))
3d1712c9	164	return;
1da177e4	165
946f2ee5 AV	166	if (!e820_all_mapped(pci_mmcfg_config[0].base_address,
	167	pci_mmcfg_config[0].base_address + MMCONFIG_APER_SIZE,
	168	E820_RESERVED)) {
	169	printk(KERN_ERR "PCI: BIOS Bug: MCFG area is not E820-reserved\n");
	170	printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
	171	return;
	172	}
	173
1da177e4	174	/* RED-PEN i386 doesn't do _nocache right now */
1cde8a16 GKH	175	pci_mmcfg_virt = kmalloc(sizeof(pci_mmcfg_virt) pci_mmcfg_config_num, GFP_KERNEL);
	176	if (pci_mmcfg_virt == NULL) {
	177	printk("PCI: Can not allocate memory for mmconfig structures\n");
3d1712c9	178	return;
1cde8a16 GKH	179	}
	180	for (i = 0; i < pci_mmcfg_config_num; ++i) {
	181	pci_mmcfg_virt[i].cfg = &pci_mmcfg_config[i];
	182	pci_mmcfg_virt[i].virt = ioremap_nocache(pci_mmcfg_config[i].base_address, MMCONFIG_APER_SIZE);
	183	if (!pci_mmcfg_virt[i].virt) {
	184	printk("PCI: Cannot map mmconfig aperture for segment %d\n",
	185	pci_mmcfg_config[i].pci_segment_group_number);
3d1712c9	186	return;
1cde8a16 GKH	187	}
	188	printk(KERN_INFO "PCI: Using MMCONFIG at %x\n", pci_mmcfg_config[i].base_address);
	189	}
1da177e4	190
d6ece549 AK	191	unreachable_devices();
d6ece549 AK	192
1da177e4 LT	193	raw_pci_ops = &pci_mmcfg;
1da177e4 LT	194	pci_probe = (pci_probe & ~PCI_PROBE_MASK) \| PCI_PROBE_MMCONF;
1da177e4	195	}