[PATCH] mmconfig: Fix x86_64 ioremap base_address
[deliverable/linux.git] / arch / x86_64 / pci / mmconfig.c
CommitLineData
1da177e4
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1/*
2 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
15a58ed1 3 *
1da177e4
LT
4 * This is an 64bit optimized version that always keeps the full mmconfig
5 * space mapped. This allows lockless config space operation.
6 */
7
8#include <linux/pci.h>
9#include <linux/init.h>
54549391 10#include <linux/acpi.h>
d6ece549 11#include <linux/bitmap.h>
946f2ee5
AV
12#include <asm/e820.h>
13
1da177e4
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14#include "pci.h"
15
ead2bfeb
CE
16/* aperture is up to 256MB but BIOS may reserve less */
17#define MMCONFIG_APER_MIN (2 * 1024*1024)
18#define MMCONFIG_APER_MAX (256 * 1024*1024)
19
8c30b1a7
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20/* Verify the first 16 busses. We assume that systems with more busses
21 get MCFG right. */
b7867394 22#define PCI_MMCFG_MAX_CHECK_BUS 16
d6ece549 23
1da177e4 24/* Static virtual mapping of the MMCONFIG aperture */
1cde8a16 25struct mmcfg_virt {
15a58ed1 26 struct acpi_mcfg_allocation *cfg;
8b8a4e33 27 char __iomem *virt;
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GKH
28};
29static struct mmcfg_virt *pci_mmcfg_virt;
1da177e4 30
faed197b
OH
31static inline int mcfg_broken(void)
32{
33 struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[0];
34
35 /* Handle more broken MCFG tables on Asus etc.
36 They only contain a single entry for bus 0-0. Assume
37 this applies to all busses. */
38 if (pci_mmcfg_config_num == 1 &&
39 cfg->pci_segment_group_number == 0 &&
40 (cfg->start_bus_number | cfg->end_bus_number) == 0)
41 return 1;
42 return 0;
43}
44
45static void __iomem *mcfg_ioremap(struct acpi_mcfg_allocation *cfg)
46{
47 void __iomem *addr;
48 u32 size;
49
50 if (mcfg_broken())
51 size = 256 << 20;
52 else
53 size = (cfg->end_bus_number + 1) << 20;
54
55 addr = ioremap_nocache(cfg->base_address, size);
56 if (addr) {
57 printk(KERN_INFO "PCI: Using MMCONFIG at %x - %x\n",
58 cfg->base_address,
59 cfg->base_address + size - 1);
60 }
61 return addr;
62}
63
8b8a4e33 64static char __iomem *get_virt(unsigned int seg, unsigned bus)
1da177e4 65{
1cde8a16 66 int cfg_num = -1;
15a58ed1 67 struct acpi_mcfg_allocation *cfg;
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68
69 while (1) {
70 ++cfg_num;
3103039c
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71 if (cfg_num >= pci_mmcfg_config_num)
72 break;
1cde8a16 73 cfg = pci_mmcfg_virt[cfg_num].cfg;
15a58ed1 74 if (cfg->pci_segment != seg)
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GKH
75 continue;
76 if ((cfg->start_bus_number <= bus) &&
77 (cfg->end_bus_number >= bus))
78 return pci_mmcfg_virt[cfg_num].virt;
79 }
3103039c 80
faed197b 81 if (mcfg_broken())
1de6bf33 82 return pci_mmcfg_virt[0].virt;
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83
84 /* Fall back to type 0 */
cc59853b 85 return NULL;
1cde8a16
GKH
86}
87
8b8a4e33 88static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
1cde8a16 89{
8b8a4e33 90 char __iomem *addr;
b7867394
OG
91 if (seg == 0 && bus < PCI_MMCFG_MAX_CHECK_BUS &&
92 test_bit(32*bus + PCI_SLOT(devfn), pci_mmcfg_fallback_slots))
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93 return NULL;
94 addr = get_virt(seg, bus);
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95 if (!addr)
96 return NULL;
97 return addr + ((bus << 20) | (devfn << 12));
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98}
99
100static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
101 unsigned int devfn, int reg, int len, u32 *value)
102{
8b8a4e33 103 char __iomem *addr;
1da177e4 104
928cf8c6 105 /* Why do we have this when nobody checks it. How about a BUG()!? -AK */
ecc16ba9 106 if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) {
49c93e84 107 *value = -1;
1da177e4 108 return -EINVAL;
49c93e84 109 }
1da177e4 110
928cf8c6
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111 addr = pci_dev_base(seg, bus, devfn);
112 if (!addr)
113 return pci_conf1_read(seg,bus,devfn,reg,len,value);
114
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LT
115 switch (len) {
116 case 1:
117 *value = readb(addr + reg);
118 break;
119 case 2:
120 *value = readw(addr + reg);
121 break;
122 case 4:
123 *value = readl(addr + reg);
124 break;
125 }
126
127 return 0;
128}
129
130static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
131 unsigned int devfn, int reg, int len, u32 value)
132{
8b8a4e33 133 char __iomem *addr;
1da177e4 134
928cf8c6 135 /* Why do we have this when nobody checks it. How about a BUG()!? -AK */
1da177e4
LT
136 if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095)))
137 return -EINVAL;
138
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139 addr = pci_dev_base(seg, bus, devfn);
140 if (!addr)
141 return pci_conf1_write(seg,bus,devfn,reg,len,value);
142
1da177e4
LT
143 switch (len) {
144 case 1:
145 writeb(value, addr + reg);
146 break;
147 case 2:
148 writew(value, addr + reg);
149 break;
150 case 4:
151 writel(value, addr + reg);
152 break;
153 }
154
155 return 0;
156}
157
158static struct pci_raw_ops pci_mmcfg = {
159 .read = pci_mmcfg_read,
160 .write = pci_mmcfg_write,
161};
162
b7867394 163int __init pci_mmcfg_arch_init(void)
1da177e4 164{
1cde8a16 165 int i;
b7867394
OG
166 pci_mmcfg_virt = kmalloc(sizeof(*pci_mmcfg_virt) *
167 pci_mmcfg_config_num, GFP_KERNEL);
1cde8a16 168 if (pci_mmcfg_virt == NULL) {
3095fc0c 169 printk(KERN_ERR "PCI: Can not allocate memory for mmconfig structures\n");
b7867394 170 return 0;
1cde8a16 171 }
b7867394 172
1cde8a16
GKH
173 for (i = 0; i < pci_mmcfg_config_num; ++i) {
174 pci_mmcfg_virt[i].cfg = &pci_mmcfg_config[i];
faed197b 175 pci_mmcfg_virt[i].virt = mcfg_ioremap(&pci_mmcfg_config[i]);
1cde8a16 176 if (!pci_mmcfg_virt[i].virt) {
3095fc0c
DJ
177 printk(KERN_ERR "PCI: Cannot map mmconfig aperture for "
178 "segment %d\n",
15a58ed1 179 pci_mmcfg_config[i].pci_segment);
b7867394 180 return 0;
1cde8a16 181 }
1cde8a16 182 }
1da177e4 183 raw_pci_ops = &pci_mmcfg;
b7867394 184 return 1;
1da177e4 185}
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