projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| f1883aa7 MF |
1 | /* |
| 2 | * Kernel virtual memory layout definitions. | |
| 3 | * | |
| 4 | * This file is subject to the terms and conditions of the GNU General | |
| 5 | * Public License. See the file "COPYING" in the main directory of | |
| 6 | * this archive for more details. | |
| 7 | * | |
| 8 | * Copyright (C) 2016 Cadence Design Systems Inc. | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef _XTENSA_KMEM_LAYOUT_H | |
| 12 | #define _XTENSA_KMEM_LAYOUT_H | |
| 13 | ||
| 14 | #include <asm/types.h> | |
| 15 | ||
| d39af902 MF |
16 | #ifdef CONFIG_MMU |
| 17 | ||
| f1883aa7 MF |
18 | /* |
| 19 | * Fixed TLB translations in the processor. | |
| 20 | */ | |
| 21 | ||
| d39af902 MF |
22 | #define XCHAL_PAGE_TABLE_VADDR __XTENSA_UL_CONST(0x80000000) |
| 23 | #define XCHAL_PAGE_TABLE_SIZE __XTENSA_UL_CONST(0x00400000) | |
| 24 | ||
| 25 | #if defined(CONFIG_XTENSA_KSEG_MMU_V2) | |
| 26 | ||
| f1883aa7 MF |
27 | #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000) |
| 28 | #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000) | |
| 29 | #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000) | |
| d39af902 MF |
30 | #define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x08000000) |
| 31 | #define XCHAL_KSEG_TLB_WAY 5 | |
| a9f2fc62 | 32 | #define XCHAL_KIO_TLB_WAY 6 |
| d39af902 MF |
33 | |
| 34 | #elif defined(CONFIG_XTENSA_KSEG_256M) | |
| 35 | ||
| 36 | #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xb0000000) | |
| 37 | #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xc0000000) | |
| 38 | #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x10000000) | |
| 39 | #define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x10000000) | |
| 40 | #define XCHAL_KSEG_TLB_WAY 6 | |
| a9f2fc62 | 41 | #define XCHAL_KIO_TLB_WAY 6 |
| d39af902 MF |
42 | |
| 43 | #elif defined(CONFIG_XTENSA_KSEG_512M) | |
| 44 | ||
| 45 | #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xa0000000) | |
| 46 | #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xc0000000) | |
| 47 | #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x20000000) | |
| 48 | #define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x10000000) | |
| 49 | #define XCHAL_KSEG_TLB_WAY 6 | |
| a9f2fc62 | 50 | #define XCHAL_KIO_TLB_WAY 6 |
| d39af902 MF |
51 | |
| 52 | #else | |
| 53 | #error Unsupported KSEG configuration | |
| 54 | #endif | |
| 55 | ||
| 56 | #ifdef CONFIG_KSEG_PADDR | |
| 57 | #define XCHAL_KSEG_PADDR __XTENSA_UL_CONST(CONFIG_KSEG_PADDR) | |
| 58 | #else | |
| f1883aa7 | 59 | #define XCHAL_KSEG_PADDR __XTENSA_UL_CONST(0x00000000) |
| d39af902 MF |
60 | #endif |
| 61 | ||
| 62 | #if XCHAL_KSEG_PADDR & (XCHAL_KSEG_ALIGNMENT - 1) | |
| 63 | #error XCHAL_KSEG_PADDR is not properly aligned to XCHAL_KSEG_ALIGNMENT | |
| 64 | #endif | |
| 65 | ||
| 66 | #else | |
| 67 | ||
| 68 | #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000) | |
| 69 | #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000) | |
| 70 | #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000) | |
| 71 | ||
| 72 | #endif | |
| f1883aa7 MF |
73 | |
| 74 | #endif |