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1 | /* |
2 | * arch/xtensa/kernel/entry.S | |
3 | * | |
4 | * Low-level exception handling | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | * | |
6656920b | 10 | * Copyright (C) 2004-2007 by Tensilica Inc. |
5a0015d6 CZ |
11 | * |
12 | * Chris Zankel <chris@zankel.net> | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/linkage.h> | |
0013a854 | 17 | #include <asm/asm-offsets.h> |
5a0015d6 CZ |
18 | #include <asm/processor.h> |
19 | #include <asm/thread_info.h> | |
20 | #include <asm/uaccess.h> | |
21 | #include <asm/unistd.h> | |
22 | #include <asm/ptrace.h> | |
23 | #include <asm/current.h> | |
24 | #include <asm/pgtable.h> | |
25 | #include <asm/page.h> | |
26 | #include <asm/signal.h> | |
173d6681 | 27 | #include <asm/tlbflush.h> |
5a0015d6 CZ |
28 | |
29 | /* Unimplemented features. */ | |
30 | ||
5a0015d6 CZ |
31 | #undef KERNEL_STACK_OVERFLOW_CHECK |
32 | #undef PREEMPTIBLE_KERNEL | |
33 | #undef ALLOCA_EXCEPTION_IN_IRAM | |
34 | ||
35 | /* Not well tested. | |
36 | * | |
37 | * - fast_coprocessor | |
38 | */ | |
39 | ||
40 | /* | |
41 | * Macro to find first bit set in WINDOWBASE from the left + 1 | |
42 | * | |
43 | * 100....0 -> 1 | |
44 | * 010....0 -> 2 | |
45 | * 000....1 -> WSBITS | |
46 | */ | |
47 | ||
48 | .macro ffs_ws bit mask | |
49 | ||
50 | #if XCHAL_HAVE_NSA | |
51 | nsau \bit, \mask # 32-WSBITS ... 31 (32 iff 0) | |
52 | addi \bit, \bit, WSBITS - 32 + 1 # uppest bit set -> return 1 | |
53 | #else | |
54 | movi \bit, WSBITS | |
55 | #if WSBITS > 16 | |
56 | _bltui \mask, 0x10000, 99f | |
57 | addi \bit, \bit, -16 | |
58 | extui \mask, \mask, 16, 16 | |
59 | #endif | |
60 | #if WSBITS > 8 | |
61 | 99: _bltui \mask, 0x100, 99f | |
62 | addi \bit, \bit, -8 | |
63 | srli \mask, \mask, 8 | |
64 | #endif | |
65 | 99: _bltui \mask, 0x10, 99f | |
66 | addi \bit, \bit, -4 | |
67 | srli \mask, \mask, 4 | |
68 | 99: _bltui \mask, 0x4, 99f | |
69 | addi \bit, \bit, -2 | |
70 | srli \mask, \mask, 2 | |
71 | 99: _bltui \mask, 0x2, 99f | |
72 | addi \bit, \bit, -1 | |
73 | 99: | |
74 | ||
75 | #endif | |
76 | .endm | |
77 | ||
78 | /* ----------------- DEFAULT FIRST LEVEL EXCEPTION HANDLERS ----------------- */ | |
79 | ||
80 | /* | |
81 | * First-level exception handler for user exceptions. | |
82 | * Save some special registers, extra states and all registers in the AR | |
83 | * register file that were in use in the user task, and jump to the common | |
84 | * exception code. | |
85 | * We save SAR (used to calculate WMASK), and WB and WS (we don't have to | |
86 | * save them for kernel exceptions). | |
87 | * | |
88 | * Entry condition for user_exception: | |
89 | * | |
90 | * a0: trashed, original value saved on stack (PT_AREG0) | |
91 | * a1: a1 | |
92 | * a2: new stack pointer, original value in depc | |
93 | * a3: dispatch table | |
94 | * depc: a2, original value saved on stack (PT_DEPC) | |
95 | * excsave1: a3 | |
96 | * | |
97 | * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC | |
98 | * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception | |
99 | * | |
100 | * Entry condition for _user_exception: | |
101 | * | |
102 | * a0-a3 and depc have been saved to PT_AREG0...PT_AREG3 and PT_DEPC | |
103 | * excsave has been restored, and | |
104 | * stack pointer (a1) has been set. | |
105 | * | |
106 | * Note: _user_exception might be at an odd adress. Don't use call0..call12 | |
107 | */ | |
108 | ||
109 | ENTRY(user_exception) | |
110 | ||
111 | /* Save a2, a3, and depc, restore excsave_1 and set SP. */ | |
112 | ||
113 | xsr a3, EXCSAVE_1 | |
114 | rsr a0, DEPC | |
115 | s32i a1, a2, PT_AREG1 | |
116 | s32i a0, a2, PT_AREG2 | |
117 | s32i a3, a2, PT_AREG3 | |
118 | mov a1, a2 | |
119 | ||
120 | .globl _user_exception | |
121 | _user_exception: | |
122 | ||
123 | /* Save SAR and turn off single stepping */ | |
124 | ||
125 | movi a2, 0 | |
126 | rsr a3, SAR | |
29c4dfd9 | 127 | xsr a2, ICOUNTLEVEL |
5a0015d6 | 128 | s32i a3, a1, PT_SAR |
29c4dfd9 | 129 | s32i a2, a1, PT_ICOUNTLEVEL |
5a0015d6 CZ |
130 | |
131 | /* Rotate ws so that the current windowbase is at bit0. */ | |
132 | /* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */ | |
133 | ||
134 | rsr a2, WINDOWBASE | |
135 | rsr a3, WINDOWSTART | |
136 | ssr a2 | |
137 | s32i a2, a1, PT_WINDOWBASE | |
138 | s32i a3, a1, PT_WINDOWSTART | |
139 | slli a2, a3, 32-WSBITS | |
140 | src a2, a3, a2 | |
141 | srli a2, a2, 32-WSBITS | |
142 | s32i a2, a1, PT_WMASK # needed for restoring registers | |
143 | ||
144 | /* Save only live registers. */ | |
145 | ||
146 | _bbsi.l a2, 1, 1f | |
147 | s32i a4, a1, PT_AREG4 | |
148 | s32i a5, a1, PT_AREG5 | |
149 | s32i a6, a1, PT_AREG6 | |
150 | s32i a7, a1, PT_AREG7 | |
151 | _bbsi.l a2, 2, 1f | |
152 | s32i a8, a1, PT_AREG8 | |
153 | s32i a9, a1, PT_AREG9 | |
154 | s32i a10, a1, PT_AREG10 | |
155 | s32i a11, a1, PT_AREG11 | |
156 | _bbsi.l a2, 3, 1f | |
157 | s32i a12, a1, PT_AREG12 | |
158 | s32i a13, a1, PT_AREG13 | |
159 | s32i a14, a1, PT_AREG14 | |
160 | s32i a15, a1, PT_AREG15 | |
161 | _bnei a2, 1, 1f # only one valid frame? | |
162 | ||
163 | /* Only one valid frame, skip saving regs. */ | |
164 | ||
165 | j 2f | |
166 | ||
167 | /* Save the remaining registers. | |
168 | * We have to save all registers up to the first '1' from | |
169 | * the right, except the current frame (bit 0). | |
170 | * Assume a2 is: 001001000110001 | |
6656920b | 171 | * All register frames starting from the top field to the marked '1' |
5a0015d6 CZ |
172 | * must be saved. |
173 | */ | |
174 | ||
175 | 1: addi a3, a2, -1 # eliminate '1' in bit 0: yyyyxxww0 | |
176 | neg a3, a3 # yyyyxxww0 -> YYYYXXWW1+1 | |
177 | and a3, a3, a2 # max. only one bit is set | |
178 | ||
179 | /* Find number of frames to save */ | |
180 | ||
181 | ffs_ws a0, a3 # number of frames to the '1' from left | |
182 | ||
183 | /* Store information into WMASK: | |
184 | * bits 0..3: xxx1 masked lower 4 bits of the rotated windowstart, | |
185 | * bits 4...: number of valid 4-register frames | |
186 | */ | |
187 | ||
188 | slli a3, a0, 4 # number of frames to save in bits 8..4 | |
189 | extui a2, a2, 0, 4 # mask for the first 16 registers | |
190 | or a2, a3, a2 | |
191 | s32i a2, a1, PT_WMASK # needed when we restore the reg-file | |
192 | ||
193 | /* Save 4 registers at a time */ | |
194 | ||
195 | 1: rotw -1 | |
196 | s32i a0, a5, PT_AREG_END - 16 | |
197 | s32i a1, a5, PT_AREG_END - 12 | |
198 | s32i a2, a5, PT_AREG_END - 8 | |
199 | s32i a3, a5, PT_AREG_END - 4 | |
200 | addi a0, a4, -1 | |
201 | addi a1, a5, -16 | |
202 | _bnez a0, 1b | |
203 | ||
204 | /* WINDOWBASE still in SAR! */ | |
205 | ||
206 | rsr a2, SAR # original WINDOWBASE | |
207 | movi a3, 1 | |
208 | ssl a2 | |
209 | sll a3, a3 | |
210 | wsr a3, WINDOWSTART # set corresponding WINDOWSTART bit | |
211 | wsr a2, WINDOWBASE # and WINDOWSTART | |
212 | rsync | |
213 | ||
214 | /* We are back to the original stack pointer (a1) */ | |
215 | ||
216 | 2: | |
217 | #if XCHAL_EXTRA_SA_SIZE | |
218 | ||
219 | /* For user exceptions, save the extra state into the user's TCB. | |
220 | * Note: We must assume that xchal_extra_store_funcbody destroys a2..a15 | |
221 | */ | |
222 | ||
223 | GET_CURRENT(a2,a1) | |
224 | addi a2, a2, THREAD_CP_SAVE | |
225 | xchal_extra_store_funcbody | |
226 | #endif | |
227 | ||
228 | /* Now, jump to the common exception handler. */ | |
229 | ||
230 | j common_exception | |
231 | ||
232 | ||
233 | /* | |
234 | * First-level exit handler for kernel exceptions | |
235 | * Save special registers and the live window frame. | |
236 | * Note: Even though we changes the stack pointer, we don't have to do a | |
237 | * MOVSP here, as we do that when we return from the exception. | |
238 | * (See comment in the kernel exception exit code) | |
239 | * | |
240 | * Entry condition for kernel_exception: | |
241 | * | |
242 | * a0: trashed, original value saved on stack (PT_AREG0) | |
243 | * a1: a1 | |
244 | * a2: new stack pointer, original in DEPC | |
245 | * a3: dispatch table | |
246 | * depc: a2, original value saved on stack (PT_DEPC) | |
247 | * excsave_1: a3 | |
248 | * | |
249 | * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC | |
250 | * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception | |
251 | * | |
252 | * Entry condition for _kernel_exception: | |
253 | * | |
254 | * a0-a3 and depc have been saved to PT_AREG0...PT_AREG3 and PT_DEPC | |
255 | * excsave has been restored, and | |
256 | * stack pointer (a1) has been set. | |
257 | * | |
258 | * Note: _kernel_exception might be at an odd adress. Don't use call0..call12 | |
259 | */ | |
260 | ||
261 | ENTRY(kernel_exception) | |
262 | ||
263 | /* Save a0, a2, a3, DEPC and set SP. */ | |
264 | ||
265 | xsr a3, EXCSAVE_1 # restore a3, excsave_1 | |
266 | rsr a0, DEPC # get a2 | |
267 | s32i a1, a2, PT_AREG1 | |
268 | s32i a0, a2, PT_AREG2 | |
269 | s32i a3, a2, PT_AREG3 | |
270 | mov a1, a2 | |
271 | ||
272 | .globl _kernel_exception | |
273 | _kernel_exception: | |
274 | ||
275 | /* Save SAR and turn off single stepping */ | |
276 | ||
277 | movi a2, 0 | |
278 | rsr a3, SAR | |
29c4dfd9 | 279 | xsr a2, ICOUNTLEVEL |
5a0015d6 | 280 | s32i a3, a1, PT_SAR |
29c4dfd9 | 281 | s32i a2, a1, PT_ICOUNTLEVEL |
5a0015d6 CZ |
282 | |
283 | /* Rotate ws so that the current windowbase is at bit0. */ | |
284 | /* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */ | |
285 | ||
286 | rsr a2, WINDOWBASE # don't need to save these, we only | |
287 | rsr a3, WINDOWSTART # need shifted windowstart: windowmask | |
288 | ssr a2 | |
289 | slli a2, a3, 32-WSBITS | |
290 | src a2, a3, a2 | |
291 | srli a2, a2, 32-WSBITS | |
292 | s32i a2, a1, PT_WMASK # needed for kernel_exception_exit | |
293 | ||
294 | /* Save only the live window-frame */ | |
295 | ||
296 | _bbsi.l a2, 1, 1f | |
297 | s32i a4, a1, PT_AREG4 | |
298 | s32i a5, a1, PT_AREG5 | |
299 | s32i a6, a1, PT_AREG6 | |
300 | s32i a7, a1, PT_AREG7 | |
301 | _bbsi.l a2, 2, 1f | |
302 | s32i a8, a1, PT_AREG8 | |
303 | s32i a9, a1, PT_AREG9 | |
304 | s32i a10, a1, PT_AREG10 | |
305 | s32i a11, a1, PT_AREG11 | |
306 | _bbsi.l a2, 3, 1f | |
307 | s32i a12, a1, PT_AREG12 | |
308 | s32i a13, a1, PT_AREG13 | |
309 | s32i a14, a1, PT_AREG14 | |
310 | s32i a15, a1, PT_AREG15 | |
311 | ||
312 | 1: | |
313 | ||
314 | #ifdef KERNEL_STACK_OVERFLOW_CHECK | |
315 | ||
316 | /* Stack overflow check, for debugging */ | |
317 | extui a2, a1, TASK_SIZE_BITS,XX | |
318 | movi a3, SIZE?? | |
319 | _bge a2, a3, out_of_stack_panic | |
320 | ||
321 | #endif | |
322 | ||
323 | /* | |
324 | * This is the common exception handler. | |
325 | * We get here from the user exception handler or simply by falling through | |
326 | * from the kernel exception handler. | |
327 | * Save the remaining special registers, switch to kernel mode, and jump | |
328 | * to the second-level exception handler. | |
329 | * | |
330 | */ | |
331 | ||
332 | common_exception: | |
333 | ||
29c4dfd9 | 334 | /* Save some registers, disable loops and clear the syscall flag. */ |
5a0015d6 CZ |
335 | |
336 | rsr a2, DEBUGCAUSE | |
337 | rsr a3, EPC_1 | |
338 | s32i a2, a1, PT_DEBUGCAUSE | |
339 | s32i a3, a1, PT_PC | |
340 | ||
29c4dfd9 | 341 | movi a2, -1 |
5a0015d6 | 342 | rsr a3, EXCVADDR |
29c4dfd9 | 343 | s32i a2, a1, PT_SYSCALL |
5a0015d6 CZ |
344 | movi a2, 0 |
345 | s32i a3, a1, PT_EXCVADDR | |
346 | xsr a2, LCOUNT | |
347 | s32i a2, a1, PT_LCOUNT | |
348 | ||
349 | /* It is now save to restore the EXC_TABLE_FIXUP variable. */ | |
350 | ||
351 | rsr a0, EXCCAUSE | |
352 | movi a3, 0 | |
353 | rsr a2, EXCSAVE_1 | |
354 | s32i a0, a1, PT_EXCCAUSE | |
355 | s32i a3, a2, EXC_TABLE_FIXUP | |
356 | ||
357 | /* All unrecoverable states are saved on stack, now, and a1 is valid, | |
358 | * so we can allow exceptions and interrupts (*) again. | |
359 | * Set PS(EXCM = 0, UM = 0, RING = 0, OWB = 0, WOE = 1, INTLEVEL = X) | |
360 | * | |
361 | * (*) We only allow interrupts if PS.INTLEVEL was not set to 1 before | |
362 | * (interrupts disabled) and if this exception is not an interrupt. | |
363 | */ | |
364 | ||
365 | rsr a3, PS | |
366 | addi a0, a0, -4 | |
367 | movi a2, 1 | |
368 | extui a3, a3, 0, 1 # a3 = PS.INTLEVEL[0] | |
369 | moveqz a3, a2, a0 # a3 = 1 iff interrupt exception | |
173d6681 | 370 | movi a2, 1 << PS_WOE_BIT |
5a0015d6 CZ |
371 | or a3, a3, a2 |
372 | rsr a0, EXCCAUSE | |
373 | xsr a3, PS | |
374 | ||
375 | s32i a3, a1, PT_PS # save ps | |
376 | ||
377 | /* Save LBEG, LEND */ | |
378 | ||
379 | rsr a2, LBEG | |
380 | rsr a3, LEND | |
381 | s32i a2, a1, PT_LBEG | |
382 | s32i a3, a1, PT_LEND | |
383 | ||
384 | /* Go to second-level dispatcher. Set up parameters to pass to the | |
385 | * exception handler and call the exception handler. | |
386 | */ | |
387 | ||
388 | movi a4, exc_table | |
389 | mov a6, a1 # pass stack frame | |
390 | mov a7, a0 # pass EXCCAUSE | |
391 | addx4 a4, a0, a4 | |
392 | l32i a4, a4, EXC_TABLE_DEFAULT # load handler | |
393 | ||
394 | /* Call the second-level handler */ | |
395 | ||
396 | callx4 a4 | |
397 | ||
398 | /* Jump here for exception exit */ | |
399 | ||
400 | common_exception_return: | |
401 | ||
402 | /* Jump if we are returning from kernel exceptions. */ | |
403 | ||
404 | 1: l32i a3, a1, PT_PS | |
173d6681 | 405 | _bbsi.l a3, PS_UM_BIT, 2f |
5a0015d6 CZ |
406 | j kernel_exception_exit |
407 | ||
408 | /* Specific to a user exception exit: | |
409 | * We need to check some flags for signal handling and rescheduling, | |
410 | * and have to restore WB and WS, extra states, and all registers | |
411 | * in the register file that were in use in the user task. | |
412 | */ | |
413 | ||
414 | 2: wsr a3, PS /* disable interrupts */ | |
415 | ||
416 | /* Check for signals (keep interrupts disabled while we read TI_FLAGS) | |
417 | * Note: PS.INTLEVEL = 0, PS.EXCM = 1 | |
418 | */ | |
419 | ||
420 | GET_THREAD_INFO(a2,a1) | |
421 | l32i a4, a2, TI_FLAGS | |
422 | ||
423 | /* Enable interrupts again. | |
424 | * Note: When we get here, we certainly have handled any interrupts. | |
425 | * (Hint: There is only one user exception frame on stack) | |
426 | */ | |
427 | ||
173d6681 | 428 | movi a3, 1 << PS_WOE_BIT |
5a0015d6 CZ |
429 | |
430 | _bbsi.l a4, TIF_NEED_RESCHED, 3f | |
431 | _bbci.l a4, TIF_SIGPENDING, 4f | |
432 | ||
5a0015d6 CZ |
433 | l32i a4, a1, PT_DEPC |
434 | bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 4f | |
5a0015d6 CZ |
435 | /* Reenable interrupts and call do_signal() */ |
436 | ||
437 | wsr a3, PS | |
438 | movi a4, do_signal # int do_signal(struct pt_regs*, sigset_t*) | |
439 | mov a6, a1 | |
440 | movi a7, 0 | |
441 | callx4 a4 | |
442 | j 1b | |
443 | ||
444 | 3: /* Reenable interrupts and reschedule */ | |
445 | ||
446 | wsr a3, PS | |
447 | movi a4, schedule # void schedule (void) | |
448 | callx4 a4 | |
449 | j 1b | |
450 | ||
451 | /* Restore the state of the task and return from the exception. */ | |
452 | ||
5a0015d6 CZ |
453 | 4: /* a2 holds GET_CURRENT(a2,a1) */ |
454 | ||
5a0015d6 CZ |
455 | #if XCHAL_EXTRA_SA_SIZE |
456 | ||
457 | /* For user exceptions, restore the extra state from the user's TCB. */ | |
458 | ||
459 | /* Note: a2 still contains GET_CURRENT(a2,a1) */ | |
460 | addi a2, a2, THREAD_CP_SAVE | |
461 | xchal_extra_load_funcbody | |
462 | ||
463 | /* We must assume that xchal_extra_store_funcbody destroys | |
464 | * registers a2..a15. FIXME, this list can eventually be | |
465 | * reduced once real register requirements of the macro are | |
466 | * finalized. */ | |
467 | ||
468 | #endif /* XCHAL_EXTRA_SA_SIZE */ | |
469 | ||
470 | ||
471 | /* Switch to the user thread WINDOWBASE. Save SP temporarily in DEPC */ | |
472 | ||
473 | l32i a2, a1, PT_WINDOWBASE | |
474 | l32i a3, a1, PT_WINDOWSTART | |
475 | wsr a1, DEPC # use DEPC as temp storage | |
476 | wsr a3, WINDOWSTART # restore WINDOWSTART | |
477 | ssr a2 # preserve user's WB in the SAR | |
478 | wsr a2, WINDOWBASE # switch to user's saved WB | |
479 | rsync | |
480 | rsr a1, DEPC # restore stack pointer | |
481 | l32i a2, a1, PT_WMASK # register frames saved (in bits 4...9) | |
482 | rotw -1 # we restore a4..a7 | |
483 | _bltui a6, 16, 1f # only have to restore current window? | |
484 | ||
485 | /* The working registers are a0 and a3. We are restoring to | |
486 | * a4..a7. Be careful not to destroy what we have just restored. | |
487 | * Note: wmask has the format YYYYM: | |
488 | * Y: number of registers saved in groups of 4 | |
489 | * M: 4 bit mask of first 16 registers | |
490 | */ | |
491 | ||
492 | mov a2, a6 | |
493 | mov a3, a5 | |
494 | ||
495 | 2: rotw -1 # a0..a3 become a4..a7 | |
496 | addi a3, a7, -4*4 # next iteration | |
497 | addi a2, a6, -16 # decrementing Y in WMASK | |
498 | l32i a4, a3, PT_AREG_END + 0 | |
499 | l32i a5, a3, PT_AREG_END + 4 | |
500 | l32i a6, a3, PT_AREG_END + 8 | |
501 | l32i a7, a3, PT_AREG_END + 12 | |
502 | _bgeui a2, 16, 2b | |
503 | ||
504 | /* Clear unrestored registers (don't leak anything to user-land */ | |
505 | ||
506 | 1: rsr a0, WINDOWBASE | |
507 | rsr a3, SAR | |
508 | sub a3, a0, a3 | |
509 | beqz a3, 2f | |
510 | extui a3, a3, 0, WBBITS | |
511 | ||
512 | 1: rotw -1 | |
513 | addi a3, a7, -1 | |
514 | movi a4, 0 | |
515 | movi a5, 0 | |
516 | movi a6, 0 | |
517 | movi a7, 0 | |
518 | bgei a3, 1, 1b | |
519 | ||
520 | /* We are back were we were when we started. | |
521 | * Note: a2 still contains WMASK (if we've returned to the original | |
522 | * frame where we had loaded a2), or at least the lower 4 bits | |
523 | * (if we have restored WSBITS-1 frames). | |
524 | */ | |
525 | ||
526 | 2: j common_exception_exit | |
527 | ||
528 | /* This is the kernel exception exit. | |
529 | * We avoided to do a MOVSP when we entered the exception, but we | |
530 | * have to do it here. | |
531 | */ | |
532 | ||
533 | kernel_exception_exit: | |
534 | ||
535 | /* Disable interrupts (a3 holds PT_PS) */ | |
536 | ||
537 | wsr a3, PS | |
538 | ||
539 | #ifdef PREEMPTIBLE_KERNEL | |
540 | ||
541 | #ifdef CONFIG_PREEMPT | |
542 | ||
543 | /* | |
544 | * Note: We've just returned from a call4, so we have | |
545 | * at least 4 addt'l regs. | |
546 | */ | |
547 | ||
548 | /* Check current_thread_info->preempt_count */ | |
549 | ||
550 | GET_THREAD_INFO(a2) | |
551 | l32i a3, a2, TI_PREEMPT | |
552 | bnez a3, 1f | |
553 | ||
554 | l32i a2, a2, TI_FLAGS | |
555 | ||
556 | 1: | |
557 | ||
558 | #endif | |
559 | ||
560 | #endif | |
561 | ||
562 | /* Check if we have to do a movsp. | |
563 | * | |
564 | * We only have to do a movsp if the previous window-frame has | |
565 | * been spilled to the *temporary* exception stack instead of the | |
566 | * task's stack. This is the case if the corresponding bit in | |
567 | * WINDOWSTART for the previous window-frame was set before | |
568 | * (not spilled) but is zero now (spilled). | |
569 | * If this bit is zero, all other bits except the one for the | |
570 | * current window frame are also zero. So, we can use a simple test: | |
571 | * 'and' WINDOWSTART and WINDOWSTART-1: | |
572 | * | |
573 | * (XXXXXX1[0]* - 1) AND XXXXXX1[0]* = XXXXXX0[0]* | |
574 | * | |
575 | * The result is zero only if one bit was set. | |
576 | * | |
577 | * (Note: We might have gone through several task switches before | |
578 | * we come back to the current task, so WINDOWBASE might be | |
579 | * different from the time the exception occurred.) | |
580 | */ | |
581 | ||
582 | /* Test WINDOWSTART before and after the exception. | |
583 | * We actually have WMASK, so we only have to test if it is 1 or not. | |
584 | */ | |
585 | ||
586 | l32i a2, a1, PT_WMASK | |
587 | _beqi a2, 1, common_exception_exit # Spilled before exception,jump | |
588 | ||
589 | /* Test WINDOWSTART now. If spilled, do the movsp */ | |
590 | ||
591 | rsr a3, WINDOWSTART | |
592 | addi a0, a3, -1 | |
593 | and a3, a3, a0 | |
594 | _bnez a3, common_exception_exit | |
595 | ||
596 | /* Do a movsp (we returned from a call4, so we have at least a0..a7) */ | |
597 | ||
598 | addi a0, a1, -16 | |
599 | l32i a3, a0, 0 | |
600 | l32i a4, a0, 4 | |
601 | s32i a3, a1, PT_SIZE+0 | |
602 | s32i a4, a1, PT_SIZE+4 | |
603 | l32i a3, a0, 8 | |
604 | l32i a4, a0, 12 | |
605 | s32i a3, a1, PT_SIZE+8 | |
606 | s32i a4, a1, PT_SIZE+12 | |
607 | ||
608 | /* Common exception exit. | |
609 | * We restore the special register and the current window frame, and | |
610 | * return from the exception. | |
611 | * | |
612 | * Note: We expect a2 to hold PT_WMASK | |
613 | */ | |
614 | ||
615 | common_exception_exit: | |
616 | ||
617 | _bbsi.l a2, 1, 1f | |
618 | l32i a4, a1, PT_AREG4 | |
619 | l32i a5, a1, PT_AREG5 | |
620 | l32i a6, a1, PT_AREG6 | |
621 | l32i a7, a1, PT_AREG7 | |
622 | _bbsi.l a2, 2, 1f | |
623 | l32i a8, a1, PT_AREG8 | |
624 | l32i a9, a1, PT_AREG9 | |
625 | l32i a10, a1, PT_AREG10 | |
626 | l32i a11, a1, PT_AREG11 | |
627 | _bbsi.l a2, 3, 1f | |
628 | l32i a12, a1, PT_AREG12 | |
629 | l32i a13, a1, PT_AREG13 | |
630 | l32i a14, a1, PT_AREG14 | |
631 | l32i a15, a1, PT_AREG15 | |
632 | ||
633 | /* Restore PC, SAR */ | |
634 | ||
635 | 1: l32i a2, a1, PT_PC | |
636 | l32i a3, a1, PT_SAR | |
637 | wsr a2, EPC_1 | |
638 | wsr a3, SAR | |
639 | ||
640 | /* Restore LBEG, LEND, LCOUNT */ | |
641 | ||
642 | l32i a2, a1, PT_LBEG | |
643 | l32i a3, a1, PT_LEND | |
644 | wsr a2, LBEG | |
645 | l32i a2, a1, PT_LCOUNT | |
646 | wsr a3, LEND | |
647 | wsr a2, LCOUNT | |
648 | ||
29c4dfd9 CZ |
649 | /* We control single stepping through the ICOUNTLEVEL register. */ |
650 | ||
651 | l32i a2, a1, PT_ICOUNTLEVEL | |
652 | movi a3, -2 | |
653 | wsr a2, ICOUNTLEVEL | |
654 | wsr a3, ICOUNT | |
655 | ||
5a0015d6 CZ |
656 | /* Check if it was double exception. */ |
657 | ||
658 | l32i a0, a1, PT_DEPC | |
659 | l32i a3, a1, PT_AREG3 | |
660 | l32i a2, a1, PT_AREG2 | |
661 | _bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f | |
662 | ||
663 | /* Restore a0...a3 and return */ | |
664 | ||
665 | l32i a0, a1, PT_AREG0 | |
666 | l32i a1, a1, PT_AREG1 | |
667 | rfe | |
668 | ||
669 | 1: wsr a0, DEPC | |
670 | l32i a0, a1, PT_AREG0 | |
671 | l32i a1, a1, PT_AREG1 | |
672 | rfde | |
673 | ||
674 | /* | |
675 | * Debug exception handler. | |
676 | * | |
677 | * Currently, we don't support KGDB, so only user application can be debugged. | |
678 | * | |
679 | * When we get here, a0 is trashed and saved to excsave[debuglevel] | |
680 | */ | |
681 | ||
682 | ENTRY(debug_exception) | |
683 | ||
684 | rsr a0, EPS + XCHAL_DEBUGLEVEL | |
173d6681 | 685 | bbsi.l a0, PS_EXCM_BIT, 1f # exception mode |
5a0015d6 CZ |
686 | |
687 | /* Set EPC_1 and EXCCAUSE */ | |
688 | ||
689 | wsr a2, DEPC # save a2 temporarily | |
690 | rsr a2, EPC + XCHAL_DEBUGLEVEL | |
691 | wsr a2, EPC_1 | |
692 | ||
693 | movi a2, EXCCAUSE_MAPPED_DEBUG | |
694 | wsr a2, EXCCAUSE | |
695 | ||
696 | /* Restore PS to the value before the debug exc but with PS.EXCM set.*/ | |
697 | ||
173d6681 | 698 | movi a2, 1 << PS_EXCM_BIT |
5a0015d6 CZ |
699 | or a2, a0, a2 |
700 | movi a0, debug_exception # restore a3, debug jump vector | |
701 | wsr a2, PS | |
702 | xsr a0, EXCSAVE + XCHAL_DEBUGLEVEL | |
703 | ||
704 | /* Switch to kernel/user stack, restore jump vector, and save a0 */ | |
705 | ||
173d6681 | 706 | bbsi.l a2, PS_UM_BIT, 2f # jump if user mode |
5a0015d6 CZ |
707 | |
708 | addi a2, a1, -16-PT_SIZE # assume kernel stack | |
709 | s32i a0, a2, PT_AREG0 | |
710 | movi a0, 0 | |
711 | s32i a1, a2, PT_AREG1 | |
712 | s32i a0, a2, PT_DEPC # mark it as a regular exception | |
713 | xsr a0, DEPC | |
714 | s32i a3, a2, PT_AREG3 | |
715 | s32i a0, a2, PT_AREG2 | |
716 | mov a1, a2 | |
717 | j _kernel_exception | |
718 | ||
719 | 2: rsr a2, EXCSAVE_1 | |
720 | l32i a2, a2, EXC_TABLE_KSTK # load kernel stack pointer | |
721 | s32i a0, a2, PT_AREG0 | |
722 | movi a0, 0 | |
723 | s32i a1, a2, PT_AREG1 | |
724 | s32i a0, a2, PT_DEPC | |
725 | xsr a0, DEPC | |
726 | s32i a3, a2, PT_AREG3 | |
727 | s32i a0, a2, PT_AREG2 | |
728 | mov a1, a2 | |
729 | j _user_exception | |
730 | ||
731 | /* Debug exception while in exception mode. */ | |
732 | 1: j 1b // FIXME!! | |
733 | ||
734 | ||
735 | /* | |
736 | * We get here in case of an unrecoverable exception. | |
737 | * The only thing we can do is to be nice and print a panic message. | |
738 | * We only produce a single stack frame for panic, so ??? | |
739 | * | |
740 | * | |
741 | * Entry conditions: | |
742 | * | |
743 | * - a0 contains the caller address; original value saved in excsave1. | |
744 | * - the original a0 contains a valid return address (backtrace) or 0. | |
745 | * - a2 contains a valid stackpointer | |
746 | * | |
747 | * Notes: | |
748 | * | |
749 | * - If the stack pointer could be invalid, the caller has to setup a | |
750 | * dummy stack pointer (e.g. the stack of the init_task) | |
751 | * | |
752 | * - If the return address could be invalid, the caller has to set it | |
753 | * to 0, so the backtrace would stop. | |
754 | * | |
755 | */ | |
756 | .align 4 | |
757 | unrecoverable_text: | |
758 | .ascii "Unrecoverable error in exception handler\0" | |
759 | ||
760 | ENTRY(unrecoverable_exception) | |
761 | ||
762 | movi a0, 1 | |
763 | movi a1, 0 | |
764 | ||
765 | wsr a0, WINDOWSTART | |
766 | wsr a1, WINDOWBASE | |
767 | rsync | |
768 | ||
173d6681 | 769 | movi a1, (1 << PS_WOE_BIT) | 1 |
5a0015d6 CZ |
770 | wsr a1, PS |
771 | rsync | |
772 | ||
773 | movi a1, init_task | |
774 | movi a0, 0 | |
775 | addi a1, a1, PT_REGS_OFFSET | |
776 | ||
777 | movi a4, panic | |
778 | movi a6, unrecoverable_text | |
779 | ||
780 | callx4 a4 | |
781 | ||
782 | 1: j 1b | |
783 | ||
784 | ||
785 | /* -------------------------- FAST EXCEPTION HANDLERS ----------------------- */ | |
786 | ||
787 | /* | |
788 | * Fast-handler for alloca exceptions | |
789 | * | |
790 | * The ALLOCA handler is entered when user code executes the MOVSP | |
791 | * instruction and the caller's frame is not in the register file. | |
792 | * In this case, the caller frame's a0..a3 are on the stack just | |
793 | * below sp (a1), and this handler moves them. | |
794 | * | |
795 | * For "MOVSP <ar>,<as>" without destination register a1, this routine | |
796 | * simply moves the value from <as> to <ar> without moving the save area. | |
797 | * | |
798 | * Entry condition: | |
799 | * | |
800 | * a0: trashed, original value saved on stack (PT_AREG0) | |
801 | * a1: a1 | |
802 | * a2: new stack pointer, original in DEPC | |
803 | * a3: dispatch table | |
804 | * depc: a2, original value saved on stack (PT_DEPC) | |
805 | * excsave_1: a3 | |
806 | * | |
807 | * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC | |
808 | * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception | |
809 | */ | |
810 | ||
811 | #if XCHAL_HAVE_BE | |
812 | #define _EXTUI_MOVSP_SRC(ar) extui ar, ar, 4, 4 | |
813 | #define _EXTUI_MOVSP_DST(ar) extui ar, ar, 0, 4 | |
814 | #else | |
815 | #define _EXTUI_MOVSP_SRC(ar) extui ar, ar, 0, 4 | |
816 | #define _EXTUI_MOVSP_DST(ar) extui ar, ar, 4, 4 | |
817 | #endif | |
818 | ||
819 | ENTRY(fast_alloca) | |
820 | ||
821 | /* We shouldn't be in a double exception. */ | |
822 | ||
823 | l32i a0, a2, PT_DEPC | |
824 | _bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, .Lunhandled_double | |
825 | ||
826 | rsr a0, DEPC # get a2 | |
827 | s32i a4, a2, PT_AREG4 # save a4 and | |
828 | s32i a0, a2, PT_AREG2 # a2 to stack | |
829 | ||
830 | /* Exit critical section. */ | |
831 | ||
832 | movi a0, 0 | |
833 | s32i a0, a3, EXC_TABLE_FIXUP | |
834 | ||
835 | /* Restore a3, excsave_1 */ | |
836 | ||
837 | xsr a3, EXCSAVE_1 # make sure excsave_1 is valid for dbl. | |
838 | rsr a4, EPC_1 # get exception address | |
839 | s32i a3, a2, PT_AREG3 # save a3 to stack | |
840 | ||
841 | #ifdef ALLOCA_EXCEPTION_IN_IRAM | |
842 | #error iram not supported | |
843 | #else | |
844 | /* Note: l8ui not allowed in IRAM/IROM!! */ | |
845 | l8ui a0, a4, 1 # read as(src) from MOVSP instruction | |
846 | #endif | |
847 | movi a3, .Lmovsp_src | |
848 | _EXTUI_MOVSP_SRC(a0) # extract source register number | |
849 | addx8 a3, a0, a3 | |
850 | jx a3 | |
851 | ||
852 | .Lunhandled_double: | |
853 | wsr a0, EXCSAVE_1 | |
854 | movi a0, unrecoverable_exception | |
855 | callx0 a0 | |
856 | ||
857 | .align 8 | |
858 | .Lmovsp_src: | |
859 | l32i a3, a2, PT_AREG0; _j 1f; .align 8 | |
860 | mov a3, a1; _j 1f; .align 8 | |
861 | l32i a3, a2, PT_AREG2; _j 1f; .align 8 | |
862 | l32i a3, a2, PT_AREG3; _j 1f; .align 8 | |
863 | l32i a3, a2, PT_AREG4; _j 1f; .align 8 | |
864 | mov a3, a5; _j 1f; .align 8 | |
865 | mov a3, a6; _j 1f; .align 8 | |
866 | mov a3, a7; _j 1f; .align 8 | |
867 | mov a3, a8; _j 1f; .align 8 | |
868 | mov a3, a9; _j 1f; .align 8 | |
869 | mov a3, a10; _j 1f; .align 8 | |
870 | mov a3, a11; _j 1f; .align 8 | |
871 | mov a3, a12; _j 1f; .align 8 | |
872 | mov a3, a13; _j 1f; .align 8 | |
873 | mov a3, a14; _j 1f; .align 8 | |
874 | mov a3, a15; _j 1f; .align 8 | |
875 | ||
876 | 1: | |
877 | ||
878 | #ifdef ALLOCA_EXCEPTION_IN_IRAM | |
879 | #error iram not supported | |
880 | #else | |
881 | l8ui a0, a4, 0 # read ar(dst) from MOVSP instruction | |
882 | #endif | |
883 | addi a4, a4, 3 # step over movsp | |
884 | _EXTUI_MOVSP_DST(a0) # extract destination register | |
885 | wsr a4, EPC_1 # save new epc_1 | |
886 | ||
887 | _bnei a0, 1, 1f # no 'movsp a1, ax': jump | |
888 | ||
889 | /* Move the save area. This implies the use of the L32E | |
890 | * and S32E instructions, because this move must be done with | |
891 | * the user's PS.RING privilege levels, not with ring 0 | |
892 | * (kernel's) privileges currently active with PS.EXCM | |
893 | * set. Note that we have stil registered a fixup routine with the | |
894 | * double exception vector in case a double exception occurs. | |
895 | */ | |
896 | ||
897 | /* a0,a4:avail a1:old user stack a2:exc. stack a3:new user stack. */ | |
898 | ||
899 | l32e a0, a1, -16 | |
900 | l32e a4, a1, -12 | |
901 | s32e a0, a3, -16 | |
902 | s32e a4, a3, -12 | |
903 | l32e a0, a1, -8 | |
904 | l32e a4, a1, -4 | |
905 | s32e a0, a3, -8 | |
906 | s32e a4, a3, -4 | |
907 | ||
908 | /* Restore stack-pointer and all the other saved registers. */ | |
909 | ||
910 | mov a1, a3 | |
911 | ||
912 | l32i a4, a2, PT_AREG4 | |
913 | l32i a3, a2, PT_AREG3 | |
914 | l32i a0, a2, PT_AREG0 | |
915 | l32i a2, a2, PT_AREG2 | |
916 | rfe | |
917 | ||
918 | /* MOVSP <at>,<as> was invoked with <at> != a1. | |
919 | * Because the stack pointer is not being modified, | |
920 | * we should be able to just modify the pointer | |
921 | * without moving any save area. | |
922 | * The processor only traps these occurrences if the | |
923 | * caller window isn't live, so unfortunately we can't | |
924 | * use this as an alternate trap mechanism. | |
925 | * So we just do the move. This requires that we | |
926 | * resolve the destination register, not just the source, | |
927 | * so there's some extra work. | |
928 | * (PERHAPS NOT REALLY NEEDED, BUT CLEANER...) | |
929 | */ | |
930 | ||
931 | /* a0 dst-reg, a1 user-stack, a2 stack, a3 value of src reg. */ | |
932 | ||
933 | 1: movi a4, .Lmovsp_dst | |
934 | addx8 a4, a0, a4 | |
935 | jx a4 | |
936 | ||
937 | .align 8 | |
938 | .Lmovsp_dst: | |
939 | s32i a3, a2, PT_AREG0; _j 1f; .align 8 | |
940 | mov a1, a3; _j 1f; .align 8 | |
941 | s32i a3, a2, PT_AREG2; _j 1f; .align 8 | |
942 | s32i a3, a2, PT_AREG3; _j 1f; .align 8 | |
943 | s32i a3, a2, PT_AREG4; _j 1f; .align 8 | |
944 | mov a5, a3; _j 1f; .align 8 | |
945 | mov a6, a3; _j 1f; .align 8 | |
946 | mov a7, a3; _j 1f; .align 8 | |
947 | mov a8, a3; _j 1f; .align 8 | |
948 | mov a9, a3; _j 1f; .align 8 | |
949 | mov a10, a3; _j 1f; .align 8 | |
950 | mov a11, a3; _j 1f; .align 8 | |
951 | mov a12, a3; _j 1f; .align 8 | |
952 | mov a13, a3; _j 1f; .align 8 | |
953 | mov a14, a3; _j 1f; .align 8 | |
954 | mov a15, a3; _j 1f; .align 8 | |
955 | ||
956 | 1: l32i a4, a2, PT_AREG4 | |
957 | l32i a3, a2, PT_AREG3 | |
958 | l32i a0, a2, PT_AREG0 | |
959 | l32i a2, a2, PT_AREG2 | |
960 | rfe | |
961 | ||
962 | ||
963 | /* | |
964 | * fast system calls. | |
965 | * | |
966 | * WARNING: The kernel doesn't save the entire user context before | |
967 | * handling a fast system call. These functions are small and short, | |
968 | * usually offering some functionality not available to user tasks. | |
969 | * | |
970 | * BE CAREFUL TO PRESERVE THE USER'S CONTEXT. | |
971 | * | |
972 | * Entry condition: | |
973 | * | |
974 | * a0: trashed, original value saved on stack (PT_AREG0) | |
975 | * a1: a1 | |
976 | * a2: new stack pointer, original in DEPC | |
977 | * a3: dispatch table | |
978 | * depc: a2, original value saved on stack (PT_DEPC) | |
979 | * excsave_1: a3 | |
980 | */ | |
981 | ||
982 | ENTRY(fast_syscall_kernel) | |
983 | ||
984 | /* Skip syscall. */ | |
985 | ||
986 | rsr a0, EPC_1 | |
987 | addi a0, a0, 3 | |
988 | wsr a0, EPC_1 | |
989 | ||
990 | l32i a0, a2, PT_DEPC | |
991 | bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, fast_syscall_unrecoverable | |
992 | ||
993 | rsr a0, DEPC # get syscall-nr | |
994 | _beqz a0, fast_syscall_spill_registers | |
fc4fb2ad | 995 | _beqi a0, __NR_xtensa, fast_syscall_xtensa |
5a0015d6 CZ |
996 | |
997 | j kernel_exception | |
998 | ||
5a0015d6 CZ |
999 | ENTRY(fast_syscall_user) |
1000 | ||
1001 | /* Skip syscall. */ | |
1002 | ||
1003 | rsr a0, EPC_1 | |
1004 | addi a0, a0, 3 | |
1005 | wsr a0, EPC_1 | |
1006 | ||
1007 | l32i a0, a2, PT_DEPC | |
1008 | bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, fast_syscall_unrecoverable | |
1009 | ||
1010 | rsr a0, DEPC # get syscall-nr | |
1011 | _beqz a0, fast_syscall_spill_registers | |
fc4fb2ad | 1012 | _beqi a0, __NR_xtensa, fast_syscall_xtensa |
5a0015d6 CZ |
1013 | |
1014 | j user_exception | |
1015 | ||
1016 | ENTRY(fast_syscall_unrecoverable) | |
1017 | ||
1018 | /* Restore all states. */ | |
1019 | ||
1020 | l32i a0, a2, PT_AREG0 # restore a0 | |
1021 | xsr a2, DEPC # restore a2, depc | |
1022 | rsr a3, EXCSAVE_1 | |
1023 | ||
1024 | wsr a0, EXCSAVE_1 | |
1025 | movi a0, unrecoverable_exception | |
1026 | callx0 a0 | |
1027 | ||
1028 | ||
1029 | ||
1030 | /* | |
1031 | * sysxtensa syscall handler | |
1032 | * | |
fc4fb2ad CZ |
1033 | * int sysxtensa (SYS_XTENSA_ATOMIC_SET, ptr, val, unused); |
1034 | * int sysxtensa (SYS_XTENSA_ATOMIC_ADD, ptr, val, unused); | |
1035 | * int sysxtensa (SYS_XTENSA_ATOMIC_EXG_ADD, ptr, val, unused); | |
1036 | * int sysxtensa (SYS_XTENSA_ATOMIC_CMP_SWP, ptr, oldval, newval); | |
1037 | * a2 a6 a3 a4 a5 | |
5a0015d6 CZ |
1038 | * |
1039 | * Entry condition: | |
1040 | * | |
fc4fb2ad | 1041 | * a0: a2 (syscall-nr), original value saved on stack (PT_AREG0) |
5a0015d6 | 1042 | * a1: a1 |
fc4fb2ad CZ |
1043 | * a2: new stack pointer, original in a0 and DEPC |
1044 | * a3: dispatch table, original in excsave_1 | |
1045 | * a4..a15: unchanged | |
5a0015d6 CZ |
1046 | * depc: a2, original value saved on stack (PT_DEPC) |
1047 | * excsave_1: a3 | |
1048 | * | |
1049 | * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC | |
1050 | * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception | |
1051 | * | |
1052 | * Note: we don't have to save a2; a2 holds the return value | |
1053 | * | |
1054 | * We use the two macros TRY and CATCH: | |
1055 | * | |
1056 | * TRY adds an entry to the __ex_table fixup table for the immediately | |
1057 | * following instruction. | |
1058 | * | |
1059 | * CATCH catches any exception that occurred at one of the preceeding TRY | |
1060 | * statements and continues from there | |
1061 | * | |
1062 | * Usage TRY l32i a0, a1, 0 | |
1063 | * <other code> | |
1064 | * done: rfe | |
1065 | * CATCH <set return code> | |
1066 | * j done | |
1067 | */ | |
1068 | ||
1069 | #define TRY \ | |
1070 | .section __ex_table, "a"; \ | |
1071 | .word 66f, 67f; \ | |
1072 | .text; \ | |
1073 | 66: | |
1074 | ||
1075 | #define CATCH \ | |
1076 | 67: | |
1077 | ||
fc4fb2ad | 1078 | ENTRY(fast_syscall_xtensa) |
5a0015d6 | 1079 | |
fc4fb2ad | 1080 | xsr a3, EXCSAVE_1 # restore a3, excsave1 |
5a0015d6 | 1081 | |
fc4fb2ad | 1082 | s32i a7, a2, PT_AREG7 # we need an additional register |
5a0015d6 | 1083 | movi a7, 4 # sizeof(unsigned int) |
fc4fb2ad | 1084 | access_ok a3, a7, a0, a2, .Leac # a0: scratch reg, a2: sp |
5a0015d6 | 1085 | |
fc4fb2ad CZ |
1086 | addi a6, a6, -1 # assuming SYS_XTENSA_ATOMIC_SET = 1 |
1087 | _bgeui a6, SYS_XTENSA_COUNT - 1, .Lill | |
1088 | _bnei a6, SYS_XTENSA_ATOMIC_CMP_SWP - 1, .Lnswp | |
5a0015d6 | 1089 | |
fc4fb2ad | 1090 | /* Fall through for ATOMIC_CMP_SWP. */ |
5a0015d6 CZ |
1091 | |
1092 | .Lswp: /* Atomic compare and swap */ | |
1093 | ||
fc4fb2ad CZ |
1094 | TRY l32i a0, a3, 0 # read old value |
1095 | bne a0, a4, 1f # same as old value? jump | |
1096 | TRY s32i a5, a3, 0 # different, modify value | |
1097 | l32i a7, a2, PT_AREG7 # restore a7 | |
1098 | l32i a0, a2, PT_AREG0 # restore a0 | |
1099 | movi a2, 1 # and return 1 | |
1100 | addi a6, a6, 1 # restore a6 (really necessary?) | |
1101 | rfe | |
5a0015d6 | 1102 | |
fc4fb2ad CZ |
1103 | 1: l32i a7, a2, PT_AREG7 # restore a7 |
1104 | l32i a0, a2, PT_AREG0 # restore a0 | |
1105 | movi a2, 0 # return 0 (note that we cannot set | |
1106 | addi a6, a6, 1 # restore a6 (really necessary?) | |
1107 | rfe | |
5a0015d6 | 1108 | |
fc4fb2ad | 1109 | .Lnswp: /* Atomic set, add, and exg_add. */ |
5a0015d6 | 1110 | |
fc4fb2ad CZ |
1111 | TRY l32i a7, a3, 0 # orig |
1112 | add a0, a4, a7 # + arg | |
1113 | moveqz a0, a4, a6 # set | |
1114 | TRY s32i a0, a3, 0 # write new value | |
5a0015d6 | 1115 | |
fc4fb2ad | 1116 | mov a0, a2 |
5a0015d6 | 1117 | mov a2, a7 |
fc4fb2ad CZ |
1118 | l32i a7, a0, PT_AREG7 # restore a7 |
1119 | l32i a0, a0, PT_AREG0 # restore a0 | |
1120 | addi a6, a6, 1 # restore a6 (really necessary?) | |
5a0015d6 CZ |
1121 | rfe |
1122 | ||
1123 | CATCH | |
fc4fb2ad CZ |
1124 | .Leac: l32i a7, a2, PT_AREG7 # restore a7 |
1125 | l32i a0, a2, PT_AREG0 # restore a0 | |
1126 | movi a2, -EFAULT | |
1127 | rfe | |
1128 | ||
1129 | .Lill: l32i a7, a2, PT_AREG0 # restore a7 | |
1130 | l32i a0, a2, PT_AREG0 # restore a0 | |
1131 | movi a2, -EINVAL | |
1132 | rfe | |
1133 | ||
5a0015d6 CZ |
1134 | |
1135 | ||
1136 | ||
1137 | /* fast_syscall_spill_registers. | |
1138 | * | |
1139 | * Entry condition: | |
1140 | * | |
1141 | * a0: trashed, original value saved on stack (PT_AREG0) | |
1142 | * a1: a1 | |
1143 | * a2: new stack pointer, original in DEPC | |
1144 | * a3: dispatch table | |
1145 | * depc: a2, original value saved on stack (PT_DEPC) | |
1146 | * excsave_1: a3 | |
1147 | * | |
1148 | * Note: We assume the stack pointer is EXC_TABLE_KSTK in the fixup handler. | |
1149 | * Note: We don't need to save a2 in depc (return value) | |
1150 | */ | |
1151 | ||
1152 | ENTRY(fast_syscall_spill_registers) | |
1153 | ||
1154 | /* Register a FIXUP handler (pass current wb as a parameter) */ | |
1155 | ||
1156 | movi a0, fast_syscall_spill_registers_fixup | |
1157 | s32i a0, a3, EXC_TABLE_FIXUP | |
1158 | rsr a0, WINDOWBASE | |
1159 | s32i a0, a3, EXC_TABLE_PARAM | |
1160 | ||
1161 | /* Save a3 and SAR on stack. */ | |
1162 | ||
1163 | rsr a0, SAR | |
1164 | xsr a3, EXCSAVE_1 # restore a3 and excsave_1 | |
1165 | s32i a0, a2, PT_AREG4 # store SAR to PT_AREG4 | |
1166 | s32i a3, a2, PT_AREG3 | |
1167 | ||
1168 | /* The spill routine might clobber a7, a11, and a15. */ | |
1169 | ||
1170 | s32i a7, a2, PT_AREG5 | |
1171 | s32i a11, a2, PT_AREG6 | |
1172 | s32i a15, a2, PT_AREG7 | |
1173 | ||
1174 | call0 _spill_registers # destroys a3, DEPC, and SAR | |
1175 | ||
1176 | /* Advance PC, restore registers and SAR, and return from exception. */ | |
1177 | ||
1178 | l32i a3, a2, PT_AREG4 | |
1179 | l32i a0, a2, PT_AREG0 | |
1180 | wsr a3, SAR | |
1181 | l32i a3, a2, PT_AREG3 | |
1182 | ||
1183 | /* Restore clobbered registers. */ | |
1184 | ||
1185 | l32i a7, a2, PT_AREG5 | |
1186 | l32i a11, a2, PT_AREG6 | |
1187 | l32i a15, a2, PT_AREG7 | |
1188 | ||
1189 | movi a2, 0 | |
1190 | rfe | |
1191 | ||
1192 | /* Fixup handler. | |
1193 | * | |
1194 | * We get here if the spill routine causes an exception, e.g. tlb miss. | |
1195 | * We basically restore WINDOWBASE and WINDOWSTART to the condition when | |
1196 | * we entered the spill routine and jump to the user exception handler. | |
1197 | * | |
1198 | * a0: value of depc, original value in depc | |
1199 | * a2: trashed, original value in EXC_TABLE_DOUBLE_SAVE | |
1200 | * a3: exctable, original value in excsave1 | |
1201 | */ | |
1202 | ||
1203 | fast_syscall_spill_registers_fixup: | |
1204 | ||
1205 | rsr a2, WINDOWBASE # get current windowbase (a2 is saved) | |
1206 | xsr a0, DEPC # restore depc and a0 | |
1207 | ssl a2 # set shift (32 - WB) | |
1208 | ||
1209 | /* We need to make sure the current registers (a0-a3) are preserved. | |
1210 | * To do this, we simply set the bit for the current window frame | |
1211 | * in WS, so that the exception handlers save them to the task stack. | |
1212 | */ | |
1213 | ||
1214 | rsr a3, EXCSAVE_1 # get spill-mask | |
1215 | slli a2, a3, 1 # shift left by one | |
1216 | ||
1217 | slli a3, a2, 32-WSBITS | |
1218 | src a2, a2, a3 # a1 = xxwww1yyxxxwww1yy...... | |
1219 | wsr a2, WINDOWSTART # set corrected windowstart | |
1220 | ||
1221 | movi a3, exc_table | |
1222 | l32i a2, a3, EXC_TABLE_DOUBLE_SAVE # restore a2 | |
1223 | l32i a3, a3, EXC_TABLE_PARAM # original WB (in user task) | |
1224 | ||
1225 | /* Return to the original (user task) WINDOWBASE. | |
1226 | * We leave the following frame behind: | |
1227 | * a0, a1, a2 same | |
1228 | * a3: trashed (saved in excsave_1) | |
1229 | * depc: depc (we have to return to that address) | |
1230 | * excsave_1: a3 | |
1231 | */ | |
1232 | ||
1233 | wsr a3, WINDOWBASE | |
1234 | rsync | |
1235 | ||
1236 | /* We are now in the original frame when we entered _spill_registers: | |
1237 | * a0: return address | |
1238 | * a1: used, stack pointer | |
1239 | * a2: kernel stack pointer | |
1240 | * a3: available, saved in EXCSAVE_1 | |
1241 | * depc: exception address | |
1242 | * excsave: a3 | |
1243 | * Note: This frame might be the same as above. | |
1244 | */ | |
1245 | ||
5a0015d6 CZ |
1246 | /* Setup stack pointer. */ |
1247 | ||
1248 | addi a2, a2, -PT_USER_SIZE | |
1249 | s32i a0, a2, PT_AREG0 | |
1250 | ||
1251 | /* Make sure we return to this fixup handler. */ | |
1252 | ||
1253 | movi a3, fast_syscall_spill_registers_fixup_return | |
1254 | s32i a3, a2, PT_DEPC # setup depc | |
1255 | ||
1256 | /* Jump to the exception handler. */ | |
1257 | ||
1258 | movi a3, exc_table | |
1259 | rsr a0, EXCCAUSE | |
1260 | addx4 a0, a0, a3 # find entry in table | |
1261 | l32i a0, a0, EXC_TABLE_FAST_USER # load handler | |
1262 | jx a0 | |
1263 | ||
1264 | fast_syscall_spill_registers_fixup_return: | |
1265 | ||
1266 | /* When we return here, all registers have been restored (a2: DEPC) */ | |
1267 | ||
1268 | wsr a2, DEPC # exception address | |
1269 | ||
1270 | /* Restore fixup handler. */ | |
1271 | ||
1272 | xsr a3, EXCSAVE_1 | |
1273 | movi a2, fast_syscall_spill_registers_fixup | |
1274 | s32i a2, a3, EXC_TABLE_FIXUP | |
1275 | rsr a2, WINDOWBASE | |
1276 | s32i a2, a3, EXC_TABLE_PARAM | |
1277 | l32i a2, a3, EXC_TABLE_KSTK | |
1278 | ||
5a0015d6 CZ |
1279 | /* Load WB at the time the exception occurred. */ |
1280 | ||
1281 | rsr a3, SAR # WB is still in SAR | |
1282 | neg a3, a3 | |
1283 | wsr a3, WINDOWBASE | |
1284 | rsync | |
1285 | ||
1286 | /* Restore a3 and return. */ | |
1287 | ||
1288 | movi a3, exc_table | |
1289 | xsr a3, EXCSAVE_1 | |
1290 | ||
1291 | rfde | |
1292 | ||
1293 | ||
1294 | /* | |
1295 | * spill all registers. | |
1296 | * | |
1297 | * This is not a real function. The following conditions must be met: | |
1298 | * | |
1299 | * - must be called with call0. | |
1300 | * - uses DEPC, a3 and SAR. | |
1301 | * - the last 'valid' register of each frame are clobbered. | |
1302 | * - the caller must have registered a fixup handler | |
1303 | * (or be inside a critical section) | |
1304 | * - PS_EXCM must be set (PS_WOE cleared?) | |
1305 | */ | |
1306 | ||
1307 | ENTRY(_spill_registers) | |
1308 | ||
1309 | /* | |
1310 | * Rotate ws so that the current windowbase is at bit 0. | |
1311 | * Assume ws = xxxwww1yy (www1 current window frame). | |
1312 | * Rotate ws right so that a2 = yyxxxwww1. | |
1313 | */ | |
1314 | ||
1315 | wsr a2, DEPC # preserve a2 | |
1316 | rsr a2, WINDOWBASE | |
ea0b6b06 | 1317 | rsr a3, WINDOWSTART # a3 = xxxwww1yy |
5a0015d6 CZ |
1318 | ssr a2 # holds WB |
1319 | slli a2, a3, WSBITS | |
ea0b6b06 CZ |
1320 | or a3, a3, a2 # a3 = xxxwww1yyxxxwww1yy |
1321 | srl a3, a3 # a3 = 00xxxwww1yyxxxwww1 | |
5a0015d6 CZ |
1322 | |
1323 | /* We are done if there are no more than the current register frame. */ | |
1324 | ||
50c0716a | 1325 | extui a3, a3, 1, WSBITS-1 # a3 = 0yyxxxwww |
5a0015d6 CZ |
1326 | movi a2, (1 << (WSBITS-1)) |
1327 | _beqz a3, .Lnospill # only one active frame? jump | |
1328 | ||
1329 | /* We want 1 at the top, so that we return to the current windowbase */ | |
1330 | ||
1331 | or a3, a3, a2 # 1yyxxxwww | |
1332 | ||
1333 | /* Skip empty frames - get 'oldest' WINDOWSTART-bit. */ | |
1334 | ||
1335 | wsr a3, WINDOWSTART # save shifted windowstart | |
1336 | neg a2, a3 | |
1337 | and a3, a2, a3 # first bit set from right: 000010000 | |
1338 | ||
1339 | ffs_ws a2, a3 # a2: shifts to skip empty frames | |
1340 | movi a3, WSBITS | |
1341 | sub a2, a3, a2 # WSBITS-a2:number of 0-bits from right | |
1342 | ssr a2 # save in SAR for later. | |
1343 | ||
1344 | rsr a3, WINDOWBASE | |
1345 | add a3, a3, a2 | |
1346 | rsr a2, DEPC # restore a2 | |
1347 | wsr a3, WINDOWBASE | |
1348 | rsync | |
1349 | ||
1350 | rsr a3, WINDOWSTART | |
1351 | srl a3, a3 # shift windowstart | |
1352 | ||
1353 | /* WB is now just one frame below the oldest frame in the register | |
1354 | window. WS is shifted so the oldest frame is in bit 0, thus, WB | |
1355 | and WS differ by one 4-register frame. */ | |
1356 | ||
1357 | /* Save frames. Depending what call was used (call4, call8, call12), | |
1358 | * we have to save 4,8. or 12 registers. | |
1359 | */ | |
1360 | ||
1361 | _bbsi.l a3, 1, .Lc4 | |
1362 | _bbsi.l a3, 2, .Lc8 | |
1363 | ||
1364 | /* Special case: we have a call12-frame starting at a4. */ | |
1365 | ||
1366 | _bbci.l a3, 3, .Lc12 # bit 3 shouldn't be zero! (Jump to Lc12 first) | |
1367 | ||
1368 | s32e a4, a1, -16 # a1 is valid with an empty spill area | |
1369 | l32e a4, a5, -12 | |
1370 | s32e a8, a4, -48 | |
1371 | mov a8, a4 | |
1372 | l32e a4, a1, -16 | |
1373 | j .Lc12c | |
1374 | ||
50c0716a | 1375 | .Lnospill: |
ea0b6b06 CZ |
1376 | rsr a2, DEPC |
1377 | ret | |
50c0716a | 1378 | |
5a0015d6 CZ |
1379 | .Lloop: _bbsi.l a3, 1, .Lc4 |
1380 | _bbci.l a3, 2, .Lc12 | |
1381 | ||
1382 | .Lc8: s32e a4, a13, -16 | |
1383 | l32e a4, a5, -12 | |
1384 | s32e a8, a4, -32 | |
1385 | s32e a5, a13, -12 | |
1386 | s32e a6, a13, -8 | |
1387 | s32e a7, a13, -4 | |
1388 | s32e a9, a4, -28 | |
1389 | s32e a10, a4, -24 | |
1390 | s32e a11, a4, -20 | |
1391 | ||
1392 | srli a11, a3, 2 # shift windowbase by 2 | |
1393 | rotw 2 | |
1394 | _bnei a3, 1, .Lloop | |
1395 | ||
1396 | .Lexit: /* Done. Do the final rotation, set WS, and return. */ | |
1397 | ||
1398 | rotw 1 | |
1399 | rsr a3, WINDOWBASE | |
1400 | ssl a3 | |
1401 | movi a3, 1 | |
1402 | sll a3, a3 | |
1403 | wsr a3, WINDOWSTART | |
ea0b6b06 | 1404 | ret |
5a0015d6 CZ |
1405 | |
1406 | .Lc4: s32e a4, a9, -16 | |
1407 | s32e a5, a9, -12 | |
1408 | s32e a6, a9, -8 | |
1409 | s32e a7, a9, -4 | |
1410 | ||
1411 | srli a7, a3, 1 | |
1412 | rotw 1 | |
1413 | _bnei a3, 1, .Lloop | |
1414 | j .Lexit | |
1415 | ||
1416 | .Lc12: _bbci.l a3, 3, .Linvalid_mask # bit 2 shouldn't be zero! | |
1417 | ||
1418 | /* 12-register frame (call12) */ | |
1419 | ||
1420 | l32e a2, a5, -12 | |
1421 | s32e a8, a2, -48 | |
1422 | mov a8, a2 | |
1423 | ||
1424 | .Lc12c: s32e a9, a8, -44 | |
1425 | s32e a10, a8, -40 | |
1426 | s32e a11, a8, -36 | |
1427 | s32e a12, a8, -32 | |
1428 | s32e a13, a8, -28 | |
1429 | s32e a14, a8, -24 | |
1430 | s32e a15, a8, -20 | |
1431 | srli a15, a3, 3 | |
1432 | ||
1433 | /* The stack pointer for a4..a7 is out of reach, so we rotate the | |
1434 | * window, grab the stackpointer, and rotate back. | |
1435 | * Alternatively, we could also use the following approach, but that | |
1436 | * makes the fixup routine much more complicated: | |
1437 | * rotw 1 | |
1438 | * s32e a0, a13, -16 | |
1439 | * ... | |
1440 | * rotw 2 | |
1441 | */ | |
1442 | ||
1443 | rotw 1 | |
1444 | mov a5, a13 | |
1445 | rotw -1 | |
1446 | ||
1447 | s32e a4, a9, -16 | |
1448 | s32e a5, a9, -12 | |
1449 | s32e a6, a9, -8 | |
1450 | s32e a7, a9, -4 | |
1451 | ||
1452 | rotw 3 | |
1453 | ||
1454 | _beqi a3, 1, .Lexit | |
1455 | j .Lloop | |
1456 | ||
1457 | .Linvalid_mask: | |
1458 | ||
1459 | /* We get here because of an unrecoverable error in the window | |
1460 | * registers. If we are in user space, we kill the application, | |
1461 | * however, this condition is unrecoverable in kernel space. | |
1462 | */ | |
1463 | ||
1464 | rsr a0, PS | |
173d6681 | 1465 | _bbci.l a0, PS_UM_BIT, 1f |
5a0015d6 CZ |
1466 | |
1467 | /* User space: Setup a dummy frame and kill application. | |
1468 | * Note: We assume EXC_TABLE_KSTK contains a valid stack pointer. | |
1469 | */ | |
1470 | ||
1471 | movi a0, 1 | |
1472 | movi a1, 0 | |
1473 | ||
1474 | wsr a0, WINDOWSTART | |
1475 | wsr a1, WINDOWBASE | |
1476 | rsync | |
1477 | ||
1478 | movi a0, 0 | |
1479 | ||
1480 | movi a3, exc_table | |
1481 | l32i a1, a3, EXC_TABLE_KSTK | |
1482 | wsr a3, EXCSAVE_1 | |
1483 | ||
173d6681 | 1484 | movi a4, (1 << PS_WOE_BIT) | 1 |
5a0015d6 CZ |
1485 | wsr a4, PS |
1486 | rsync | |
1487 | ||
1488 | movi a6, SIGSEGV | |
1489 | movi a4, do_exit | |
1490 | callx4 a4 | |
1491 | ||
1492 | 1: /* Kernel space: PANIC! */ | |
1493 | ||
1494 | wsr a0, EXCSAVE_1 | |
1495 | movi a0, unrecoverable_exception | |
1496 | callx0 a0 # should not return | |
1497 | 1: j 1b | |
1498 | ||
1499 | /* | |
1500 | * We should never get here. Bail out! | |
1501 | */ | |
1502 | ||
1503 | ENTRY(fast_second_level_miss_double_kernel) | |
1504 | ||
1505 | 1: movi a0, unrecoverable_exception | |
1506 | callx0 a0 # should not return | |
1507 | 1: j 1b | |
1508 | ||
1509 | /* First-level entry handler for user, kernel, and double 2nd-level | |
1510 | * TLB miss exceptions. Note that for now, user and kernel miss | |
1511 | * exceptions share the same entry point and are handled identically. | |
1512 | * | |
1513 | * An old, less-efficient C version of this function used to exist. | |
1514 | * We include it below, interleaved as comments, for reference. | |
1515 | * | |
1516 | * Entry condition: | |
1517 | * | |
1518 | * a0: trashed, original value saved on stack (PT_AREG0) | |
1519 | * a1: a1 | |
1520 | * a2: new stack pointer, original in DEPC | |
1521 | * a3: dispatch table | |
1522 | * depc: a2, original value saved on stack (PT_DEPC) | |
1523 | * excsave_1: a3 | |
1524 | * | |
1525 | * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC | |
1526 | * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception | |
1527 | */ | |
1528 | ||
1529 | ENTRY(fast_second_level_miss) | |
1530 | ||
1531 | /* Save a1. Note: we don't expect a double exception. */ | |
1532 | ||
1533 | s32i a1, a2, PT_AREG1 | |
1534 | ||
1535 | /* We need to map the page of PTEs for the user task. Find | |
1536 | * the pointer to that page. Also, it's possible for tsk->mm | |
1537 | * to be NULL while tsk->active_mm is nonzero if we faulted on | |
1538 | * a vmalloc address. In that rare case, we must use | |
1539 | * active_mm instead to avoid a fault in this handler. See | |
1540 | * | |
1541 | * http://mail.nl.linux.org/linux-mm/2002-08/msg00258.html | |
1542 | * (or search Internet on "mm vs. active_mm") | |
1543 | * | |
1544 | * if (!mm) | |
1545 | * mm = tsk->active_mm; | |
1546 | * pgd = pgd_offset (mm, regs->excvaddr); | |
1547 | * pmd = pmd_offset (pgd, regs->excvaddr); | |
1548 | * pmdval = *pmd; | |
1549 | */ | |
1550 | ||
1551 | GET_CURRENT(a1,a2) | |
1552 | l32i a0, a1, TASK_MM # tsk->mm | |
1553 | beqz a0, 9f | |
1554 | ||
01858d1b CZ |
1555 | |
1556 | /* We deliberately destroy a3 that holds the exception table. */ | |
1557 | ||
1558 | 8: rsr a3, EXCVADDR # fault address | |
1559 | _PGD_OFFSET(a0, a3, a1) | |
5a0015d6 | 1560 | l32i a0, a0, 0 # read pmdval |
5a0015d6 CZ |
1561 | beqz a0, 2f |
1562 | ||
1563 | /* Read ptevaddr and convert to top of page-table page. | |
1564 | * | |
1565 | * vpnval = read_ptevaddr_register() & PAGE_MASK; | |
1566 | * vpnval += DTLB_WAY_PGTABLE; | |
1567 | * pteval = mk_pte (virt_to_page(pmd_val(pmdval)), PAGE_KERNEL); | |
1568 | * write_dtlb_entry (pteval, vpnval); | |
1569 | * | |
1570 | * The messy computation for 'pteval' above really simplifies | |
1571 | * into the following: | |
1572 | * | |
6656920b | 1573 | * pteval = ((pmdval - PAGE_OFFSET) & PAGE_MASK) | PAGE_DIRECTORY |
5a0015d6 CZ |
1574 | */ |
1575 | ||
1576 | movi a1, -PAGE_OFFSET | |
1577 | add a0, a0, a1 # pmdval - PAGE_OFFSET | |
1578 | extui a1, a0, 0, PAGE_SHIFT # ... & PAGE_MASK | |
1579 | xor a0, a0, a1 | |
1580 | ||
01858d1b | 1581 | movi a1, _PAGE_DIRECTORY |
5a0015d6 CZ |
1582 | or a0, a0, a1 # ... | PAGE_DIRECTORY |
1583 | ||
01858d1b | 1584 | /* |
6656920b | 1585 | * We utilize all three wired-ways (7-9) to hold pmd translations. |
01858d1b CZ |
1586 | * Memory regions are mapped to the DTLBs according to bits 28 and 29. |
1587 | * This allows to map the three most common regions to three different | |
1588 | * DTLBs: | |
1589 | * 0,1 -> way 7 program (0040.0000) and virtual (c000.0000) | |
1590 | * 2 -> way 8 shared libaries (2000.0000) | |
1591 | * 3 -> way 0 stack (3000.0000) | |
1592 | */ | |
1593 | ||
1594 | extui a3, a3, 28, 2 # addr. bit 28 and 29 0,1,2,3 | |
5a0015d6 | 1595 | rsr a1, PTEVADDR |
01858d1b | 1596 | addx2 a3, a3, a3 # -> 0,3,6,9 |
5a0015d6 | 1597 | srli a1, a1, PAGE_SHIFT |
01858d1b | 1598 | extui a3, a3, 2, 2 # -> 0,0,1,2 |
5a0015d6 | 1599 | slli a1, a1, PAGE_SHIFT # ptevaddr & PAGE_MASK |
01858d1b CZ |
1600 | addi a3, a3, DTLB_WAY_PGD |
1601 | add a1, a1, a3 # ... + way_number | |
5a0015d6 | 1602 | |
01858d1b | 1603 | 3: wdtlb a0, a1 |
5a0015d6 CZ |
1604 | dsync |
1605 | ||
1606 | /* Exit critical section. */ | |
1607 | ||
01858d1b | 1608 | 4: movi a3, exc_table # restore a3 |
5a0015d6 CZ |
1609 | movi a0, 0 |
1610 | s32i a0, a3, EXC_TABLE_FIXUP | |
1611 | ||
1612 | /* Restore the working registers, and return. */ | |
1613 | ||
1614 | l32i a0, a2, PT_AREG0 | |
1615 | l32i a1, a2, PT_AREG1 | |
1616 | l32i a2, a2, PT_DEPC | |
1617 | xsr a3, EXCSAVE_1 | |
1618 | ||
1619 | bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f | |
1620 | ||
1621 | /* Restore excsave1 and return. */ | |
1622 | ||
1623 | rsr a2, DEPC | |
1624 | rfe | |
1625 | ||
1626 | /* Return from double exception. */ | |
1627 | ||
1628 | 1: xsr a2, DEPC | |
1629 | esync | |
1630 | rfde | |
1631 | ||
1632 | 9: l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0 | |
1633 | j 8b | |
1634 | ||
6656920b CZ |
1635 | #if (DCACHE_WAY_SIZE > PAGE_SIZE) |
1636 | ||
1637 | 2: /* Special case for cache aliasing. | |
1638 | * We (should) only get here if a clear_user_page, copy_user_page | |
1639 | * or the aliased cache flush functions got preemptively interrupted | |
1640 | * by another task. Re-establish temporary mapping to the | |
1641 | * TLBTEMP_BASE areas. | |
1642 | */ | |
1643 | ||
1644 | /* We shouldn't be in a double exception */ | |
1645 | ||
1646 | l32i a0, a2, PT_DEPC | |
1647 | bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 2f | |
1648 | ||
1649 | /* Make sure the exception originated in the special functions */ | |
1650 | ||
1651 | movi a0, __tlbtemp_mapping_start | |
1652 | rsr a3, EPC_1 | |
1653 | bltu a3, a0, 2f | |
1654 | movi a0, __tlbtemp_mapping_end | |
1655 | bgeu a3, a0, 2f | |
1656 | ||
1657 | /* Check if excvaddr was in one of the TLBTEMP_BASE areas. */ | |
1658 | ||
1659 | movi a3, TLBTEMP_BASE_1 | |
1660 | rsr a0, EXCVADDR | |
1661 | bltu a0, a3, 2f | |
1662 | ||
1663 | addi a1, a0, -(2 << (DCACHE_ALIAS_ORDER + PAGE_SHIFT)) | |
1664 | bgeu a1, a3, 2f | |
1665 | ||
1666 | /* Check if we have to restore an ITLB mapping. */ | |
1667 | ||
1668 | movi a1, __tlbtemp_mapping_itlb | |
1669 | rsr a3, EPC_1 | |
1670 | sub a3, a3, a1 | |
1671 | ||
1672 | /* Calculate VPN */ | |
1673 | ||
1674 | movi a1, PAGE_MASK | |
1675 | and a1, a1, a0 | |
1676 | ||
1677 | /* Jump for ITLB entry */ | |
1678 | ||
1679 | bgez a3, 1f | |
1680 | ||
1681 | /* We can use up to two TLBTEMP areas, one for src and one for dst. */ | |
1682 | ||
1683 | extui a3, a0, PAGE_SHIFT + DCACHE_ALIAS_ORDER, 1 | |
1684 | add a1, a3, a1 | |
1685 | ||
1686 | /* PPN is in a6 for the first TLBTEMP area and in a7 for the second. */ | |
1687 | ||
1688 | mov a0, a6 | |
1689 | movnez a0, a7, a3 | |
1690 | j 3b | |
1691 | ||
1692 | /* ITLB entry. We only use dst in a6. */ | |
1693 | ||
1694 | 1: witlb a6, a1 | |
1695 | isync | |
1696 | j 4b | |
1697 | ||
1698 | ||
1699 | #endif // DCACHE_WAY_SIZE > PAGE_SIZE | |
1700 | ||
1701 | ||
5a0015d6 CZ |
1702 | 2: /* Invalid PGD, default exception handling */ |
1703 | ||
01858d1b | 1704 | movi a3, exc_table |
5a0015d6 CZ |
1705 | rsr a1, DEPC |
1706 | xsr a3, EXCSAVE_1 | |
1707 | s32i a1, a2, PT_AREG2 | |
1708 | s32i a3, a2, PT_AREG3 | |
1709 | mov a1, a2 | |
1710 | ||
1711 | rsr a2, PS | |
173d6681 | 1712 | bbsi.l a2, PS_UM_BIT, 1f |
5a0015d6 CZ |
1713 | j _kernel_exception |
1714 | 1: j _user_exception | |
1715 | ||
1716 | ||
1717 | /* | |
1718 | * StoreProhibitedException | |
1719 | * | |
1720 | * Update the pte and invalidate the itlb mapping for this pte. | |
1721 | * | |
1722 | * Entry condition: | |
1723 | * | |
1724 | * a0: trashed, original value saved on stack (PT_AREG0) | |
1725 | * a1: a1 | |
1726 | * a2: new stack pointer, original in DEPC | |
1727 | * a3: dispatch table | |
1728 | * depc: a2, original value saved on stack (PT_DEPC) | |
1729 | * excsave_1: a3 | |
1730 | * | |
1731 | * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC | |
1732 | * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception | |
1733 | */ | |
1734 | ||
1735 | ENTRY(fast_store_prohibited) | |
1736 | ||
1737 | /* Save a1 and a4. */ | |
1738 | ||
1739 | s32i a1, a2, PT_AREG1 | |
1740 | s32i a4, a2, PT_AREG4 | |
1741 | ||
1742 | GET_CURRENT(a1,a2) | |
1743 | l32i a0, a1, TASK_MM # tsk->mm | |
1744 | beqz a0, 9f | |
1745 | ||
1746 | 8: rsr a1, EXCVADDR # fault address | |
1747 | _PGD_OFFSET(a0, a1, a4) | |
1748 | l32i a0, a0, 0 | |
5a0015d6 CZ |
1749 | beqz a0, 2f |
1750 | ||
01858d1b CZ |
1751 | /* Note that we assume _PAGE_WRITABLE_BIT is only set if pte is valid.*/ |
1752 | ||
5a0015d6 CZ |
1753 | _PTE_OFFSET(a0, a1, a4) |
1754 | l32i a4, a0, 0 # read pteval | |
01858d1b | 1755 | bbci.l a4, _PAGE_WRITABLE_BIT, 2f |
5a0015d6 | 1756 | |
01858d1b | 1757 | movi a1, _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_HW_WRITE |
5a0015d6 CZ |
1758 | or a4, a4, a1 |
1759 | rsr a1, EXCVADDR | |
1760 | s32i a4, a0, 0 | |
1761 | ||
1762 | /* We need to flush the cache if we have page coloring. */ | |
1763 | #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK | |
1764 | dhwb a0, 0 | |
1765 | #endif | |
1766 | pdtlb a0, a1 | |
5a0015d6 | 1767 | wdtlb a4, a0 |
5a0015d6 CZ |
1768 | |
1769 | /* Exit critical section. */ | |
1770 | ||
1771 | movi a0, 0 | |
1772 | s32i a0, a3, EXC_TABLE_FIXUP | |
1773 | ||
1774 | /* Restore the working registers, and return. */ | |
1775 | ||
1776 | l32i a4, a2, PT_AREG4 | |
1777 | l32i a1, a2, PT_AREG1 | |
1778 | l32i a0, a2, PT_AREG0 | |
1779 | l32i a2, a2, PT_DEPC | |
1780 | ||
1781 | /* Restore excsave1 and a3. */ | |
1782 | ||
1783 | xsr a3, EXCSAVE_1 | |
1784 | bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f | |
1785 | ||
1786 | rsr a2, DEPC | |
1787 | rfe | |
1788 | ||
1789 | /* Double exception. Restore FIXUP handler and return. */ | |
1790 | ||
1791 | 1: xsr a2, DEPC | |
1792 | esync | |
1793 | rfde | |
1794 | ||
1795 | 9: l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0 | |
1796 | j 8b | |
1797 | ||
1798 | 2: /* If there was a problem, handle fault in C */ | |
1799 | ||
1800 | rsr a4, DEPC # still holds a2 | |
1801 | xsr a3, EXCSAVE_1 | |
1802 | s32i a4, a2, PT_AREG2 | |
1803 | s32i a3, a2, PT_AREG3 | |
1804 | l32i a4, a2, PT_AREG4 | |
1805 | mov a1, a2 | |
1806 | ||
1807 | rsr a2, PS | |
173d6681 | 1808 | bbsi.l a2, PS_UM_BIT, 1f |
5a0015d6 CZ |
1809 | j _kernel_exception |
1810 | 1: j _user_exception | |
1811 | ||
1812 | ||
1813 | #if XCHAL_EXTRA_SA_SIZE | |
1814 | ||
1815 | #warning fast_coprocessor untested | |
1816 | ||
1817 | /* | |
1818 | * Entry condition: | |
1819 | * | |
1820 | * a0: trashed, original value saved on stack (PT_AREG0) | |
1821 | * a1: a1 | |
1822 | * a2: new stack pointer, original in DEPC | |
1823 | * a3: dispatch table | |
1824 | * depc: a2, original value saved on stack (PT_DEPC) | |
1825 | * excsave_1: a3 | |
1826 | * | |
1827 | * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC | |
1828 | * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception | |
1829 | */ | |
1830 | ||
1831 | ENTRY(fast_coprocessor_double) | |
1832 | wsr a0, EXCSAVE_1 | |
1833 | movi a0, unrecoverable_exception | |
1834 | callx0 a0 | |
1835 | ||
1836 | ENTRY(fast_coprocessor) | |
1837 | ||
1838 | /* Fatal if we are in a double exception. */ | |
1839 | ||
1840 | l32i a0, a2, PT_DEPC | |
1841 | _bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, fast_coprocessor_double | |
1842 | ||
1843 | /* Save some registers a1, a3, a4, SAR */ | |
1844 | ||
1845 | xsr a3, EXCSAVE_1 | |
1846 | s32i a3, a2, PT_AREG3 | |
1847 | rsr a3, SAR | |
1848 | s32i a4, a2, PT_AREG4 | |
1849 | s32i a1, a2, PT_AREG1 | |
1850 | s32i a5, a1, PT_AREG5 | |
1851 | s32i a3, a2, PT_SAR | |
1852 | mov a1, a2 | |
1853 | ||
1854 | /* Currently, the HAL macros only guarantee saving a0 and a1. | |
1855 | * These can and will be refined in the future, but for now, | |
1856 | * just save the remaining registers of a2...a15. | |
1857 | */ | |
1858 | s32i a6, a1, PT_AREG6 | |
1859 | s32i a7, a1, PT_AREG7 | |
1860 | s32i a8, a1, PT_AREG8 | |
1861 | s32i a9, a1, PT_AREG9 | |
1862 | s32i a10, a1, PT_AREG10 | |
1863 | s32i a11, a1, PT_AREG11 | |
1864 | s32i a12, a1, PT_AREG12 | |
1865 | s32i a13, a1, PT_AREG13 | |
1866 | s32i a14, a1, PT_AREG14 | |
1867 | s32i a15, a1, PT_AREG15 | |
1868 | ||
1869 | /* Find coprocessor number. Subtract first CP EXCCAUSE from EXCCAUSE */ | |
1870 | ||
1871 | rsr a0, EXCCAUSE | |
1872 | addi a3, a0, -XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED | |
1873 | ||
1874 | /* Set corresponding CPENABLE bit */ | |
1875 | ||
1876 | movi a4, 1 | |
1877 | ssl a3 # SAR: 32 - coprocessor_number | |
1878 | rsr a5, CPENABLE | |
1879 | sll a4, a4 | |
1880 | or a4, a5, a4 | |
1881 | wsr a4, CPENABLE | |
1882 | rsync | |
1883 | movi a5, coprocessor_info # list of owner and offset into cp_save | |
1884 | addx8 a0, a4, a5 # entry for CP | |
1885 | ||
1886 | bne a4, a5, .Lload # bit wasn't set before, cp not in use | |
1887 | ||
1888 | /* Now compare the current task with the owner of the coprocessor. | |
1889 | * If they are the same, there is no reason to save or restore any | |
1890 | * coprocessor state. Having already enabled the coprocessor, | |
1891 | * branch ahead to return. | |
1892 | */ | |
1893 | GET_CURRENT(a5,a1) | |
1894 | l32i a4, a0, COPROCESSOR_INFO_OWNER # a4: current owner for this CP | |
1895 | beq a4, a5, .Ldone | |
1896 | ||
1897 | /* Find location to dump current coprocessor state: | |
1898 | * task_struct->task_cp_save_offset + coprocessor_offset[coprocessor] | |
1899 | * | |
1900 | * Note: a0 pointer to the entry in the coprocessor owner table, | |
1901 | * a3 coprocessor number, | |
1902 | * a4 current owner of coprocessor. | |
1903 | */ | |
1904 | l32i a5, a0, COPROCESSOR_INFO_OFFSET | |
1905 | addi a2, a4, THREAD_CP_SAVE | |
1906 | add a2, a2, a5 | |
1907 | ||
1908 | /* Store current coprocessor states. (a5 still has CP number) */ | |
1909 | ||
1910 | xchal_cpi_store_funcbody | |
1911 | ||
1912 | /* The macro might have destroyed a3 (coprocessor number), but | |
1913 | * SAR still has 32 - coprocessor_number! | |
1914 | */ | |
1915 | movi a3, 32 | |
1916 | rsr a4, SAR | |
1917 | sub a3, a3, a4 | |
1918 | ||
1919 | .Lload: /* A new task now owns the corpocessors. Save its TCB pointer into | |
1920 | * the coprocessor owner table. | |
1921 | * | |
1922 | * Note: a0 pointer to the entry in the coprocessor owner table, | |
1923 | * a3 coprocessor number. | |
1924 | */ | |
1925 | GET_CURRENT(a4,a1) | |
1926 | s32i a4, a0, 0 | |
1927 | ||
1928 | /* Find location from where to restore the current coprocessor state.*/ | |
1929 | ||
1930 | l32i a5, a0, COPROCESSOR_INFO_OFFSET | |
1931 | addi a2, a4, THREAD_CP_SAVE | |
1932 | add a2, a2, a4 | |
1933 | ||
1934 | xchal_cpi_load_funcbody | |
1935 | ||
1936 | /* We must assume that the xchal_cpi_store_funcbody macro destroyed | |
1937 | * registers a2..a15. | |
1938 | */ | |
1939 | ||
1940 | .Ldone: l32i a15, a1, PT_AREG15 | |
1941 | l32i a14, a1, PT_AREG14 | |
1942 | l32i a13, a1, PT_AREG13 | |
1943 | l32i a12, a1, PT_AREG12 | |
1944 | l32i a11, a1, PT_AREG11 | |
1945 | l32i a10, a1, PT_AREG10 | |
1946 | l32i a9, a1, PT_AREG9 | |
1947 | l32i a8, a1, PT_AREG8 | |
1948 | l32i a7, a1, PT_AREG7 | |
1949 | l32i a6, a1, PT_AREG6 | |
1950 | l32i a5, a1, PT_AREG5 | |
1951 | l32i a4, a1, PT_AREG4 | |
1952 | l32i a3, a1, PT_AREG3 | |
1953 | l32i a2, a1, PT_AREG2 | |
1954 | l32i a0, a1, PT_AREG0 | |
1955 | l32i a1, a1, PT_AREG1 | |
1956 | ||
1957 | rfe | |
1958 | ||
1959 | #endif /* XCHAL_EXTRA_SA_SIZE */ | |
1960 | ||
fc4fb2ad CZ |
1961 | /* |
1962 | * System Calls. | |
1963 | * | |
1964 | * void system_call (struct pt_regs* regs, int exccause) | |
1965 | * a2 a3 | |
1966 | */ | |
1967 | ||
1968 | ENTRY(system_call) | |
1969 | entry a1, 32 | |
1970 | ||
1971 | /* regs->syscall = regs->areg[2] */ | |
1972 | ||
1973 | l32i a3, a2, PT_AREG2 | |
1974 | mov a6, a2 | |
1975 | movi a4, do_syscall_trace_enter | |
1976 | s32i a3, a2, PT_SYSCALL | |
1977 | callx4 a4 | |
1978 | ||
1979 | /* syscall = sys_call_table[syscall_nr] */ | |
1980 | ||
1981 | movi a4, sys_call_table; | |
1982 | movi a5, __NR_syscall_count | |
1983 | movi a6, -ENOSYS | |
1984 | bgeu a3, a5, 1f | |
1985 | ||
1986 | addx4 a4, a3, a4 | |
1987 | l32i a4, a4, 0 | |
1988 | movi a5, sys_ni_syscall; | |
1989 | beq a4, a5, 1f | |
1990 | ||
1991 | /* Load args: arg0 - arg5 are passed via regs. */ | |
1992 | ||
1993 | l32i a6, a2, PT_AREG6 | |
1994 | l32i a7, a2, PT_AREG3 | |
1995 | l32i a8, a2, PT_AREG4 | |
1996 | l32i a9, a2, PT_AREG5 | |
1997 | l32i a10, a2, PT_AREG8 | |
1998 | l32i a11, a2, PT_AREG9 | |
1999 | ||
2000 | /* Pass one additional argument to the syscall: pt_regs (on stack) */ | |
2001 | s32i a2, a1, 0 | |
2002 | ||
2003 | callx4 a4 | |
2004 | ||
2005 | 1: /* regs->areg[2] = return_value */ | |
2006 | ||
2007 | s32i a6, a2, PT_AREG2 | |
2008 | movi a4, do_syscall_trace_leave | |
2009 | mov a6, a2 | |
2010 | callx4 a4 | |
2011 | retw | |
2012 | ||
2013 | ||
2014 | /* | |
2015 | * Create a kernel thread | |
2016 | * | |
2017 | * int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags) | |
2018 | * a2 a2 a3 a4 | |
2019 | */ | |
2020 | ||
2021 | ENTRY(kernel_thread) | |
2022 | entry a1, 16 | |
2023 | ||
2024 | mov a5, a2 # preserve fn over syscall | |
2025 | mov a7, a3 # preserve args over syscall | |
2026 | ||
2027 | movi a3, _CLONE_VM | _CLONE_UNTRACED | |
2028 | movi a2, __NR_clone | |
2029 | or a6, a4, a3 # arg0: flags | |
2030 | mov a3, a1 # arg1: sp | |
2031 | syscall | |
2032 | ||
2033 | beq a3, a1, 1f # branch if parent | |
2034 | mov a6, a7 # args | |
2035 | callx4 a5 # fn(args) | |
2036 | ||
2037 | movi a2, __NR_exit | |
2038 | syscall # return value of fn(args) still in a6 | |
2039 | ||
2040 | 1: retw | |
2041 | ||
2042 | /* | |
2043 | * Do a system call from kernel instead of calling sys_execve, so we end up | |
2044 | * with proper pt_regs. | |
2045 | * | |
2046 | * int kernel_execve(const char *fname, char *const argv[], charg *const envp[]) | |
2047 | * a2 a2 a3 a4 | |
2048 | */ | |
2049 | ||
2050 | ENTRY(kernel_execve) | |
2051 | entry a1, 16 | |
2052 | mov a6, a2 # arg0 is in a6 | |
2053 | movi a2, __NR_execve | |
2054 | syscall | |
2055 | ||
2056 | retw | |
2057 | ||
5a0015d6 CZ |
2058 | /* |
2059 | * Task switch. | |
2060 | * | |
2061 | * struct task* _switch_to (struct task* prev, struct task* next) | |
2062 | * a2 a2 a3 | |
2063 | */ | |
2064 | ||
2065 | ENTRY(_switch_to) | |
2066 | ||
2067 | entry a1, 16 | |
2068 | ||
2069 | mov a4, a3 # preserve a3 | |
2070 | ||
2071 | s32i a0, a2, THREAD_RA # save return address | |
2072 | s32i a1, a2, THREAD_SP # save stack pointer | |
2073 | ||
2074 | /* Disable ints while we manipulate the stack pointer; spill regs. */ | |
2075 | ||
173d6681 | 2076 | movi a5, (1 << PS_EXCM_BIT) | LOCKLEVEL |
5a0015d6 CZ |
2077 | xsr a5, PS |
2078 | rsr a3, EXCSAVE_1 | |
2079 | rsync | |
2080 | s32i a3, a3, EXC_TABLE_FIXUP /* enter critical section */ | |
2081 | ||
2082 | call0 _spill_registers | |
2083 | ||
2084 | /* Set kernel stack (and leave critical section) | |
2085 | * Note: It's save to set it here. The stack will not be overwritten | |
2086 | * because the kernel stack will only be loaded again after | |
2087 | * we return from kernel space. | |
2088 | */ | |
2089 | ||
2090 | l32i a0, a4, TASK_THREAD_INFO | |
2091 | rsr a3, EXCSAVE_1 # exc_table | |
2092 | movi a1, 0 | |
2093 | addi a0, a0, PT_REGS_OFFSET | |
2094 | s32i a1, a3, EXC_TABLE_FIXUP | |
2095 | s32i a0, a3, EXC_TABLE_KSTK | |
2096 | ||
2097 | /* restore context of the task that 'next' addresses */ | |
2098 | ||
2099 | l32i a0, a4, THREAD_RA /* restore return address */ | |
2100 | l32i a1, a4, THREAD_SP /* restore stack pointer */ | |
2101 | ||
2102 | wsr a5, PS | |
2103 | rsync | |
2104 | ||
2105 | retw | |
2106 | ||
2107 | ||
2108 | ENTRY(ret_from_fork) | |
2109 | ||
2110 | /* void schedule_tail (struct task_struct *prev) | |
2111 | * Note: prev is still in a6 (return value from fake call4 frame) | |
2112 | */ | |
2113 | movi a4, schedule_tail | |
2114 | callx4 a4 | |
2115 | ||
fc4fb2ad CZ |
2116 | movi a4, do_syscall_trace_leave |
2117 | mov a6, a1 | |
5a0015d6 CZ |
2118 | callx4 a4 |
2119 | ||
2120 | j common_exception_return | |
2121 |