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[deliverable/binutils-gdb.git] / bfd / coff-sh.c
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c2dcd04e 1/* BFD back-end for Renesas Super-H COFF binaries.
eea6121a 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
2b5c217d 3 2003, 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
252b5132
RH		 4 Contributed by Cygnus Support.
5 Written by Steve Chamberlain, <sac@cygnus.com>.
6 Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>.
7
c2dcd04e 8 This file is part of BFD, the Binary File Descriptor library.
252b5132 9
c2dcd04e
NC		 10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
cd123cb7 12 the Free Software Foundation; either version 3 of the License, or
c2dcd04e 13 (at your option) any later version.
252b5132 14
c2dcd04e
NC		 15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
252b5132 19
c2dcd04e
NC		 20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
cd123cb7
NC		 22 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
23 MA 02110-1301, USA. */
252b5132 24
252b5132 25#include "sysdep.h"
3db64b00 26#include "bfd.h"
993e9275 27#include "libiberty.h"
252b5132
RH		 28#include "libbfd.h"
29#include "bfdlink.h"
30#include "coff/sh.h"
31#include "coff/internal.h"
17505c5c
NC		 32
33#ifdef COFF_WITH_PE
34#include "coff/pe.h"
86033394
NC		 35
36#ifndef COFF_IMAGE_WITH_PE
b34976b6 37static bfd_boolean sh_align_load_span
86033394 38 PARAMS ((bfd *, asection *, bfd_byte *,
b34976b6
AM		 39 bfd_boolean (*) (bfd *, asection *, PTR, bfd_byte *, bfd_vma),
40 PTR, bfd_vma **, bfd_vma *, bfd_vma, bfd_vma, bfd_boolean *));
86033394
NC		 41
42#define _bfd_sh_align_load_span sh_align_load_span
43#endif
17505c5c
NC		 44#endif
45
2b5c217d
NC		 46#undef bfd_pe_print_pdata
47#define bfd_pe_print_pdata pe_print_ce_compressed_pdata
48extern bfd_boolean pe_print_ce_compressed_pdata (bfd *, void *);
49
252b5132
RH		 50#include "libcoff.h"
51
52/* Internal functions. */
53static bfd_reloc_status_type sh_reloc
54 PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
55static long get_symbol_value PARAMS ((asymbol *));
b34976b6
AM		 56static bfd_boolean sh_relax_section
57 PARAMS ((bfd *, asection *, struct bfd_link_info *, bfd_boolean *));
58static bfd_boolean sh_relax_delete_bytes
252b5132 59 PARAMS ((bfd *, asection *, bfd_vma, int));
86033394 60#ifndef COFF_IMAGE_WITH_PE
252b5132 61static const struct sh_opcode *sh_insn_info PARAMS ((unsigned int));
86033394 62#endif
b34976b6
AM		 63static bfd_boolean sh_align_loads
64 PARAMS ((bfd *, asection *, struct internal_reloc *, bfd_byte *,
65 bfd_boolean *));
66static bfd_boolean sh_swap_insns
252b5132 67 PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
b34976b6 68static bfd_boolean sh_relocate_section
252b5132
RH		 69 PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
70 struct internal_reloc *, struct internal_syment *, asection **));
71static bfd_byte *sh_coff_get_relocated_section_contents
72 PARAMS ((bfd *, struct bfd_link_info *, struct bfd_link_order *,
b34976b6 73 bfd_byte *, bfd_boolean, asymbol **));
f4ffd778 74static reloc_howto_type * sh_coff_reloc_type_lookup PARAMS ((bfd *, bfd_reloc_code_real_type));
252b5132 75
17505c5c
NC		 76#ifdef COFF_WITH_PE
77/* Can't build import tables with 2**4 alignment. */
78#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 2
79#else
252b5132 80/* Default section alignment to 2**4. */
17505c5c
NC		 81#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 4
82#endif
83
84#ifdef COFF_IMAGE_WITH_PE
85/* Align PE executables. */
86#define COFF_PAGE_SIZE 0x1000
87#endif
252b5132
RH		 88
89/* Generate long file names. */
90#define COFF_LONG_FILENAMES
91
17505c5c 92#ifdef COFF_WITH_PE
b34976b6
AM		 93static bfd_boolean in_reloc_p PARAMS ((bfd *, reloc_howto_type *));
94/* Return TRUE if this relocation should
17505c5c 95 appear in the output .reloc section. */
b34976b6 96static bfd_boolean in_reloc_p (abfd, howto)
17505c5c
NC		 97 bfd * abfd ATTRIBUTE_UNUSED;
98 reloc_howto_type * howto;
99{
100 return ! howto->pc_relative && howto->type != R_SH_IMAGEBASE;
cbfe05c4 101}
17505c5c
NC		 102#endif
103
252b5132
RH		 104/* The supported relocations. There are a lot of relocations defined
105 in coff/internal.h which we do not expect to ever see. */
106static reloc_howto_type sh_coff_howtos[] =
107{
5f771d47
ILT		 108 EMPTY_HOWTO (0),
109 EMPTY_HOWTO (1),
17505c5c
NC		 110#ifdef COFF_WITH_PE
111 /* Windows CE */
112 HOWTO (R_SH_IMM32CE, /* type */
113 0, /* rightshift */
114 2, /* size (0 = byte, 1 = short, 2 = long) */
115 32, /* bitsize */
b34976b6 116 FALSE, /* pc_relative */
17505c5c
NC		 117 0, /* bitpos */
118 complain_overflow_bitfield, /* complain_on_overflow */
119 sh_reloc, /* special_function */
120 "r_imm32ce", /* name */
b34976b6 121 TRUE, /* partial_inplace */
17505c5c
NC		 122 0xffffffff, /* src_mask */
123 0xffffffff, /* dst_mask */
b34976b6 124 FALSE), /* pcrel_offset */
17505c5c 125#else
5f771d47 126 EMPTY_HOWTO (2),
17505c5c 127#endif
5f771d47
ILT		 128 EMPTY_HOWTO (3), /* R_SH_PCREL8 */
129 EMPTY_HOWTO (4), /* R_SH_PCREL16 */
130 EMPTY_HOWTO (5), /* R_SH_HIGH8 */
131 EMPTY_HOWTO (6), /* R_SH_IMM24 */
132 EMPTY_HOWTO (7), /* R_SH_LOW16 */
133 EMPTY_HOWTO (8),
134 EMPTY_HOWTO (9), /* R_SH_PCDISP8BY4 */
252b5132
RH		 135
136 HOWTO (R_SH_PCDISP8BY2, /* type */
137 1, /* rightshift */
138 1, /* size (0 = byte, 1 = short, 2 = long) */
139 8, /* bitsize */
b34976b6 140 TRUE, /* pc_relative */
252b5132
RH		 141 0, /* bitpos */
142 complain_overflow_signed, /* complain_on_overflow */
143 sh_reloc, /* special_function */
144 "r_pcdisp8by2", /* name */
b34976b6 145 TRUE, /* partial_inplace */
252b5132
RH		 146 0xff, /* src_mask */
147 0xff, /* dst_mask */
b34976b6 148 TRUE), /* pcrel_offset */
252b5132 149
5f771d47 150 EMPTY_HOWTO (11), /* R_SH_PCDISP8 */
252b5132
RH		 151
152 HOWTO (R_SH_PCDISP, /* type */
153 1, /* rightshift */
154 1, /* size (0 = byte, 1 = short, 2 = long) */
155 12, /* bitsize */
b34976b6 156 TRUE, /* pc_relative */
252b5132
RH		 157 0, /* bitpos */
158 complain_overflow_signed, /* complain_on_overflow */
159 sh_reloc, /* special_function */
160 "r_pcdisp12by2", /* name */
b34976b6 161 TRUE, /* partial_inplace */
252b5132
RH		 162 0xfff, /* src_mask */
163 0xfff, /* dst_mask */
b34976b6 164 TRUE), /* pcrel_offset */
252b5132 165
5f771d47 166 EMPTY_HOWTO (13),
252b5132
RH		 167
168 HOWTO (R_SH_IMM32, /* type */
169 0, /* rightshift */
170 2, /* size (0 = byte, 1 = short, 2 = long) */
171 32, /* bitsize */
b34976b6 172 FALSE, /* pc_relative */
252b5132
RH		 173 0, /* bitpos */
174 complain_overflow_bitfield, /* complain_on_overflow */
175 sh_reloc, /* special_function */
176 "r_imm32", /* name */
b34976b6 177 TRUE, /* partial_inplace */
252b5132
RH		 178 0xffffffff, /* src_mask */
179 0xffffffff, /* dst_mask */
b34976b6 180 FALSE), /* pcrel_offset */
252b5132 181
5f771d47 182 EMPTY_HOWTO (15),
17505c5c 183#ifdef COFF_WITH_PE
cbfe05c4
KH		 184 HOWTO (R_SH_IMAGEBASE, /* type */
185 0, /* rightshift */
186 2, /* size (0 = byte, 1 = short, 2 = long) */
187 32, /* bitsize */
b34976b6 188 FALSE, /* pc_relative */
cbfe05c4 189 0, /* bitpos */
17505c5c 190 complain_overflow_bitfield, /* complain_on_overflow */
cbfe05c4
KH		 191 sh_reloc, /* special_function */
192 "rva32", /* name */
b34976b6 193 TRUE, /* partial_inplace */
cbfe05c4
KH		 194 0xffffffff, /* src_mask */
195 0xffffffff, /* dst_mask */
b34976b6 196 FALSE), /* pcrel_offset */
17505c5c 197#else
5f771d47 198 EMPTY_HOWTO (16), /* R_SH_IMM8 */
17505c5c 199#endif
5f771d47
ILT		 200 EMPTY_HOWTO (17), /* R_SH_IMM8BY2 */
201 EMPTY_HOWTO (18), /* R_SH_IMM8BY4 */
202 EMPTY_HOWTO (19), /* R_SH_IMM4 */
203 EMPTY_HOWTO (20), /* R_SH_IMM4BY2 */
204 EMPTY_HOWTO (21), /* R_SH_IMM4BY4 */
252b5132
RH		 205
206 HOWTO (R_SH_PCRELIMM8BY2, /* type */
207 1, /* rightshift */
208 1, /* size (0 = byte, 1 = short, 2 = long) */
209 8, /* bitsize */
b34976b6 210 TRUE, /* pc_relative */
252b5132
RH		 211 0, /* bitpos */
212 complain_overflow_unsigned, /* complain_on_overflow */
213 sh_reloc, /* special_function */
214 "r_pcrelimm8by2", /* name */
b34976b6 215 TRUE, /* partial_inplace */
252b5132
RH		 216 0xff, /* src_mask */
217 0xff, /* dst_mask */
b34976b6 218 TRUE), /* pcrel_offset */
252b5132
RH		 219
220 HOWTO (R_SH_PCRELIMM8BY4, /* type */
221 2, /* rightshift */
222 1, /* size (0 = byte, 1 = short, 2 = long) */
223 8, /* bitsize */
b34976b6 224 TRUE, /* pc_relative */
252b5132
RH		 225 0, /* bitpos */
226 complain_overflow_unsigned, /* complain_on_overflow */
227 sh_reloc, /* special_function */
228 "r_pcrelimm8by4", /* name */
b34976b6 229 TRUE, /* partial_inplace */
252b5132
RH		 230 0xff, /* src_mask */
231 0xff, /* dst_mask */
b34976b6 232 TRUE), /* pcrel_offset */
252b5132
RH		 233
234 HOWTO (R_SH_IMM16, /* type */
235 0, /* rightshift */
236 1, /* size (0 = byte, 1 = short, 2 = long) */
237 16, /* bitsize */
b34976b6 238 FALSE, /* pc_relative */
252b5132
RH		 239 0, /* bitpos */
240 complain_overflow_bitfield, /* complain_on_overflow */
241 sh_reloc, /* special_function */
242 "r_imm16", /* name */
b34976b6 243 TRUE, /* partial_inplace */
252b5132
RH		 244 0xffff, /* src_mask */
245 0xffff, /* dst_mask */
b34976b6 246 FALSE), /* pcrel_offset */
252b5132
RH		 247
248 HOWTO (R_SH_SWITCH16, /* type */
249 0, /* rightshift */
250 1, /* size (0 = byte, 1 = short, 2 = long) */
251 16, /* bitsize */
b34976b6 252 FALSE, /* pc_relative */
252b5132
RH		 253 0, /* bitpos */
254 complain_overflow_bitfield, /* complain_on_overflow */
255 sh_reloc, /* special_function */
256 "r_switch16", /* name */
b34976b6 257 TRUE, /* partial_inplace */
252b5132
RH		 258 0xffff, /* src_mask */
259 0xffff, /* dst_mask */
b34976b6 260 FALSE), /* pcrel_offset */
252b5132
RH		 261
262 HOWTO (R_SH_SWITCH32, /* type */
263 0, /* rightshift */
264 2, /* size (0 = byte, 1 = short, 2 = long) */
265 32, /* bitsize */
b34976b6 266 FALSE, /* pc_relative */
252b5132
RH		 267 0, /* bitpos */
268 complain_overflow_bitfield, /* complain_on_overflow */
269 sh_reloc, /* special_function */
270 "r_switch32", /* name */
b34976b6 271 TRUE, /* partial_inplace */
252b5132
RH		 272 0xffffffff, /* src_mask */
273 0xffffffff, /* dst_mask */
b34976b6 274 FALSE), /* pcrel_offset */
252b5132
RH		 275
276 HOWTO (R_SH_USES, /* type */
277 0, /* rightshift */
278 1, /* size (0 = byte, 1 = short, 2 = long) */
279 16, /* bitsize */
b34976b6 280 FALSE, /* pc_relative */
252b5132
RH		 281 0, /* bitpos */
282 complain_overflow_bitfield, /* complain_on_overflow */
283 sh_reloc, /* special_function */
284 "r_uses", /* name */
b34976b6 285 TRUE, /* partial_inplace */
252b5132
RH		 286 0xffff, /* src_mask */
287 0xffff, /* dst_mask */
b34976b6 288 FALSE), /* pcrel_offset */
252b5132
RH		 289
290 HOWTO (R_SH_COUNT, /* type */
291 0, /* rightshift */
292 2, /* size (0 = byte, 1 = short, 2 = long) */
293 32, /* bitsize */
b34976b6 294 FALSE, /* pc_relative */
252b5132
RH		 295 0, /* bitpos */
296 complain_overflow_bitfield, /* complain_on_overflow */
297 sh_reloc, /* special_function */
298 "r_count", /* name */
b34976b6 299 TRUE, /* partial_inplace */
252b5132
RH		 300 0xffffffff, /* src_mask */
301 0xffffffff, /* dst_mask */
b34976b6 302 FALSE), /* pcrel_offset */
252b5132
RH		 303
304 HOWTO (R_SH_ALIGN, /* type */
305 0, /* rightshift */
306 2, /* size (0 = byte, 1 = short, 2 = long) */
307 32, /* bitsize */
b34976b6 308 FALSE, /* pc_relative */
252b5132
RH		 309 0, /* bitpos */
310 complain_overflow_bitfield, /* complain_on_overflow */
311 sh_reloc, /* special_function */
312 "r_align", /* name */
b34976b6 313 TRUE, /* partial_inplace */
252b5132
RH		 314 0xffffffff, /* src_mask */
315 0xffffffff, /* dst_mask */
b34976b6 316 FALSE), /* pcrel_offset */
252b5132
RH		 317
318 HOWTO (R_SH_CODE, /* type */
319 0, /* rightshift */
320 2, /* size (0 = byte, 1 = short, 2 = long) */
321 32, /* bitsize */
b34976b6 322 FALSE, /* pc_relative */
252b5132
RH		 323 0, /* bitpos */
324 complain_overflow_bitfield, /* complain_on_overflow */
325 sh_reloc, /* special_function */
326 "r_code", /* name */
b34976b6 327 TRUE, /* partial_inplace */
252b5132
RH		 328 0xffffffff, /* src_mask */
329 0xffffffff, /* dst_mask */
b34976b6 330 FALSE), /* pcrel_offset */
252b5132
RH		 331
332 HOWTO (R_SH_DATA, /* type */
333 0, /* rightshift */
334 2, /* size (0 = byte, 1 = short, 2 = long) */
335 32, /* bitsize */
b34976b6 336 FALSE, /* pc_relative */
252b5132
RH		 337 0, /* bitpos */
338 complain_overflow_bitfield, /* complain_on_overflow */
339 sh_reloc, /* special_function */
340 "r_data", /* name */
b34976b6 341 TRUE, /* partial_inplace */
252b5132
RH		 342 0xffffffff, /* src_mask */
343 0xffffffff, /* dst_mask */
b34976b6 344 FALSE), /* pcrel_offset */
252b5132
RH		 345
346 HOWTO (R_SH_LABEL, /* type */
347 0, /* rightshift */
348 2, /* size (0 = byte, 1 = short, 2 = long) */
349 32, /* bitsize */
b34976b6 350 FALSE, /* pc_relative */
252b5132
RH		 351 0, /* bitpos */
352 complain_overflow_bitfield, /* complain_on_overflow */
353 sh_reloc, /* special_function */
354 "r_label", /* name */
b34976b6 355 TRUE, /* partial_inplace */
252b5132
RH		 356 0xffffffff, /* src_mask */
357 0xffffffff, /* dst_mask */
b34976b6 358 FALSE), /* pcrel_offset */
252b5132
RH		 359
360 HOWTO (R_SH_SWITCH8, /* type */
361 0, /* rightshift */
362 0, /* size (0 = byte, 1 = short, 2 = long) */
363 8, /* bitsize */
b34976b6 364 FALSE, /* pc_relative */
252b5132
RH		 365 0, /* bitpos */
366 complain_overflow_bitfield, /* complain_on_overflow */
367 sh_reloc, /* special_function */
368 "r_switch8", /* name */
b34976b6 369 TRUE, /* partial_inplace */
252b5132
RH		 370 0xff, /* src_mask */
371 0xff, /* dst_mask */
b34976b6 372 FALSE) /* pcrel_offset */
252b5132
RH		 373};
374
375#define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])
376
377/* Check for a bad magic number. */
378#define BADMAG(x) SHBADMAG(x)
379
380/* Customize coffcode.h (this is not currently used). */
381#define SH 1
382
383/* FIXME: This should not be set here. */
384#define __A_MAGIC_SET__
385
17505c5c 386#ifndef COFF_WITH_PE
252b5132 387/* Swap the r_offset field in and out. */
dc810e39
AM		 388#define SWAP_IN_RELOC_OFFSET H_GET_32
389#define SWAP_OUT_RELOC_OFFSET H_PUT_32
252b5132
RH		 390
391/* Swap out extra information in the reloc structure. */
392#define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \
393 do \
394 { \
395 dst->r_stuff[0] = 'S'; \
396 dst->r_stuff[1] = 'C'; \
397 } \
398 while (0)
17505c5c 399#endif
252b5132
RH		 400
401/* Get the value of a symbol, when performing a relocation. */
402
403static long
cbfe05c4 404get_symbol_value (symbol)
252b5132 405 asymbol *symbol;
cbfe05c4 406{
252b5132
RH		 407 bfd_vma relocation;
408
409 if (bfd_is_com_section (symbol->section))
cbfe05c4
KH		 410 relocation = 0;
411 else
252b5132
RH		 412 relocation = (symbol->value +
413 symbol->section->output_section->vma +
414 symbol->section->output_offset);
415
416 return relocation;
417}
418
17505c5c
NC		 419#ifdef COFF_WITH_PE
420/* Convert an rtype to howto for the COFF backend linker.
421 Copied from coff-i386. */
422#define coff_rtype_to_howto coff_sh_rtype_to_howto
f4ffd778 423static reloc_howto_type * coff_sh_rtype_to_howto PARAMS ((bfd *, asection *, struct internal_reloc *, struct coff_link_hash_entry *, struct internal_syment *, bfd_vma *));
17505c5c
NC		 424
425static reloc_howto_type *
426coff_sh_rtype_to_howto (abfd, sec, rel, h, sym, addendp)
86033394 427 bfd * abfd ATTRIBUTE_UNUSED;
17505c5c
NC		 428 asection * sec;
429 struct internal_reloc * rel;
430 struct coff_link_hash_entry * h;
431 struct internal_syment * sym;
432 bfd_vma * addendp;
433{
434 reloc_howto_type * howto;
435
436 howto = sh_coff_howtos + rel->r_type;
437
438 *addendp = 0;
439
440 if (howto->pc_relative)
441 *addendp += sec->vma;
442
443 if (sym != NULL && sym->n_scnum == 0 && sym->n_value != 0)
444 {
445 /* This is a common symbol. The section contents include the
446 size (sym->n_value) as an addend. The relocate_section
447 function will be adding in the final value of the symbol. We
448 need to subtract out the current size in order to get the
449 correct result. */
450 BFD_ASSERT (h != NULL);
451 }
452
453 if (howto->pc_relative)
454 {
455 *addendp -= 4;
456
457 /* If the symbol is defined, then the generic code is going to
458 add back the symbol value in order to cancel out an
459 adjustment it made to the addend. However, we set the addend
460 to 0 at the start of this function. We need to adjust here,
461 to avoid the adjustment the generic code will make. FIXME:
462 This is getting a bit hackish. */
463 if (sym != NULL && sym->n_scnum != 0)
464 *addendp -= sym->n_value;
465 }
466
467 if (rel->r_type == R_SH_IMAGEBASE)
468 *addendp -= pe_data (sec->output_section->owner)->pe_opthdr.ImageBase;
469
470 return howto;
471}
472
993e9275
NC		 473#endif /* COFF_WITH_PE */
474
17505c5c
NC		 475/* This structure is used to map BFD reloc codes to SH PE relocs. */
476struct shcoff_reloc_map
477{
aa066ac8 478 bfd_reloc_code_real_type bfd_reloc_val;
17505c5c
NC		 479 unsigned char shcoff_reloc_val;
480};
481
a9a32010 482#ifdef COFF_WITH_PE
17505c5c
NC		 483/* An array mapping BFD reloc codes to SH PE relocs. */
484static const struct shcoff_reloc_map sh_reloc_map[] =
485{
486 { BFD_RELOC_32, R_SH_IMM32CE },
487 { BFD_RELOC_RVA, R_SH_IMAGEBASE },
488 { BFD_RELOC_CTOR, R_SH_IMM32CE },
489};
a9a32010
DJ		 490#else
491/* An array mapping BFD reloc codes to SH PE relocs. */
492static const struct shcoff_reloc_map sh_reloc_map[] =
493{
494 { BFD_RELOC_32, R_SH_IMM32 },
495 { BFD_RELOC_CTOR, R_SH_IMM32 },
496};
497#endif
17505c5c
NC		 498
499/* Given a BFD reloc code, return the howto structure for the
500 corresponding SH PE reloc. */
501#define coff_bfd_reloc_type_lookup sh_coff_reloc_type_lookup
157090f7 502#define coff_bfd_reloc_name_lookup sh_coff_reloc_name_lookup
17505c5c
NC		 503
504static reloc_howto_type *
505sh_coff_reloc_type_lookup (abfd, code)
506 bfd * abfd ATTRIBUTE_UNUSED;
507 bfd_reloc_code_real_type code;
508{
509 unsigned int i;
510
993e9275
NC		 511 for (i = ARRAY_SIZE (sh_reloc_map); i--;)
512 if (sh_reloc_map[i].bfd_reloc_val == code)
513 return &sh_coff_howtos[(int) sh_reloc_map[i].shcoff_reloc_val];
17505c5c
NC		 514
515 fprintf (stderr, "SH Error: unknown reloc type %d\n", code);
516 return NULL;
517}
17505c5c 518
157090f7
AM		 519static reloc_howto_type *
520sh_coff_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
521 const char *r_name)
522{
523 unsigned int i;
524
525 for (i = 0; i < sizeof (sh_coff_howtos) / sizeof (sh_coff_howtos[0]); i++)
526 if (sh_coff_howtos[i].name != NULL
527 && strcasecmp (sh_coff_howtos[i].name, r_name) == 0)
528 return &sh_coff_howtos[i];
529
530 return NULL;
531}
532
252b5132
RH		 533/* This macro is used in coffcode.h to get the howto corresponding to
534 an internal reloc. */
535
536#define RTYPE2HOWTO(relent, internal) \
537 ((relent)->howto = \
538 ((internal)->r_type < SH_COFF_HOWTO_COUNT \
539 ? &sh_coff_howtos[(internal)->r_type] \
540 : (reloc_howto_type *) NULL))
541
542/* This is the same as the macro in coffcode.h, except that it copies
543 r_offset into reloc_entry->addend for some relocs. */
544#define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \
545 { \
546 coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \
547 if (ptr && bfd_asymbol_bfd (ptr) != abfd) \
548 coffsym = (obj_symbols (abfd) \
549 + (cache_ptr->sym_ptr_ptr - symbols)); \
550 else if (ptr) \
551 coffsym = coff_symbol_from (abfd, ptr); \
552 if (coffsym != (coff_symbol_type *) NULL \
553 && coffsym->native->u.syment.n_scnum == 0) \
554 cache_ptr->addend = 0; \
555 else if (ptr && bfd_asymbol_bfd (ptr) == abfd \
556 && ptr->section != (asection *) NULL) \
557 cache_ptr->addend = - (ptr->section->vma + ptr->value); \
558 else \
559 cache_ptr->addend = 0; \
560 if ((reloc).r_type == R_SH_SWITCH8 \
561 || (reloc).r_type == R_SH_SWITCH16 \
562 || (reloc).r_type == R_SH_SWITCH32 \
563 || (reloc).r_type == R_SH_USES \
564 || (reloc).r_type == R_SH_COUNT \
565 || (reloc).r_type == R_SH_ALIGN) \
566 cache_ptr->addend = (reloc).r_offset; \
567 }
568
569/* This is the howto function for the SH relocations. */
570
571static bfd_reloc_status_type
572sh_reloc (abfd, reloc_entry, symbol_in, data, input_section, output_bfd,
573 error_message)
574 bfd *abfd;
575 arelent *reloc_entry;
576 asymbol *symbol_in;
577 PTR data;
578 asection *input_section;
579 bfd *output_bfd;
5f771d47 580 char **error_message ATTRIBUTE_UNUSED;
252b5132
RH		 581{
582 unsigned long insn;
583 bfd_vma sym_value;
584 unsigned short r_type;
585 bfd_vma addr = reloc_entry->address;
586 bfd_byte *hit_data = addr + (bfd_byte *) data;
587
588 r_type = reloc_entry->howto->type;
589
590 if (output_bfd != NULL)
591 {
592 /* Partial linking--do nothing. */
593 reloc_entry->address += input_section->output_offset;
594 return bfd_reloc_ok;
595 }
596
597 /* Almost all relocs have to do with relaxing. If any work must be
598 done for them, it has been done in sh_relax_section. */
599 if (r_type != R_SH_IMM32
17505c5c
NC		 600#ifdef COFF_WITH_PE
601 && r_type != R_SH_IMM32CE
602 && r_type != R_SH_IMAGEBASE
603#endif
252b5132
RH		 604 && (r_type != R_SH_PCDISP
605 || (symbol_in->flags & BSF_LOCAL) != 0))
606 return bfd_reloc_ok;
607
608 if (symbol_in != NULL
609 && bfd_is_und_section (symbol_in->section))
610 return bfd_reloc_undefined;
611
612 sym_value = get_symbol_value (symbol_in);
613
614 switch (r_type)
615 {
616 case R_SH_IMM32:
17505c5c
NC		 617#ifdef COFF_WITH_PE
618 case R_SH_IMM32CE:
619#endif
252b5132
RH		 620 insn = bfd_get_32 (abfd, hit_data);
621 insn += sym_value + reloc_entry->addend;
dc810e39 622 bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
252b5132 623 break;
17505c5c
NC		 624#ifdef COFF_WITH_PE
625 case R_SH_IMAGEBASE:
626 insn = bfd_get_32 (abfd, hit_data);
dc810e39
AM		 627 insn += sym_value + reloc_entry->addend;
628 insn -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
629 bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
17505c5c
NC		 630 break;
631#endif
252b5132
RH		 632 case R_SH_PCDISP:
633 insn = bfd_get_16 (abfd, hit_data);
634 sym_value += reloc_entry->addend;
635 sym_value -= (input_section->output_section->vma
636 + input_section->output_offset
637 + addr
638 + 4);
639 sym_value += (insn & 0xfff) << 1;
640 if (insn & 0x800)
641 sym_value -= 0x1000;
642 insn = (insn & 0xf000) | (sym_value & 0xfff);
dc810e39 643 bfd_put_16 (abfd, (bfd_vma) insn, hit_data);
252b5132
RH		 644 if (sym_value < (bfd_vma) -0x1000 || sym_value >= 0x1000)
645 return bfd_reloc_overflow;
646 break;
647 default:
648 abort ();
649 break;
650 }
651
652 return bfd_reloc_ok;
653}
654
875f7f69 655#define coff_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match
252b5132
RH		 656
657/* We can do relaxing. */
658#define coff_bfd_relax_section sh_relax_section
659
660/* We use the special COFF backend linker. */
661#define coff_relocate_section sh_relocate_section
662
663/* When relaxing, we need to use special code to get the relocated
664 section contents. */
665#define coff_bfd_get_relocated_section_contents \
666 sh_coff_get_relocated_section_contents
667
668#include "coffcode.h"
669\f
670/* This function handles relaxing on the SH.
671
672 Function calls on the SH look like this:
673
674 movl L1,r0
675 ...
676 jsr @r0
677 ...
678 L1:
679 .long function
680
681 The compiler and assembler will cooperate to create R_SH_USES
682 relocs on the jsr instructions. The r_offset field of the
683 R_SH_USES reloc is the PC relative offset to the instruction which
684 loads the register (the r_offset field is computed as though it
685 were a jump instruction, so the offset value is actually from four
686 bytes past the instruction). The linker can use this reloc to
687 determine just which function is being called, and thus decide
688 whether it is possible to replace the jsr with a bsr.
689
690 If multiple function calls are all based on a single register load
691 (i.e., the same function is called multiple times), the compiler
692 guarantees that each function call will have an R_SH_USES reloc.
693 Therefore, if the linker is able to convert each R_SH_USES reloc
694 which refers to that address, it can safely eliminate the register
695 load.
696
697 When the assembler creates an R_SH_USES reloc, it examines it to
698 determine which address is being loaded (L1 in the above example).
699 It then counts the number of references to that address, and
700 creates an R_SH_COUNT reloc at that address. The r_offset field of
701 the R_SH_COUNT reloc will be the number of references. If the
702 linker is able to eliminate a register load, it can use the
703 R_SH_COUNT reloc to see whether it can also eliminate the function
704 address.
705
706 SH relaxing also handles another, unrelated, matter. On the SH, if
707 a load or store instruction is not aligned on a four byte boundary,
708 the memory cycle interferes with the 32 bit instruction fetch,
709 causing a one cycle bubble in the pipeline. Therefore, we try to
710 align load and store instructions on four byte boundaries if we
711 can, by swapping them with one of the adjacent instructions. */
712
b34976b6 713static bfd_boolean
252b5132
RH		 714sh_relax_section (abfd, sec, link_info, again)
715 bfd *abfd;
716 asection *sec;
717 struct bfd_link_info *link_info;
b34976b6 718 bfd_boolean *again;
252b5132
RH		 719{
720 struct internal_reloc *internal_relocs;
b34976b6 721 bfd_boolean have_code;
252b5132
RH		 722 struct internal_reloc *irel, *irelend;
723 bfd_byte *contents = NULL;
252b5132 724
b34976b6 725 *again = FALSE;
252b5132 726
1049f94e 727 if (link_info->relocatable
252b5132
RH		 728 || (sec->flags & SEC_RELOC) == 0
729 || sec->reloc_count == 0)
b34976b6 730 return TRUE;
252b5132 731
eea6121a
AM		 732 if (coff_section_data (abfd, sec) == NULL)
733 {
734 bfd_size_type amt = sizeof (struct coff_section_tdata);
735 sec->used_by_bfd = (PTR) bfd_zalloc (abfd, amt);
736 if (sec->used_by_bfd == NULL)
737 return FALSE;
738 }
252b5132
RH		 739
740 internal_relocs = (_bfd_coff_read_internal_relocs
741 (abfd, sec, link_info->keep_memory,
b34976b6 742 (bfd_byte *) NULL, FALSE,
252b5132
RH		 743 (struct internal_reloc *) NULL));
744 if (internal_relocs == NULL)
745 goto error_return;
252b5132 746
b34976b6 747 have_code = FALSE;
252b5132
RH		 748
749 irelend = internal_relocs + sec->reloc_count;
750 for (irel = internal_relocs; irel < irelend; irel++)
751 {
752 bfd_vma laddr, paddr, symval;
753 unsigned short insn;
754 struct internal_reloc *irelfn, *irelscan, *irelcount;
755 struct internal_syment sym;
756 bfd_signed_vma foff;
757
758 if (irel->r_type == R_SH_CODE)
b34976b6 759 have_code = TRUE;
252b5132
RH		 760
761 if (irel->r_type != R_SH_USES)
762 continue;
763
764 /* Get the section contents. */
765 if (contents == NULL)
766 {
eea6121a 767 if (coff_section_data (abfd, sec)->contents != NULL)
252b5132
RH		 768 contents = coff_section_data (abfd, sec)->contents;
769 else
770 {
eea6121a 771 if (!bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 772 goto error_return;
773 }
774 }
775
776 /* The r_offset field of the R_SH_USES reloc will point us to
777 the register load. The 4 is because the r_offset field is
778 computed as though it were a jump offset, which are based
779 from 4 bytes after the jump instruction. */
780 laddr = irel->r_vaddr - sec->vma + 4;
781 /* Careful to sign extend the 32-bit offset. */
782 laddr += ((irel->r_offset & 0xffffffff) ^ 0x80000000) - 0x80000000;
eea6121a 783 if (laddr >= sec->size)
252b5132 784 {
d003868e
AM		 785 (*_bfd_error_handler) ("%B: 0x%lx: warning: bad R_SH_USES offset",
786 abfd, (unsigned long) irel->r_vaddr);
252b5132
RH		 787 continue;
788 }
789 insn = bfd_get_16 (abfd, contents + laddr);
790
791 /* If the instruction is not mov.l NN,rN, we don't know what to do. */
792 if ((insn & 0xf000) != 0xd000)
793 {
794 ((*_bfd_error_handler)
d003868e
AM		 795 ("%B: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x",
796 abfd, (unsigned long) irel->r_vaddr, insn));
252b5132
RH		 797 continue;
798 }
799
800 /* Get the address from which the register is being loaded. The
801 displacement in the mov.l instruction is quadrupled. It is a
802 displacement from four bytes after the movl instruction, but,
803 before adding in the PC address, two least significant bits
804 of the PC are cleared. We assume that the section is aligned
805 on a four byte boundary. */
806 paddr = insn & 0xff;
807 paddr *= 4;
dc810e39 808 paddr += (laddr + 4) &~ (bfd_vma) 3;
eea6121a 809 if (paddr >= sec->size)
252b5132
RH		 810 {
811 ((*_bfd_error_handler)
d003868e
AM		 812 ("%B: 0x%lx: warning: bad R_SH_USES load offset",
813 abfd, (unsigned long) irel->r_vaddr));
252b5132
RH		 814 continue;
815 }
816
817 /* Get the reloc for the address from which the register is
818 being loaded. This reloc will tell us which function is
819 actually being called. */
820 paddr += sec->vma;
821 for (irelfn = internal_relocs; irelfn < irelend; irelfn++)
822 if (irelfn->r_vaddr == paddr
17505c5c
NC		 823#ifdef COFF_WITH_PE
824 && (irelfn->r_type == R_SH_IMM32
825 || irelfn->r_type == R_SH_IMM32CE
eea6121a 826 || irelfn->r_type == R_SH_IMAGEBASE)
17505c5c
NC		 827
828#else
eea6121a 829 && irelfn->r_type == R_SH_IMM32
17505c5c 830#endif
eea6121a 831 )
252b5132
RH		 832 break;
833 if (irelfn >= irelend)
834 {
835 ((*_bfd_error_handler)
d003868e
AM		 836 ("%B: 0x%lx: warning: could not find expected reloc",
837 abfd, (unsigned long) paddr));
252b5132
RH		 838 continue;
839 }
840
841 /* Get the value of the symbol referred to by the reloc. */
842 if (! _bfd_coff_get_external_symbols (abfd))
843 goto error_return;
844 bfd_coff_swap_sym_in (abfd,
845 ((bfd_byte *) obj_coff_external_syms (abfd)
846 + (irelfn->r_symndx
847 * bfd_coff_symesz (abfd))),
848 &sym);
849 if (sym.n_scnum != 0 && sym.n_scnum != sec->target_index)
850 {
851 ((*_bfd_error_handler)
d003868e
AM		 852 ("%B: 0x%lx: warning: symbol in unexpected section",
853 abfd, (unsigned long) paddr));
252b5132
RH		 854 continue;
855 }
856
857 if (sym.n_sclass != C_EXT)
858 {
859 symval = (sym.n_value
860 - sec->vma
861 + sec->output_section->vma
862 + sec->output_offset);
863 }
864 else
865 {
866 struct coff_link_hash_entry *h;
867
868 h = obj_coff_sym_hashes (abfd)[irelfn->r_symndx];
869 BFD_ASSERT (h != NULL);
870 if (h->root.type != bfd_link_hash_defined
871 && h->root.type != bfd_link_hash_defweak)
872 {
873 /* This appears to be a reference to an undefined
874 symbol. Just ignore it--it will be caught by the
875 regular reloc processing. */
876 continue;
877 }
878
879 symval = (h->root.u.def.value
880 + h->root.u.def.section->output_section->vma
881 + h->root.u.def.section->output_offset);
882 }
883
884 symval += bfd_get_32 (abfd, contents + paddr - sec->vma);
885
886 /* See if this function call can be shortened. */
887 foff = (symval
888 - (irel->r_vaddr
889 - sec->vma
890 + sec->output_section->vma
891 + sec->output_offset
892 + 4));
893 if (foff < -0x1000 || foff >= 0x1000)
894 {
895 /* After all that work, we can't shorten this function call. */
896 continue;
897 }
898
899 /* Shorten the function call. */
900
901 /* For simplicity of coding, we are going to modify the section
902 contents, the section relocs, and the BFD symbol table. We
903 must tell the rest of the code not to free up this
904 information. It would be possible to instead create a table
905 of changes which have to be made, as is done in coff-mips.c;
906 that would be more work, but would require less memory when
907 the linker is run. */
908
252b5132 909 coff_section_data (abfd, sec)->relocs = internal_relocs;
b34976b6 910 coff_section_data (abfd, sec)->keep_relocs = TRUE;
252b5132
RH		 911
912 coff_section_data (abfd, sec)->contents = contents;
b34976b6 913 coff_section_data (abfd, sec)->keep_contents = TRUE;
252b5132 914
b34976b6 915 obj_coff_keep_syms (abfd) = TRUE;
252b5132
RH		 916
917 /* Replace the jsr with a bsr. */
918
919 /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and
920 replace the jsr with a bsr. */
921 irel->r_type = R_SH_PCDISP;
922 irel->r_symndx = irelfn->r_symndx;
923 if (sym.n_sclass != C_EXT)
924 {
925 /* If this needs to be changed because of future relaxing,
926 it will be handled here like other internal PCDISP
927 relocs. */
928 bfd_put_16 (abfd,
dc810e39 929 (bfd_vma) 0xb000 | ((foff >> 1) & 0xfff),
252b5132
RH		 930 contents + irel->r_vaddr - sec->vma);
931 }
932 else
933 {
934 /* We can't fully resolve this yet, because the external
935 symbol value may be changed by future relaxing. We let
936 the final link phase handle it. */
dc810e39
AM		 937 bfd_put_16 (abfd, (bfd_vma) 0xb000,
938 contents + irel->r_vaddr - sec->vma);
252b5132
RH		 939 }
940
941 /* See if there is another R_SH_USES reloc referring to the same
942 register load. */
943 for (irelscan = internal_relocs; irelscan < irelend; irelscan++)
944 if (irelscan->r_type == R_SH_USES
945 && laddr == irelscan->r_vaddr - sec->vma + 4 + irelscan->r_offset)
946 break;
947 if (irelscan < irelend)
948 {
949 /* Some other function call depends upon this register load,
950 and we have not yet converted that function call.
951 Indeed, we may never be able to convert it. There is
952 nothing else we can do at this point. */
953 continue;
954 }
955
956 /* Look for a R_SH_COUNT reloc on the location where the
957 function address is stored. Do this before deleting any
958 bytes, to avoid confusion about the address. */
959 for (irelcount = internal_relocs; irelcount < irelend; irelcount++)
960 if (irelcount->r_vaddr == paddr
961 && irelcount->r_type == R_SH_COUNT)
962 break;
963
964 /* Delete the register load. */
965 if (! sh_relax_delete_bytes (abfd, sec, laddr, 2))
966 goto error_return;
967
968 /* That will change things, so, just in case it permits some
969 other function call to come within range, we should relax
970 again. Note that this is not required, and it may be slow. */
b34976b6 971 *again = TRUE;
252b5132
RH		 972
973 /* Now check whether we got a COUNT reloc. */
974 if (irelcount >= irelend)
975 {
976 ((*_bfd_error_handler)
d003868e
AM		 977 ("%B: 0x%lx: warning: could not find expected COUNT reloc",
978 abfd, (unsigned long) paddr));
252b5132
RH		 979 continue;
980 }
981
982 /* The number of uses is stored in the r_offset field. We've
983 just deleted one. */
984 if (irelcount->r_offset == 0)
985 {
d003868e
AM		 986 ((*_bfd_error_handler) ("%B: 0x%lx: warning: bad count",
987 abfd, (unsigned long) paddr));
252b5132
RH		 988 continue;
989 }
990
991 --irelcount->r_offset;
992
993 /* If there are no more uses, we can delete the address. Reload
994 the address from irelfn, in case it was changed by the
995 previous call to sh_relax_delete_bytes. */
996 if (irelcount->r_offset == 0)
997 {
998 if (! sh_relax_delete_bytes (abfd, sec,
999 irelfn->r_vaddr - sec->vma, 4))
1000 goto error_return;
1001 }
1002
1003 /* We've done all we can with that function call. */
1004 }
1005
1006 /* Look for load and store instructions that we can align on four
1007 byte boundaries. */
1008 if (have_code)
1009 {
b34976b6 1010 bfd_boolean swapped;
252b5132
RH		 1011
1012 /* Get the section contents. */
1013 if (contents == NULL)
1014 {
eea6121a 1015 if (coff_section_data (abfd, sec)->contents != NULL)
252b5132
RH		 1016 contents = coff_section_data (abfd, sec)->contents;
1017 else
1018 {
eea6121a 1019 if (!bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 1020 goto error_return;
1021 }
1022 }
1023
1024 if (! sh_align_loads (abfd, sec, internal_relocs, contents, &swapped))
1025 goto error_return;
1026
1027 if (swapped)
1028 {
252b5132 1029 coff_section_data (abfd, sec)->relocs = internal_relocs;
b34976b6 1030 coff_section_data (abfd, sec)->keep_relocs = TRUE;
252b5132
RH		 1031
1032 coff_section_data (abfd, sec)->contents = contents;
b34976b6 1033 coff_section_data (abfd, sec)->keep_contents = TRUE;
252b5132 1034
b34976b6 1035 obj_coff_keep_syms (abfd) = TRUE;
252b5132
RH		 1036 }
1037 }
1038
eea6121a
AM		 1039 if (internal_relocs != NULL
1040 && internal_relocs != coff_section_data (abfd, sec)->relocs)
252b5132 1041 {
eea6121a
AM		 1042 if (! link_info->keep_memory)
1043 free (internal_relocs);
1044 else
1045 coff_section_data (abfd, sec)->relocs = internal_relocs;
252b5132
RH		 1046 }
1047
eea6121a 1048 if (contents != NULL && contents != coff_section_data (abfd, sec)->contents)
252b5132
RH		 1049 {
1050 if (! link_info->keep_memory)
eea6121a 1051 free (contents);
252b5132 1052 else
eea6121a
AM		 1053 /* Cache the section contents for coff_link_input_bfd. */
1054 coff_section_data (abfd, sec)->contents = contents;
252b5132
RH		 1055 }
1056
b34976b6 1057 return TRUE;
252b5132
RH		 1058
1059 error_return:
eea6121a
AM		 1060 if (internal_relocs != NULL
1061 && internal_relocs != coff_section_data (abfd, sec)->relocs)
1062 free (internal_relocs);
1063 if (contents != NULL && contents != coff_section_data (abfd, sec)->contents)
1064 free (contents);
b34976b6 1065 return FALSE;
252b5132
RH		 1066}
1067
1068/* Delete some bytes from a section while relaxing. */
1069
b34976b6 1070static bfd_boolean
252b5132
RH		 1071sh_relax_delete_bytes (abfd, sec, addr, count)
1072 bfd *abfd;
1073 asection *sec;
1074 bfd_vma addr;
1075 int count;
1076{
1077 bfd_byte *contents;
1078 struct internal_reloc *irel, *irelend;
1079 struct internal_reloc *irelalign;
1080 bfd_vma toaddr;
1081 bfd_byte *esym, *esymend;
1082 bfd_size_type symesz;
1083 struct coff_link_hash_entry **sym_hash;
1084 asection *o;
1085
1086 contents = coff_section_data (abfd, sec)->contents;
1087
1088 /* The deletion must stop at the next ALIGN reloc for an aligment
1089 power larger than the number of bytes we are deleting. */
1090
1091 irelalign = NULL;
eea6121a 1092 toaddr = sec->size;
252b5132
RH		 1093
1094 irel = coff_section_data (abfd, sec)->relocs;
1095 irelend = irel + sec->reloc_count;
1096 for (; irel < irelend; irel++)
1097 {
1098 if (irel->r_type == R_SH_ALIGN
1099 && irel->r_vaddr - sec->vma > addr
1100 && count < (1 << irel->r_offset))
1101 {
1102 irelalign = irel;
1103 toaddr = irel->r_vaddr - sec->vma;
1104 break;
1105 }
1106 }
1107
1108 /* Actually delete the bytes. */
dc810e39
AM		 1109 memmove (contents + addr, contents + addr + count,
1110 (size_t) (toaddr - addr - count));
252b5132 1111 if (irelalign == NULL)
eea6121a 1112 sec->size -= count;
252b5132
RH		 1113 else
1114 {
1115 int i;
1116
1117#define NOP_OPCODE (0x0009)
1118
1119 BFD_ASSERT ((count & 1) == 0);
1120 for (i = 0; i < count; i += 2)
dc810e39 1121 bfd_put_16 (abfd, (bfd_vma) NOP_OPCODE, contents + toaddr - count + i);
252b5132
RH		 1122 }
1123
1124 /* Adjust all the relocs. */
1125 for (irel = coff_section_data (abfd, sec)->relocs; irel < irelend; irel++)
1126 {
1127 bfd_vma nraddr, stop;
1128 bfd_vma start = 0;
1129 int insn = 0;
1130 struct internal_syment sym;
1131 int off, adjust, oinsn;
1132 bfd_signed_vma voff = 0;
b34976b6 1133 bfd_boolean overflow;
252b5132
RH		 1134
1135 /* Get the new reloc address. */
1136 nraddr = irel->r_vaddr - sec->vma;
1137 if ((irel->r_vaddr - sec->vma > addr
1138 && irel->r_vaddr - sec->vma < toaddr)
1139 || (irel->r_type == R_SH_ALIGN
1140 && irel->r_vaddr - sec->vma == toaddr))
1141 nraddr -= count;
1142
1143 /* See if this reloc was for the bytes we have deleted, in which
1144 case we no longer care about it. Don't delete relocs which
1145 represent addresses, though. */
1146 if (irel->r_vaddr - sec->vma >= addr
1147 && irel->r_vaddr - sec->vma < addr + count
1148 && irel->r_type != R_SH_ALIGN
1149 && irel->r_type != R_SH_CODE
1150 && irel->r_type != R_SH_DATA
1151 && irel->r_type != R_SH_LABEL)
1152 irel->r_type = R_SH_UNUSED;
1153
1154 /* If this is a PC relative reloc, see if the range it covers
1155 includes the bytes we have deleted. */
1156 switch (irel->r_type)
1157 {
1158 default:
1159 break;
1160
1161 case R_SH_PCDISP8BY2:
1162 case R_SH_PCDISP:
1163 case R_SH_PCRELIMM8BY2:
1164 case R_SH_PCRELIMM8BY4:
1165 start = irel->r_vaddr - sec->vma;
1166 insn = bfd_get_16 (abfd, contents + nraddr);
1167 break;
1168 }
1169
1170 switch (irel->r_type)
1171 {
1172 default:
1173 start = stop = addr;
1174 break;
1175
1176 case R_SH_IMM32:
17505c5c
NC		 1177#ifdef COFF_WITH_PE
1178 case R_SH_IMM32CE:
1179 case R_SH_IMAGEBASE:
1180#endif
252b5132
RH		 1181 /* If this reloc is against a symbol defined in this
1182 section, and the symbol will not be adjusted below, we
1183 must check the addend to see it will put the value in
1184 range to be adjusted, and hence must be changed. */
1185 bfd_coff_swap_sym_in (abfd,
1186 ((bfd_byte *) obj_coff_external_syms (abfd)
1187 + (irel->r_symndx
1188 * bfd_coff_symesz (abfd))),
1189 &sym);
1190 if (sym.n_sclass != C_EXT
1191 && sym.n_scnum == sec->target_index
1192 && ((bfd_vma) sym.n_value <= addr
1193 || (bfd_vma) sym.n_value >= toaddr))
1194 {
1195 bfd_vma val;
1196
1197 val = bfd_get_32 (abfd, contents + nraddr);
1198 val += sym.n_value;
1199 if (val > addr && val < toaddr)
1200 bfd_put_32 (abfd, val - count, contents + nraddr);
1201 }
1202 start = stop = addr;
1203 break;
1204
1205 case R_SH_PCDISP8BY2:
1206 off = insn & 0xff;
1207 if (off & 0x80)
1208 off -= 0x100;
1209 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1210 break;
1211
1212 case R_SH_PCDISP:
1213 bfd_coff_swap_sym_in (abfd,
1214 ((bfd_byte *) obj_coff_external_syms (abfd)
1215 + (irel->r_symndx
1216 * bfd_coff_symesz (abfd))),
1217 &sym);
1218 if (sym.n_sclass == C_EXT)
1219 start = stop = addr;
1220 else
1221 {
1222 off = insn & 0xfff;
1223 if (off & 0x800)
1224 off -= 0x1000;
1225 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1226 }
1227 break;
1228
1229 case R_SH_PCRELIMM8BY2:
1230 off = insn & 0xff;
1231 stop = start + 4 + off * 2;
1232 break;
1233
1234 case R_SH_PCRELIMM8BY4:
1235 off = insn & 0xff;
1236 stop = (start &~ (bfd_vma) 3) + 4 + off * 4;
1237 break;
1238
1239 case R_SH_SWITCH8:
1240 case R_SH_SWITCH16:
1241 case R_SH_SWITCH32:
1242 /* These relocs types represent
1243 .word L2-L1
1244 The r_offset field holds the difference between the reloc
1245 address and L1. That is the start of the reloc, and
1246 adding in the contents gives us the top. We must adjust
1247 both the r_offset field and the section contents. */
1248
1249 start = irel->r_vaddr - sec->vma;
1250 stop = (bfd_vma) ((bfd_signed_vma) start - (long) irel->r_offset);
1251
1252 if (start > addr
1253 && start < toaddr
1254 && (stop <= addr || stop >= toaddr))
1255 irel->r_offset += count;
1256 else if (stop > addr
1257 && stop < toaddr
1258 && (start <= addr || start >= toaddr))
1259 irel->r_offset -= count;
1260
1261 start = stop;
1262
1263 if (irel->r_type == R_SH_SWITCH16)
1264 voff = bfd_get_signed_16 (abfd, contents + nraddr);
1265 else if (irel->r_type == R_SH_SWITCH8)
1266 voff = bfd_get_8 (abfd, contents + nraddr);
1267 else
1268 voff = bfd_get_signed_32 (abfd, contents + nraddr);
1269 stop = (bfd_vma) ((bfd_signed_vma) start + voff);
1270
1271 break;
1272
1273 case R_SH_USES:
1274 start = irel->r_vaddr - sec->vma;
1275 stop = (bfd_vma) ((bfd_signed_vma) start
1276 + (long) irel->r_offset
1277 + 4);
1278 break;
1279 }
1280
1281 if (start > addr
1282 && start < toaddr
1283 && (stop <= addr || stop >= toaddr))
1284 adjust = count;
1285 else if (stop > addr
1286 && stop < toaddr
1287 && (start <= addr || start >= toaddr))
1288 adjust = - count;
1289 else
1290 adjust = 0;
1291
1292 if (adjust != 0)
1293 {
1294 oinsn = insn;
b34976b6 1295 overflow = FALSE;
252b5132
RH		 1296 switch (irel->r_type)
1297 {
1298 default:
1299 abort ();
1300 break;
1301
1302 case R_SH_PCDISP8BY2:
1303 case R_SH_PCRELIMM8BY2:
1304 insn += adjust / 2;
1305 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 1306 overflow = TRUE;
dc810e39 1307 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1308 break;
1309
1310 case R_SH_PCDISP:
1311 insn += adjust / 2;
1312 if ((oinsn & 0xf000) != (insn & 0xf000))
b34976b6 1313 overflow = TRUE;
dc810e39 1314 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1315 break;
1316
1317 case R_SH_PCRELIMM8BY4:
1318 BFD_ASSERT (adjust == count || count >= 4);
1319 if (count >= 4)
1320 insn += adjust / 4;
1321 else
1322 {
1323 if ((irel->r_vaddr & 3) == 0)
1324 ++insn;
1325 }
1326 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 1327 overflow = TRUE;
dc810e39 1328 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1329 break;
1330
1331 case R_SH_SWITCH8:
1332 voff += adjust;
1333 if (voff < 0 || voff >= 0xff)
b34976b6 1334 overflow = TRUE;
dc810e39 1335 bfd_put_8 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1336 break;
1337
1338 case R_SH_SWITCH16:
1339 voff += adjust;
1340 if (voff < - 0x8000 || voff >= 0x8000)
b34976b6 1341 overflow = TRUE;
dc810e39 1342 bfd_put_signed_16 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1343 break;
1344
1345 case R_SH_SWITCH32:
1346 voff += adjust;
dc810e39 1347 bfd_put_signed_32 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1348 break;
1349
1350 case R_SH_USES:
1351 irel->r_offset += adjust;
1352 break;
1353 }
1354
1355 if (overflow)
1356 {
1357 ((*_bfd_error_handler)
d003868e
AM		 1358 ("%B: 0x%lx: fatal: reloc overflow while relaxing",
1359 abfd, (unsigned long) irel->r_vaddr));
252b5132 1360 bfd_set_error (bfd_error_bad_value);
b34976b6 1361 return FALSE;
252b5132
RH		 1362 }
1363 }
1364
1365 irel->r_vaddr = nraddr + sec->vma;
1366 }
1367
1368 /* Look through all the other sections. If there contain any IMM32
1369 relocs against internal symbols which we are not going to adjust
1370 below, we may need to adjust the addends. */
1371 for (o = abfd->sections; o != NULL; o = o->next)
1372 {
1373 struct internal_reloc *internal_relocs;
1374 struct internal_reloc *irelscan, *irelscanend;
1375 bfd_byte *ocontents;
1376
1377 if (o == sec
1378 || (o->flags & SEC_RELOC) == 0
1379 || o->reloc_count == 0)
1380 continue;
1381
1382 /* We always cache the relocs. Perhaps, if info->keep_memory is
b34976b6 1383 FALSE, we should free them, if we are permitted to, when we
252b5132
RH		 1384 leave sh_coff_relax_section. */
1385 internal_relocs = (_bfd_coff_read_internal_relocs
b34976b6 1386 (abfd, o, TRUE, (bfd_byte *) NULL, FALSE,
252b5132
RH		 1387 (struct internal_reloc *) NULL));
1388 if (internal_relocs == NULL)
b34976b6 1389 return FALSE;
252b5132
RH		 1390
1391 ocontents = NULL;
1392 irelscanend = internal_relocs + o->reloc_count;
1393 for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++)
1394 {
1395 struct internal_syment sym;
1396
17505c5c
NC		 1397#ifdef COFF_WITH_PE
1398 if (irelscan->r_type != R_SH_IMM32
1399 && irelscan->r_type != R_SH_IMAGEBASE
1400 && irelscan->r_type != R_SH_IMM32CE)
1401#else
252b5132 1402 if (irelscan->r_type != R_SH_IMM32)
17505c5c 1403#endif
252b5132
RH		 1404 continue;
1405
1406 bfd_coff_swap_sym_in (abfd,
1407 ((bfd_byte *) obj_coff_external_syms (abfd)
1408 + (irelscan->r_symndx
1409 * bfd_coff_symesz (abfd))),
1410 &sym);
1411 if (sym.n_sclass != C_EXT
1412 && sym.n_scnum == sec->target_index
1413 && ((bfd_vma) sym.n_value <= addr
1414 || (bfd_vma) sym.n_value >= toaddr))
1415 {
1416 bfd_vma val;
1417
1418 if (ocontents == NULL)
1419 {
1420 if (coff_section_data (abfd, o)->contents != NULL)
1421 ocontents = coff_section_data (abfd, o)->contents;
1422 else
1423 {
eea6121a
AM		 1424 if (!bfd_malloc_and_get_section (abfd, o, &ocontents))
1425 return FALSE;
252b5132 1426 /* We always cache the section contents.
b34976b6 1427 Perhaps, if info->keep_memory is FALSE, we
252b5132
RH		 1428 should free them, if we are permitted to,
1429 when we leave sh_coff_relax_section. */
252b5132
RH		 1430 coff_section_data (abfd, o)->contents = ocontents;
1431 }
1432 }
1433
1434 val = bfd_get_32 (abfd, ocontents + irelscan->r_vaddr - o->vma);
1435 val += sym.n_value;
1436 if (val > addr && val < toaddr)
1437 bfd_put_32 (abfd, val - count,
1438 ocontents + irelscan->r_vaddr - o->vma);
1439
b34976b6 1440 coff_section_data (abfd, o)->keep_contents = TRUE;
252b5132
RH		 1441 }
1442 }
1443 }
1444
1445 /* Adjusting the internal symbols will not work if something has
1446 already retrieved the generic symbols. It would be possible to
1447 make this work by adjusting the generic symbols at the same time.
1448 However, this case should not arise in normal usage. */
1449 if (obj_symbols (abfd) != NULL
1450 || obj_raw_syments (abfd) != NULL)
1451 {
1452 ((*_bfd_error_handler)
d003868e 1453 ("%B: fatal: generic symbols retrieved before relaxing", abfd));
252b5132 1454 bfd_set_error (bfd_error_invalid_operation);
b34976b6 1455 return FALSE;
252b5132
RH		 1456 }
1457
1458 /* Adjust all the symbols. */
1459 sym_hash = obj_coff_sym_hashes (abfd);
1460 symesz = bfd_coff_symesz (abfd);
1461 esym = (bfd_byte *) obj_coff_external_syms (abfd);
1462 esymend = esym + obj_raw_syment_count (abfd) * symesz;
1463 while (esym < esymend)
1464 {
1465 struct internal_syment isym;
1466
1467 bfd_coff_swap_sym_in (abfd, (PTR) esym, (PTR) &isym);
1468
1469 if (isym.n_scnum == sec->target_index
1470 && (bfd_vma) isym.n_value > addr
1471 && (bfd_vma) isym.n_value < toaddr)
1472 {
1473 isym.n_value -= count;
1474
1475 bfd_coff_swap_sym_out (abfd, (PTR) &isym, (PTR) esym);
1476
1477 if (*sym_hash != NULL)
1478 {
1479 BFD_ASSERT ((*sym_hash)->root.type == bfd_link_hash_defined
1480 || (*sym_hash)->root.type == bfd_link_hash_defweak);
1481 BFD_ASSERT ((*sym_hash)->root.u.def.value >= addr
1482 && (*sym_hash)->root.u.def.value < toaddr);
1483 (*sym_hash)->root.u.def.value -= count;
1484 }
1485 }
1486
1487 esym += (isym.n_numaux + 1) * symesz;
1488 sym_hash += isym.n_numaux + 1;
1489 }
1490
1491 /* See if we can move the ALIGN reloc forward. We have adjusted
1492 r_vaddr for it already. */
1493 if (irelalign != NULL)
1494 {
1495 bfd_vma alignto, alignaddr;
1496
1497 alignto = BFD_ALIGN (toaddr, 1 << irelalign->r_offset);
1498 alignaddr = BFD_ALIGN (irelalign->r_vaddr - sec->vma,
1499 1 << irelalign->r_offset);
1500 if (alignto != alignaddr)
1501 {
1502 /* Tail recursion. */
1503 return sh_relax_delete_bytes (abfd, sec, alignaddr,
dc810e39 1504 (int) (alignto - alignaddr));
252b5132
RH		 1505 }
1506 }
1507
b34976b6 1508 return TRUE;
252b5132
RH		 1509}
1510\f
1511/* This is yet another version of the SH opcode table, used to rapidly
1512 get information about a particular instruction. */
1513
1514/* The opcode map is represented by an array of these structures. The
1515 array is indexed by the high order four bits in the instruction. */
1516
1517struct sh_major_opcode
1518{
1519 /* A pointer to the instruction list. This is an array which
1520 contains all the instructions with this major opcode. */
1521 const struct sh_minor_opcode *minor_opcodes;
1522 /* The number of elements in minor_opcodes. */
1523 unsigned short count;
1524};
1525
1526/* This structure holds information for a set of SH opcodes. The
1527 instruction code is anded with the mask value, and the resulting
1528 value is used to search the order opcode list. */
1529
1530struct sh_minor_opcode
1531{
1532 /* The sorted opcode list. */
1533 const struct sh_opcode *opcodes;
1534 /* The number of elements in opcodes. */
1535 unsigned short count;
1536 /* The mask value to use when searching the opcode list. */
1537 unsigned short mask;
1538};
1539
1540/* This structure holds information for an SH instruction. An array
1541 of these structures is sorted in order by opcode. */
1542
1543struct sh_opcode
1544{
1545 /* The code for this instruction, after it has been anded with the
1546 mask value in the sh_major_opcode structure. */
1547 unsigned short opcode;
1548 /* Flags for this instruction. */
86033394 1549 unsigned long flags;
252b5132
RH		 1550};
1551
1552/* Flag which appear in the sh_opcode structure. */
1553
1554/* This instruction loads a value from memory. */
1555#define LOAD (0x1)
1556
1557/* This instruction stores a value to memory. */
1558#define STORE (0x2)
1559
1560/* This instruction is a branch. */
1561#define BRANCH (0x4)
1562
1563/* This instruction has a delay slot. */
1564#define DELAY (0x8)
1565
1566/* This instruction uses the value in the register in the field at
1567 mask 0x0f00 of the instruction. */
1568#define USES1 (0x10)
84dcfba7 1569#define USES1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1570
1571/* This instruction uses the value in the register in the field at
1572 mask 0x00f0 of the instruction. */
1573#define USES2 (0x20)
84dcfba7 1574#define USES2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1575
1576/* This instruction uses the value in register 0. */
1577#define USESR0 (0x40)
1578
1579/* This instruction sets the value in the register in the field at
1580 mask 0x0f00 of the instruction. */
1581#define SETS1 (0x80)
84dcfba7 1582#define SETS1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1583
1584/* This instruction sets the value in the register in the field at
1585 mask 0x00f0 of the instruction. */
1586#define SETS2 (0x100)
84dcfba7 1587#define SETS2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1588
1589/* This instruction sets register 0. */
1590#define SETSR0 (0x200)
1591
1592/* This instruction sets a special register. */
1593#define SETSSP (0x400)
1594
1595/* This instruction uses a special register. */
1596#define USESSP (0x800)
1597
1598/* This instruction uses the floating point register in the field at
1599 mask 0x0f00 of the instruction. */
1600#define USESF1 (0x1000)
84dcfba7 1601#define USESF1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1602
1603/* This instruction uses the floating point register in the field at
1604 mask 0x00f0 of the instruction. */
1605#define USESF2 (0x2000)
84dcfba7 1606#define USESF2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1607
1608/* This instruction uses floating point register 0. */
1609#define USESF0 (0x4000)
1610
1611/* This instruction sets the floating point register in the field at
1612 mask 0x0f00 of the instruction. */
1613#define SETSF1 (0x8000)
84dcfba7 1614#define SETSF1_REG(x) ((x & 0x0f00) >> 8)
252b5132 1615
d4845d57
JR		 1616#define USESAS (0x10000)
1617#define USESAS_REG(x) (((((x) >> 8) - 2) & 3) + 2)
1618#define USESR8 (0x20000)
1619#define SETSAS (0x40000)
1620#define SETSAS_REG(x) USESAS_REG (x)
1621
8d6ad26e
AM		 1622#define MAP(a) a, sizeof a / sizeof a[0]
1623
86033394 1624#ifndef COFF_IMAGE_WITH_PE
b34976b6 1625static bfd_boolean sh_insn_uses_reg
252b5132 1626 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1627static bfd_boolean sh_insn_sets_reg
84dcfba7 1628 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1629static bfd_boolean sh_insn_uses_or_sets_reg
84dcfba7 1630 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1631static bfd_boolean sh_insn_uses_freg
252b5132 1632 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1633static bfd_boolean sh_insn_sets_freg
84dcfba7 1634 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1635static bfd_boolean sh_insn_uses_or_sets_freg
84dcfba7 1636 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1637static bfd_boolean sh_insns_conflict
252b5132
RH		 1638 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1639 const struct sh_opcode *));
b34976b6 1640static bfd_boolean sh_load_use
252b5132
RH		 1641 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1642 const struct sh_opcode *));
252b5132 1643
8d6ad26e 1644/* The opcode maps. */
252b5132
RH		 1645
1646static const struct sh_opcode sh_opcode00[] =
1647{
1648 { 0x0008, SETSSP }, /* clrt */
1649 { 0x0009, 0 }, /* nop */
1650 { 0x000b, BRANCH | DELAY | USESSP }, /* rts */
1651 { 0x0018, SETSSP }, /* sett */
1652 { 0x0019, SETSSP }, /* div0u */
1653 { 0x001b, 0 }, /* sleep */
1654 { 0x0028, SETSSP }, /* clrmac */
1655 { 0x002b, BRANCH | DELAY | SETSSP }, /* rte */
1656 { 0x0038, USESSP | SETSSP }, /* ldtlb */
1657 { 0x0048, SETSSP }, /* clrs */
1658 { 0x0058, SETSSP } /* sets */
1659};
1660
1661static const struct sh_opcode sh_opcode01[] =
1662{
252b5132
RH		 1663 { 0x0003, BRANCH | DELAY | USES1 | SETSSP }, /* bsrf rn */
1664 { 0x000a, SETS1 | USESSP }, /* sts mach,rn */
252b5132 1665 { 0x001a, SETS1 | USESSP }, /* sts macl,rn */
252b5132
RH		 1666 { 0x0023, BRANCH | DELAY | USES1 }, /* braf rn */
1667 { 0x0029, SETS1 | USESSP }, /* movt rn */
1668 { 0x002a, SETS1 | USESSP }, /* sts pr,rn */
d4845d57
JR		 1669 { 0x005a, SETS1 | USESSP }, /* sts fpul,rn */
1670 { 0x006a, SETS1 | USESSP }, /* sts fpscr,rn / sts dsr,rn */
1671 { 0x0083, LOAD | USES1 }, /* pref @rn */
1672 { 0x007a, SETS1 | USESSP }, /* sts a0,rn */
1673 { 0x008a, SETS1 | USESSP }, /* sts x0,rn */
1674 { 0x009a, SETS1 | USESSP }, /* sts x1,rn */
1675 { 0x00aa, SETS1 | USESSP }, /* sts y0,rn */
1676 { 0x00ba, SETS1 | USESSP } /* sts y1,rn */
1677};
1678
252b5132
RH		 1679static const struct sh_opcode sh_opcode02[] =
1680{
d4845d57 1681 { 0x0002, SETS1 | USESSP }, /* stc <special_reg>,rn */
252b5132
RH		 1682 { 0x0004, STORE | USES1 | USES2 | USESR0 }, /* mov.b rm,@(r0,rn) */
1683 { 0x0005, STORE | USES1 | USES2 | USESR0 }, /* mov.w rm,@(r0,rn) */
1684 { 0x0006, STORE | USES1 | USES2 | USESR0 }, /* mov.l rm,@(r0,rn) */
1685 { 0x0007, SETSSP | USES1 | USES2 }, /* mul.l rm,rn */
1686 { 0x000c, LOAD | SETS1 | USES2 | USESR0 }, /* mov.b @(r0,rm),rn */
1687 { 0x000d, LOAD | SETS1 | USES2 | USESR0 }, /* mov.w @(r0,rm),rn */
1688 { 0x000e, LOAD | SETS1 | USES2 | USESR0 }, /* mov.l @(r0,rm),rn */
1689 { 0x000f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.l @rm+,@rn+ */
1690};
1691
1692static const struct sh_minor_opcode sh_opcode0[] =
1693{
1694 { MAP (sh_opcode00), 0xffff },
1695 { MAP (sh_opcode01), 0xf0ff },
1696 { MAP (sh_opcode02), 0xf00f }
1697};
1698
1699static const struct sh_opcode sh_opcode10[] =
1700{
1701 { 0x1000, STORE | USES1 | USES2 } /* mov.l rm,@(disp,rn) */
1702};
1703
1704static const struct sh_minor_opcode sh_opcode1[] =
1705{
1706 { MAP (sh_opcode10), 0xf000 }
1707};
1708
1709static const struct sh_opcode sh_opcode20[] =
1710{
1711 { 0x2000, STORE | USES1 | USES2 }, /* mov.b rm,@rn */
1712 { 0x2001, STORE | USES1 | USES2 }, /* mov.w rm,@rn */
1713 { 0x2002, STORE | USES1 | USES2 }, /* mov.l rm,@rn */
1714 { 0x2004, STORE | SETS1 | USES1 | USES2 }, /* mov.b rm,@-rn */
1715 { 0x2005, STORE | SETS1 | USES1 | USES2 }, /* mov.w rm,@-rn */
1716 { 0x2006, STORE | SETS1 | USES1 | USES2 }, /* mov.l rm,@-rn */
1717 { 0x2007, SETSSP | USES1 | USES2 | USESSP }, /* div0s */
1718 { 0x2008, SETSSP | USES1 | USES2 }, /* tst rm,rn */
1719 { 0x2009, SETS1 | USES1 | USES2 }, /* and rm,rn */
1720 { 0x200a, SETS1 | USES1 | USES2 }, /* xor rm,rn */
1721 { 0x200b, SETS1 | USES1 | USES2 }, /* or rm,rn */
1722 { 0x200c, SETSSP | USES1 | USES2 }, /* cmp/str rm,rn */
1723 { 0x200d, SETS1 | USES1 | USES2 }, /* xtrct rm,rn */
1724 { 0x200e, SETSSP | USES1 | USES2 }, /* mulu.w rm,rn */
1725 { 0x200f, SETSSP | USES1 | USES2 } /* muls.w rm,rn */
1726};
1727
1728static const struct sh_minor_opcode sh_opcode2[] =
1729{
1730 { MAP (sh_opcode20), 0xf00f }
1731};
1732
1733static const struct sh_opcode sh_opcode30[] =
1734{
1735 { 0x3000, SETSSP | USES1 | USES2 }, /* cmp/eq rm,rn */
1736 { 0x3002, SETSSP | USES1 | USES2 }, /* cmp/hs rm,rn */
1737 { 0x3003, SETSSP | USES1 | USES2 }, /* cmp/ge rm,rn */
1738 { 0x3004, SETSSP | USESSP | USES1 | USES2 }, /* div1 rm,rn */
1739 { 0x3005, SETSSP | USES1 | USES2 }, /* dmulu.l rm,rn */
1740 { 0x3006, SETSSP | USES1 | USES2 }, /* cmp/hi rm,rn */
1741 { 0x3007, SETSSP | USES1 | USES2 }, /* cmp/gt rm,rn */
1742 { 0x3008, SETS1 | USES1 | USES2 }, /* sub rm,rn */
1743 { 0x300a, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* subc rm,rn */
1744 { 0x300b, SETS1 | SETSSP | USES1 | USES2 }, /* subv rm,rn */
1745 { 0x300c, SETS1 | USES1 | USES2 }, /* add rm,rn */
1746 { 0x300d, SETSSP | USES1 | USES2 }, /* dmuls.l rm,rn */
1747 { 0x300e, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* addc rm,rn */
1748 { 0x300f, SETS1 | SETSSP | USES1 | USES2 } /* addv rm,rn */
1749};
1750
1751static const struct sh_minor_opcode sh_opcode3[] =
1752{
1753 { MAP (sh_opcode30), 0xf00f }
1754};
1755
1756static const struct sh_opcode sh_opcode40[] =
1757{
1758 { 0x4000, SETS1 | SETSSP | USES1 }, /* shll rn */
1759 { 0x4001, SETS1 | SETSSP | USES1 }, /* shlr rn */
1760 { 0x4002, STORE | SETS1 | USES1 | USESSP }, /* sts.l mach,@-rn */
252b5132
RH		 1761 { 0x4004, SETS1 | SETSSP | USES1 }, /* rotl rn */
1762 { 0x4005, SETS1 | SETSSP | USES1 }, /* rotr rn */
1763 { 0x4006, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,mach */
252b5132
RH		 1764 { 0x4008, SETS1 | USES1 }, /* shll2 rn */
1765 { 0x4009, SETS1 | USES1 }, /* shlr2 rn */
1766 { 0x400a, SETSSP | USES1 }, /* lds rm,mach */
1767 { 0x400b, BRANCH | DELAY | USES1 }, /* jsr @rn */
252b5132
RH		 1768 { 0x4010, SETS1 | SETSSP | USES1 }, /* dt rn */
1769 { 0x4011, SETSSP | USES1 }, /* cmp/pz rn */
1770 { 0x4012, STORE | SETS1 | USES1 | USESSP }, /* sts.l macl,@-rn */
d4845d57 1771 { 0x4014, SETSSP | USES1 }, /* setrc rm */
252b5132
RH		 1772 { 0x4015, SETSSP | USES1 }, /* cmp/pl rn */
1773 { 0x4016, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,macl */
252b5132
RH		 1774 { 0x4018, SETS1 | USES1 }, /* shll8 rn */
1775 { 0x4019, SETS1 | USES1 }, /* shlr8 rn */
1776 { 0x401a, SETSSP | USES1 }, /* lds rm,macl */
1777 { 0x401b, LOAD | SETSSP | USES1 }, /* tas.b @rn */
252b5132
RH		 1778 { 0x4020, SETS1 | SETSSP | USES1 }, /* shal rn */
1779 { 0x4021, SETS1 | SETSSP | USES1 }, /* shar rn */
1780 { 0x4022, STORE | SETS1 | USES1 | USESSP }, /* sts.l pr,@-rn */
252b5132
RH		 1781 { 0x4024, SETS1 | SETSSP | USES1 | USESSP }, /* rotcl rn */
1782 { 0x4025, SETS1 | SETSSP | USES1 | USESSP }, /* rotcr rn */
1783 { 0x4026, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,pr */
252b5132
RH		 1784 { 0x4028, SETS1 | USES1 }, /* shll16 rn */
1785 { 0x4029, SETS1 | USES1 }, /* shlr16 rn */
1786 { 0x402a, SETSSP | USES1 }, /* lds rm,pr */
1787 { 0x402b, BRANCH | DELAY | USES1 }, /* jmp @rn */
d4845d57
JR		 1788 { 0x4052, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpul,@-rn */
1789 { 0x4056, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpul */
1790 { 0x405a, SETSSP | USES1 }, /* lds.l rm,fpul */
1791 { 0x4062, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpscr / dsr,@-rn */
1792 { 0x4066, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpscr / dsr */
1793 { 0x406a, SETSSP | USES1 }, /* lds rm,fpscr / lds rm,dsr */
1794 { 0x4072, STORE | SETS1 | USES1 | USESSP }, /* sts.l a0,@-rn */
1795 { 0x4076, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,a0 */
1796 { 0x407a, SETSSP | USES1 }, /* lds.l rm,a0 */
1797 { 0x4082, STORE | SETS1 | USES1 | USESSP }, /* sts.l x0,@-rn */
1798 { 0x4086, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x0 */
1799 { 0x408a, SETSSP | USES1 }, /* lds.l rm,x0 */
1800 { 0x4092, STORE | SETS1 | USES1 | USESSP }, /* sts.l x1,@-rn */
1801 { 0x4096, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x1 */
1802 { 0x409a, SETSSP | USES1 }, /* lds.l rm,x1 */
1803 { 0x40a2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y0,@-rn */
1804 { 0x40a6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y0 */
1805 { 0x40aa, SETSSP | USES1 }, /* lds.l rm,y0 */
1806 { 0x40b2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y1,@-rn */
1807 { 0x40b6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y1 */
1808 { 0x40ba, SETSSP | USES1 } /* lds.l rm,y1 */
252b5132
RH		 1809};
1810
1811static const struct sh_opcode sh_opcode41[] =
1812{
d4845d57
JR		 1813 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l <special_reg>,@-rn */
1814 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,<special_reg> */
1815 { 0x400c, SETS1 | USES1 | USES2 }, /* shad rm,rn */
1816 { 0x400d, SETS1 | USES1 | USES2 }, /* shld rm,rn */
1817 { 0x400e, SETSSP | USES1 }, /* ldc rm,<special_reg> */
252b5132
RH		 1818 { 0x400f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.w @rm+,@rn+ */
1819};
1820
1821static const struct sh_minor_opcode sh_opcode4[] =
1822{
1823 { MAP (sh_opcode40), 0xf0ff },
d4845d57 1824 { MAP (sh_opcode41), 0xf00f }
252b5132
RH		 1825};
1826
1827static const struct sh_opcode sh_opcode50[] =
1828{
1829 { 0x5000, LOAD | SETS1 | USES2 } /* mov.l @(disp,rm),rn */
1830};
1831
1832static const struct sh_minor_opcode sh_opcode5[] =
1833{
1834 { MAP (sh_opcode50), 0xf000 }
1835};
1836
1837static const struct sh_opcode sh_opcode60[] =
1838{
1839 { 0x6000, LOAD | SETS1 | USES2 }, /* mov.b @rm,rn */
1840 { 0x6001, LOAD | SETS1 | USES2 }, /* mov.w @rm,rn */
1841 { 0x6002, LOAD | SETS1 | USES2 }, /* mov.l @rm,rn */
1842 { 0x6003, SETS1 | USES2 }, /* mov rm,rn */
1843 { 0x6004, LOAD | SETS1 | SETS2 | USES2 }, /* mov.b @rm+,rn */
1844 { 0x6005, LOAD | SETS1 | SETS2 | USES2 }, /* mov.w @rm+,rn */
1845 { 0x6006, LOAD | SETS1 | SETS2 | USES2 }, /* mov.l @rm+,rn */
1846 { 0x6007, SETS1 | USES2 }, /* not rm,rn */
1847 { 0x6008, SETS1 | USES2 }, /* swap.b rm,rn */
1848 { 0x6009, SETS1 | USES2 }, /* swap.w rm,rn */
1849 { 0x600a, SETS1 | SETSSP | USES2 | USESSP }, /* negc rm,rn */
1850 { 0x600b, SETS1 | USES2 }, /* neg rm,rn */
1851 { 0x600c, SETS1 | USES2 }, /* extu.b rm,rn */
1852 { 0x600d, SETS1 | USES2 }, /* extu.w rm,rn */
1853 { 0x600e, SETS1 | USES2 }, /* exts.b rm,rn */
1854 { 0x600f, SETS1 | USES2 } /* exts.w rm,rn */
1855};
1856
1857static const struct sh_minor_opcode sh_opcode6[] =
1858{
1859 { MAP (sh_opcode60), 0xf00f }
1860};
1861
1862static const struct sh_opcode sh_opcode70[] =
1863{
1864 { 0x7000, SETS1 | USES1 } /* add #imm,rn */
1865};
1866
1867static const struct sh_minor_opcode sh_opcode7[] =
1868{
1869 { MAP (sh_opcode70), 0xf000 }
1870};
1871
1872static const struct sh_opcode sh_opcode80[] =
1873{
1874 { 0x8000, STORE | USES2 | USESR0 }, /* mov.b r0,@(disp,rn) */
1875 { 0x8100, STORE | USES2 | USESR0 }, /* mov.w r0,@(disp,rn) */
d4845d57 1876 { 0x8200, SETSSP }, /* setrc #imm */
252b5132
RH		 1877 { 0x8400, LOAD | SETSR0 | USES2 }, /* mov.b @(disp,rm),r0 */
1878 { 0x8500, LOAD | SETSR0 | USES2 }, /* mov.w @(disp,rn),r0 */
1879 { 0x8800, SETSSP | USESR0 }, /* cmp/eq #imm,r0 */
1880 { 0x8900, BRANCH | USESSP }, /* bt label */
1881 { 0x8b00, BRANCH | USESSP }, /* bf label */
d4845d57 1882 { 0x8c00, SETSSP }, /* ldrs @(disp,pc) */
252b5132 1883 { 0x8d00, BRANCH | DELAY | USESSP }, /* bt/s label */
d4845d57 1884 { 0x8e00, SETSSP }, /* ldre @(disp,pc) */
252b5132
RH		 1885 { 0x8f00, BRANCH | DELAY | USESSP } /* bf/s label */
1886};
1887
1888static const struct sh_minor_opcode sh_opcode8[] =
1889{
1890 { MAP (sh_opcode80), 0xff00 }
1891};
1892
1893static const struct sh_opcode sh_opcode90[] =
1894{
1895 { 0x9000, LOAD | SETS1 } /* mov.w @(disp,pc),rn */
1896};
1897
1898static const struct sh_minor_opcode sh_opcode9[] =
1899{
1900 { MAP (sh_opcode90), 0xf000 }
1901};
1902
1903static const struct sh_opcode sh_opcodea0[] =
1904{
1905 { 0xa000, BRANCH | DELAY } /* bra label */
1906};
1907
1908static const struct sh_minor_opcode sh_opcodea[] =
1909{
1910 { MAP (sh_opcodea0), 0xf000 }
1911};
1912
1913static const struct sh_opcode sh_opcodeb0[] =
1914{
1915 { 0xb000, BRANCH | DELAY } /* bsr label */
1916};
1917
1918static const struct sh_minor_opcode sh_opcodeb[] =
1919{
1920 { MAP (sh_opcodeb0), 0xf000 }
1921};
1922
1923static const struct sh_opcode sh_opcodec0[] =
1924{
1925 { 0xc000, STORE | USESR0 | USESSP }, /* mov.b r0,@(disp,gbr) */
1926 { 0xc100, STORE | USESR0 | USESSP }, /* mov.w r0,@(disp,gbr) */
1927 { 0xc200, STORE | USESR0 | USESSP }, /* mov.l r0,@(disp,gbr) */
1928 { 0xc300, BRANCH | USESSP }, /* trapa #imm */
1929 { 0xc400, LOAD | SETSR0 | USESSP }, /* mov.b @(disp,gbr),r0 */
1930 { 0xc500, LOAD | SETSR0 | USESSP }, /* mov.w @(disp,gbr),r0 */
1931 { 0xc600, LOAD | SETSR0 | USESSP }, /* mov.l @(disp,gbr),r0 */
1932 { 0xc700, SETSR0 }, /* mova @(disp,pc),r0 */
1933 { 0xc800, SETSSP | USESR0 }, /* tst #imm,r0 */
1934 { 0xc900, SETSR0 | USESR0 }, /* and #imm,r0 */
1935 { 0xca00, SETSR0 | USESR0 }, /* xor #imm,r0 */
1936 { 0xcb00, SETSR0 | USESR0 }, /* or #imm,r0 */
1937 { 0xcc00, LOAD | SETSSP | USESR0 | USESSP }, /* tst.b #imm,@(r0,gbr) */
1938 { 0xcd00, LOAD | STORE | USESR0 | USESSP }, /* and.b #imm,@(r0,gbr) */
1939 { 0xce00, LOAD | STORE | USESR0 | USESSP }, /* xor.b #imm,@(r0,gbr) */
1940 { 0xcf00, LOAD | STORE | USESR0 | USESSP } /* or.b #imm,@(r0,gbr) */
1941};
1942
1943static const struct sh_minor_opcode sh_opcodec[] =
1944{
1945 { MAP (sh_opcodec0), 0xff00 }
1946};
1947
1948static const struct sh_opcode sh_opcoded0[] =
1949{
1950 { 0xd000, LOAD | SETS1 } /* mov.l @(disp,pc),rn */
1951};
1952
1953static const struct sh_minor_opcode sh_opcoded[] =
1954{
1955 { MAP (sh_opcoded0), 0xf000 }
1956};
1957
1958static const struct sh_opcode sh_opcodee0[] =
1959{
1960 { 0xe000, SETS1 } /* mov #imm,rn */
1961};
1962
1963static const struct sh_minor_opcode sh_opcodee[] =
1964{
1965 { MAP (sh_opcodee0), 0xf000 }
1966};
1967
1968static const struct sh_opcode sh_opcodef0[] =
1969{
1970 { 0xf000, SETSF1 | USESF1 | USESF2 }, /* fadd fm,fn */
1971 { 0xf001, SETSF1 | USESF1 | USESF2 }, /* fsub fm,fn */
1972 { 0xf002, SETSF1 | USESF1 | USESF2 }, /* fmul fm,fn */
1973 { 0xf003, SETSF1 | USESF1 | USESF2 }, /* fdiv fm,fn */
1974 { 0xf004, SETSSP | USESF1 | USESF2 }, /* fcmp/eq fm,fn */
1975 { 0xf005, SETSSP | USESF1 | USESF2 }, /* fcmp/gt fm,fn */
1976 { 0xf006, LOAD | SETSF1 | USES2 | USESR0 }, /* fmov.s @(r0,rm),fn */
1977 { 0xf007, STORE | USES1 | USESF2 | USESR0 }, /* fmov.s fm,@(r0,rn) */
1978 { 0xf008, LOAD | SETSF1 | USES2 }, /* fmov.s @rm,fn */
1979 { 0xf009, LOAD | SETS2 | SETSF1 | USES2 }, /* fmov.s @rm+,fn */
1980 { 0xf00a, STORE | USES1 | USESF2 }, /* fmov.s fm,@rn */
1981 { 0xf00b, STORE | SETS1 | USES1 | USESF2 }, /* fmov.s fm,@-rn */
1982 { 0xf00c, SETSF1 | USESF2 }, /* fmov fm,fn */
1983 { 0xf00e, SETSF1 | USESF1 | USESF2 | USESF0 } /* fmac f0,fm,fn */
1984};
1985
1986static const struct sh_opcode sh_opcodef1[] =
1987{
1988 { 0xf00d, SETSF1 | USESSP }, /* fsts fpul,fn */
1989 { 0xf01d, SETSSP | USESF1 }, /* flds fn,fpul */
1990 { 0xf02d, SETSF1 | USESSP }, /* float fpul,fn */
1991 { 0xf03d, SETSSP | USESF1 }, /* ftrc fn,fpul */
1992 { 0xf04d, SETSF1 | USESF1 }, /* fneg fn */
1993 { 0xf05d, SETSF1 | USESF1 }, /* fabs fn */
1994 { 0xf06d, SETSF1 | USESF1 }, /* fsqrt fn */
1995 { 0xf07d, SETSSP | USESF1 }, /* ftst/nan fn */
1996 { 0xf08d, SETSF1 }, /* fldi0 fn */
1997 { 0xf09d, SETSF1 } /* fldi1 fn */
1998};
1999
2000static const struct sh_minor_opcode sh_opcodef[] =
2001{
2002 { MAP (sh_opcodef0), 0xf00f },
2003 { MAP (sh_opcodef1), 0xf0ff }
2004};
2005
d4845d57 2006static struct sh_major_opcode sh_opcodes[] =
252b5132
RH		 2007{
2008 { MAP (sh_opcode0) },
2009 { MAP (sh_opcode1) },
2010 { MAP (sh_opcode2) },
2011 { MAP (sh_opcode3) },
2012 { MAP (sh_opcode4) },
2013 { MAP (sh_opcode5) },
2014 { MAP (sh_opcode6) },
2015 { MAP (sh_opcode7) },
2016 { MAP (sh_opcode8) },
2017 { MAP (sh_opcode9) },
2018 { MAP (sh_opcodea) },
2019 { MAP (sh_opcodeb) },
2020 { MAP (sh_opcodec) },
2021 { MAP (sh_opcoded) },
2022 { MAP (sh_opcodee) },
2023 { MAP (sh_opcodef) }
2024};
2025
d4845d57
JR		 2026/* The double data transfer / parallel processing insns are not
2027 described here. This will cause sh_align_load_span to leave them alone. */
2028
2029static const struct sh_opcode sh_dsp_opcodef0[] =
2030{
2031 { 0xf400, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @-as,ds */
2032 { 0xf401, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@-as */
2033 { 0xf404, USESAS | LOAD | SETSSP }, /* movs.x @as,ds */
2034 { 0xf405, USESAS | STORE | USESSP }, /* movs.x ds,@as */
2035 { 0xf408, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @as+,ds */
2036 { 0xf409, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@as+ */
2037 { 0xf40c, USESAS | SETSAS | LOAD | SETSSP | USESR8 }, /* movs.x @as+r8,ds */
2038 { 0xf40d, USESAS | SETSAS | STORE | USESSP | USESR8 } /* movs.x ds,@as+r8 */
2039};
2040
2041static const struct sh_minor_opcode sh_dsp_opcodef[] =
2042{
2043 { MAP (sh_dsp_opcodef0), 0xfc0d }
2044};
2045
252b5132
RH		 2046/* Given an instruction, return a pointer to the corresponding
2047 sh_opcode structure. Return NULL if the instruction is not
2048 recognized. */
2049
2050static const struct sh_opcode *
2051sh_insn_info (insn)
2052 unsigned int insn;
2053{
2054 const struct sh_major_opcode *maj;
2055 const struct sh_minor_opcode *min, *minend;
2056
2057 maj = &sh_opcodes[(insn & 0xf000) >> 12];
2058 min = maj->minor_opcodes;
2059 minend = min + maj->count;
2060 for (; min < minend; min++)
2061 {
2062 unsigned int l;
2063 const struct sh_opcode *op, *opend;
2064
2065 l = insn & min->mask;
2066 op = min->opcodes;
2067 opend = op + min->count;
2068
2069 /* Since the opcodes tables are sorted, we could use a binary
2070 search here if the count were above some cutoff value. */
2071 for (; op < opend; op++)
2072 if (op->opcode == l)
2073 return op;
2074 }
2075
cbfe05c4 2076 return NULL;
252b5132
RH		 2077}
2078
84dcfba7
JR		 2079/* See whether an instruction uses or sets a general purpose register */
2080
b34976b6 2081static bfd_boolean
84dcfba7
JR		 2082sh_insn_uses_or_sets_reg (insn, op, reg)
2083 unsigned int insn;
2084 const struct sh_opcode *op;
2085 unsigned int reg;
2086{
2087 if (sh_insn_uses_reg (insn, op, reg))
b34976b6 2088 return TRUE;
84dcfba7
JR		 2089
2090 return sh_insn_sets_reg (insn, op, reg);
2091}
2092
252b5132
RH		 2093/* See whether an instruction uses a general purpose register. */
2094
b34976b6 2095static bfd_boolean
252b5132
RH		 2096sh_insn_uses_reg (insn, op, reg)
2097 unsigned int insn;
2098 const struct sh_opcode *op;
2099 unsigned int reg;
2100{
2101 unsigned int f;
2102
2103 f = op->flags;
2104
2105 if ((f & USES1) != 0
84dcfba7 2106 && USES1_REG (insn) == reg)
b34976b6 2107 return TRUE;
252b5132 2108 if ((f & USES2) != 0
84dcfba7 2109 && USES2_REG (insn) == reg)
b34976b6 2110 return TRUE;
252b5132
RH		 2111 if ((f & USESR0) != 0
2112 && reg == 0)
b34976b6 2113 return TRUE;
d4845d57 2114 if ((f & USESAS) && reg == USESAS_REG (insn))
b34976b6 2115 return TRUE;
d4845d57 2116 if ((f & USESR8) && reg == 8)
b34976b6 2117 return TRUE;
252b5132 2118
b34976b6 2119 return FALSE;
252b5132 2120}
17505c5c 2121
84dcfba7
JR		 2122/* See whether an instruction sets a general purpose register. */
2123
b34976b6 2124static bfd_boolean
84dcfba7
JR		 2125sh_insn_sets_reg (insn, op, reg)
2126 unsigned int insn;
2127 const struct sh_opcode *op;
2128 unsigned int reg;
2129{
2130 unsigned int f;
2131
2132 f = op->flags;
2133
2134 if ((f & SETS1) != 0
2135 && SETS1_REG (insn) == reg)
b34976b6 2136 return TRUE;
84dcfba7
JR		 2137 if ((f & SETS2) != 0
2138 && SETS2_REG (insn) == reg)
b34976b6 2139 return TRUE;
84dcfba7
JR		 2140 if ((f & SETSR0) != 0
2141 && reg == 0)
b34976b6 2142 return TRUE;
d4845d57 2143 if ((f & SETSAS) && reg == SETSAS_REG (insn))
b34976b6 2144 return TRUE;
84dcfba7 2145
b34976b6 2146 return FALSE;
84dcfba7
JR		 2147}
2148
2149/* See whether an instruction uses or sets a floating point register */
2150
b34976b6 2151static bfd_boolean
84dcfba7
JR		 2152sh_insn_uses_or_sets_freg (insn, op, reg)
2153 unsigned int insn;
2154 const struct sh_opcode *op;
2155 unsigned int reg;
2156{
2157 if (sh_insn_uses_freg (insn, op, reg))
b34976b6 2158 return TRUE;
84dcfba7
JR		 2159
2160 return sh_insn_sets_freg (insn, op, reg);
2161}
252b5132
RH		 2162
2163/* See whether an instruction uses a floating point register. */
2164
b34976b6 2165static bfd_boolean
252b5132
RH		 2166sh_insn_uses_freg (insn, op, freg)
2167 unsigned int insn;
2168 const struct sh_opcode *op;
2169 unsigned int freg;
2170{
2171 unsigned int f;
2172
2173 f = op->flags;
2174
2175 /* We can't tell if this is a double-precision insn, so just play safe
2176 and assume that it might be. So not only have we test FREG against
2177 itself, but also even FREG against FREG+1 - if the using insn uses
2178 just the low part of a double precision value - but also an odd
2179 FREG against FREG-1 - if the setting insn sets just the low part
2180 of a double precision value.
2181 So what this all boils down to is that we have to ignore the lowest
2182 bit of the register number. */
cbfe05c4 2183
252b5132 2184 if ((f & USESF1) != 0
84dcfba7 2185 && (USESF1_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2186 return TRUE;
252b5132 2187 if ((f & USESF2) != 0
84dcfba7 2188 && (USESF2_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2189 return TRUE;
252b5132
RH		 2190 if ((f & USESF0) != 0
2191 && freg == 0)
b34976b6 2192 return TRUE;
252b5132 2193
b34976b6 2194 return FALSE;
252b5132
RH		 2195}
2196
84dcfba7
JR		 2197/* See whether an instruction sets a floating point register. */
2198
b34976b6 2199static bfd_boolean
84dcfba7
JR		 2200sh_insn_sets_freg (insn, op, freg)
2201 unsigned int insn;
2202 const struct sh_opcode *op;
2203 unsigned int freg;
2204{
2205 unsigned int f;
2206
2207 f = op->flags;
2208
2209 /* We can't tell if this is a double-precision insn, so just play safe
2210 and assume that it might be. So not only have we test FREG against
2211 itself, but also even FREG against FREG+1 - if the using insn uses
2212 just the low part of a double precision value - but also an odd
2213 FREG against FREG-1 - if the setting insn sets just the low part
2214 of a double precision value.
2215 So what this all boils down to is that we have to ignore the lowest
2216 bit of the register number. */
cbfe05c4 2217
84dcfba7
JR		 2218 if ((f & SETSF1) != 0
2219 && (SETSF1_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2220 return TRUE;
84dcfba7 2221
b34976b6 2222 return FALSE;
84dcfba7
JR		 2223}
2224
252b5132
RH		 2225/* See whether instructions I1 and I2 conflict, assuming I1 comes
2226 before I2. OP1 and OP2 are the corresponding sh_opcode structures.
b34976b6 2227 This should return TRUE if there is a conflict, or FALSE if the
252b5132
RH		 2228 instructions can be swapped safely. */
2229
b34976b6 2230static bfd_boolean
252b5132
RH		 2231sh_insns_conflict (i1, op1, i2, op2)
2232 unsigned int i1;
2233 const struct sh_opcode *op1;
2234 unsigned int i2;
2235 const struct sh_opcode *op2;
2236{
2237 unsigned int f1, f2;
2238
2239 f1 = op1->flags;
2240 f2 = op2->flags;
2241
2242 /* Load of fpscr conflicts with floating point operations.
2243 FIXME: shouldn't test raw opcodes here. */
2244 if (((i1 & 0xf0ff) == 0x4066 && (i2 & 0xf000) == 0xf000)
2245 || ((i2 & 0xf0ff) == 0x4066 && (i1 & 0xf000) == 0xf000))
b34976b6 2246 return TRUE;
252b5132
RH		 2247
2248 if ((f1 & (BRANCH | DELAY)) != 0
2249 || (f2 & (BRANCH | DELAY)) != 0)
b34976b6 2250 return TRUE;
252b5132 2251
84dcfba7
JR		 2252 if (((f1 | f2) & SETSSP)
2253 && (f1 & (SETSSP | USESSP))
2254 && (f2 & (SETSSP | USESSP)))
b34976b6 2255 return TRUE;
252b5132
RH		 2256
2257 if ((f1 & SETS1) != 0
84dcfba7 2258 && sh_insn_uses_or_sets_reg (i2, op2, SETS1_REG (i1)))
b34976b6 2259 return TRUE;
252b5132 2260 if ((f1 & SETS2) != 0
84dcfba7 2261 && sh_insn_uses_or_sets_reg (i2, op2, SETS2_REG (i1)))
b34976b6 2262 return TRUE;
252b5132 2263 if ((f1 & SETSR0) != 0
84dcfba7 2264 && sh_insn_uses_or_sets_reg (i2, op2, 0))
b34976b6 2265 return TRUE;
d4845d57
JR		 2266 if ((f1 & SETSAS)
2267 && sh_insn_uses_or_sets_reg (i2, op2, SETSAS_REG (i1)))
b34976b6 2268 return TRUE;
252b5132 2269 if ((f1 & SETSF1) != 0
84dcfba7 2270 && sh_insn_uses_or_sets_freg (i2, op2, SETSF1_REG (i1)))
b34976b6 2271 return TRUE;
252b5132
RH		 2272
2273 if ((f2 & SETS1) != 0
84dcfba7 2274 && sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2)))
b34976b6 2275 return TRUE;
252b5132 2276 if ((f2 & SETS2) != 0
84dcfba7 2277 && sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2)))
b34976b6 2278 return TRUE;
252b5132 2279 if ((f2 & SETSR0) != 0
84dcfba7 2280 && sh_insn_uses_or_sets_reg (i1, op1, 0))
b34976b6 2281 return TRUE;
d4845d57
JR		 2282 if ((f2 & SETSAS)
2283 && sh_insn_uses_or_sets_reg (i1, op1, SETSAS_REG (i2)))
b34976b6 2284 return TRUE;
252b5132 2285 if ((f2 & SETSF1) != 0
84dcfba7 2286 && sh_insn_uses_or_sets_freg (i1, op1, SETSF1_REG (i2)))
b34976b6 2287 return TRUE;
252b5132
RH		 2288
2289 /* The instructions do not conflict. */
b34976b6 2290 return FALSE;
252b5132
RH		 2291}
2292
2293/* I1 is a load instruction, and I2 is some other instruction. Return
b34976b6 2294 TRUE if I1 loads a register which I2 uses. */
252b5132 2295
b34976b6 2296static bfd_boolean
252b5132
RH		 2297sh_load_use (i1, op1, i2, op2)
2298 unsigned int i1;
2299 const struct sh_opcode *op1;
2300 unsigned int i2;
2301 const struct sh_opcode *op2;
2302{
2303 unsigned int f1;
2304
2305 f1 = op1->flags;
2306
2307 if ((f1 & LOAD) == 0)
b34976b6 2308 return FALSE;
252b5132
RH		 2309
2310 /* If both SETS1 and SETSSP are set, that means a load to a special
2311 register using postincrement addressing mode, which we don't care
2312 about here. */
2313 if ((f1 & SETS1) != 0
2314 && (f1 & SETSSP) == 0
2315 && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
b34976b6 2316 return TRUE;
252b5132
RH		 2317
2318 if ((f1 & SETSR0) != 0
2319 && sh_insn_uses_reg (i2, op2, 0))
b34976b6 2320 return TRUE;
252b5132
RH		 2321
2322 if ((f1 & SETSF1) != 0
2323 && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
b34976b6 2324 return TRUE;
252b5132 2325
b34976b6 2326 return FALSE;
252b5132
RH		 2327}
2328
2329/* Try to align loads and stores within a span of memory. This is
2330 called by both the ELF and the COFF sh targets. ABFD and SEC are
2331 the BFD and section we are examining. CONTENTS is the contents of
2332 the section. SWAP is the routine to call to swap two instructions.
2333 RELOCS is a pointer to the internal relocation information, to be
2334 passed to SWAP. PLABEL is a pointer to the current label in a
2335 sorted list of labels; LABEL_END is the end of the list. START and
2336 STOP are the range of memory to examine. If a swap is made,
b34976b6 2337 *PSWAPPED is set to TRUE. */
252b5132 2338
86033394
NC		 2339#ifdef COFF_WITH_PE
2340static
2341#endif
b34976b6 2342bfd_boolean
252b5132
RH		 2343_bfd_sh_align_load_span (abfd, sec, contents, swap, relocs,
2344 plabel, label_end, start, stop, pswapped)
2345 bfd *abfd;
2346 asection *sec;
2347 bfd_byte *contents;
b34976b6 2348 bfd_boolean (*swap) PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
252b5132
RH		 2349 PTR relocs;
2350 bfd_vma **plabel;
2351 bfd_vma *label_end;
2352 bfd_vma start;
2353 bfd_vma stop;
b34976b6 2354 bfd_boolean *pswapped;
252b5132 2355{
d4845d57
JR		 2356 int dsp = (abfd->arch_info->mach == bfd_mach_sh_dsp
2357 || abfd->arch_info->mach == bfd_mach_sh3_dsp);
252b5132
RH		 2358 bfd_vma i;
2359
d4845d57
JR		 2360 /* The SH4 has a Harvard architecture, hence aligning loads is not
2361 desirable. In fact, it is counter-productive, since it interferes
2362 with the schedules generated by the compiler. */
2363 if (abfd->arch_info->mach == bfd_mach_sh4)
b34976b6 2364 return TRUE;
d4845d57
JR		 2365
2366 /* If we are linking sh[3]-dsp code, swap the FPU instructions for DSP
2367 instructions. */
2368 if (dsp)
2369 {
2370 sh_opcodes[0xf].minor_opcodes = sh_dsp_opcodef;
2371 sh_opcodes[0xf].count = sizeof sh_dsp_opcodef / sizeof sh_dsp_opcodef;
2372 }
2373
252b5132
RH		 2374 /* Instructions should be aligned on 2 byte boundaries. */
2375 if ((start & 1) == 1)
2376 ++start;
2377
2378 /* Now look through the unaligned addresses. */
2379 i = start;
2380 if ((i & 2) == 0)
2381 i += 2;
2382 for (; i < stop; i += 4)
2383 {
2384 unsigned int insn;
2385 const struct sh_opcode *op;
2386 unsigned int prev_insn = 0;
2387 const struct sh_opcode *prev_op = NULL;
2388
2389 insn = bfd_get_16 (abfd, contents + i);
2390 op = sh_insn_info (insn);
2391 if (op == NULL
2392 || (op->flags & (LOAD | STORE)) == 0)
2393 continue;
2394
2395 /* This is a load or store which is not on a four byte boundary. */
2396
2397 while (*plabel < label_end && **plabel < i)
2398 ++*plabel;
2399
2400 if (i > start)
2401 {
2402 prev_insn = bfd_get_16 (abfd, contents + i - 2);
d4845d57
JR		 2403 /* If INSN is the field b of a parallel processing insn, it is not
2404 a load / store after all. Note that the test here might mistake
2405 the field_b of a pcopy insn for the starting code of a parallel
2406 processing insn; this might miss a swapping opportunity, but at
2407 least we're on the safe side. */
2408 if (dsp && (prev_insn & 0xfc00) == 0xf800)
2409 continue;
2410
2411 /* Check if prev_insn is actually the field b of a parallel
2412 processing insn. Again, this can give a spurious match
2413 after a pcopy. */
2414 if (dsp && i - 2 > start)
2415 {
2416 unsigned pprev_insn = bfd_get_16 (abfd, contents + i - 4);
cbfe05c4 2417
d4845d57
JR		 2418 if ((pprev_insn & 0xfc00) == 0xf800)
2419 prev_op = NULL;
2420 else
2421 prev_op = sh_insn_info (prev_insn);
2422 }
2423 else
2424 prev_op = sh_insn_info (prev_insn);
252b5132
RH		 2425
2426 /* If the load/store instruction is in a delay slot, we
2427 can't swap. */
2428 if (prev_op == NULL
2429 || (prev_op->flags & DELAY) != 0)
2430 continue;
2431 }
2432 if (i > start
2433 && (*plabel >= label_end || **plabel != i)
2434 && prev_op != NULL
2435 && (prev_op->flags & (LOAD | STORE)) == 0
2436 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2437 {
b34976b6 2438 bfd_boolean ok;
252b5132
RH		 2439
2440 /* The load/store instruction does not have a label, and
2441 there is a previous instruction; PREV_INSN is not
2442 itself a load/store instruction, and PREV_INSN and
2443 INSN do not conflict. */
2444
b34976b6 2445 ok = TRUE;
252b5132
RH		 2446
2447 if (i >= start + 4)
2448 {
2449 unsigned int prev2_insn;
2450 const struct sh_opcode *prev2_op;
2451
2452 prev2_insn = bfd_get_16 (abfd, contents + i - 4);
2453 prev2_op = sh_insn_info (prev2_insn);
2454
2455 /* If the instruction before PREV_INSN has a delay
2456 slot--that is, PREV_INSN is in a delay slot--we
2457 can not swap. */
2458 if (prev2_op == NULL
2459 || (prev2_op->flags & DELAY) != 0)
b34976b6 2460 ok = FALSE;
252b5132
RH		 2461
2462 /* If the instruction before PREV_INSN is a load,
2463 and it sets a register which INSN uses, then
2464 putting INSN immediately after PREV_INSN will
2465 cause a pipeline bubble, so there is no point to
2466 making the swap. */
2467 if (ok
2468 && (prev2_op->flags & LOAD) != 0
2469 && sh_load_use (prev2_insn, prev2_op, insn, op))
b34976b6 2470 ok = FALSE;
252b5132
RH		 2471 }
2472
2473 if (ok)
2474 {
2475 if (! (*swap) (abfd, sec, relocs, contents, i - 2))
b34976b6
AM		 2476 return FALSE;
2477 *pswapped = TRUE;
252b5132
RH		 2478 continue;
2479 }
2480 }
2481
2482 while (*plabel < label_end && **plabel < i + 2)
2483 ++*plabel;
2484
2485 if (i + 2 < stop
2486 && (*plabel >= label_end || **plabel != i + 2))
2487 {
2488 unsigned int next_insn;
2489 const struct sh_opcode *next_op;
2490
2491 /* There is an instruction after the load/store
2492 instruction, and it does not have a label. */
2493 next_insn = bfd_get_16 (abfd, contents + i + 2);
2494 next_op = sh_insn_info (next_insn);
2495 if (next_op != NULL
2496 && (next_op->flags & (LOAD | STORE)) == 0
2497 && ! sh_insns_conflict (insn, op, next_insn, next_op))
2498 {
b34976b6 2499 bfd_boolean ok;
252b5132
RH		 2500
2501 /* NEXT_INSN is not itself a load/store instruction,
2502 and it does not conflict with INSN. */
2503
b34976b6 2504 ok = TRUE;
252b5132
RH		 2505
2506 /* If PREV_INSN is a load, and it sets a register
2507 which NEXT_INSN uses, then putting NEXT_INSN
2508 immediately after PREV_INSN will cause a pipeline
2509 bubble, so there is no reason to make this swap. */
2510 if (prev_op != NULL
2511 && (prev_op->flags & LOAD) != 0
2512 && sh_load_use (prev_insn, prev_op, next_insn, next_op))
b34976b6 2513 ok = FALSE;
252b5132
RH		 2514
2515 /* If INSN is a load, and it sets a register which
2516 the insn after NEXT_INSN uses, then doing the
2517 swap will cause a pipeline bubble, so there is no
2518 reason to make the swap. However, if the insn
2519 after NEXT_INSN is itself a load or store
2520 instruction, then it is misaligned, so
2521 optimistically hope that it will be swapped
2522 itself, and just live with the pipeline bubble if
2523 it isn't. */
2524 if (ok
2525 && i + 4 < stop
2526 && (op->flags & LOAD) != 0)
2527 {
2528 unsigned int next2_insn;
2529 const struct sh_opcode *next2_op;
2530
2531 next2_insn = bfd_get_16 (abfd, contents + i + 4);
2532 next2_op = sh_insn_info (next2_insn);
230d6d81
NC		 2533 if (next2_op == NULL
2534 || ((next2_op->flags & (LOAD | STORE)) == 0
2535 && sh_load_use (insn, op, next2_insn, next2_op)))
b34976b6 2536 ok = FALSE;
252b5132
RH		 2537 }
2538
2539 if (ok)
2540 {
2541 if (! (*swap) (abfd, sec, relocs, contents, i))
b34976b6
AM		 2542 return FALSE;
2543 *pswapped = TRUE;
252b5132
RH		 2544 continue;
2545 }
2546 }
2547 }
2548 }
2549
b34976b6 2550 return TRUE;
252b5132 2551}
86033394 2552#endif /* not COFF_IMAGE_WITH_PE */
252b5132
RH		 2553
2554/* Look for loads and stores which we can align to four byte
2555 boundaries. See the longer comment above sh_relax_section for why
2556 this is desirable. This sets *PSWAPPED if some instruction was
2557 swapped. */
2558
b34976b6 2559static bfd_boolean
252b5132
RH		 2560sh_align_loads (abfd, sec, internal_relocs, contents, pswapped)
2561 bfd *abfd;
2562 asection *sec;
2563 struct internal_reloc *internal_relocs;
2564 bfd_byte *contents;
b34976b6 2565 bfd_boolean *pswapped;
252b5132
RH		 2566{
2567 struct internal_reloc *irel, *irelend;
2568 bfd_vma *labels = NULL;
2569 bfd_vma *label, *label_end;
dc810e39 2570 bfd_size_type amt;
252b5132 2571
b34976b6 2572 *pswapped = FALSE;
252b5132
RH		 2573
2574 irelend = internal_relocs + sec->reloc_count;
2575
2576 /* Get all the addresses with labels on them. */
dc810e39
AM		 2577 amt = (bfd_size_type) sec->reloc_count * sizeof (bfd_vma);
2578 labels = (bfd_vma *) bfd_malloc (amt);
252b5132
RH		 2579 if (labels == NULL)
2580 goto error_return;
2581 label_end = labels;
2582 for (irel = internal_relocs; irel < irelend; irel++)
2583 {
2584 if (irel->r_type == R_SH_LABEL)
2585 {
2586 *label_end = irel->r_vaddr - sec->vma;
2587 ++label_end;
2588 }
2589 }
2590
2591 /* Note that the assembler currently always outputs relocs in
2592 address order. If that ever changes, this code will need to sort
2593 the label values and the relocs. */
2594
2595 label = labels;
2596
2597 for (irel = internal_relocs; irel < irelend; irel++)
2598 {
2599 bfd_vma start, stop;
2600
2601 if (irel->r_type != R_SH_CODE)
2602 continue;
2603
2604 start = irel->r_vaddr - sec->vma;
2605
2606 for (irel++; irel < irelend; irel++)
2607 if (irel->r_type == R_SH_DATA)
2608 break;
2609 if (irel < irelend)
2610 stop = irel->r_vaddr - sec->vma;
2611 else
eea6121a 2612 stop = sec->size;
252b5132
RH		 2613
2614 if (! _bfd_sh_align_load_span (abfd, sec, contents, sh_swap_insns,
2615 (PTR) internal_relocs, &label,
2616 label_end, start, stop, pswapped))
2617 goto error_return;
2618 }
2619
2620 free (labels);
2621
b34976b6 2622 return TRUE;
252b5132
RH		 2623
2624 error_return:
2625 if (labels != NULL)
2626 free (labels);
b34976b6 2627 return FALSE;
252b5132
RH		 2628}
2629
2630/* Swap two SH instructions. */
2631
b34976b6 2632static bfd_boolean
252b5132
RH		 2633sh_swap_insns (abfd, sec, relocs, contents, addr)
2634 bfd *abfd;
2635 asection *sec;
2636 PTR relocs;
2637 bfd_byte *contents;
2638 bfd_vma addr;
2639{
2640 struct internal_reloc *internal_relocs = (struct internal_reloc *) relocs;
2641 unsigned short i1, i2;
2642 struct internal_reloc *irel, *irelend;
2643
2644 /* Swap the instructions themselves. */
2645 i1 = bfd_get_16 (abfd, contents + addr);
2646 i2 = bfd_get_16 (abfd, contents + addr + 2);
dc810e39
AM		 2647 bfd_put_16 (abfd, (bfd_vma) i2, contents + addr);
2648 bfd_put_16 (abfd, (bfd_vma) i1, contents + addr + 2);
252b5132
RH		 2649
2650 /* Adjust all reloc addresses. */
2651 irelend = internal_relocs + sec->reloc_count;
2652 for (irel = internal_relocs; irel < irelend; irel++)
2653 {
2654 int type, add;
2655
2656 /* There are a few special types of relocs that we don't want to
2657 adjust. These relocs do not apply to the instruction itself,
2658 but are only associated with the address. */
2659 type = irel->r_type;
2660 if (type == R_SH_ALIGN
2661 || type == R_SH_CODE
2662 || type == R_SH_DATA
2663 || type == R_SH_LABEL)
2664 continue;
2665
2666 /* If an R_SH_USES reloc points to one of the addresses being
2667 swapped, we must adjust it. It would be incorrect to do this
2668 for a jump, though, since we want to execute both
2669 instructions after the jump. (We have avoided swapping
2670 around a label, so the jump will not wind up executing an
2671 instruction it shouldn't). */
2672 if (type == R_SH_USES)
2673 {
2674 bfd_vma off;
2675
2676 off = irel->r_vaddr - sec->vma + 4 + irel->r_offset;
2677 if (off == addr)
2678 irel->r_offset += 2;
2679 else if (off == addr + 2)
2680 irel->r_offset -= 2;
2681 }
2682
2683 if (irel->r_vaddr - sec->vma == addr)
2684 {
2685 irel->r_vaddr += 2;
2686 add = -2;
2687 }
2688 else if (irel->r_vaddr - sec->vma == addr + 2)
2689 {
2690 irel->r_vaddr -= 2;
2691 add = 2;
2692 }
2693 else
2694 add = 0;
2695
2696 if (add != 0)
2697 {
2698 bfd_byte *loc;
2699 unsigned short insn, oinsn;
b34976b6 2700 bfd_boolean overflow;
252b5132
RH		 2701
2702 loc = contents + irel->r_vaddr - sec->vma;
b34976b6 2703 overflow = FALSE;
252b5132
RH		 2704 switch (type)
2705 {
2706 default:
2707 break;
2708
2709 case R_SH_PCDISP8BY2:
2710 case R_SH_PCRELIMM8BY2:
2711 insn = bfd_get_16 (abfd, loc);
2712 oinsn = insn;
2713 insn += add / 2;
2714 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 2715 overflow = TRUE;
dc810e39 2716 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2717 break;
2718
2719 case R_SH_PCDISP:
2720 insn = bfd_get_16 (abfd, loc);
2721 oinsn = insn;
2722 insn += add / 2;
2723 if ((oinsn & 0xf000) != (insn & 0xf000))
b34976b6 2724 overflow = TRUE;
dc810e39 2725 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2726 break;
2727
2728 case R_SH_PCRELIMM8BY4:
2729 /* This reloc ignores the least significant 3 bits of
2730 the program counter before adding in the offset.
2731 This means that if ADDR is at an even address, the
2732 swap will not affect the offset. If ADDR is an at an
2733 odd address, then the instruction will be crossing a
2734 four byte boundary, and must be adjusted. */
2735 if ((addr & 3) != 0)
2736 {
2737 insn = bfd_get_16 (abfd, loc);
2738 oinsn = insn;
2739 insn += add / 2;
2740 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 2741 overflow = TRUE;
dc810e39 2742 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2743 }
2744
2745 break;
2746 }
2747
2748 if (overflow)
2749 {
2750 ((*_bfd_error_handler)
d003868e
AM		 2751 ("%B: 0x%lx: fatal: reloc overflow while relaxing",
2752 abfd, (unsigned long) irel->r_vaddr));
252b5132 2753 bfd_set_error (bfd_error_bad_value);
b34976b6 2754 return FALSE;
252b5132
RH		 2755 }
2756 }
2757 }
2758
b34976b6 2759 return TRUE;
252b5132
RH		 2760}
2761\f
2762/* This is a modification of _bfd_coff_generic_relocate_section, which
2763 will handle SH relaxing. */
2764
b34976b6 2765static bfd_boolean
252b5132
RH		 2766sh_relocate_section (output_bfd, info, input_bfd, input_section, contents,
2767 relocs, syms, sections)
5f771d47 2768 bfd *output_bfd ATTRIBUTE_UNUSED;
252b5132
RH		 2769 struct bfd_link_info *info;
2770 bfd *input_bfd;
2771 asection *input_section;
2772 bfd_byte *contents;
2773 struct internal_reloc *relocs;
2774 struct internal_syment *syms;
2775 asection **sections;
2776{
2777 struct internal_reloc *rel;
2778 struct internal_reloc *relend;
2779
2780 rel = relocs;
2781 relend = rel + input_section->reloc_count;
2782 for (; rel < relend; rel++)
2783 {
2784 long symndx;
2785 struct coff_link_hash_entry *h;
2786 struct internal_syment *sym;
2787 bfd_vma addend;
2788 bfd_vma val;
2789 reloc_howto_type *howto;
2790 bfd_reloc_status_type rstat;
2791
2792 /* Almost all relocs have to do with relaxing. If any work must
2793 be done for them, it has been done in sh_relax_section. */
2794 if (rel->r_type != R_SH_IMM32
17505c5c
NC		 2795#ifdef COFF_WITH_PE
2796 && rel->r_type != R_SH_IMM32CE
2797 && rel->r_type != R_SH_IMAGEBASE
2798#endif
252b5132
RH		 2799 && rel->r_type != R_SH_PCDISP)
2800 continue;
2801
2802 symndx = rel->r_symndx;
2803
2804 if (symndx == -1)
2805 {
2806 h = NULL;
2807 sym = NULL;
2808 }
2809 else
cbfe05c4 2810 {
252b5132
RH		 2811 if (symndx < 0
2812 || (unsigned long) symndx >= obj_raw_syment_count (input_bfd))
2813 {
2814 (*_bfd_error_handler)
d003868e
AM		 2815 ("%B: illegal symbol index %ld in relocs",
2816 input_bfd, symndx);
252b5132 2817 bfd_set_error (bfd_error_bad_value);
b34976b6 2818 return FALSE;
252b5132
RH		 2819 }
2820 h = obj_coff_sym_hashes (input_bfd)[symndx];
2821 sym = syms + symndx;
2822 }
2823
2824 if (sym != NULL && sym->n_scnum != 0)
2825 addend = - sym->n_value;
2826 else
2827 addend = 0;
2828
2829 if (rel->r_type == R_SH_PCDISP)
2830 addend -= 4;
2831
2832 if (rel->r_type >= SH_COFF_HOWTO_COUNT)
2833 howto = NULL;
2834 else
2835 howto = &sh_coff_howtos[rel->r_type];
2836
2837 if (howto == NULL)
2838 {
2839 bfd_set_error (bfd_error_bad_value);
b34976b6 2840 return FALSE;
252b5132
RH		 2841 }
2842
17505c5c
NC		 2843#ifdef COFF_WITH_PE
2844 if (rel->r_type == R_SH_IMAGEBASE)
2845 addend -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
2846#endif
cbfe05c4 2847
252b5132
RH		 2848 val = 0;
2849
2850 if (h == NULL)
2851 {
2852 asection *sec;
2853
2854 /* There is nothing to do for an internal PCDISP reloc. */
2855 if (rel->r_type == R_SH_PCDISP)
2856 continue;
2857
2858 if (symndx == -1)
2859 {
2860 sec = bfd_abs_section_ptr;
2861 val = 0;
2862 }
2863 else
2864 {
2865 sec = sections[symndx];
2866 val = (sec->output_section->vma
2867 + sec->output_offset
2868 + sym->n_value
2869 - sec->vma);
2870 }
2871 }
2872 else
2873 {
2874 if (h->root.type == bfd_link_hash_defined
2875 || h->root.type == bfd_link_hash_defweak)
2876 {
2877 asection *sec;
2878
2879 sec = h->root.u.def.section;
2880 val = (h->root.u.def.value
2881 + sec->output_section->vma
2882 + sec->output_offset);
2883 }
1049f94e 2884 else if (! info->relocatable)
252b5132
RH		 2885 {
2886 if (! ((*info->callbacks->undefined_symbol)
2887 (info, h->root.root.string, input_bfd, input_section,
b34976b6
AM		 2888 rel->r_vaddr - input_section->vma, TRUE)))
2889 return FALSE;
252b5132
RH		 2890 }
2891 }
2892
2893 rstat = _bfd_final_link_relocate (howto, input_bfd, input_section,
2894 contents,
2895 rel->r_vaddr - input_section->vma,
2896 val, addend);
2897
2898 switch (rstat)
2899 {
2900 default:
2901 abort ();
2902 case bfd_reloc_ok:
2903 break;
2904 case bfd_reloc_overflow:
2905 {
2906 const char *name;
2907 char buf[SYMNMLEN + 1];
2908
2909 if (symndx == -1)
2910 name = "*ABS*";
2911 else if (h != NULL)
dfeffb9f 2912 name = NULL;
252b5132
RH		 2913 else if (sym->_n._n_n._n_zeroes == 0
2914 && sym->_n._n_n._n_offset != 0)
2915 name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset;
2916 else
2917 {
2918 strncpy (buf, sym->_n._n_name, SYMNMLEN);
2919 buf[SYMNMLEN] = '\0';
2920 name = buf;
2921 }
2922
2923 if (! ((*info->callbacks->reloc_overflow)
dfeffb9f
L		 2924 (info, (h ? &h->root : NULL), name, howto->name,
2925 (bfd_vma) 0, input_bfd, input_section,
2926 rel->r_vaddr - input_section->vma)))
b34976b6 2927 return FALSE;
252b5132
RH		 2928 }
2929 }
2930 }
2931
b34976b6 2932 return TRUE;
252b5132
RH		 2933}
2934
2935/* This is a version of bfd_generic_get_relocated_section_contents
2936 which uses sh_relocate_section. */
2937
2938static bfd_byte *
2939sh_coff_get_relocated_section_contents (output_bfd, link_info, link_order,
1049f94e 2940 data, relocatable, symbols)
252b5132
RH		 2941 bfd *output_bfd;
2942 struct bfd_link_info *link_info;
2943 struct bfd_link_order *link_order;
2944 bfd_byte *data;
1049f94e 2945 bfd_boolean relocatable;
252b5132
RH		 2946 asymbol **symbols;
2947{
2948 asection *input_section = link_order->u.indirect.section;
2949 bfd *input_bfd = input_section->owner;
2950 asection **sections = NULL;
2951 struct internal_reloc *internal_relocs = NULL;
2952 struct internal_syment *internal_syms = NULL;
2953
2954 /* We only need to handle the case of relaxing, or of having a
2955 particular set of section contents, specially. */
1049f94e 2956 if (relocatable
252b5132
RH		 2957 || coff_section_data (input_bfd, input_section) == NULL
2958 || coff_section_data (input_bfd, input_section)->contents == NULL)
2959 return bfd_generic_get_relocated_section_contents (output_bfd, link_info,
2960 link_order, data,
1049f94e 2961 relocatable,
252b5132
RH		 2962 symbols);
2963
2964 memcpy (data, coff_section_data (input_bfd, input_section)->contents,
eea6121a 2965 (size_t) input_section->size);
252b5132
RH		 2966
2967 if ((input_section->flags & SEC_RELOC) != 0
2968 && input_section->reloc_count > 0)
2969 {
2970 bfd_size_type symesz = bfd_coff_symesz (input_bfd);
2971 bfd_byte *esym, *esymend;
2972 struct internal_syment *isymp;
2973 asection **secpp;
dc810e39 2974 bfd_size_type amt;
252b5132
RH		 2975
2976 if (! _bfd_coff_get_external_symbols (input_bfd))
2977 goto error_return;
2978
2979 internal_relocs = (_bfd_coff_read_internal_relocs
b34976b6
AM		 2980 (input_bfd, input_section, FALSE, (bfd_byte *) NULL,
2981 FALSE, (struct internal_reloc *) NULL));
252b5132
RH		 2982 if (internal_relocs == NULL)
2983 goto error_return;
2984
dc810e39
AM		 2985 amt = obj_raw_syment_count (input_bfd);
2986 amt *= sizeof (struct internal_syment);
2987 internal_syms = (struct internal_syment *) bfd_malloc (amt);
252b5132
RH		 2988 if (internal_syms == NULL)
2989 goto error_return;
2990
dc810e39
AM		 2991 amt = obj_raw_syment_count (input_bfd);
2992 amt *= sizeof (asection *);
2993 sections = (asection **) bfd_malloc (amt);
252b5132
RH		 2994 if (sections == NULL)
2995 goto error_return;
2996
2997 isymp = internal_syms;
2998 secpp = sections;
2999 esym = (bfd_byte *) obj_coff_external_syms (input_bfd);
3000 esymend = esym + obj_raw_syment_count (input_bfd) * symesz;
3001 while (esym < esymend)
3002 {
3003 bfd_coff_swap_sym_in (input_bfd, (PTR) esym, (PTR) isymp);
3004
3005 if (isymp->n_scnum != 0)
3006 *secpp = coff_section_from_bfd_index (input_bfd, isymp->n_scnum);
3007 else
3008 {
3009 if (isymp->n_value == 0)
3010 *secpp = bfd_und_section_ptr;
3011 else
3012 *secpp = bfd_com_section_ptr;
3013 }
3014
3015 esym += (isymp->n_numaux + 1) * symesz;
3016 secpp += isymp->n_numaux + 1;
3017 isymp += isymp->n_numaux + 1;
3018 }
3019
3020 if (! sh_relocate_section (output_bfd, link_info, input_bfd,
3021 input_section, data, internal_relocs,
3022 internal_syms, sections))
3023 goto error_return;
3024
3025 free (sections);
3026 sections = NULL;
3027 free (internal_syms);
3028 internal_syms = NULL;
3029 free (internal_relocs);
3030 internal_relocs = NULL;
3031 }
3032
3033 return data;
3034
3035 error_return:
3036 if (internal_relocs != NULL)
3037 free (internal_relocs);
3038 if (internal_syms != NULL)
3039 free (internal_syms);
3040 if (sections != NULL)
3041 free (sections);
3042 return NULL;
3043}
3044
3045/* The target vectors. */
3046
17505c5c 3047#ifndef TARGET_SHL_SYM
3fa78519 3048CREATE_BIG_COFF_TARGET_VEC (shcoff_vec, "coff-sh", BFD_IS_RELAXABLE, 0, '_', NULL, COFF_SWAP_TABLE)
17505c5c 3049#endif
252b5132 3050
c3c89269
NC		 3051#ifdef TARGET_SHL_SYM
3052#define TARGET_SYM TARGET_SHL_SYM
3053#else
3054#define TARGET_SYM shlcoff_vec
3055#endif
cbfe05c4 3056
c3c89269
NC		 3057#ifndef TARGET_SHL_NAME
3058#define TARGET_SHL_NAME "coff-shl"
3059#endif
252b5132 3060
17505c5c
NC		 3061#ifdef COFF_WITH_PE
3062CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3fa78519 3063 SEC_CODE | SEC_DATA, '_', NULL, COFF_SWAP_TABLE);
17505c5c 3064#else
86033394 3065CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3fa78519 3066 0, '_', NULL, COFF_SWAP_TABLE)
17505c5c 3067#endif
86033394 3068
17505c5c 3069#ifndef TARGET_SHL_SYM
f4ffd778 3070static const bfd_target * coff_small_object_p PARAMS ((bfd *));
b34976b6 3071static bfd_boolean coff_small_new_section_hook PARAMS ((bfd *, asection *));
252b5132
RH		 3072/* Some people want versions of the SH COFF target which do not align
3073 to 16 byte boundaries. We implement that by adding a couple of new
3074 target vectors. These are just like the ones above, but they
3075 change the default section alignment. To generate them in the
3076 assembler, use -small. To use them in the linker, use -b
3077 coff-sh{l}-small and -oformat coff-sh{l}-small.
3078
3079 Yes, this is a horrible hack. A general solution for setting
3080 section alignment in COFF is rather complex. ELF handles this
3081 correctly. */
3082
3083/* Only recognize the small versions if the target was not defaulted.
3084 Otherwise we won't recognize the non default endianness. */
3085
3086static const bfd_target *
3087coff_small_object_p (abfd)
3088 bfd *abfd;
3089{
3090 if (abfd->target_defaulted)
3091 {
3092 bfd_set_error (bfd_error_wrong_format);
3093 return NULL;
3094 }
3095 return coff_object_p (abfd);
3096}
3097
3098/* Set the section alignment for the small versions. */
3099
b34976b6 3100static bfd_boolean
252b5132
RH		 3101coff_small_new_section_hook (abfd, section)
3102 bfd *abfd;
3103 asection *section;
3104{
3105 if (! coff_new_section_hook (abfd, section))
b34976b6 3106 return FALSE;
252b5132
RH		 3107
3108 /* We must align to at least a four byte boundary, because longword
3109 accesses must be on a four byte boundary. */
3110 if (section->alignment_power == COFF_DEFAULT_SECTION_ALIGNMENT_POWER)
3111 section->alignment_power = 2;
3112
b34976b6 3113 return TRUE;
252b5132
RH		 3114}
3115
3116/* This is copied from bfd_coff_std_swap_table so that we can change
3117 the default section alignment power. */
3118
3119static const bfd_coff_backend_data bfd_coff_small_swap_table =
3120{
3121 coff_swap_aux_in, coff_swap_sym_in, coff_swap_lineno_in,
3122 coff_swap_aux_out, coff_swap_sym_out,
3123 coff_swap_lineno_out, coff_swap_reloc_out,
3124 coff_swap_filehdr_out, coff_swap_aouthdr_out,
3125 coff_swap_scnhdr_out,
692b7d62 3126 FILHSZ, AOUTSZ, SCNHSZ, SYMESZ, AUXESZ, RELSZ, LINESZ, FILNMLEN,
252b5132 3127#ifdef COFF_LONG_FILENAMES
b34976b6 3128 TRUE,
252b5132 3129#else
b34976b6 3130 FALSE,
252b5132
RH		 3131#endif
3132#ifdef COFF_LONG_SECTION_NAMES
b34976b6 3133 TRUE,
252b5132 3134#else
b34976b6 3135 FALSE,
252b5132
RH		 3136#endif
3137 2,
ecefdb58 3138#ifdef COFF_FORCE_SYMBOLS_IN_STRINGS
b34976b6 3139 TRUE,
ecefdb58 3140#else
b34976b6 3141 FALSE,
ecefdb58
CP		 3142#endif
3143#ifdef COFF_DEBUG_STRING_WIDE_PREFIX
3144 4,
3145#else
3146 2,
3147#endif
252b5132
RH		 3148 coff_swap_filehdr_in, coff_swap_aouthdr_in, coff_swap_scnhdr_in,
3149 coff_swap_reloc_in, coff_bad_format_hook, coff_set_arch_mach_hook,
3150 coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook,
3151 coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook,
3152 coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate,
5d54c628 3153 coff_classify_symbol, coff_compute_section_file_positions,
252b5132
RH		 3154 coff_start_final_link, coff_relocate_section, coff_rtype_to_howto,
3155 coff_adjust_symndx, coff_link_add_one_symbol,
2b5c217d
NC		 3156 coff_link_output_has_begun, coff_final_link_postscript,
3157 bfd_pe_print_pdata
252b5132
RH		 3158};
3159
3160#define coff_small_close_and_cleanup \
3161 coff_close_and_cleanup
3162#define coff_small_bfd_free_cached_info \
3163 coff_bfd_free_cached_info
3164#define coff_small_get_section_contents \
3165 coff_get_section_contents
3166#define coff_small_get_section_contents_in_window \
3167 coff_get_section_contents_in_window
3168
c3c89269
NC		 3169extern const bfd_target shlcoff_small_vec;
3170
252b5132
RH		 3171const bfd_target shcoff_small_vec =
3172{
3173 "coff-sh-small", /* name */
3174 bfd_target_coff_flavour,
3175 BFD_ENDIAN_BIG, /* data byte order is big */
3176 BFD_ENDIAN_BIG, /* header byte order is big */
3177
3178 (HAS_RELOC | EXEC_P | /* object flags */
3179 HAS_LINENO | HAS_DEBUG |
3180 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
3181
3182 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3183 '_', /* leading symbol underscore */
3184 '/', /* ar_pad_char */
3185 15, /* ar_max_namelen */
3186 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3187 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3188 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
3189 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3190 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3191 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
3192
3193 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
3194 bfd_generic_archive_p, _bfd_dummy_target},
3195 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
3196 bfd_false},
3197 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
3198 _bfd_write_archive_contents, bfd_false},
3199
3200 BFD_JUMP_TABLE_GENERIC (coff_small),
3201 BFD_JUMP_TABLE_COPY (coff),
3202 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3203 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3204 BFD_JUMP_TABLE_SYMBOLS (coff),
3205 BFD_JUMP_TABLE_RELOCS (coff),
3206 BFD_JUMP_TABLE_WRITE (coff),
3207 BFD_JUMP_TABLE_LINK (coff),
3208 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3209
c3c89269 3210 & shlcoff_small_vec,
cbfe05c4 3211
252b5132
RH		 3212 (PTR) &bfd_coff_small_swap_table
3213};
3214
3215const bfd_target shlcoff_small_vec =
3216{
3217 "coff-shl-small", /* name */
3218 bfd_target_coff_flavour,
3219 BFD_ENDIAN_LITTLE, /* data byte order is little */
3220 BFD_ENDIAN_LITTLE, /* header byte order is little endian too*/
3221
3222 (HAS_RELOC | EXEC_P | /* object flags */
3223 HAS_LINENO | HAS_DEBUG |
3224 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
3225
3226 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3227 '_', /* leading symbol underscore */
3228 '/', /* ar_pad_char */
3229 15, /* ar_max_namelen */
3230 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3231 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3232 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
3233 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3234 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3235 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
3236
3237 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
cbfe05c4 3238 bfd_generic_archive_p, _bfd_dummy_target},
252b5132
RH		 3239 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
3240 bfd_false},
3241 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
3242 _bfd_write_archive_contents, bfd_false},
3243
3244 BFD_JUMP_TABLE_GENERIC (coff_small),
3245 BFD_JUMP_TABLE_COPY (coff),
3246 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3247 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3248 BFD_JUMP_TABLE_SYMBOLS (coff),
3249 BFD_JUMP_TABLE_RELOCS (coff),
3250 BFD_JUMP_TABLE_WRITE (coff),
3251 BFD_JUMP_TABLE_LINK (coff),
3252 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3253
c3c89269 3254 & shcoff_small_vec,
cbfe05c4 3255
252b5132
RH		 3256 (PTR) &bfd_coff_small_swap_table
3257};
17505c5c 3258#endif
GDB Binutils - Deliverables
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