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c2dcd04e 1/* BFD back-end for Renesas Super-H COFF binaries.
219d1afa 2 Copyright (C) 1993-2018 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Cygnus Support.
4 Written by Steve Chamberlain, <sac@cygnus.com>.
5 Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>.
6
c2dcd04e 7 This file is part of BFD, the Binary File Descriptor library.
252b5132 8
c2dcd04e
NC		 9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
cd123cb7 11 the Free Software Foundation; either version 3 of the License, or
c2dcd04e 12 (at your option) any later version.
252b5132 13
c2dcd04e
NC		 14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
252b5132 18
c2dcd04e
NC		 19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
cd123cb7
NC		 21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
252b5132 23
252b5132 24#include "sysdep.h"
3db64b00 25#include "bfd.h"
993e9275 26#include "libiberty.h"
252b5132
RH		 27#include "libbfd.h"
28#include "bfdlink.h"
29#include "coff/sh.h"
30#include "coff/internal.h"
17505c5c 31
799c00e0
NC		 32#undef bfd_pe_print_pdata
33
17505c5c
NC		 34#ifdef COFF_WITH_PE
35#include "coff/pe.h"
86033394
NC		 36
37#ifndef COFF_IMAGE_WITH_PE
b34976b6 38static bfd_boolean sh_align_load_span
2c3fc389
NC		 39 (bfd *, asection *, bfd_byte *,
40 bfd_boolean (*) (bfd *, asection *, void *, bfd_byte *, bfd_vma),
41 void *, bfd_vma **, bfd_vma *, bfd_vma, bfd_vma, bfd_boolean *);
86033394
NC		 42
43#define _bfd_sh_align_load_span sh_align_load_span
44#endif
17505c5c 45
799c00e0
NC		 46#define bfd_pe_print_pdata _bfd_pe_print_ce_compressed_pdata
47
48#else
49
50#define bfd_pe_print_pdata NULL
51
52#endif /* COFF_WITH_PE. */
2b5c217d 53
252b5132
RH		 54#include "libcoff.h"
55
56/* Internal functions. */
252b5132 57
17505c5c
NC		 58#ifdef COFF_WITH_PE
59/* Can't build import tables with 2**4 alignment. */
60#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 2
61#else
252b5132 62/* Default section alignment to 2**4. */
17505c5c
NC		 63#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 4
64#endif
65
66#ifdef COFF_IMAGE_WITH_PE
67/* Align PE executables. */
68#define COFF_PAGE_SIZE 0x1000
69#endif
252b5132
RH		 70
71/* Generate long file names. */
72#define COFF_LONG_FILENAMES
73
17505c5c 74#ifdef COFF_WITH_PE
b34976b6 75/* Return TRUE if this relocation should
17505c5c 76 appear in the output .reloc section. */
2c3fc389
NC		 77
78static bfd_boolean
79in_reloc_p (bfd * abfd ATTRIBUTE_UNUSED,
80 reloc_howto_type * howto)
17505c5c
NC		 81{
82 return ! howto->pc_relative && howto->type != R_SH_IMAGEBASE;
cbfe05c4 83}
17505c5c
NC		 84#endif
85
2c3fc389
NC		 86static bfd_reloc_status_type
87sh_reloc (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
88static bfd_boolean
89sh_relocate_section (bfd *, struct bfd_link_info *, bfd *, asection *,
90 bfd_byte *, struct internal_reloc *,
91 struct internal_syment *, asection **);
92static bfd_boolean
93sh_align_loads (bfd *, asection *, struct internal_reloc *,
94 bfd_byte *, bfd_boolean *);
95
252b5132
RH		 96/* The supported relocations. There are a lot of relocations defined
97 in coff/internal.h which we do not expect to ever see. */
98static reloc_howto_type sh_coff_howtos[] =
99{
5f771d47
ILT		 100 EMPTY_HOWTO (0),
101 EMPTY_HOWTO (1),
17505c5c
NC		 102#ifdef COFF_WITH_PE
103 /* Windows CE */
104 HOWTO (R_SH_IMM32CE, /* type */
105 0, /* rightshift */
106 2, /* size (0 = byte, 1 = short, 2 = long) */
107 32, /* bitsize */
b34976b6 108 FALSE, /* pc_relative */
17505c5c
NC		 109 0, /* bitpos */
110 complain_overflow_bitfield, /* complain_on_overflow */
111 sh_reloc, /* special_function */
112 "r_imm32ce", /* name */
b34976b6 113 TRUE, /* partial_inplace */
17505c5c
NC		 114 0xffffffff, /* src_mask */
115 0xffffffff, /* dst_mask */
b34976b6 116 FALSE), /* pcrel_offset */
17505c5c 117#else
5f771d47 118 EMPTY_HOWTO (2),
17505c5c 119#endif
5f771d47
ILT		 120 EMPTY_HOWTO (3), /* R_SH_PCREL8 */
121 EMPTY_HOWTO (4), /* R_SH_PCREL16 */
122 EMPTY_HOWTO (5), /* R_SH_HIGH8 */
123 EMPTY_HOWTO (6), /* R_SH_IMM24 */
124 EMPTY_HOWTO (7), /* R_SH_LOW16 */
125 EMPTY_HOWTO (8),
126 EMPTY_HOWTO (9), /* R_SH_PCDISP8BY4 */
252b5132
RH		 127
128 HOWTO (R_SH_PCDISP8BY2, /* type */
129 1, /* rightshift */
130 1, /* size (0 = byte, 1 = short, 2 = long) */
131 8, /* bitsize */
b34976b6 132 TRUE, /* pc_relative */
252b5132
RH		 133 0, /* bitpos */
134 complain_overflow_signed, /* complain_on_overflow */
135 sh_reloc, /* special_function */
136 "r_pcdisp8by2", /* name */
b34976b6 137 TRUE, /* partial_inplace */
252b5132
RH		 138 0xff, /* src_mask */
139 0xff, /* dst_mask */
b34976b6 140 TRUE), /* pcrel_offset */
252b5132 141
5f771d47 142 EMPTY_HOWTO (11), /* R_SH_PCDISP8 */
252b5132
RH		 143
144 HOWTO (R_SH_PCDISP, /* type */
145 1, /* rightshift */
146 1, /* size (0 = byte, 1 = short, 2 = long) */
147 12, /* bitsize */
b34976b6 148 TRUE, /* pc_relative */
252b5132
RH		 149 0, /* bitpos */
150 complain_overflow_signed, /* complain_on_overflow */
151 sh_reloc, /* special_function */
152 "r_pcdisp12by2", /* name */
b34976b6 153 TRUE, /* partial_inplace */
252b5132
RH		 154 0xfff, /* src_mask */
155 0xfff, /* dst_mask */
b34976b6 156 TRUE), /* pcrel_offset */
252b5132 157
5f771d47 158 EMPTY_HOWTO (13),
252b5132
RH		 159
160 HOWTO (R_SH_IMM32, /* type */
161 0, /* rightshift */
162 2, /* size (0 = byte, 1 = short, 2 = long) */
163 32, /* bitsize */
b34976b6 164 FALSE, /* pc_relative */
252b5132
RH		 165 0, /* bitpos */
166 complain_overflow_bitfield, /* complain_on_overflow */
167 sh_reloc, /* special_function */
168 "r_imm32", /* name */
b34976b6 169 TRUE, /* partial_inplace */
252b5132
RH		 170 0xffffffff, /* src_mask */
171 0xffffffff, /* dst_mask */
b34976b6 172 FALSE), /* pcrel_offset */
252b5132 173
5f771d47 174 EMPTY_HOWTO (15),
17505c5c 175#ifdef COFF_WITH_PE
07d6d2b8
AM		 176 HOWTO (R_SH_IMAGEBASE, /* type */
177 0, /* rightshift */
178 2, /* size (0 = byte, 1 = short, 2 = long) */
179 32, /* bitsize */
180 FALSE, /* pc_relative */
181 0, /* bitpos */
17505c5c 182 complain_overflow_bitfield, /* complain_on_overflow */
07d6d2b8
AM		 183 sh_reloc, /* special_function */
184 "rva32", /* name */
185 TRUE, /* partial_inplace */
186 0xffffffff, /* src_mask */
187 0xffffffff, /* dst_mask */
188 FALSE), /* pcrel_offset */
17505c5c 189#else
5f771d47 190 EMPTY_HOWTO (16), /* R_SH_IMM8 */
17505c5c 191#endif
5f771d47
ILT		 192 EMPTY_HOWTO (17), /* R_SH_IMM8BY2 */
193 EMPTY_HOWTO (18), /* R_SH_IMM8BY4 */
194 EMPTY_HOWTO (19), /* R_SH_IMM4 */
195 EMPTY_HOWTO (20), /* R_SH_IMM4BY2 */
196 EMPTY_HOWTO (21), /* R_SH_IMM4BY4 */
252b5132
RH		 197
198 HOWTO (R_SH_PCRELIMM8BY2, /* type */
199 1, /* rightshift */
200 1, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
b34976b6 202 TRUE, /* pc_relative */
252b5132
RH		 203 0, /* bitpos */
204 complain_overflow_unsigned, /* complain_on_overflow */
205 sh_reloc, /* special_function */
206 "r_pcrelimm8by2", /* name */
b34976b6 207 TRUE, /* partial_inplace */
252b5132
RH		 208 0xff, /* src_mask */
209 0xff, /* dst_mask */
b34976b6 210 TRUE), /* pcrel_offset */
252b5132
RH		 211
212 HOWTO (R_SH_PCRELIMM8BY4, /* type */
213 2, /* rightshift */
214 1, /* size (0 = byte, 1 = short, 2 = long) */
215 8, /* bitsize */
b34976b6 216 TRUE, /* pc_relative */
252b5132
RH		 217 0, /* bitpos */
218 complain_overflow_unsigned, /* complain_on_overflow */
219 sh_reloc, /* special_function */
220 "r_pcrelimm8by4", /* name */
b34976b6 221 TRUE, /* partial_inplace */
252b5132
RH		 222 0xff, /* src_mask */
223 0xff, /* dst_mask */
b34976b6 224 TRUE), /* pcrel_offset */
252b5132
RH		 225
226 HOWTO (R_SH_IMM16, /* type */
227 0, /* rightshift */
228 1, /* size (0 = byte, 1 = short, 2 = long) */
229 16, /* bitsize */
b34976b6 230 FALSE, /* pc_relative */
252b5132
RH		 231 0, /* bitpos */
232 complain_overflow_bitfield, /* complain_on_overflow */
233 sh_reloc, /* special_function */
234 "r_imm16", /* name */
b34976b6 235 TRUE, /* partial_inplace */
252b5132
RH		 236 0xffff, /* src_mask */
237 0xffff, /* dst_mask */
b34976b6 238 FALSE), /* pcrel_offset */
252b5132
RH		 239
240 HOWTO (R_SH_SWITCH16, /* type */
241 0, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 16, /* bitsize */
b34976b6 244 FALSE, /* pc_relative */
252b5132
RH		 245 0, /* bitpos */
246 complain_overflow_bitfield, /* complain_on_overflow */
247 sh_reloc, /* special_function */
248 "r_switch16", /* name */
b34976b6 249 TRUE, /* partial_inplace */
252b5132
RH		 250 0xffff, /* src_mask */
251 0xffff, /* dst_mask */
b34976b6 252 FALSE), /* pcrel_offset */
252b5132
RH		 253
254 HOWTO (R_SH_SWITCH32, /* type */
255 0, /* rightshift */
256 2, /* size (0 = byte, 1 = short, 2 = long) */
257 32, /* bitsize */
b34976b6 258 FALSE, /* pc_relative */
252b5132
RH		 259 0, /* bitpos */
260 complain_overflow_bitfield, /* complain_on_overflow */
261 sh_reloc, /* special_function */
262 "r_switch32", /* name */
b34976b6 263 TRUE, /* partial_inplace */
252b5132
RH		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
b34976b6 266 FALSE), /* pcrel_offset */
252b5132
RH		 267
268 HOWTO (R_SH_USES, /* type */
269 0, /* rightshift */
270 1, /* size (0 = byte, 1 = short, 2 = long) */
271 16, /* bitsize */
b34976b6 272 FALSE, /* pc_relative */
252b5132
RH		 273 0, /* bitpos */
274 complain_overflow_bitfield, /* complain_on_overflow */
275 sh_reloc, /* special_function */
276 "r_uses", /* name */
b34976b6 277 TRUE, /* partial_inplace */
252b5132
RH		 278 0xffff, /* src_mask */
279 0xffff, /* dst_mask */
b34976b6 280 FALSE), /* pcrel_offset */
252b5132
RH		 281
282 HOWTO (R_SH_COUNT, /* type */
283 0, /* rightshift */
284 2, /* size (0 = byte, 1 = short, 2 = long) */
285 32, /* bitsize */
b34976b6 286 FALSE, /* pc_relative */
252b5132
RH		 287 0, /* bitpos */
288 complain_overflow_bitfield, /* complain_on_overflow */
289 sh_reloc, /* special_function */
290 "r_count", /* name */
b34976b6 291 TRUE, /* partial_inplace */
252b5132
RH		 292 0xffffffff, /* src_mask */
293 0xffffffff, /* dst_mask */
b34976b6 294 FALSE), /* pcrel_offset */
252b5132
RH		 295
296 HOWTO (R_SH_ALIGN, /* type */
297 0, /* rightshift */
298 2, /* size (0 = byte, 1 = short, 2 = long) */
299 32, /* bitsize */
b34976b6 300 FALSE, /* pc_relative */
252b5132
RH		 301 0, /* bitpos */
302 complain_overflow_bitfield, /* complain_on_overflow */
303 sh_reloc, /* special_function */
304 "r_align", /* name */
b34976b6 305 TRUE, /* partial_inplace */
252b5132
RH		 306 0xffffffff, /* src_mask */
307 0xffffffff, /* dst_mask */
b34976b6 308 FALSE), /* pcrel_offset */
252b5132
RH		 309
310 HOWTO (R_SH_CODE, /* type */
311 0, /* rightshift */
312 2, /* size (0 = byte, 1 = short, 2 = long) */
313 32, /* bitsize */
b34976b6 314 FALSE, /* pc_relative */
252b5132
RH		 315 0, /* bitpos */
316 complain_overflow_bitfield, /* complain_on_overflow */
317 sh_reloc, /* special_function */
318 "r_code", /* name */
b34976b6 319 TRUE, /* partial_inplace */
252b5132
RH		 320 0xffffffff, /* src_mask */
321 0xffffffff, /* dst_mask */
b34976b6 322 FALSE), /* pcrel_offset */
252b5132
RH		 323
324 HOWTO (R_SH_DATA, /* type */
325 0, /* rightshift */
326 2, /* size (0 = byte, 1 = short, 2 = long) */
327 32, /* bitsize */
b34976b6 328 FALSE, /* pc_relative */
252b5132
RH		 329 0, /* bitpos */
330 complain_overflow_bitfield, /* complain_on_overflow */
331 sh_reloc, /* special_function */
332 "r_data", /* name */
b34976b6 333 TRUE, /* partial_inplace */
252b5132
RH		 334 0xffffffff, /* src_mask */
335 0xffffffff, /* dst_mask */
b34976b6 336 FALSE), /* pcrel_offset */
252b5132
RH		 337
338 HOWTO (R_SH_LABEL, /* type */
339 0, /* rightshift */
340 2, /* size (0 = byte, 1 = short, 2 = long) */
341 32, /* bitsize */
b34976b6 342 FALSE, /* pc_relative */
252b5132
RH		 343 0, /* bitpos */
344 complain_overflow_bitfield, /* complain_on_overflow */
345 sh_reloc, /* special_function */
346 "r_label", /* name */
b34976b6 347 TRUE, /* partial_inplace */
252b5132
RH		 348 0xffffffff, /* src_mask */
349 0xffffffff, /* dst_mask */
b34976b6 350 FALSE), /* pcrel_offset */
252b5132
RH		 351
352 HOWTO (R_SH_SWITCH8, /* type */
353 0, /* rightshift */
354 0, /* size (0 = byte, 1 = short, 2 = long) */
355 8, /* bitsize */
b34976b6 356 FALSE, /* pc_relative */
252b5132
RH		 357 0, /* bitpos */
358 complain_overflow_bitfield, /* complain_on_overflow */
359 sh_reloc, /* special_function */
360 "r_switch8", /* name */
b34976b6 361 TRUE, /* partial_inplace */
252b5132
RH		 362 0xff, /* src_mask */
363 0xff, /* dst_mask */
b34976b6 364 FALSE) /* pcrel_offset */
252b5132
RH		 365};
366
367#define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])
368
369/* Check for a bad magic number. */
370#define BADMAG(x) SHBADMAG(x)
371
372/* Customize coffcode.h (this is not currently used). */
373#define SH 1
374
375/* FIXME: This should not be set here. */
376#define __A_MAGIC_SET__
377
17505c5c 378#ifndef COFF_WITH_PE
252b5132 379/* Swap the r_offset field in and out. */
dc810e39
AM		 380#define SWAP_IN_RELOC_OFFSET H_GET_32
381#define SWAP_OUT_RELOC_OFFSET H_PUT_32
252b5132
RH		 382
383/* Swap out extra information in the reloc structure. */
384#define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \
385 do \
386 { \
387 dst->r_stuff[0] = 'S'; \
388 dst->r_stuff[1] = 'C'; \
389 } \
390 while (0)
17505c5c 391#endif
252b5132
RH		 392
393/* Get the value of a symbol, when performing a relocation. */
394
395static long
2c3fc389 396get_symbol_value (asymbol *symbol)
cbfe05c4 397{
252b5132
RH		 398 bfd_vma relocation;
399
400 if (bfd_is_com_section (symbol->section))
cbfe05c4
KH		 401 relocation = 0;
402 else
252b5132
RH		 403 relocation = (symbol->value +
404 symbol->section->output_section->vma +
405 symbol->section->output_offset);
406
407 return relocation;
408}
409
17505c5c
NC		 410#ifdef COFF_WITH_PE
411/* Convert an rtype to howto for the COFF backend linker.
412 Copied from coff-i386. */
413#define coff_rtype_to_howto coff_sh_rtype_to_howto
2c3fc389 414
17505c5c
NC		 415
416static reloc_howto_type *
2c3fc389
NC		 417coff_sh_rtype_to_howto (bfd * abfd ATTRIBUTE_UNUSED,
418 asection * sec,
419 struct internal_reloc * rel,
420 struct coff_link_hash_entry * h,
421 struct internal_syment * sym,
422 bfd_vma * addendp)
17505c5c
NC		 423{
424 reloc_howto_type * howto;
425
426 howto = sh_coff_howtos + rel->r_type;
427
428 *addendp = 0;
429
430 if (howto->pc_relative)
431 *addendp += sec->vma;
432
433 if (sym != NULL && sym->n_scnum == 0 && sym->n_value != 0)
434 {
435 /* This is a common symbol. The section contents include the
436 size (sym->n_value) as an addend. The relocate_section
437 function will be adding in the final value of the symbol. We
438 need to subtract out the current size in order to get the
439 correct result. */
440 BFD_ASSERT (h != NULL);
441 }
442
443 if (howto->pc_relative)
444 {
445 *addendp -= 4;
446
447 /* If the symbol is defined, then the generic code is going to
07d6d2b8
AM		 448 add back the symbol value in order to cancel out an
449 adjustment it made to the addend. However, we set the addend
450 to 0 at the start of this function. We need to adjust here,
451 to avoid the adjustment the generic code will make. FIXME:
452 This is getting a bit hackish. */
17505c5c
NC		 453 if (sym != NULL && sym->n_scnum != 0)
454 *addendp -= sym->n_value;
455 }
456
457 if (rel->r_type == R_SH_IMAGEBASE)
458 *addendp -= pe_data (sec->output_section->owner)->pe_opthdr.ImageBase;
459
460 return howto;
461}
462
993e9275
NC		 463#endif /* COFF_WITH_PE */
464
17505c5c
NC		 465/* This structure is used to map BFD reloc codes to SH PE relocs. */
466struct shcoff_reloc_map
467{
aa066ac8 468 bfd_reloc_code_real_type bfd_reloc_val;
17505c5c
NC		 469 unsigned char shcoff_reloc_val;
470};
471
a9a32010 472#ifdef COFF_WITH_PE
17505c5c
NC		 473/* An array mapping BFD reloc codes to SH PE relocs. */
474static const struct shcoff_reloc_map sh_reloc_map[] =
475{
476 { BFD_RELOC_32, R_SH_IMM32CE },
477 { BFD_RELOC_RVA, R_SH_IMAGEBASE },
478 { BFD_RELOC_CTOR, R_SH_IMM32CE },
479};
a9a32010
DJ		 480#else
481/* An array mapping BFD reloc codes to SH PE relocs. */
482static const struct shcoff_reloc_map sh_reloc_map[] =
483{
484 { BFD_RELOC_32, R_SH_IMM32 },
485 { BFD_RELOC_CTOR, R_SH_IMM32 },
486};
487#endif
17505c5c
NC		 488
489/* Given a BFD reloc code, return the howto structure for the
490 corresponding SH PE reloc. */
491#define coff_bfd_reloc_type_lookup sh_coff_reloc_type_lookup
157090f7 492#define coff_bfd_reloc_name_lookup sh_coff_reloc_name_lookup
17505c5c
NC		 493
494static reloc_howto_type *
2c3fc389
NC		 495sh_coff_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
496 bfd_reloc_code_real_type code)
17505c5c
NC		 497{
498 unsigned int i;
499
993e9275
NC		 500 for (i = ARRAY_SIZE (sh_reloc_map); i--;)
501 if (sh_reloc_map[i].bfd_reloc_val == code)
502 return &sh_coff_howtos[(int) sh_reloc_map[i].shcoff_reloc_val];
17505c5c 503
4eca0228 504 _bfd_error_handler (_("SH Error: unknown reloc type %d"), code);
17505c5c
NC		 505 return NULL;
506}
17505c5c 507
157090f7
AM		 508static reloc_howto_type *
509sh_coff_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
510 const char *r_name)
511{
512 unsigned int i;
513
514 for (i = 0; i < sizeof (sh_coff_howtos) / sizeof (sh_coff_howtos[0]); i++)
515 if (sh_coff_howtos[i].name != NULL
516 && strcasecmp (sh_coff_howtos[i].name, r_name) == 0)
517 return &sh_coff_howtos[i];
518
519 return NULL;
520}
521
252b5132
RH		 522/* This macro is used in coffcode.h to get the howto corresponding to
523 an internal reloc. */
524
525#define RTYPE2HOWTO(relent, internal) \
526 ((relent)->howto = \
527 ((internal)->r_type < SH_COFF_HOWTO_COUNT \
528 ? &sh_coff_howtos[(internal)->r_type] \
529 : (reloc_howto_type *) NULL))
530
531/* This is the same as the macro in coffcode.h, except that it copies
532 r_offset into reloc_entry->addend for some relocs. */
f4943d82
AM		 533#define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \
534 { \
535 coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \
536 if (ptr && bfd_asymbol_bfd (ptr) != abfd) \
537 coffsym = (obj_symbols (abfd) \
538 + (cache_ptr->sym_ptr_ptr - symbols)); \
539 else if (ptr) \
540 coffsym = coff_symbol_from (ptr); \
541 if (coffsym != (coff_symbol_type *) NULL \
542 && coffsym->native->u.syment.n_scnum == 0) \
543 cache_ptr->addend = 0; \
544 else if (ptr && bfd_asymbol_bfd (ptr) == abfd \
545 && ptr->section != (asection *) NULL) \
546 cache_ptr->addend = - (ptr->section->vma + ptr->value); \
547 else \
548 cache_ptr->addend = 0; \
252b5132
RH		 549 if ((reloc).r_type == R_SH_SWITCH8 \
550 || (reloc).r_type == R_SH_SWITCH16 \
551 || (reloc).r_type == R_SH_SWITCH32 \
552 || (reloc).r_type == R_SH_USES \
553 || (reloc).r_type == R_SH_COUNT \
554 || (reloc).r_type == R_SH_ALIGN) \
555 cache_ptr->addend = (reloc).r_offset; \
556 }
557
558/* This is the howto function for the SH relocations. */
559
560static bfd_reloc_status_type
2c3fc389
NC		 561sh_reloc (bfd * abfd,
562 arelent * reloc_entry,
563 asymbol * symbol_in,
564 void * data,
565 asection * input_section,
566 bfd * output_bfd,
567 char ** error_message ATTRIBUTE_UNUSED)
252b5132
RH		 568{
569 unsigned long insn;
570 bfd_vma sym_value;
571 unsigned short r_type;
572 bfd_vma addr = reloc_entry->address;
573 bfd_byte *hit_data = addr + (bfd_byte *) data;
574
575 r_type = reloc_entry->howto->type;
576
577 if (output_bfd != NULL)
578 {
579 /* Partial linking--do nothing. */
580 reloc_entry->address += input_section->output_offset;
581 return bfd_reloc_ok;
582 }
583
584 /* Almost all relocs have to do with relaxing. If any work must be
585 done for them, it has been done in sh_relax_section. */
586 if (r_type != R_SH_IMM32
17505c5c
NC		 587#ifdef COFF_WITH_PE
588 && r_type != R_SH_IMM32CE
589 && r_type != R_SH_IMAGEBASE
590#endif
252b5132
RH		 591 && (r_type != R_SH_PCDISP
592 || (symbol_in->flags & BSF_LOCAL) != 0))
593 return bfd_reloc_ok;
594
595 if (symbol_in != NULL
596 && bfd_is_und_section (symbol_in->section))
597 return bfd_reloc_undefined;
598
6879f5a9
NC		 599 if (addr > input_section->size)
600 return bfd_reloc_outofrange;
601
252b5132
RH		 602 sym_value = get_symbol_value (symbol_in);
603
604 switch (r_type)
605 {
606 case R_SH_IMM32:
17505c5c
NC		 607#ifdef COFF_WITH_PE
608 case R_SH_IMM32CE:
609#endif
252b5132
RH		 610 insn = bfd_get_32 (abfd, hit_data);
611 insn += sym_value + reloc_entry->addend;
dc810e39 612 bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
252b5132 613 break;
17505c5c
NC		 614#ifdef COFF_WITH_PE
615 case R_SH_IMAGEBASE:
616 insn = bfd_get_32 (abfd, hit_data);
dc810e39
AM		 617 insn += sym_value + reloc_entry->addend;
618 insn -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
619 bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
17505c5c
NC		 620 break;
621#endif
252b5132
RH		 622 case R_SH_PCDISP:
623 insn = bfd_get_16 (abfd, hit_data);
624 sym_value += reloc_entry->addend;
625 sym_value -= (input_section->output_section->vma
626 + input_section->output_offset
627 + addr
628 + 4);
629 sym_value += (insn & 0xfff) << 1;
630 if (insn & 0x800)
631 sym_value -= 0x1000;
632 insn = (insn & 0xf000) | (sym_value & 0xfff);
dc810e39 633 bfd_put_16 (abfd, (bfd_vma) insn, hit_data);
252b5132
RH		 634 if (sym_value < (bfd_vma) -0x1000 || sym_value >= 0x1000)
635 return bfd_reloc_overflow;
636 break;
637 default:
638 abort ();
639 break;
640 }
641
642 return bfd_reloc_ok;
643}
644
875f7f69 645#define coff_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match
252b5132
RH		 646
647/* We can do relaxing. */
648#define coff_bfd_relax_section sh_relax_section
649
650/* We use the special COFF backend linker. */
651#define coff_relocate_section sh_relocate_section
652
653/* When relaxing, we need to use special code to get the relocated
654 section contents. */
655#define coff_bfd_get_relocated_section_contents \
656 sh_coff_get_relocated_section_contents
657
658#include "coffcode.h"
659\f
2c3fc389
NC		 660static bfd_boolean
661sh_relax_delete_bytes (bfd *, asection *, bfd_vma, int);
662
252b5132
RH		 663/* This function handles relaxing on the SH.
664
665 Function calls on the SH look like this:
666
667 movl L1,r0
668 ...
669 jsr @r0
670 ...
671 L1:
672 .long function
673
674 The compiler and assembler will cooperate to create R_SH_USES
675 relocs on the jsr instructions. The r_offset field of the
676 R_SH_USES reloc is the PC relative offset to the instruction which
677 loads the register (the r_offset field is computed as though it
678 were a jump instruction, so the offset value is actually from four
679 bytes past the instruction). The linker can use this reloc to
680 determine just which function is being called, and thus decide
681 whether it is possible to replace the jsr with a bsr.
682
683 If multiple function calls are all based on a single register load
684 (i.e., the same function is called multiple times), the compiler
685 guarantees that each function call will have an R_SH_USES reloc.
686 Therefore, if the linker is able to convert each R_SH_USES reloc
687 which refers to that address, it can safely eliminate the register
688 load.
689
690 When the assembler creates an R_SH_USES reloc, it examines it to
691 determine which address is being loaded (L1 in the above example).
692 It then counts the number of references to that address, and
693 creates an R_SH_COUNT reloc at that address. The r_offset field of
694 the R_SH_COUNT reloc will be the number of references. If the
695 linker is able to eliminate a register load, it can use the
696 R_SH_COUNT reloc to see whether it can also eliminate the function
697 address.
698
699 SH relaxing also handles another, unrelated, matter. On the SH, if
700 a load or store instruction is not aligned on a four byte boundary,
701 the memory cycle interferes with the 32 bit instruction fetch,
702 causing a one cycle bubble in the pipeline. Therefore, we try to
703 align load and store instructions on four byte boundaries if we
704 can, by swapping them with one of the adjacent instructions. */
705
b34976b6 706static bfd_boolean
2c3fc389
NC		 707sh_relax_section (bfd *abfd,
708 asection *sec,
709 struct bfd_link_info *link_info,
710 bfd_boolean *again)
252b5132
RH		 711{
712 struct internal_reloc *internal_relocs;
b34976b6 713 bfd_boolean have_code;
252b5132
RH		 714 struct internal_reloc *irel, *irelend;
715 bfd_byte *contents = NULL;
252b5132 716
b34976b6 717 *again = FALSE;
252b5132 718
0e1862bb 719 if (bfd_link_relocatable (link_info)
252b5132
RH		 720 || (sec->flags & SEC_RELOC) == 0
721 || sec->reloc_count == 0)
b34976b6 722 return TRUE;
252b5132 723
eea6121a
AM		 724 if (coff_section_data (abfd, sec) == NULL)
725 {
726 bfd_size_type amt = sizeof (struct coff_section_tdata);
2c3fc389 727 sec->used_by_bfd = bfd_zalloc (abfd, amt);
eea6121a
AM		 728 if (sec->used_by_bfd == NULL)
729 return FALSE;
730 }
252b5132
RH		 731
732 internal_relocs = (_bfd_coff_read_internal_relocs
733 (abfd, sec, link_info->keep_memory,
b34976b6 734 (bfd_byte *) NULL, FALSE,
252b5132
RH		 735 (struct internal_reloc *) NULL));
736 if (internal_relocs == NULL)
737 goto error_return;
252b5132 738
b34976b6 739 have_code = FALSE;
252b5132
RH		 740
741 irelend = internal_relocs + sec->reloc_count;
742 for (irel = internal_relocs; irel < irelend; irel++)
743 {
744 bfd_vma laddr, paddr, symval;
745 unsigned short insn;
746 struct internal_reloc *irelfn, *irelscan, *irelcount;
747 struct internal_syment sym;
748 bfd_signed_vma foff;
749
750 if (irel->r_type == R_SH_CODE)
b34976b6 751 have_code = TRUE;
252b5132
RH		 752
753 if (irel->r_type != R_SH_USES)
754 continue;
755
756 /* Get the section contents. */
757 if (contents == NULL)
758 {
eea6121a 759 if (coff_section_data (abfd, sec)->contents != NULL)
252b5132
RH		 760 contents = coff_section_data (abfd, sec)->contents;
761 else
762 {
eea6121a 763 if (!bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 764 goto error_return;
765 }
766 }
767
768 /* The r_offset field of the R_SH_USES reloc will point us to
07d6d2b8
AM		 769 the register load. The 4 is because the r_offset field is
770 computed as though it were a jump offset, which are based
771 from 4 bytes after the jump instruction. */
252b5132
RH		 772 laddr = irel->r_vaddr - sec->vma + 4;
773 /* Careful to sign extend the 32-bit offset. */
774 laddr += ((irel->r_offset & 0xffffffff) ^ 0x80000000) - 0x80000000;
eea6121a 775 if (laddr >= sec->size)
252b5132 776 {
695344c0 777 /* xgettext: c-format */
2dcf00ce
AM		 778 _bfd_error_handler
779 (_("%pB: %#" PRIx64 ": warning: bad R_SH_USES offset"),
780 abfd, (uint64_t) irel->r_vaddr);
252b5132
RH		 781 continue;
782 }
783 insn = bfd_get_16 (abfd, contents + laddr);
784
785 /* If the instruction is not mov.l NN,rN, we don't know what to do. */
786 if ((insn & 0xf000) != 0xd000)
787 {
4eca0228 788 _bfd_error_handler
695344c0 789 /* xgettext: c-format */
2dcf00ce
AM		 790 (_("%pB: %#" PRIx64 ": warning: R_SH_USES points to unrecognized insn %#x"),
791 abfd, (uint64_t) irel->r_vaddr, insn);
252b5132
RH		 792 continue;
793 }
794
795 /* Get the address from which the register is being loaded. The
07d6d2b8
AM		 796 displacement in the mov.l instruction is quadrupled. It is a
797 displacement from four bytes after the movl instruction, but,
798 before adding in the PC address, two least significant bits
799 of the PC are cleared. We assume that the section is aligned
800 on a four byte boundary. */
252b5132
RH		 801 paddr = insn & 0xff;
802 paddr *= 4;
dc810e39 803 paddr += (laddr + 4) &~ (bfd_vma) 3;
eea6121a 804 if (paddr >= sec->size)
252b5132 805 {
4eca0228 806 _bfd_error_handler
695344c0 807 /* xgettext: c-format */
2dcf00ce
AM		 808 (_("%pB: %#" PRIx64 ": warning: bad R_SH_USES load offset"),
809 abfd, (uint64_t) irel->r_vaddr);
252b5132
RH		 810 continue;
811 }
812
813 /* Get the reloc for the address from which the register is
07d6d2b8
AM		 814 being loaded. This reloc will tell us which function is
815 actually being called. */
252b5132
RH		 816 paddr += sec->vma;
817 for (irelfn = internal_relocs; irelfn < irelend; irelfn++)
818 if (irelfn->r_vaddr == paddr
17505c5c
NC		 819#ifdef COFF_WITH_PE
820 && (irelfn->r_type == R_SH_IMM32
821 || irelfn->r_type == R_SH_IMM32CE
eea6121a 822 || irelfn->r_type == R_SH_IMAGEBASE)
17505c5c
NC		 823
824#else
eea6121a 825 && irelfn->r_type == R_SH_IMM32
17505c5c 826#endif
eea6121a 827 )
252b5132
RH		 828 break;
829 if (irelfn >= irelend)
830 {
4eca0228 831 _bfd_error_handler
695344c0 832 /* xgettext: c-format */
2dcf00ce
AM		 833 (_("%pB: %#" PRIx64 ": warning: could not find expected reloc"),
834 abfd, (uint64_t) paddr);
252b5132
RH		 835 continue;
836 }
837
838 /* Get the value of the symbol referred to by the reloc. */
839 if (! _bfd_coff_get_external_symbols (abfd))
840 goto error_return;
841 bfd_coff_swap_sym_in (abfd,
842 ((bfd_byte *) obj_coff_external_syms (abfd)
843 + (irelfn->r_symndx
844 * bfd_coff_symesz (abfd))),
845 &sym);
846 if (sym.n_scnum != 0 && sym.n_scnum != sec->target_index)
847 {
4eca0228 848 _bfd_error_handler
695344c0 849 /* xgettext: c-format */
2dcf00ce
AM		 850 (_("%pB: %#" PRIx64 ": warning: symbol in unexpected section"),
851 abfd, (uint64_t) paddr);
252b5132
RH		 852 continue;
853 }
854
855 if (sym.n_sclass != C_EXT)
856 {
857 symval = (sym.n_value
858 - sec->vma
859 + sec->output_section->vma
860 + sec->output_offset);
861 }
862 else
863 {
864 struct coff_link_hash_entry *h;
865
866 h = obj_coff_sym_hashes (abfd)[irelfn->r_symndx];
867 BFD_ASSERT (h != NULL);
868 if (h->root.type != bfd_link_hash_defined
869 && h->root.type != bfd_link_hash_defweak)
870 {
871 /* This appears to be a reference to an undefined
07d6d2b8
AM		 872 symbol. Just ignore it--it will be caught by the
873 regular reloc processing. */
252b5132
RH		 874 continue;
875 }
876
877 symval = (h->root.u.def.value
878 + h->root.u.def.section->output_section->vma
879 + h->root.u.def.section->output_offset);
880 }
881
882 symval += bfd_get_32 (abfd, contents + paddr - sec->vma);
883
884 /* See if this function call can be shortened. */
885 foff = (symval
886 - (irel->r_vaddr
887 - sec->vma
888 + sec->output_section->vma
889 + sec->output_offset
890 + 4));
891 if (foff < -0x1000 || foff >= 0x1000)
892 {
893 /* After all that work, we can't shorten this function call. */
894 continue;
895 }
896
897 /* Shorten the function call. */
898
899 /* For simplicity of coding, we are going to modify the section
900 contents, the section relocs, and the BFD symbol table. We
901 must tell the rest of the code not to free up this
902 information. It would be possible to instead create a table
903 of changes which have to be made, as is done in coff-mips.c;
904 that would be more work, but would require less memory when
905 the linker is run. */
906
252b5132 907 coff_section_data (abfd, sec)->relocs = internal_relocs;
b34976b6 908 coff_section_data (abfd, sec)->keep_relocs = TRUE;
252b5132
RH		 909
910 coff_section_data (abfd, sec)->contents = contents;
b34976b6 911 coff_section_data (abfd, sec)->keep_contents = TRUE;
252b5132 912
b34976b6 913 obj_coff_keep_syms (abfd) = TRUE;
252b5132
RH		 914
915 /* Replace the jsr with a bsr. */
916
917 /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and
07d6d2b8 918 replace the jsr with a bsr. */
252b5132
RH		 919 irel->r_type = R_SH_PCDISP;
920 irel->r_symndx = irelfn->r_symndx;
921 if (sym.n_sclass != C_EXT)
922 {
923 /* If this needs to be changed because of future relaxing,
07d6d2b8
AM		 924 it will be handled here like other internal PCDISP
925 relocs. */
252b5132 926 bfd_put_16 (abfd,
dc810e39 927 (bfd_vma) 0xb000 | ((foff >> 1) & 0xfff),
252b5132
RH		 928 contents + irel->r_vaddr - sec->vma);
929 }
930 else
931 {
932 /* We can't fully resolve this yet, because the external
07d6d2b8
AM		 933 symbol value may be changed by future relaxing. We let
934 the final link phase handle it. */
dc810e39
AM		 935 bfd_put_16 (abfd, (bfd_vma) 0xb000,
936 contents + irel->r_vaddr - sec->vma);
252b5132
RH		 937 }
938
939 /* See if there is another R_SH_USES reloc referring to the same
07d6d2b8 940 register load. */
252b5132
RH		 941 for (irelscan = internal_relocs; irelscan < irelend; irelscan++)
942 if (irelscan->r_type == R_SH_USES
943 && laddr == irelscan->r_vaddr - sec->vma + 4 + irelscan->r_offset)
944 break;
945 if (irelscan < irelend)
946 {
947 /* Some other function call depends upon this register load,
948 and we have not yet converted that function call.
949 Indeed, we may never be able to convert it. There is
950 nothing else we can do at this point. */
951 continue;
952 }
953
954 /* Look for a R_SH_COUNT reloc on the location where the
07d6d2b8
AM		 955 function address is stored. Do this before deleting any
956 bytes, to avoid confusion about the address. */
252b5132
RH		 957 for (irelcount = internal_relocs; irelcount < irelend; irelcount++)
958 if (irelcount->r_vaddr == paddr
959 && irelcount->r_type == R_SH_COUNT)
960 break;
961
962 /* Delete the register load. */
963 if (! sh_relax_delete_bytes (abfd, sec, laddr, 2))
964 goto error_return;
965
966 /* That will change things, so, just in case it permits some
07d6d2b8
AM		 967 other function call to come within range, we should relax
968 again. Note that this is not required, and it may be slow. */
b34976b6 969 *again = TRUE;
252b5132
RH		 970
971 /* Now check whether we got a COUNT reloc. */
972 if (irelcount >= irelend)
973 {
4eca0228 974 _bfd_error_handler
695344c0 975 /* xgettext: c-format */
2dcf00ce
AM		 976 (_("%pB: %#" PRIx64 ": warning: could not find expected COUNT reloc"),
977 abfd, (uint64_t) paddr);
252b5132
RH		 978 continue;
979 }
980
981 /* The number of uses is stored in the r_offset field. We've
07d6d2b8 982 just deleted one. */
252b5132
RH		 983 if (irelcount->r_offset == 0)
984 {
695344c0 985 /* xgettext: c-format */
2dcf00ce
AM		 986 _bfd_error_handler (_("%pB: %#" PRIx64 ": warning: bad count"),
987 abfd, (uint64_t) paddr);
252b5132
RH		 988 continue;
989 }
990
991 --irelcount->r_offset;
992
993 /* If there are no more uses, we can delete the address. Reload
07d6d2b8
AM		 994 the address from irelfn, in case it was changed by the
995 previous call to sh_relax_delete_bytes. */
252b5132
RH		 996 if (irelcount->r_offset == 0)
997 {
998 if (! sh_relax_delete_bytes (abfd, sec,
999 irelfn->r_vaddr - sec->vma, 4))
1000 goto error_return;
1001 }
1002
1003 /* We've done all we can with that function call. */
1004 }
1005
1006 /* Look for load and store instructions that we can align on four
1007 byte boundaries. */
1008 if (have_code)
1009 {
b34976b6 1010 bfd_boolean swapped;
252b5132
RH		 1011
1012 /* Get the section contents. */
1013 if (contents == NULL)
1014 {
eea6121a 1015 if (coff_section_data (abfd, sec)->contents != NULL)
252b5132
RH		 1016 contents = coff_section_data (abfd, sec)->contents;
1017 else
1018 {
eea6121a 1019 if (!bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 1020 goto error_return;
1021 }
1022 }
1023
1024 if (! sh_align_loads (abfd, sec, internal_relocs, contents, &swapped))
1025 goto error_return;
1026
1027 if (swapped)
1028 {
252b5132 1029 coff_section_data (abfd, sec)->relocs = internal_relocs;
b34976b6 1030 coff_section_data (abfd, sec)->keep_relocs = TRUE;
252b5132
RH		 1031
1032 coff_section_data (abfd, sec)->contents = contents;
b34976b6 1033 coff_section_data (abfd, sec)->keep_contents = TRUE;
252b5132 1034
b34976b6 1035 obj_coff_keep_syms (abfd) = TRUE;
252b5132
RH		 1036 }
1037 }
1038
eea6121a
AM		 1039 if (internal_relocs != NULL
1040 && internal_relocs != coff_section_data (abfd, sec)->relocs)
252b5132 1041 {
eea6121a
AM		 1042 if (! link_info->keep_memory)
1043 free (internal_relocs);
1044 else
1045 coff_section_data (abfd, sec)->relocs = internal_relocs;
252b5132
RH		 1046 }
1047
eea6121a 1048 if (contents != NULL && contents != coff_section_data (abfd, sec)->contents)
252b5132
RH		 1049 {
1050 if (! link_info->keep_memory)
eea6121a 1051 free (contents);
252b5132 1052 else
eea6121a
AM		 1053 /* Cache the section contents for coff_link_input_bfd. */
1054 coff_section_data (abfd, sec)->contents = contents;
252b5132
RH		 1055 }
1056
b34976b6 1057 return TRUE;
252b5132
RH		 1058
1059 error_return:
eea6121a
AM		 1060 if (internal_relocs != NULL
1061 && internal_relocs != coff_section_data (abfd, sec)->relocs)
1062 free (internal_relocs);
1063 if (contents != NULL && contents != coff_section_data (abfd, sec)->contents)
1064 free (contents);
b34976b6 1065 return FALSE;
252b5132
RH		 1066}
1067
1068/* Delete some bytes from a section while relaxing. */
1069
b34976b6 1070static bfd_boolean
2c3fc389
NC		 1071sh_relax_delete_bytes (bfd *abfd,
1072 asection *sec,
1073 bfd_vma addr,
1074 int count)
252b5132
RH		 1075{
1076 bfd_byte *contents;
1077 struct internal_reloc *irel, *irelend;
1078 struct internal_reloc *irelalign;
1079 bfd_vma toaddr;
1080 bfd_byte *esym, *esymend;
1081 bfd_size_type symesz;
1082 struct coff_link_hash_entry **sym_hash;
1083 asection *o;
1084
1085 contents = coff_section_data (abfd, sec)->contents;
1086
de194d85 1087 /* The deletion must stop at the next ALIGN reloc for an alignment
252b5132
RH		 1088 power larger than the number of bytes we are deleting. */
1089
1090 irelalign = NULL;
eea6121a 1091 toaddr = sec->size;
252b5132
RH		 1092
1093 irel = coff_section_data (abfd, sec)->relocs;
1094 irelend = irel + sec->reloc_count;
1095 for (; irel < irelend; irel++)
1096 {
1097 if (irel->r_type == R_SH_ALIGN
1098 && irel->r_vaddr - sec->vma > addr
1099 && count < (1 << irel->r_offset))
1100 {
1101 irelalign = irel;
1102 toaddr = irel->r_vaddr - sec->vma;
1103 break;
1104 }
1105 }
1106
1107 /* Actually delete the bytes. */
dc810e39
AM		 1108 memmove (contents + addr, contents + addr + count,
1109 (size_t) (toaddr - addr - count));
252b5132 1110 if (irelalign == NULL)
eea6121a 1111 sec->size -= count;
252b5132
RH		 1112 else
1113 {
1114 int i;
1115
1116#define NOP_OPCODE (0x0009)
1117
1118 BFD_ASSERT ((count & 1) == 0);
1119 for (i = 0; i < count; i += 2)
dc810e39 1120 bfd_put_16 (abfd, (bfd_vma) NOP_OPCODE, contents + toaddr - count + i);
252b5132
RH		 1121 }
1122
1123 /* Adjust all the relocs. */
1124 for (irel = coff_section_data (abfd, sec)->relocs; irel < irelend; irel++)
1125 {
1126 bfd_vma nraddr, stop;
1127 bfd_vma start = 0;
1128 int insn = 0;
1129 struct internal_syment sym;
1130 int off, adjust, oinsn;
1131 bfd_signed_vma voff = 0;
b34976b6 1132 bfd_boolean overflow;
252b5132
RH		 1133
1134 /* Get the new reloc address. */
1135 nraddr = irel->r_vaddr - sec->vma;
1136 if ((irel->r_vaddr - sec->vma > addr
1137 && irel->r_vaddr - sec->vma < toaddr)
1138 || (irel->r_type == R_SH_ALIGN
1139 && irel->r_vaddr - sec->vma == toaddr))
1140 nraddr -= count;
1141
1142 /* See if this reloc was for the bytes we have deleted, in which
1143 case we no longer care about it. Don't delete relocs which
1144 represent addresses, though. */
1145 if (irel->r_vaddr - sec->vma >= addr
1146 && irel->r_vaddr - sec->vma < addr + count
1147 && irel->r_type != R_SH_ALIGN
1148 && irel->r_type != R_SH_CODE
1149 && irel->r_type != R_SH_DATA
1150 && irel->r_type != R_SH_LABEL)
1151 irel->r_type = R_SH_UNUSED;
1152
1153 /* If this is a PC relative reloc, see if the range it covers
07d6d2b8 1154 includes the bytes we have deleted. */
252b5132
RH		 1155 switch (irel->r_type)
1156 {
1157 default:
1158 break;
1159
1160 case R_SH_PCDISP8BY2:
1161 case R_SH_PCDISP:
1162 case R_SH_PCRELIMM8BY2:
1163 case R_SH_PCRELIMM8BY4:
1164 start = irel->r_vaddr - sec->vma;
1165 insn = bfd_get_16 (abfd, contents + nraddr);
1166 break;
1167 }
1168
1169 switch (irel->r_type)
1170 {
1171 default:
1172 start = stop = addr;
1173 break;
1174
1175 case R_SH_IMM32:
17505c5c
NC		 1176#ifdef COFF_WITH_PE
1177 case R_SH_IMM32CE:
1178 case R_SH_IMAGEBASE:
1179#endif
252b5132 1180 /* If this reloc is against a symbol defined in this
07d6d2b8
AM		 1181 section, and the symbol will not be adjusted below, we
1182 must check the addend to see it will put the value in
1183 range to be adjusted, and hence must be changed. */
252b5132
RH		 1184 bfd_coff_swap_sym_in (abfd,
1185 ((bfd_byte *) obj_coff_external_syms (abfd)
1186 + (irel->r_symndx
1187 * bfd_coff_symesz (abfd))),
1188 &sym);
1189 if (sym.n_sclass != C_EXT
1190 && sym.n_scnum == sec->target_index
1191 && ((bfd_vma) sym.n_value <= addr
1192 || (bfd_vma) sym.n_value >= toaddr))
1193 {
1194 bfd_vma val;
1195
1196 val = bfd_get_32 (abfd, contents + nraddr);
1197 val += sym.n_value;
1198 if (val > addr && val < toaddr)
1199 bfd_put_32 (abfd, val - count, contents + nraddr);
1200 }
1201 start = stop = addr;
1202 break;
1203
1204 case R_SH_PCDISP8BY2:
1205 off = insn & 0xff;
1206 if (off & 0x80)
1207 off -= 0x100;
1208 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1209 break;
1210
1211 case R_SH_PCDISP:
1212 bfd_coff_swap_sym_in (abfd,
1213 ((bfd_byte *) obj_coff_external_syms (abfd)
1214 + (irel->r_symndx
1215 * bfd_coff_symesz (abfd))),
1216 &sym);
1217 if (sym.n_sclass == C_EXT)
1218 start = stop = addr;
1219 else
1220 {
1221 off = insn & 0xfff;
1222 if (off & 0x800)
1223 off -= 0x1000;
1224 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1225 }
1226 break;
1227
1228 case R_SH_PCRELIMM8BY2:
1229 off = insn & 0xff;
1230 stop = start + 4 + off * 2;
1231 break;
1232
1233 case R_SH_PCRELIMM8BY4:
1234 off = insn & 0xff;
1235 stop = (start &~ (bfd_vma) 3) + 4 + off * 4;
1236 break;
1237
1238 case R_SH_SWITCH8:
1239 case R_SH_SWITCH16:
1240 case R_SH_SWITCH32:
1241 /* These relocs types represent
1242 .word L2-L1
1243 The r_offset field holds the difference between the reloc
1244 address and L1. That is the start of the reloc, and
1245 adding in the contents gives us the top. We must adjust
1246 both the r_offset field and the section contents. */
1247
1248 start = irel->r_vaddr - sec->vma;
1249 stop = (bfd_vma) ((bfd_signed_vma) start - (long) irel->r_offset);
1250
1251 if (start > addr
1252 && start < toaddr
1253 && (stop <= addr || stop >= toaddr))
1254 irel->r_offset += count;
1255 else if (stop > addr
1256 && stop < toaddr
1257 && (start <= addr || start >= toaddr))
1258 irel->r_offset -= count;
1259
1260 start = stop;
1261
1262 if (irel->r_type == R_SH_SWITCH16)
1263 voff = bfd_get_signed_16 (abfd, contents + nraddr);
1264 else if (irel->r_type == R_SH_SWITCH8)
1265 voff = bfd_get_8 (abfd, contents + nraddr);
1266 else
1267 voff = bfd_get_signed_32 (abfd, contents + nraddr);
1268 stop = (bfd_vma) ((bfd_signed_vma) start + voff);
1269
1270 break;
1271
1272 case R_SH_USES:
1273 start = irel->r_vaddr - sec->vma;
1274 stop = (bfd_vma) ((bfd_signed_vma) start
1275 + (long) irel->r_offset
1276 + 4);
1277 break;
1278 }
1279
1280 if (start > addr
1281 && start < toaddr
1282 && (stop <= addr || stop >= toaddr))
1283 adjust = count;
1284 else if (stop > addr
1285 && stop < toaddr
1286 && (start <= addr || start >= toaddr))
1287 adjust = - count;
1288 else
1289 adjust = 0;
1290
1291 if (adjust != 0)
1292 {
1293 oinsn = insn;
b34976b6 1294 overflow = FALSE;
252b5132
RH		 1295 switch (irel->r_type)
1296 {
1297 default:
1298 abort ();
1299 break;
1300
1301 case R_SH_PCDISP8BY2:
1302 case R_SH_PCRELIMM8BY2:
1303 insn += adjust / 2;
1304 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 1305 overflow = TRUE;
dc810e39 1306 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1307 break;
1308
1309 case R_SH_PCDISP:
1310 insn += adjust / 2;
1311 if ((oinsn & 0xf000) != (insn & 0xf000))
b34976b6 1312 overflow = TRUE;
dc810e39 1313 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1314 break;
1315
1316 case R_SH_PCRELIMM8BY4:
1317 BFD_ASSERT (adjust == count || count >= 4);
1318 if (count >= 4)
1319 insn += adjust / 4;
1320 else
1321 {
1322 if ((irel->r_vaddr & 3) == 0)
1323 ++insn;
1324 }
1325 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 1326 overflow = TRUE;
dc810e39 1327 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1328 break;
1329
1330 case R_SH_SWITCH8:
1331 voff += adjust;
1332 if (voff < 0 || voff >= 0xff)
b34976b6 1333 overflow = TRUE;
dc810e39 1334 bfd_put_8 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1335 break;
1336
1337 case R_SH_SWITCH16:
1338 voff += adjust;
1339 if (voff < - 0x8000 || voff >= 0x8000)
b34976b6 1340 overflow = TRUE;
dc810e39 1341 bfd_put_signed_16 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1342 break;
1343
1344 case R_SH_SWITCH32:
1345 voff += adjust;
dc810e39 1346 bfd_put_signed_32 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1347 break;
1348
1349 case R_SH_USES:
1350 irel->r_offset += adjust;
1351 break;
1352 }
1353
1354 if (overflow)
1355 {
4eca0228 1356 _bfd_error_handler
695344c0 1357 /* xgettext: c-format */
2dcf00ce
AM		 1358 (_("%pB: %#" PRIx64 ": fatal: reloc overflow while relaxing"),
1359 abfd, (uint64_t) irel->r_vaddr);
252b5132 1360 bfd_set_error (bfd_error_bad_value);
b34976b6 1361 return FALSE;
252b5132
RH		 1362 }
1363 }
1364
1365 irel->r_vaddr = nraddr + sec->vma;
1366 }
1367
1368 /* Look through all the other sections. If there contain any IMM32
1369 relocs against internal symbols which we are not going to adjust
1370 below, we may need to adjust the addends. */
1371 for (o = abfd->sections; o != NULL; o = o->next)
1372 {
1373 struct internal_reloc *internal_relocs;
1374 struct internal_reloc *irelscan, *irelscanend;
1375 bfd_byte *ocontents;
1376
1377 if (o == sec
1378 || (o->flags & SEC_RELOC) == 0
1379 || o->reloc_count == 0)
1380 continue;
1381
1382 /* We always cache the relocs. Perhaps, if info->keep_memory is
07d6d2b8
AM		 1383 FALSE, we should free them, if we are permitted to, when we
1384 leave sh_coff_relax_section. */
252b5132 1385 internal_relocs = (_bfd_coff_read_internal_relocs
b34976b6 1386 (abfd, o, TRUE, (bfd_byte *) NULL, FALSE,
252b5132
RH		 1387 (struct internal_reloc *) NULL));
1388 if (internal_relocs == NULL)
b34976b6 1389 return FALSE;
252b5132
RH		 1390
1391 ocontents = NULL;
1392 irelscanend = internal_relocs + o->reloc_count;
1393 for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++)
1394 {
1395 struct internal_syment sym;
1396
17505c5c
NC		 1397#ifdef COFF_WITH_PE
1398 if (irelscan->r_type != R_SH_IMM32
1399 && irelscan->r_type != R_SH_IMAGEBASE
1400 && irelscan->r_type != R_SH_IMM32CE)
1401#else
252b5132 1402 if (irelscan->r_type != R_SH_IMM32)
17505c5c 1403#endif
252b5132
RH		 1404 continue;
1405
1406 bfd_coff_swap_sym_in (abfd,
1407 ((bfd_byte *) obj_coff_external_syms (abfd)
1408 + (irelscan->r_symndx
1409 * bfd_coff_symesz (abfd))),
1410 &sym);
1411 if (sym.n_sclass != C_EXT
1412 && sym.n_scnum == sec->target_index
1413 && ((bfd_vma) sym.n_value <= addr
1414 || (bfd_vma) sym.n_value >= toaddr))
1415 {
1416 bfd_vma val;
1417
1418 if (ocontents == NULL)
1419 {
1420 if (coff_section_data (abfd, o)->contents != NULL)
1421 ocontents = coff_section_data (abfd, o)->contents;
1422 else
1423 {
eea6121a
AM		 1424 if (!bfd_malloc_and_get_section (abfd, o, &ocontents))
1425 return FALSE;
252b5132 1426 /* We always cache the section contents.
07d6d2b8
AM		 1427 Perhaps, if info->keep_memory is FALSE, we
1428 should free them, if we are permitted to,
1429 when we leave sh_coff_relax_section. */
252b5132
RH		 1430 coff_section_data (abfd, o)->contents = ocontents;
1431 }
1432 }
1433
1434 val = bfd_get_32 (abfd, ocontents + irelscan->r_vaddr - o->vma);
1435 val += sym.n_value;
1436 if (val > addr && val < toaddr)
1437 bfd_put_32 (abfd, val - count,
1438 ocontents + irelscan->r_vaddr - o->vma);
1439
b34976b6 1440 coff_section_data (abfd, o)->keep_contents = TRUE;
252b5132
RH		 1441 }
1442 }
1443 }
1444
1445 /* Adjusting the internal symbols will not work if something has
1446 already retrieved the generic symbols. It would be possible to
1447 make this work by adjusting the generic symbols at the same time.
1448 However, this case should not arise in normal usage. */
1449 if (obj_symbols (abfd) != NULL
1450 || obj_raw_syments (abfd) != NULL)
1451 {
4eca0228 1452 _bfd_error_handler
871b3ab2 1453 (_("%pB: fatal: generic symbols retrieved before relaxing"), abfd);
252b5132 1454 bfd_set_error (bfd_error_invalid_operation);
b34976b6 1455 return FALSE;
252b5132
RH		 1456 }
1457
1458 /* Adjust all the symbols. */
1459 sym_hash = obj_coff_sym_hashes (abfd);
1460 symesz = bfd_coff_symesz (abfd);
1461 esym = (bfd_byte *) obj_coff_external_syms (abfd);
1462 esymend = esym + obj_raw_syment_count (abfd) * symesz;
1463 while (esym < esymend)
1464 {
1465 struct internal_syment isym;
1466
2c3fc389 1467 bfd_coff_swap_sym_in (abfd, esym, &isym);
252b5132
RH		 1468
1469 if (isym.n_scnum == sec->target_index
1470 && (bfd_vma) isym.n_value > addr
1471 && (bfd_vma) isym.n_value < toaddr)
1472 {
1473 isym.n_value -= count;
1474
2c3fc389 1475 bfd_coff_swap_sym_out (abfd, &isym, esym);
252b5132
RH		 1476
1477 if (*sym_hash != NULL)
1478 {
1479 BFD_ASSERT ((*sym_hash)->root.type == bfd_link_hash_defined
1480 || (*sym_hash)->root.type == bfd_link_hash_defweak);
1481 BFD_ASSERT ((*sym_hash)->root.u.def.value >= addr
1482 && (*sym_hash)->root.u.def.value < toaddr);
1483 (*sym_hash)->root.u.def.value -= count;
1484 }
1485 }
1486
1487 esym += (isym.n_numaux + 1) * symesz;
1488 sym_hash += isym.n_numaux + 1;
1489 }
1490
1491 /* See if we can move the ALIGN reloc forward. We have adjusted
1492 r_vaddr for it already. */
1493 if (irelalign != NULL)
1494 {
1495 bfd_vma alignto, alignaddr;
1496
1497 alignto = BFD_ALIGN (toaddr, 1 << irelalign->r_offset);
1498 alignaddr = BFD_ALIGN (irelalign->r_vaddr - sec->vma,
1499 1 << irelalign->r_offset);
1500 if (alignto != alignaddr)
1501 {
1502 /* Tail recursion. */
1503 return sh_relax_delete_bytes (abfd, sec, alignaddr,
dc810e39 1504 (int) (alignto - alignaddr));
252b5132
RH		 1505 }
1506 }
1507
b34976b6 1508 return TRUE;
252b5132
RH		 1509}
1510\f
1511/* This is yet another version of the SH opcode table, used to rapidly
1512 get information about a particular instruction. */
1513
1514/* The opcode map is represented by an array of these structures. The
1515 array is indexed by the high order four bits in the instruction. */
1516
1517struct sh_major_opcode
1518{
1519 /* A pointer to the instruction list. This is an array which
1520 contains all the instructions with this major opcode. */
1521 const struct sh_minor_opcode *minor_opcodes;
1522 /* The number of elements in minor_opcodes. */
1523 unsigned short count;
1524};
1525
1526/* This structure holds information for a set of SH opcodes. The
1527 instruction code is anded with the mask value, and the resulting
1528 value is used to search the order opcode list. */
1529
1530struct sh_minor_opcode
1531{
1532 /* The sorted opcode list. */
1533 const struct sh_opcode *opcodes;
1534 /* The number of elements in opcodes. */
1535 unsigned short count;
1536 /* The mask value to use when searching the opcode list. */
1537 unsigned short mask;
1538};
1539
1540/* This structure holds information for an SH instruction. An array
1541 of these structures is sorted in order by opcode. */
1542
1543struct sh_opcode
1544{
1545 /* The code for this instruction, after it has been anded with the
1546 mask value in the sh_major_opcode structure. */
1547 unsigned short opcode;
1548 /* Flags for this instruction. */
86033394 1549 unsigned long flags;
252b5132
RH		 1550};
1551
1552/* Flag which appear in the sh_opcode structure. */
1553
1554/* This instruction loads a value from memory. */
1555#define LOAD (0x1)
1556
1557/* This instruction stores a value to memory. */
1558#define STORE (0x2)
1559
1560/* This instruction is a branch. */
1561#define BRANCH (0x4)
1562
1563/* This instruction has a delay slot. */
1564#define DELAY (0x8)
1565
1566/* This instruction uses the value in the register in the field at
1567 mask 0x0f00 of the instruction. */
1568#define USES1 (0x10)
84dcfba7 1569#define USES1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1570
1571/* This instruction uses the value in the register in the field at
1572 mask 0x00f0 of the instruction. */
1573#define USES2 (0x20)
84dcfba7 1574#define USES2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1575
1576/* This instruction uses the value in register 0. */
1577#define USESR0 (0x40)
1578
1579/* This instruction sets the value in the register in the field at
1580 mask 0x0f00 of the instruction. */
1581#define SETS1 (0x80)
84dcfba7 1582#define SETS1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1583
1584/* This instruction sets the value in the register in the field at
1585 mask 0x00f0 of the instruction. */
1586#define SETS2 (0x100)
84dcfba7 1587#define SETS2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1588
1589/* This instruction sets register 0. */
1590#define SETSR0 (0x200)
1591
1592/* This instruction sets a special register. */
1593#define SETSSP (0x400)
1594
1595/* This instruction uses a special register. */
1596#define USESSP (0x800)
1597
1598/* This instruction uses the floating point register in the field at
1599 mask 0x0f00 of the instruction. */
1600#define USESF1 (0x1000)
84dcfba7 1601#define USESF1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1602
1603/* This instruction uses the floating point register in the field at
1604 mask 0x00f0 of the instruction. */
1605#define USESF2 (0x2000)
84dcfba7 1606#define USESF2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1607
1608/* This instruction uses floating point register 0. */
1609#define USESF0 (0x4000)
1610
1611/* This instruction sets the floating point register in the field at
1612 mask 0x0f00 of the instruction. */
1613#define SETSF1 (0x8000)
84dcfba7 1614#define SETSF1_REG(x) ((x & 0x0f00) >> 8)
252b5132 1615
d4845d57
JR		 1616#define USESAS (0x10000)
1617#define USESAS_REG(x) (((((x) >> 8) - 2) & 3) + 2)
1618#define USESR8 (0x20000)
1619#define SETSAS (0x40000)
1620#define SETSAS_REG(x) USESAS_REG (x)
1621
8d6ad26e
AM		 1622#define MAP(a) a, sizeof a / sizeof a[0]
1623
86033394 1624#ifndef COFF_IMAGE_WITH_PE
252b5132 1625
8d6ad26e 1626/* The opcode maps. */
252b5132
RH		 1627
1628static const struct sh_opcode sh_opcode00[] =
1629{
1630 { 0x0008, SETSSP }, /* clrt */
1631 { 0x0009, 0 }, /* nop */
1632 { 0x000b, BRANCH | DELAY | USESSP }, /* rts */
1633 { 0x0018, SETSSP }, /* sett */
1634 { 0x0019, SETSSP }, /* div0u */
1635 { 0x001b, 0 }, /* sleep */
1636 { 0x0028, SETSSP }, /* clrmac */
1637 { 0x002b, BRANCH | DELAY | SETSSP }, /* rte */
1638 { 0x0038, USESSP | SETSSP }, /* ldtlb */
1639 { 0x0048, SETSSP }, /* clrs */
1640 { 0x0058, SETSSP } /* sets */
1641};
1642
1643static const struct sh_opcode sh_opcode01[] =
1644{
252b5132
RH		 1645 { 0x0003, BRANCH | DELAY | USES1 | SETSSP }, /* bsrf rn */
1646 { 0x000a, SETS1 | USESSP }, /* sts mach,rn */
252b5132 1647 { 0x001a, SETS1 | USESSP }, /* sts macl,rn */
252b5132
RH		 1648 { 0x0023, BRANCH | DELAY | USES1 }, /* braf rn */
1649 { 0x0029, SETS1 | USESSP }, /* movt rn */
1650 { 0x002a, SETS1 | USESSP }, /* sts pr,rn */
d4845d57
JR		 1651 { 0x005a, SETS1 | USESSP }, /* sts fpul,rn */
1652 { 0x006a, SETS1 | USESSP }, /* sts fpscr,rn / sts dsr,rn */
1653 { 0x0083, LOAD | USES1 }, /* pref @rn */
1654 { 0x007a, SETS1 | USESSP }, /* sts a0,rn */
1655 { 0x008a, SETS1 | USESSP }, /* sts x0,rn */
1656 { 0x009a, SETS1 | USESSP }, /* sts x1,rn */
1657 { 0x00aa, SETS1 | USESSP }, /* sts y0,rn */
1658 { 0x00ba, SETS1 | USESSP } /* sts y1,rn */
1659};
1660
252b5132
RH		 1661static const struct sh_opcode sh_opcode02[] =
1662{
d4845d57 1663 { 0x0002, SETS1 | USESSP }, /* stc <special_reg>,rn */
252b5132
RH		 1664 { 0x0004, STORE | USES1 | USES2 | USESR0 }, /* mov.b rm,@(r0,rn) */
1665 { 0x0005, STORE | USES1 | USES2 | USESR0 }, /* mov.w rm,@(r0,rn) */
1666 { 0x0006, STORE | USES1 | USES2 | USESR0 }, /* mov.l rm,@(r0,rn) */
1667 { 0x0007, SETSSP | USES1 | USES2 }, /* mul.l rm,rn */
1668 { 0x000c, LOAD | SETS1 | USES2 | USESR0 }, /* mov.b @(r0,rm),rn */
1669 { 0x000d, LOAD | SETS1 | USES2 | USESR0 }, /* mov.w @(r0,rm),rn */
1670 { 0x000e, LOAD | SETS1 | USES2 | USESR0 }, /* mov.l @(r0,rm),rn */
1671 { 0x000f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.l @rm+,@rn+ */
1672};
1673
1674static const struct sh_minor_opcode sh_opcode0[] =
1675{
1676 { MAP (sh_opcode00), 0xffff },
1677 { MAP (sh_opcode01), 0xf0ff },
1678 { MAP (sh_opcode02), 0xf00f }
1679};
1680
1681static const struct sh_opcode sh_opcode10[] =
1682{
1683 { 0x1000, STORE | USES1 | USES2 } /* mov.l rm,@(disp,rn) */
1684};
1685
1686static const struct sh_minor_opcode sh_opcode1[] =
1687{
1688 { MAP (sh_opcode10), 0xf000 }
1689};
1690
1691static const struct sh_opcode sh_opcode20[] =
1692{
1693 { 0x2000, STORE | USES1 | USES2 }, /* mov.b rm,@rn */
1694 { 0x2001, STORE | USES1 | USES2 }, /* mov.w rm,@rn */
1695 { 0x2002, STORE | USES1 | USES2 }, /* mov.l rm,@rn */
1696 { 0x2004, STORE | SETS1 | USES1 | USES2 }, /* mov.b rm,@-rn */
1697 { 0x2005, STORE | SETS1 | USES1 | USES2 }, /* mov.w rm,@-rn */
1698 { 0x2006, STORE | SETS1 | USES1 | USES2 }, /* mov.l rm,@-rn */
1699 { 0x2007, SETSSP | USES1 | USES2 | USESSP }, /* div0s */
1700 { 0x2008, SETSSP | USES1 | USES2 }, /* tst rm,rn */
1701 { 0x2009, SETS1 | USES1 | USES2 }, /* and rm,rn */
1702 { 0x200a, SETS1 | USES1 | USES2 }, /* xor rm,rn */
1703 { 0x200b, SETS1 | USES1 | USES2 }, /* or rm,rn */
1704 { 0x200c, SETSSP | USES1 | USES2 }, /* cmp/str rm,rn */
1705 { 0x200d, SETS1 | USES1 | USES2 }, /* xtrct rm,rn */
1706 { 0x200e, SETSSP | USES1 | USES2 }, /* mulu.w rm,rn */
1707 { 0x200f, SETSSP | USES1 | USES2 } /* muls.w rm,rn */
1708};
1709
1710static const struct sh_minor_opcode sh_opcode2[] =
1711{
1712 { MAP (sh_opcode20), 0xf00f }
1713};
1714
1715static const struct sh_opcode sh_opcode30[] =
1716{
1717 { 0x3000, SETSSP | USES1 | USES2 }, /* cmp/eq rm,rn */
1718 { 0x3002, SETSSP | USES1 | USES2 }, /* cmp/hs rm,rn */
1719 { 0x3003, SETSSP | USES1 | USES2 }, /* cmp/ge rm,rn */
1720 { 0x3004, SETSSP | USESSP | USES1 | USES2 }, /* div1 rm,rn */
1721 { 0x3005, SETSSP | USES1 | USES2 }, /* dmulu.l rm,rn */
1722 { 0x3006, SETSSP | USES1 | USES2 }, /* cmp/hi rm,rn */
1723 { 0x3007, SETSSP | USES1 | USES2 }, /* cmp/gt rm,rn */
1724 { 0x3008, SETS1 | USES1 | USES2 }, /* sub rm,rn */
1725 { 0x300a, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* subc rm,rn */
1726 { 0x300b, SETS1 | SETSSP | USES1 | USES2 }, /* subv rm,rn */
1727 { 0x300c, SETS1 | USES1 | USES2 }, /* add rm,rn */
1728 { 0x300d, SETSSP | USES1 | USES2 }, /* dmuls.l rm,rn */
1729 { 0x300e, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* addc rm,rn */
1730 { 0x300f, SETS1 | SETSSP | USES1 | USES2 } /* addv rm,rn */
1731};
1732
1733static const struct sh_minor_opcode sh_opcode3[] =
1734{
1735 { MAP (sh_opcode30), 0xf00f }
1736};
1737
1738static const struct sh_opcode sh_opcode40[] =
1739{
1740 { 0x4000, SETS1 | SETSSP | USES1 }, /* shll rn */
1741 { 0x4001, SETS1 | SETSSP | USES1 }, /* shlr rn */
1742 { 0x4002, STORE | SETS1 | USES1 | USESSP }, /* sts.l mach,@-rn */
252b5132
RH		 1743 { 0x4004, SETS1 | SETSSP | USES1 }, /* rotl rn */
1744 { 0x4005, SETS1 | SETSSP | USES1 }, /* rotr rn */
1745 { 0x4006, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,mach */
252b5132
RH		 1746 { 0x4008, SETS1 | USES1 }, /* shll2 rn */
1747 { 0x4009, SETS1 | USES1 }, /* shlr2 rn */
1748 { 0x400a, SETSSP | USES1 }, /* lds rm,mach */
1749 { 0x400b, BRANCH | DELAY | USES1 }, /* jsr @rn */
252b5132
RH		 1750 { 0x4010, SETS1 | SETSSP | USES1 }, /* dt rn */
1751 { 0x4011, SETSSP | USES1 }, /* cmp/pz rn */
1752 { 0x4012, STORE | SETS1 | USES1 | USESSP }, /* sts.l macl,@-rn */
d4845d57 1753 { 0x4014, SETSSP | USES1 }, /* setrc rm */
252b5132
RH		 1754 { 0x4015, SETSSP | USES1 }, /* cmp/pl rn */
1755 { 0x4016, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,macl */
252b5132
RH		 1756 { 0x4018, SETS1 | USES1 }, /* shll8 rn */
1757 { 0x4019, SETS1 | USES1 }, /* shlr8 rn */
1758 { 0x401a, SETSSP | USES1 }, /* lds rm,macl */
1759 { 0x401b, LOAD | SETSSP | USES1 }, /* tas.b @rn */
252b5132
RH		 1760 { 0x4020, SETS1 | SETSSP | USES1 }, /* shal rn */
1761 { 0x4021, SETS1 | SETSSP | USES1 }, /* shar rn */
1762 { 0x4022, STORE | SETS1 | USES1 | USESSP }, /* sts.l pr,@-rn */
252b5132
RH		 1763 { 0x4024, SETS1 | SETSSP | USES1 | USESSP }, /* rotcl rn */
1764 { 0x4025, SETS1 | SETSSP | USES1 | USESSP }, /* rotcr rn */
1765 { 0x4026, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,pr */
252b5132
RH		 1766 { 0x4028, SETS1 | USES1 }, /* shll16 rn */
1767 { 0x4029, SETS1 | USES1 }, /* shlr16 rn */
1768 { 0x402a, SETSSP | USES1 }, /* lds rm,pr */
1769 { 0x402b, BRANCH | DELAY | USES1 }, /* jmp @rn */
d4845d57
JR		 1770 { 0x4052, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpul,@-rn */
1771 { 0x4056, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpul */
1772 { 0x405a, SETSSP | USES1 }, /* lds.l rm,fpul */
1773 { 0x4062, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpscr / dsr,@-rn */
1774 { 0x4066, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpscr / dsr */
1775 { 0x406a, SETSSP | USES1 }, /* lds rm,fpscr / lds rm,dsr */
1776 { 0x4072, STORE | SETS1 | USES1 | USESSP }, /* sts.l a0,@-rn */
1777 { 0x4076, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,a0 */
1778 { 0x407a, SETSSP | USES1 }, /* lds.l rm,a0 */
1779 { 0x4082, STORE | SETS1 | USES1 | USESSP }, /* sts.l x0,@-rn */
1780 { 0x4086, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x0 */
1781 { 0x408a, SETSSP | USES1 }, /* lds.l rm,x0 */
1782 { 0x4092, STORE | SETS1 | USES1 | USESSP }, /* sts.l x1,@-rn */
1783 { 0x4096, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x1 */
1784 { 0x409a, SETSSP | USES1 }, /* lds.l rm,x1 */
1785 { 0x40a2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y0,@-rn */
1786 { 0x40a6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y0 */
1787 { 0x40aa, SETSSP | USES1 }, /* lds.l rm,y0 */
1788 { 0x40b2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y1,@-rn */
1789 { 0x40b6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y1 */
1790 { 0x40ba, SETSSP | USES1 } /* lds.l rm,y1 */
252b5132
RH		 1791};
1792
1793static const struct sh_opcode sh_opcode41[] =
1794{
d4845d57
JR		 1795 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l <special_reg>,@-rn */
1796 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,<special_reg> */
1797 { 0x400c, SETS1 | USES1 | USES2 }, /* shad rm,rn */
1798 { 0x400d, SETS1 | USES1 | USES2 }, /* shld rm,rn */
1799 { 0x400e, SETSSP | USES1 }, /* ldc rm,<special_reg> */
252b5132
RH		 1800 { 0x400f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.w @rm+,@rn+ */
1801};
1802
1803static const struct sh_minor_opcode sh_opcode4[] =
1804{
1805 { MAP (sh_opcode40), 0xf0ff },
d4845d57 1806 { MAP (sh_opcode41), 0xf00f }
252b5132
RH		 1807};
1808
1809static const struct sh_opcode sh_opcode50[] =
1810{
1811 { 0x5000, LOAD | SETS1 | USES2 } /* mov.l @(disp,rm),rn */
1812};
1813
1814static const struct sh_minor_opcode sh_opcode5[] =
1815{
1816 { MAP (sh_opcode50), 0xf000 }
1817};
1818
1819static const struct sh_opcode sh_opcode60[] =
1820{
1821 { 0x6000, LOAD | SETS1 | USES2 }, /* mov.b @rm,rn */
1822 { 0x6001, LOAD | SETS1 | USES2 }, /* mov.w @rm,rn */
1823 { 0x6002, LOAD | SETS1 | USES2 }, /* mov.l @rm,rn */
1824 { 0x6003, SETS1 | USES2 }, /* mov rm,rn */
1825 { 0x6004, LOAD | SETS1 | SETS2 | USES2 }, /* mov.b @rm+,rn */
1826 { 0x6005, LOAD | SETS1 | SETS2 | USES2 }, /* mov.w @rm+,rn */
1827 { 0x6006, LOAD | SETS1 | SETS2 | USES2 }, /* mov.l @rm+,rn */
1828 { 0x6007, SETS1 | USES2 }, /* not rm,rn */
1829 { 0x6008, SETS1 | USES2 }, /* swap.b rm,rn */
1830 { 0x6009, SETS1 | USES2 }, /* swap.w rm,rn */
1831 { 0x600a, SETS1 | SETSSP | USES2 | USESSP }, /* negc rm,rn */
1832 { 0x600b, SETS1 | USES2 }, /* neg rm,rn */
1833 { 0x600c, SETS1 | USES2 }, /* extu.b rm,rn */
1834 { 0x600d, SETS1 | USES2 }, /* extu.w rm,rn */
1835 { 0x600e, SETS1 | USES2 }, /* exts.b rm,rn */
1836 { 0x600f, SETS1 | USES2 } /* exts.w rm,rn */
1837};
1838
1839static const struct sh_minor_opcode sh_opcode6[] =
1840{
1841 { MAP (sh_opcode60), 0xf00f }
1842};
1843
1844static const struct sh_opcode sh_opcode70[] =
1845{
1846 { 0x7000, SETS1 | USES1 } /* add #imm,rn */
1847};
1848
1849static const struct sh_minor_opcode sh_opcode7[] =
1850{
1851 { MAP (sh_opcode70), 0xf000 }
1852};
1853
1854static const struct sh_opcode sh_opcode80[] =
1855{
1856 { 0x8000, STORE | USES2 | USESR0 }, /* mov.b r0,@(disp,rn) */
1857 { 0x8100, STORE | USES2 | USESR0 }, /* mov.w r0,@(disp,rn) */
d4845d57 1858 { 0x8200, SETSSP }, /* setrc #imm */
252b5132
RH		 1859 { 0x8400, LOAD | SETSR0 | USES2 }, /* mov.b @(disp,rm),r0 */
1860 { 0x8500, LOAD | SETSR0 | USES2 }, /* mov.w @(disp,rn),r0 */
1861 { 0x8800, SETSSP | USESR0 }, /* cmp/eq #imm,r0 */
1862 { 0x8900, BRANCH | USESSP }, /* bt label */
1863 { 0x8b00, BRANCH | USESSP }, /* bf label */
d4845d57 1864 { 0x8c00, SETSSP }, /* ldrs @(disp,pc) */
252b5132 1865 { 0x8d00, BRANCH | DELAY | USESSP }, /* bt/s label */
d4845d57 1866 { 0x8e00, SETSSP }, /* ldre @(disp,pc) */
252b5132
RH		 1867 { 0x8f00, BRANCH | DELAY | USESSP } /* bf/s label */
1868};
1869
1870static const struct sh_minor_opcode sh_opcode8[] =
1871{
1872 { MAP (sh_opcode80), 0xff00 }
1873};
1874
1875static const struct sh_opcode sh_opcode90[] =
1876{
1877 { 0x9000, LOAD | SETS1 } /* mov.w @(disp,pc),rn */
1878};
1879
1880static const struct sh_minor_opcode sh_opcode9[] =
1881{
1882 { MAP (sh_opcode90), 0xf000 }
1883};
1884
1885static const struct sh_opcode sh_opcodea0[] =
1886{
1887 { 0xa000, BRANCH | DELAY } /* bra label */
1888};
1889
1890static const struct sh_minor_opcode sh_opcodea[] =
1891{
1892 { MAP (sh_opcodea0), 0xf000 }
1893};
1894
1895static const struct sh_opcode sh_opcodeb0[] =
1896{
1897 { 0xb000, BRANCH | DELAY } /* bsr label */
1898};
1899
1900static const struct sh_minor_opcode sh_opcodeb[] =
1901{
1902 { MAP (sh_opcodeb0), 0xf000 }
1903};
1904
1905static const struct sh_opcode sh_opcodec0[] =
1906{
1907 { 0xc000, STORE | USESR0 | USESSP }, /* mov.b r0,@(disp,gbr) */
1908 { 0xc100, STORE | USESR0 | USESSP }, /* mov.w r0,@(disp,gbr) */
1909 { 0xc200, STORE | USESR0 | USESSP }, /* mov.l r0,@(disp,gbr) */
1910 { 0xc300, BRANCH | USESSP }, /* trapa #imm */
1911 { 0xc400, LOAD | SETSR0 | USESSP }, /* mov.b @(disp,gbr),r0 */
1912 { 0xc500, LOAD | SETSR0 | USESSP }, /* mov.w @(disp,gbr),r0 */
1913 { 0xc600, LOAD | SETSR0 | USESSP }, /* mov.l @(disp,gbr),r0 */
1914 { 0xc700, SETSR0 }, /* mova @(disp,pc),r0 */
1915 { 0xc800, SETSSP | USESR0 }, /* tst #imm,r0 */
1916 { 0xc900, SETSR0 | USESR0 }, /* and #imm,r0 */
1917 { 0xca00, SETSR0 | USESR0 }, /* xor #imm,r0 */
1918 { 0xcb00, SETSR0 | USESR0 }, /* or #imm,r0 */
1919 { 0xcc00, LOAD | SETSSP | USESR0 | USESSP }, /* tst.b #imm,@(r0,gbr) */
1920 { 0xcd00, LOAD | STORE | USESR0 | USESSP }, /* and.b #imm,@(r0,gbr) */
1921 { 0xce00, LOAD | STORE | USESR0 | USESSP }, /* xor.b #imm,@(r0,gbr) */
1922 { 0xcf00, LOAD | STORE | USESR0 | USESSP } /* or.b #imm,@(r0,gbr) */
1923};
1924
1925static const struct sh_minor_opcode sh_opcodec[] =
1926{
1927 { MAP (sh_opcodec0), 0xff00 }
1928};
1929
1930static const struct sh_opcode sh_opcoded0[] =
1931{
1932 { 0xd000, LOAD | SETS1 } /* mov.l @(disp,pc),rn */
1933};
1934
1935static const struct sh_minor_opcode sh_opcoded[] =
1936{
1937 { MAP (sh_opcoded0), 0xf000 }
1938};
1939
1940static const struct sh_opcode sh_opcodee0[] =
1941{
1942 { 0xe000, SETS1 } /* mov #imm,rn */
1943};
1944
1945static const struct sh_minor_opcode sh_opcodee[] =
1946{
1947 { MAP (sh_opcodee0), 0xf000 }
1948};
1949
1950static const struct sh_opcode sh_opcodef0[] =
1951{
1952 { 0xf000, SETSF1 | USESF1 | USESF2 }, /* fadd fm,fn */
1953 { 0xf001, SETSF1 | USESF1 | USESF2 }, /* fsub fm,fn */
1954 { 0xf002, SETSF1 | USESF1 | USESF2 }, /* fmul fm,fn */
1955 { 0xf003, SETSF1 | USESF1 | USESF2 }, /* fdiv fm,fn */
1956 { 0xf004, SETSSP | USESF1 | USESF2 }, /* fcmp/eq fm,fn */
1957 { 0xf005, SETSSP | USESF1 | USESF2 }, /* fcmp/gt fm,fn */
1958 { 0xf006, LOAD | SETSF1 | USES2 | USESR0 }, /* fmov.s @(r0,rm),fn */
1959 { 0xf007, STORE | USES1 | USESF2 | USESR0 }, /* fmov.s fm,@(r0,rn) */
1960 { 0xf008, LOAD | SETSF1 | USES2 }, /* fmov.s @rm,fn */
1961 { 0xf009, LOAD | SETS2 | SETSF1 | USES2 }, /* fmov.s @rm+,fn */
1962 { 0xf00a, STORE | USES1 | USESF2 }, /* fmov.s fm,@rn */
1963 { 0xf00b, STORE | SETS1 | USES1 | USESF2 }, /* fmov.s fm,@-rn */
1964 { 0xf00c, SETSF1 | USESF2 }, /* fmov fm,fn */
1965 { 0xf00e, SETSF1 | USESF1 | USESF2 | USESF0 } /* fmac f0,fm,fn */
1966};
1967
1968static const struct sh_opcode sh_opcodef1[] =
1969{
1970 { 0xf00d, SETSF1 | USESSP }, /* fsts fpul,fn */
1971 { 0xf01d, SETSSP | USESF1 }, /* flds fn,fpul */
1972 { 0xf02d, SETSF1 | USESSP }, /* float fpul,fn */
1973 { 0xf03d, SETSSP | USESF1 }, /* ftrc fn,fpul */
1974 { 0xf04d, SETSF1 | USESF1 }, /* fneg fn */
1975 { 0xf05d, SETSF1 | USESF1 }, /* fabs fn */
1976 { 0xf06d, SETSF1 | USESF1 }, /* fsqrt fn */
1977 { 0xf07d, SETSSP | USESF1 }, /* ftst/nan fn */
1978 { 0xf08d, SETSF1 }, /* fldi0 fn */
1979 { 0xf09d, SETSF1 } /* fldi1 fn */
1980};
1981
1982static const struct sh_minor_opcode sh_opcodef[] =
1983{
1984 { MAP (sh_opcodef0), 0xf00f },
1985 { MAP (sh_opcodef1), 0xf0ff }
1986};
1987
d4845d57 1988static struct sh_major_opcode sh_opcodes[] =
252b5132
RH		 1989{
1990 { MAP (sh_opcode0) },
1991 { MAP (sh_opcode1) },
1992 { MAP (sh_opcode2) },
1993 { MAP (sh_opcode3) },
1994 { MAP (sh_opcode4) },
1995 { MAP (sh_opcode5) },
1996 { MAP (sh_opcode6) },
1997 { MAP (sh_opcode7) },
1998 { MAP (sh_opcode8) },
1999 { MAP (sh_opcode9) },
2000 { MAP (sh_opcodea) },
2001 { MAP (sh_opcodeb) },
2002 { MAP (sh_opcodec) },
2003 { MAP (sh_opcoded) },
2004 { MAP (sh_opcodee) },
2005 { MAP (sh_opcodef) }
2006};
2007
d4845d57
JR		 2008/* The double data transfer / parallel processing insns are not
2009 described here. This will cause sh_align_load_span to leave them alone. */
2010
2011static const struct sh_opcode sh_dsp_opcodef0[] =
2012{
2013 { 0xf400, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @-as,ds */
2014 { 0xf401, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@-as */
2015 { 0xf404, USESAS | LOAD | SETSSP }, /* movs.x @as,ds */
2016 { 0xf405, USESAS | STORE | USESSP }, /* movs.x ds,@as */
2017 { 0xf408, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @as+,ds */
2018 { 0xf409, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@as+ */
2019 { 0xf40c, USESAS | SETSAS | LOAD | SETSSP | USESR8 }, /* movs.x @as+r8,ds */
2020 { 0xf40d, USESAS | SETSAS | STORE | USESSP | USESR8 } /* movs.x ds,@as+r8 */
2021};
2022
2023static const struct sh_minor_opcode sh_dsp_opcodef[] =
2024{
2025 { MAP (sh_dsp_opcodef0), 0xfc0d }
2026};
2027
252b5132
RH		 2028/* Given an instruction, return a pointer to the corresponding
2029 sh_opcode structure. Return NULL if the instruction is not
2030 recognized. */
2031
2032static const struct sh_opcode *
2c3fc389 2033sh_insn_info (unsigned int insn)
252b5132
RH		 2034{
2035 const struct sh_major_opcode *maj;
2036 const struct sh_minor_opcode *min, *minend;
2037
2038 maj = &sh_opcodes[(insn & 0xf000) >> 12];
2039 min = maj->minor_opcodes;
2040 minend = min + maj->count;
2041 for (; min < minend; min++)
2042 {
2043 unsigned int l;
2044 const struct sh_opcode *op, *opend;
2045
2046 l = insn & min->mask;
2047 op = min->opcodes;
2048 opend = op + min->count;
2049
2050 /* Since the opcodes tables are sorted, we could use a binary
07d6d2b8 2051 search here if the count were above some cutoff value. */
252b5132
RH		 2052 for (; op < opend; op++)
2053 if (op->opcode == l)
2054 return op;
2055 }
2056
cbfe05c4 2057 return NULL;
252b5132
RH		 2058}
2059
2060/* See whether an instruction uses a general purpose register. */
2061
b34976b6 2062static bfd_boolean
2c3fc389
NC		 2063sh_insn_uses_reg (unsigned int insn,
2064 const struct sh_opcode *op,
2065 unsigned int reg)
252b5132
RH		 2066{
2067 unsigned int f;
2068
2069 f = op->flags;
2070
2071 if ((f & USES1) != 0
84dcfba7 2072 && USES1_REG (insn) == reg)
b34976b6 2073 return TRUE;
252b5132 2074 if ((f & USES2) != 0
84dcfba7 2075 && USES2_REG (insn) == reg)
b34976b6 2076 return TRUE;
252b5132
RH		 2077 if ((f & USESR0) != 0
2078 && reg == 0)
b34976b6 2079 return TRUE;
d4845d57 2080 if ((f & USESAS) && reg == USESAS_REG (insn))
b34976b6 2081 return TRUE;
d4845d57 2082 if ((f & USESR8) && reg == 8)
b34976b6 2083 return TRUE;
252b5132 2084
b34976b6 2085 return FALSE;
252b5132 2086}
17505c5c 2087
84dcfba7
JR		 2088/* See whether an instruction sets a general purpose register. */
2089
b34976b6 2090static bfd_boolean
2c3fc389
NC		 2091sh_insn_sets_reg (unsigned int insn,
2092 const struct sh_opcode *op,
2093 unsigned int reg)
84dcfba7
JR		 2094{
2095 unsigned int f;
2096
2097 f = op->flags;
2098
2099 if ((f & SETS1) != 0
2100 && SETS1_REG (insn) == reg)
b34976b6 2101 return TRUE;
84dcfba7
JR		 2102 if ((f & SETS2) != 0
2103 && SETS2_REG (insn) == reg)
b34976b6 2104 return TRUE;
84dcfba7
JR		 2105 if ((f & SETSR0) != 0
2106 && reg == 0)
b34976b6 2107 return TRUE;
d4845d57 2108 if ((f & SETSAS) && reg == SETSAS_REG (insn))
b34976b6 2109 return TRUE;
84dcfba7 2110
b34976b6 2111 return FALSE;
84dcfba7
JR		 2112}
2113
2c3fc389 2114/* See whether an instruction uses or sets a general purpose register */
84dcfba7 2115
b34976b6 2116static bfd_boolean
2c3fc389
NC		 2117sh_insn_uses_or_sets_reg (unsigned int insn,
2118 const struct sh_opcode *op,
2119 unsigned int reg)
84dcfba7 2120{
2c3fc389 2121 if (sh_insn_uses_reg (insn, op, reg))
b34976b6 2122 return TRUE;
84dcfba7 2123
2c3fc389 2124 return sh_insn_sets_reg (insn, op, reg);
84dcfba7 2125}
252b5132
RH		 2126
2127/* See whether an instruction uses a floating point register. */
2128
b34976b6 2129static bfd_boolean
2c3fc389
NC		 2130sh_insn_uses_freg (unsigned int insn,
2131 const struct sh_opcode *op,
2132 unsigned int freg)
252b5132
RH		 2133{
2134 unsigned int f;
2135
2136 f = op->flags;
2137
2138 /* We can't tell if this is a double-precision insn, so just play safe
2139 and assume that it might be. So not only have we test FREG against
2140 itself, but also even FREG against FREG+1 - if the using insn uses
2141 just the low part of a double precision value - but also an odd
2142 FREG against FREG-1 - if the setting insn sets just the low part
2143 of a double precision value.
2144 So what this all boils down to is that we have to ignore the lowest
2145 bit of the register number. */
cbfe05c4 2146
252b5132 2147 if ((f & USESF1) != 0
84dcfba7 2148 && (USESF1_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2149 return TRUE;
252b5132 2150 if ((f & USESF2) != 0
84dcfba7 2151 && (USESF2_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2152 return TRUE;
252b5132
RH		 2153 if ((f & USESF0) != 0
2154 && freg == 0)
b34976b6 2155 return TRUE;
252b5132 2156
b34976b6 2157 return FALSE;
252b5132
RH		 2158}
2159
84dcfba7
JR		 2160/* See whether an instruction sets a floating point register. */
2161
b34976b6 2162static bfd_boolean
2c3fc389
NC		 2163sh_insn_sets_freg (unsigned int insn,
2164 const struct sh_opcode *op,
2165 unsigned int freg)
84dcfba7
JR		 2166{
2167 unsigned int f;
2168
2169 f = op->flags;
2170
2171 /* We can't tell if this is a double-precision insn, so just play safe
2172 and assume that it might be. So not only have we test FREG against
2173 itself, but also even FREG against FREG+1 - if the using insn uses
2174 just the low part of a double precision value - but also an odd
2175 FREG against FREG-1 - if the setting insn sets just the low part
2176 of a double precision value.
2177 So what this all boils down to is that we have to ignore the lowest
2178 bit of the register number. */
cbfe05c4 2179
84dcfba7
JR		 2180 if ((f & SETSF1) != 0
2181 && (SETSF1_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2182 return TRUE;
84dcfba7 2183
b34976b6 2184 return FALSE;
84dcfba7
JR		 2185}
2186
2c3fc389
NC		 2187/* See whether an instruction uses or sets a floating point register */
2188
2189static bfd_boolean
2190sh_insn_uses_or_sets_freg (unsigned int insn,
2191 const struct sh_opcode *op,
2192 unsigned int reg)
2193{
2194 if (sh_insn_uses_freg (insn, op, reg))
2195 return TRUE;
2196
2197 return sh_insn_sets_freg (insn, op, reg);
2198}
2199
252b5132
RH		 2200/* See whether instructions I1 and I2 conflict, assuming I1 comes
2201 before I2. OP1 and OP2 are the corresponding sh_opcode structures.
b34976b6 2202 This should return TRUE if there is a conflict, or FALSE if the
252b5132
RH		 2203 instructions can be swapped safely. */
2204
b34976b6 2205static bfd_boolean
2c3fc389
NC		 2206sh_insns_conflict (unsigned int i1,
2207 const struct sh_opcode *op1,
2208 unsigned int i2,
2209 const struct sh_opcode *op2)
252b5132
RH		 2210{
2211 unsigned int f1, f2;
2212
2213 f1 = op1->flags;
2214 f2 = op2->flags;
2215
2216 /* Load of fpscr conflicts with floating point operations.
2217 FIXME: shouldn't test raw opcodes here. */
2218 if (((i1 & 0xf0ff) == 0x4066 && (i2 & 0xf000) == 0xf000)
2219 || ((i2 & 0xf0ff) == 0x4066 && (i1 & 0xf000) == 0xf000))
b34976b6 2220 return TRUE;
252b5132
RH		 2221
2222 if ((f1 & (BRANCH | DELAY)) != 0
2223 || (f2 & (BRANCH | DELAY)) != 0)
b34976b6 2224 return TRUE;
252b5132 2225
84dcfba7
JR		 2226 if (((f1 | f2) & SETSSP)
2227 && (f1 & (SETSSP | USESSP))
2228 && (f2 & (SETSSP | USESSP)))
b34976b6 2229 return TRUE;
252b5132
RH		 2230
2231 if ((f1 & SETS1) != 0
84dcfba7 2232 && sh_insn_uses_or_sets_reg (i2, op2, SETS1_REG (i1)))
b34976b6 2233 return TRUE;
252b5132 2234 if ((f1 & SETS2) != 0
84dcfba7 2235 && sh_insn_uses_or_sets_reg (i2, op2, SETS2_REG (i1)))
b34976b6 2236 return TRUE;
252b5132 2237 if ((f1 & SETSR0) != 0
84dcfba7 2238 && sh_insn_uses_or_sets_reg (i2, op2, 0))
b34976b6 2239 return TRUE;
d4845d57
JR		 2240 if ((f1 & SETSAS)
2241 && sh_insn_uses_or_sets_reg (i2, op2, SETSAS_REG (i1)))
b34976b6 2242 return TRUE;
252b5132 2243 if ((f1 & SETSF1) != 0
84dcfba7 2244 && sh_insn_uses_or_sets_freg (i2, op2, SETSF1_REG (i1)))
b34976b6 2245 return TRUE;
252b5132
RH		 2246
2247 if ((f2 & SETS1) != 0
84dcfba7 2248 && sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2)))
b34976b6 2249 return TRUE;
252b5132 2250 if ((f2 & SETS2) != 0
84dcfba7 2251 && sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2)))
b34976b6 2252 return TRUE;
252b5132 2253 if ((f2 & SETSR0) != 0
84dcfba7 2254 && sh_insn_uses_or_sets_reg (i1, op1, 0))
b34976b6 2255 return TRUE;
d4845d57
JR		 2256 if ((f2 & SETSAS)
2257 && sh_insn_uses_or_sets_reg (i1, op1, SETSAS_REG (i2)))
b34976b6 2258 return TRUE;
252b5132 2259 if ((f2 & SETSF1) != 0
84dcfba7 2260 && sh_insn_uses_or_sets_freg (i1, op1, SETSF1_REG (i2)))
b34976b6 2261 return TRUE;
252b5132
RH		 2262
2263 /* The instructions do not conflict. */
b34976b6 2264 return FALSE;
252b5132
RH		 2265}
2266
2267/* I1 is a load instruction, and I2 is some other instruction. Return
b34976b6 2268 TRUE if I1 loads a register which I2 uses. */
252b5132 2269
b34976b6 2270static bfd_boolean
2c3fc389
NC		 2271sh_load_use (unsigned int i1,
2272 const struct sh_opcode *op1,
2273 unsigned int i2,
2274 const struct sh_opcode *op2)
252b5132
RH		 2275{
2276 unsigned int f1;
2277
2278 f1 = op1->flags;
2279
2280 if ((f1 & LOAD) == 0)
b34976b6 2281 return FALSE;
252b5132
RH		 2282
2283 /* If both SETS1 and SETSSP are set, that means a load to a special
2284 register using postincrement addressing mode, which we don't care
2285 about here. */
2286 if ((f1 & SETS1) != 0
2287 && (f1 & SETSSP) == 0
2288 && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
b34976b6 2289 return TRUE;
252b5132
RH		 2290
2291 if ((f1 & SETSR0) != 0
2292 && sh_insn_uses_reg (i2, op2, 0))
b34976b6 2293 return TRUE;
252b5132
RH		 2294
2295 if ((f1 & SETSF1) != 0
2296 && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
b34976b6 2297 return TRUE;
252b5132 2298
b34976b6 2299 return FALSE;
252b5132
RH		 2300}
2301
2302/* Try to align loads and stores within a span of memory. This is
2303 called by both the ELF and the COFF sh targets. ABFD and SEC are
2304 the BFD and section we are examining. CONTENTS is the contents of
2305 the section. SWAP is the routine to call to swap two instructions.
2306 RELOCS is a pointer to the internal relocation information, to be
2307 passed to SWAP. PLABEL is a pointer to the current label in a
2308 sorted list of labels; LABEL_END is the end of the list. START and
2309 STOP are the range of memory to examine. If a swap is made,
b34976b6 2310 *PSWAPPED is set to TRUE. */
252b5132 2311
86033394
NC		 2312#ifdef COFF_WITH_PE
2313static
2314#endif
b34976b6 2315bfd_boolean
2c3fc389
NC		 2316_bfd_sh_align_load_span (bfd *abfd,
2317 asection *sec,
2318 bfd_byte *contents,
2319 bfd_boolean (*swap) (bfd *, asection *, void *, bfd_byte *, bfd_vma),
2320 void * relocs,
2321 bfd_vma **plabel,
2322 bfd_vma *label_end,
2323 bfd_vma start,
2324 bfd_vma stop,
2325 bfd_boolean *pswapped)
252b5132 2326{
d4845d57
JR		 2327 int dsp = (abfd->arch_info->mach == bfd_mach_sh_dsp
2328 || abfd->arch_info->mach == bfd_mach_sh3_dsp);
252b5132
RH		 2329 bfd_vma i;
2330
d4845d57
JR		 2331 /* The SH4 has a Harvard architecture, hence aligning loads is not
2332 desirable. In fact, it is counter-productive, since it interferes
2333 with the schedules generated by the compiler. */
2334 if (abfd->arch_info->mach == bfd_mach_sh4)
b34976b6 2335 return TRUE;
d4845d57
JR		 2336
2337 /* If we are linking sh[3]-dsp code, swap the FPU instructions for DSP
2338 instructions. */
2339 if (dsp)
2340 {
2341 sh_opcodes[0xf].minor_opcodes = sh_dsp_opcodef;
4c0160b8 2342 sh_opcodes[0xf].count = sizeof sh_dsp_opcodef / sizeof sh_dsp_opcodef [0];
d4845d57
JR		 2343 }
2344
252b5132
RH		 2345 /* Instructions should be aligned on 2 byte boundaries. */
2346 if ((start & 1) == 1)
2347 ++start;
2348
2349 /* Now look through the unaligned addresses. */
2350 i = start;
2351 if ((i & 2) == 0)
2352 i += 2;
2353 for (; i < stop; i += 4)
2354 {
2355 unsigned int insn;
2356 const struct sh_opcode *op;
2357 unsigned int prev_insn = 0;
2358 const struct sh_opcode *prev_op = NULL;
2359
2360 insn = bfd_get_16 (abfd, contents + i);
2361 op = sh_insn_info (insn);
2362 if (op == NULL
2363 || (op->flags & (LOAD | STORE)) == 0)
2364 continue;
2365
2366 /* This is a load or store which is not on a four byte boundary. */
2367
2368 while (*plabel < label_end && **plabel < i)
2369 ++*plabel;
2370
2371 if (i > start)
2372 {
2373 prev_insn = bfd_get_16 (abfd, contents + i - 2);
d4845d57
JR		 2374 /* If INSN is the field b of a parallel processing insn, it is not
2375 a load / store after all. Note that the test here might mistake
2376 the field_b of a pcopy insn for the starting code of a parallel
2377 processing insn; this might miss a swapping opportunity, but at
2378 least we're on the safe side. */
2379 if (dsp && (prev_insn & 0xfc00) == 0xf800)
2380 continue;
2381
2382 /* Check if prev_insn is actually the field b of a parallel
2383 processing insn. Again, this can give a spurious match
2384 after a pcopy. */
2385 if (dsp && i - 2 > start)
2386 {
2387 unsigned pprev_insn = bfd_get_16 (abfd, contents + i - 4);
cbfe05c4 2388
d4845d57
JR		 2389 if ((pprev_insn & 0xfc00) == 0xf800)
2390 prev_op = NULL;
2391 else
2392 prev_op = sh_insn_info (prev_insn);
2393 }
2394 else
2395 prev_op = sh_insn_info (prev_insn);
252b5132
RH		 2396
2397 /* If the load/store instruction is in a delay slot, we
2398 can't swap. */
2399 if (prev_op == NULL
2400 || (prev_op->flags & DELAY) != 0)
2401 continue;
2402 }
2403 if (i > start
2404 && (*plabel >= label_end || **plabel != i)
2405 && prev_op != NULL
2406 && (prev_op->flags & (LOAD | STORE)) == 0
2407 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2408 {
b34976b6 2409 bfd_boolean ok;
252b5132
RH		 2410
2411 /* The load/store instruction does not have a label, and
2412 there is a previous instruction; PREV_INSN is not
2413 itself a load/store instruction, and PREV_INSN and
2414 INSN do not conflict. */
2415
b34976b6 2416 ok = TRUE;
252b5132
RH		 2417
2418 if (i >= start + 4)
2419 {
2420 unsigned int prev2_insn;
2421 const struct sh_opcode *prev2_op;
2422
2423 prev2_insn = bfd_get_16 (abfd, contents + i - 4);
2424 prev2_op = sh_insn_info (prev2_insn);
2425
2426 /* If the instruction before PREV_INSN has a delay
2427 slot--that is, PREV_INSN is in a delay slot--we
2428 can not swap. */
2429 if (prev2_op == NULL
2430 || (prev2_op->flags & DELAY) != 0)
b34976b6 2431 ok = FALSE;
252b5132
RH		 2432
2433 /* If the instruction before PREV_INSN is a load,
2434 and it sets a register which INSN uses, then
2435 putting INSN immediately after PREV_INSN will
2436 cause a pipeline bubble, so there is no point to
2437 making the swap. */
2438 if (ok
2439 && (prev2_op->flags & LOAD) != 0
2440 && sh_load_use (prev2_insn, prev2_op, insn, op))
b34976b6 2441 ok = FALSE;
252b5132
RH		 2442 }
2443
2444 if (ok)
2445 {
2446 if (! (*swap) (abfd, sec, relocs, contents, i - 2))
b34976b6
AM		 2447 return FALSE;
2448 *pswapped = TRUE;
252b5132
RH		 2449 continue;
2450 }
2451 }
2452
2453 while (*plabel < label_end && **plabel < i + 2)
2454 ++*plabel;
2455
2456 if (i + 2 < stop
2457 && (*plabel >= label_end || **plabel != i + 2))
2458 {
2459 unsigned int next_insn;
2460 const struct sh_opcode *next_op;
2461
2462 /* There is an instruction after the load/store
2463 instruction, and it does not have a label. */
2464 next_insn = bfd_get_16 (abfd, contents + i + 2);
2465 next_op = sh_insn_info (next_insn);
2466 if (next_op != NULL
2467 && (next_op->flags & (LOAD | STORE)) == 0
2468 && ! sh_insns_conflict (insn, op, next_insn, next_op))
2469 {
b34976b6 2470 bfd_boolean ok;
252b5132
RH		 2471
2472 /* NEXT_INSN is not itself a load/store instruction,
2473 and it does not conflict with INSN. */
2474
b34976b6 2475 ok = TRUE;
252b5132
RH		 2476
2477 /* If PREV_INSN is a load, and it sets a register
2478 which NEXT_INSN uses, then putting NEXT_INSN
2479 immediately after PREV_INSN will cause a pipeline
2480 bubble, so there is no reason to make this swap. */
2481 if (prev_op != NULL
2482 && (prev_op->flags & LOAD) != 0
2483 && sh_load_use (prev_insn, prev_op, next_insn, next_op))
b34976b6 2484 ok = FALSE;
252b5132
RH		 2485
2486 /* If INSN is a load, and it sets a register which
2487 the insn after NEXT_INSN uses, then doing the
2488 swap will cause a pipeline bubble, so there is no
2489 reason to make the swap. However, if the insn
2490 after NEXT_INSN is itself a load or store
2491 instruction, then it is misaligned, so
2492 optimistically hope that it will be swapped
2493 itself, and just live with the pipeline bubble if
2494 it isn't. */
2495 if (ok
2496 && i + 4 < stop
2497 && (op->flags & LOAD) != 0)
2498 {
2499 unsigned int next2_insn;
2500 const struct sh_opcode *next2_op;
2501
2502 next2_insn = bfd_get_16 (abfd, contents + i + 4);
2503 next2_op = sh_insn_info (next2_insn);
230d6d81
NC		 2504 if (next2_op == NULL
2505 || ((next2_op->flags & (LOAD | STORE)) == 0
2506 && sh_load_use (insn, op, next2_insn, next2_op)))
b34976b6 2507 ok = FALSE;
252b5132
RH		 2508 }
2509
2510 if (ok)
2511 {
2512 if (! (*swap) (abfd, sec, relocs, contents, i))
b34976b6
AM		 2513 return FALSE;
2514 *pswapped = TRUE;
252b5132
RH		 2515 continue;
2516 }
2517 }
2518 }
2519 }
2520
b34976b6 2521 return TRUE;
252b5132 2522}
86033394 2523#endif /* not COFF_IMAGE_WITH_PE */
252b5132 2524
252b5132
RH		 2525/* Swap two SH instructions. */
2526
b34976b6 2527static bfd_boolean
2c3fc389
NC		 2528sh_swap_insns (bfd * abfd,
2529 asection * sec,
2530 void * relocs,
2531 bfd_byte * contents,
2532 bfd_vma addr)
252b5132
RH		 2533{
2534 struct internal_reloc *internal_relocs = (struct internal_reloc *) relocs;
2535 unsigned short i1, i2;
2536 struct internal_reloc *irel, *irelend;
2537
2538 /* Swap the instructions themselves. */
2539 i1 = bfd_get_16 (abfd, contents + addr);
2540 i2 = bfd_get_16 (abfd, contents + addr + 2);
dc810e39
AM		 2541 bfd_put_16 (abfd, (bfd_vma) i2, contents + addr);
2542 bfd_put_16 (abfd, (bfd_vma) i1, contents + addr + 2);
252b5132
RH		 2543
2544 /* Adjust all reloc addresses. */
2545 irelend = internal_relocs + sec->reloc_count;
2546 for (irel = internal_relocs; irel < irelend; irel++)
2547 {
2548 int type, add;
2549
2550 /* There are a few special types of relocs that we don't want to
07d6d2b8
AM		 2551 adjust. These relocs do not apply to the instruction itself,
2552 but are only associated with the address. */
252b5132
RH		 2553 type = irel->r_type;
2554 if (type == R_SH_ALIGN
2555 || type == R_SH_CODE
2556 || type == R_SH_DATA
2557 || type == R_SH_LABEL)
2558 continue;
2559
2560 /* If an R_SH_USES reloc points to one of the addresses being
07d6d2b8
AM		 2561 swapped, we must adjust it. It would be incorrect to do this
2562 for a jump, though, since we want to execute both
2563 instructions after the jump. (We have avoided swapping
2564 around a label, so the jump will not wind up executing an
2565 instruction it shouldn't). */
252b5132
RH		 2566 if (type == R_SH_USES)
2567 {
2568 bfd_vma off;
2569
2570 off = irel->r_vaddr - sec->vma + 4 + irel->r_offset;
2571 if (off == addr)
2572 irel->r_offset += 2;
2573 else if (off == addr + 2)
2574 irel->r_offset -= 2;
2575 }
2576
2577 if (irel->r_vaddr - sec->vma == addr)
2578 {
2579 irel->r_vaddr += 2;
2580 add = -2;
2581 }
2582 else if (irel->r_vaddr - sec->vma == addr + 2)
2583 {
2584 irel->r_vaddr -= 2;
2585 add = 2;
2586 }
2587 else
2588 add = 0;
2589
2590 if (add != 0)
2591 {
2592 bfd_byte *loc;
2593 unsigned short insn, oinsn;
b34976b6 2594 bfd_boolean overflow;
252b5132
RH		 2595
2596 loc = contents + irel->r_vaddr - sec->vma;
b34976b6 2597 overflow = FALSE;
252b5132
RH		 2598 switch (type)
2599 {
2600 default:
2601 break;
2602
2603 case R_SH_PCDISP8BY2:
2604 case R_SH_PCRELIMM8BY2:
2605 insn = bfd_get_16 (abfd, loc);
2606 oinsn = insn;
2607 insn += add / 2;
2608 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 2609 overflow = TRUE;
dc810e39 2610 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2611 break;
2612
2613 case R_SH_PCDISP:
2614 insn = bfd_get_16 (abfd, loc);
2615 oinsn = insn;
2616 insn += add / 2;
2617 if ((oinsn & 0xf000) != (insn & 0xf000))
b34976b6 2618 overflow = TRUE;
dc810e39 2619 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2620 break;
2621
2622 case R_SH_PCRELIMM8BY4:
2623 /* This reloc ignores the least significant 3 bits of
07d6d2b8
AM		 2624 the program counter before adding in the offset.
2625 This means that if ADDR is at an even address, the
2626 swap will not affect the offset. If ADDR is an at an
2627 odd address, then the instruction will be crossing a
2628 four byte boundary, and must be adjusted. */
252b5132
RH		 2629 if ((addr & 3) != 0)
2630 {
2631 insn = bfd_get_16 (abfd, loc);
2632 oinsn = insn;
2633 insn += add / 2;
2634 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 2635 overflow = TRUE;
dc810e39 2636 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2637 }
2638
2639 break;
2640 }
2641
2642 if (overflow)
2643 {
4eca0228 2644 _bfd_error_handler
695344c0 2645 /* xgettext: c-format */
2dcf00ce
AM		 2646 (_("%pB: %#" PRIx64 ": fatal: reloc overflow while relaxing"),
2647 abfd, (uint64_t) irel->r_vaddr);
252b5132 2648 bfd_set_error (bfd_error_bad_value);
b34976b6 2649 return FALSE;
252b5132
RH		 2650 }
2651 }
2652 }
2653
b34976b6 2654 return TRUE;
252b5132 2655}
2c3fc389
NC		 2656
2657/* Look for loads and stores which we can align to four byte
2658 boundaries. See the longer comment above sh_relax_section for why
2659 this is desirable. This sets *PSWAPPED if some instruction was
2660 swapped. */
2661
2662static bfd_boolean
2663sh_align_loads (bfd *abfd,
2664 asection *sec,
2665 struct internal_reloc *internal_relocs,
2666 bfd_byte *contents,
2667 bfd_boolean *pswapped)
2668{
2669 struct internal_reloc *irel, *irelend;
2670 bfd_vma *labels = NULL;
2671 bfd_vma *label, *label_end;
2672 bfd_size_type amt;
2673
2674 *pswapped = FALSE;
2675
2676 irelend = internal_relocs + sec->reloc_count;
2677
2678 /* Get all the addresses with labels on them. */
2679 amt = (bfd_size_type) sec->reloc_count * sizeof (bfd_vma);
2680 labels = (bfd_vma *) bfd_malloc (amt);
2681 if (labels == NULL)
2682 goto error_return;
2683 label_end = labels;
2684 for (irel = internal_relocs; irel < irelend; irel++)
2685 {
2686 if (irel->r_type == R_SH_LABEL)
2687 {
2688 *label_end = irel->r_vaddr - sec->vma;
2689 ++label_end;
2690 }
2691 }
2692
2693 /* Note that the assembler currently always outputs relocs in
2694 address order. If that ever changes, this code will need to sort
2695 the label values and the relocs. */
2696
2697 label = labels;
2698
2699 for (irel = internal_relocs; irel < irelend; irel++)
2700 {
2701 bfd_vma start, stop;
2702
2703 if (irel->r_type != R_SH_CODE)
2704 continue;
2705
2706 start = irel->r_vaddr - sec->vma;
2707
2708 for (irel++; irel < irelend; irel++)
2709 if (irel->r_type == R_SH_DATA)
2710 break;
2711 if (irel < irelend)
2712 stop = irel->r_vaddr - sec->vma;
2713 else
2714 stop = sec->size;
2715
2716 if (! _bfd_sh_align_load_span (abfd, sec, contents, sh_swap_insns,
2717 internal_relocs, &label,
2718 label_end, start, stop, pswapped))
2719 goto error_return;
2720 }
2721
2722 free (labels);
2723
2724 return TRUE;
2725
2726 error_return:
2727 if (labels != NULL)
2728 free (labels);
2729 return FALSE;
2730}
252b5132
RH		 2731\f
2732/* This is a modification of _bfd_coff_generic_relocate_section, which
2733 will handle SH relaxing. */
2734
b34976b6 2735static bfd_boolean
2c3fc389
NC		 2736sh_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
2737 struct bfd_link_info *info,
2738 bfd *input_bfd,
2739 asection *input_section,
2740 bfd_byte *contents,
2741 struct internal_reloc *relocs,
2742 struct internal_syment *syms,
2743 asection **sections)
252b5132
RH		 2744{
2745 struct internal_reloc *rel;
2746 struct internal_reloc *relend;
2747
2748 rel = relocs;
2749 relend = rel + input_section->reloc_count;
2750 for (; rel < relend; rel++)
2751 {
2752 long symndx;
2753 struct coff_link_hash_entry *h;
2754 struct internal_syment *sym;
2755 bfd_vma addend;
2756 bfd_vma val;
2757 reloc_howto_type *howto;
2758 bfd_reloc_status_type rstat;
2759
2760 /* Almost all relocs have to do with relaxing. If any work must
07d6d2b8 2761 be done for them, it has been done in sh_relax_section. */
252b5132 2762 if (rel->r_type != R_SH_IMM32
17505c5c
NC		 2763#ifdef COFF_WITH_PE
2764 && rel->r_type != R_SH_IMM32CE
2765 && rel->r_type != R_SH_IMAGEBASE
2766#endif
252b5132
RH		 2767 && rel->r_type != R_SH_PCDISP)
2768 continue;
2769
2770 symndx = rel->r_symndx;
2771
2772 if (symndx == -1)
2773 {
2774 h = NULL;
2775 sym = NULL;
2776 }
2777 else
cbfe05c4 2778 {
252b5132
RH		 2779 if (symndx < 0
2780 || (unsigned long) symndx >= obj_raw_syment_count (input_bfd))
2781 {
4eca0228 2782 _bfd_error_handler
695344c0 2783 /* xgettext: c-format */
871b3ab2 2784 (_("%pB: illegal symbol index %ld in relocs"),
d003868e 2785 input_bfd, symndx);
252b5132 2786 bfd_set_error (bfd_error_bad_value);
b34976b6 2787 return FALSE;
252b5132
RH		 2788 }
2789 h = obj_coff_sym_hashes (input_bfd)[symndx];
2790 sym = syms + symndx;
2791 }
2792
2793 if (sym != NULL && sym->n_scnum != 0)
2794 addend = - sym->n_value;
2795 else
2796 addend = 0;
2797
2798 if (rel->r_type == R_SH_PCDISP)
2799 addend -= 4;
2800
2801 if (rel->r_type >= SH_COFF_HOWTO_COUNT)
2802 howto = NULL;
2803 else
2804 howto = &sh_coff_howtos[rel->r_type];
2805
2806 if (howto == NULL)
2807 {
2808 bfd_set_error (bfd_error_bad_value);
b34976b6 2809 return FALSE;
252b5132
RH		 2810 }
2811
17505c5c
NC		 2812#ifdef COFF_WITH_PE
2813 if (rel->r_type == R_SH_IMAGEBASE)
2814 addend -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
2815#endif
cbfe05c4 2816
252b5132
RH		 2817 val = 0;
2818
2819 if (h == NULL)
2820 {
2821 asection *sec;
2822
2823 /* There is nothing to do for an internal PCDISP reloc. */
2824 if (rel->r_type == R_SH_PCDISP)
2825 continue;
2826
2827 if (symndx == -1)
2828 {
2829 sec = bfd_abs_section_ptr;
2830 val = 0;
2831 }
2832 else
2833 {
2834 sec = sections[symndx];
07d6d2b8 2835 val = (sec->output_section->vma
252b5132
RH		 2836 + sec->output_offset
2837 + sym->n_value
2838 - sec->vma);
2839 }
2840 }
2841 else
2842 {
2843 if (h->root.type == bfd_link_hash_defined
2844 || h->root.type == bfd_link_hash_defweak)
2845 {
2846 asection *sec;
2847
2848 sec = h->root.u.def.section;
2849 val = (h->root.u.def.value
2850 + sec->output_section->vma
2851 + sec->output_offset);
2852 }
0e1862bb 2853 else if (! bfd_link_relocatable (info))
1a72702b
AM		 2854 (*info->callbacks->undefined_symbol)
2855 (info, h->root.root.string, input_bfd, input_section,
2856 rel->r_vaddr - input_section->vma, TRUE);
252b5132
RH		 2857 }
2858
2859 rstat = _bfd_final_link_relocate (howto, input_bfd, input_section,
2860 contents,
2861 rel->r_vaddr - input_section->vma,
2862 val, addend);
2863
2864 switch (rstat)
2865 {
2866 default:
2867 abort ();
2868 case bfd_reloc_ok:
2869 break;
2870 case bfd_reloc_overflow:
2871 {
2872 const char *name;
2873 char buf[SYMNMLEN + 1];
2874
2875 if (symndx == -1)
2876 name = "*ABS*";
2877 else if (h != NULL)
dfeffb9f 2878 name = NULL;
252b5132
RH		 2879 else if (sym->_n._n_n._n_zeroes == 0
2880 && sym->_n._n_n._n_offset != 0)
2881 name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset;
2882 else
2883 {
07d6d2b8 2884 strncpy (buf, sym->_n._n_name, SYMNMLEN);
252b5132
RH		 2885 buf[SYMNMLEN] = '\0';
2886 name = buf;
2887 }
2888
1a72702b
AM		 2889 (*info->callbacks->reloc_overflow)
2890 (info, (h ? &h->root : NULL), name, howto->name,
2891 (bfd_vma) 0, input_bfd, input_section,
2892 rel->r_vaddr - input_section->vma);
252b5132
RH		 2893 }
2894 }
2895 }
2896
b34976b6 2897 return TRUE;
252b5132
RH		 2898}
2899
2900/* This is a version of bfd_generic_get_relocated_section_contents
2901 which uses sh_relocate_section. */
2902
2903static bfd_byte *
2c3fc389
NC		 2904sh_coff_get_relocated_section_contents (bfd *output_bfd,
2905 struct bfd_link_info *link_info,
2906 struct bfd_link_order *link_order,
2907 bfd_byte *data,
2908 bfd_boolean relocatable,
2909 asymbol **symbols)
252b5132
RH		 2910{
2911 asection *input_section = link_order->u.indirect.section;
2912 bfd *input_bfd = input_section->owner;
2913 asection **sections = NULL;
2914 struct internal_reloc *internal_relocs = NULL;
2915 struct internal_syment *internal_syms = NULL;
2916
2917 /* We only need to handle the case of relaxing, or of having a
2918 particular set of section contents, specially. */
1049f94e 2919 if (relocatable
252b5132
RH		 2920 || coff_section_data (input_bfd, input_section) == NULL
2921 || coff_section_data (input_bfd, input_section)->contents == NULL)
2922 return bfd_generic_get_relocated_section_contents (output_bfd, link_info,
2923 link_order, data,
1049f94e 2924 relocatable,
252b5132
RH		 2925 symbols);
2926
2927 memcpy (data, coff_section_data (input_bfd, input_section)->contents,
eea6121a 2928 (size_t) input_section->size);
252b5132
RH		 2929
2930 if ((input_section->flags & SEC_RELOC) != 0
2931 && input_section->reloc_count > 0)
2932 {
2933 bfd_size_type symesz = bfd_coff_symesz (input_bfd);
2934 bfd_byte *esym, *esymend;
2935 struct internal_syment *isymp;
2936 asection **secpp;
dc810e39 2937 bfd_size_type amt;
252b5132
RH		 2938
2939 if (! _bfd_coff_get_external_symbols (input_bfd))
2940 goto error_return;
2941
2942 internal_relocs = (_bfd_coff_read_internal_relocs
b34976b6
AM		 2943 (input_bfd, input_section, FALSE, (bfd_byte *) NULL,
2944 FALSE, (struct internal_reloc *) NULL));
252b5132
RH		 2945 if (internal_relocs == NULL)
2946 goto error_return;
2947
dc810e39
AM		 2948 amt = obj_raw_syment_count (input_bfd);
2949 amt *= sizeof (struct internal_syment);
2950 internal_syms = (struct internal_syment *) bfd_malloc (amt);
252b5132
RH		 2951 if (internal_syms == NULL)
2952 goto error_return;
2953
dc810e39
AM		 2954 amt = obj_raw_syment_count (input_bfd);
2955 amt *= sizeof (asection *);
2956 sections = (asection **) bfd_malloc (amt);
252b5132
RH		 2957 if (sections == NULL)
2958 goto error_return;
2959
2960 isymp = internal_syms;
2961 secpp = sections;
2962 esym = (bfd_byte *) obj_coff_external_syms (input_bfd);
2963 esymend = esym + obj_raw_syment_count (input_bfd) * symesz;
2964 while (esym < esymend)
2965 {
2c3fc389 2966 bfd_coff_swap_sym_in (input_bfd, esym, isymp);
252b5132
RH		 2967
2968 if (isymp->n_scnum != 0)
2969 *secpp = coff_section_from_bfd_index (input_bfd, isymp->n_scnum);
2970 else
2971 {
2972 if (isymp->n_value == 0)
2973 *secpp = bfd_und_section_ptr;
2974 else
2975 *secpp = bfd_com_section_ptr;
2976 }
2977
2978 esym += (isymp->n_numaux + 1) * symesz;
2979 secpp += isymp->n_numaux + 1;
2980 isymp += isymp->n_numaux + 1;
2981 }
2982
2983 if (! sh_relocate_section (output_bfd, link_info, input_bfd,
2984 input_section, data, internal_relocs,
2985 internal_syms, sections))
2986 goto error_return;
2987
2988 free (sections);
2989 sections = NULL;
2990 free (internal_syms);
2991 internal_syms = NULL;
2992 free (internal_relocs);
2993 internal_relocs = NULL;
2994 }
2995
2996 return data;
2997
2998 error_return:
2999 if (internal_relocs != NULL)
3000 free (internal_relocs);
3001 if (internal_syms != NULL)
3002 free (internal_syms);
3003 if (sections != NULL)
3004 free (sections);
3005 return NULL;
3006}
3007
3008/* The target vectors. */
3009
17505c5c 3010#ifndef TARGET_SHL_SYM
6d00b590 3011CREATE_BIG_COFF_TARGET_VEC (sh_coff_vec, "coff-sh", BFD_IS_RELAXABLE, 0, '_', NULL, COFF_SWAP_TABLE)
17505c5c 3012#endif
252b5132 3013
c3c89269
NC		 3014#ifdef TARGET_SHL_SYM
3015#define TARGET_SYM TARGET_SHL_SYM
3016#else
6d00b590 3017#define TARGET_SYM sh_coff_le_vec
c3c89269 3018#endif
cbfe05c4 3019
c3c89269
NC		 3020#ifndef TARGET_SHL_NAME
3021#define TARGET_SHL_NAME "coff-shl"
3022#endif
252b5132 3023
17505c5c
NC		 3024#ifdef COFF_WITH_PE
3025CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3fa78519 3026 SEC_CODE | SEC_DATA, '_', NULL, COFF_SWAP_TABLE);
17505c5c 3027#else
86033394 3028CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3fa78519 3029 0, '_', NULL, COFF_SWAP_TABLE)
17505c5c 3030#endif
86033394 3031
17505c5c 3032#ifndef TARGET_SHL_SYM
2c3fc389 3033
252b5132
RH		 3034/* Some people want versions of the SH COFF target which do not align
3035 to 16 byte boundaries. We implement that by adding a couple of new
3036 target vectors. These are just like the ones above, but they
3037 change the default section alignment. To generate them in the
3038 assembler, use -small. To use them in the linker, use -b
3039 coff-sh{l}-small and -oformat coff-sh{l}-small.
3040
3041 Yes, this is a horrible hack. A general solution for setting
3042 section alignment in COFF is rather complex. ELF handles this
3043 correctly. */
3044
3045/* Only recognize the small versions if the target was not defaulted.
3046 Otherwise we won't recognize the non default endianness. */
3047
3048static const bfd_target *
2c3fc389 3049coff_small_object_p (bfd *abfd)
252b5132
RH		 3050{
3051 if (abfd->target_defaulted)
3052 {
3053 bfd_set_error (bfd_error_wrong_format);
3054 return NULL;
3055 }
3056 return coff_object_p (abfd);
3057}
3058
3059/* Set the section alignment for the small versions. */
3060
b34976b6 3061static bfd_boolean
2c3fc389 3062coff_small_new_section_hook (bfd *abfd, asection *section)
252b5132
RH		 3063{
3064 if (! coff_new_section_hook (abfd, section))
b34976b6 3065 return FALSE;
252b5132
RH		 3066
3067 /* We must align to at least a four byte boundary, because longword
3068 accesses must be on a four byte boundary. */
3069 if (section->alignment_power == COFF_DEFAULT_SECTION_ALIGNMENT_POWER)
3070 section->alignment_power = 2;
3071
b34976b6 3072 return TRUE;
252b5132
RH		 3073}
3074
3075/* This is copied from bfd_coff_std_swap_table so that we can change
3076 the default section alignment power. */
3077
88183869 3078static bfd_coff_backend_data bfd_coff_small_swap_table =
252b5132
RH		 3079{
3080 coff_swap_aux_in, coff_swap_sym_in, coff_swap_lineno_in,
3081 coff_swap_aux_out, coff_swap_sym_out,
3082 coff_swap_lineno_out, coff_swap_reloc_out,
3083 coff_swap_filehdr_out, coff_swap_aouthdr_out,
3084 coff_swap_scnhdr_out,
692b7d62 3085 FILHSZ, AOUTSZ, SCNHSZ, SYMESZ, AUXESZ, RELSZ, LINESZ, FILNMLEN,
252b5132 3086#ifdef COFF_LONG_FILENAMES
b34976b6 3087 TRUE,
252b5132 3088#else
b34976b6 3089 FALSE,
252b5132 3090#endif
88183869 3091 COFF_DEFAULT_LONG_SECTION_NAMES,
252b5132 3092 2,
ecefdb58 3093#ifdef COFF_FORCE_SYMBOLS_IN_STRINGS
b34976b6 3094 TRUE,
ecefdb58 3095#else
b34976b6 3096 FALSE,
ecefdb58
CP		 3097#endif
3098#ifdef COFF_DEBUG_STRING_WIDE_PREFIX
3099 4,
3100#else
3101 2,
3102#endif
167ad85b 3103 32768,
252b5132
RH		 3104 coff_swap_filehdr_in, coff_swap_aouthdr_in, coff_swap_scnhdr_in,
3105 coff_swap_reloc_in, coff_bad_format_hook, coff_set_arch_mach_hook,
3106 coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook,
3107 coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook,
3108 coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate,
5d54c628 3109 coff_classify_symbol, coff_compute_section_file_positions,
252b5132
RH		 3110 coff_start_final_link, coff_relocate_section, coff_rtype_to_howto,
3111 coff_adjust_symndx, coff_link_add_one_symbol,
2b5c217d
NC		 3112 coff_link_output_has_begun, coff_final_link_postscript,
3113 bfd_pe_print_pdata
252b5132
RH		 3114};
3115
3116#define coff_small_close_and_cleanup \
3117 coff_close_and_cleanup
3118#define coff_small_bfd_free_cached_info \
3119 coff_bfd_free_cached_info
3120#define coff_small_get_section_contents \
3121 coff_get_section_contents
3122#define coff_small_get_section_contents_in_window \
3123 coff_get_section_contents_in_window
3124
6d00b590 3125extern const bfd_target sh_coff_small_le_vec;
c3c89269 3126
6d00b590 3127const bfd_target sh_coff_small_vec =
252b5132
RH		 3128{
3129 "coff-sh-small", /* name */
3130 bfd_target_coff_flavour,
3131 BFD_ENDIAN_BIG, /* data byte order is big */
3132 BFD_ENDIAN_BIG, /* header byte order is big */
3133
d00dd7dc
AM		 3134 (HAS_RELOC | EXEC_P /* object flags */
3135 | HAS_LINENO | HAS_DEBUG
3136 | HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
252b5132
RH		 3137
3138 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3139 '_', /* leading symbol underscore */
3140 '/', /* ar_pad_char */
3141 15, /* ar_max_namelen */
0aabe54e 3142 0, /* match priority. */
252b5132
RH		 3143 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3144 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3145 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
3146 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3147 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3148 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
3149
d00dd7dc
AM		 3150 { /* bfd_check_format */
3151 _bfd_dummy_target,
3152 coff_small_object_p,
3153 bfd_generic_archive_p,
3154 _bfd_dummy_target
3155 },
3156 { /* bfd_set_format */
3157 _bfd_bool_bfd_false_error,
3158 coff_mkobject,
3159 _bfd_generic_mkarchive,
3160 _bfd_bool_bfd_false_error
3161 },
3162 { /* bfd_write_contents */
3163 _bfd_bool_bfd_false_error,
3164 coff_write_object_contents,
3165 _bfd_write_archive_contents,
3166 _bfd_bool_bfd_false_error
3167 },
252b5132
RH		 3168
3169 BFD_JUMP_TABLE_GENERIC (coff_small),
3170 BFD_JUMP_TABLE_COPY (coff),
3171 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3172 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3173 BFD_JUMP_TABLE_SYMBOLS (coff),
3174 BFD_JUMP_TABLE_RELOCS (coff),
3175 BFD_JUMP_TABLE_WRITE (coff),
3176 BFD_JUMP_TABLE_LINK (coff),
3177 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3178
d00dd7dc 3179 &sh_coff_small_le_vec,
cbfe05c4 3180
d00dd7dc 3181 &bfd_coff_small_swap_table
252b5132
RH		 3182};
3183
6d00b590 3184const bfd_target sh_coff_small_le_vec =
252b5132
RH		 3185{
3186 "coff-shl-small", /* name */
3187 bfd_target_coff_flavour,
3188 BFD_ENDIAN_LITTLE, /* data byte order is little */
3189 BFD_ENDIAN_LITTLE, /* header byte order is little endian too*/
3190
d00dd7dc
AM		 3191 (HAS_RELOC | EXEC_P /* object flags */
3192 | HAS_LINENO | HAS_DEBUG
3193 | HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
252b5132
RH		 3194
3195 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3196 '_', /* leading symbol underscore */
3197 '/', /* ar_pad_char */
3198 15, /* ar_max_namelen */
0aabe54e 3199 0, /* match priority. */
252b5132
RH		 3200 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3201 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3202 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
3203 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3204 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3205 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
3206
d00dd7dc
AM		 3207 { /* bfd_check_format */
3208 _bfd_dummy_target,
3209 coff_small_object_p,
3210 bfd_generic_archive_p,
3211 _bfd_dummy_target
3212 },
3213 { /* bfd_set_format */
3214 _bfd_bool_bfd_false_error,
3215 coff_mkobject,
3216 _bfd_generic_mkarchive,
3217 _bfd_bool_bfd_false_error
3218 },
3219 { /* bfd_write_contents */
3220 _bfd_bool_bfd_false_error,
3221 coff_write_object_contents,
3222 _bfd_write_archive_contents,
3223 _bfd_bool_bfd_false_error
3224 },
252b5132
RH		 3225
3226 BFD_JUMP_TABLE_GENERIC (coff_small),
3227 BFD_JUMP_TABLE_COPY (coff),
3228 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3229 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3230 BFD_JUMP_TABLE_SYMBOLS (coff),
3231 BFD_JUMP_TABLE_RELOCS (coff),
3232 BFD_JUMP_TABLE_WRITE (coff),
3233 BFD_JUMP_TABLE_LINK (coff),
3234 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3235
d00dd7dc 3236 &sh_coff_small_vec,
cbfe05c4 3237
d00dd7dc 3238 &bfd_coff_small_swap_table
252b5132 3239};
17505c5c 3240#endif
GDB Binutils - Deliverables
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