Commit | Line | Data |
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252b5132 | 1 | /* BFD back-end for Hitachi Super-H COFF binaries. |
7898deda NC |
2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000 |
3 | Free Software Foundation, Inc. | |
252b5132 RH |
4 | Contributed by Cygnus Support. |
5 | Written by Steve Chamberlain, <sac@cygnus.com>. | |
6 | Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>. | |
7 | ||
8 | This file is part of BFD, the Binary File Descriptor library. | |
9 | ||
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2 of the License, or | |
13 | (at your option) any later version. | |
14 | ||
15 | This program is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with this program; if not, write to the Free Software | |
22 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
23 | ||
24 | #include "bfd.h" | |
25 | #include "sysdep.h" | |
26 | #include "libbfd.h" | |
27 | #include "bfdlink.h" | |
28 | #include "coff/sh.h" | |
29 | #include "coff/internal.h" | |
17505c5c NC |
30 | |
31 | #ifdef COFF_WITH_PE | |
32 | #include "coff/pe.h" | |
86033394 NC |
33 | |
34 | #ifndef COFF_IMAGE_WITH_PE | |
cbfe05c4 | 35 | static boolean sh_align_load_span |
86033394 NC |
36 | PARAMS ((bfd *, asection *, bfd_byte *, |
37 | boolean (*) (bfd *, asection *, PTR, bfd_byte *, bfd_vma), | |
38 | PTR, bfd_vma **, bfd_vma *, bfd_vma, bfd_vma, boolean *)); | |
39 | ||
40 | #define _bfd_sh_align_load_span sh_align_load_span | |
41 | #endif | |
17505c5c NC |
42 | #endif |
43 | ||
252b5132 RH |
44 | #include "libcoff.h" |
45 | ||
46 | /* Internal functions. */ | |
47 | static bfd_reloc_status_type sh_reloc | |
48 | PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); | |
49 | static long get_symbol_value PARAMS ((asymbol *)); | |
252b5132 RH |
50 | static boolean sh_relax_section |
51 | PARAMS ((bfd *, asection *, struct bfd_link_info *, boolean *)); | |
52 | static boolean sh_relax_delete_bytes | |
53 | PARAMS ((bfd *, asection *, bfd_vma, int)); | |
86033394 | 54 | #ifndef COFF_IMAGE_WITH_PE |
252b5132 | 55 | static const struct sh_opcode *sh_insn_info PARAMS ((unsigned int)); |
86033394 | 56 | #endif |
252b5132 RH |
57 | static boolean sh_align_loads |
58 | PARAMS ((bfd *, asection *, struct internal_reloc *, bfd_byte *, boolean *)); | |
59 | static boolean sh_swap_insns | |
60 | PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma)); | |
61 | static boolean sh_relocate_section | |
62 | PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, | |
63 | struct internal_reloc *, struct internal_syment *, asection **)); | |
64 | static bfd_byte *sh_coff_get_relocated_section_contents | |
65 | PARAMS ((bfd *, struct bfd_link_info *, struct bfd_link_order *, | |
66 | bfd_byte *, boolean, asymbol **)); | |
67 | ||
17505c5c NC |
68 | #ifdef COFF_WITH_PE |
69 | /* Can't build import tables with 2**4 alignment. */ | |
70 | #define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 2 | |
71 | #else | |
252b5132 | 72 | /* Default section alignment to 2**4. */ |
17505c5c NC |
73 | #define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 4 |
74 | #endif | |
75 | ||
76 | #ifdef COFF_IMAGE_WITH_PE | |
77 | /* Align PE executables. */ | |
78 | #define COFF_PAGE_SIZE 0x1000 | |
79 | #endif | |
252b5132 RH |
80 | |
81 | /* Generate long file names. */ | |
82 | #define COFF_LONG_FILENAMES | |
83 | ||
17505c5c NC |
84 | #ifdef COFF_WITH_PE |
85 | /* Return true if this relocation should | |
86 | appear in the output .reloc section. */ | |
87 | static boolean in_reloc_p (abfd, howto) | |
88 | bfd * abfd ATTRIBUTE_UNUSED; | |
89 | reloc_howto_type * howto; | |
90 | { | |
91 | return ! howto->pc_relative && howto->type != R_SH_IMAGEBASE; | |
cbfe05c4 | 92 | } |
17505c5c NC |
93 | #endif |
94 | ||
252b5132 RH |
95 | /* The supported relocations. There are a lot of relocations defined |
96 | in coff/internal.h which we do not expect to ever see. */ | |
97 | static reloc_howto_type sh_coff_howtos[] = | |
98 | { | |
5f771d47 ILT |
99 | EMPTY_HOWTO (0), |
100 | EMPTY_HOWTO (1), | |
17505c5c NC |
101 | #ifdef COFF_WITH_PE |
102 | /* Windows CE */ | |
103 | HOWTO (R_SH_IMM32CE, /* type */ | |
104 | 0, /* rightshift */ | |
105 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
106 | 32, /* bitsize */ | |
107 | false, /* pc_relative */ | |
108 | 0, /* bitpos */ | |
109 | complain_overflow_bitfield, /* complain_on_overflow */ | |
110 | sh_reloc, /* special_function */ | |
111 | "r_imm32ce", /* name */ | |
112 | true, /* partial_inplace */ | |
113 | 0xffffffff, /* src_mask */ | |
114 | 0xffffffff, /* dst_mask */ | |
115 | false), /* pcrel_offset */ | |
116 | #else | |
5f771d47 | 117 | EMPTY_HOWTO (2), |
17505c5c | 118 | #endif |
5f771d47 ILT |
119 | EMPTY_HOWTO (3), /* R_SH_PCREL8 */ |
120 | EMPTY_HOWTO (4), /* R_SH_PCREL16 */ | |
121 | EMPTY_HOWTO (5), /* R_SH_HIGH8 */ | |
122 | EMPTY_HOWTO (6), /* R_SH_IMM24 */ | |
123 | EMPTY_HOWTO (7), /* R_SH_LOW16 */ | |
124 | EMPTY_HOWTO (8), | |
125 | EMPTY_HOWTO (9), /* R_SH_PCDISP8BY4 */ | |
252b5132 RH |
126 | |
127 | HOWTO (R_SH_PCDISP8BY2, /* type */ | |
128 | 1, /* rightshift */ | |
129 | 1, /* size (0 = byte, 1 = short, 2 = long) */ | |
130 | 8, /* bitsize */ | |
131 | true, /* pc_relative */ | |
132 | 0, /* bitpos */ | |
133 | complain_overflow_signed, /* complain_on_overflow */ | |
134 | sh_reloc, /* special_function */ | |
135 | "r_pcdisp8by2", /* name */ | |
136 | true, /* partial_inplace */ | |
137 | 0xff, /* src_mask */ | |
138 | 0xff, /* dst_mask */ | |
139 | true), /* pcrel_offset */ | |
140 | ||
5f771d47 | 141 | EMPTY_HOWTO (11), /* R_SH_PCDISP8 */ |
252b5132 RH |
142 | |
143 | HOWTO (R_SH_PCDISP, /* type */ | |
144 | 1, /* rightshift */ | |
145 | 1, /* size (0 = byte, 1 = short, 2 = long) */ | |
146 | 12, /* bitsize */ | |
147 | true, /* pc_relative */ | |
148 | 0, /* bitpos */ | |
149 | complain_overflow_signed, /* complain_on_overflow */ | |
150 | sh_reloc, /* special_function */ | |
151 | "r_pcdisp12by2", /* name */ | |
152 | true, /* partial_inplace */ | |
153 | 0xfff, /* src_mask */ | |
154 | 0xfff, /* dst_mask */ | |
155 | true), /* pcrel_offset */ | |
156 | ||
5f771d47 | 157 | EMPTY_HOWTO (13), |
252b5132 RH |
158 | |
159 | HOWTO (R_SH_IMM32, /* type */ | |
160 | 0, /* rightshift */ | |
161 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
162 | 32, /* bitsize */ | |
163 | false, /* pc_relative */ | |
164 | 0, /* bitpos */ | |
165 | complain_overflow_bitfield, /* complain_on_overflow */ | |
166 | sh_reloc, /* special_function */ | |
167 | "r_imm32", /* name */ | |
168 | true, /* partial_inplace */ | |
169 | 0xffffffff, /* src_mask */ | |
170 | 0xffffffff, /* dst_mask */ | |
171 | false), /* pcrel_offset */ | |
172 | ||
5f771d47 | 173 | EMPTY_HOWTO (15), |
17505c5c | 174 | #ifdef COFF_WITH_PE |
cbfe05c4 KH |
175 | HOWTO (R_SH_IMAGEBASE, /* type */ |
176 | 0, /* rightshift */ | |
177 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
178 | 32, /* bitsize */ | |
179 | false, /* pc_relative */ | |
180 | 0, /* bitpos */ | |
17505c5c | 181 | complain_overflow_bitfield, /* complain_on_overflow */ |
cbfe05c4 KH |
182 | sh_reloc, /* special_function */ |
183 | "rva32", /* name */ | |
184 | true, /* partial_inplace */ | |
185 | 0xffffffff, /* src_mask */ | |
186 | 0xffffffff, /* dst_mask */ | |
17505c5c NC |
187 | false), /* pcrel_offset */ |
188 | #else | |
5f771d47 | 189 | EMPTY_HOWTO (16), /* R_SH_IMM8 */ |
17505c5c | 190 | #endif |
5f771d47 ILT |
191 | EMPTY_HOWTO (17), /* R_SH_IMM8BY2 */ |
192 | EMPTY_HOWTO (18), /* R_SH_IMM8BY4 */ | |
193 | EMPTY_HOWTO (19), /* R_SH_IMM4 */ | |
194 | EMPTY_HOWTO (20), /* R_SH_IMM4BY2 */ | |
195 | EMPTY_HOWTO (21), /* R_SH_IMM4BY4 */ | |
252b5132 RH |
196 | |
197 | HOWTO (R_SH_PCRELIMM8BY2, /* type */ | |
198 | 1, /* rightshift */ | |
199 | 1, /* size (0 = byte, 1 = short, 2 = long) */ | |
200 | 8, /* bitsize */ | |
201 | true, /* pc_relative */ | |
202 | 0, /* bitpos */ | |
203 | complain_overflow_unsigned, /* complain_on_overflow */ | |
204 | sh_reloc, /* special_function */ | |
205 | "r_pcrelimm8by2", /* name */ | |
206 | true, /* partial_inplace */ | |
207 | 0xff, /* src_mask */ | |
208 | 0xff, /* dst_mask */ | |
209 | true), /* pcrel_offset */ | |
210 | ||
211 | HOWTO (R_SH_PCRELIMM8BY4, /* type */ | |
212 | 2, /* rightshift */ | |
213 | 1, /* size (0 = byte, 1 = short, 2 = long) */ | |
214 | 8, /* bitsize */ | |
215 | true, /* pc_relative */ | |
216 | 0, /* bitpos */ | |
217 | complain_overflow_unsigned, /* complain_on_overflow */ | |
218 | sh_reloc, /* special_function */ | |
219 | "r_pcrelimm8by4", /* name */ | |
220 | true, /* partial_inplace */ | |
221 | 0xff, /* src_mask */ | |
222 | 0xff, /* dst_mask */ | |
223 | true), /* pcrel_offset */ | |
224 | ||
225 | HOWTO (R_SH_IMM16, /* type */ | |
226 | 0, /* rightshift */ | |
227 | 1, /* size (0 = byte, 1 = short, 2 = long) */ | |
228 | 16, /* bitsize */ | |
229 | false, /* pc_relative */ | |
230 | 0, /* bitpos */ | |
231 | complain_overflow_bitfield, /* complain_on_overflow */ | |
232 | sh_reloc, /* special_function */ | |
233 | "r_imm16", /* name */ | |
234 | true, /* partial_inplace */ | |
235 | 0xffff, /* src_mask */ | |
236 | 0xffff, /* dst_mask */ | |
237 | false), /* pcrel_offset */ | |
238 | ||
239 | HOWTO (R_SH_SWITCH16, /* type */ | |
240 | 0, /* rightshift */ | |
241 | 1, /* size (0 = byte, 1 = short, 2 = long) */ | |
242 | 16, /* bitsize */ | |
243 | false, /* pc_relative */ | |
244 | 0, /* bitpos */ | |
245 | complain_overflow_bitfield, /* complain_on_overflow */ | |
246 | sh_reloc, /* special_function */ | |
247 | "r_switch16", /* name */ | |
248 | true, /* partial_inplace */ | |
249 | 0xffff, /* src_mask */ | |
250 | 0xffff, /* dst_mask */ | |
251 | false), /* pcrel_offset */ | |
252 | ||
253 | HOWTO (R_SH_SWITCH32, /* type */ | |
254 | 0, /* rightshift */ | |
255 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
256 | 32, /* bitsize */ | |
257 | false, /* pc_relative */ | |
258 | 0, /* bitpos */ | |
259 | complain_overflow_bitfield, /* complain_on_overflow */ | |
260 | sh_reloc, /* special_function */ | |
261 | "r_switch32", /* name */ | |
262 | true, /* partial_inplace */ | |
263 | 0xffffffff, /* src_mask */ | |
264 | 0xffffffff, /* dst_mask */ | |
265 | false), /* pcrel_offset */ | |
266 | ||
267 | HOWTO (R_SH_USES, /* type */ | |
268 | 0, /* rightshift */ | |
269 | 1, /* size (0 = byte, 1 = short, 2 = long) */ | |
270 | 16, /* bitsize */ | |
271 | false, /* pc_relative */ | |
272 | 0, /* bitpos */ | |
273 | complain_overflow_bitfield, /* complain_on_overflow */ | |
274 | sh_reloc, /* special_function */ | |
275 | "r_uses", /* name */ | |
276 | true, /* partial_inplace */ | |
277 | 0xffff, /* src_mask */ | |
278 | 0xffff, /* dst_mask */ | |
279 | false), /* pcrel_offset */ | |
280 | ||
281 | HOWTO (R_SH_COUNT, /* type */ | |
282 | 0, /* rightshift */ | |
283 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
284 | 32, /* bitsize */ | |
285 | false, /* pc_relative */ | |
286 | 0, /* bitpos */ | |
287 | complain_overflow_bitfield, /* complain_on_overflow */ | |
288 | sh_reloc, /* special_function */ | |
289 | "r_count", /* name */ | |
290 | true, /* partial_inplace */ | |
291 | 0xffffffff, /* src_mask */ | |
292 | 0xffffffff, /* dst_mask */ | |
293 | false), /* pcrel_offset */ | |
294 | ||
295 | HOWTO (R_SH_ALIGN, /* type */ | |
296 | 0, /* rightshift */ | |
297 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
298 | 32, /* bitsize */ | |
299 | false, /* pc_relative */ | |
300 | 0, /* bitpos */ | |
301 | complain_overflow_bitfield, /* complain_on_overflow */ | |
302 | sh_reloc, /* special_function */ | |
303 | "r_align", /* name */ | |
304 | true, /* partial_inplace */ | |
305 | 0xffffffff, /* src_mask */ | |
306 | 0xffffffff, /* dst_mask */ | |
307 | false), /* pcrel_offset */ | |
308 | ||
309 | HOWTO (R_SH_CODE, /* type */ | |
310 | 0, /* rightshift */ | |
311 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
312 | 32, /* bitsize */ | |
313 | false, /* pc_relative */ | |
314 | 0, /* bitpos */ | |
315 | complain_overflow_bitfield, /* complain_on_overflow */ | |
316 | sh_reloc, /* special_function */ | |
317 | "r_code", /* name */ | |
318 | true, /* partial_inplace */ | |
319 | 0xffffffff, /* src_mask */ | |
320 | 0xffffffff, /* dst_mask */ | |
321 | false), /* pcrel_offset */ | |
322 | ||
323 | HOWTO (R_SH_DATA, /* type */ | |
324 | 0, /* rightshift */ | |
325 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
326 | 32, /* bitsize */ | |
327 | false, /* pc_relative */ | |
328 | 0, /* bitpos */ | |
329 | complain_overflow_bitfield, /* complain_on_overflow */ | |
330 | sh_reloc, /* special_function */ | |
331 | "r_data", /* name */ | |
332 | true, /* partial_inplace */ | |
333 | 0xffffffff, /* src_mask */ | |
334 | 0xffffffff, /* dst_mask */ | |
335 | false), /* pcrel_offset */ | |
336 | ||
337 | HOWTO (R_SH_LABEL, /* type */ | |
338 | 0, /* rightshift */ | |
339 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
340 | 32, /* bitsize */ | |
341 | false, /* pc_relative */ | |
342 | 0, /* bitpos */ | |
343 | complain_overflow_bitfield, /* complain_on_overflow */ | |
344 | sh_reloc, /* special_function */ | |
345 | "r_label", /* name */ | |
346 | true, /* partial_inplace */ | |
347 | 0xffffffff, /* src_mask */ | |
348 | 0xffffffff, /* dst_mask */ | |
349 | false), /* pcrel_offset */ | |
350 | ||
351 | HOWTO (R_SH_SWITCH8, /* type */ | |
352 | 0, /* rightshift */ | |
353 | 0, /* size (0 = byte, 1 = short, 2 = long) */ | |
354 | 8, /* bitsize */ | |
355 | false, /* pc_relative */ | |
356 | 0, /* bitpos */ | |
357 | complain_overflow_bitfield, /* complain_on_overflow */ | |
358 | sh_reloc, /* special_function */ | |
359 | "r_switch8", /* name */ | |
360 | true, /* partial_inplace */ | |
361 | 0xff, /* src_mask */ | |
362 | 0xff, /* dst_mask */ | |
363 | false) /* pcrel_offset */ | |
364 | }; | |
365 | ||
366 | #define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0]) | |
367 | ||
368 | /* Check for a bad magic number. */ | |
369 | #define BADMAG(x) SHBADMAG(x) | |
370 | ||
371 | /* Customize coffcode.h (this is not currently used). */ | |
372 | #define SH 1 | |
373 | ||
374 | /* FIXME: This should not be set here. */ | |
375 | #define __A_MAGIC_SET__ | |
376 | ||
17505c5c | 377 | #ifndef COFF_WITH_PE |
252b5132 RH |
378 | /* Swap the r_offset field in and out. */ |
379 | #define SWAP_IN_RELOC_OFFSET bfd_h_get_32 | |
380 | #define SWAP_OUT_RELOC_OFFSET bfd_h_put_32 | |
381 | ||
382 | /* Swap out extra information in the reloc structure. */ | |
383 | #define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \ | |
384 | do \ | |
385 | { \ | |
386 | dst->r_stuff[0] = 'S'; \ | |
387 | dst->r_stuff[1] = 'C'; \ | |
388 | } \ | |
389 | while (0) | |
17505c5c | 390 | #endif |
252b5132 RH |
391 | |
392 | /* Get the value of a symbol, when performing a relocation. */ | |
393 | ||
394 | static long | |
cbfe05c4 | 395 | get_symbol_value (symbol) |
252b5132 | 396 | asymbol *symbol; |
cbfe05c4 | 397 | { |
252b5132 RH |
398 | bfd_vma relocation; |
399 | ||
400 | if (bfd_is_com_section (symbol->section)) | |
cbfe05c4 KH |
401 | relocation = 0; |
402 | else | |
252b5132 RH |
403 | relocation = (symbol->value + |
404 | symbol->section->output_section->vma + | |
405 | symbol->section->output_offset); | |
406 | ||
407 | return relocation; | |
408 | } | |
409 | ||
17505c5c NC |
410 | #ifdef COFF_WITH_PE |
411 | /* Convert an rtype to howto for the COFF backend linker. | |
412 | Copied from coff-i386. */ | |
413 | #define coff_rtype_to_howto coff_sh_rtype_to_howto | |
414 | ||
415 | static reloc_howto_type * | |
416 | coff_sh_rtype_to_howto (abfd, sec, rel, h, sym, addendp) | |
86033394 | 417 | bfd * abfd ATTRIBUTE_UNUSED; |
17505c5c NC |
418 | asection * sec; |
419 | struct internal_reloc * rel; | |
420 | struct coff_link_hash_entry * h; | |
421 | struct internal_syment * sym; | |
422 | bfd_vma * addendp; | |
423 | { | |
424 | reloc_howto_type * howto; | |
425 | ||
426 | howto = sh_coff_howtos + rel->r_type; | |
427 | ||
428 | *addendp = 0; | |
429 | ||
430 | if (howto->pc_relative) | |
431 | *addendp += sec->vma; | |
432 | ||
433 | if (sym != NULL && sym->n_scnum == 0 && sym->n_value != 0) | |
434 | { | |
435 | /* This is a common symbol. The section contents include the | |
436 | size (sym->n_value) as an addend. The relocate_section | |
437 | function will be adding in the final value of the symbol. We | |
438 | need to subtract out the current size in order to get the | |
439 | correct result. */ | |
440 | BFD_ASSERT (h != NULL); | |
441 | } | |
442 | ||
443 | if (howto->pc_relative) | |
444 | { | |
445 | *addendp -= 4; | |
446 | ||
447 | /* If the symbol is defined, then the generic code is going to | |
448 | add back the symbol value in order to cancel out an | |
449 | adjustment it made to the addend. However, we set the addend | |
450 | to 0 at the start of this function. We need to adjust here, | |
451 | to avoid the adjustment the generic code will make. FIXME: | |
452 | This is getting a bit hackish. */ | |
453 | if (sym != NULL && sym->n_scnum != 0) | |
454 | *addendp -= sym->n_value; | |
455 | } | |
456 | ||
457 | if (rel->r_type == R_SH_IMAGEBASE) | |
458 | *addendp -= pe_data (sec->output_section->owner)->pe_opthdr.ImageBase; | |
459 | ||
460 | return howto; | |
461 | } | |
462 | ||
463 | /* This structure is used to map BFD reloc codes to SH PE relocs. */ | |
464 | struct shcoff_reloc_map | |
465 | { | |
466 | unsigned char bfd_reloc_val; | |
467 | unsigned char shcoff_reloc_val; | |
468 | }; | |
469 | ||
470 | /* An array mapping BFD reloc codes to SH PE relocs. */ | |
471 | static const struct shcoff_reloc_map sh_reloc_map[] = | |
472 | { | |
473 | { BFD_RELOC_32, R_SH_IMM32CE }, | |
474 | { BFD_RELOC_RVA, R_SH_IMAGEBASE }, | |
475 | { BFD_RELOC_CTOR, R_SH_IMM32CE }, | |
476 | }; | |
477 | ||
478 | /* Given a BFD reloc code, return the howto structure for the | |
479 | corresponding SH PE reloc. */ | |
480 | #define coff_bfd_reloc_type_lookup sh_coff_reloc_type_lookup | |
481 | ||
482 | static reloc_howto_type * | |
483 | sh_coff_reloc_type_lookup (abfd, code) | |
484 | bfd * abfd ATTRIBUTE_UNUSED; | |
485 | bfd_reloc_code_real_type code; | |
486 | { | |
487 | unsigned int i; | |
488 | ||
489 | for (i = 0; i < sizeof (sh_reloc_map) / sizeof (struct shcoff_reloc_map); i++) | |
490 | { | |
491 | if (sh_reloc_map[i].bfd_reloc_val == code) | |
492 | return &sh_coff_howtos[(int) sh_reloc_map[i].shcoff_reloc_val]; | |
493 | } | |
494 | ||
495 | fprintf (stderr, "SH Error: unknown reloc type %d\n", code); | |
496 | return NULL; | |
497 | } | |
498 | #endif /* COFF_WITH_PE */ | |
499 | ||
252b5132 RH |
500 | /* This macro is used in coffcode.h to get the howto corresponding to |
501 | an internal reloc. */ | |
502 | ||
503 | #define RTYPE2HOWTO(relent, internal) \ | |
504 | ((relent)->howto = \ | |
505 | ((internal)->r_type < SH_COFF_HOWTO_COUNT \ | |
506 | ? &sh_coff_howtos[(internal)->r_type] \ | |
507 | : (reloc_howto_type *) NULL)) | |
508 | ||
509 | /* This is the same as the macro in coffcode.h, except that it copies | |
510 | r_offset into reloc_entry->addend for some relocs. */ | |
511 | #define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \ | |
512 | { \ | |
513 | coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \ | |
514 | if (ptr && bfd_asymbol_bfd (ptr) != abfd) \ | |
515 | coffsym = (obj_symbols (abfd) \ | |
516 | + (cache_ptr->sym_ptr_ptr - symbols)); \ | |
517 | else if (ptr) \ | |
518 | coffsym = coff_symbol_from (abfd, ptr); \ | |
519 | if (coffsym != (coff_symbol_type *) NULL \ | |
520 | && coffsym->native->u.syment.n_scnum == 0) \ | |
521 | cache_ptr->addend = 0; \ | |
522 | else if (ptr && bfd_asymbol_bfd (ptr) == abfd \ | |
523 | && ptr->section != (asection *) NULL) \ | |
524 | cache_ptr->addend = - (ptr->section->vma + ptr->value); \ | |
525 | else \ | |
526 | cache_ptr->addend = 0; \ | |
527 | if ((reloc).r_type == R_SH_SWITCH8 \ | |
528 | || (reloc).r_type == R_SH_SWITCH16 \ | |
529 | || (reloc).r_type == R_SH_SWITCH32 \ | |
530 | || (reloc).r_type == R_SH_USES \ | |
531 | || (reloc).r_type == R_SH_COUNT \ | |
532 | || (reloc).r_type == R_SH_ALIGN) \ | |
533 | cache_ptr->addend = (reloc).r_offset; \ | |
534 | } | |
535 | ||
536 | /* This is the howto function for the SH relocations. */ | |
537 | ||
538 | static bfd_reloc_status_type | |
539 | sh_reloc (abfd, reloc_entry, symbol_in, data, input_section, output_bfd, | |
540 | error_message) | |
541 | bfd *abfd; | |
542 | arelent *reloc_entry; | |
543 | asymbol *symbol_in; | |
544 | PTR data; | |
545 | asection *input_section; | |
546 | bfd *output_bfd; | |
5f771d47 | 547 | char **error_message ATTRIBUTE_UNUSED; |
252b5132 RH |
548 | { |
549 | unsigned long insn; | |
550 | bfd_vma sym_value; | |
551 | unsigned short r_type; | |
552 | bfd_vma addr = reloc_entry->address; | |
553 | bfd_byte *hit_data = addr + (bfd_byte *) data; | |
554 | ||
555 | r_type = reloc_entry->howto->type; | |
556 | ||
557 | if (output_bfd != NULL) | |
558 | { | |
559 | /* Partial linking--do nothing. */ | |
560 | reloc_entry->address += input_section->output_offset; | |
561 | return bfd_reloc_ok; | |
562 | } | |
563 | ||
564 | /* Almost all relocs have to do with relaxing. If any work must be | |
565 | done for them, it has been done in sh_relax_section. */ | |
566 | if (r_type != R_SH_IMM32 | |
17505c5c NC |
567 | #ifdef COFF_WITH_PE |
568 | && r_type != R_SH_IMM32CE | |
569 | && r_type != R_SH_IMAGEBASE | |
570 | #endif | |
252b5132 RH |
571 | && (r_type != R_SH_PCDISP |
572 | || (symbol_in->flags & BSF_LOCAL) != 0)) | |
573 | return bfd_reloc_ok; | |
574 | ||
575 | if (symbol_in != NULL | |
576 | && bfd_is_und_section (symbol_in->section)) | |
577 | return bfd_reloc_undefined; | |
578 | ||
579 | sym_value = get_symbol_value (symbol_in); | |
580 | ||
581 | switch (r_type) | |
582 | { | |
583 | case R_SH_IMM32: | |
17505c5c NC |
584 | #ifdef COFF_WITH_PE |
585 | case R_SH_IMM32CE: | |
586 | #endif | |
252b5132 RH |
587 | insn = bfd_get_32 (abfd, hit_data); |
588 | insn += sym_value + reloc_entry->addend; | |
589 | bfd_put_32 (abfd, insn, hit_data); | |
590 | break; | |
17505c5c NC |
591 | #ifdef COFF_WITH_PE |
592 | case R_SH_IMAGEBASE: | |
593 | insn = bfd_get_32 (abfd, hit_data); | |
594 | insn += (sym_value + reloc_entry->addend | |
595 | - pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase); | |
596 | bfd_put_32 (abfd, insn, hit_data); | |
597 | break; | |
598 | #endif | |
252b5132 RH |
599 | case R_SH_PCDISP: |
600 | insn = bfd_get_16 (abfd, hit_data); | |
601 | sym_value += reloc_entry->addend; | |
602 | sym_value -= (input_section->output_section->vma | |
603 | + input_section->output_offset | |
604 | + addr | |
605 | + 4); | |
606 | sym_value += (insn & 0xfff) << 1; | |
607 | if (insn & 0x800) | |
608 | sym_value -= 0x1000; | |
609 | insn = (insn & 0xf000) | (sym_value & 0xfff); | |
610 | bfd_put_16 (abfd, insn, hit_data); | |
611 | if (sym_value < (bfd_vma) -0x1000 || sym_value >= 0x1000) | |
612 | return bfd_reloc_overflow; | |
613 | break; | |
614 | default: | |
615 | abort (); | |
616 | break; | |
617 | } | |
618 | ||
619 | return bfd_reloc_ok; | |
620 | } | |
621 | ||
875f7f69 | 622 | #define coff_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match |
252b5132 RH |
623 | |
624 | /* We can do relaxing. */ | |
625 | #define coff_bfd_relax_section sh_relax_section | |
626 | ||
627 | /* We use the special COFF backend linker. */ | |
628 | #define coff_relocate_section sh_relocate_section | |
629 | ||
630 | /* When relaxing, we need to use special code to get the relocated | |
631 | section contents. */ | |
632 | #define coff_bfd_get_relocated_section_contents \ | |
633 | sh_coff_get_relocated_section_contents | |
634 | ||
635 | #include "coffcode.h" | |
636 | \f | |
637 | /* This function handles relaxing on the SH. | |
638 | ||
639 | Function calls on the SH look like this: | |
640 | ||
641 | movl L1,r0 | |
642 | ... | |
643 | jsr @r0 | |
644 | ... | |
645 | L1: | |
646 | .long function | |
647 | ||
648 | The compiler and assembler will cooperate to create R_SH_USES | |
649 | relocs on the jsr instructions. The r_offset field of the | |
650 | R_SH_USES reloc is the PC relative offset to the instruction which | |
651 | loads the register (the r_offset field is computed as though it | |
652 | were a jump instruction, so the offset value is actually from four | |
653 | bytes past the instruction). The linker can use this reloc to | |
654 | determine just which function is being called, and thus decide | |
655 | whether it is possible to replace the jsr with a bsr. | |
656 | ||
657 | If multiple function calls are all based on a single register load | |
658 | (i.e., the same function is called multiple times), the compiler | |
659 | guarantees that each function call will have an R_SH_USES reloc. | |
660 | Therefore, if the linker is able to convert each R_SH_USES reloc | |
661 | which refers to that address, it can safely eliminate the register | |
662 | load. | |
663 | ||
664 | When the assembler creates an R_SH_USES reloc, it examines it to | |
665 | determine which address is being loaded (L1 in the above example). | |
666 | It then counts the number of references to that address, and | |
667 | creates an R_SH_COUNT reloc at that address. The r_offset field of | |
668 | the R_SH_COUNT reloc will be the number of references. If the | |
669 | linker is able to eliminate a register load, it can use the | |
670 | R_SH_COUNT reloc to see whether it can also eliminate the function | |
671 | address. | |
672 | ||
673 | SH relaxing also handles another, unrelated, matter. On the SH, if | |
674 | a load or store instruction is not aligned on a four byte boundary, | |
675 | the memory cycle interferes with the 32 bit instruction fetch, | |
676 | causing a one cycle bubble in the pipeline. Therefore, we try to | |
677 | align load and store instructions on four byte boundaries if we | |
678 | can, by swapping them with one of the adjacent instructions. */ | |
679 | ||
cbfe05c4 | 680 | static boolean |
252b5132 RH |
681 | sh_relax_section (abfd, sec, link_info, again) |
682 | bfd *abfd; | |
683 | asection *sec; | |
684 | struct bfd_link_info *link_info; | |
685 | boolean *again; | |
686 | { | |
687 | struct internal_reloc *internal_relocs; | |
688 | struct internal_reloc *free_relocs = NULL; | |
689 | boolean have_code; | |
690 | struct internal_reloc *irel, *irelend; | |
691 | bfd_byte *contents = NULL; | |
692 | bfd_byte *free_contents = NULL; | |
693 | ||
694 | *again = false; | |
695 | ||
696 | if (link_info->relocateable | |
697 | || (sec->flags & SEC_RELOC) == 0 | |
698 | || sec->reloc_count == 0) | |
699 | return true; | |
700 | ||
701 | /* If this is the first time we have been called for this section, | |
702 | initialize the cooked size. */ | |
703 | if (sec->_cooked_size == 0) | |
704 | sec->_cooked_size = sec->_raw_size; | |
705 | ||
706 | internal_relocs = (_bfd_coff_read_internal_relocs | |
707 | (abfd, sec, link_info->keep_memory, | |
708 | (bfd_byte *) NULL, false, | |
709 | (struct internal_reloc *) NULL)); | |
710 | if (internal_relocs == NULL) | |
711 | goto error_return; | |
712 | if (! link_info->keep_memory) | |
713 | free_relocs = internal_relocs; | |
714 | ||
715 | have_code = false; | |
716 | ||
717 | irelend = internal_relocs + sec->reloc_count; | |
718 | for (irel = internal_relocs; irel < irelend; irel++) | |
719 | { | |
720 | bfd_vma laddr, paddr, symval; | |
721 | unsigned short insn; | |
722 | struct internal_reloc *irelfn, *irelscan, *irelcount; | |
723 | struct internal_syment sym; | |
724 | bfd_signed_vma foff; | |
725 | ||
726 | if (irel->r_type == R_SH_CODE) | |
727 | have_code = true; | |
728 | ||
729 | if (irel->r_type != R_SH_USES) | |
730 | continue; | |
731 | ||
732 | /* Get the section contents. */ | |
733 | if (contents == NULL) | |
734 | { | |
735 | if (coff_section_data (abfd, sec) != NULL | |
736 | && coff_section_data (abfd, sec)->contents != NULL) | |
737 | contents = coff_section_data (abfd, sec)->contents; | |
738 | else | |
739 | { | |
740 | contents = (bfd_byte *) bfd_malloc (sec->_raw_size); | |
741 | if (contents == NULL) | |
742 | goto error_return; | |
743 | free_contents = contents; | |
744 | ||
745 | if (! bfd_get_section_contents (abfd, sec, contents, | |
746 | (file_ptr) 0, sec->_raw_size)) | |
747 | goto error_return; | |
748 | } | |
749 | } | |
750 | ||
751 | /* The r_offset field of the R_SH_USES reloc will point us to | |
752 | the register load. The 4 is because the r_offset field is | |
753 | computed as though it were a jump offset, which are based | |
754 | from 4 bytes after the jump instruction. */ | |
755 | laddr = irel->r_vaddr - sec->vma + 4; | |
756 | /* Careful to sign extend the 32-bit offset. */ | |
757 | laddr += ((irel->r_offset & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
758 | if (laddr >= sec->_raw_size) | |
759 | { | |
760 | (*_bfd_error_handler) ("%s: 0x%lx: warning: bad R_SH_USES offset", | |
761 | bfd_get_filename (abfd), | |
762 | (unsigned long) irel->r_vaddr); | |
763 | continue; | |
764 | } | |
765 | insn = bfd_get_16 (abfd, contents + laddr); | |
766 | ||
767 | /* If the instruction is not mov.l NN,rN, we don't know what to do. */ | |
768 | if ((insn & 0xf000) != 0xd000) | |
769 | { | |
770 | ((*_bfd_error_handler) | |
771 | ("%s: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x", | |
772 | bfd_get_filename (abfd), (unsigned long) irel->r_vaddr, insn)); | |
773 | continue; | |
774 | } | |
775 | ||
776 | /* Get the address from which the register is being loaded. The | |
777 | displacement in the mov.l instruction is quadrupled. It is a | |
778 | displacement from four bytes after the movl instruction, but, | |
779 | before adding in the PC address, two least significant bits | |
780 | of the PC are cleared. We assume that the section is aligned | |
781 | on a four byte boundary. */ | |
782 | paddr = insn & 0xff; | |
783 | paddr *= 4; | |
784 | paddr += (laddr + 4) &~ 3; | |
785 | if (paddr >= sec->_raw_size) | |
786 | { | |
787 | ((*_bfd_error_handler) | |
788 | ("%s: 0x%lx: warning: bad R_SH_USES load offset", | |
789 | bfd_get_filename (abfd), (unsigned long) irel->r_vaddr)); | |
790 | continue; | |
791 | } | |
792 | ||
793 | /* Get the reloc for the address from which the register is | |
794 | being loaded. This reloc will tell us which function is | |
795 | actually being called. */ | |
796 | paddr += sec->vma; | |
797 | for (irelfn = internal_relocs; irelfn < irelend; irelfn++) | |
798 | if (irelfn->r_vaddr == paddr | |
17505c5c NC |
799 | #ifdef COFF_WITH_PE |
800 | && (irelfn->r_type == R_SH_IMM32 | |
801 | || irelfn->r_type == R_SH_IMM32CE | |
802 | || irelfn->r_type == R_SH_IMAGEBASE)) | |
803 | ||
804 | #else | |
252b5132 | 805 | && irelfn->r_type == R_SH_IMM32) |
17505c5c | 806 | #endif |
252b5132 RH |
807 | break; |
808 | if (irelfn >= irelend) | |
809 | { | |
810 | ((*_bfd_error_handler) | |
811 | ("%s: 0x%lx: warning: could not find expected reloc", | |
812 | bfd_get_filename (abfd), (unsigned long) paddr)); | |
813 | continue; | |
814 | } | |
815 | ||
816 | /* Get the value of the symbol referred to by the reloc. */ | |
817 | if (! _bfd_coff_get_external_symbols (abfd)) | |
818 | goto error_return; | |
819 | bfd_coff_swap_sym_in (abfd, | |
820 | ((bfd_byte *) obj_coff_external_syms (abfd) | |
821 | + (irelfn->r_symndx | |
822 | * bfd_coff_symesz (abfd))), | |
823 | &sym); | |
824 | if (sym.n_scnum != 0 && sym.n_scnum != sec->target_index) | |
825 | { | |
826 | ((*_bfd_error_handler) | |
827 | ("%s: 0x%lx: warning: symbol in unexpected section", | |
828 | bfd_get_filename (abfd), (unsigned long) paddr)); | |
829 | continue; | |
830 | } | |
831 | ||
832 | if (sym.n_sclass != C_EXT) | |
833 | { | |
834 | symval = (sym.n_value | |
835 | - sec->vma | |
836 | + sec->output_section->vma | |
837 | + sec->output_offset); | |
838 | } | |
839 | else | |
840 | { | |
841 | struct coff_link_hash_entry *h; | |
842 | ||
843 | h = obj_coff_sym_hashes (abfd)[irelfn->r_symndx]; | |
844 | BFD_ASSERT (h != NULL); | |
845 | if (h->root.type != bfd_link_hash_defined | |
846 | && h->root.type != bfd_link_hash_defweak) | |
847 | { | |
848 | /* This appears to be a reference to an undefined | |
849 | symbol. Just ignore it--it will be caught by the | |
850 | regular reloc processing. */ | |
851 | continue; | |
852 | } | |
853 | ||
854 | symval = (h->root.u.def.value | |
855 | + h->root.u.def.section->output_section->vma | |
856 | + h->root.u.def.section->output_offset); | |
857 | } | |
858 | ||
859 | symval += bfd_get_32 (abfd, contents + paddr - sec->vma); | |
860 | ||
861 | /* See if this function call can be shortened. */ | |
862 | foff = (symval | |
863 | - (irel->r_vaddr | |
864 | - sec->vma | |
865 | + sec->output_section->vma | |
866 | + sec->output_offset | |
867 | + 4)); | |
868 | if (foff < -0x1000 || foff >= 0x1000) | |
869 | { | |
870 | /* After all that work, we can't shorten this function call. */ | |
871 | continue; | |
872 | } | |
873 | ||
874 | /* Shorten the function call. */ | |
875 | ||
876 | /* For simplicity of coding, we are going to modify the section | |
877 | contents, the section relocs, and the BFD symbol table. We | |
878 | must tell the rest of the code not to free up this | |
879 | information. It would be possible to instead create a table | |
880 | of changes which have to be made, as is done in coff-mips.c; | |
881 | that would be more work, but would require less memory when | |
882 | the linker is run. */ | |
883 | ||
884 | if (coff_section_data (abfd, sec) == NULL) | |
885 | { | |
886 | sec->used_by_bfd = | |
887 | ((PTR) bfd_zalloc (abfd, sizeof (struct coff_section_tdata))); | |
888 | if (sec->used_by_bfd == NULL) | |
889 | goto error_return; | |
890 | } | |
891 | ||
892 | coff_section_data (abfd, sec)->relocs = internal_relocs; | |
893 | coff_section_data (abfd, sec)->keep_relocs = true; | |
894 | free_relocs = NULL; | |
895 | ||
896 | coff_section_data (abfd, sec)->contents = contents; | |
897 | coff_section_data (abfd, sec)->keep_contents = true; | |
898 | free_contents = NULL; | |
899 | ||
900 | obj_coff_keep_syms (abfd) = true; | |
901 | ||
902 | /* Replace the jsr with a bsr. */ | |
903 | ||
904 | /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and | |
905 | replace the jsr with a bsr. */ | |
906 | irel->r_type = R_SH_PCDISP; | |
907 | irel->r_symndx = irelfn->r_symndx; | |
908 | if (sym.n_sclass != C_EXT) | |
909 | { | |
910 | /* If this needs to be changed because of future relaxing, | |
911 | it will be handled here like other internal PCDISP | |
912 | relocs. */ | |
913 | bfd_put_16 (abfd, | |
914 | 0xb000 | ((foff >> 1) & 0xfff), | |
915 | contents + irel->r_vaddr - sec->vma); | |
916 | } | |
917 | else | |
918 | { | |
919 | /* We can't fully resolve this yet, because the external | |
920 | symbol value may be changed by future relaxing. We let | |
921 | the final link phase handle it. */ | |
922 | bfd_put_16 (abfd, 0xb000, contents + irel->r_vaddr - sec->vma); | |
923 | } | |
924 | ||
925 | /* See if there is another R_SH_USES reloc referring to the same | |
926 | register load. */ | |
927 | for (irelscan = internal_relocs; irelscan < irelend; irelscan++) | |
928 | if (irelscan->r_type == R_SH_USES | |
929 | && laddr == irelscan->r_vaddr - sec->vma + 4 + irelscan->r_offset) | |
930 | break; | |
931 | if (irelscan < irelend) | |
932 | { | |
933 | /* Some other function call depends upon this register load, | |
934 | and we have not yet converted that function call. | |
935 | Indeed, we may never be able to convert it. There is | |
936 | nothing else we can do at this point. */ | |
937 | continue; | |
938 | } | |
939 | ||
940 | /* Look for a R_SH_COUNT reloc on the location where the | |
941 | function address is stored. Do this before deleting any | |
942 | bytes, to avoid confusion about the address. */ | |
943 | for (irelcount = internal_relocs; irelcount < irelend; irelcount++) | |
944 | if (irelcount->r_vaddr == paddr | |
945 | && irelcount->r_type == R_SH_COUNT) | |
946 | break; | |
947 | ||
948 | /* Delete the register load. */ | |
949 | if (! sh_relax_delete_bytes (abfd, sec, laddr, 2)) | |
950 | goto error_return; | |
951 | ||
952 | /* That will change things, so, just in case it permits some | |
953 | other function call to come within range, we should relax | |
954 | again. Note that this is not required, and it may be slow. */ | |
955 | *again = true; | |
956 | ||
957 | /* Now check whether we got a COUNT reloc. */ | |
958 | if (irelcount >= irelend) | |
959 | { | |
960 | ((*_bfd_error_handler) | |
961 | ("%s: 0x%lx: warning: could not find expected COUNT reloc", | |
962 | bfd_get_filename (abfd), (unsigned long) paddr)); | |
963 | continue; | |
964 | } | |
965 | ||
966 | /* The number of uses is stored in the r_offset field. We've | |
967 | just deleted one. */ | |
968 | if (irelcount->r_offset == 0) | |
969 | { | |
970 | ((*_bfd_error_handler) ("%s: 0x%lx: warning: bad count", | |
971 | bfd_get_filename (abfd), | |
972 | (unsigned long) paddr)); | |
973 | continue; | |
974 | } | |
975 | ||
976 | --irelcount->r_offset; | |
977 | ||
978 | /* If there are no more uses, we can delete the address. Reload | |
979 | the address from irelfn, in case it was changed by the | |
980 | previous call to sh_relax_delete_bytes. */ | |
981 | if (irelcount->r_offset == 0) | |
982 | { | |
983 | if (! sh_relax_delete_bytes (abfd, sec, | |
984 | irelfn->r_vaddr - sec->vma, 4)) | |
985 | goto error_return; | |
986 | } | |
987 | ||
988 | /* We've done all we can with that function call. */ | |
989 | } | |
990 | ||
991 | /* Look for load and store instructions that we can align on four | |
992 | byte boundaries. */ | |
993 | if (have_code) | |
994 | { | |
995 | boolean swapped; | |
996 | ||
997 | /* Get the section contents. */ | |
998 | if (contents == NULL) | |
999 | { | |
1000 | if (coff_section_data (abfd, sec) != NULL | |
1001 | && coff_section_data (abfd, sec)->contents != NULL) | |
1002 | contents = coff_section_data (abfd, sec)->contents; | |
1003 | else | |
1004 | { | |
1005 | contents = (bfd_byte *) bfd_malloc (sec->_raw_size); | |
1006 | if (contents == NULL) | |
1007 | goto error_return; | |
1008 | free_contents = contents; | |
1009 | ||
1010 | if (! bfd_get_section_contents (abfd, sec, contents, | |
1011 | (file_ptr) 0, sec->_raw_size)) | |
1012 | goto error_return; | |
1013 | } | |
1014 | } | |
1015 | ||
1016 | if (! sh_align_loads (abfd, sec, internal_relocs, contents, &swapped)) | |
1017 | goto error_return; | |
1018 | ||
1019 | if (swapped) | |
1020 | { | |
1021 | if (coff_section_data (abfd, sec) == NULL) | |
1022 | { | |
1023 | sec->used_by_bfd = | |
1024 | ((PTR) bfd_zalloc (abfd, sizeof (struct coff_section_tdata))); | |
1025 | if (sec->used_by_bfd == NULL) | |
1026 | goto error_return; | |
1027 | } | |
1028 | ||
1029 | coff_section_data (abfd, sec)->relocs = internal_relocs; | |
1030 | coff_section_data (abfd, sec)->keep_relocs = true; | |
1031 | free_relocs = NULL; | |
1032 | ||
1033 | coff_section_data (abfd, sec)->contents = contents; | |
1034 | coff_section_data (abfd, sec)->keep_contents = true; | |
1035 | free_contents = NULL; | |
1036 | ||
1037 | obj_coff_keep_syms (abfd) = true; | |
1038 | } | |
1039 | } | |
1040 | ||
1041 | if (free_relocs != NULL) | |
1042 | { | |
1043 | free (free_relocs); | |
1044 | free_relocs = NULL; | |
1045 | } | |
1046 | ||
1047 | if (free_contents != NULL) | |
1048 | { | |
1049 | if (! link_info->keep_memory) | |
1050 | free (free_contents); | |
1051 | else | |
1052 | { | |
1053 | /* Cache the section contents for coff_link_input_bfd. */ | |
1054 | if (coff_section_data (abfd, sec) == NULL) | |
1055 | { | |
1056 | sec->used_by_bfd = | |
1057 | ((PTR) bfd_zalloc (abfd, sizeof (struct coff_section_tdata))); | |
1058 | if (sec->used_by_bfd == NULL) | |
1059 | goto error_return; | |
1060 | coff_section_data (abfd, sec)->relocs = NULL; | |
1061 | } | |
1062 | coff_section_data (abfd, sec)->contents = contents; | |
1063 | } | |
1064 | } | |
1065 | ||
1066 | return true; | |
1067 | ||
1068 | error_return: | |
1069 | if (free_relocs != NULL) | |
1070 | free (free_relocs); | |
1071 | if (free_contents != NULL) | |
1072 | free (free_contents); | |
1073 | return false; | |
1074 | } | |
1075 | ||
1076 | /* Delete some bytes from a section while relaxing. */ | |
1077 | ||
1078 | static boolean | |
1079 | sh_relax_delete_bytes (abfd, sec, addr, count) | |
1080 | bfd *abfd; | |
1081 | asection *sec; | |
1082 | bfd_vma addr; | |
1083 | int count; | |
1084 | { | |
1085 | bfd_byte *contents; | |
1086 | struct internal_reloc *irel, *irelend; | |
1087 | struct internal_reloc *irelalign; | |
1088 | bfd_vma toaddr; | |
1089 | bfd_byte *esym, *esymend; | |
1090 | bfd_size_type symesz; | |
1091 | struct coff_link_hash_entry **sym_hash; | |
1092 | asection *o; | |
1093 | ||
1094 | contents = coff_section_data (abfd, sec)->contents; | |
1095 | ||
1096 | /* The deletion must stop at the next ALIGN reloc for an aligment | |
1097 | power larger than the number of bytes we are deleting. */ | |
1098 | ||
1099 | irelalign = NULL; | |
1100 | toaddr = sec->_cooked_size; | |
1101 | ||
1102 | irel = coff_section_data (abfd, sec)->relocs; | |
1103 | irelend = irel + sec->reloc_count; | |
1104 | for (; irel < irelend; irel++) | |
1105 | { | |
1106 | if (irel->r_type == R_SH_ALIGN | |
1107 | && irel->r_vaddr - sec->vma > addr | |
1108 | && count < (1 << irel->r_offset)) | |
1109 | { | |
1110 | irelalign = irel; | |
1111 | toaddr = irel->r_vaddr - sec->vma; | |
1112 | break; | |
1113 | } | |
1114 | } | |
1115 | ||
1116 | /* Actually delete the bytes. */ | |
1117 | memmove (contents + addr, contents + addr + count, toaddr - addr - count); | |
1118 | if (irelalign == NULL) | |
1119 | sec->_cooked_size -= count; | |
1120 | else | |
1121 | { | |
1122 | int i; | |
1123 | ||
1124 | #define NOP_OPCODE (0x0009) | |
1125 | ||
1126 | BFD_ASSERT ((count & 1) == 0); | |
1127 | for (i = 0; i < count; i += 2) | |
1128 | bfd_put_16 (abfd, NOP_OPCODE, contents + toaddr - count + i); | |
1129 | } | |
1130 | ||
1131 | /* Adjust all the relocs. */ | |
1132 | for (irel = coff_section_data (abfd, sec)->relocs; irel < irelend; irel++) | |
1133 | { | |
1134 | bfd_vma nraddr, stop; | |
1135 | bfd_vma start = 0; | |
1136 | int insn = 0; | |
1137 | struct internal_syment sym; | |
1138 | int off, adjust, oinsn; | |
1139 | bfd_signed_vma voff = 0; | |
1140 | boolean overflow; | |
1141 | ||
1142 | /* Get the new reloc address. */ | |
1143 | nraddr = irel->r_vaddr - sec->vma; | |
1144 | if ((irel->r_vaddr - sec->vma > addr | |
1145 | && irel->r_vaddr - sec->vma < toaddr) | |
1146 | || (irel->r_type == R_SH_ALIGN | |
1147 | && irel->r_vaddr - sec->vma == toaddr)) | |
1148 | nraddr -= count; | |
1149 | ||
1150 | /* See if this reloc was for the bytes we have deleted, in which | |
1151 | case we no longer care about it. Don't delete relocs which | |
1152 | represent addresses, though. */ | |
1153 | if (irel->r_vaddr - sec->vma >= addr | |
1154 | && irel->r_vaddr - sec->vma < addr + count | |
1155 | && irel->r_type != R_SH_ALIGN | |
1156 | && irel->r_type != R_SH_CODE | |
1157 | && irel->r_type != R_SH_DATA | |
1158 | && irel->r_type != R_SH_LABEL) | |
1159 | irel->r_type = R_SH_UNUSED; | |
1160 | ||
1161 | /* If this is a PC relative reloc, see if the range it covers | |
1162 | includes the bytes we have deleted. */ | |
1163 | switch (irel->r_type) | |
1164 | { | |
1165 | default: | |
1166 | break; | |
1167 | ||
1168 | case R_SH_PCDISP8BY2: | |
1169 | case R_SH_PCDISP: | |
1170 | case R_SH_PCRELIMM8BY2: | |
1171 | case R_SH_PCRELIMM8BY4: | |
1172 | start = irel->r_vaddr - sec->vma; | |
1173 | insn = bfd_get_16 (abfd, contents + nraddr); | |
1174 | break; | |
1175 | } | |
1176 | ||
1177 | switch (irel->r_type) | |
1178 | { | |
1179 | default: | |
1180 | start = stop = addr; | |
1181 | break; | |
1182 | ||
1183 | case R_SH_IMM32: | |
17505c5c NC |
1184 | #ifdef COFF_WITH_PE |
1185 | case R_SH_IMM32CE: | |
1186 | case R_SH_IMAGEBASE: | |
1187 | #endif | |
252b5132 RH |
1188 | /* If this reloc is against a symbol defined in this |
1189 | section, and the symbol will not be adjusted below, we | |
1190 | must check the addend to see it will put the value in | |
1191 | range to be adjusted, and hence must be changed. */ | |
1192 | bfd_coff_swap_sym_in (abfd, | |
1193 | ((bfd_byte *) obj_coff_external_syms (abfd) | |
1194 | + (irel->r_symndx | |
1195 | * bfd_coff_symesz (abfd))), | |
1196 | &sym); | |
1197 | if (sym.n_sclass != C_EXT | |
1198 | && sym.n_scnum == sec->target_index | |
1199 | && ((bfd_vma) sym.n_value <= addr | |
1200 | || (bfd_vma) sym.n_value >= toaddr)) | |
1201 | { | |
1202 | bfd_vma val; | |
1203 | ||
1204 | val = bfd_get_32 (abfd, contents + nraddr); | |
1205 | val += sym.n_value; | |
1206 | if (val > addr && val < toaddr) | |
1207 | bfd_put_32 (abfd, val - count, contents + nraddr); | |
1208 | } | |
1209 | start = stop = addr; | |
1210 | break; | |
1211 | ||
1212 | case R_SH_PCDISP8BY2: | |
1213 | off = insn & 0xff; | |
1214 | if (off & 0x80) | |
1215 | off -= 0x100; | |
1216 | stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2); | |
1217 | break; | |
1218 | ||
1219 | case R_SH_PCDISP: | |
1220 | bfd_coff_swap_sym_in (abfd, | |
1221 | ((bfd_byte *) obj_coff_external_syms (abfd) | |
1222 | + (irel->r_symndx | |
1223 | * bfd_coff_symesz (abfd))), | |
1224 | &sym); | |
1225 | if (sym.n_sclass == C_EXT) | |
1226 | start = stop = addr; | |
1227 | else | |
1228 | { | |
1229 | off = insn & 0xfff; | |
1230 | if (off & 0x800) | |
1231 | off -= 0x1000; | |
1232 | stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2); | |
1233 | } | |
1234 | break; | |
1235 | ||
1236 | case R_SH_PCRELIMM8BY2: | |
1237 | off = insn & 0xff; | |
1238 | stop = start + 4 + off * 2; | |
1239 | break; | |
1240 | ||
1241 | case R_SH_PCRELIMM8BY4: | |
1242 | off = insn & 0xff; | |
1243 | stop = (start &~ (bfd_vma) 3) + 4 + off * 4; | |
1244 | break; | |
1245 | ||
1246 | case R_SH_SWITCH8: | |
1247 | case R_SH_SWITCH16: | |
1248 | case R_SH_SWITCH32: | |
1249 | /* These relocs types represent | |
1250 | .word L2-L1 | |
1251 | The r_offset field holds the difference between the reloc | |
1252 | address and L1. That is the start of the reloc, and | |
1253 | adding in the contents gives us the top. We must adjust | |
1254 | both the r_offset field and the section contents. */ | |
1255 | ||
1256 | start = irel->r_vaddr - sec->vma; | |
1257 | stop = (bfd_vma) ((bfd_signed_vma) start - (long) irel->r_offset); | |
1258 | ||
1259 | if (start > addr | |
1260 | && start < toaddr | |
1261 | && (stop <= addr || stop >= toaddr)) | |
1262 | irel->r_offset += count; | |
1263 | else if (stop > addr | |
1264 | && stop < toaddr | |
1265 | && (start <= addr || start >= toaddr)) | |
1266 | irel->r_offset -= count; | |
1267 | ||
1268 | start = stop; | |
1269 | ||
1270 | if (irel->r_type == R_SH_SWITCH16) | |
1271 | voff = bfd_get_signed_16 (abfd, contents + nraddr); | |
1272 | else if (irel->r_type == R_SH_SWITCH8) | |
1273 | voff = bfd_get_8 (abfd, contents + nraddr); | |
1274 | else | |
1275 | voff = bfd_get_signed_32 (abfd, contents + nraddr); | |
1276 | stop = (bfd_vma) ((bfd_signed_vma) start + voff); | |
1277 | ||
1278 | break; | |
1279 | ||
1280 | case R_SH_USES: | |
1281 | start = irel->r_vaddr - sec->vma; | |
1282 | stop = (bfd_vma) ((bfd_signed_vma) start | |
1283 | + (long) irel->r_offset | |
1284 | + 4); | |
1285 | break; | |
1286 | } | |
1287 | ||
1288 | if (start > addr | |
1289 | && start < toaddr | |
1290 | && (stop <= addr || stop >= toaddr)) | |
1291 | adjust = count; | |
1292 | else if (stop > addr | |
1293 | && stop < toaddr | |
1294 | && (start <= addr || start >= toaddr)) | |
1295 | adjust = - count; | |
1296 | else | |
1297 | adjust = 0; | |
1298 | ||
1299 | if (adjust != 0) | |
1300 | { | |
1301 | oinsn = insn; | |
1302 | overflow = false; | |
1303 | switch (irel->r_type) | |
1304 | { | |
1305 | default: | |
1306 | abort (); | |
1307 | break; | |
1308 | ||
1309 | case R_SH_PCDISP8BY2: | |
1310 | case R_SH_PCRELIMM8BY2: | |
1311 | insn += adjust / 2; | |
1312 | if ((oinsn & 0xff00) != (insn & 0xff00)) | |
1313 | overflow = true; | |
1314 | bfd_put_16 (abfd, insn, contents + nraddr); | |
1315 | break; | |
1316 | ||
1317 | case R_SH_PCDISP: | |
1318 | insn += adjust / 2; | |
1319 | if ((oinsn & 0xf000) != (insn & 0xf000)) | |
1320 | overflow = true; | |
1321 | bfd_put_16 (abfd, insn, contents + nraddr); | |
1322 | break; | |
1323 | ||
1324 | case R_SH_PCRELIMM8BY4: | |
1325 | BFD_ASSERT (adjust == count || count >= 4); | |
1326 | if (count >= 4) | |
1327 | insn += adjust / 4; | |
1328 | else | |
1329 | { | |
1330 | if ((irel->r_vaddr & 3) == 0) | |
1331 | ++insn; | |
1332 | } | |
1333 | if ((oinsn & 0xff00) != (insn & 0xff00)) | |
1334 | overflow = true; | |
1335 | bfd_put_16 (abfd, insn, contents + nraddr); | |
1336 | break; | |
1337 | ||
1338 | case R_SH_SWITCH8: | |
1339 | voff += adjust; | |
1340 | if (voff < 0 || voff >= 0xff) | |
1341 | overflow = true; | |
1342 | bfd_put_8 (abfd, voff, contents + nraddr); | |
1343 | break; | |
1344 | ||
1345 | case R_SH_SWITCH16: | |
1346 | voff += adjust; | |
1347 | if (voff < - 0x8000 || voff >= 0x8000) | |
1348 | overflow = true; | |
1349 | bfd_put_signed_16 (abfd, voff, contents + nraddr); | |
1350 | break; | |
1351 | ||
1352 | case R_SH_SWITCH32: | |
1353 | voff += adjust; | |
1354 | bfd_put_signed_32 (abfd, voff, contents + nraddr); | |
1355 | break; | |
1356 | ||
1357 | case R_SH_USES: | |
1358 | irel->r_offset += adjust; | |
1359 | break; | |
1360 | } | |
1361 | ||
1362 | if (overflow) | |
1363 | { | |
1364 | ((*_bfd_error_handler) | |
1365 | ("%s: 0x%lx: fatal: reloc overflow while relaxing", | |
1366 | bfd_get_filename (abfd), (unsigned long) irel->r_vaddr)); | |
1367 | bfd_set_error (bfd_error_bad_value); | |
1368 | return false; | |
1369 | } | |
1370 | } | |
1371 | ||
1372 | irel->r_vaddr = nraddr + sec->vma; | |
1373 | } | |
1374 | ||
1375 | /* Look through all the other sections. If there contain any IMM32 | |
1376 | relocs against internal symbols which we are not going to adjust | |
1377 | below, we may need to adjust the addends. */ | |
1378 | for (o = abfd->sections; o != NULL; o = o->next) | |
1379 | { | |
1380 | struct internal_reloc *internal_relocs; | |
1381 | struct internal_reloc *irelscan, *irelscanend; | |
1382 | bfd_byte *ocontents; | |
1383 | ||
1384 | if (o == sec | |
1385 | || (o->flags & SEC_RELOC) == 0 | |
1386 | || o->reloc_count == 0) | |
1387 | continue; | |
1388 | ||
1389 | /* We always cache the relocs. Perhaps, if info->keep_memory is | |
1390 | false, we should free them, if we are permitted to, when we | |
1391 | leave sh_coff_relax_section. */ | |
1392 | internal_relocs = (_bfd_coff_read_internal_relocs | |
1393 | (abfd, o, true, (bfd_byte *) NULL, false, | |
1394 | (struct internal_reloc *) NULL)); | |
1395 | if (internal_relocs == NULL) | |
1396 | return false; | |
1397 | ||
1398 | ocontents = NULL; | |
1399 | irelscanend = internal_relocs + o->reloc_count; | |
1400 | for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++) | |
1401 | { | |
1402 | struct internal_syment sym; | |
1403 | ||
17505c5c NC |
1404 | #ifdef COFF_WITH_PE |
1405 | if (irelscan->r_type != R_SH_IMM32 | |
1406 | && irelscan->r_type != R_SH_IMAGEBASE | |
1407 | && irelscan->r_type != R_SH_IMM32CE) | |
1408 | #else | |
252b5132 | 1409 | if (irelscan->r_type != R_SH_IMM32) |
17505c5c | 1410 | #endif |
252b5132 RH |
1411 | continue; |
1412 | ||
1413 | bfd_coff_swap_sym_in (abfd, | |
1414 | ((bfd_byte *) obj_coff_external_syms (abfd) | |
1415 | + (irelscan->r_symndx | |
1416 | * bfd_coff_symesz (abfd))), | |
1417 | &sym); | |
1418 | if (sym.n_sclass != C_EXT | |
1419 | && sym.n_scnum == sec->target_index | |
1420 | && ((bfd_vma) sym.n_value <= addr | |
1421 | || (bfd_vma) sym.n_value >= toaddr)) | |
1422 | { | |
1423 | bfd_vma val; | |
1424 | ||
1425 | if (ocontents == NULL) | |
1426 | { | |
1427 | if (coff_section_data (abfd, o)->contents != NULL) | |
1428 | ocontents = coff_section_data (abfd, o)->contents; | |
1429 | else | |
1430 | { | |
1431 | /* We always cache the section contents. | |
1432 | Perhaps, if info->keep_memory is false, we | |
1433 | should free them, if we are permitted to, | |
1434 | when we leave sh_coff_relax_section. */ | |
1435 | ocontents = (bfd_byte *) bfd_malloc (o->_raw_size); | |
1436 | if (ocontents == NULL) | |
1437 | return false; | |
1438 | if (! bfd_get_section_contents (abfd, o, ocontents, | |
1439 | (file_ptr) 0, | |
1440 | o->_raw_size)) | |
1441 | return false; | |
1442 | coff_section_data (abfd, o)->contents = ocontents; | |
1443 | } | |
1444 | } | |
1445 | ||
1446 | val = bfd_get_32 (abfd, ocontents + irelscan->r_vaddr - o->vma); | |
1447 | val += sym.n_value; | |
1448 | if (val > addr && val < toaddr) | |
1449 | bfd_put_32 (abfd, val - count, | |
1450 | ocontents + irelscan->r_vaddr - o->vma); | |
1451 | ||
1452 | coff_section_data (abfd, o)->keep_contents = true; | |
1453 | } | |
1454 | } | |
1455 | } | |
1456 | ||
1457 | /* Adjusting the internal symbols will not work if something has | |
1458 | already retrieved the generic symbols. It would be possible to | |
1459 | make this work by adjusting the generic symbols at the same time. | |
1460 | However, this case should not arise in normal usage. */ | |
1461 | if (obj_symbols (abfd) != NULL | |
1462 | || obj_raw_syments (abfd) != NULL) | |
1463 | { | |
1464 | ((*_bfd_error_handler) | |
1465 | ("%s: fatal: generic symbols retrieved before relaxing", | |
1466 | bfd_get_filename (abfd))); | |
1467 | bfd_set_error (bfd_error_invalid_operation); | |
1468 | return false; | |
1469 | } | |
1470 | ||
1471 | /* Adjust all the symbols. */ | |
1472 | sym_hash = obj_coff_sym_hashes (abfd); | |
1473 | symesz = bfd_coff_symesz (abfd); | |
1474 | esym = (bfd_byte *) obj_coff_external_syms (abfd); | |
1475 | esymend = esym + obj_raw_syment_count (abfd) * symesz; | |
1476 | while (esym < esymend) | |
1477 | { | |
1478 | struct internal_syment isym; | |
1479 | ||
1480 | bfd_coff_swap_sym_in (abfd, (PTR) esym, (PTR) &isym); | |
1481 | ||
1482 | if (isym.n_scnum == sec->target_index | |
1483 | && (bfd_vma) isym.n_value > addr | |
1484 | && (bfd_vma) isym.n_value < toaddr) | |
1485 | { | |
1486 | isym.n_value -= count; | |
1487 | ||
1488 | bfd_coff_swap_sym_out (abfd, (PTR) &isym, (PTR) esym); | |
1489 | ||
1490 | if (*sym_hash != NULL) | |
1491 | { | |
1492 | BFD_ASSERT ((*sym_hash)->root.type == bfd_link_hash_defined | |
1493 | || (*sym_hash)->root.type == bfd_link_hash_defweak); | |
1494 | BFD_ASSERT ((*sym_hash)->root.u.def.value >= addr | |
1495 | && (*sym_hash)->root.u.def.value < toaddr); | |
1496 | (*sym_hash)->root.u.def.value -= count; | |
1497 | } | |
1498 | } | |
1499 | ||
1500 | esym += (isym.n_numaux + 1) * symesz; | |
1501 | sym_hash += isym.n_numaux + 1; | |
1502 | } | |
1503 | ||
1504 | /* See if we can move the ALIGN reloc forward. We have adjusted | |
1505 | r_vaddr for it already. */ | |
1506 | if (irelalign != NULL) | |
1507 | { | |
1508 | bfd_vma alignto, alignaddr; | |
1509 | ||
1510 | alignto = BFD_ALIGN (toaddr, 1 << irelalign->r_offset); | |
1511 | alignaddr = BFD_ALIGN (irelalign->r_vaddr - sec->vma, | |
1512 | 1 << irelalign->r_offset); | |
1513 | if (alignto != alignaddr) | |
1514 | { | |
1515 | /* Tail recursion. */ | |
1516 | return sh_relax_delete_bytes (abfd, sec, alignaddr, | |
1517 | alignto - alignaddr); | |
1518 | } | |
1519 | } | |
1520 | ||
1521 | return true; | |
1522 | } | |
1523 | \f | |
1524 | /* This is yet another version of the SH opcode table, used to rapidly | |
1525 | get information about a particular instruction. */ | |
1526 | ||
1527 | /* The opcode map is represented by an array of these structures. The | |
1528 | array is indexed by the high order four bits in the instruction. */ | |
1529 | ||
1530 | struct sh_major_opcode | |
1531 | { | |
1532 | /* A pointer to the instruction list. This is an array which | |
1533 | contains all the instructions with this major opcode. */ | |
1534 | const struct sh_minor_opcode *minor_opcodes; | |
1535 | /* The number of elements in minor_opcodes. */ | |
1536 | unsigned short count; | |
1537 | }; | |
1538 | ||
1539 | /* This structure holds information for a set of SH opcodes. The | |
1540 | instruction code is anded with the mask value, and the resulting | |
1541 | value is used to search the order opcode list. */ | |
1542 | ||
1543 | struct sh_minor_opcode | |
1544 | { | |
1545 | /* The sorted opcode list. */ | |
1546 | const struct sh_opcode *opcodes; | |
1547 | /* The number of elements in opcodes. */ | |
1548 | unsigned short count; | |
1549 | /* The mask value to use when searching the opcode list. */ | |
1550 | unsigned short mask; | |
1551 | }; | |
1552 | ||
1553 | /* This structure holds information for an SH instruction. An array | |
1554 | of these structures is sorted in order by opcode. */ | |
1555 | ||
1556 | struct sh_opcode | |
1557 | { | |
1558 | /* The code for this instruction, after it has been anded with the | |
1559 | mask value in the sh_major_opcode structure. */ | |
1560 | unsigned short opcode; | |
1561 | /* Flags for this instruction. */ | |
86033394 | 1562 | unsigned long flags; |
252b5132 RH |
1563 | }; |
1564 | ||
1565 | /* Flag which appear in the sh_opcode structure. */ | |
1566 | ||
1567 | /* This instruction loads a value from memory. */ | |
1568 | #define LOAD (0x1) | |
1569 | ||
1570 | /* This instruction stores a value to memory. */ | |
1571 | #define STORE (0x2) | |
1572 | ||
1573 | /* This instruction is a branch. */ | |
1574 | #define BRANCH (0x4) | |
1575 | ||
1576 | /* This instruction has a delay slot. */ | |
1577 | #define DELAY (0x8) | |
1578 | ||
1579 | /* This instruction uses the value in the register in the field at | |
1580 | mask 0x0f00 of the instruction. */ | |
1581 | #define USES1 (0x10) | |
84dcfba7 | 1582 | #define USES1_REG(x) ((x & 0x0f00) >> 8) |
252b5132 RH |
1583 | |
1584 | /* This instruction uses the value in the register in the field at | |
1585 | mask 0x00f0 of the instruction. */ | |
1586 | #define USES2 (0x20) | |
84dcfba7 | 1587 | #define USES2_REG(x) ((x & 0x00f0) >> 4) |
252b5132 RH |
1588 | |
1589 | /* This instruction uses the value in register 0. */ | |
1590 | #define USESR0 (0x40) | |
1591 | ||
1592 | /* This instruction sets the value in the register in the field at | |
1593 | mask 0x0f00 of the instruction. */ | |
1594 | #define SETS1 (0x80) | |
84dcfba7 | 1595 | #define SETS1_REG(x) ((x & 0x0f00) >> 8) |
252b5132 RH |
1596 | |
1597 | /* This instruction sets the value in the register in the field at | |
1598 | mask 0x00f0 of the instruction. */ | |
1599 | #define SETS2 (0x100) | |
84dcfba7 | 1600 | #define SETS2_REG(x) ((x & 0x00f0) >> 4) |
252b5132 RH |
1601 | |
1602 | /* This instruction sets register 0. */ | |
1603 | #define SETSR0 (0x200) | |
1604 | ||
1605 | /* This instruction sets a special register. */ | |
1606 | #define SETSSP (0x400) | |
1607 | ||
1608 | /* This instruction uses a special register. */ | |
1609 | #define USESSP (0x800) | |
1610 | ||
1611 | /* This instruction uses the floating point register in the field at | |
1612 | mask 0x0f00 of the instruction. */ | |
1613 | #define USESF1 (0x1000) | |
84dcfba7 | 1614 | #define USESF1_REG(x) ((x & 0x0f00) >> 8) |
252b5132 RH |
1615 | |
1616 | /* This instruction uses the floating point register in the field at | |
1617 | mask 0x00f0 of the instruction. */ | |
1618 | #define USESF2 (0x2000) | |
84dcfba7 | 1619 | #define USESF2_REG(x) ((x & 0x00f0) >> 4) |
252b5132 RH |
1620 | |
1621 | /* This instruction uses floating point register 0. */ | |
1622 | #define USESF0 (0x4000) | |
1623 | ||
1624 | /* This instruction sets the floating point register in the field at | |
1625 | mask 0x0f00 of the instruction. */ | |
1626 | #define SETSF1 (0x8000) | |
84dcfba7 | 1627 | #define SETSF1_REG(x) ((x & 0x0f00) >> 8) |
252b5132 | 1628 | |
d4845d57 JR |
1629 | #define USESAS (0x10000) |
1630 | #define USESAS_REG(x) (((((x) >> 8) - 2) & 3) + 2) | |
1631 | #define USESR8 (0x20000) | |
1632 | #define SETSAS (0x40000) | |
1633 | #define SETSAS_REG(x) USESAS_REG (x) | |
1634 | ||
86033394 | 1635 | #ifndef COFF_IMAGE_WITH_PE |
252b5132 RH |
1636 | static boolean sh_insn_uses_reg |
1637 | PARAMS ((unsigned int, const struct sh_opcode *, unsigned int)); | |
84dcfba7 JR |
1638 | static boolean sh_insn_sets_reg |
1639 | PARAMS ((unsigned int, const struct sh_opcode *, unsigned int)); | |
1640 | static boolean sh_insn_uses_or_sets_reg | |
1641 | PARAMS ((unsigned int, const struct sh_opcode *, unsigned int)); | |
252b5132 RH |
1642 | static boolean sh_insn_uses_freg |
1643 | PARAMS ((unsigned int, const struct sh_opcode *, unsigned int)); | |
84dcfba7 JR |
1644 | static boolean sh_insn_sets_freg |
1645 | PARAMS ((unsigned int, const struct sh_opcode *, unsigned int)); | |
1646 | static boolean sh_insn_uses_or_sets_freg | |
1647 | PARAMS ((unsigned int, const struct sh_opcode *, unsigned int)); | |
252b5132 RH |
1648 | static boolean sh_insns_conflict |
1649 | PARAMS ((unsigned int, const struct sh_opcode *, unsigned int, | |
1650 | const struct sh_opcode *)); | |
1651 | static boolean sh_load_use | |
1652 | PARAMS ((unsigned int, const struct sh_opcode *, unsigned int, | |
1653 | const struct sh_opcode *)); | |
86033394 | 1654 | #endif |
252b5132 RH |
1655 | /* The opcode maps. */ |
1656 | ||
1657 | #define MAP(a) a, sizeof a / sizeof a[0] | |
1658 | ||
1659 | static const struct sh_opcode sh_opcode00[] = | |
1660 | { | |
1661 | { 0x0008, SETSSP }, /* clrt */ | |
1662 | { 0x0009, 0 }, /* nop */ | |
1663 | { 0x000b, BRANCH | DELAY | USESSP }, /* rts */ | |
1664 | { 0x0018, SETSSP }, /* sett */ | |
1665 | { 0x0019, SETSSP }, /* div0u */ | |
1666 | { 0x001b, 0 }, /* sleep */ | |
1667 | { 0x0028, SETSSP }, /* clrmac */ | |
1668 | { 0x002b, BRANCH | DELAY | SETSSP }, /* rte */ | |
1669 | { 0x0038, USESSP | SETSSP }, /* ldtlb */ | |
1670 | { 0x0048, SETSSP }, /* clrs */ | |
1671 | { 0x0058, SETSSP } /* sets */ | |
1672 | }; | |
1673 | ||
1674 | static const struct sh_opcode sh_opcode01[] = | |
1675 | { | |
252b5132 RH |
1676 | { 0x0003, BRANCH | DELAY | USES1 | SETSSP }, /* bsrf rn */ |
1677 | { 0x000a, SETS1 | USESSP }, /* sts mach,rn */ | |
252b5132 | 1678 | { 0x001a, SETS1 | USESSP }, /* sts macl,rn */ |
252b5132 RH |
1679 | { 0x0023, BRANCH | DELAY | USES1 }, /* braf rn */ |
1680 | { 0x0029, SETS1 | USESSP }, /* movt rn */ | |
1681 | { 0x002a, SETS1 | USESSP }, /* sts pr,rn */ | |
d4845d57 JR |
1682 | { 0x005a, SETS1 | USESSP }, /* sts fpul,rn */ |
1683 | { 0x006a, SETS1 | USESSP }, /* sts fpscr,rn / sts dsr,rn */ | |
1684 | { 0x0083, LOAD | USES1 }, /* pref @rn */ | |
1685 | { 0x007a, SETS1 | USESSP }, /* sts a0,rn */ | |
1686 | { 0x008a, SETS1 | USESSP }, /* sts x0,rn */ | |
1687 | { 0x009a, SETS1 | USESSP }, /* sts x1,rn */ | |
1688 | { 0x00aa, SETS1 | USESSP }, /* sts y0,rn */ | |
1689 | { 0x00ba, SETS1 | USESSP } /* sts y1,rn */ | |
1690 | }; | |
1691 | ||
1692 | /* These sixteen instructions can be handled with one table entry below. */ | |
1693 | #if 0 | |
1694 | { 0x0002, SETS1 | USESSP }, /* stc sr,rn */ | |
1695 | { 0x0012, SETS1 | USESSP }, /* stc gbr,rn */ | |
1696 | { 0x0022, SETS1 | USESSP }, /* stc vbr,rn */ | |
252b5132 RH |
1697 | { 0x0032, SETS1 | USESSP }, /* stc ssr,rn */ |
1698 | { 0x0042, SETS1 | USESSP }, /* stc spc,rn */ | |
d4845d57 JR |
1699 | { 0x0052, SETS1 | USESSP }, /* stc mod,rn */ |
1700 | { 0x0062, SETS1 | USESSP }, /* stc rs,rn */ | |
1701 | { 0x0072, SETS1 | USESSP }, /* stc re,rn */ | |
252b5132 | 1702 | { 0x0082, SETS1 | USESSP }, /* stc r0_bank,rn */ |
252b5132 RH |
1703 | { 0x0092, SETS1 | USESSP }, /* stc r1_bank,rn */ |
1704 | { 0x00a2, SETS1 | USESSP }, /* stc r2_bank,rn */ | |
1705 | { 0x00b2, SETS1 | USESSP }, /* stc r3_bank,rn */ | |
1706 | { 0x00c2, SETS1 | USESSP }, /* stc r4_bank,rn */ | |
1707 | { 0x00d2, SETS1 | USESSP }, /* stc r5_bank,rn */ | |
1708 | { 0x00e2, SETS1 | USESSP }, /* stc r6_bank,rn */ | |
1709 | { 0x00f2, SETS1 | USESSP } /* stc r7_bank,rn */ | |
d4845d57 | 1710 | #endif |
252b5132 RH |
1711 | |
1712 | static const struct sh_opcode sh_opcode02[] = | |
1713 | { | |
d4845d57 | 1714 | { 0x0002, SETS1 | USESSP }, /* stc <special_reg>,rn */ |
252b5132 RH |
1715 | { 0x0004, STORE | USES1 | USES2 | USESR0 }, /* mov.b rm,@(r0,rn) */ |
1716 | { 0x0005, STORE | USES1 | USES2 | USESR0 }, /* mov.w rm,@(r0,rn) */ | |
1717 | { 0x0006, STORE | USES1 | USES2 | USESR0 }, /* mov.l rm,@(r0,rn) */ | |
1718 | { 0x0007, SETSSP | USES1 | USES2 }, /* mul.l rm,rn */ | |
1719 | { 0x000c, LOAD | SETS1 | USES2 | USESR0 }, /* mov.b @(r0,rm),rn */ | |
1720 | { 0x000d, LOAD | SETS1 | USES2 | USESR0 }, /* mov.w @(r0,rm),rn */ | |
1721 | { 0x000e, LOAD | SETS1 | USES2 | USESR0 }, /* mov.l @(r0,rm),rn */ | |
1722 | { 0x000f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.l @rm+,@rn+ */ | |
1723 | }; | |
1724 | ||
1725 | static const struct sh_minor_opcode sh_opcode0[] = | |
1726 | { | |
1727 | { MAP (sh_opcode00), 0xffff }, | |
1728 | { MAP (sh_opcode01), 0xf0ff }, | |
1729 | { MAP (sh_opcode02), 0xf00f } | |
1730 | }; | |
1731 | ||
1732 | static const struct sh_opcode sh_opcode10[] = | |
1733 | { | |
1734 | { 0x1000, STORE | USES1 | USES2 } /* mov.l rm,@(disp,rn) */ | |
1735 | }; | |
1736 | ||
1737 | static const struct sh_minor_opcode sh_opcode1[] = | |
1738 | { | |
1739 | { MAP (sh_opcode10), 0xf000 } | |
1740 | }; | |
1741 | ||
1742 | static const struct sh_opcode sh_opcode20[] = | |
1743 | { | |
1744 | { 0x2000, STORE | USES1 | USES2 }, /* mov.b rm,@rn */ | |
1745 | { 0x2001, STORE | USES1 | USES2 }, /* mov.w rm,@rn */ | |
1746 | { 0x2002, STORE | USES1 | USES2 }, /* mov.l rm,@rn */ | |
1747 | { 0x2004, STORE | SETS1 | USES1 | USES2 }, /* mov.b rm,@-rn */ | |
1748 | { 0x2005, STORE | SETS1 | USES1 | USES2 }, /* mov.w rm,@-rn */ | |
1749 | { 0x2006, STORE | SETS1 | USES1 | USES2 }, /* mov.l rm,@-rn */ | |
1750 | { 0x2007, SETSSP | USES1 | USES2 | USESSP }, /* div0s */ | |
1751 | { 0x2008, SETSSP | USES1 | USES2 }, /* tst rm,rn */ | |
1752 | { 0x2009, SETS1 | USES1 | USES2 }, /* and rm,rn */ | |
1753 | { 0x200a, SETS1 | USES1 | USES2 }, /* xor rm,rn */ | |
1754 | { 0x200b, SETS1 | USES1 | USES2 }, /* or rm,rn */ | |
1755 | { 0x200c, SETSSP | USES1 | USES2 }, /* cmp/str rm,rn */ | |
1756 | { 0x200d, SETS1 | USES1 | USES2 }, /* xtrct rm,rn */ | |
1757 | { 0x200e, SETSSP | USES1 | USES2 }, /* mulu.w rm,rn */ | |
1758 | { 0x200f, SETSSP | USES1 | USES2 } /* muls.w rm,rn */ | |
1759 | }; | |
1760 | ||
1761 | static const struct sh_minor_opcode sh_opcode2[] = | |
1762 | { | |
1763 | { MAP (sh_opcode20), 0xf00f } | |
1764 | }; | |
1765 | ||
1766 | static const struct sh_opcode sh_opcode30[] = | |
1767 | { | |
1768 | { 0x3000, SETSSP | USES1 | USES2 }, /* cmp/eq rm,rn */ | |
1769 | { 0x3002, SETSSP | USES1 | USES2 }, /* cmp/hs rm,rn */ | |
1770 | { 0x3003, SETSSP | USES1 | USES2 }, /* cmp/ge rm,rn */ | |
1771 | { 0x3004, SETSSP | USESSP | USES1 | USES2 }, /* div1 rm,rn */ | |
1772 | { 0x3005, SETSSP | USES1 | USES2 }, /* dmulu.l rm,rn */ | |
1773 | { 0x3006, SETSSP | USES1 | USES2 }, /* cmp/hi rm,rn */ | |
1774 | { 0x3007, SETSSP | USES1 | USES2 }, /* cmp/gt rm,rn */ | |
1775 | { 0x3008, SETS1 | USES1 | USES2 }, /* sub rm,rn */ | |
1776 | { 0x300a, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* subc rm,rn */ | |
1777 | { 0x300b, SETS1 | SETSSP | USES1 | USES2 }, /* subv rm,rn */ | |
1778 | { 0x300c, SETS1 | USES1 | USES2 }, /* add rm,rn */ | |
1779 | { 0x300d, SETSSP | USES1 | USES2 }, /* dmuls.l rm,rn */ | |
1780 | { 0x300e, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* addc rm,rn */ | |
1781 | { 0x300f, SETS1 | SETSSP | USES1 | USES2 } /* addv rm,rn */ | |
1782 | }; | |
1783 | ||
1784 | static const struct sh_minor_opcode sh_opcode3[] = | |
1785 | { | |
1786 | { MAP (sh_opcode30), 0xf00f } | |
1787 | }; | |
1788 | ||
1789 | static const struct sh_opcode sh_opcode40[] = | |
1790 | { | |
1791 | { 0x4000, SETS1 | SETSSP | USES1 }, /* shll rn */ | |
1792 | { 0x4001, SETS1 | SETSSP | USES1 }, /* shlr rn */ | |
1793 | { 0x4002, STORE | SETS1 | USES1 | USESSP }, /* sts.l mach,@-rn */ | |
252b5132 RH |
1794 | { 0x4004, SETS1 | SETSSP | USES1 }, /* rotl rn */ |
1795 | { 0x4005, SETS1 | SETSSP | USES1 }, /* rotr rn */ | |
1796 | { 0x4006, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,mach */ | |
252b5132 RH |
1797 | { 0x4008, SETS1 | USES1 }, /* shll2 rn */ |
1798 | { 0x4009, SETS1 | USES1 }, /* shlr2 rn */ | |
1799 | { 0x400a, SETSSP | USES1 }, /* lds rm,mach */ | |
1800 | { 0x400b, BRANCH | DELAY | USES1 }, /* jsr @rn */ | |
252b5132 RH |
1801 | { 0x4010, SETS1 | SETSSP | USES1 }, /* dt rn */ |
1802 | { 0x4011, SETSSP | USES1 }, /* cmp/pz rn */ | |
1803 | { 0x4012, STORE | SETS1 | USES1 | USESSP }, /* sts.l macl,@-rn */ | |
d4845d57 | 1804 | { 0x4014, SETSSP | USES1 }, /* setrc rm */ |
252b5132 RH |
1805 | { 0x4015, SETSSP | USES1 }, /* cmp/pl rn */ |
1806 | { 0x4016, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,macl */ | |
252b5132 RH |
1807 | { 0x4018, SETS1 | USES1 }, /* shll8 rn */ |
1808 | { 0x4019, SETS1 | USES1 }, /* shlr8 rn */ | |
1809 | { 0x401a, SETSSP | USES1 }, /* lds rm,macl */ | |
1810 | { 0x401b, LOAD | SETSSP | USES1 }, /* tas.b @rn */ | |
252b5132 RH |
1811 | { 0x4020, SETS1 | SETSSP | USES1 }, /* shal rn */ |
1812 | { 0x4021, SETS1 | SETSSP | USES1 }, /* shar rn */ | |
1813 | { 0x4022, STORE | SETS1 | USES1 | USESSP }, /* sts.l pr,@-rn */ | |
252b5132 RH |
1814 | { 0x4024, SETS1 | SETSSP | USES1 | USESSP }, /* rotcl rn */ |
1815 | { 0x4025, SETS1 | SETSSP | USES1 | USESSP }, /* rotcr rn */ | |
1816 | { 0x4026, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,pr */ | |
252b5132 RH |
1817 | { 0x4028, SETS1 | USES1 }, /* shll16 rn */ |
1818 | { 0x4029, SETS1 | USES1 }, /* shlr16 rn */ | |
1819 | { 0x402a, SETSSP | USES1 }, /* lds rm,pr */ | |
1820 | { 0x402b, BRANCH | DELAY | USES1 }, /* jmp @rn */ | |
d4845d57 JR |
1821 | { 0x4052, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpul,@-rn */ |
1822 | { 0x4056, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpul */ | |
1823 | { 0x405a, SETSSP | USES1 }, /* lds.l rm,fpul */ | |
1824 | { 0x4062, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpscr / dsr,@-rn */ | |
1825 | { 0x4066, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpscr / dsr */ | |
1826 | { 0x406a, SETSSP | USES1 }, /* lds rm,fpscr / lds rm,dsr */ | |
1827 | { 0x4072, STORE | SETS1 | USES1 | USESSP }, /* sts.l a0,@-rn */ | |
1828 | { 0x4076, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,a0 */ | |
1829 | { 0x407a, SETSSP | USES1 }, /* lds.l rm,a0 */ | |
1830 | { 0x4082, STORE | SETS1 | USES1 | USESSP }, /* sts.l x0,@-rn */ | |
1831 | { 0x4086, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x0 */ | |
1832 | { 0x408a, SETSSP | USES1 }, /* lds.l rm,x0 */ | |
1833 | { 0x4092, STORE | SETS1 | USES1 | USESSP }, /* sts.l x1,@-rn */ | |
1834 | { 0x4096, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x1 */ | |
1835 | { 0x409a, SETSSP | USES1 }, /* lds.l rm,x1 */ | |
1836 | { 0x40a2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y0,@-rn */ | |
1837 | { 0x40a6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y0 */ | |
1838 | { 0x40aa, SETSSP | USES1 }, /* lds.l rm,y0 */ | |
1839 | { 0x40b2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y1,@-rn */ | |
1840 | { 0x40b6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y1 */ | |
1841 | { 0x40ba, SETSSP | USES1 } /* lds.l rm,y1 */ | |
1842 | #if 0 /* These groups sixteen insns can be | |
1843 | handled with one table entry each below. */ | |
1844 | { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l sr,@-rn */ | |
1845 | { 0x4013, STORE | SETS1 | USES1 | USESSP }, /* stc.l gbr,@-rn */ | |
1846 | { 0x4023, STORE | SETS1 | USES1 | USESSP }, /* stc.l vbr,@-rn */ | |
252b5132 | 1847 | { 0x4033, STORE | SETS1 | USES1 | USESSP }, /* stc.l ssr,@-rn */ |
252b5132 | 1848 | { 0x4043, STORE | SETS1 | USES1 | USESSP }, /* stc.l spc,@-rn */ |
d4845d57 JR |
1849 | { 0x4053, STORE | SETS1 | USES1 | USESSP }, /* stc.l mod,@-rn */ |
1850 | { 0x4063, STORE | SETS1 | USES1 | USESSP }, /* stc.l rs,@-rn */ | |
1851 | { 0x4073, STORE | SETS1 | USES1 | USESSP }, /* stc.l re,@-rn */ | |
1852 | { 0x4083, STORE | SETS1 | USES1 | USESSP }, /* stc.l r0_bank,@-rn */ | |
1853 | .. | |
1854 | { 0x40f3, STORE | SETS1 | USES1 | USESSP }, /* stc.l r7_bank,@-rn */ | |
1855 | ||
1856 | { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,sr */ | |
1857 | { 0x4017, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,gbr */ | |
1858 | { 0x4027, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,vbr */ | |
1859 | { 0x4037, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,ssr */ | |
252b5132 | 1860 | { 0x4047, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,spc */ |
d4845d57 JR |
1861 | { 0x4057, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,mod */ |
1862 | { 0x4067, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,rs */ | |
1863 | { 0x4077, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,re */ | |
1864 | { 0x4087, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,r0_bank */ | |
1865 | .. | |
1866 | { 0x40f7, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,r7_bank */ | |
1867 | ||
1868 | { 0x400e, SETSSP | USES1 }, /* ldc rm,sr */ | |
1869 | { 0x401e, SETSSP | USES1 }, /* ldc rm,gbr */ | |
1870 | { 0x402e, SETSSP | USES1 }, /* ldc rm,vbr */ | |
1871 | { 0x403e, SETSSP | USES1 }, /* ldc rm,ssr */ | |
252b5132 | 1872 | { 0x404e, SETSSP | USES1 }, /* ldc rm,spc */ |
d4845d57 JR |
1873 | { 0x405e, SETSSP | USES1 }, /* ldc rm,mod */ |
1874 | { 0x406e, SETSSP | USES1 }, /* ldc rm,rs */ | |
1875 | { 0x407e, SETSSP | USES1 } /* ldc rm,re */ | |
1876 | { 0x408e, SETSSP | USES1 } /* ldc rm,r0_bank */ | |
1877 | .. | |
1878 | { 0x40fe, SETSSP | USES1 } /* ldc rm,r7_bank */ | |
1879 | #endif | |
252b5132 RH |
1880 | }; |
1881 | ||
1882 | static const struct sh_opcode sh_opcode41[] = | |
1883 | { | |
d4845d57 JR |
1884 | { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l <special_reg>,@-rn */ |
1885 | { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,<special_reg> */ | |
1886 | { 0x400c, SETS1 | USES1 | USES2 }, /* shad rm,rn */ | |
1887 | { 0x400d, SETS1 | USES1 | USES2 }, /* shld rm,rn */ | |
1888 | { 0x400e, SETSSP | USES1 }, /* ldc rm,<special_reg> */ | |
252b5132 RH |
1889 | { 0x400f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.w @rm+,@rn+ */ |
1890 | }; | |
1891 | ||
1892 | static const struct sh_minor_opcode sh_opcode4[] = | |
1893 | { | |
1894 | { MAP (sh_opcode40), 0xf0ff }, | |
d4845d57 | 1895 | { MAP (sh_opcode41), 0xf00f } |
252b5132 RH |
1896 | }; |
1897 | ||
1898 | static const struct sh_opcode sh_opcode50[] = | |
1899 | { | |
1900 | { 0x5000, LOAD | SETS1 | USES2 } /* mov.l @(disp,rm),rn */ | |
1901 | }; | |
1902 | ||
1903 | static const struct sh_minor_opcode sh_opcode5[] = | |
1904 | { | |
1905 | { MAP (sh_opcode50), 0xf000 } | |
1906 | }; | |
1907 | ||
1908 | static const struct sh_opcode sh_opcode60[] = | |
1909 | { | |
1910 | { 0x6000, LOAD | SETS1 | USES2 }, /* mov.b @rm,rn */ | |
1911 | { 0x6001, LOAD | SETS1 | USES2 }, /* mov.w @rm,rn */ | |
1912 | { 0x6002, LOAD | SETS1 | USES2 }, /* mov.l @rm,rn */ | |
1913 | { 0x6003, SETS1 | USES2 }, /* mov rm,rn */ | |
1914 | { 0x6004, LOAD | SETS1 | SETS2 | USES2 }, /* mov.b @rm+,rn */ | |
1915 | { 0x6005, LOAD | SETS1 | SETS2 | USES2 }, /* mov.w @rm+,rn */ | |
1916 | { 0x6006, LOAD | SETS1 | SETS2 | USES2 }, /* mov.l @rm+,rn */ | |
1917 | { 0x6007, SETS1 | USES2 }, /* not rm,rn */ | |
1918 | { 0x6008, SETS1 | USES2 }, /* swap.b rm,rn */ | |
1919 | { 0x6009, SETS1 | USES2 }, /* swap.w rm,rn */ | |
1920 | { 0x600a, SETS1 | SETSSP | USES2 | USESSP }, /* negc rm,rn */ | |
1921 | { 0x600b, SETS1 | USES2 }, /* neg rm,rn */ | |
1922 | { 0x600c, SETS1 | USES2 }, /* extu.b rm,rn */ | |
1923 | { 0x600d, SETS1 | USES2 }, /* extu.w rm,rn */ | |
1924 | { 0x600e, SETS1 | USES2 }, /* exts.b rm,rn */ | |
1925 | { 0x600f, SETS1 | USES2 } /* exts.w rm,rn */ | |
1926 | }; | |
1927 | ||
1928 | static const struct sh_minor_opcode sh_opcode6[] = | |
1929 | { | |
1930 | { MAP (sh_opcode60), 0xf00f } | |
1931 | }; | |
1932 | ||
1933 | static const struct sh_opcode sh_opcode70[] = | |
1934 | { | |
1935 | { 0x7000, SETS1 | USES1 } /* add #imm,rn */ | |
1936 | }; | |
1937 | ||
1938 | static const struct sh_minor_opcode sh_opcode7[] = | |
1939 | { | |
1940 | { MAP (sh_opcode70), 0xf000 } | |
1941 | }; | |
1942 | ||
1943 | static const struct sh_opcode sh_opcode80[] = | |
1944 | { | |
1945 | { 0x8000, STORE | USES2 | USESR0 }, /* mov.b r0,@(disp,rn) */ | |
1946 | { 0x8100, STORE | USES2 | USESR0 }, /* mov.w r0,@(disp,rn) */ | |
d4845d57 | 1947 | { 0x8200, SETSSP }, /* setrc #imm */ |
252b5132 RH |
1948 | { 0x8400, LOAD | SETSR0 | USES2 }, /* mov.b @(disp,rm),r0 */ |
1949 | { 0x8500, LOAD | SETSR0 | USES2 }, /* mov.w @(disp,rn),r0 */ | |
1950 | { 0x8800, SETSSP | USESR0 }, /* cmp/eq #imm,r0 */ | |
1951 | { 0x8900, BRANCH | USESSP }, /* bt label */ | |
1952 | { 0x8b00, BRANCH | USESSP }, /* bf label */ | |
d4845d57 | 1953 | { 0x8c00, SETSSP }, /* ldrs @(disp,pc) */ |
252b5132 | 1954 | { 0x8d00, BRANCH | DELAY | USESSP }, /* bt/s label */ |
d4845d57 | 1955 | { 0x8e00, SETSSP }, /* ldre @(disp,pc) */ |
252b5132 RH |
1956 | { 0x8f00, BRANCH | DELAY | USESSP } /* bf/s label */ |
1957 | }; | |
1958 | ||
1959 | static const struct sh_minor_opcode sh_opcode8[] = | |
1960 | { | |
1961 | { MAP (sh_opcode80), 0xff00 } | |
1962 | }; | |
1963 | ||
1964 | static const struct sh_opcode sh_opcode90[] = | |
1965 | { | |
1966 | { 0x9000, LOAD | SETS1 } /* mov.w @(disp,pc),rn */ | |
1967 | }; | |
1968 | ||
1969 | static const struct sh_minor_opcode sh_opcode9[] = | |
1970 | { | |
1971 | { MAP (sh_opcode90), 0xf000 } | |
1972 | }; | |
1973 | ||
1974 | static const struct sh_opcode sh_opcodea0[] = | |
1975 | { | |
1976 | { 0xa000, BRANCH | DELAY } /* bra label */ | |
1977 | }; | |
1978 | ||
1979 | static const struct sh_minor_opcode sh_opcodea[] = | |
1980 | { | |
1981 | { MAP (sh_opcodea0), 0xf000 } | |
1982 | }; | |
1983 | ||
1984 | static const struct sh_opcode sh_opcodeb0[] = | |
1985 | { | |
1986 | { 0xb000, BRANCH | DELAY } /* bsr label */ | |
1987 | }; | |
1988 | ||
1989 | static const struct sh_minor_opcode sh_opcodeb[] = | |
1990 | { | |
1991 | { MAP (sh_opcodeb0), 0xf000 } | |
1992 | }; | |
1993 | ||
1994 | static const struct sh_opcode sh_opcodec0[] = | |
1995 | { | |
1996 | { 0xc000, STORE | USESR0 | USESSP }, /* mov.b r0,@(disp,gbr) */ | |
1997 | { 0xc100, STORE | USESR0 | USESSP }, /* mov.w r0,@(disp,gbr) */ | |
1998 | { 0xc200, STORE | USESR0 | USESSP }, /* mov.l r0,@(disp,gbr) */ | |
1999 | { 0xc300, BRANCH | USESSP }, /* trapa #imm */ | |
2000 | { 0xc400, LOAD | SETSR0 | USESSP }, /* mov.b @(disp,gbr),r0 */ | |
2001 | { 0xc500, LOAD | SETSR0 | USESSP }, /* mov.w @(disp,gbr),r0 */ | |
2002 | { 0xc600, LOAD | SETSR0 | USESSP }, /* mov.l @(disp,gbr),r0 */ | |
2003 | { 0xc700, SETSR0 }, /* mova @(disp,pc),r0 */ | |
2004 | { 0xc800, SETSSP | USESR0 }, /* tst #imm,r0 */ | |
2005 | { 0xc900, SETSR0 | USESR0 }, /* and #imm,r0 */ | |
2006 | { 0xca00, SETSR0 | USESR0 }, /* xor #imm,r0 */ | |
2007 | { 0xcb00, SETSR0 | USESR0 }, /* or #imm,r0 */ | |
2008 | { 0xcc00, LOAD | SETSSP | USESR0 | USESSP }, /* tst.b #imm,@(r0,gbr) */ | |
2009 | { 0xcd00, LOAD | STORE | USESR0 | USESSP }, /* and.b #imm,@(r0,gbr) */ | |
2010 | { 0xce00, LOAD | STORE | USESR0 | USESSP }, /* xor.b #imm,@(r0,gbr) */ | |
2011 | { 0xcf00, LOAD | STORE | USESR0 | USESSP } /* or.b #imm,@(r0,gbr) */ | |
2012 | }; | |
2013 | ||
2014 | static const struct sh_minor_opcode sh_opcodec[] = | |
2015 | { | |
2016 | { MAP (sh_opcodec0), 0xff00 } | |
2017 | }; | |
2018 | ||
2019 | static const struct sh_opcode sh_opcoded0[] = | |
2020 | { | |
2021 | { 0xd000, LOAD | SETS1 } /* mov.l @(disp,pc),rn */ | |
2022 | }; | |
2023 | ||
2024 | static const struct sh_minor_opcode sh_opcoded[] = | |
2025 | { | |
2026 | { MAP (sh_opcoded0), 0xf000 } | |
2027 | }; | |
2028 | ||
2029 | static const struct sh_opcode sh_opcodee0[] = | |
2030 | { | |
2031 | { 0xe000, SETS1 } /* mov #imm,rn */ | |
2032 | }; | |
2033 | ||
2034 | static const struct sh_minor_opcode sh_opcodee[] = | |
2035 | { | |
2036 | { MAP (sh_opcodee0), 0xf000 } | |
2037 | }; | |
2038 | ||
2039 | static const struct sh_opcode sh_opcodef0[] = | |
2040 | { | |
2041 | { 0xf000, SETSF1 | USESF1 | USESF2 }, /* fadd fm,fn */ | |
2042 | { 0xf001, SETSF1 | USESF1 | USESF2 }, /* fsub fm,fn */ | |
2043 | { 0xf002, SETSF1 | USESF1 | USESF2 }, /* fmul fm,fn */ | |
2044 | { 0xf003, SETSF1 | USESF1 | USESF2 }, /* fdiv fm,fn */ | |
2045 | { 0xf004, SETSSP | USESF1 | USESF2 }, /* fcmp/eq fm,fn */ | |
2046 | { 0xf005, SETSSP | USESF1 | USESF2 }, /* fcmp/gt fm,fn */ | |
2047 | { 0xf006, LOAD | SETSF1 | USES2 | USESR0 }, /* fmov.s @(r0,rm),fn */ | |
2048 | { 0xf007, STORE | USES1 | USESF2 | USESR0 }, /* fmov.s fm,@(r0,rn) */ | |
2049 | { 0xf008, LOAD | SETSF1 | USES2 }, /* fmov.s @rm,fn */ | |
2050 | { 0xf009, LOAD | SETS2 | SETSF1 | USES2 }, /* fmov.s @rm+,fn */ | |
2051 | { 0xf00a, STORE | USES1 | USESF2 }, /* fmov.s fm,@rn */ | |
2052 | { 0xf00b, STORE | SETS1 | USES1 | USESF2 }, /* fmov.s fm,@-rn */ | |
2053 | { 0xf00c, SETSF1 | USESF2 }, /* fmov fm,fn */ | |
2054 | { 0xf00e, SETSF1 | USESF1 | USESF2 | USESF0 } /* fmac f0,fm,fn */ | |
2055 | }; | |
2056 | ||
2057 | static const struct sh_opcode sh_opcodef1[] = | |
2058 | { | |
2059 | { 0xf00d, SETSF1 | USESSP }, /* fsts fpul,fn */ | |
2060 | { 0xf01d, SETSSP | USESF1 }, /* flds fn,fpul */ | |
2061 | { 0xf02d, SETSF1 | USESSP }, /* float fpul,fn */ | |
2062 | { 0xf03d, SETSSP | USESF1 }, /* ftrc fn,fpul */ | |
2063 | { 0xf04d, SETSF1 | USESF1 }, /* fneg fn */ | |
2064 | { 0xf05d, SETSF1 | USESF1 }, /* fabs fn */ | |
2065 | { 0xf06d, SETSF1 | USESF1 }, /* fsqrt fn */ | |
2066 | { 0xf07d, SETSSP | USESF1 }, /* ftst/nan fn */ | |
2067 | { 0xf08d, SETSF1 }, /* fldi0 fn */ | |
2068 | { 0xf09d, SETSF1 } /* fldi1 fn */ | |
2069 | }; | |
2070 | ||
2071 | static const struct sh_minor_opcode sh_opcodef[] = | |
2072 | { | |
2073 | { MAP (sh_opcodef0), 0xf00f }, | |
2074 | { MAP (sh_opcodef1), 0xf0ff } | |
2075 | }; | |
2076 | ||
d4845d57 | 2077 | static struct sh_major_opcode sh_opcodes[] = |
252b5132 RH |
2078 | { |
2079 | { MAP (sh_opcode0) }, | |
2080 | { MAP (sh_opcode1) }, | |
2081 | { MAP (sh_opcode2) }, | |
2082 | { MAP (sh_opcode3) }, | |
2083 | { MAP (sh_opcode4) }, | |
2084 | { MAP (sh_opcode5) }, | |
2085 | { MAP (sh_opcode6) }, | |
2086 | { MAP (sh_opcode7) }, | |
2087 | { MAP (sh_opcode8) }, | |
2088 | { MAP (sh_opcode9) }, | |
2089 | { MAP (sh_opcodea) }, | |
2090 | { MAP (sh_opcodeb) }, | |
2091 | { MAP (sh_opcodec) }, | |
2092 | { MAP (sh_opcoded) }, | |
2093 | { MAP (sh_opcodee) }, | |
2094 | { MAP (sh_opcodef) } | |
2095 | }; | |
2096 | ||
d4845d57 JR |
2097 | /* The double data transfer / parallel processing insns are not |
2098 | described here. This will cause sh_align_load_span to leave them alone. */ | |
2099 | ||
2100 | static const struct sh_opcode sh_dsp_opcodef0[] = | |
2101 | { | |
2102 | { 0xf400, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @-as,ds */ | |
2103 | { 0xf401, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@-as */ | |
2104 | { 0xf404, USESAS | LOAD | SETSSP }, /* movs.x @as,ds */ | |
2105 | { 0xf405, USESAS | STORE | USESSP }, /* movs.x ds,@as */ | |
2106 | { 0xf408, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @as+,ds */ | |
2107 | { 0xf409, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@as+ */ | |
2108 | { 0xf40c, USESAS | SETSAS | LOAD | SETSSP | USESR8 }, /* movs.x @as+r8,ds */ | |
2109 | { 0xf40d, USESAS | SETSAS | STORE | USESSP | USESR8 } /* movs.x ds,@as+r8 */ | |
2110 | }; | |
2111 | ||
2112 | static const struct sh_minor_opcode sh_dsp_opcodef[] = | |
2113 | { | |
2114 | { MAP (sh_dsp_opcodef0), 0xfc0d } | |
2115 | }; | |
2116 | ||
86033394 | 2117 | #ifndef COFF_IMAGE_WITH_PE |
252b5132 RH |
2118 | /* Given an instruction, return a pointer to the corresponding |
2119 | sh_opcode structure. Return NULL if the instruction is not | |
2120 | recognized. */ | |
2121 | ||
2122 | static const struct sh_opcode * | |
2123 | sh_insn_info (insn) | |
2124 | unsigned int insn; | |
2125 | { | |
2126 | const struct sh_major_opcode *maj; | |
2127 | const struct sh_minor_opcode *min, *minend; | |
2128 | ||
2129 | maj = &sh_opcodes[(insn & 0xf000) >> 12]; | |
2130 | min = maj->minor_opcodes; | |
2131 | minend = min + maj->count; | |
2132 | for (; min < minend; min++) | |
2133 | { | |
2134 | unsigned int l; | |
2135 | const struct sh_opcode *op, *opend; | |
2136 | ||
2137 | l = insn & min->mask; | |
2138 | op = min->opcodes; | |
2139 | opend = op + min->count; | |
2140 | ||
2141 | /* Since the opcodes tables are sorted, we could use a binary | |
2142 | search here if the count were above some cutoff value. */ | |
2143 | for (; op < opend; op++) | |
2144 | if (op->opcode == l) | |
2145 | return op; | |
2146 | } | |
2147 | ||
cbfe05c4 | 2148 | return NULL; |
252b5132 RH |
2149 | } |
2150 | ||
84dcfba7 JR |
2151 | /* See whether an instruction uses or sets a general purpose register */ |
2152 | ||
2153 | static boolean | |
2154 | sh_insn_uses_or_sets_reg (insn, op, reg) | |
2155 | unsigned int insn; | |
2156 | const struct sh_opcode *op; | |
2157 | unsigned int reg; | |
2158 | { | |
2159 | if (sh_insn_uses_reg (insn, op, reg)) | |
2160 | return true; | |
2161 | ||
2162 | return sh_insn_sets_reg (insn, op, reg); | |
2163 | } | |
2164 | ||
252b5132 RH |
2165 | /* See whether an instruction uses a general purpose register. */ |
2166 | ||
2167 | static boolean | |
2168 | sh_insn_uses_reg (insn, op, reg) | |
2169 | unsigned int insn; | |
2170 | const struct sh_opcode *op; | |
2171 | unsigned int reg; | |
2172 | { | |
2173 | unsigned int f; | |
2174 | ||
2175 | f = op->flags; | |
2176 | ||
2177 | if ((f & USES1) != 0 | |
84dcfba7 | 2178 | && USES1_REG (insn) == reg) |
252b5132 RH |
2179 | return true; |
2180 | if ((f & USES2) != 0 | |
84dcfba7 | 2181 | && USES2_REG (insn) == reg) |
252b5132 RH |
2182 | return true; |
2183 | if ((f & USESR0) != 0 | |
2184 | && reg == 0) | |
2185 | return true; | |
d4845d57 JR |
2186 | if ((f & USESAS) && reg == USESAS_REG (insn)) |
2187 | return true; | |
2188 | if ((f & USESR8) && reg == 8) | |
2189 | return true; | |
252b5132 RH |
2190 | |
2191 | return false; | |
2192 | } | |
17505c5c | 2193 | |
84dcfba7 JR |
2194 | /* See whether an instruction sets a general purpose register. */ |
2195 | ||
2196 | static boolean | |
2197 | sh_insn_sets_reg (insn, op, reg) | |
2198 | unsigned int insn; | |
2199 | const struct sh_opcode *op; | |
2200 | unsigned int reg; | |
2201 | { | |
2202 | unsigned int f; | |
2203 | ||
2204 | f = op->flags; | |
2205 | ||
2206 | if ((f & SETS1) != 0 | |
2207 | && SETS1_REG (insn) == reg) | |
2208 | return true; | |
2209 | if ((f & SETS2) != 0 | |
2210 | && SETS2_REG (insn) == reg) | |
2211 | return true; | |
2212 | if ((f & SETSR0) != 0 | |
2213 | && reg == 0) | |
2214 | return true; | |
d4845d57 JR |
2215 | if ((f & SETSAS) && reg == SETSAS_REG (insn)) |
2216 | return true; | |
84dcfba7 JR |
2217 | |
2218 | return false; | |
2219 | } | |
2220 | ||
2221 | /* See whether an instruction uses or sets a floating point register */ | |
2222 | ||
2223 | static boolean | |
2224 | sh_insn_uses_or_sets_freg (insn, op, reg) | |
2225 | unsigned int insn; | |
2226 | const struct sh_opcode *op; | |
2227 | unsigned int reg; | |
2228 | { | |
2229 | if (sh_insn_uses_freg (insn, op, reg)) | |
2230 | return true; | |
2231 | ||
2232 | return sh_insn_sets_freg (insn, op, reg); | |
2233 | } | |
252b5132 RH |
2234 | |
2235 | /* See whether an instruction uses a floating point register. */ | |
2236 | ||
2237 | static boolean | |
2238 | sh_insn_uses_freg (insn, op, freg) | |
2239 | unsigned int insn; | |
2240 | const struct sh_opcode *op; | |
2241 | unsigned int freg; | |
2242 | { | |
2243 | unsigned int f; | |
2244 | ||
2245 | f = op->flags; | |
2246 | ||
2247 | /* We can't tell if this is a double-precision insn, so just play safe | |
2248 | and assume that it might be. So not only have we test FREG against | |
2249 | itself, but also even FREG against FREG+1 - if the using insn uses | |
2250 | just the low part of a double precision value - but also an odd | |
2251 | FREG against FREG-1 - if the setting insn sets just the low part | |
2252 | of a double precision value. | |
2253 | So what this all boils down to is that we have to ignore the lowest | |
2254 | bit of the register number. */ | |
cbfe05c4 | 2255 | |
252b5132 | 2256 | if ((f & USESF1) != 0 |
84dcfba7 | 2257 | && (USESF1_REG (insn) & 0xe) == (freg & 0xe)) |
252b5132 RH |
2258 | return true; |
2259 | if ((f & USESF2) != 0 | |
84dcfba7 | 2260 | && (USESF2_REG (insn) & 0xe) == (freg & 0xe)) |
252b5132 RH |
2261 | return true; |
2262 | if ((f & USESF0) != 0 | |
2263 | && freg == 0) | |
2264 | return true; | |
2265 | ||
2266 | return false; | |
2267 | } | |
2268 | ||
84dcfba7 JR |
2269 | /* See whether an instruction sets a floating point register. */ |
2270 | ||
2271 | static boolean | |
2272 | sh_insn_sets_freg (insn, op, freg) | |
2273 | unsigned int insn; | |
2274 | const struct sh_opcode *op; | |
2275 | unsigned int freg; | |
2276 | { | |
2277 | unsigned int f; | |
2278 | ||
2279 | f = op->flags; | |
2280 | ||
2281 | /* We can't tell if this is a double-precision insn, so just play safe | |
2282 | and assume that it might be. So not only have we test FREG against | |
2283 | itself, but also even FREG against FREG+1 - if the using insn uses | |
2284 | just the low part of a double precision value - but also an odd | |
2285 | FREG against FREG-1 - if the setting insn sets just the low part | |
2286 | of a double precision value. | |
2287 | So what this all boils down to is that we have to ignore the lowest | |
2288 | bit of the register number. */ | |
cbfe05c4 | 2289 | |
84dcfba7 JR |
2290 | if ((f & SETSF1) != 0 |
2291 | && (SETSF1_REG (insn) & 0xe) == (freg & 0xe)) | |
2292 | return true; | |
2293 | ||
2294 | return false; | |
2295 | } | |
2296 | ||
252b5132 RH |
2297 | /* See whether instructions I1 and I2 conflict, assuming I1 comes |
2298 | before I2. OP1 and OP2 are the corresponding sh_opcode structures. | |
2299 | This should return true if there is a conflict, or false if the | |
2300 | instructions can be swapped safely. */ | |
2301 | ||
2302 | static boolean | |
2303 | sh_insns_conflict (i1, op1, i2, op2) | |
2304 | unsigned int i1; | |
2305 | const struct sh_opcode *op1; | |
2306 | unsigned int i2; | |
2307 | const struct sh_opcode *op2; | |
2308 | { | |
2309 | unsigned int f1, f2; | |
2310 | ||
2311 | f1 = op1->flags; | |
2312 | f2 = op2->flags; | |
2313 | ||
2314 | /* Load of fpscr conflicts with floating point operations. | |
2315 | FIXME: shouldn't test raw opcodes here. */ | |
2316 | if (((i1 & 0xf0ff) == 0x4066 && (i2 & 0xf000) == 0xf000) | |
2317 | || ((i2 & 0xf0ff) == 0x4066 && (i1 & 0xf000) == 0xf000)) | |
2318 | return true; | |
2319 | ||
2320 | if ((f1 & (BRANCH | DELAY)) != 0 | |
2321 | || (f2 & (BRANCH | DELAY)) != 0) | |
2322 | return true; | |
2323 | ||
84dcfba7 JR |
2324 | if (((f1 | f2) & SETSSP) |
2325 | && (f1 & (SETSSP | USESSP)) | |
2326 | && (f2 & (SETSSP | USESSP))) | |
252b5132 RH |
2327 | return true; |
2328 | ||
2329 | if ((f1 & SETS1) != 0 | |
84dcfba7 | 2330 | && sh_insn_uses_or_sets_reg (i2, op2, SETS1_REG (i1))) |
252b5132 RH |
2331 | return true; |
2332 | if ((f1 & SETS2) != 0 | |
84dcfba7 | 2333 | && sh_insn_uses_or_sets_reg (i2, op2, SETS2_REG (i1))) |
252b5132 RH |
2334 | return true; |
2335 | if ((f1 & SETSR0) != 0 | |
84dcfba7 | 2336 | && sh_insn_uses_or_sets_reg (i2, op2, 0)) |
252b5132 | 2337 | return true; |
d4845d57 JR |
2338 | if ((f1 & SETSAS) |
2339 | && sh_insn_uses_or_sets_reg (i2, op2, SETSAS_REG (i1))) | |
2340 | return true; | |
252b5132 | 2341 | if ((f1 & SETSF1) != 0 |
84dcfba7 | 2342 | && sh_insn_uses_or_sets_freg (i2, op2, SETSF1_REG (i1))) |
252b5132 RH |
2343 | return true; |
2344 | ||
2345 | if ((f2 & SETS1) != 0 | |
84dcfba7 | 2346 | && sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2))) |
252b5132 RH |
2347 | return true; |
2348 | if ((f2 & SETS2) != 0 | |
84dcfba7 | 2349 | && sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2))) |
252b5132 RH |
2350 | return true; |
2351 | if ((f2 & SETSR0) != 0 | |
84dcfba7 | 2352 | && sh_insn_uses_or_sets_reg (i1, op1, 0)) |
252b5132 | 2353 | return true; |
d4845d57 JR |
2354 | if ((f2 & SETSAS) |
2355 | && sh_insn_uses_or_sets_reg (i1, op1, SETSAS_REG (i2))) | |
2356 | return true; | |
252b5132 | 2357 | if ((f2 & SETSF1) != 0 |
84dcfba7 | 2358 | && sh_insn_uses_or_sets_freg (i1, op1, SETSF1_REG (i2))) |
252b5132 RH |
2359 | return true; |
2360 | ||
2361 | /* The instructions do not conflict. */ | |
2362 | return false; | |
2363 | } | |
2364 | ||
2365 | /* I1 is a load instruction, and I2 is some other instruction. Return | |
2366 | true if I1 loads a register which I2 uses. */ | |
2367 | ||
2368 | static boolean | |
2369 | sh_load_use (i1, op1, i2, op2) | |
2370 | unsigned int i1; | |
2371 | const struct sh_opcode *op1; | |
2372 | unsigned int i2; | |
2373 | const struct sh_opcode *op2; | |
2374 | { | |
2375 | unsigned int f1; | |
2376 | ||
2377 | f1 = op1->flags; | |
2378 | ||
2379 | if ((f1 & LOAD) == 0) | |
2380 | return false; | |
2381 | ||
2382 | /* If both SETS1 and SETSSP are set, that means a load to a special | |
2383 | register using postincrement addressing mode, which we don't care | |
2384 | about here. */ | |
2385 | if ((f1 & SETS1) != 0 | |
2386 | && (f1 & SETSSP) == 0 | |
2387 | && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8)) | |
2388 | return true; | |
2389 | ||
2390 | if ((f1 & SETSR0) != 0 | |
2391 | && sh_insn_uses_reg (i2, op2, 0)) | |
2392 | return true; | |
2393 | ||
2394 | if ((f1 & SETSF1) != 0 | |
2395 | && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8)) | |
2396 | return true; | |
2397 | ||
2398 | return false; | |
2399 | } | |
2400 | ||
2401 | /* Try to align loads and stores within a span of memory. This is | |
2402 | called by both the ELF and the COFF sh targets. ABFD and SEC are | |
2403 | the BFD and section we are examining. CONTENTS is the contents of | |
2404 | the section. SWAP is the routine to call to swap two instructions. | |
2405 | RELOCS is a pointer to the internal relocation information, to be | |
2406 | passed to SWAP. PLABEL is a pointer to the current label in a | |
2407 | sorted list of labels; LABEL_END is the end of the list. START and | |
2408 | STOP are the range of memory to examine. If a swap is made, | |
2409 | *PSWAPPED is set to true. */ | |
2410 | ||
86033394 NC |
2411 | #ifdef COFF_WITH_PE |
2412 | static | |
2413 | #endif | |
252b5132 RH |
2414 | boolean |
2415 | _bfd_sh_align_load_span (abfd, sec, contents, swap, relocs, | |
2416 | plabel, label_end, start, stop, pswapped) | |
2417 | bfd *abfd; | |
2418 | asection *sec; | |
2419 | bfd_byte *contents; | |
2420 | boolean (*swap) PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma)); | |
2421 | PTR relocs; | |
2422 | bfd_vma **plabel; | |
2423 | bfd_vma *label_end; | |
2424 | bfd_vma start; | |
2425 | bfd_vma stop; | |
2426 | boolean *pswapped; | |
2427 | { | |
d4845d57 JR |
2428 | int dsp = (abfd->arch_info->mach == bfd_mach_sh_dsp |
2429 | || abfd->arch_info->mach == bfd_mach_sh3_dsp); | |
252b5132 RH |
2430 | bfd_vma i; |
2431 | ||
d4845d57 JR |
2432 | /* The SH4 has a Harvard architecture, hence aligning loads is not |
2433 | desirable. In fact, it is counter-productive, since it interferes | |
2434 | with the schedules generated by the compiler. */ | |
2435 | if (abfd->arch_info->mach == bfd_mach_sh4) | |
2436 | return true; | |
2437 | ||
2438 | /* If we are linking sh[3]-dsp code, swap the FPU instructions for DSP | |
2439 | instructions. */ | |
2440 | if (dsp) | |
2441 | { | |
2442 | sh_opcodes[0xf].minor_opcodes = sh_dsp_opcodef; | |
2443 | sh_opcodes[0xf].count = sizeof sh_dsp_opcodef / sizeof sh_dsp_opcodef; | |
2444 | } | |
2445 | ||
252b5132 RH |
2446 | /* Instructions should be aligned on 2 byte boundaries. */ |
2447 | if ((start & 1) == 1) | |
2448 | ++start; | |
2449 | ||
2450 | /* Now look through the unaligned addresses. */ | |
2451 | i = start; | |
2452 | if ((i & 2) == 0) | |
2453 | i += 2; | |
2454 | for (; i < stop; i += 4) | |
2455 | { | |
2456 | unsigned int insn; | |
2457 | const struct sh_opcode *op; | |
2458 | unsigned int prev_insn = 0; | |
2459 | const struct sh_opcode *prev_op = NULL; | |
2460 | ||
2461 | insn = bfd_get_16 (abfd, contents + i); | |
2462 | op = sh_insn_info (insn); | |
2463 | if (op == NULL | |
2464 | || (op->flags & (LOAD | STORE)) == 0) | |
2465 | continue; | |
2466 | ||
2467 | /* This is a load or store which is not on a four byte boundary. */ | |
2468 | ||
2469 | while (*plabel < label_end && **plabel < i) | |
2470 | ++*plabel; | |
2471 | ||
2472 | if (i > start) | |
2473 | { | |
2474 | prev_insn = bfd_get_16 (abfd, contents + i - 2); | |
d4845d57 JR |
2475 | /* If INSN is the field b of a parallel processing insn, it is not |
2476 | a load / store after all. Note that the test here might mistake | |
2477 | the field_b of a pcopy insn for the starting code of a parallel | |
2478 | processing insn; this might miss a swapping opportunity, but at | |
2479 | least we're on the safe side. */ | |
2480 | if (dsp && (prev_insn & 0xfc00) == 0xf800) | |
2481 | continue; | |
2482 | ||
2483 | /* Check if prev_insn is actually the field b of a parallel | |
2484 | processing insn. Again, this can give a spurious match | |
2485 | after a pcopy. */ | |
2486 | if (dsp && i - 2 > start) | |
2487 | { | |
2488 | unsigned pprev_insn = bfd_get_16 (abfd, contents + i - 4); | |
cbfe05c4 | 2489 | |
d4845d57 JR |
2490 | if ((pprev_insn & 0xfc00) == 0xf800) |
2491 | prev_op = NULL; | |
2492 | else | |
2493 | prev_op = sh_insn_info (prev_insn); | |
2494 | } | |
2495 | else | |
2496 | prev_op = sh_insn_info (prev_insn); | |
252b5132 RH |
2497 | |
2498 | /* If the load/store instruction is in a delay slot, we | |
2499 | can't swap. */ | |
2500 | if (prev_op == NULL | |
2501 | || (prev_op->flags & DELAY) != 0) | |
2502 | continue; | |
2503 | } | |
2504 | if (i > start | |
2505 | && (*plabel >= label_end || **plabel != i) | |
2506 | && prev_op != NULL | |
2507 | && (prev_op->flags & (LOAD | STORE)) == 0 | |
2508 | && ! sh_insns_conflict (prev_insn, prev_op, insn, op)) | |
2509 | { | |
2510 | boolean ok; | |
2511 | ||
2512 | /* The load/store instruction does not have a label, and | |
2513 | there is a previous instruction; PREV_INSN is not | |
2514 | itself a load/store instruction, and PREV_INSN and | |
2515 | INSN do not conflict. */ | |
2516 | ||
2517 | ok = true; | |
2518 | ||
2519 | if (i >= start + 4) | |
2520 | { | |
2521 | unsigned int prev2_insn; | |
2522 | const struct sh_opcode *prev2_op; | |
2523 | ||
2524 | prev2_insn = bfd_get_16 (abfd, contents + i - 4); | |
2525 | prev2_op = sh_insn_info (prev2_insn); | |
2526 | ||
2527 | /* If the instruction before PREV_INSN has a delay | |
2528 | slot--that is, PREV_INSN is in a delay slot--we | |
2529 | can not swap. */ | |
2530 | if (prev2_op == NULL | |
2531 | || (prev2_op->flags & DELAY) != 0) | |
2532 | ok = false; | |
2533 | ||
2534 | /* If the instruction before PREV_INSN is a load, | |
2535 | and it sets a register which INSN uses, then | |
2536 | putting INSN immediately after PREV_INSN will | |
2537 | cause a pipeline bubble, so there is no point to | |
2538 | making the swap. */ | |
2539 | if (ok | |
2540 | && (prev2_op->flags & LOAD) != 0 | |
2541 | && sh_load_use (prev2_insn, prev2_op, insn, op)) | |
2542 | ok = false; | |
2543 | } | |
2544 | ||
2545 | if (ok) | |
2546 | { | |
2547 | if (! (*swap) (abfd, sec, relocs, contents, i - 2)) | |
2548 | return false; | |
2549 | *pswapped = true; | |
2550 | continue; | |
2551 | } | |
2552 | } | |
2553 | ||
2554 | while (*plabel < label_end && **plabel < i + 2) | |
2555 | ++*plabel; | |
2556 | ||
2557 | if (i + 2 < stop | |
2558 | && (*plabel >= label_end || **plabel != i + 2)) | |
2559 | { | |
2560 | unsigned int next_insn; | |
2561 | const struct sh_opcode *next_op; | |
2562 | ||
2563 | /* There is an instruction after the load/store | |
2564 | instruction, and it does not have a label. */ | |
2565 | next_insn = bfd_get_16 (abfd, contents + i + 2); | |
2566 | next_op = sh_insn_info (next_insn); | |
2567 | if (next_op != NULL | |
2568 | && (next_op->flags & (LOAD | STORE)) == 0 | |
2569 | && ! sh_insns_conflict (insn, op, next_insn, next_op)) | |
2570 | { | |
2571 | boolean ok; | |
2572 | ||
2573 | /* NEXT_INSN is not itself a load/store instruction, | |
2574 | and it does not conflict with INSN. */ | |
2575 | ||
2576 | ok = true; | |
2577 | ||
2578 | /* If PREV_INSN is a load, and it sets a register | |
2579 | which NEXT_INSN uses, then putting NEXT_INSN | |
2580 | immediately after PREV_INSN will cause a pipeline | |
2581 | bubble, so there is no reason to make this swap. */ | |
2582 | if (prev_op != NULL | |
2583 | && (prev_op->flags & LOAD) != 0 | |
2584 | && sh_load_use (prev_insn, prev_op, next_insn, next_op)) | |
2585 | ok = false; | |
2586 | ||
2587 | /* If INSN is a load, and it sets a register which | |
2588 | the insn after NEXT_INSN uses, then doing the | |
2589 | swap will cause a pipeline bubble, so there is no | |
2590 | reason to make the swap. However, if the insn | |
2591 | after NEXT_INSN is itself a load or store | |
2592 | instruction, then it is misaligned, so | |
2593 | optimistically hope that it will be swapped | |
2594 | itself, and just live with the pipeline bubble if | |
2595 | it isn't. */ | |
2596 | if (ok | |
2597 | && i + 4 < stop | |
2598 | && (op->flags & LOAD) != 0) | |
2599 | { | |
2600 | unsigned int next2_insn; | |
2601 | const struct sh_opcode *next2_op; | |
2602 | ||
2603 | next2_insn = bfd_get_16 (abfd, contents + i + 4); | |
2604 | next2_op = sh_insn_info (next2_insn); | |
2605 | if ((next2_op->flags & (LOAD | STORE)) == 0 | |
2606 | && sh_load_use (insn, op, next2_insn, next2_op)) | |
2607 | ok = false; | |
2608 | } | |
2609 | ||
2610 | if (ok) | |
2611 | { | |
2612 | if (! (*swap) (abfd, sec, relocs, contents, i)) | |
2613 | return false; | |
2614 | *pswapped = true; | |
2615 | continue; | |
2616 | } | |
2617 | } | |
2618 | } | |
2619 | } | |
2620 | ||
2621 | return true; | |
2622 | } | |
86033394 | 2623 | #endif /* not COFF_IMAGE_WITH_PE */ |
252b5132 RH |
2624 | |
2625 | /* Look for loads and stores which we can align to four byte | |
2626 | boundaries. See the longer comment above sh_relax_section for why | |
2627 | this is desirable. This sets *PSWAPPED if some instruction was | |
2628 | swapped. */ | |
2629 | ||
2630 | static boolean | |
2631 | sh_align_loads (abfd, sec, internal_relocs, contents, pswapped) | |
2632 | bfd *abfd; | |
2633 | asection *sec; | |
2634 | struct internal_reloc *internal_relocs; | |
2635 | bfd_byte *contents; | |
2636 | boolean *pswapped; | |
2637 | { | |
2638 | struct internal_reloc *irel, *irelend; | |
2639 | bfd_vma *labels = NULL; | |
2640 | bfd_vma *label, *label_end; | |
2641 | ||
2642 | *pswapped = false; | |
2643 | ||
2644 | irelend = internal_relocs + sec->reloc_count; | |
2645 | ||
2646 | /* Get all the addresses with labels on them. */ | |
2647 | labels = (bfd_vma *) bfd_malloc (sec->reloc_count * sizeof (bfd_vma)); | |
2648 | if (labels == NULL) | |
2649 | goto error_return; | |
2650 | label_end = labels; | |
2651 | for (irel = internal_relocs; irel < irelend; irel++) | |
2652 | { | |
2653 | if (irel->r_type == R_SH_LABEL) | |
2654 | { | |
2655 | *label_end = irel->r_vaddr - sec->vma; | |
2656 | ++label_end; | |
2657 | } | |
2658 | } | |
2659 | ||
2660 | /* Note that the assembler currently always outputs relocs in | |
2661 | address order. If that ever changes, this code will need to sort | |
2662 | the label values and the relocs. */ | |
2663 | ||
2664 | label = labels; | |
2665 | ||
2666 | for (irel = internal_relocs; irel < irelend; irel++) | |
2667 | { | |
2668 | bfd_vma start, stop; | |
2669 | ||
2670 | if (irel->r_type != R_SH_CODE) | |
2671 | continue; | |
2672 | ||
2673 | start = irel->r_vaddr - sec->vma; | |
2674 | ||
2675 | for (irel++; irel < irelend; irel++) | |
2676 | if (irel->r_type == R_SH_DATA) | |
2677 | break; | |
2678 | if (irel < irelend) | |
2679 | stop = irel->r_vaddr - sec->vma; | |
2680 | else | |
2681 | stop = sec->_cooked_size; | |
2682 | ||
2683 | if (! _bfd_sh_align_load_span (abfd, sec, contents, sh_swap_insns, | |
2684 | (PTR) internal_relocs, &label, | |
2685 | label_end, start, stop, pswapped)) | |
2686 | goto error_return; | |
2687 | } | |
2688 | ||
2689 | free (labels); | |
2690 | ||
2691 | return true; | |
2692 | ||
2693 | error_return: | |
2694 | if (labels != NULL) | |
2695 | free (labels); | |
2696 | return false; | |
2697 | } | |
2698 | ||
2699 | /* Swap two SH instructions. */ | |
2700 | ||
2701 | static boolean | |
2702 | sh_swap_insns (abfd, sec, relocs, contents, addr) | |
2703 | bfd *abfd; | |
2704 | asection *sec; | |
2705 | PTR relocs; | |
2706 | bfd_byte *contents; | |
2707 | bfd_vma addr; | |
2708 | { | |
2709 | struct internal_reloc *internal_relocs = (struct internal_reloc *) relocs; | |
2710 | unsigned short i1, i2; | |
2711 | struct internal_reloc *irel, *irelend; | |
2712 | ||
2713 | /* Swap the instructions themselves. */ | |
2714 | i1 = bfd_get_16 (abfd, contents + addr); | |
2715 | i2 = bfd_get_16 (abfd, contents + addr + 2); | |
2716 | bfd_put_16 (abfd, i2, contents + addr); | |
2717 | bfd_put_16 (abfd, i1, contents + addr + 2); | |
2718 | ||
2719 | /* Adjust all reloc addresses. */ | |
2720 | irelend = internal_relocs + sec->reloc_count; | |
2721 | for (irel = internal_relocs; irel < irelend; irel++) | |
2722 | { | |
2723 | int type, add; | |
2724 | ||
2725 | /* There are a few special types of relocs that we don't want to | |
2726 | adjust. These relocs do not apply to the instruction itself, | |
2727 | but are only associated with the address. */ | |
2728 | type = irel->r_type; | |
2729 | if (type == R_SH_ALIGN | |
2730 | || type == R_SH_CODE | |
2731 | || type == R_SH_DATA | |
2732 | || type == R_SH_LABEL) | |
2733 | continue; | |
2734 | ||
2735 | /* If an R_SH_USES reloc points to one of the addresses being | |
2736 | swapped, we must adjust it. It would be incorrect to do this | |
2737 | for a jump, though, since we want to execute both | |
2738 | instructions after the jump. (We have avoided swapping | |
2739 | around a label, so the jump will not wind up executing an | |
2740 | instruction it shouldn't). */ | |
2741 | if (type == R_SH_USES) | |
2742 | { | |
2743 | bfd_vma off; | |
2744 | ||
2745 | off = irel->r_vaddr - sec->vma + 4 + irel->r_offset; | |
2746 | if (off == addr) | |
2747 | irel->r_offset += 2; | |
2748 | else if (off == addr + 2) | |
2749 | irel->r_offset -= 2; | |
2750 | } | |
2751 | ||
2752 | if (irel->r_vaddr - sec->vma == addr) | |
2753 | { | |
2754 | irel->r_vaddr += 2; | |
2755 | add = -2; | |
2756 | } | |
2757 | else if (irel->r_vaddr - sec->vma == addr + 2) | |
2758 | { | |
2759 | irel->r_vaddr -= 2; | |
2760 | add = 2; | |
2761 | } | |
2762 | else | |
2763 | add = 0; | |
2764 | ||
2765 | if (add != 0) | |
2766 | { | |
2767 | bfd_byte *loc; | |
2768 | unsigned short insn, oinsn; | |
2769 | boolean overflow; | |
2770 | ||
2771 | loc = contents + irel->r_vaddr - sec->vma; | |
2772 | overflow = false; | |
2773 | switch (type) | |
2774 | { | |
2775 | default: | |
2776 | break; | |
2777 | ||
2778 | case R_SH_PCDISP8BY2: | |
2779 | case R_SH_PCRELIMM8BY2: | |
2780 | insn = bfd_get_16 (abfd, loc); | |
2781 | oinsn = insn; | |
2782 | insn += add / 2; | |
2783 | if ((oinsn & 0xff00) != (insn & 0xff00)) | |
2784 | overflow = true; | |
2785 | bfd_put_16 (abfd, insn, loc); | |
2786 | break; | |
2787 | ||
2788 | case R_SH_PCDISP: | |
2789 | insn = bfd_get_16 (abfd, loc); | |
2790 | oinsn = insn; | |
2791 | insn += add / 2; | |
2792 | if ((oinsn & 0xf000) != (insn & 0xf000)) | |
2793 | overflow = true; | |
2794 | bfd_put_16 (abfd, insn, loc); | |
2795 | break; | |
2796 | ||
2797 | case R_SH_PCRELIMM8BY4: | |
2798 | /* This reloc ignores the least significant 3 bits of | |
2799 | the program counter before adding in the offset. | |
2800 | This means that if ADDR is at an even address, the | |
2801 | swap will not affect the offset. If ADDR is an at an | |
2802 | odd address, then the instruction will be crossing a | |
2803 | four byte boundary, and must be adjusted. */ | |
2804 | if ((addr & 3) != 0) | |
2805 | { | |
2806 | insn = bfd_get_16 (abfd, loc); | |
2807 | oinsn = insn; | |
2808 | insn += add / 2; | |
2809 | if ((oinsn & 0xff00) != (insn & 0xff00)) | |
2810 | overflow = true; | |
2811 | bfd_put_16 (abfd, insn, loc); | |
2812 | } | |
2813 | ||
2814 | break; | |
2815 | } | |
2816 | ||
2817 | if (overflow) | |
2818 | { | |
2819 | ((*_bfd_error_handler) | |
2820 | ("%s: 0x%lx: fatal: reloc overflow while relaxing", | |
2821 | bfd_get_filename (abfd), (unsigned long) irel->r_vaddr)); | |
2822 | bfd_set_error (bfd_error_bad_value); | |
2823 | return false; | |
2824 | } | |
2825 | } | |
2826 | } | |
2827 | ||
2828 | return true; | |
2829 | } | |
2830 | \f | |
2831 | /* This is a modification of _bfd_coff_generic_relocate_section, which | |
2832 | will handle SH relaxing. */ | |
2833 | ||
2834 | static boolean | |
2835 | sh_relocate_section (output_bfd, info, input_bfd, input_section, contents, | |
2836 | relocs, syms, sections) | |
5f771d47 | 2837 | bfd *output_bfd ATTRIBUTE_UNUSED; |
252b5132 RH |
2838 | struct bfd_link_info *info; |
2839 | bfd *input_bfd; | |
2840 | asection *input_section; | |
2841 | bfd_byte *contents; | |
2842 | struct internal_reloc *relocs; | |
2843 | struct internal_syment *syms; | |
2844 | asection **sections; | |
2845 | { | |
2846 | struct internal_reloc *rel; | |
2847 | struct internal_reloc *relend; | |
2848 | ||
2849 | rel = relocs; | |
2850 | relend = rel + input_section->reloc_count; | |
2851 | for (; rel < relend; rel++) | |
2852 | { | |
2853 | long symndx; | |
2854 | struct coff_link_hash_entry *h; | |
2855 | struct internal_syment *sym; | |
2856 | bfd_vma addend; | |
2857 | bfd_vma val; | |
2858 | reloc_howto_type *howto; | |
2859 | bfd_reloc_status_type rstat; | |
2860 | ||
2861 | /* Almost all relocs have to do with relaxing. If any work must | |
2862 | be done for them, it has been done in sh_relax_section. */ | |
2863 | if (rel->r_type != R_SH_IMM32 | |
17505c5c NC |
2864 | #ifdef COFF_WITH_PE |
2865 | && rel->r_type != R_SH_IMM32CE | |
2866 | && rel->r_type != R_SH_IMAGEBASE | |
2867 | #endif | |
252b5132 RH |
2868 | && rel->r_type != R_SH_PCDISP) |
2869 | continue; | |
2870 | ||
2871 | symndx = rel->r_symndx; | |
2872 | ||
2873 | if (symndx == -1) | |
2874 | { | |
2875 | h = NULL; | |
2876 | sym = NULL; | |
2877 | } | |
2878 | else | |
cbfe05c4 | 2879 | { |
252b5132 RH |
2880 | if (symndx < 0 |
2881 | || (unsigned long) symndx >= obj_raw_syment_count (input_bfd)) | |
2882 | { | |
2883 | (*_bfd_error_handler) | |
2884 | ("%s: illegal symbol index %ld in relocs", | |
2885 | bfd_get_filename (input_bfd), symndx); | |
2886 | bfd_set_error (bfd_error_bad_value); | |
2887 | return false; | |
2888 | } | |
2889 | h = obj_coff_sym_hashes (input_bfd)[symndx]; | |
2890 | sym = syms + symndx; | |
2891 | } | |
2892 | ||
2893 | if (sym != NULL && sym->n_scnum != 0) | |
2894 | addend = - sym->n_value; | |
2895 | else | |
2896 | addend = 0; | |
2897 | ||
2898 | if (rel->r_type == R_SH_PCDISP) | |
2899 | addend -= 4; | |
2900 | ||
2901 | if (rel->r_type >= SH_COFF_HOWTO_COUNT) | |
2902 | howto = NULL; | |
2903 | else | |
2904 | howto = &sh_coff_howtos[rel->r_type]; | |
2905 | ||
2906 | if (howto == NULL) | |
2907 | { | |
2908 | bfd_set_error (bfd_error_bad_value); | |
2909 | return false; | |
2910 | } | |
2911 | ||
17505c5c NC |
2912 | #ifdef COFF_WITH_PE |
2913 | if (rel->r_type == R_SH_IMAGEBASE) | |
2914 | addend -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase; | |
2915 | #endif | |
cbfe05c4 | 2916 | |
252b5132 RH |
2917 | val = 0; |
2918 | ||
2919 | if (h == NULL) | |
2920 | { | |
2921 | asection *sec; | |
2922 | ||
2923 | /* There is nothing to do for an internal PCDISP reloc. */ | |
2924 | if (rel->r_type == R_SH_PCDISP) | |
2925 | continue; | |
2926 | ||
2927 | if (symndx == -1) | |
2928 | { | |
2929 | sec = bfd_abs_section_ptr; | |
2930 | val = 0; | |
2931 | } | |
2932 | else | |
2933 | { | |
2934 | sec = sections[symndx]; | |
2935 | val = (sec->output_section->vma | |
2936 | + sec->output_offset | |
2937 | + sym->n_value | |
2938 | - sec->vma); | |
2939 | } | |
2940 | } | |
2941 | else | |
2942 | { | |
2943 | if (h->root.type == bfd_link_hash_defined | |
2944 | || h->root.type == bfd_link_hash_defweak) | |
2945 | { | |
2946 | asection *sec; | |
2947 | ||
2948 | sec = h->root.u.def.section; | |
2949 | val = (h->root.u.def.value | |
2950 | + sec->output_section->vma | |
2951 | + sec->output_offset); | |
2952 | } | |
2953 | else if (! info->relocateable) | |
2954 | { | |
2955 | if (! ((*info->callbacks->undefined_symbol) | |
2956 | (info, h->root.root.string, input_bfd, input_section, | |
5cc7c785 | 2957 | rel->r_vaddr - input_section->vma, true))) |
252b5132 RH |
2958 | return false; |
2959 | } | |
2960 | } | |
2961 | ||
2962 | rstat = _bfd_final_link_relocate (howto, input_bfd, input_section, | |
2963 | contents, | |
2964 | rel->r_vaddr - input_section->vma, | |
2965 | val, addend); | |
2966 | ||
2967 | switch (rstat) | |
2968 | { | |
2969 | default: | |
2970 | abort (); | |
2971 | case bfd_reloc_ok: | |
2972 | break; | |
2973 | case bfd_reloc_overflow: | |
2974 | { | |
2975 | const char *name; | |
2976 | char buf[SYMNMLEN + 1]; | |
2977 | ||
2978 | if (symndx == -1) | |
2979 | name = "*ABS*"; | |
2980 | else if (h != NULL) | |
2981 | name = h->root.root.string; | |
2982 | else if (sym->_n._n_n._n_zeroes == 0 | |
2983 | && sym->_n._n_n._n_offset != 0) | |
2984 | name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset; | |
2985 | else | |
2986 | { | |
2987 | strncpy (buf, sym->_n._n_name, SYMNMLEN); | |
2988 | buf[SYMNMLEN] = '\0'; | |
2989 | name = buf; | |
2990 | } | |
2991 | ||
2992 | if (! ((*info->callbacks->reloc_overflow) | |
2993 | (info, name, howto->name, (bfd_vma) 0, input_bfd, | |
2994 | input_section, rel->r_vaddr - input_section->vma))) | |
2995 | return false; | |
2996 | } | |
2997 | } | |
2998 | } | |
2999 | ||
3000 | return true; | |
3001 | } | |
3002 | ||
3003 | /* This is a version of bfd_generic_get_relocated_section_contents | |
3004 | which uses sh_relocate_section. */ | |
3005 | ||
3006 | static bfd_byte * | |
3007 | sh_coff_get_relocated_section_contents (output_bfd, link_info, link_order, | |
3008 | data, relocateable, symbols) | |
3009 | bfd *output_bfd; | |
3010 | struct bfd_link_info *link_info; | |
3011 | struct bfd_link_order *link_order; | |
3012 | bfd_byte *data; | |
3013 | boolean relocateable; | |
3014 | asymbol **symbols; | |
3015 | { | |
3016 | asection *input_section = link_order->u.indirect.section; | |
3017 | bfd *input_bfd = input_section->owner; | |
3018 | asection **sections = NULL; | |
3019 | struct internal_reloc *internal_relocs = NULL; | |
3020 | struct internal_syment *internal_syms = NULL; | |
3021 | ||
3022 | /* We only need to handle the case of relaxing, or of having a | |
3023 | particular set of section contents, specially. */ | |
3024 | if (relocateable | |
3025 | || coff_section_data (input_bfd, input_section) == NULL | |
3026 | || coff_section_data (input_bfd, input_section)->contents == NULL) | |
3027 | return bfd_generic_get_relocated_section_contents (output_bfd, link_info, | |
3028 | link_order, data, | |
3029 | relocateable, | |
3030 | symbols); | |
3031 | ||
3032 | memcpy (data, coff_section_data (input_bfd, input_section)->contents, | |
3033 | input_section->_raw_size); | |
3034 | ||
3035 | if ((input_section->flags & SEC_RELOC) != 0 | |
3036 | && input_section->reloc_count > 0) | |
3037 | { | |
3038 | bfd_size_type symesz = bfd_coff_symesz (input_bfd); | |
3039 | bfd_byte *esym, *esymend; | |
3040 | struct internal_syment *isymp; | |
3041 | asection **secpp; | |
3042 | ||
3043 | if (! _bfd_coff_get_external_symbols (input_bfd)) | |
3044 | goto error_return; | |
3045 | ||
3046 | internal_relocs = (_bfd_coff_read_internal_relocs | |
3047 | (input_bfd, input_section, false, (bfd_byte *) NULL, | |
3048 | false, (struct internal_reloc *) NULL)); | |
3049 | if (internal_relocs == NULL) | |
3050 | goto error_return; | |
3051 | ||
3052 | internal_syms = ((struct internal_syment *) | |
3053 | bfd_malloc (obj_raw_syment_count (input_bfd) | |
3054 | * sizeof (struct internal_syment))); | |
3055 | if (internal_syms == NULL) | |
3056 | goto error_return; | |
3057 | ||
3058 | sections = (asection **) bfd_malloc (obj_raw_syment_count (input_bfd) | |
3059 | * sizeof (asection *)); | |
3060 | if (sections == NULL) | |
3061 | goto error_return; | |
3062 | ||
3063 | isymp = internal_syms; | |
3064 | secpp = sections; | |
3065 | esym = (bfd_byte *) obj_coff_external_syms (input_bfd); | |
3066 | esymend = esym + obj_raw_syment_count (input_bfd) * symesz; | |
3067 | while (esym < esymend) | |
3068 | { | |
3069 | bfd_coff_swap_sym_in (input_bfd, (PTR) esym, (PTR) isymp); | |
3070 | ||
3071 | if (isymp->n_scnum != 0) | |
3072 | *secpp = coff_section_from_bfd_index (input_bfd, isymp->n_scnum); | |
3073 | else | |
3074 | { | |
3075 | if (isymp->n_value == 0) | |
3076 | *secpp = bfd_und_section_ptr; | |
3077 | else | |
3078 | *secpp = bfd_com_section_ptr; | |
3079 | } | |
3080 | ||
3081 | esym += (isymp->n_numaux + 1) * symesz; | |
3082 | secpp += isymp->n_numaux + 1; | |
3083 | isymp += isymp->n_numaux + 1; | |
3084 | } | |
3085 | ||
3086 | if (! sh_relocate_section (output_bfd, link_info, input_bfd, | |
3087 | input_section, data, internal_relocs, | |
3088 | internal_syms, sections)) | |
3089 | goto error_return; | |
3090 | ||
3091 | free (sections); | |
3092 | sections = NULL; | |
3093 | free (internal_syms); | |
3094 | internal_syms = NULL; | |
3095 | free (internal_relocs); | |
3096 | internal_relocs = NULL; | |
3097 | } | |
3098 | ||
3099 | return data; | |
3100 | ||
3101 | error_return: | |
3102 | if (internal_relocs != NULL) | |
3103 | free (internal_relocs); | |
3104 | if (internal_syms != NULL) | |
3105 | free (internal_syms); | |
3106 | if (sections != NULL) | |
3107 | free (sections); | |
3108 | return NULL; | |
3109 | } | |
3110 | ||
3111 | /* The target vectors. */ | |
3112 | ||
17505c5c | 3113 | #ifndef TARGET_SHL_SYM |
c3c89269 | 3114 | CREATE_BIG_COFF_TARGET_VEC (shcoff_vec, "coff-sh", BFD_IS_RELAXABLE, 0, '_', NULL) |
17505c5c | 3115 | #endif |
252b5132 | 3116 | |
c3c89269 NC |
3117 | #ifdef TARGET_SHL_SYM |
3118 | #define TARGET_SYM TARGET_SHL_SYM | |
3119 | #else | |
3120 | #define TARGET_SYM shlcoff_vec | |
3121 | #endif | |
cbfe05c4 | 3122 | |
c3c89269 NC |
3123 | #ifndef TARGET_SHL_NAME |
3124 | #define TARGET_SHL_NAME "coff-shl" | |
3125 | #endif | |
252b5132 | 3126 | |
17505c5c NC |
3127 | #ifdef COFF_WITH_PE |
3128 | CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE, | |
3129 | SEC_CODE | SEC_DATA, '_', NULL); | |
3130 | #else | |
86033394 NC |
3131 | CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE, |
3132 | 0, '_', NULL) | |
17505c5c | 3133 | #endif |
86033394 | 3134 | |
17505c5c | 3135 | #ifndef TARGET_SHL_SYM |
252b5132 RH |
3136 | /* Some people want versions of the SH COFF target which do not align |
3137 | to 16 byte boundaries. We implement that by adding a couple of new | |
3138 | target vectors. These are just like the ones above, but they | |
3139 | change the default section alignment. To generate them in the | |
3140 | assembler, use -small. To use them in the linker, use -b | |
3141 | coff-sh{l}-small and -oformat coff-sh{l}-small. | |
3142 | ||
3143 | Yes, this is a horrible hack. A general solution for setting | |
3144 | section alignment in COFF is rather complex. ELF handles this | |
3145 | correctly. */ | |
3146 | ||
3147 | /* Only recognize the small versions if the target was not defaulted. | |
3148 | Otherwise we won't recognize the non default endianness. */ | |
3149 | ||
3150 | static const bfd_target * | |
3151 | coff_small_object_p (abfd) | |
3152 | bfd *abfd; | |
3153 | { | |
3154 | if (abfd->target_defaulted) | |
3155 | { | |
3156 | bfd_set_error (bfd_error_wrong_format); | |
3157 | return NULL; | |
3158 | } | |
3159 | return coff_object_p (abfd); | |
3160 | } | |
3161 | ||
3162 | /* Set the section alignment for the small versions. */ | |
3163 | ||
3164 | static boolean | |
3165 | coff_small_new_section_hook (abfd, section) | |
3166 | bfd *abfd; | |
3167 | asection *section; | |
3168 | { | |
3169 | if (! coff_new_section_hook (abfd, section)) | |
3170 | return false; | |
3171 | ||
3172 | /* We must align to at least a four byte boundary, because longword | |
3173 | accesses must be on a four byte boundary. */ | |
3174 | if (section->alignment_power == COFF_DEFAULT_SECTION_ALIGNMENT_POWER) | |
3175 | section->alignment_power = 2; | |
3176 | ||
3177 | return true; | |
3178 | } | |
3179 | ||
3180 | /* This is copied from bfd_coff_std_swap_table so that we can change | |
3181 | the default section alignment power. */ | |
3182 | ||
3183 | static const bfd_coff_backend_data bfd_coff_small_swap_table = | |
3184 | { | |
3185 | coff_swap_aux_in, coff_swap_sym_in, coff_swap_lineno_in, | |
3186 | coff_swap_aux_out, coff_swap_sym_out, | |
3187 | coff_swap_lineno_out, coff_swap_reloc_out, | |
3188 | coff_swap_filehdr_out, coff_swap_aouthdr_out, | |
3189 | coff_swap_scnhdr_out, | |
692b7d62 | 3190 | FILHSZ, AOUTSZ, SCNHSZ, SYMESZ, AUXESZ, RELSZ, LINESZ, FILNMLEN, |
252b5132 RH |
3191 | #ifdef COFF_LONG_FILENAMES |
3192 | true, | |
3193 | #else | |
3194 | false, | |
3195 | #endif | |
3196 | #ifdef COFF_LONG_SECTION_NAMES | |
3197 | true, | |
3198 | #else | |
3199 | false, | |
3200 | #endif | |
3201 | 2, | |
ecefdb58 CP |
3202 | #ifdef COFF_FORCE_SYMBOLS_IN_STRINGS |
3203 | true, | |
3204 | #else | |
3205 | false, | |
3206 | #endif | |
3207 | #ifdef COFF_DEBUG_STRING_WIDE_PREFIX | |
3208 | 4, | |
3209 | #else | |
3210 | 2, | |
3211 | #endif | |
252b5132 RH |
3212 | coff_swap_filehdr_in, coff_swap_aouthdr_in, coff_swap_scnhdr_in, |
3213 | coff_swap_reloc_in, coff_bad_format_hook, coff_set_arch_mach_hook, | |
3214 | coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook, | |
3215 | coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook, | |
3216 | coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate, | |
5d54c628 | 3217 | coff_classify_symbol, coff_compute_section_file_positions, |
252b5132 RH |
3218 | coff_start_final_link, coff_relocate_section, coff_rtype_to_howto, |
3219 | coff_adjust_symndx, coff_link_add_one_symbol, | |
3220 | coff_link_output_has_begun, coff_final_link_postscript | |
3221 | }; | |
3222 | ||
3223 | #define coff_small_close_and_cleanup \ | |
3224 | coff_close_and_cleanup | |
3225 | #define coff_small_bfd_free_cached_info \ | |
3226 | coff_bfd_free_cached_info | |
3227 | #define coff_small_get_section_contents \ | |
3228 | coff_get_section_contents | |
3229 | #define coff_small_get_section_contents_in_window \ | |
3230 | coff_get_section_contents_in_window | |
3231 | ||
c3c89269 NC |
3232 | extern const bfd_target shlcoff_small_vec; |
3233 | ||
252b5132 RH |
3234 | const bfd_target shcoff_small_vec = |
3235 | { | |
3236 | "coff-sh-small", /* name */ | |
3237 | bfd_target_coff_flavour, | |
3238 | BFD_ENDIAN_BIG, /* data byte order is big */ | |
3239 | BFD_ENDIAN_BIG, /* header byte order is big */ | |
3240 | ||
3241 | (HAS_RELOC | EXEC_P | /* object flags */ | |
3242 | HAS_LINENO | HAS_DEBUG | | |
3243 | HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE), | |
3244 | ||
3245 | (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC), | |
3246 | '_', /* leading symbol underscore */ | |
3247 | '/', /* ar_pad_char */ | |
3248 | 15, /* ar_max_namelen */ | |
3249 | bfd_getb64, bfd_getb_signed_64, bfd_putb64, | |
3250 | bfd_getb32, bfd_getb_signed_32, bfd_putb32, | |
3251 | bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */ | |
3252 | bfd_getb64, bfd_getb_signed_64, bfd_putb64, | |
3253 | bfd_getb32, bfd_getb_signed_32, bfd_putb32, | |
3254 | bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */ | |
3255 | ||
3256 | {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */ | |
3257 | bfd_generic_archive_p, _bfd_dummy_target}, | |
3258 | {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */ | |
3259 | bfd_false}, | |
3260 | {bfd_false, coff_write_object_contents, /* bfd_write_contents */ | |
3261 | _bfd_write_archive_contents, bfd_false}, | |
3262 | ||
3263 | BFD_JUMP_TABLE_GENERIC (coff_small), | |
3264 | BFD_JUMP_TABLE_COPY (coff), | |
3265 | BFD_JUMP_TABLE_CORE (_bfd_nocore), | |
3266 | BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff), | |
3267 | BFD_JUMP_TABLE_SYMBOLS (coff), | |
3268 | BFD_JUMP_TABLE_RELOCS (coff), | |
3269 | BFD_JUMP_TABLE_WRITE (coff), | |
3270 | BFD_JUMP_TABLE_LINK (coff), | |
3271 | BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic), | |
3272 | ||
c3c89269 | 3273 | & shlcoff_small_vec, |
cbfe05c4 | 3274 | |
252b5132 RH |
3275 | (PTR) &bfd_coff_small_swap_table |
3276 | }; | |
3277 | ||
3278 | const bfd_target shlcoff_small_vec = | |
3279 | { | |
3280 | "coff-shl-small", /* name */ | |
3281 | bfd_target_coff_flavour, | |
3282 | BFD_ENDIAN_LITTLE, /* data byte order is little */ | |
3283 | BFD_ENDIAN_LITTLE, /* header byte order is little endian too*/ | |
3284 | ||
3285 | (HAS_RELOC | EXEC_P | /* object flags */ | |
3286 | HAS_LINENO | HAS_DEBUG | | |
3287 | HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE), | |
3288 | ||
3289 | (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC), | |
3290 | '_', /* leading symbol underscore */ | |
3291 | '/', /* ar_pad_char */ | |
3292 | 15, /* ar_max_namelen */ | |
3293 | bfd_getl64, bfd_getl_signed_64, bfd_putl64, | |
3294 | bfd_getl32, bfd_getl_signed_32, bfd_putl32, | |
3295 | bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */ | |
3296 | bfd_getl64, bfd_getl_signed_64, bfd_putl64, | |
3297 | bfd_getl32, bfd_getl_signed_32, bfd_putl32, | |
3298 | bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */ | |
3299 | ||
3300 | {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */ | |
cbfe05c4 | 3301 | bfd_generic_archive_p, _bfd_dummy_target}, |
252b5132 RH |
3302 | {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */ |
3303 | bfd_false}, | |
3304 | {bfd_false, coff_write_object_contents, /* bfd_write_contents */ | |
3305 | _bfd_write_archive_contents, bfd_false}, | |
3306 | ||
3307 | BFD_JUMP_TABLE_GENERIC (coff_small), | |
3308 | BFD_JUMP_TABLE_COPY (coff), | |
3309 | BFD_JUMP_TABLE_CORE (_bfd_nocore), | |
3310 | BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff), | |
3311 | BFD_JUMP_TABLE_SYMBOLS (coff), | |
3312 | BFD_JUMP_TABLE_RELOCS (coff), | |
3313 | BFD_JUMP_TABLE_WRITE (coff), | |
3314 | BFD_JUMP_TABLE_LINK (coff), | |
3315 | BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic), | |
3316 | ||
c3c89269 | 3317 | & shcoff_small_vec, |
cbfe05c4 | 3318 | |
252b5132 RH |
3319 | (PTR) &bfd_coff_small_swap_table |
3320 | }; | |
17505c5c | 3321 | #endif |