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[deliverable/binutils-gdb.git] / bfd / coff-sh.c
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c2dcd04e 1/* BFD back-end for Renesas Super-H COFF binaries.
eea6121a
AM		 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
252b5132
RH		 4 Contributed by Cygnus Support.
5 Written by Steve Chamberlain, <sac@cygnus.com>.
6 Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>.
7
c2dcd04e 8 This file is part of BFD, the Binary File Descriptor library.
252b5132 9
c2dcd04e
NC		 10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
252b5132 14
c2dcd04e
NC		 15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
252b5132 19
c2dcd04e
NC		 20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
252b5132
RH		 23
24#include "bfd.h"
25#include "sysdep.h"
993e9275 26#include "libiberty.h"
252b5132
RH		 27#include "libbfd.h"
28#include "bfdlink.h"
29#include "coff/sh.h"
30#include "coff/internal.h"
17505c5c
NC		 31
32#ifdef COFF_WITH_PE
33#include "coff/pe.h"
86033394
NC		 34
35#ifndef COFF_IMAGE_WITH_PE
b34976b6 36static bfd_boolean sh_align_load_span
86033394 37 PARAMS ((bfd *, asection *, bfd_byte *,
b34976b6
AM		 38 bfd_boolean (*) (bfd *, asection *, PTR, bfd_byte *, bfd_vma),
39 PTR, bfd_vma **, bfd_vma *, bfd_vma, bfd_vma, bfd_boolean *));
86033394
NC		 40
41#define _bfd_sh_align_load_span sh_align_load_span
42#endif
17505c5c
NC		 43#endif
44
252b5132
RH		 45#include "libcoff.h"
46
47/* Internal functions. */
48static bfd_reloc_status_type sh_reloc
49 PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
50static long get_symbol_value PARAMS ((asymbol *));
b34976b6
AM		 51static bfd_boolean sh_relax_section
52 PARAMS ((bfd *, asection *, struct bfd_link_info *, bfd_boolean *));
53static bfd_boolean sh_relax_delete_bytes
252b5132 54 PARAMS ((bfd *, asection *, bfd_vma, int));
86033394 55#ifndef COFF_IMAGE_WITH_PE
252b5132 56static const struct sh_opcode *sh_insn_info PARAMS ((unsigned int));
86033394 57#endif
b34976b6
AM		 58static bfd_boolean sh_align_loads
59 PARAMS ((bfd *, asection *, struct internal_reloc *, bfd_byte *,
60 bfd_boolean *));
61static bfd_boolean sh_swap_insns
252b5132 62 PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
b34976b6 63static bfd_boolean sh_relocate_section
252b5132
RH		 64 PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
65 struct internal_reloc *, struct internal_syment *, asection **));
66static bfd_byte *sh_coff_get_relocated_section_contents
67 PARAMS ((bfd *, struct bfd_link_info *, struct bfd_link_order *,
b34976b6 68 bfd_byte *, bfd_boolean, asymbol **));
f4ffd778 69static reloc_howto_type * sh_coff_reloc_type_lookup PARAMS ((bfd *, bfd_reloc_code_real_type));
252b5132 70
17505c5c
NC		 71#ifdef COFF_WITH_PE
72/* Can't build import tables with 2**4 alignment. */
73#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 2
74#else
252b5132 75/* Default section alignment to 2**4. */
17505c5c
NC		 76#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 4
77#endif
78
79#ifdef COFF_IMAGE_WITH_PE
80/* Align PE executables. */
81#define COFF_PAGE_SIZE 0x1000
82#endif
252b5132
RH		 83
84/* Generate long file names. */
85#define COFF_LONG_FILENAMES
86
17505c5c 87#ifdef COFF_WITH_PE
b34976b6
AM		 88static bfd_boolean in_reloc_p PARAMS ((bfd *, reloc_howto_type *));
89/* Return TRUE if this relocation should
17505c5c 90 appear in the output .reloc section. */
b34976b6 91static bfd_boolean in_reloc_p (abfd, howto)
17505c5c
NC		 92 bfd * abfd ATTRIBUTE_UNUSED;
93 reloc_howto_type * howto;
94{
95 return ! howto->pc_relative && howto->type != R_SH_IMAGEBASE;
cbfe05c4 96}
17505c5c
NC		 97#endif
98
252b5132
RH		 99/* The supported relocations. There are a lot of relocations defined
100 in coff/internal.h which we do not expect to ever see. */
101static reloc_howto_type sh_coff_howtos[] =
102{
5f771d47
ILT		 103 EMPTY_HOWTO (0),
104 EMPTY_HOWTO (1),
17505c5c
NC		 105#ifdef COFF_WITH_PE
106 /* Windows CE */
107 HOWTO (R_SH_IMM32CE, /* type */
108 0, /* rightshift */
109 2, /* size (0 = byte, 1 = short, 2 = long) */
110 32, /* bitsize */
b34976b6 111 FALSE, /* pc_relative */
17505c5c
NC		 112 0, /* bitpos */
113 complain_overflow_bitfield, /* complain_on_overflow */
114 sh_reloc, /* special_function */
115 "r_imm32ce", /* name */
b34976b6 116 TRUE, /* partial_inplace */
17505c5c
NC		 117 0xffffffff, /* src_mask */
118 0xffffffff, /* dst_mask */
b34976b6 119 FALSE), /* pcrel_offset */
17505c5c 120#else
5f771d47 121 EMPTY_HOWTO (2),
17505c5c 122#endif
5f771d47
ILT		 123 EMPTY_HOWTO (3), /* R_SH_PCREL8 */
124 EMPTY_HOWTO (4), /* R_SH_PCREL16 */
125 EMPTY_HOWTO (5), /* R_SH_HIGH8 */
126 EMPTY_HOWTO (6), /* R_SH_IMM24 */
127 EMPTY_HOWTO (7), /* R_SH_LOW16 */
128 EMPTY_HOWTO (8),
129 EMPTY_HOWTO (9), /* R_SH_PCDISP8BY4 */
252b5132
RH		 130
131 HOWTO (R_SH_PCDISP8BY2, /* type */
132 1, /* rightshift */
133 1, /* size (0 = byte, 1 = short, 2 = long) */
134 8, /* bitsize */
b34976b6 135 TRUE, /* pc_relative */
252b5132
RH		 136 0, /* bitpos */
137 complain_overflow_signed, /* complain_on_overflow */
138 sh_reloc, /* special_function */
139 "r_pcdisp8by2", /* name */
b34976b6 140 TRUE, /* partial_inplace */
252b5132
RH		 141 0xff, /* src_mask */
142 0xff, /* dst_mask */
b34976b6 143 TRUE), /* pcrel_offset */
252b5132 144
5f771d47 145 EMPTY_HOWTO (11), /* R_SH_PCDISP8 */
252b5132
RH		 146
147 HOWTO (R_SH_PCDISP, /* type */
148 1, /* rightshift */
149 1, /* size (0 = byte, 1 = short, 2 = long) */
150 12, /* bitsize */
b34976b6 151 TRUE, /* pc_relative */
252b5132
RH		 152 0, /* bitpos */
153 complain_overflow_signed, /* complain_on_overflow */
154 sh_reloc, /* special_function */
155 "r_pcdisp12by2", /* name */
b34976b6 156 TRUE, /* partial_inplace */
252b5132
RH		 157 0xfff, /* src_mask */
158 0xfff, /* dst_mask */
b34976b6 159 TRUE), /* pcrel_offset */
252b5132 160
5f771d47 161 EMPTY_HOWTO (13),
252b5132
RH		 162
163 HOWTO (R_SH_IMM32, /* type */
164 0, /* rightshift */
165 2, /* size (0 = byte, 1 = short, 2 = long) */
166 32, /* bitsize */
b34976b6 167 FALSE, /* pc_relative */
252b5132
RH		 168 0, /* bitpos */
169 complain_overflow_bitfield, /* complain_on_overflow */
170 sh_reloc, /* special_function */
171 "r_imm32", /* name */
b34976b6 172 TRUE, /* partial_inplace */
252b5132
RH		 173 0xffffffff, /* src_mask */
174 0xffffffff, /* dst_mask */
b34976b6 175 FALSE), /* pcrel_offset */
252b5132 176
5f771d47 177 EMPTY_HOWTO (15),
17505c5c 178#ifdef COFF_WITH_PE
cbfe05c4
KH		 179 HOWTO (R_SH_IMAGEBASE, /* type */
180 0, /* rightshift */
181 2, /* size (0 = byte, 1 = short, 2 = long) */
182 32, /* bitsize */
b34976b6 183 FALSE, /* pc_relative */
cbfe05c4 184 0, /* bitpos */
17505c5c 185 complain_overflow_bitfield, /* complain_on_overflow */
cbfe05c4
KH		 186 sh_reloc, /* special_function */
187 "rva32", /* name */
b34976b6 188 TRUE, /* partial_inplace */
cbfe05c4
KH		 189 0xffffffff, /* src_mask */
190 0xffffffff, /* dst_mask */
b34976b6 191 FALSE), /* pcrel_offset */
17505c5c 192#else
5f771d47 193 EMPTY_HOWTO (16), /* R_SH_IMM8 */
17505c5c 194#endif
5f771d47
ILT		 195 EMPTY_HOWTO (17), /* R_SH_IMM8BY2 */
196 EMPTY_HOWTO (18), /* R_SH_IMM8BY4 */
197 EMPTY_HOWTO (19), /* R_SH_IMM4 */
198 EMPTY_HOWTO (20), /* R_SH_IMM4BY2 */
199 EMPTY_HOWTO (21), /* R_SH_IMM4BY4 */
252b5132
RH		 200
201 HOWTO (R_SH_PCRELIMM8BY2, /* type */
202 1, /* rightshift */
203 1, /* size (0 = byte, 1 = short, 2 = long) */
204 8, /* bitsize */
b34976b6 205 TRUE, /* pc_relative */
252b5132
RH		 206 0, /* bitpos */
207 complain_overflow_unsigned, /* complain_on_overflow */
208 sh_reloc, /* special_function */
209 "r_pcrelimm8by2", /* name */
b34976b6 210 TRUE, /* partial_inplace */
252b5132
RH		 211 0xff, /* src_mask */
212 0xff, /* dst_mask */
b34976b6 213 TRUE), /* pcrel_offset */
252b5132
RH		 214
215 HOWTO (R_SH_PCRELIMM8BY4, /* type */
216 2, /* rightshift */
217 1, /* size (0 = byte, 1 = short, 2 = long) */
218 8, /* bitsize */
b34976b6 219 TRUE, /* pc_relative */
252b5132
RH		 220 0, /* bitpos */
221 complain_overflow_unsigned, /* complain_on_overflow */
222 sh_reloc, /* special_function */
223 "r_pcrelimm8by4", /* name */
b34976b6 224 TRUE, /* partial_inplace */
252b5132
RH		 225 0xff, /* src_mask */
226 0xff, /* dst_mask */
b34976b6 227 TRUE), /* pcrel_offset */
252b5132
RH		 228
229 HOWTO (R_SH_IMM16, /* type */
230 0, /* rightshift */
231 1, /* size (0 = byte, 1 = short, 2 = long) */
232 16, /* bitsize */
b34976b6 233 FALSE, /* pc_relative */
252b5132
RH		 234 0, /* bitpos */
235 complain_overflow_bitfield, /* complain_on_overflow */
236 sh_reloc, /* special_function */
237 "r_imm16", /* name */
b34976b6 238 TRUE, /* partial_inplace */
252b5132
RH		 239 0xffff, /* src_mask */
240 0xffff, /* dst_mask */
b34976b6 241 FALSE), /* pcrel_offset */
252b5132
RH		 242
243 HOWTO (R_SH_SWITCH16, /* type */
244 0, /* rightshift */
245 1, /* size (0 = byte, 1 = short, 2 = long) */
246 16, /* bitsize */
b34976b6 247 FALSE, /* pc_relative */
252b5132
RH		 248 0, /* bitpos */
249 complain_overflow_bitfield, /* complain_on_overflow */
250 sh_reloc, /* special_function */
251 "r_switch16", /* name */
b34976b6 252 TRUE, /* partial_inplace */
252b5132
RH		 253 0xffff, /* src_mask */
254 0xffff, /* dst_mask */
b34976b6 255 FALSE), /* pcrel_offset */
252b5132
RH		 256
257 HOWTO (R_SH_SWITCH32, /* type */
258 0, /* rightshift */
259 2, /* size (0 = byte, 1 = short, 2 = long) */
260 32, /* bitsize */
b34976b6 261 FALSE, /* pc_relative */
252b5132
RH		 262 0, /* bitpos */
263 complain_overflow_bitfield, /* complain_on_overflow */
264 sh_reloc, /* special_function */
265 "r_switch32", /* name */
b34976b6 266 TRUE, /* partial_inplace */
252b5132
RH		 267 0xffffffff, /* src_mask */
268 0xffffffff, /* dst_mask */
b34976b6 269 FALSE), /* pcrel_offset */
252b5132
RH		 270
271 HOWTO (R_SH_USES, /* type */
272 0, /* rightshift */
273 1, /* size (0 = byte, 1 = short, 2 = long) */
274 16, /* bitsize */
b34976b6 275 FALSE, /* pc_relative */
252b5132
RH		 276 0, /* bitpos */
277 complain_overflow_bitfield, /* complain_on_overflow */
278 sh_reloc, /* special_function */
279 "r_uses", /* name */
b34976b6 280 TRUE, /* partial_inplace */
252b5132
RH		 281 0xffff, /* src_mask */
282 0xffff, /* dst_mask */
b34976b6 283 FALSE), /* pcrel_offset */
252b5132
RH		 284
285 HOWTO (R_SH_COUNT, /* type */
286 0, /* rightshift */
287 2, /* size (0 = byte, 1 = short, 2 = long) */
288 32, /* bitsize */
b34976b6 289 FALSE, /* pc_relative */
252b5132
RH		 290 0, /* bitpos */
291 complain_overflow_bitfield, /* complain_on_overflow */
292 sh_reloc, /* special_function */
293 "r_count", /* name */
b34976b6 294 TRUE, /* partial_inplace */
252b5132
RH		 295 0xffffffff, /* src_mask */
296 0xffffffff, /* dst_mask */
b34976b6 297 FALSE), /* pcrel_offset */
252b5132
RH		 298
299 HOWTO (R_SH_ALIGN, /* type */
300 0, /* rightshift */
301 2, /* size (0 = byte, 1 = short, 2 = long) */
302 32, /* bitsize */
b34976b6 303 FALSE, /* pc_relative */
252b5132
RH		 304 0, /* bitpos */
305 complain_overflow_bitfield, /* complain_on_overflow */
306 sh_reloc, /* special_function */
307 "r_align", /* name */
b34976b6 308 TRUE, /* partial_inplace */
252b5132
RH		 309 0xffffffff, /* src_mask */
310 0xffffffff, /* dst_mask */
b34976b6 311 FALSE), /* pcrel_offset */
252b5132
RH		 312
313 HOWTO (R_SH_CODE, /* type */
314 0, /* rightshift */
315 2, /* size (0 = byte, 1 = short, 2 = long) */
316 32, /* bitsize */
b34976b6 317 FALSE, /* pc_relative */
252b5132
RH		 318 0, /* bitpos */
319 complain_overflow_bitfield, /* complain_on_overflow */
320 sh_reloc, /* special_function */
321 "r_code", /* name */
b34976b6 322 TRUE, /* partial_inplace */
252b5132
RH		 323 0xffffffff, /* src_mask */
324 0xffffffff, /* dst_mask */
b34976b6 325 FALSE), /* pcrel_offset */
252b5132
RH		 326
327 HOWTO (R_SH_DATA, /* type */
328 0, /* rightshift */
329 2, /* size (0 = byte, 1 = short, 2 = long) */
330 32, /* bitsize */
b34976b6 331 FALSE, /* pc_relative */
252b5132
RH		 332 0, /* bitpos */
333 complain_overflow_bitfield, /* complain_on_overflow */
334 sh_reloc, /* special_function */
335 "r_data", /* name */
b34976b6 336 TRUE, /* partial_inplace */
252b5132
RH		 337 0xffffffff, /* src_mask */
338 0xffffffff, /* dst_mask */
b34976b6 339 FALSE), /* pcrel_offset */
252b5132
RH		 340
341 HOWTO (R_SH_LABEL, /* type */
342 0, /* rightshift */
343 2, /* size (0 = byte, 1 = short, 2 = long) */
344 32, /* bitsize */
b34976b6 345 FALSE, /* pc_relative */
252b5132
RH		 346 0, /* bitpos */
347 complain_overflow_bitfield, /* complain_on_overflow */
348 sh_reloc, /* special_function */
349 "r_label", /* name */
b34976b6 350 TRUE, /* partial_inplace */
252b5132
RH		 351 0xffffffff, /* src_mask */
352 0xffffffff, /* dst_mask */
b34976b6 353 FALSE), /* pcrel_offset */
252b5132
RH		 354
355 HOWTO (R_SH_SWITCH8, /* type */
356 0, /* rightshift */
357 0, /* size (0 = byte, 1 = short, 2 = long) */
358 8, /* bitsize */
b34976b6 359 FALSE, /* pc_relative */
252b5132
RH		 360 0, /* bitpos */
361 complain_overflow_bitfield, /* complain_on_overflow */
362 sh_reloc, /* special_function */
363 "r_switch8", /* name */
b34976b6 364 TRUE, /* partial_inplace */
252b5132
RH		 365 0xff, /* src_mask */
366 0xff, /* dst_mask */
b34976b6 367 FALSE) /* pcrel_offset */
252b5132
RH		 368};
369
370#define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])
371
372/* Check for a bad magic number. */
373#define BADMAG(x) SHBADMAG(x)
374
375/* Customize coffcode.h (this is not currently used). */
376#define SH 1
377
378/* FIXME: This should not be set here. */
379#define __A_MAGIC_SET__
380
17505c5c 381#ifndef COFF_WITH_PE
252b5132 382/* Swap the r_offset field in and out. */
dc810e39
AM		 383#define SWAP_IN_RELOC_OFFSET H_GET_32
384#define SWAP_OUT_RELOC_OFFSET H_PUT_32
252b5132
RH		 385
386/* Swap out extra information in the reloc structure. */
387#define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \
388 do \
389 { \
390 dst->r_stuff[0] = 'S'; \
391 dst->r_stuff[1] = 'C'; \
392 } \
393 while (0)
17505c5c 394#endif
252b5132
RH		 395
396/* Get the value of a symbol, when performing a relocation. */
397
398static long
cbfe05c4 399get_symbol_value (symbol)
252b5132 400 asymbol *symbol;
cbfe05c4 401{
252b5132
RH		 402 bfd_vma relocation;
403
404 if (bfd_is_com_section (symbol->section))
cbfe05c4
KH		 405 relocation = 0;
406 else
252b5132
RH		 407 relocation = (symbol->value +
408 symbol->section->output_section->vma +
409 symbol->section->output_offset);
410
411 return relocation;
412}
413
17505c5c
NC		 414#ifdef COFF_WITH_PE
415/* Convert an rtype to howto for the COFF backend linker.
416 Copied from coff-i386. */
417#define coff_rtype_to_howto coff_sh_rtype_to_howto
f4ffd778 418static reloc_howto_type * coff_sh_rtype_to_howto PARAMS ((bfd *, asection *, struct internal_reloc *, struct coff_link_hash_entry *, struct internal_syment *, bfd_vma *));
17505c5c
NC		 419
420static reloc_howto_type *
421coff_sh_rtype_to_howto (abfd, sec, rel, h, sym, addendp)
86033394 422 bfd * abfd ATTRIBUTE_UNUSED;
17505c5c
NC		 423 asection * sec;
424 struct internal_reloc * rel;
425 struct coff_link_hash_entry * h;
426 struct internal_syment * sym;
427 bfd_vma * addendp;
428{
429 reloc_howto_type * howto;
430
431 howto = sh_coff_howtos + rel->r_type;
432
433 *addendp = 0;
434
435 if (howto->pc_relative)
436 *addendp += sec->vma;
437
438 if (sym != NULL && sym->n_scnum == 0 && sym->n_value != 0)
439 {
440 /* This is a common symbol. The section contents include the
441 size (sym->n_value) as an addend. The relocate_section
442 function will be adding in the final value of the symbol. We
443 need to subtract out the current size in order to get the
444 correct result. */
445 BFD_ASSERT (h != NULL);
446 }
447
448 if (howto->pc_relative)
449 {
450 *addendp -= 4;
451
452 /* If the symbol is defined, then the generic code is going to
453 add back the symbol value in order to cancel out an
454 adjustment it made to the addend. However, we set the addend
455 to 0 at the start of this function. We need to adjust here,
456 to avoid the adjustment the generic code will make. FIXME:
457 This is getting a bit hackish. */
458 if (sym != NULL && sym->n_scnum != 0)
459 *addendp -= sym->n_value;
460 }
461
462 if (rel->r_type == R_SH_IMAGEBASE)
463 *addendp -= pe_data (sec->output_section->owner)->pe_opthdr.ImageBase;
464
465 return howto;
466}
467
993e9275
NC		 468#endif /* COFF_WITH_PE */
469
17505c5c
NC		 470/* This structure is used to map BFD reloc codes to SH PE relocs. */
471struct shcoff_reloc_map
472{
aa066ac8 473 bfd_reloc_code_real_type bfd_reloc_val;
17505c5c
NC		 474 unsigned char shcoff_reloc_val;
475};
476
a9a32010 477#ifdef COFF_WITH_PE
17505c5c
NC		 478/* An array mapping BFD reloc codes to SH PE relocs. */
479static const struct shcoff_reloc_map sh_reloc_map[] =
480{
481 { BFD_RELOC_32, R_SH_IMM32CE },
482 { BFD_RELOC_RVA, R_SH_IMAGEBASE },
483 { BFD_RELOC_CTOR, R_SH_IMM32CE },
484};
a9a32010
DJ		 485#else
486/* An array mapping BFD reloc codes to SH PE relocs. */
487static const struct shcoff_reloc_map sh_reloc_map[] =
488{
489 { BFD_RELOC_32, R_SH_IMM32 },
490 { BFD_RELOC_CTOR, R_SH_IMM32 },
491};
492#endif
17505c5c
NC		 493
494/* Given a BFD reloc code, return the howto structure for the
495 corresponding SH PE reloc. */
496#define coff_bfd_reloc_type_lookup sh_coff_reloc_type_lookup
497
498static reloc_howto_type *
499sh_coff_reloc_type_lookup (abfd, code)
500 bfd * abfd ATTRIBUTE_UNUSED;
501 bfd_reloc_code_real_type code;
502{
503 unsigned int i;
504
993e9275
NC		 505 for (i = ARRAY_SIZE (sh_reloc_map); i--;)
506 if (sh_reloc_map[i].bfd_reloc_val == code)
507 return &sh_coff_howtos[(int) sh_reloc_map[i].shcoff_reloc_val];
17505c5c
NC		 508
509 fprintf (stderr, "SH Error: unknown reloc type %d\n", code);
510 return NULL;
511}
17505c5c 512
252b5132
RH		 513/* This macro is used in coffcode.h to get the howto corresponding to
514 an internal reloc. */
515
516#define RTYPE2HOWTO(relent, internal) \
517 ((relent)->howto = \
518 ((internal)->r_type < SH_COFF_HOWTO_COUNT \
519 ? &sh_coff_howtos[(internal)->r_type] \
520 : (reloc_howto_type *) NULL))
521
522/* This is the same as the macro in coffcode.h, except that it copies
523 r_offset into reloc_entry->addend for some relocs. */
524#define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \
525 { \
526 coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \
527 if (ptr && bfd_asymbol_bfd (ptr) != abfd) \
528 coffsym = (obj_symbols (abfd) \
529 + (cache_ptr->sym_ptr_ptr - symbols)); \
530 else if (ptr) \
531 coffsym = coff_symbol_from (abfd, ptr); \
532 if (coffsym != (coff_symbol_type *) NULL \
533 && coffsym->native->u.syment.n_scnum == 0) \
534 cache_ptr->addend = 0; \
535 else if (ptr && bfd_asymbol_bfd (ptr) == abfd \
536 && ptr->section != (asection *) NULL) \
537 cache_ptr->addend = - (ptr->section->vma + ptr->value); \
538 else \
539 cache_ptr->addend = 0; \
540 if ((reloc).r_type == R_SH_SWITCH8 \
541 || (reloc).r_type == R_SH_SWITCH16 \
542 || (reloc).r_type == R_SH_SWITCH32 \
543 || (reloc).r_type == R_SH_USES \
544 || (reloc).r_type == R_SH_COUNT \
545 || (reloc).r_type == R_SH_ALIGN) \
546 cache_ptr->addend = (reloc).r_offset; \
547 }
548
549/* This is the howto function for the SH relocations. */
550
551static bfd_reloc_status_type
552sh_reloc (abfd, reloc_entry, symbol_in, data, input_section, output_bfd,
553 error_message)
554 bfd *abfd;
555 arelent *reloc_entry;
556 asymbol *symbol_in;
557 PTR data;
558 asection *input_section;
559 bfd *output_bfd;
5f771d47 560 char **error_message ATTRIBUTE_UNUSED;
252b5132
RH		 561{
562 unsigned long insn;
563 bfd_vma sym_value;
564 unsigned short r_type;
565 bfd_vma addr = reloc_entry->address;
566 bfd_byte *hit_data = addr + (bfd_byte *) data;
567
568 r_type = reloc_entry->howto->type;
569
570 if (output_bfd != NULL)
571 {
572 /* Partial linking--do nothing. */
573 reloc_entry->address += input_section->output_offset;
574 return bfd_reloc_ok;
575 }
576
577 /* Almost all relocs have to do with relaxing. If any work must be
578 done for them, it has been done in sh_relax_section. */
579 if (r_type != R_SH_IMM32
17505c5c
NC		 580#ifdef COFF_WITH_PE
581 && r_type != R_SH_IMM32CE
582 && r_type != R_SH_IMAGEBASE
583#endif
252b5132
RH		 584 && (r_type != R_SH_PCDISP
585 || (symbol_in->flags & BSF_LOCAL) != 0))
586 return bfd_reloc_ok;
587
588 if (symbol_in != NULL
589 && bfd_is_und_section (symbol_in->section))
590 return bfd_reloc_undefined;
591
592 sym_value = get_symbol_value (symbol_in);
593
594 switch (r_type)
595 {
596 case R_SH_IMM32:
17505c5c
NC		 597#ifdef COFF_WITH_PE
598 case R_SH_IMM32CE:
599#endif
252b5132
RH		 600 insn = bfd_get_32 (abfd, hit_data);
601 insn += sym_value + reloc_entry->addend;
dc810e39 602 bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
252b5132 603 break;
17505c5c
NC		 604#ifdef COFF_WITH_PE
605 case R_SH_IMAGEBASE:
606 insn = bfd_get_32 (abfd, hit_data);
dc810e39
AM		 607 insn += sym_value + reloc_entry->addend;
608 insn -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
609 bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
17505c5c
NC		 610 break;
611#endif
252b5132
RH		 612 case R_SH_PCDISP:
613 insn = bfd_get_16 (abfd, hit_data);
614 sym_value += reloc_entry->addend;
615 sym_value -= (input_section->output_section->vma
616 + input_section->output_offset
617 + addr
618 + 4);
619 sym_value += (insn & 0xfff) << 1;
620 if (insn & 0x800)
621 sym_value -= 0x1000;
622 insn = (insn & 0xf000) | (sym_value & 0xfff);
dc810e39 623 bfd_put_16 (abfd, (bfd_vma) insn, hit_data);
252b5132
RH		 624 if (sym_value < (bfd_vma) -0x1000 || sym_value >= 0x1000)
625 return bfd_reloc_overflow;
626 break;
627 default:
628 abort ();
629 break;
630 }
631
632 return bfd_reloc_ok;
633}
634
875f7f69 635#define coff_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match
252b5132
RH		 636
637/* We can do relaxing. */
638#define coff_bfd_relax_section sh_relax_section
639
640/* We use the special COFF backend linker. */
641#define coff_relocate_section sh_relocate_section
642
643/* When relaxing, we need to use special code to get the relocated
644 section contents. */
645#define coff_bfd_get_relocated_section_contents \
646 sh_coff_get_relocated_section_contents
647
648#include "coffcode.h"
649\f
650/* This function handles relaxing on the SH.
651
652 Function calls on the SH look like this:
653
654 movl L1,r0
655 ...
656 jsr @r0
657 ...
658 L1:
659 .long function
660
661 The compiler and assembler will cooperate to create R_SH_USES
662 relocs on the jsr instructions. The r_offset field of the
663 R_SH_USES reloc is the PC relative offset to the instruction which
664 loads the register (the r_offset field is computed as though it
665 were a jump instruction, so the offset value is actually from four
666 bytes past the instruction). The linker can use this reloc to
667 determine just which function is being called, and thus decide
668 whether it is possible to replace the jsr with a bsr.
669
670 If multiple function calls are all based on a single register load
671 (i.e., the same function is called multiple times), the compiler
672 guarantees that each function call will have an R_SH_USES reloc.
673 Therefore, if the linker is able to convert each R_SH_USES reloc
674 which refers to that address, it can safely eliminate the register
675 load.
676
677 When the assembler creates an R_SH_USES reloc, it examines it to
678 determine which address is being loaded (L1 in the above example).
679 It then counts the number of references to that address, and
680 creates an R_SH_COUNT reloc at that address. The r_offset field of
681 the R_SH_COUNT reloc will be the number of references. If the
682 linker is able to eliminate a register load, it can use the
683 R_SH_COUNT reloc to see whether it can also eliminate the function
684 address.
685
686 SH relaxing also handles another, unrelated, matter. On the SH, if
687 a load or store instruction is not aligned on a four byte boundary,
688 the memory cycle interferes with the 32 bit instruction fetch,
689 causing a one cycle bubble in the pipeline. Therefore, we try to
690 align load and store instructions on four byte boundaries if we
691 can, by swapping them with one of the adjacent instructions. */
692
b34976b6 693static bfd_boolean
252b5132
RH		 694sh_relax_section (abfd, sec, link_info, again)
695 bfd *abfd;
696 asection *sec;
697 struct bfd_link_info *link_info;
b34976b6 698 bfd_boolean *again;
252b5132
RH		 699{
700 struct internal_reloc *internal_relocs;
b34976b6 701 bfd_boolean have_code;
252b5132
RH		 702 struct internal_reloc *irel, *irelend;
703 bfd_byte *contents = NULL;
252b5132 704
b34976b6 705 *again = FALSE;
252b5132 706
1049f94e 707 if (link_info->relocatable
252b5132
RH		 708 || (sec->flags & SEC_RELOC) == 0
709 || sec->reloc_count == 0)
b34976b6 710 return TRUE;
252b5132 711
eea6121a
AM		 712 if (coff_section_data (abfd, sec) == NULL)
713 {
714 bfd_size_type amt = sizeof (struct coff_section_tdata);
715 sec->used_by_bfd = (PTR) bfd_zalloc (abfd, amt);
716 if (sec->used_by_bfd == NULL)
717 return FALSE;
718 }
252b5132
RH		 719
720 internal_relocs = (_bfd_coff_read_internal_relocs
721 (abfd, sec, link_info->keep_memory,
b34976b6 722 (bfd_byte *) NULL, FALSE,
252b5132
RH		 723 (struct internal_reloc *) NULL));
724 if (internal_relocs == NULL)
725 goto error_return;
252b5132 726
b34976b6 727 have_code = FALSE;
252b5132
RH		 728
729 irelend = internal_relocs + sec->reloc_count;
730 for (irel = internal_relocs; irel < irelend; irel++)
731 {
732 bfd_vma laddr, paddr, symval;
733 unsigned short insn;
734 struct internal_reloc *irelfn, *irelscan, *irelcount;
735 struct internal_syment sym;
736 bfd_signed_vma foff;
737
738 if (irel->r_type == R_SH_CODE)
b34976b6 739 have_code = TRUE;
252b5132
RH		 740
741 if (irel->r_type != R_SH_USES)
742 continue;
743
744 /* Get the section contents. */
745 if (contents == NULL)
746 {
eea6121a 747 if (coff_section_data (abfd, sec)->contents != NULL)
252b5132
RH		 748 contents = coff_section_data (abfd, sec)->contents;
749 else
750 {
eea6121a 751 if (!bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 752 goto error_return;
753 }
754 }
755
756 /* The r_offset field of the R_SH_USES reloc will point us to
757 the register load. The 4 is because the r_offset field is
758 computed as though it were a jump offset, which are based
759 from 4 bytes after the jump instruction. */
760 laddr = irel->r_vaddr - sec->vma + 4;
761 /* Careful to sign extend the 32-bit offset. */
762 laddr += ((irel->r_offset & 0xffffffff) ^ 0x80000000) - 0x80000000;
eea6121a 763 if (laddr >= sec->size)
252b5132
RH		 764 {
765 (*_bfd_error_handler) ("%s: 0x%lx: warning: bad R_SH_USES offset",
8f615d07 766 bfd_archive_filename (abfd),
252b5132
RH		 767 (unsigned long) irel->r_vaddr);
768 continue;
769 }
770 insn = bfd_get_16 (abfd, contents + laddr);
771
772 /* If the instruction is not mov.l NN,rN, we don't know what to do. */
773 if ((insn & 0xf000) != 0xd000)
774 {
775 ((*_bfd_error_handler)
776 ("%s: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x",
8f615d07 777 bfd_archive_filename (abfd), (unsigned long) irel->r_vaddr, insn));
252b5132
RH		 778 continue;
779 }
780
781 /* Get the address from which the register is being loaded. The
782 displacement in the mov.l instruction is quadrupled. It is a
783 displacement from four bytes after the movl instruction, but,
784 before adding in the PC address, two least significant bits
785 of the PC are cleared. We assume that the section is aligned
786 on a four byte boundary. */
787 paddr = insn & 0xff;
788 paddr *= 4;
dc810e39 789 paddr += (laddr + 4) &~ (bfd_vma) 3;
eea6121a 790 if (paddr >= sec->size)
252b5132
RH		 791 {
792 ((*_bfd_error_handler)
793 ("%s: 0x%lx: warning: bad R_SH_USES load offset",
8f615d07 794 bfd_archive_filename (abfd), (unsigned long) irel->r_vaddr));
252b5132
RH		 795 continue;
796 }
797
798 /* Get the reloc for the address from which the register is
799 being loaded. This reloc will tell us which function is
800 actually being called. */
801 paddr += sec->vma;
802 for (irelfn = internal_relocs; irelfn < irelend; irelfn++)
803 if (irelfn->r_vaddr == paddr
17505c5c
NC		 804#ifdef COFF_WITH_PE
805 && (irelfn->r_type == R_SH_IMM32
806 || irelfn->r_type == R_SH_IMM32CE
eea6121a 807 || irelfn->r_type == R_SH_IMAGEBASE)
17505c5c
NC		 808
809#else
eea6121a 810 && irelfn->r_type == R_SH_IMM32
17505c5c 811#endif
eea6121a 812 )
252b5132
RH		 813 break;
814 if (irelfn >= irelend)
815 {
816 ((*_bfd_error_handler)
817 ("%s: 0x%lx: warning: could not find expected reloc",
8f615d07 818 bfd_archive_filename (abfd), (unsigned long) paddr));
252b5132
RH		 819 continue;
820 }
821
822 /* Get the value of the symbol referred to by the reloc. */
823 if (! _bfd_coff_get_external_symbols (abfd))
824 goto error_return;
825 bfd_coff_swap_sym_in (abfd,
826 ((bfd_byte *) obj_coff_external_syms (abfd)
827 + (irelfn->r_symndx
828 * bfd_coff_symesz (abfd))),
829 &sym);
830 if (sym.n_scnum != 0 && sym.n_scnum != sec->target_index)
831 {
832 ((*_bfd_error_handler)
833 ("%s: 0x%lx: warning: symbol in unexpected section",
8f615d07 834 bfd_archive_filename (abfd), (unsigned long) paddr));
252b5132
RH		 835 continue;
836 }
837
838 if (sym.n_sclass != C_EXT)
839 {
840 symval = (sym.n_value
841 - sec->vma
842 + sec->output_section->vma
843 + sec->output_offset);
844 }
845 else
846 {
847 struct coff_link_hash_entry *h;
848
849 h = obj_coff_sym_hashes (abfd)[irelfn->r_symndx];
850 BFD_ASSERT (h != NULL);
851 if (h->root.type != bfd_link_hash_defined
852 && h->root.type != bfd_link_hash_defweak)
853 {
854 /* This appears to be a reference to an undefined
855 symbol. Just ignore it--it will be caught by the
856 regular reloc processing. */
857 continue;
858 }
859
860 symval = (h->root.u.def.value
861 + h->root.u.def.section->output_section->vma
862 + h->root.u.def.section->output_offset);
863 }
864
865 symval += bfd_get_32 (abfd, contents + paddr - sec->vma);
866
867 /* See if this function call can be shortened. */
868 foff = (symval
869 - (irel->r_vaddr
870 - sec->vma
871 + sec->output_section->vma
872 + sec->output_offset
873 + 4));
874 if (foff < -0x1000 || foff >= 0x1000)
875 {
876 /* After all that work, we can't shorten this function call. */
877 continue;
878 }
879
880 /* Shorten the function call. */
881
882 /* For simplicity of coding, we are going to modify the section
883 contents, the section relocs, and the BFD symbol table. We
884 must tell the rest of the code not to free up this
885 information. It would be possible to instead create a table
886 of changes which have to be made, as is done in coff-mips.c;
887 that would be more work, but would require less memory when
888 the linker is run. */
889
252b5132 890 coff_section_data (abfd, sec)->relocs = internal_relocs;
b34976b6 891 coff_section_data (abfd, sec)->keep_relocs = TRUE;
252b5132
RH		 892
893 coff_section_data (abfd, sec)->contents = contents;
b34976b6 894 coff_section_data (abfd, sec)->keep_contents = TRUE;
252b5132 895
b34976b6 896 obj_coff_keep_syms (abfd) = TRUE;
252b5132
RH		 897
898 /* Replace the jsr with a bsr. */
899
900 /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and
901 replace the jsr with a bsr. */
902 irel->r_type = R_SH_PCDISP;
903 irel->r_symndx = irelfn->r_symndx;
904 if (sym.n_sclass != C_EXT)
905 {
906 /* If this needs to be changed because of future relaxing,
907 it will be handled here like other internal PCDISP
908 relocs. */
909 bfd_put_16 (abfd,
dc810e39 910 (bfd_vma) 0xb000 | ((foff >> 1) & 0xfff),
252b5132
RH		 911 contents + irel->r_vaddr - sec->vma);
912 }
913 else
914 {
915 /* We can't fully resolve this yet, because the external
916 symbol value may be changed by future relaxing. We let
917 the final link phase handle it. */
dc810e39
AM		 918 bfd_put_16 (abfd, (bfd_vma) 0xb000,
919 contents + irel->r_vaddr - sec->vma);
252b5132
RH		 920 }
921
922 /* See if there is another R_SH_USES reloc referring to the same
923 register load. */
924 for (irelscan = internal_relocs; irelscan < irelend; irelscan++)
925 if (irelscan->r_type == R_SH_USES
926 && laddr == irelscan->r_vaddr - sec->vma + 4 + irelscan->r_offset)
927 break;
928 if (irelscan < irelend)
929 {
930 /* Some other function call depends upon this register load,
931 and we have not yet converted that function call.
932 Indeed, we may never be able to convert it. There is
933 nothing else we can do at this point. */
934 continue;
935 }
936
937 /* Look for a R_SH_COUNT reloc on the location where the
938 function address is stored. Do this before deleting any
939 bytes, to avoid confusion about the address. */
940 for (irelcount = internal_relocs; irelcount < irelend; irelcount++)
941 if (irelcount->r_vaddr == paddr
942 && irelcount->r_type == R_SH_COUNT)
943 break;
944
945 /* Delete the register load. */
946 if (! sh_relax_delete_bytes (abfd, sec, laddr, 2))
947 goto error_return;
948
949 /* That will change things, so, just in case it permits some
950 other function call to come within range, we should relax
951 again. Note that this is not required, and it may be slow. */
b34976b6 952 *again = TRUE;
252b5132
RH		 953
954 /* Now check whether we got a COUNT reloc. */
955 if (irelcount >= irelend)
956 {
957 ((*_bfd_error_handler)
958 ("%s: 0x%lx: warning: could not find expected COUNT reloc",
8f615d07 959 bfd_archive_filename (abfd), (unsigned long) paddr));
252b5132
RH		 960 continue;
961 }
962
963 /* The number of uses is stored in the r_offset field. We've
964 just deleted one. */
965 if (irelcount->r_offset == 0)
966 {
967 ((*_bfd_error_handler) ("%s: 0x%lx: warning: bad count",
8f615d07 968 bfd_archive_filename (abfd),
252b5132
RH		 969 (unsigned long) paddr));
970 continue;
971 }
972
973 --irelcount->r_offset;
974
975 /* If there are no more uses, we can delete the address. Reload
976 the address from irelfn, in case it was changed by the
977 previous call to sh_relax_delete_bytes. */
978 if (irelcount->r_offset == 0)
979 {
980 if (! sh_relax_delete_bytes (abfd, sec,
981 irelfn->r_vaddr - sec->vma, 4))
982 goto error_return;
983 }
984
985 /* We've done all we can with that function call. */
986 }
987
988 /* Look for load and store instructions that we can align on four
989 byte boundaries. */
990 if (have_code)
991 {
b34976b6 992 bfd_boolean swapped;
252b5132
RH		 993
994 /* Get the section contents. */
995 if (contents == NULL)
996 {
eea6121a 997 if (coff_section_data (abfd, sec)->contents != NULL)
252b5132
RH		 998 contents = coff_section_data (abfd, sec)->contents;
999 else
1000 {
eea6121a 1001 if (!bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 1002 goto error_return;
1003 }
1004 }
1005
1006 if (! sh_align_loads (abfd, sec, internal_relocs, contents, &swapped))
1007 goto error_return;
1008
1009 if (swapped)
1010 {
252b5132 1011 coff_section_data (abfd, sec)->relocs = internal_relocs;
b34976b6 1012 coff_section_data (abfd, sec)->keep_relocs = TRUE;
252b5132
RH		 1013
1014 coff_section_data (abfd, sec)->contents = contents;
b34976b6 1015 coff_section_data (abfd, sec)->keep_contents = TRUE;
252b5132 1016
b34976b6 1017 obj_coff_keep_syms (abfd) = TRUE;
252b5132
RH		 1018 }
1019 }
1020
eea6121a
AM		 1021 if (internal_relocs != NULL
1022 && internal_relocs != coff_section_data (abfd, sec)->relocs)
252b5132 1023 {
eea6121a
AM		 1024 if (! link_info->keep_memory)
1025 free (internal_relocs);
1026 else
1027 coff_section_data (abfd, sec)->relocs = internal_relocs;
252b5132
RH		 1028 }
1029
eea6121a 1030 if (contents != NULL && contents != coff_section_data (abfd, sec)->contents)
252b5132
RH		 1031 {
1032 if (! link_info->keep_memory)
eea6121a 1033 free (contents);
252b5132 1034 else
eea6121a
AM		 1035 /* Cache the section contents for coff_link_input_bfd. */
1036 coff_section_data (abfd, sec)->contents = contents;
252b5132
RH		 1037 }
1038
b34976b6 1039 return TRUE;
252b5132
RH		 1040
1041 error_return:
eea6121a
AM		 1042 if (internal_relocs != NULL
1043 && internal_relocs != coff_section_data (abfd, sec)->relocs)
1044 free (internal_relocs);
1045 if (contents != NULL && contents != coff_section_data (abfd, sec)->contents)
1046 free (contents);
b34976b6 1047 return FALSE;
252b5132
RH		 1048}
1049
1050/* Delete some bytes from a section while relaxing. */
1051
b34976b6 1052static bfd_boolean
252b5132
RH		 1053sh_relax_delete_bytes (abfd, sec, addr, count)
1054 bfd *abfd;
1055 asection *sec;
1056 bfd_vma addr;
1057 int count;
1058{
1059 bfd_byte *contents;
1060 struct internal_reloc *irel, *irelend;
1061 struct internal_reloc *irelalign;
1062 bfd_vma toaddr;
1063 bfd_byte *esym, *esymend;
1064 bfd_size_type symesz;
1065 struct coff_link_hash_entry **sym_hash;
1066 asection *o;
1067
1068 contents = coff_section_data (abfd, sec)->contents;
1069
1070 /* The deletion must stop at the next ALIGN reloc for an aligment
1071 power larger than the number of bytes we are deleting. */
1072
1073 irelalign = NULL;
eea6121a 1074 toaddr = sec->size;
252b5132
RH		 1075
1076 irel = coff_section_data (abfd, sec)->relocs;
1077 irelend = irel + sec->reloc_count;
1078 for (; irel < irelend; irel++)
1079 {
1080 if (irel->r_type == R_SH_ALIGN
1081 && irel->r_vaddr - sec->vma > addr
1082 && count < (1 << irel->r_offset))
1083 {
1084 irelalign = irel;
1085 toaddr = irel->r_vaddr - sec->vma;
1086 break;
1087 }
1088 }
1089
1090 /* Actually delete the bytes. */
dc810e39
AM		 1091 memmove (contents + addr, contents + addr + count,
1092 (size_t) (toaddr - addr - count));
252b5132 1093 if (irelalign == NULL)
eea6121a 1094 sec->size -= count;
252b5132
RH		 1095 else
1096 {
1097 int i;
1098
1099#define NOP_OPCODE (0x0009)
1100
1101 BFD_ASSERT ((count & 1) == 0);
1102 for (i = 0; i < count; i += 2)
dc810e39 1103 bfd_put_16 (abfd, (bfd_vma) NOP_OPCODE, contents + toaddr - count + i);
252b5132
RH		 1104 }
1105
1106 /* Adjust all the relocs. */
1107 for (irel = coff_section_data (abfd, sec)->relocs; irel < irelend; irel++)
1108 {
1109 bfd_vma nraddr, stop;
1110 bfd_vma start = 0;
1111 int insn = 0;
1112 struct internal_syment sym;
1113 int off, adjust, oinsn;
1114 bfd_signed_vma voff = 0;
b34976b6 1115 bfd_boolean overflow;
252b5132
RH		 1116
1117 /* Get the new reloc address. */
1118 nraddr = irel->r_vaddr - sec->vma;
1119 if ((irel->r_vaddr - sec->vma > addr
1120 && irel->r_vaddr - sec->vma < toaddr)
1121 || (irel->r_type == R_SH_ALIGN
1122 && irel->r_vaddr - sec->vma == toaddr))
1123 nraddr -= count;
1124
1125 /* See if this reloc was for the bytes we have deleted, in which
1126 case we no longer care about it. Don't delete relocs which
1127 represent addresses, though. */
1128 if (irel->r_vaddr - sec->vma >= addr
1129 && irel->r_vaddr - sec->vma < addr + count
1130 && irel->r_type != R_SH_ALIGN
1131 && irel->r_type != R_SH_CODE
1132 && irel->r_type != R_SH_DATA
1133 && irel->r_type != R_SH_LABEL)
1134 irel->r_type = R_SH_UNUSED;
1135
1136 /* If this is a PC relative reloc, see if the range it covers
1137 includes the bytes we have deleted. */
1138 switch (irel->r_type)
1139 {
1140 default:
1141 break;
1142
1143 case R_SH_PCDISP8BY2:
1144 case R_SH_PCDISP:
1145 case R_SH_PCRELIMM8BY2:
1146 case R_SH_PCRELIMM8BY4:
1147 start = irel->r_vaddr - sec->vma;
1148 insn = bfd_get_16 (abfd, contents + nraddr);
1149 break;
1150 }
1151
1152 switch (irel->r_type)
1153 {
1154 default:
1155 start = stop = addr;
1156 break;
1157
1158 case R_SH_IMM32:
17505c5c
NC		 1159#ifdef COFF_WITH_PE
1160 case R_SH_IMM32CE:
1161 case R_SH_IMAGEBASE:
1162#endif
252b5132
RH		 1163 /* If this reloc is against a symbol defined in this
1164 section, and the symbol will not be adjusted below, we
1165 must check the addend to see it will put the value in
1166 range to be adjusted, and hence must be changed. */
1167 bfd_coff_swap_sym_in (abfd,
1168 ((bfd_byte *) obj_coff_external_syms (abfd)
1169 + (irel->r_symndx
1170 * bfd_coff_symesz (abfd))),
1171 &sym);
1172 if (sym.n_sclass != C_EXT
1173 && sym.n_scnum == sec->target_index
1174 && ((bfd_vma) sym.n_value <= addr
1175 || (bfd_vma) sym.n_value >= toaddr))
1176 {
1177 bfd_vma val;
1178
1179 val = bfd_get_32 (abfd, contents + nraddr);
1180 val += sym.n_value;
1181 if (val > addr && val < toaddr)
1182 bfd_put_32 (abfd, val - count, contents + nraddr);
1183 }
1184 start = stop = addr;
1185 break;
1186
1187 case R_SH_PCDISP8BY2:
1188 off = insn & 0xff;
1189 if (off & 0x80)
1190 off -= 0x100;
1191 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1192 break;
1193
1194 case R_SH_PCDISP:
1195 bfd_coff_swap_sym_in (abfd,
1196 ((bfd_byte *) obj_coff_external_syms (abfd)
1197 + (irel->r_symndx
1198 * bfd_coff_symesz (abfd))),
1199 &sym);
1200 if (sym.n_sclass == C_EXT)
1201 start = stop = addr;
1202 else
1203 {
1204 off = insn & 0xfff;
1205 if (off & 0x800)
1206 off -= 0x1000;
1207 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1208 }
1209 break;
1210
1211 case R_SH_PCRELIMM8BY2:
1212 off = insn & 0xff;
1213 stop = start + 4 + off * 2;
1214 break;
1215
1216 case R_SH_PCRELIMM8BY4:
1217 off = insn & 0xff;
1218 stop = (start &~ (bfd_vma) 3) + 4 + off * 4;
1219 break;
1220
1221 case R_SH_SWITCH8:
1222 case R_SH_SWITCH16:
1223 case R_SH_SWITCH32:
1224 /* These relocs types represent
1225 .word L2-L1
1226 The r_offset field holds the difference between the reloc
1227 address and L1. That is the start of the reloc, and
1228 adding in the contents gives us the top. We must adjust
1229 both the r_offset field and the section contents. */
1230
1231 start = irel->r_vaddr - sec->vma;
1232 stop = (bfd_vma) ((bfd_signed_vma) start - (long) irel->r_offset);
1233
1234 if (start > addr
1235 && start < toaddr
1236 && (stop <= addr || stop >= toaddr))
1237 irel->r_offset += count;
1238 else if (stop > addr
1239 && stop < toaddr
1240 && (start <= addr || start >= toaddr))
1241 irel->r_offset -= count;
1242
1243 start = stop;
1244
1245 if (irel->r_type == R_SH_SWITCH16)
1246 voff = bfd_get_signed_16 (abfd, contents + nraddr);
1247 else if (irel->r_type == R_SH_SWITCH8)
1248 voff = bfd_get_8 (abfd, contents + nraddr);
1249 else
1250 voff = bfd_get_signed_32 (abfd, contents + nraddr);
1251 stop = (bfd_vma) ((bfd_signed_vma) start + voff);
1252
1253 break;
1254
1255 case R_SH_USES:
1256 start = irel->r_vaddr - sec->vma;
1257 stop = (bfd_vma) ((bfd_signed_vma) start
1258 + (long) irel->r_offset
1259 + 4);
1260 break;
1261 }
1262
1263 if (start > addr
1264 && start < toaddr
1265 && (stop <= addr || stop >= toaddr))
1266 adjust = count;
1267 else if (stop > addr
1268 && stop < toaddr
1269 && (start <= addr || start >= toaddr))
1270 adjust = - count;
1271 else
1272 adjust = 0;
1273
1274 if (adjust != 0)
1275 {
1276 oinsn = insn;
b34976b6 1277 overflow = FALSE;
252b5132
RH		 1278 switch (irel->r_type)
1279 {
1280 default:
1281 abort ();
1282 break;
1283
1284 case R_SH_PCDISP8BY2:
1285 case R_SH_PCRELIMM8BY2:
1286 insn += adjust / 2;
1287 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 1288 overflow = TRUE;
dc810e39 1289 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1290 break;
1291
1292 case R_SH_PCDISP:
1293 insn += adjust / 2;
1294 if ((oinsn & 0xf000) != (insn & 0xf000))
b34976b6 1295 overflow = TRUE;
dc810e39 1296 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1297 break;
1298
1299 case R_SH_PCRELIMM8BY4:
1300 BFD_ASSERT (adjust == count || count >= 4);
1301 if (count >= 4)
1302 insn += adjust / 4;
1303 else
1304 {
1305 if ((irel->r_vaddr & 3) == 0)
1306 ++insn;
1307 }
1308 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 1309 overflow = TRUE;
dc810e39 1310 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1311 break;
1312
1313 case R_SH_SWITCH8:
1314 voff += adjust;
1315 if (voff < 0 || voff >= 0xff)
b34976b6 1316 overflow = TRUE;
dc810e39 1317 bfd_put_8 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1318 break;
1319
1320 case R_SH_SWITCH16:
1321 voff += adjust;
1322 if (voff < - 0x8000 || voff >= 0x8000)
b34976b6 1323 overflow = TRUE;
dc810e39 1324 bfd_put_signed_16 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1325 break;
1326
1327 case R_SH_SWITCH32:
1328 voff += adjust;
dc810e39 1329 bfd_put_signed_32 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1330 break;
1331
1332 case R_SH_USES:
1333 irel->r_offset += adjust;
1334 break;
1335 }
1336
1337 if (overflow)
1338 {
1339 ((*_bfd_error_handler)
1340 ("%s: 0x%lx: fatal: reloc overflow while relaxing",
8f615d07 1341 bfd_archive_filename (abfd), (unsigned long) irel->r_vaddr));
252b5132 1342 bfd_set_error (bfd_error_bad_value);
b34976b6 1343 return FALSE;
252b5132
RH		 1344 }
1345 }
1346
1347 irel->r_vaddr = nraddr + sec->vma;
1348 }
1349
1350 /* Look through all the other sections. If there contain any IMM32
1351 relocs against internal symbols which we are not going to adjust
1352 below, we may need to adjust the addends. */
1353 for (o = abfd->sections; o != NULL; o = o->next)
1354 {
1355 struct internal_reloc *internal_relocs;
1356 struct internal_reloc *irelscan, *irelscanend;
1357 bfd_byte *ocontents;
1358
1359 if (o == sec
1360 || (o->flags & SEC_RELOC) == 0
1361 || o->reloc_count == 0)
1362 continue;
1363
1364 /* We always cache the relocs. Perhaps, if info->keep_memory is
b34976b6 1365 FALSE, we should free them, if we are permitted to, when we
252b5132
RH		 1366 leave sh_coff_relax_section. */
1367 internal_relocs = (_bfd_coff_read_internal_relocs
b34976b6 1368 (abfd, o, TRUE, (bfd_byte *) NULL, FALSE,
252b5132
RH		 1369 (struct internal_reloc *) NULL));
1370 if (internal_relocs == NULL)
b34976b6 1371 return FALSE;
252b5132
RH		 1372
1373 ocontents = NULL;
1374 irelscanend = internal_relocs + o->reloc_count;
1375 for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++)
1376 {
1377 struct internal_syment sym;
1378
17505c5c
NC		 1379#ifdef COFF_WITH_PE
1380 if (irelscan->r_type != R_SH_IMM32
1381 && irelscan->r_type != R_SH_IMAGEBASE
1382 && irelscan->r_type != R_SH_IMM32CE)
1383#else
252b5132 1384 if (irelscan->r_type != R_SH_IMM32)
17505c5c 1385#endif
252b5132
RH		 1386 continue;
1387
1388 bfd_coff_swap_sym_in (abfd,
1389 ((bfd_byte *) obj_coff_external_syms (abfd)
1390 + (irelscan->r_symndx
1391 * bfd_coff_symesz (abfd))),
1392 &sym);
1393 if (sym.n_sclass != C_EXT
1394 && sym.n_scnum == sec->target_index
1395 && ((bfd_vma) sym.n_value <= addr
1396 || (bfd_vma) sym.n_value >= toaddr))
1397 {
1398 bfd_vma val;
1399
1400 if (ocontents == NULL)
1401 {
1402 if (coff_section_data (abfd, o)->contents != NULL)
1403 ocontents = coff_section_data (abfd, o)->contents;
1404 else
1405 {
eea6121a
AM		 1406 if (!bfd_malloc_and_get_section (abfd, o, &ocontents))
1407 return FALSE;
252b5132 1408 /* We always cache the section contents.
b34976b6 1409 Perhaps, if info->keep_memory is FALSE, we
252b5132
RH		 1410 should free them, if we are permitted to,
1411 when we leave sh_coff_relax_section. */
252b5132
RH		 1412 coff_section_data (abfd, o)->contents = ocontents;
1413 }
1414 }
1415
1416 val = bfd_get_32 (abfd, ocontents + irelscan->r_vaddr - o->vma);
1417 val += sym.n_value;
1418 if (val > addr && val < toaddr)
1419 bfd_put_32 (abfd, val - count,
1420 ocontents + irelscan->r_vaddr - o->vma);
1421
b34976b6 1422 coff_section_data (abfd, o)->keep_contents = TRUE;
252b5132
RH		 1423 }
1424 }
1425 }
1426
1427 /* Adjusting the internal symbols will not work if something has
1428 already retrieved the generic symbols. It would be possible to
1429 make this work by adjusting the generic symbols at the same time.
1430 However, this case should not arise in normal usage. */
1431 if (obj_symbols (abfd) != NULL
1432 || obj_raw_syments (abfd) != NULL)
1433 {
1434 ((*_bfd_error_handler)
1435 ("%s: fatal: generic symbols retrieved before relaxing",
8f615d07 1436 bfd_archive_filename (abfd)));
252b5132 1437 bfd_set_error (bfd_error_invalid_operation);
b34976b6 1438 return FALSE;
252b5132
RH		 1439 }
1440
1441 /* Adjust all the symbols. */
1442 sym_hash = obj_coff_sym_hashes (abfd);
1443 symesz = bfd_coff_symesz (abfd);
1444 esym = (bfd_byte *) obj_coff_external_syms (abfd);
1445 esymend = esym + obj_raw_syment_count (abfd) * symesz;
1446 while (esym < esymend)
1447 {
1448 struct internal_syment isym;
1449
1450 bfd_coff_swap_sym_in (abfd, (PTR) esym, (PTR) &isym);
1451
1452 if (isym.n_scnum == sec->target_index
1453 && (bfd_vma) isym.n_value > addr
1454 && (bfd_vma) isym.n_value < toaddr)
1455 {
1456 isym.n_value -= count;
1457
1458 bfd_coff_swap_sym_out (abfd, (PTR) &isym, (PTR) esym);
1459
1460 if (*sym_hash != NULL)
1461 {
1462 BFD_ASSERT ((*sym_hash)->root.type == bfd_link_hash_defined
1463 || (*sym_hash)->root.type == bfd_link_hash_defweak);
1464 BFD_ASSERT ((*sym_hash)->root.u.def.value >= addr
1465 && (*sym_hash)->root.u.def.value < toaddr);
1466 (*sym_hash)->root.u.def.value -= count;
1467 }
1468 }
1469
1470 esym += (isym.n_numaux + 1) * symesz;
1471 sym_hash += isym.n_numaux + 1;
1472 }
1473
1474 /* See if we can move the ALIGN reloc forward. We have adjusted
1475 r_vaddr for it already. */
1476 if (irelalign != NULL)
1477 {
1478 bfd_vma alignto, alignaddr;
1479
1480 alignto = BFD_ALIGN (toaddr, 1 << irelalign->r_offset);
1481 alignaddr = BFD_ALIGN (irelalign->r_vaddr - sec->vma,
1482 1 << irelalign->r_offset);
1483 if (alignto != alignaddr)
1484 {
1485 /* Tail recursion. */
1486 return sh_relax_delete_bytes (abfd, sec, alignaddr,
dc810e39 1487 (int) (alignto - alignaddr));
252b5132
RH		 1488 }
1489 }
1490
b34976b6 1491 return TRUE;
252b5132
RH		 1492}
1493\f
1494/* This is yet another version of the SH opcode table, used to rapidly
1495 get information about a particular instruction. */
1496
1497/* The opcode map is represented by an array of these structures. The
1498 array is indexed by the high order four bits in the instruction. */
1499
1500struct sh_major_opcode
1501{
1502 /* A pointer to the instruction list. This is an array which
1503 contains all the instructions with this major opcode. */
1504 const struct sh_minor_opcode *minor_opcodes;
1505 /* The number of elements in minor_opcodes. */
1506 unsigned short count;
1507};
1508
1509/* This structure holds information for a set of SH opcodes. The
1510 instruction code is anded with the mask value, and the resulting
1511 value is used to search the order opcode list. */
1512
1513struct sh_minor_opcode
1514{
1515 /* The sorted opcode list. */
1516 const struct sh_opcode *opcodes;
1517 /* The number of elements in opcodes. */
1518 unsigned short count;
1519 /* The mask value to use when searching the opcode list. */
1520 unsigned short mask;
1521};
1522
1523/* This structure holds information for an SH instruction. An array
1524 of these structures is sorted in order by opcode. */
1525
1526struct sh_opcode
1527{
1528 /* The code for this instruction, after it has been anded with the
1529 mask value in the sh_major_opcode structure. */
1530 unsigned short opcode;
1531 /* Flags for this instruction. */
86033394 1532 unsigned long flags;
252b5132
RH		 1533};
1534
1535/* Flag which appear in the sh_opcode structure. */
1536
1537/* This instruction loads a value from memory. */
1538#define LOAD (0x1)
1539
1540/* This instruction stores a value to memory. */
1541#define STORE (0x2)
1542
1543/* This instruction is a branch. */
1544#define BRANCH (0x4)
1545
1546/* This instruction has a delay slot. */
1547#define DELAY (0x8)
1548
1549/* This instruction uses the value in the register in the field at
1550 mask 0x0f00 of the instruction. */
1551#define USES1 (0x10)
84dcfba7 1552#define USES1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1553
1554/* This instruction uses the value in the register in the field at
1555 mask 0x00f0 of the instruction. */
1556#define USES2 (0x20)
84dcfba7 1557#define USES2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1558
1559/* This instruction uses the value in register 0. */
1560#define USESR0 (0x40)
1561
1562/* This instruction sets the value in the register in the field at
1563 mask 0x0f00 of the instruction. */
1564#define SETS1 (0x80)
84dcfba7 1565#define SETS1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1566
1567/* This instruction sets the value in the register in the field at
1568 mask 0x00f0 of the instruction. */
1569#define SETS2 (0x100)
84dcfba7 1570#define SETS2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1571
1572/* This instruction sets register 0. */
1573#define SETSR0 (0x200)
1574
1575/* This instruction sets a special register. */
1576#define SETSSP (0x400)
1577
1578/* This instruction uses a special register. */
1579#define USESSP (0x800)
1580
1581/* This instruction uses the floating point register in the field at
1582 mask 0x0f00 of the instruction. */
1583#define USESF1 (0x1000)
84dcfba7 1584#define USESF1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1585
1586/* This instruction uses the floating point register in the field at
1587 mask 0x00f0 of the instruction. */
1588#define USESF2 (0x2000)
84dcfba7 1589#define USESF2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1590
1591/* This instruction uses floating point register 0. */
1592#define USESF0 (0x4000)
1593
1594/* This instruction sets the floating point register in the field at
1595 mask 0x0f00 of the instruction. */
1596#define SETSF1 (0x8000)
84dcfba7 1597#define SETSF1_REG(x) ((x & 0x0f00) >> 8)
252b5132 1598
d4845d57
JR		 1599#define USESAS (0x10000)
1600#define USESAS_REG(x) (((((x) >> 8) - 2) & 3) + 2)
1601#define USESR8 (0x20000)
1602#define SETSAS (0x40000)
1603#define SETSAS_REG(x) USESAS_REG (x)
1604
8d6ad26e
AM		 1605#define MAP(a) a, sizeof a / sizeof a[0]
1606
86033394 1607#ifndef COFF_IMAGE_WITH_PE
b34976b6 1608static bfd_boolean sh_insn_uses_reg
252b5132 1609 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1610static bfd_boolean sh_insn_sets_reg
84dcfba7 1611 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1612static bfd_boolean sh_insn_uses_or_sets_reg
84dcfba7 1613 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1614static bfd_boolean sh_insn_uses_freg
252b5132 1615 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1616static bfd_boolean sh_insn_sets_freg
84dcfba7 1617 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1618static bfd_boolean sh_insn_uses_or_sets_freg
84dcfba7 1619 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1620static bfd_boolean sh_insns_conflict
252b5132
RH		 1621 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1622 const struct sh_opcode *));
b34976b6 1623static bfd_boolean sh_load_use
252b5132
RH		 1624 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1625 const struct sh_opcode *));
252b5132 1626
8d6ad26e 1627/* The opcode maps. */
252b5132
RH		 1628
1629static const struct sh_opcode sh_opcode00[] =
1630{
1631 { 0x0008, SETSSP }, /* clrt */
1632 { 0x0009, 0 }, /* nop */
1633 { 0x000b, BRANCH | DELAY | USESSP }, /* rts */
1634 { 0x0018, SETSSP }, /* sett */
1635 { 0x0019, SETSSP }, /* div0u */
1636 { 0x001b, 0 }, /* sleep */
1637 { 0x0028, SETSSP }, /* clrmac */
1638 { 0x002b, BRANCH | DELAY | SETSSP }, /* rte */
1639 { 0x0038, USESSP | SETSSP }, /* ldtlb */
1640 { 0x0048, SETSSP }, /* clrs */
1641 { 0x0058, SETSSP } /* sets */
1642};
1643
1644static const struct sh_opcode sh_opcode01[] =
1645{
252b5132
RH		 1646 { 0x0003, BRANCH | DELAY | USES1 | SETSSP }, /* bsrf rn */
1647 { 0x000a, SETS1 | USESSP }, /* sts mach,rn */
252b5132 1648 { 0x001a, SETS1 | USESSP }, /* sts macl,rn */
252b5132
RH		 1649 { 0x0023, BRANCH | DELAY | USES1 }, /* braf rn */
1650 { 0x0029, SETS1 | USESSP }, /* movt rn */
1651 { 0x002a, SETS1 | USESSP }, /* sts pr,rn */
d4845d57
JR		 1652 { 0x005a, SETS1 | USESSP }, /* sts fpul,rn */
1653 { 0x006a, SETS1 | USESSP }, /* sts fpscr,rn / sts dsr,rn */
1654 { 0x0083, LOAD | USES1 }, /* pref @rn */
1655 { 0x007a, SETS1 | USESSP }, /* sts a0,rn */
1656 { 0x008a, SETS1 | USESSP }, /* sts x0,rn */
1657 { 0x009a, SETS1 | USESSP }, /* sts x1,rn */
1658 { 0x00aa, SETS1 | USESSP }, /* sts y0,rn */
1659 { 0x00ba, SETS1 | USESSP } /* sts y1,rn */
1660};
1661
1662/* These sixteen instructions can be handled with one table entry below. */
1663#if 0
1664 { 0x0002, SETS1 | USESSP }, /* stc sr,rn */
1665 { 0x0012, SETS1 | USESSP }, /* stc gbr,rn */
1666 { 0x0022, SETS1 | USESSP }, /* stc vbr,rn */
252b5132
RH		 1667 { 0x0032, SETS1 | USESSP }, /* stc ssr,rn */
1668 { 0x0042, SETS1 | USESSP }, /* stc spc,rn */
d4845d57
JR		 1669 { 0x0052, SETS1 | USESSP }, /* stc mod,rn */
1670 { 0x0062, SETS1 | USESSP }, /* stc rs,rn */
1671 { 0x0072, SETS1 | USESSP }, /* stc re,rn */
252b5132 1672 { 0x0082, SETS1 | USESSP }, /* stc r0_bank,rn */
252b5132
RH		 1673 { 0x0092, SETS1 | USESSP }, /* stc r1_bank,rn */
1674 { 0x00a2, SETS1 | USESSP }, /* stc r2_bank,rn */
1675 { 0x00b2, SETS1 | USESSP }, /* stc r3_bank,rn */
1676 { 0x00c2, SETS1 | USESSP }, /* stc r4_bank,rn */
1677 { 0x00d2, SETS1 | USESSP }, /* stc r5_bank,rn */
1678 { 0x00e2, SETS1 | USESSP }, /* stc r6_bank,rn */
1679 { 0x00f2, SETS1 | USESSP } /* stc r7_bank,rn */
d4845d57 1680#endif
252b5132
RH		 1681
1682static const struct sh_opcode sh_opcode02[] =
1683{
d4845d57 1684 { 0x0002, SETS1 | USESSP }, /* stc <special_reg>,rn */
252b5132
RH		 1685 { 0x0004, STORE | USES1 | USES2 | USESR0 }, /* mov.b rm,@(r0,rn) */
1686 { 0x0005, STORE | USES1 | USES2 | USESR0 }, /* mov.w rm,@(r0,rn) */
1687 { 0x0006, STORE | USES1 | USES2 | USESR0 }, /* mov.l rm,@(r0,rn) */
1688 { 0x0007, SETSSP | USES1 | USES2 }, /* mul.l rm,rn */
1689 { 0x000c, LOAD | SETS1 | USES2 | USESR0 }, /* mov.b @(r0,rm),rn */
1690 { 0x000d, LOAD | SETS1 | USES2 | USESR0 }, /* mov.w @(r0,rm),rn */
1691 { 0x000e, LOAD | SETS1 | USES2 | USESR0 }, /* mov.l @(r0,rm),rn */
1692 { 0x000f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.l @rm+,@rn+ */
1693};
1694
1695static const struct sh_minor_opcode sh_opcode0[] =
1696{
1697 { MAP (sh_opcode00), 0xffff },
1698 { MAP (sh_opcode01), 0xf0ff },
1699 { MAP (sh_opcode02), 0xf00f }
1700};
1701
1702static const struct sh_opcode sh_opcode10[] =
1703{
1704 { 0x1000, STORE | USES1 | USES2 } /* mov.l rm,@(disp,rn) */
1705};
1706
1707static const struct sh_minor_opcode sh_opcode1[] =
1708{
1709 { MAP (sh_opcode10), 0xf000 }
1710};
1711
1712static const struct sh_opcode sh_opcode20[] =
1713{
1714 { 0x2000, STORE | USES1 | USES2 }, /* mov.b rm,@rn */
1715 { 0x2001, STORE | USES1 | USES2 }, /* mov.w rm,@rn */
1716 { 0x2002, STORE | USES1 | USES2 }, /* mov.l rm,@rn */
1717 { 0x2004, STORE | SETS1 | USES1 | USES2 }, /* mov.b rm,@-rn */
1718 { 0x2005, STORE | SETS1 | USES1 | USES2 }, /* mov.w rm,@-rn */
1719 { 0x2006, STORE | SETS1 | USES1 | USES2 }, /* mov.l rm,@-rn */
1720 { 0x2007, SETSSP | USES1 | USES2 | USESSP }, /* div0s */
1721 { 0x2008, SETSSP | USES1 | USES2 }, /* tst rm,rn */
1722 { 0x2009, SETS1 | USES1 | USES2 }, /* and rm,rn */
1723 { 0x200a, SETS1 | USES1 | USES2 }, /* xor rm,rn */
1724 { 0x200b, SETS1 | USES1 | USES2 }, /* or rm,rn */
1725 { 0x200c, SETSSP | USES1 | USES2 }, /* cmp/str rm,rn */
1726 { 0x200d, SETS1 | USES1 | USES2 }, /* xtrct rm,rn */
1727 { 0x200e, SETSSP | USES1 | USES2 }, /* mulu.w rm,rn */
1728 { 0x200f, SETSSP | USES1 | USES2 } /* muls.w rm,rn */
1729};
1730
1731static const struct sh_minor_opcode sh_opcode2[] =
1732{
1733 { MAP (sh_opcode20), 0xf00f }
1734};
1735
1736static const struct sh_opcode sh_opcode30[] =
1737{
1738 { 0x3000, SETSSP | USES1 | USES2 }, /* cmp/eq rm,rn */
1739 { 0x3002, SETSSP | USES1 | USES2 }, /* cmp/hs rm,rn */
1740 { 0x3003, SETSSP | USES1 | USES2 }, /* cmp/ge rm,rn */
1741 { 0x3004, SETSSP | USESSP | USES1 | USES2 }, /* div1 rm,rn */
1742 { 0x3005, SETSSP | USES1 | USES2 }, /* dmulu.l rm,rn */
1743 { 0x3006, SETSSP | USES1 | USES2 }, /* cmp/hi rm,rn */
1744 { 0x3007, SETSSP | USES1 | USES2 }, /* cmp/gt rm,rn */
1745 { 0x3008, SETS1 | USES1 | USES2 }, /* sub rm,rn */
1746 { 0x300a, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* subc rm,rn */
1747 { 0x300b, SETS1 | SETSSP | USES1 | USES2 }, /* subv rm,rn */
1748 { 0x300c, SETS1 | USES1 | USES2 }, /* add rm,rn */
1749 { 0x300d, SETSSP | USES1 | USES2 }, /* dmuls.l rm,rn */
1750 { 0x300e, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* addc rm,rn */
1751 { 0x300f, SETS1 | SETSSP | USES1 | USES2 } /* addv rm,rn */
1752};
1753
1754static const struct sh_minor_opcode sh_opcode3[] =
1755{
1756 { MAP (sh_opcode30), 0xf00f }
1757};
1758
1759static const struct sh_opcode sh_opcode40[] =
1760{
1761 { 0x4000, SETS1 | SETSSP | USES1 }, /* shll rn */
1762 { 0x4001, SETS1 | SETSSP | USES1 }, /* shlr rn */
1763 { 0x4002, STORE | SETS1 | USES1 | USESSP }, /* sts.l mach,@-rn */
252b5132
RH		 1764 { 0x4004, SETS1 | SETSSP | USES1 }, /* rotl rn */
1765 { 0x4005, SETS1 | SETSSP | USES1 }, /* rotr rn */
1766 { 0x4006, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,mach */
252b5132
RH		 1767 { 0x4008, SETS1 | USES1 }, /* shll2 rn */
1768 { 0x4009, SETS1 | USES1 }, /* shlr2 rn */
1769 { 0x400a, SETSSP | USES1 }, /* lds rm,mach */
1770 { 0x400b, BRANCH | DELAY | USES1 }, /* jsr @rn */
252b5132
RH		 1771 { 0x4010, SETS1 | SETSSP | USES1 }, /* dt rn */
1772 { 0x4011, SETSSP | USES1 }, /* cmp/pz rn */
1773 { 0x4012, STORE | SETS1 | USES1 | USESSP }, /* sts.l macl,@-rn */
d4845d57 1774 { 0x4014, SETSSP | USES1 }, /* setrc rm */
252b5132
RH		 1775 { 0x4015, SETSSP | USES1 }, /* cmp/pl rn */
1776 { 0x4016, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,macl */
252b5132
RH		 1777 { 0x4018, SETS1 | USES1 }, /* shll8 rn */
1778 { 0x4019, SETS1 | USES1 }, /* shlr8 rn */
1779 { 0x401a, SETSSP | USES1 }, /* lds rm,macl */
1780 { 0x401b, LOAD | SETSSP | USES1 }, /* tas.b @rn */
252b5132
RH		 1781 { 0x4020, SETS1 | SETSSP | USES1 }, /* shal rn */
1782 { 0x4021, SETS1 | SETSSP | USES1 }, /* shar rn */
1783 { 0x4022, STORE | SETS1 | USES1 | USESSP }, /* sts.l pr,@-rn */
252b5132
RH		 1784 { 0x4024, SETS1 | SETSSP | USES1 | USESSP }, /* rotcl rn */
1785 { 0x4025, SETS1 | SETSSP | USES1 | USESSP }, /* rotcr rn */
1786 { 0x4026, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,pr */
252b5132
RH		 1787 { 0x4028, SETS1 | USES1 }, /* shll16 rn */
1788 { 0x4029, SETS1 | USES1 }, /* shlr16 rn */
1789 { 0x402a, SETSSP | USES1 }, /* lds rm,pr */
1790 { 0x402b, BRANCH | DELAY | USES1 }, /* jmp @rn */
d4845d57
JR		 1791 { 0x4052, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpul,@-rn */
1792 { 0x4056, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpul */
1793 { 0x405a, SETSSP | USES1 }, /* lds.l rm,fpul */
1794 { 0x4062, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpscr / dsr,@-rn */
1795 { 0x4066, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpscr / dsr */
1796 { 0x406a, SETSSP | USES1 }, /* lds rm,fpscr / lds rm,dsr */
1797 { 0x4072, STORE | SETS1 | USES1 | USESSP }, /* sts.l a0,@-rn */
1798 { 0x4076, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,a0 */
1799 { 0x407a, SETSSP | USES1 }, /* lds.l rm,a0 */
1800 { 0x4082, STORE | SETS1 | USES1 | USESSP }, /* sts.l x0,@-rn */
1801 { 0x4086, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x0 */
1802 { 0x408a, SETSSP | USES1 }, /* lds.l rm,x0 */
1803 { 0x4092, STORE | SETS1 | USES1 | USESSP }, /* sts.l x1,@-rn */
1804 { 0x4096, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x1 */
1805 { 0x409a, SETSSP | USES1 }, /* lds.l rm,x1 */
1806 { 0x40a2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y0,@-rn */
1807 { 0x40a6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y0 */
1808 { 0x40aa, SETSSP | USES1 }, /* lds.l rm,y0 */
1809 { 0x40b2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y1,@-rn */
1810 { 0x40b6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y1 */
1811 { 0x40ba, SETSSP | USES1 } /* lds.l rm,y1 */
1812#if 0 /* These groups sixteen insns can be
1813 handled with one table entry each below. */
1814 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l sr,@-rn */
1815 { 0x4013, STORE | SETS1 | USES1 | USESSP }, /* stc.l gbr,@-rn */
1816 { 0x4023, STORE | SETS1 | USES1 | USESSP }, /* stc.l vbr,@-rn */
252b5132 1817 { 0x4033, STORE | SETS1 | USES1 | USESSP }, /* stc.l ssr,@-rn */
252b5132 1818 { 0x4043, STORE | SETS1 | USES1 | USESSP }, /* stc.l spc,@-rn */
d4845d57
JR		 1819 { 0x4053, STORE | SETS1 | USES1 | USESSP }, /* stc.l mod,@-rn */
1820 { 0x4063, STORE | SETS1 | USES1 | USESSP }, /* stc.l rs,@-rn */
1821 { 0x4073, STORE | SETS1 | USES1 | USESSP }, /* stc.l re,@-rn */
1822 { 0x4083, STORE | SETS1 | USES1 | USESSP }, /* stc.l r0_bank,@-rn */
1823 ..
1824 { 0x40f3, STORE | SETS1 | USES1 | USESSP }, /* stc.l r7_bank,@-rn */
1825
1826 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,sr */
1827 { 0x4017, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,gbr */
1828 { 0x4027, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,vbr */
1829 { 0x4037, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,ssr */
252b5132 1830 { 0x4047, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,spc */
d4845d57
JR		 1831 { 0x4057, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,mod */
1832 { 0x4067, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,rs */
1833 { 0x4077, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,re */
1834 { 0x4087, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,r0_bank */
1835 ..
1836 { 0x40f7, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,r7_bank */
1837
1838 { 0x400e, SETSSP | USES1 }, /* ldc rm,sr */
1839 { 0x401e, SETSSP | USES1 }, /* ldc rm,gbr */
1840 { 0x402e, SETSSP | USES1 }, /* ldc rm,vbr */
1841 { 0x403e, SETSSP | USES1 }, /* ldc rm,ssr */
252b5132 1842 { 0x404e, SETSSP | USES1 }, /* ldc rm,spc */
d4845d57
JR		 1843 { 0x405e, SETSSP | USES1 }, /* ldc rm,mod */
1844 { 0x406e, SETSSP | USES1 }, /* ldc rm,rs */
1845 { 0x407e, SETSSP | USES1 } /* ldc rm,re */
1846 { 0x408e, SETSSP | USES1 } /* ldc rm,r0_bank */
1847 ..
1848 { 0x40fe, SETSSP | USES1 } /* ldc rm,r7_bank */
1849#endif
252b5132
RH		 1850};
1851
1852static const struct sh_opcode sh_opcode41[] =
1853{
d4845d57
JR		 1854 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l <special_reg>,@-rn */
1855 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,<special_reg> */
1856 { 0x400c, SETS1 | USES1 | USES2 }, /* shad rm,rn */
1857 { 0x400d, SETS1 | USES1 | USES2 }, /* shld rm,rn */
1858 { 0x400e, SETSSP | USES1 }, /* ldc rm,<special_reg> */
252b5132
RH		 1859 { 0x400f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.w @rm+,@rn+ */
1860};
1861
1862static const struct sh_minor_opcode sh_opcode4[] =
1863{
1864 { MAP (sh_opcode40), 0xf0ff },
d4845d57 1865 { MAP (sh_opcode41), 0xf00f }
252b5132
RH		 1866};
1867
1868static const struct sh_opcode sh_opcode50[] =
1869{
1870 { 0x5000, LOAD | SETS1 | USES2 } /* mov.l @(disp,rm),rn */
1871};
1872
1873static const struct sh_minor_opcode sh_opcode5[] =
1874{
1875 { MAP (sh_opcode50), 0xf000 }
1876};
1877
1878static const struct sh_opcode sh_opcode60[] =
1879{
1880 { 0x6000, LOAD | SETS1 | USES2 }, /* mov.b @rm,rn */
1881 { 0x6001, LOAD | SETS1 | USES2 }, /* mov.w @rm,rn */
1882 { 0x6002, LOAD | SETS1 | USES2 }, /* mov.l @rm,rn */
1883 { 0x6003, SETS1 | USES2 }, /* mov rm,rn */
1884 { 0x6004, LOAD | SETS1 | SETS2 | USES2 }, /* mov.b @rm+,rn */
1885 { 0x6005, LOAD | SETS1 | SETS2 | USES2 }, /* mov.w @rm+,rn */
1886 { 0x6006, LOAD | SETS1 | SETS2 | USES2 }, /* mov.l @rm+,rn */
1887 { 0x6007, SETS1 | USES2 }, /* not rm,rn */
1888 { 0x6008, SETS1 | USES2 }, /* swap.b rm,rn */
1889 { 0x6009, SETS1 | USES2 }, /* swap.w rm,rn */
1890 { 0x600a, SETS1 | SETSSP | USES2 | USESSP }, /* negc rm,rn */
1891 { 0x600b, SETS1 | USES2 }, /* neg rm,rn */
1892 { 0x600c, SETS1 | USES2 }, /* extu.b rm,rn */
1893 { 0x600d, SETS1 | USES2 }, /* extu.w rm,rn */
1894 { 0x600e, SETS1 | USES2 }, /* exts.b rm,rn */
1895 { 0x600f, SETS1 | USES2 } /* exts.w rm,rn */
1896};
1897
1898static const struct sh_minor_opcode sh_opcode6[] =
1899{
1900 { MAP (sh_opcode60), 0xf00f }
1901};
1902
1903static const struct sh_opcode sh_opcode70[] =
1904{
1905 { 0x7000, SETS1 | USES1 } /* add #imm,rn */
1906};
1907
1908static const struct sh_minor_opcode sh_opcode7[] =
1909{
1910 { MAP (sh_opcode70), 0xf000 }
1911};
1912
1913static const struct sh_opcode sh_opcode80[] =
1914{
1915 { 0x8000, STORE | USES2 | USESR0 }, /* mov.b r0,@(disp,rn) */
1916 { 0x8100, STORE | USES2 | USESR0 }, /* mov.w r0,@(disp,rn) */
d4845d57 1917 { 0x8200, SETSSP }, /* setrc #imm */
252b5132
RH		 1918 { 0x8400, LOAD | SETSR0 | USES2 }, /* mov.b @(disp,rm),r0 */
1919 { 0x8500, LOAD | SETSR0 | USES2 }, /* mov.w @(disp,rn),r0 */
1920 { 0x8800, SETSSP | USESR0 }, /* cmp/eq #imm,r0 */
1921 { 0x8900, BRANCH | USESSP }, /* bt label */
1922 { 0x8b00, BRANCH | USESSP }, /* bf label */
d4845d57 1923 { 0x8c00, SETSSP }, /* ldrs @(disp,pc) */
252b5132 1924 { 0x8d00, BRANCH | DELAY | USESSP }, /* bt/s label */
d4845d57 1925 { 0x8e00, SETSSP }, /* ldre @(disp,pc) */
252b5132
RH		 1926 { 0x8f00, BRANCH | DELAY | USESSP } /* bf/s label */
1927};
1928
1929static const struct sh_minor_opcode sh_opcode8[] =
1930{
1931 { MAP (sh_opcode80), 0xff00 }
1932};
1933
1934static const struct sh_opcode sh_opcode90[] =
1935{
1936 { 0x9000, LOAD | SETS1 } /* mov.w @(disp,pc),rn */
1937};
1938
1939static const struct sh_minor_opcode sh_opcode9[] =
1940{
1941 { MAP (sh_opcode90), 0xf000 }
1942};
1943
1944static const struct sh_opcode sh_opcodea0[] =
1945{
1946 { 0xa000, BRANCH | DELAY } /* bra label */
1947};
1948
1949static const struct sh_minor_opcode sh_opcodea[] =
1950{
1951 { MAP (sh_opcodea0), 0xf000 }
1952};
1953
1954static const struct sh_opcode sh_opcodeb0[] =
1955{
1956 { 0xb000, BRANCH | DELAY } /* bsr label */
1957};
1958
1959static const struct sh_minor_opcode sh_opcodeb[] =
1960{
1961 { MAP (sh_opcodeb0), 0xf000 }
1962};
1963
1964static const struct sh_opcode sh_opcodec0[] =
1965{
1966 { 0xc000, STORE | USESR0 | USESSP }, /* mov.b r0,@(disp,gbr) */
1967 { 0xc100, STORE | USESR0 | USESSP }, /* mov.w r0,@(disp,gbr) */
1968 { 0xc200, STORE | USESR0 | USESSP }, /* mov.l r0,@(disp,gbr) */
1969 { 0xc300, BRANCH | USESSP }, /* trapa #imm */
1970 { 0xc400, LOAD | SETSR0 | USESSP }, /* mov.b @(disp,gbr),r0 */
1971 { 0xc500, LOAD | SETSR0 | USESSP }, /* mov.w @(disp,gbr),r0 */
1972 { 0xc600, LOAD | SETSR0 | USESSP }, /* mov.l @(disp,gbr),r0 */
1973 { 0xc700, SETSR0 }, /* mova @(disp,pc),r0 */
1974 { 0xc800, SETSSP | USESR0 }, /* tst #imm,r0 */
1975 { 0xc900, SETSR0 | USESR0 }, /* and #imm,r0 */
1976 { 0xca00, SETSR0 | USESR0 }, /* xor #imm,r0 */
1977 { 0xcb00, SETSR0 | USESR0 }, /* or #imm,r0 */
1978 { 0xcc00, LOAD | SETSSP | USESR0 | USESSP }, /* tst.b #imm,@(r0,gbr) */
1979 { 0xcd00, LOAD | STORE | USESR0 | USESSP }, /* and.b #imm,@(r0,gbr) */
1980 { 0xce00, LOAD | STORE | USESR0 | USESSP }, /* xor.b #imm,@(r0,gbr) */
1981 { 0xcf00, LOAD | STORE | USESR0 | USESSP } /* or.b #imm,@(r0,gbr) */
1982};
1983
1984static const struct sh_minor_opcode sh_opcodec[] =
1985{
1986 { MAP (sh_opcodec0), 0xff00 }
1987};
1988
1989static const struct sh_opcode sh_opcoded0[] =
1990{
1991 { 0xd000, LOAD | SETS1 } /* mov.l @(disp,pc),rn */
1992};
1993
1994static const struct sh_minor_opcode sh_opcoded[] =
1995{
1996 { MAP (sh_opcoded0), 0xf000 }
1997};
1998
1999static const struct sh_opcode sh_opcodee0[] =
2000{
2001 { 0xe000, SETS1 } /* mov #imm,rn */
2002};
2003
2004static const struct sh_minor_opcode sh_opcodee[] =
2005{
2006 { MAP (sh_opcodee0), 0xf000 }
2007};
2008
2009static const struct sh_opcode sh_opcodef0[] =
2010{
2011 { 0xf000, SETSF1 | USESF1 | USESF2 }, /* fadd fm,fn */
2012 { 0xf001, SETSF1 | USESF1 | USESF2 }, /* fsub fm,fn */
2013 { 0xf002, SETSF1 | USESF1 | USESF2 }, /* fmul fm,fn */
2014 { 0xf003, SETSF1 | USESF1 | USESF2 }, /* fdiv fm,fn */
2015 { 0xf004, SETSSP | USESF1 | USESF2 }, /* fcmp/eq fm,fn */
2016 { 0xf005, SETSSP | USESF1 | USESF2 }, /* fcmp/gt fm,fn */
2017 { 0xf006, LOAD | SETSF1 | USES2 | USESR0 }, /* fmov.s @(r0,rm),fn */
2018 { 0xf007, STORE | USES1 | USESF2 | USESR0 }, /* fmov.s fm,@(r0,rn) */
2019 { 0xf008, LOAD | SETSF1 | USES2 }, /* fmov.s @rm,fn */
2020 { 0xf009, LOAD | SETS2 | SETSF1 | USES2 }, /* fmov.s @rm+,fn */
2021 { 0xf00a, STORE | USES1 | USESF2 }, /* fmov.s fm,@rn */
2022 { 0xf00b, STORE | SETS1 | USES1 | USESF2 }, /* fmov.s fm,@-rn */
2023 { 0xf00c, SETSF1 | USESF2 }, /* fmov fm,fn */
2024 { 0xf00e, SETSF1 | USESF1 | USESF2 | USESF0 } /* fmac f0,fm,fn */
2025};
2026
2027static const struct sh_opcode sh_opcodef1[] =
2028{
2029 { 0xf00d, SETSF1 | USESSP }, /* fsts fpul,fn */
2030 { 0xf01d, SETSSP | USESF1 }, /* flds fn,fpul */
2031 { 0xf02d, SETSF1 | USESSP }, /* float fpul,fn */
2032 { 0xf03d, SETSSP | USESF1 }, /* ftrc fn,fpul */
2033 { 0xf04d, SETSF1 | USESF1 }, /* fneg fn */
2034 { 0xf05d, SETSF1 | USESF1 }, /* fabs fn */
2035 { 0xf06d, SETSF1 | USESF1 }, /* fsqrt fn */
2036 { 0xf07d, SETSSP | USESF1 }, /* ftst/nan fn */
2037 { 0xf08d, SETSF1 }, /* fldi0 fn */
2038 { 0xf09d, SETSF1 } /* fldi1 fn */
2039};
2040
2041static const struct sh_minor_opcode sh_opcodef[] =
2042{
2043 { MAP (sh_opcodef0), 0xf00f },
2044 { MAP (sh_opcodef1), 0xf0ff }
2045};
2046
d4845d57 2047static struct sh_major_opcode sh_opcodes[] =
252b5132
RH		 2048{
2049 { MAP (sh_opcode0) },
2050 { MAP (sh_opcode1) },
2051 { MAP (sh_opcode2) },
2052 { MAP (sh_opcode3) },
2053 { MAP (sh_opcode4) },
2054 { MAP (sh_opcode5) },
2055 { MAP (sh_opcode6) },
2056 { MAP (sh_opcode7) },
2057 { MAP (sh_opcode8) },
2058 { MAP (sh_opcode9) },
2059 { MAP (sh_opcodea) },
2060 { MAP (sh_opcodeb) },
2061 { MAP (sh_opcodec) },
2062 { MAP (sh_opcoded) },
2063 { MAP (sh_opcodee) },
2064 { MAP (sh_opcodef) }
2065};
2066
d4845d57
JR		 2067/* The double data transfer / parallel processing insns are not
2068 described here. This will cause sh_align_load_span to leave them alone. */
2069
2070static const struct sh_opcode sh_dsp_opcodef0[] =
2071{
2072 { 0xf400, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @-as,ds */
2073 { 0xf401, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@-as */
2074 { 0xf404, USESAS | LOAD | SETSSP }, /* movs.x @as,ds */
2075 { 0xf405, USESAS | STORE | USESSP }, /* movs.x ds,@as */
2076 { 0xf408, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @as+,ds */
2077 { 0xf409, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@as+ */
2078 { 0xf40c, USESAS | SETSAS | LOAD | SETSSP | USESR8 }, /* movs.x @as+r8,ds */
2079 { 0xf40d, USESAS | SETSAS | STORE | USESSP | USESR8 } /* movs.x ds,@as+r8 */
2080};
2081
2082static const struct sh_minor_opcode sh_dsp_opcodef[] =
2083{
2084 { MAP (sh_dsp_opcodef0), 0xfc0d }
2085};
2086
252b5132
RH		 2087/* Given an instruction, return a pointer to the corresponding
2088 sh_opcode structure. Return NULL if the instruction is not
2089 recognized. */
2090
2091static const struct sh_opcode *
2092sh_insn_info (insn)
2093 unsigned int insn;
2094{
2095 const struct sh_major_opcode *maj;
2096 const struct sh_minor_opcode *min, *minend;
2097
2098 maj = &sh_opcodes[(insn & 0xf000) >> 12];
2099 min = maj->minor_opcodes;
2100 minend = min + maj->count;
2101 for (; min < minend; min++)
2102 {
2103 unsigned int l;
2104 const struct sh_opcode *op, *opend;
2105
2106 l = insn & min->mask;
2107 op = min->opcodes;
2108 opend = op + min->count;
2109
2110 /* Since the opcodes tables are sorted, we could use a binary
2111 search here if the count were above some cutoff value. */
2112 for (; op < opend; op++)
2113 if (op->opcode == l)
2114 return op;
2115 }
2116
cbfe05c4 2117 return NULL;
252b5132
RH		 2118}
2119
84dcfba7
JR		 2120/* See whether an instruction uses or sets a general purpose register */
2121
b34976b6 2122static bfd_boolean
84dcfba7
JR		 2123sh_insn_uses_or_sets_reg (insn, op, reg)
2124 unsigned int insn;
2125 const struct sh_opcode *op;
2126 unsigned int reg;
2127{
2128 if (sh_insn_uses_reg (insn, op, reg))
b34976b6 2129 return TRUE;
84dcfba7
JR		 2130
2131 return sh_insn_sets_reg (insn, op, reg);
2132}
2133
252b5132
RH		 2134/* See whether an instruction uses a general purpose register. */
2135
b34976b6 2136static bfd_boolean
252b5132
RH		 2137sh_insn_uses_reg (insn, op, reg)
2138 unsigned int insn;
2139 const struct sh_opcode *op;
2140 unsigned int reg;
2141{
2142 unsigned int f;
2143
2144 f = op->flags;
2145
2146 if ((f & USES1) != 0
84dcfba7 2147 && USES1_REG (insn) == reg)
b34976b6 2148 return TRUE;
252b5132 2149 if ((f & USES2) != 0
84dcfba7 2150 && USES2_REG (insn) == reg)
b34976b6 2151 return TRUE;
252b5132
RH		 2152 if ((f & USESR0) != 0
2153 && reg == 0)
b34976b6 2154 return TRUE;
d4845d57 2155 if ((f & USESAS) && reg == USESAS_REG (insn))
b34976b6 2156 return TRUE;
d4845d57 2157 if ((f & USESR8) && reg == 8)
b34976b6 2158 return TRUE;
252b5132 2159
b34976b6 2160 return FALSE;
252b5132 2161}
17505c5c 2162
84dcfba7
JR		 2163/* See whether an instruction sets a general purpose register. */
2164
b34976b6 2165static bfd_boolean
84dcfba7
JR		 2166sh_insn_sets_reg (insn, op, reg)
2167 unsigned int insn;
2168 const struct sh_opcode *op;
2169 unsigned int reg;
2170{
2171 unsigned int f;
2172
2173 f = op->flags;
2174
2175 if ((f & SETS1) != 0
2176 && SETS1_REG (insn) == reg)
b34976b6 2177 return TRUE;
84dcfba7
JR		 2178 if ((f & SETS2) != 0
2179 && SETS2_REG (insn) == reg)
b34976b6 2180 return TRUE;
84dcfba7
JR		 2181 if ((f & SETSR0) != 0
2182 && reg == 0)
b34976b6 2183 return TRUE;
d4845d57 2184 if ((f & SETSAS) && reg == SETSAS_REG (insn))
b34976b6 2185 return TRUE;
84dcfba7 2186
b34976b6 2187 return FALSE;
84dcfba7
JR		 2188}
2189
2190/* See whether an instruction uses or sets a floating point register */
2191
b34976b6 2192static bfd_boolean
84dcfba7
JR		 2193sh_insn_uses_or_sets_freg (insn, op, reg)
2194 unsigned int insn;
2195 const struct sh_opcode *op;
2196 unsigned int reg;
2197{
2198 if (sh_insn_uses_freg (insn, op, reg))
b34976b6 2199 return TRUE;
84dcfba7
JR		 2200
2201 return sh_insn_sets_freg (insn, op, reg);
2202}
252b5132
RH		 2203
2204/* See whether an instruction uses a floating point register. */
2205
b34976b6 2206static bfd_boolean
252b5132
RH		 2207sh_insn_uses_freg (insn, op, freg)
2208 unsigned int insn;
2209 const struct sh_opcode *op;
2210 unsigned int freg;
2211{
2212 unsigned int f;
2213
2214 f = op->flags;
2215
2216 /* We can't tell if this is a double-precision insn, so just play safe
2217 and assume that it might be. So not only have we test FREG against
2218 itself, but also even FREG against FREG+1 - if the using insn uses
2219 just the low part of a double precision value - but also an odd
2220 FREG against FREG-1 - if the setting insn sets just the low part
2221 of a double precision value.
2222 So what this all boils down to is that we have to ignore the lowest
2223 bit of the register number. */
cbfe05c4 2224
252b5132 2225 if ((f & USESF1) != 0
84dcfba7 2226 && (USESF1_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2227 return TRUE;
252b5132 2228 if ((f & USESF2) != 0
84dcfba7 2229 && (USESF2_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2230 return TRUE;
252b5132
RH		 2231 if ((f & USESF0) != 0
2232 && freg == 0)
b34976b6 2233 return TRUE;
252b5132 2234
b34976b6 2235 return FALSE;
252b5132
RH		 2236}
2237
84dcfba7
JR		 2238/* See whether an instruction sets a floating point register. */
2239
b34976b6 2240static bfd_boolean
84dcfba7
JR		 2241sh_insn_sets_freg (insn, op, freg)
2242 unsigned int insn;
2243 const struct sh_opcode *op;
2244 unsigned int freg;
2245{
2246 unsigned int f;
2247
2248 f = op->flags;
2249
2250 /* We can't tell if this is a double-precision insn, so just play safe
2251 and assume that it might be. So not only have we test FREG against
2252 itself, but also even FREG against FREG+1 - if the using insn uses
2253 just the low part of a double precision value - but also an odd
2254 FREG against FREG-1 - if the setting insn sets just the low part
2255 of a double precision value.
2256 So what this all boils down to is that we have to ignore the lowest
2257 bit of the register number. */
cbfe05c4 2258
84dcfba7
JR		 2259 if ((f & SETSF1) != 0
2260 && (SETSF1_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2261 return TRUE;
84dcfba7 2262
b34976b6 2263 return FALSE;
84dcfba7
JR		 2264}
2265
252b5132
RH		 2266/* See whether instructions I1 and I2 conflict, assuming I1 comes
2267 before I2. OP1 and OP2 are the corresponding sh_opcode structures.
b34976b6 2268 This should return TRUE if there is a conflict, or FALSE if the
252b5132
RH		 2269 instructions can be swapped safely. */
2270
b34976b6 2271static bfd_boolean
252b5132
RH		 2272sh_insns_conflict (i1, op1, i2, op2)
2273 unsigned int i1;
2274 const struct sh_opcode *op1;
2275 unsigned int i2;
2276 const struct sh_opcode *op2;
2277{
2278 unsigned int f1, f2;
2279
2280 f1 = op1->flags;
2281 f2 = op2->flags;
2282
2283 /* Load of fpscr conflicts with floating point operations.
2284 FIXME: shouldn't test raw opcodes here. */
2285 if (((i1 & 0xf0ff) == 0x4066 && (i2 & 0xf000) == 0xf000)
2286 || ((i2 & 0xf0ff) == 0x4066 && (i1 & 0xf000) == 0xf000))
b34976b6 2287 return TRUE;
252b5132
RH		 2288
2289 if ((f1 & (BRANCH | DELAY)) != 0
2290 || (f2 & (BRANCH | DELAY)) != 0)
b34976b6 2291 return TRUE;
252b5132 2292
84dcfba7
JR		 2293 if (((f1 | f2) & SETSSP)
2294 && (f1 & (SETSSP | USESSP))
2295 && (f2 & (SETSSP | USESSP)))
b34976b6 2296 return TRUE;
252b5132
RH		 2297
2298 if ((f1 & SETS1) != 0
84dcfba7 2299 && sh_insn_uses_or_sets_reg (i2, op2, SETS1_REG (i1)))
b34976b6 2300 return TRUE;
252b5132 2301 if ((f1 & SETS2) != 0
84dcfba7 2302 && sh_insn_uses_or_sets_reg (i2, op2, SETS2_REG (i1)))
b34976b6 2303 return TRUE;
252b5132 2304 if ((f1 & SETSR0) != 0
84dcfba7 2305 && sh_insn_uses_or_sets_reg (i2, op2, 0))
b34976b6 2306 return TRUE;
d4845d57
JR		 2307 if ((f1 & SETSAS)
2308 && sh_insn_uses_or_sets_reg (i2, op2, SETSAS_REG (i1)))
b34976b6 2309 return TRUE;
252b5132 2310 if ((f1 & SETSF1) != 0
84dcfba7 2311 && sh_insn_uses_or_sets_freg (i2, op2, SETSF1_REG (i1)))
b34976b6 2312 return TRUE;
252b5132
RH		 2313
2314 if ((f2 & SETS1) != 0
84dcfba7 2315 && sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2)))
b34976b6 2316 return TRUE;
252b5132 2317 if ((f2 & SETS2) != 0
84dcfba7 2318 && sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2)))
b34976b6 2319 return TRUE;
252b5132 2320 if ((f2 & SETSR0) != 0
84dcfba7 2321 && sh_insn_uses_or_sets_reg (i1, op1, 0))
b34976b6 2322 return TRUE;
d4845d57
JR		 2323 if ((f2 & SETSAS)
2324 && sh_insn_uses_or_sets_reg (i1, op1, SETSAS_REG (i2)))
b34976b6 2325 return TRUE;
252b5132 2326 if ((f2 & SETSF1) != 0
84dcfba7 2327 && sh_insn_uses_or_sets_freg (i1, op1, SETSF1_REG (i2)))
b34976b6 2328 return TRUE;
252b5132
RH		 2329
2330 /* The instructions do not conflict. */
b34976b6 2331 return FALSE;
252b5132
RH		 2332}
2333
2334/* I1 is a load instruction, and I2 is some other instruction. Return
b34976b6 2335 TRUE if I1 loads a register which I2 uses. */
252b5132 2336
b34976b6 2337static bfd_boolean
252b5132
RH		 2338sh_load_use (i1, op1, i2, op2)
2339 unsigned int i1;
2340 const struct sh_opcode *op1;
2341 unsigned int i2;
2342 const struct sh_opcode *op2;
2343{
2344 unsigned int f1;
2345
2346 f1 = op1->flags;
2347
2348 if ((f1 & LOAD) == 0)
b34976b6 2349 return FALSE;
252b5132
RH		 2350
2351 /* If both SETS1 and SETSSP are set, that means a load to a special
2352 register using postincrement addressing mode, which we don't care
2353 about here. */
2354 if ((f1 & SETS1) != 0
2355 && (f1 & SETSSP) == 0
2356 && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
b34976b6 2357 return TRUE;
252b5132
RH		 2358
2359 if ((f1 & SETSR0) != 0
2360 && sh_insn_uses_reg (i2, op2, 0))
b34976b6 2361 return TRUE;
252b5132
RH		 2362
2363 if ((f1 & SETSF1) != 0
2364 && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
b34976b6 2365 return TRUE;
252b5132 2366
b34976b6 2367 return FALSE;
252b5132
RH		 2368}
2369
2370/* Try to align loads and stores within a span of memory. This is
2371 called by both the ELF and the COFF sh targets. ABFD and SEC are
2372 the BFD and section we are examining. CONTENTS is the contents of
2373 the section. SWAP is the routine to call to swap two instructions.
2374 RELOCS is a pointer to the internal relocation information, to be
2375 passed to SWAP. PLABEL is a pointer to the current label in a
2376 sorted list of labels; LABEL_END is the end of the list. START and
2377 STOP are the range of memory to examine. If a swap is made,
b34976b6 2378 *PSWAPPED is set to TRUE. */
252b5132 2379
86033394
NC		 2380#ifdef COFF_WITH_PE
2381static
2382#endif
b34976b6 2383bfd_boolean
252b5132
RH		 2384_bfd_sh_align_load_span (abfd, sec, contents, swap, relocs,
2385 plabel, label_end, start, stop, pswapped)
2386 bfd *abfd;
2387 asection *sec;
2388 bfd_byte *contents;
b34976b6 2389 bfd_boolean (*swap) PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
252b5132
RH		 2390 PTR relocs;
2391 bfd_vma **plabel;
2392 bfd_vma *label_end;
2393 bfd_vma start;
2394 bfd_vma stop;
b34976b6 2395 bfd_boolean *pswapped;
252b5132 2396{
d4845d57
JR		 2397 int dsp = (abfd->arch_info->mach == bfd_mach_sh_dsp
2398 || abfd->arch_info->mach == bfd_mach_sh3_dsp);
252b5132
RH		 2399 bfd_vma i;
2400
d4845d57
JR		 2401 /* The SH4 has a Harvard architecture, hence aligning loads is not
2402 desirable. In fact, it is counter-productive, since it interferes
2403 with the schedules generated by the compiler. */
2404 if (abfd->arch_info->mach == bfd_mach_sh4)
b34976b6 2405 return TRUE;
d4845d57
JR		 2406
2407 /* If we are linking sh[3]-dsp code, swap the FPU instructions for DSP
2408 instructions. */
2409 if (dsp)
2410 {
2411 sh_opcodes[0xf].minor_opcodes = sh_dsp_opcodef;
2412 sh_opcodes[0xf].count = sizeof sh_dsp_opcodef / sizeof sh_dsp_opcodef;
2413 }
2414
252b5132
RH		 2415 /* Instructions should be aligned on 2 byte boundaries. */
2416 if ((start & 1) == 1)
2417 ++start;
2418
2419 /* Now look through the unaligned addresses. */
2420 i = start;
2421 if ((i & 2) == 0)
2422 i += 2;
2423 for (; i < stop; i += 4)
2424 {
2425 unsigned int insn;
2426 const struct sh_opcode *op;
2427 unsigned int prev_insn = 0;
2428 const struct sh_opcode *prev_op = NULL;
2429
2430 insn = bfd_get_16 (abfd, contents + i);
2431 op = sh_insn_info (insn);
2432 if (op == NULL
2433 || (op->flags & (LOAD | STORE)) == 0)
2434 continue;
2435
2436 /* This is a load or store which is not on a four byte boundary. */
2437
2438 while (*plabel < label_end && **plabel < i)
2439 ++*plabel;
2440
2441 if (i > start)
2442 {
2443 prev_insn = bfd_get_16 (abfd, contents + i - 2);
d4845d57
JR		 2444 /* If INSN is the field b of a parallel processing insn, it is not
2445 a load / store after all. Note that the test here might mistake
2446 the field_b of a pcopy insn for the starting code of a parallel
2447 processing insn; this might miss a swapping opportunity, but at
2448 least we're on the safe side. */
2449 if (dsp && (prev_insn & 0xfc00) == 0xf800)
2450 continue;
2451
2452 /* Check if prev_insn is actually the field b of a parallel
2453 processing insn. Again, this can give a spurious match
2454 after a pcopy. */
2455 if (dsp && i - 2 > start)
2456 {
2457 unsigned pprev_insn = bfd_get_16 (abfd, contents + i - 4);
cbfe05c4 2458
d4845d57
JR		 2459 if ((pprev_insn & 0xfc00) == 0xf800)
2460 prev_op = NULL;
2461 else
2462 prev_op = sh_insn_info (prev_insn);
2463 }
2464 else
2465 prev_op = sh_insn_info (prev_insn);
252b5132
RH		 2466
2467 /* If the load/store instruction is in a delay slot, we
2468 can't swap. */
2469 if (prev_op == NULL
2470 || (prev_op->flags & DELAY) != 0)
2471 continue;
2472 }
2473 if (i > start
2474 && (*plabel >= label_end || **plabel != i)
2475 && prev_op != NULL
2476 && (prev_op->flags & (LOAD | STORE)) == 0
2477 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2478 {
b34976b6 2479 bfd_boolean ok;
252b5132
RH		 2480
2481 /* The load/store instruction does not have a label, and
2482 there is a previous instruction; PREV_INSN is not
2483 itself a load/store instruction, and PREV_INSN and
2484 INSN do not conflict. */
2485
b34976b6 2486 ok = TRUE;
252b5132
RH		 2487
2488 if (i >= start + 4)
2489 {
2490 unsigned int prev2_insn;
2491 const struct sh_opcode *prev2_op;
2492
2493 prev2_insn = bfd_get_16 (abfd, contents + i - 4);
2494 prev2_op = sh_insn_info (prev2_insn);
2495
2496 /* If the instruction before PREV_INSN has a delay
2497 slot--that is, PREV_INSN is in a delay slot--we
2498 can not swap. */
2499 if (prev2_op == NULL
2500 || (prev2_op->flags & DELAY) != 0)
b34976b6 2501 ok = FALSE;
252b5132
RH		 2502
2503 /* If the instruction before PREV_INSN is a load,
2504 and it sets a register which INSN uses, then
2505 putting INSN immediately after PREV_INSN will
2506 cause a pipeline bubble, so there is no point to
2507 making the swap. */
2508 if (ok
2509 && (prev2_op->flags & LOAD) != 0
2510 && sh_load_use (prev2_insn, prev2_op, insn, op))
b34976b6 2511 ok = FALSE;
252b5132
RH		 2512 }
2513
2514 if (ok)
2515 {
2516 if (! (*swap) (abfd, sec, relocs, contents, i - 2))
b34976b6
AM		 2517 return FALSE;
2518 *pswapped = TRUE;
252b5132
RH		 2519 continue;
2520 }
2521 }
2522
2523 while (*plabel < label_end && **plabel < i + 2)
2524 ++*plabel;
2525
2526 if (i + 2 < stop
2527 && (*plabel >= label_end || **plabel != i + 2))
2528 {
2529 unsigned int next_insn;
2530 const struct sh_opcode *next_op;
2531
2532 /* There is an instruction after the load/store
2533 instruction, and it does not have a label. */
2534 next_insn = bfd_get_16 (abfd, contents + i + 2);
2535 next_op = sh_insn_info (next_insn);
2536 if (next_op != NULL
2537 && (next_op->flags & (LOAD | STORE)) == 0
2538 && ! sh_insns_conflict (insn, op, next_insn, next_op))
2539 {
b34976b6 2540 bfd_boolean ok;
252b5132
RH		 2541
2542 /* NEXT_INSN is not itself a load/store instruction,
2543 and it does not conflict with INSN. */
2544
b34976b6 2545 ok = TRUE;
252b5132
RH		 2546
2547 /* If PREV_INSN is a load, and it sets a register
2548 which NEXT_INSN uses, then putting NEXT_INSN
2549 immediately after PREV_INSN will cause a pipeline
2550 bubble, so there is no reason to make this swap. */
2551 if (prev_op != NULL
2552 && (prev_op->flags & LOAD) != 0
2553 && sh_load_use (prev_insn, prev_op, next_insn, next_op))
b34976b6 2554 ok = FALSE;
252b5132
RH		 2555
2556 /* If INSN is a load, and it sets a register which
2557 the insn after NEXT_INSN uses, then doing the
2558 swap will cause a pipeline bubble, so there is no
2559 reason to make the swap. However, if the insn
2560 after NEXT_INSN is itself a load or store
2561 instruction, then it is misaligned, so
2562 optimistically hope that it will be swapped
2563 itself, and just live with the pipeline bubble if
2564 it isn't. */
2565 if (ok
2566 && i + 4 < stop
2567 && (op->flags & LOAD) != 0)
2568 {
2569 unsigned int next2_insn;
2570 const struct sh_opcode *next2_op;
2571
2572 next2_insn = bfd_get_16 (abfd, contents + i + 4);
2573 next2_op = sh_insn_info (next2_insn);
2574 if ((next2_op->flags & (LOAD | STORE)) == 0
2575 && sh_load_use (insn, op, next2_insn, next2_op))
b34976b6 2576 ok = FALSE;
252b5132
RH		 2577 }
2578
2579 if (ok)
2580 {
2581 if (! (*swap) (abfd, sec, relocs, contents, i))
b34976b6
AM		 2582 return FALSE;
2583 *pswapped = TRUE;
252b5132
RH		 2584 continue;
2585 }
2586 }
2587 }
2588 }
2589
b34976b6 2590 return TRUE;
252b5132 2591}
86033394 2592#endif /* not COFF_IMAGE_WITH_PE */
252b5132
RH		 2593
2594/* Look for loads and stores which we can align to four byte
2595 boundaries. See the longer comment above sh_relax_section for why
2596 this is desirable. This sets *PSWAPPED if some instruction was
2597 swapped. */
2598
b34976b6 2599static bfd_boolean
252b5132
RH		 2600sh_align_loads (abfd, sec, internal_relocs, contents, pswapped)
2601 bfd *abfd;
2602 asection *sec;
2603 struct internal_reloc *internal_relocs;
2604 bfd_byte *contents;
b34976b6 2605 bfd_boolean *pswapped;
252b5132
RH		 2606{
2607 struct internal_reloc *irel, *irelend;
2608 bfd_vma *labels = NULL;
2609 bfd_vma *label, *label_end;
dc810e39 2610 bfd_size_type amt;
252b5132 2611
b34976b6 2612 *pswapped = FALSE;
252b5132
RH		 2613
2614 irelend = internal_relocs + sec->reloc_count;
2615
2616 /* Get all the addresses with labels on them. */
dc810e39
AM		 2617 amt = (bfd_size_type) sec->reloc_count * sizeof (bfd_vma);
2618 labels = (bfd_vma *) bfd_malloc (amt);
252b5132
RH		 2619 if (labels == NULL)
2620 goto error_return;
2621 label_end = labels;
2622 for (irel = internal_relocs; irel < irelend; irel++)
2623 {
2624 if (irel->r_type == R_SH_LABEL)
2625 {
2626 *label_end = irel->r_vaddr - sec->vma;
2627 ++label_end;
2628 }
2629 }
2630
2631 /* Note that the assembler currently always outputs relocs in
2632 address order. If that ever changes, this code will need to sort
2633 the label values and the relocs. */
2634
2635 label = labels;
2636
2637 for (irel = internal_relocs; irel < irelend; irel++)
2638 {
2639 bfd_vma start, stop;
2640
2641 if (irel->r_type != R_SH_CODE)
2642 continue;
2643
2644 start = irel->r_vaddr - sec->vma;
2645
2646 for (irel++; irel < irelend; irel++)
2647 if (irel->r_type == R_SH_DATA)
2648 break;
2649 if (irel < irelend)
2650 stop = irel->r_vaddr - sec->vma;
2651 else
eea6121a 2652 stop = sec->size;
252b5132
RH		 2653
2654 if (! _bfd_sh_align_load_span (abfd, sec, contents, sh_swap_insns,
2655 (PTR) internal_relocs, &label,
2656 label_end, start, stop, pswapped))
2657 goto error_return;
2658 }
2659
2660 free (labels);
2661
b34976b6 2662 return TRUE;
252b5132
RH		 2663
2664 error_return:
2665 if (labels != NULL)
2666 free (labels);
b34976b6 2667 return FALSE;
252b5132
RH		 2668}
2669
2670/* Swap two SH instructions. */
2671
b34976b6 2672static bfd_boolean
252b5132
RH		 2673sh_swap_insns (abfd, sec, relocs, contents, addr)
2674 bfd *abfd;
2675 asection *sec;
2676 PTR relocs;
2677 bfd_byte *contents;
2678 bfd_vma addr;
2679{
2680 struct internal_reloc *internal_relocs = (struct internal_reloc *) relocs;
2681 unsigned short i1, i2;
2682 struct internal_reloc *irel, *irelend;
2683
2684 /* Swap the instructions themselves. */
2685 i1 = bfd_get_16 (abfd, contents + addr);
2686 i2 = bfd_get_16 (abfd, contents + addr + 2);
dc810e39
AM		 2687 bfd_put_16 (abfd, (bfd_vma) i2, contents + addr);
2688 bfd_put_16 (abfd, (bfd_vma) i1, contents + addr + 2);
252b5132
RH		 2689
2690 /* Adjust all reloc addresses. */
2691 irelend = internal_relocs + sec->reloc_count;
2692 for (irel = internal_relocs; irel < irelend; irel++)
2693 {
2694 int type, add;
2695
2696 /* There are a few special types of relocs that we don't want to
2697 adjust. These relocs do not apply to the instruction itself,
2698 but are only associated with the address. */
2699 type = irel->r_type;
2700 if (type == R_SH_ALIGN
2701 || type == R_SH_CODE
2702 || type == R_SH_DATA
2703 || type == R_SH_LABEL)
2704 continue;
2705
2706 /* If an R_SH_USES reloc points to one of the addresses being
2707 swapped, we must adjust it. It would be incorrect to do this
2708 for a jump, though, since we want to execute both
2709 instructions after the jump. (We have avoided swapping
2710 around a label, so the jump will not wind up executing an
2711 instruction it shouldn't). */
2712 if (type == R_SH_USES)
2713 {
2714 bfd_vma off;
2715
2716 off = irel->r_vaddr - sec->vma + 4 + irel->r_offset;
2717 if (off == addr)
2718 irel->r_offset += 2;
2719 else if (off == addr + 2)
2720 irel->r_offset -= 2;
2721 }
2722
2723 if (irel->r_vaddr - sec->vma == addr)
2724 {
2725 irel->r_vaddr += 2;
2726 add = -2;
2727 }
2728 else if (irel->r_vaddr - sec->vma == addr + 2)
2729 {
2730 irel->r_vaddr -= 2;
2731 add = 2;
2732 }
2733 else
2734 add = 0;
2735
2736 if (add != 0)
2737 {
2738 bfd_byte *loc;
2739 unsigned short insn, oinsn;
b34976b6 2740 bfd_boolean overflow;
252b5132
RH		 2741
2742 loc = contents + irel->r_vaddr - sec->vma;
b34976b6 2743 overflow = FALSE;
252b5132
RH		 2744 switch (type)
2745 {
2746 default:
2747 break;
2748
2749 case R_SH_PCDISP8BY2:
2750 case R_SH_PCRELIMM8BY2:
2751 insn = bfd_get_16 (abfd, loc);
2752 oinsn = insn;
2753 insn += add / 2;
2754 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 2755 overflow = TRUE;
dc810e39 2756 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2757 break;
2758
2759 case R_SH_PCDISP:
2760 insn = bfd_get_16 (abfd, loc);
2761 oinsn = insn;
2762 insn += add / 2;
2763 if ((oinsn & 0xf000) != (insn & 0xf000))
b34976b6 2764 overflow = TRUE;
dc810e39 2765 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2766 break;
2767
2768 case R_SH_PCRELIMM8BY4:
2769 /* This reloc ignores the least significant 3 bits of
2770 the program counter before adding in the offset.
2771 This means that if ADDR is at an even address, the
2772 swap will not affect the offset. If ADDR is an at an
2773 odd address, then the instruction will be crossing a
2774 four byte boundary, and must be adjusted. */
2775 if ((addr & 3) != 0)
2776 {
2777 insn = bfd_get_16 (abfd, loc);
2778 oinsn = insn;
2779 insn += add / 2;
2780 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 2781 overflow = TRUE;
dc810e39 2782 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2783 }
2784
2785 break;
2786 }
2787
2788 if (overflow)
2789 {
2790 ((*_bfd_error_handler)
2791 ("%s: 0x%lx: fatal: reloc overflow while relaxing",
8f615d07 2792 bfd_archive_filename (abfd), (unsigned long) irel->r_vaddr));
252b5132 2793 bfd_set_error (bfd_error_bad_value);
b34976b6 2794 return FALSE;
252b5132
RH		 2795 }
2796 }
2797 }
2798
b34976b6 2799 return TRUE;
252b5132
RH		 2800}
2801\f
2802/* This is a modification of _bfd_coff_generic_relocate_section, which
2803 will handle SH relaxing. */
2804
b34976b6 2805static bfd_boolean
252b5132
RH		 2806sh_relocate_section (output_bfd, info, input_bfd, input_section, contents,
2807 relocs, syms, sections)
5f771d47 2808 bfd *output_bfd ATTRIBUTE_UNUSED;
252b5132
RH		 2809 struct bfd_link_info *info;
2810 bfd *input_bfd;
2811 asection *input_section;
2812 bfd_byte *contents;
2813 struct internal_reloc *relocs;
2814 struct internal_syment *syms;
2815 asection **sections;
2816{
2817 struct internal_reloc *rel;
2818 struct internal_reloc *relend;
2819
2820 rel = relocs;
2821 relend = rel + input_section->reloc_count;
2822 for (; rel < relend; rel++)
2823 {
2824 long symndx;
2825 struct coff_link_hash_entry *h;
2826 struct internal_syment *sym;
2827 bfd_vma addend;
2828 bfd_vma val;
2829 reloc_howto_type *howto;
2830 bfd_reloc_status_type rstat;
2831
2832 /* Almost all relocs have to do with relaxing. If any work must
2833 be done for them, it has been done in sh_relax_section. */
2834 if (rel->r_type != R_SH_IMM32
17505c5c
NC		 2835#ifdef COFF_WITH_PE
2836 && rel->r_type != R_SH_IMM32CE
2837 && rel->r_type != R_SH_IMAGEBASE
2838#endif
252b5132
RH		 2839 && rel->r_type != R_SH_PCDISP)
2840 continue;
2841
2842 symndx = rel->r_symndx;
2843
2844 if (symndx == -1)
2845 {
2846 h = NULL;
2847 sym = NULL;
2848 }
2849 else
cbfe05c4 2850 {
252b5132
RH		 2851 if (symndx < 0
2852 || (unsigned long) symndx >= obj_raw_syment_count (input_bfd))
2853 {
2854 (*_bfd_error_handler)
2855 ("%s: illegal symbol index %ld in relocs",
8f615d07 2856 bfd_archive_filename (input_bfd), symndx);
252b5132 2857 bfd_set_error (bfd_error_bad_value);
b34976b6 2858 return FALSE;
252b5132
RH		 2859 }
2860 h = obj_coff_sym_hashes (input_bfd)[symndx];
2861 sym = syms + symndx;
2862 }
2863
2864 if (sym != NULL && sym->n_scnum != 0)
2865 addend = - sym->n_value;
2866 else
2867 addend = 0;
2868
2869 if (rel->r_type == R_SH_PCDISP)
2870 addend -= 4;
2871
2872 if (rel->r_type >= SH_COFF_HOWTO_COUNT)
2873 howto = NULL;
2874 else
2875 howto = &sh_coff_howtos[rel->r_type];
2876
2877 if (howto == NULL)
2878 {
2879 bfd_set_error (bfd_error_bad_value);
b34976b6 2880 return FALSE;
252b5132
RH		 2881 }
2882
17505c5c
NC		 2883#ifdef COFF_WITH_PE
2884 if (rel->r_type == R_SH_IMAGEBASE)
2885 addend -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
2886#endif
cbfe05c4 2887
252b5132
RH		 2888 val = 0;
2889
2890 if (h == NULL)
2891 {
2892 asection *sec;
2893
2894 /* There is nothing to do for an internal PCDISP reloc. */
2895 if (rel->r_type == R_SH_PCDISP)
2896 continue;
2897
2898 if (symndx == -1)
2899 {
2900 sec = bfd_abs_section_ptr;
2901 val = 0;
2902 }
2903 else
2904 {
2905 sec = sections[symndx];
2906 val = (sec->output_section->vma
2907 + sec->output_offset
2908 + sym->n_value
2909 - sec->vma);
2910 }
2911 }
2912 else
2913 {
2914 if (h->root.type == bfd_link_hash_defined
2915 || h->root.type == bfd_link_hash_defweak)
2916 {
2917 asection *sec;
2918
2919 sec = h->root.u.def.section;
2920 val = (h->root.u.def.value
2921 + sec->output_section->vma
2922 + sec->output_offset);
2923 }
1049f94e 2924 else if (! info->relocatable)
252b5132
RH		 2925 {
2926 if (! ((*info->callbacks->undefined_symbol)
2927 (info, h->root.root.string, input_bfd, input_section,
b34976b6
AM		 2928 rel->r_vaddr - input_section->vma, TRUE)))
2929 return FALSE;
252b5132
RH		 2930 }
2931 }
2932
2933 rstat = _bfd_final_link_relocate (howto, input_bfd, input_section,
2934 contents,
2935 rel->r_vaddr - input_section->vma,
2936 val, addend);
2937
2938 switch (rstat)
2939 {
2940 default:
2941 abort ();
2942 case bfd_reloc_ok:
2943 break;
2944 case bfd_reloc_overflow:
2945 {
2946 const char *name;
2947 char buf[SYMNMLEN + 1];
2948
2949 if (symndx == -1)
2950 name = "*ABS*";
2951 else if (h != NULL)
2952 name = h->root.root.string;
2953 else if (sym->_n._n_n._n_zeroes == 0
2954 && sym->_n._n_n._n_offset != 0)
2955 name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset;
2956 else
2957 {
2958 strncpy (buf, sym->_n._n_name, SYMNMLEN);
2959 buf[SYMNMLEN] = '\0';
2960 name = buf;
2961 }
2962
2963 if (! ((*info->callbacks->reloc_overflow)
2964 (info, name, howto->name, (bfd_vma) 0, input_bfd,
2965 input_section, rel->r_vaddr - input_section->vma)))
b34976b6 2966 return FALSE;
252b5132
RH		 2967 }
2968 }
2969 }
2970
b34976b6 2971 return TRUE;
252b5132
RH		 2972}
2973
2974/* This is a version of bfd_generic_get_relocated_section_contents
2975 which uses sh_relocate_section. */
2976
2977static bfd_byte *
2978sh_coff_get_relocated_section_contents (output_bfd, link_info, link_order,
1049f94e 2979 data, relocatable, symbols)
252b5132
RH		 2980 bfd *output_bfd;
2981 struct bfd_link_info *link_info;
2982 struct bfd_link_order *link_order;
2983 bfd_byte *data;
1049f94e 2984 bfd_boolean relocatable;
252b5132
RH		 2985 asymbol **symbols;
2986{
2987 asection *input_section = link_order->u.indirect.section;
2988 bfd *input_bfd = input_section->owner;
2989 asection **sections = NULL;
2990 struct internal_reloc *internal_relocs = NULL;
2991 struct internal_syment *internal_syms = NULL;
2992
2993 /* We only need to handle the case of relaxing, or of having a
2994 particular set of section contents, specially. */
1049f94e 2995 if (relocatable
252b5132
RH		 2996 || coff_section_data (input_bfd, input_section) == NULL
2997 || coff_section_data (input_bfd, input_section)->contents == NULL)
2998 return bfd_generic_get_relocated_section_contents (output_bfd, link_info,
2999 link_order, data,
1049f94e 3000 relocatable,
252b5132
RH		 3001 symbols);
3002
3003 memcpy (data, coff_section_data (input_bfd, input_section)->contents,
eea6121a 3004 (size_t) input_section->size);
252b5132
RH		 3005
3006 if ((input_section->flags & SEC_RELOC) != 0
3007 && input_section->reloc_count > 0)
3008 {
3009 bfd_size_type symesz = bfd_coff_symesz (input_bfd);
3010 bfd_byte *esym, *esymend;
3011 struct internal_syment *isymp;
3012 asection **secpp;
dc810e39 3013 bfd_size_type amt;
252b5132
RH		 3014
3015 if (! _bfd_coff_get_external_symbols (input_bfd))
3016 goto error_return;
3017
3018 internal_relocs = (_bfd_coff_read_internal_relocs
b34976b6
AM		 3019 (input_bfd, input_section, FALSE, (bfd_byte *) NULL,
3020 FALSE, (struct internal_reloc *) NULL));
252b5132
RH		 3021 if (internal_relocs == NULL)
3022 goto error_return;
3023
dc810e39
AM		 3024 amt = obj_raw_syment_count (input_bfd);
3025 amt *= sizeof (struct internal_syment);
3026 internal_syms = (struct internal_syment *) bfd_malloc (amt);
252b5132
RH		 3027 if (internal_syms == NULL)
3028 goto error_return;
3029
dc810e39
AM		 3030 amt = obj_raw_syment_count (input_bfd);
3031 amt *= sizeof (asection *);
3032 sections = (asection **) bfd_malloc (amt);
252b5132
RH		 3033 if (sections == NULL)
3034 goto error_return;
3035
3036 isymp = internal_syms;
3037 secpp = sections;
3038 esym = (bfd_byte *) obj_coff_external_syms (input_bfd);
3039 esymend = esym + obj_raw_syment_count (input_bfd) * symesz;
3040 while (esym < esymend)
3041 {
3042 bfd_coff_swap_sym_in (input_bfd, (PTR) esym, (PTR) isymp);
3043
3044 if (isymp->n_scnum != 0)
3045 *secpp = coff_section_from_bfd_index (input_bfd, isymp->n_scnum);
3046 else
3047 {
3048 if (isymp->n_value == 0)
3049 *secpp = bfd_und_section_ptr;
3050 else
3051 *secpp = bfd_com_section_ptr;
3052 }
3053
3054 esym += (isymp->n_numaux + 1) * symesz;
3055 secpp += isymp->n_numaux + 1;
3056 isymp += isymp->n_numaux + 1;
3057 }
3058
3059 if (! sh_relocate_section (output_bfd, link_info, input_bfd,
3060 input_section, data, internal_relocs,
3061 internal_syms, sections))
3062 goto error_return;
3063
3064 free (sections);
3065 sections = NULL;
3066 free (internal_syms);
3067 internal_syms = NULL;
3068 free (internal_relocs);
3069 internal_relocs = NULL;
3070 }
3071
3072 return data;
3073
3074 error_return:
3075 if (internal_relocs != NULL)
3076 free (internal_relocs);
3077 if (internal_syms != NULL)
3078 free (internal_syms);
3079 if (sections != NULL)
3080 free (sections);
3081 return NULL;
3082}
3083
3084/* The target vectors. */
3085
17505c5c 3086#ifndef TARGET_SHL_SYM
3fa78519 3087CREATE_BIG_COFF_TARGET_VEC (shcoff_vec, "coff-sh", BFD_IS_RELAXABLE, 0, '_', NULL, COFF_SWAP_TABLE)
17505c5c 3088#endif
252b5132 3089
c3c89269
NC		 3090#ifdef TARGET_SHL_SYM
3091#define TARGET_SYM TARGET_SHL_SYM
3092#else
3093#define TARGET_SYM shlcoff_vec
3094#endif
cbfe05c4 3095
c3c89269
NC		 3096#ifndef TARGET_SHL_NAME
3097#define TARGET_SHL_NAME "coff-shl"
3098#endif
252b5132 3099
17505c5c
NC		 3100#ifdef COFF_WITH_PE
3101CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3fa78519 3102 SEC_CODE | SEC_DATA, '_', NULL, COFF_SWAP_TABLE);
17505c5c 3103#else
86033394 3104CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3fa78519 3105 0, '_', NULL, COFF_SWAP_TABLE)
17505c5c 3106#endif
86033394 3107
17505c5c 3108#ifndef TARGET_SHL_SYM
f4ffd778 3109static const bfd_target * coff_small_object_p PARAMS ((bfd *));
b34976b6 3110static bfd_boolean coff_small_new_section_hook PARAMS ((bfd *, asection *));
252b5132
RH		 3111/* Some people want versions of the SH COFF target which do not align
3112 to 16 byte boundaries. We implement that by adding a couple of new
3113 target vectors. These are just like the ones above, but they
3114 change the default section alignment. To generate them in the
3115 assembler, use -small. To use them in the linker, use -b
3116 coff-sh{l}-small and -oformat coff-sh{l}-small.
3117
3118 Yes, this is a horrible hack. A general solution for setting
3119 section alignment in COFF is rather complex. ELF handles this
3120 correctly. */
3121
3122/* Only recognize the small versions if the target was not defaulted.
3123 Otherwise we won't recognize the non default endianness. */
3124
3125static const bfd_target *
3126coff_small_object_p (abfd)
3127 bfd *abfd;
3128{
3129 if (abfd->target_defaulted)
3130 {
3131 bfd_set_error (bfd_error_wrong_format);
3132 return NULL;
3133 }
3134 return coff_object_p (abfd);
3135}
3136
3137/* Set the section alignment for the small versions. */
3138
b34976b6 3139static bfd_boolean
252b5132
RH		 3140coff_small_new_section_hook (abfd, section)
3141 bfd *abfd;
3142 asection *section;
3143{
3144 if (! coff_new_section_hook (abfd, section))
b34976b6 3145 return FALSE;
252b5132
RH		 3146
3147 /* We must align to at least a four byte boundary, because longword
3148 accesses must be on a four byte boundary. */
3149 if (section->alignment_power == COFF_DEFAULT_SECTION_ALIGNMENT_POWER)
3150 section->alignment_power = 2;
3151
b34976b6 3152 return TRUE;
252b5132
RH		 3153}
3154
3155/* This is copied from bfd_coff_std_swap_table so that we can change
3156 the default section alignment power. */
3157
3158static const bfd_coff_backend_data bfd_coff_small_swap_table =
3159{
3160 coff_swap_aux_in, coff_swap_sym_in, coff_swap_lineno_in,
3161 coff_swap_aux_out, coff_swap_sym_out,
3162 coff_swap_lineno_out, coff_swap_reloc_out,
3163 coff_swap_filehdr_out, coff_swap_aouthdr_out,
3164 coff_swap_scnhdr_out,
692b7d62 3165 FILHSZ, AOUTSZ, SCNHSZ, SYMESZ, AUXESZ, RELSZ, LINESZ, FILNMLEN,
252b5132 3166#ifdef COFF_LONG_FILENAMES
b34976b6 3167 TRUE,
252b5132 3168#else
b34976b6 3169 FALSE,
252b5132
RH		 3170#endif
3171#ifdef COFF_LONG_SECTION_NAMES
b34976b6 3172 TRUE,
252b5132 3173#else
b34976b6 3174 FALSE,
252b5132
RH		 3175#endif
3176 2,
ecefdb58 3177#ifdef COFF_FORCE_SYMBOLS_IN_STRINGS
b34976b6 3178 TRUE,
ecefdb58 3179#else
b34976b6 3180 FALSE,
ecefdb58
CP		 3181#endif
3182#ifdef COFF_DEBUG_STRING_WIDE_PREFIX
3183 4,
3184#else
3185 2,
3186#endif
252b5132
RH		 3187 coff_swap_filehdr_in, coff_swap_aouthdr_in, coff_swap_scnhdr_in,
3188 coff_swap_reloc_in, coff_bad_format_hook, coff_set_arch_mach_hook,
3189 coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook,
3190 coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook,
3191 coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate,
5d54c628 3192 coff_classify_symbol, coff_compute_section_file_positions,
252b5132
RH		 3193 coff_start_final_link, coff_relocate_section, coff_rtype_to_howto,
3194 coff_adjust_symndx, coff_link_add_one_symbol,
3195 coff_link_output_has_begun, coff_final_link_postscript
3196};
3197
3198#define coff_small_close_and_cleanup \
3199 coff_close_and_cleanup
3200#define coff_small_bfd_free_cached_info \
3201 coff_bfd_free_cached_info
3202#define coff_small_get_section_contents \
3203 coff_get_section_contents
3204#define coff_small_get_section_contents_in_window \
3205 coff_get_section_contents_in_window
3206
c3c89269
NC		 3207extern const bfd_target shlcoff_small_vec;
3208
252b5132
RH		 3209const bfd_target shcoff_small_vec =
3210{
3211 "coff-sh-small", /* name */
3212 bfd_target_coff_flavour,
3213 BFD_ENDIAN_BIG, /* data byte order is big */
3214 BFD_ENDIAN_BIG, /* header byte order is big */
3215
3216 (HAS_RELOC | EXEC_P | /* object flags */
3217 HAS_LINENO | HAS_DEBUG |
3218 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
3219
3220 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3221 '_', /* leading symbol underscore */
3222 '/', /* ar_pad_char */
3223 15, /* ar_max_namelen */
3224 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3225 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3226 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
3227 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3228 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3229 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
3230
3231 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
3232 bfd_generic_archive_p, _bfd_dummy_target},
3233 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
3234 bfd_false},
3235 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
3236 _bfd_write_archive_contents, bfd_false},
3237
3238 BFD_JUMP_TABLE_GENERIC (coff_small),
3239 BFD_JUMP_TABLE_COPY (coff),
3240 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3241 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3242 BFD_JUMP_TABLE_SYMBOLS (coff),
3243 BFD_JUMP_TABLE_RELOCS (coff),
3244 BFD_JUMP_TABLE_WRITE (coff),
3245 BFD_JUMP_TABLE_LINK (coff),
3246 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3247
c3c89269 3248 & shlcoff_small_vec,
cbfe05c4 3249
252b5132
RH		 3250 (PTR) &bfd_coff_small_swap_table
3251};
3252
3253const bfd_target shlcoff_small_vec =
3254{
3255 "coff-shl-small", /* name */
3256 bfd_target_coff_flavour,
3257 BFD_ENDIAN_LITTLE, /* data byte order is little */
3258 BFD_ENDIAN_LITTLE, /* header byte order is little endian too*/
3259
3260 (HAS_RELOC | EXEC_P | /* object flags */
3261 HAS_LINENO | HAS_DEBUG |
3262 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
3263
3264 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3265 '_', /* leading symbol underscore */
3266 '/', /* ar_pad_char */
3267 15, /* ar_max_namelen */
3268 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3269 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3270 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
3271 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3272 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3273 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
3274
3275 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
cbfe05c4 3276 bfd_generic_archive_p, _bfd_dummy_target},
252b5132
RH		 3277 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
3278 bfd_false},
3279 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
3280 _bfd_write_archive_contents, bfd_false},
3281
3282 BFD_JUMP_TABLE_GENERIC (coff_small),
3283 BFD_JUMP_TABLE_COPY (coff),
3284 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3285 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3286 BFD_JUMP_TABLE_SYMBOLS (coff),
3287 BFD_JUMP_TABLE_RELOCS (coff),
3288 BFD_JUMP_TABLE_WRITE (coff),
3289 BFD_JUMP_TABLE_LINK (coff),
3290 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3291
c3c89269 3292 & shcoff_small_vec,
cbfe05c4 3293
252b5132
RH		 3294 (PTR) &bfd_coff_small_swap_table
3295};
17505c5c 3296#endif
GDB Binutils - Deliverables
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