projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
PR23652, Use symbols from debug bfd for _bfd_elf_find_function
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
82704155 2 Copyright (C) 1998-2019 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
00a97672 25#include "libiberty.h"
7f266840
DJ		 26#include "libbfd.h"
27#include "elf-bfd.h"
b38cadfb 28#include "elf-nacl.h"
00a97672 29#include "elf-vxworks.h"
ee065d83 30#include "elf/arm.h"
f37164d7
AM		 31#include "elf32-arm.h"
32#include "cpu-arm.h"
7f266840 33
00a97672
RS		 34/* Return the relocation section associated with NAME. HTAB is the
35 bfd's elf32_arm_link_hash_entry. */
36#define RELOC_SECTION(HTAB, NAME) \
37 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
38
39/* Return size of a relocation entry. HTAB is the bfd's
40 elf32_arm_link_hash_entry. */
41#define RELOC_SIZE(HTAB) \
42 ((HTAB)->use_rel \
43 ? sizeof (Elf32_External_Rel) \
44 : sizeof (Elf32_External_Rela))
45
46/* Return function to swap relocations in. HTAB is the bfd's
47 elf32_arm_link_hash_entry. */
48#define SWAP_RELOC_IN(HTAB) \
49 ((HTAB)->use_rel \
50 ? bfd_elf32_swap_reloc_in \
51 : bfd_elf32_swap_reloca_in)
52
53/* Return function to swap relocations out. HTAB is the bfd's
54 elf32_arm_link_hash_entry. */
55#define SWAP_RELOC_OUT(HTAB) \
56 ((HTAB)->use_rel \
57 ? bfd_elf32_swap_reloc_out \
58 : bfd_elf32_swap_reloca_out)
59
f3185997 60#define elf_info_to_howto NULL
07d6d2b8 61#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 62
63#define ARM_ELF_ABI_VERSION 0
64#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
65
79f08007
YZ		 66/* The Adjusted Place, as defined by AAELF. */
67#define Pa(X) ((X) & 0xfffffffc)
68
3e6b1042
DJ		 69static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
70 struct bfd_link_info *link_info,
71 asection *sec,
72 bfd_byte *contents);
73
7f266840
DJ		 74/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
75 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
76 in that slot. */
77
c19d1205 78static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 79{
8029a119 80 /* No relocation. */
7f266840
DJ		 81 HOWTO (R_ARM_NONE, /* type */
82 0, /* rightshift */
6346d5ca 83 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 84 0, /* bitsize */
85 FALSE, /* pc_relative */
86 0, /* bitpos */
87 complain_overflow_dont,/* complain_on_overflow */
88 bfd_elf_generic_reloc, /* special_function */
89 "R_ARM_NONE", /* name */
90 FALSE, /* partial_inplace */
91 0, /* src_mask */
92 0, /* dst_mask */
93 FALSE), /* pcrel_offset */
94
95 HOWTO (R_ARM_PC24, /* type */
96 2, /* rightshift */
97 2, /* size (0 = byte, 1 = short, 2 = long) */
98 24, /* bitsize */
99 TRUE, /* pc_relative */
100 0, /* bitpos */
101 complain_overflow_signed,/* complain_on_overflow */
102 bfd_elf_generic_reloc, /* special_function */
103 "R_ARM_PC24", /* name */
104 FALSE, /* partial_inplace */
105 0x00ffffff, /* src_mask */
106 0x00ffffff, /* dst_mask */
107 TRUE), /* pcrel_offset */
108
109 /* 32 bit absolute */
110 HOWTO (R_ARM_ABS32, /* type */
111 0, /* rightshift */
112 2, /* size (0 = byte, 1 = short, 2 = long) */
113 32, /* bitsize */
114 FALSE, /* pc_relative */
115 0, /* bitpos */
116 complain_overflow_bitfield,/* complain_on_overflow */
117 bfd_elf_generic_reloc, /* special_function */
118 "R_ARM_ABS32", /* name */
119 FALSE, /* partial_inplace */
120 0xffffffff, /* src_mask */
121 0xffffffff, /* dst_mask */
122 FALSE), /* pcrel_offset */
123
124 /* standard 32bit pc-relative reloc */
125 HOWTO (R_ARM_REL32, /* type */
126 0, /* rightshift */
127 2, /* size (0 = byte, 1 = short, 2 = long) */
128 32, /* bitsize */
129 TRUE, /* pc_relative */
130 0, /* bitpos */
131 complain_overflow_bitfield,/* complain_on_overflow */
132 bfd_elf_generic_reloc, /* special_function */
133 "R_ARM_REL32", /* name */
134 FALSE, /* partial_inplace */
135 0xffffffff, /* src_mask */
136 0xffffffff, /* dst_mask */
137 TRUE), /* pcrel_offset */
138
c19d1205 139 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 140 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 141 0, /* rightshift */
142 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 143 32, /* bitsize */
144 TRUE, /* pc_relative */
7f266840 145 0, /* bitpos */
4962c51a 146 complain_overflow_dont,/* complain_on_overflow */
7f266840 147 bfd_elf_generic_reloc, /* special_function */
4962c51a 148 "R_ARM_LDR_PC_G0", /* name */
7f266840 149 FALSE, /* partial_inplace */
4962c51a
MS		 150 0xffffffff, /* src_mask */
151 0xffffffff, /* dst_mask */
152 TRUE), /* pcrel_offset */
7f266840
DJ		 153
154 /* 16 bit absolute */
155 HOWTO (R_ARM_ABS16, /* type */
156 0, /* rightshift */
157 1, /* size (0 = byte, 1 = short, 2 = long) */
158 16, /* bitsize */
159 FALSE, /* pc_relative */
160 0, /* bitpos */
161 complain_overflow_bitfield,/* complain_on_overflow */
162 bfd_elf_generic_reloc, /* special_function */
163 "R_ARM_ABS16", /* name */
164 FALSE, /* partial_inplace */
165 0x0000ffff, /* src_mask */
166 0x0000ffff, /* dst_mask */
167 FALSE), /* pcrel_offset */
168
169 /* 12 bit absolute */
170 HOWTO (R_ARM_ABS12, /* type */
171 0, /* rightshift */
172 2, /* size (0 = byte, 1 = short, 2 = long) */
173 12, /* bitsize */
174 FALSE, /* pc_relative */
175 0, /* bitpos */
176 complain_overflow_bitfield,/* complain_on_overflow */
177 bfd_elf_generic_reloc, /* special_function */
178 "R_ARM_ABS12", /* name */
179 FALSE, /* partial_inplace */
00a97672
RS		 180 0x00000fff, /* src_mask */
181 0x00000fff, /* dst_mask */
7f266840
DJ		 182 FALSE), /* pcrel_offset */
183
184 HOWTO (R_ARM_THM_ABS5, /* type */
185 6, /* rightshift */
186 1, /* size (0 = byte, 1 = short, 2 = long) */
187 5, /* bitsize */
188 FALSE, /* pc_relative */
189 0, /* bitpos */
190 complain_overflow_bitfield,/* complain_on_overflow */
191 bfd_elf_generic_reloc, /* special_function */
192 "R_ARM_THM_ABS5", /* name */
193 FALSE, /* partial_inplace */
194 0x000007e0, /* src_mask */
195 0x000007e0, /* dst_mask */
196 FALSE), /* pcrel_offset */
197
198 /* 8 bit absolute */
199 HOWTO (R_ARM_ABS8, /* type */
200 0, /* rightshift */
201 0, /* size (0 = byte, 1 = short, 2 = long) */
202 8, /* bitsize */
203 FALSE, /* pc_relative */
204 0, /* bitpos */
205 complain_overflow_bitfield,/* complain_on_overflow */
206 bfd_elf_generic_reloc, /* special_function */
207 "R_ARM_ABS8", /* name */
208 FALSE, /* partial_inplace */
209 0x000000ff, /* src_mask */
210 0x000000ff, /* dst_mask */
211 FALSE), /* pcrel_offset */
212
213 HOWTO (R_ARM_SBREL32, /* type */
214 0, /* rightshift */
215 2, /* size (0 = byte, 1 = short, 2 = long) */
216 32, /* bitsize */
217 FALSE, /* pc_relative */
218 0, /* bitpos */
219 complain_overflow_dont,/* complain_on_overflow */
220 bfd_elf_generic_reloc, /* special_function */
221 "R_ARM_SBREL32", /* name */
222 FALSE, /* partial_inplace */
223 0xffffffff, /* src_mask */
224 0xffffffff, /* dst_mask */
225 FALSE), /* pcrel_offset */
226
c19d1205 227 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 228 1, /* rightshift */
229 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 230 24, /* bitsize */
7f266840
DJ		 231 TRUE, /* pc_relative */
232 0, /* bitpos */
233 complain_overflow_signed,/* complain_on_overflow */
234 bfd_elf_generic_reloc, /* special_function */
c19d1205 235 "R_ARM_THM_CALL", /* name */
7f266840 236 FALSE, /* partial_inplace */
7f6ab9f8
AM		 237 0x07ff2fff, /* src_mask */
238 0x07ff2fff, /* dst_mask */
7f266840
DJ		 239 TRUE), /* pcrel_offset */
240
07d6d2b8 241 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 242 1, /* rightshift */
243 1, /* size (0 = byte, 1 = short, 2 = long) */
244 8, /* bitsize */
245 TRUE, /* pc_relative */
246 0, /* bitpos */
247 complain_overflow_signed,/* complain_on_overflow */
248 bfd_elf_generic_reloc, /* special_function */
249 "R_ARM_THM_PC8", /* name */
250 FALSE, /* partial_inplace */
251 0x000000ff, /* src_mask */
252 0x000000ff, /* dst_mask */
253 TRUE), /* pcrel_offset */
254
c19d1205 255 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 256 1, /* rightshift */
257 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 258 32, /* bitsize */
259 FALSE, /* pc_relative */
7f266840
DJ		 260 0, /* bitpos */
261 complain_overflow_signed,/* complain_on_overflow */
262 bfd_elf_generic_reloc, /* special_function */
c19d1205 263 "R_ARM_BREL_ADJ", /* name */
7f266840 264 FALSE, /* partial_inplace */
c19d1205
ZW		 265 0xffffffff, /* src_mask */
266 0xffffffff, /* dst_mask */
267 FALSE), /* pcrel_offset */
7f266840 268
0855e32b 269 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 270 0, /* rightshift */
0855e32b
NS		 271 2, /* size (0 = byte, 1 = short, 2 = long) */
272 32, /* bitsize */
7f266840
DJ		 273 FALSE, /* pc_relative */
274 0, /* bitpos */
0855e32b 275 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 276 bfd_elf_generic_reloc, /* special_function */
0855e32b 277 "R_ARM_TLS_DESC", /* name */
7f266840 278 FALSE, /* partial_inplace */
0855e32b
NS		 279 0xffffffff, /* src_mask */
280 0xffffffff, /* dst_mask */
7f266840
DJ		 281 FALSE), /* pcrel_offset */
282
283 HOWTO (R_ARM_THM_SWI8, /* type */
284 0, /* rightshift */
285 0, /* size (0 = byte, 1 = short, 2 = long) */
286 0, /* bitsize */
287 FALSE, /* pc_relative */
288 0, /* bitpos */
289 complain_overflow_signed,/* complain_on_overflow */
290 bfd_elf_generic_reloc, /* special_function */
291 "R_ARM_SWI8", /* name */
292 FALSE, /* partial_inplace */
293 0x00000000, /* src_mask */
294 0x00000000, /* dst_mask */
295 FALSE), /* pcrel_offset */
296
297 /* BLX instruction for the ARM. */
298 HOWTO (R_ARM_XPC25, /* type */
299 2, /* rightshift */
300 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 301 24, /* bitsize */
7f266840
DJ		 302 TRUE, /* pc_relative */
303 0, /* bitpos */
304 complain_overflow_signed,/* complain_on_overflow */
305 bfd_elf_generic_reloc, /* special_function */
306 "R_ARM_XPC25", /* name */
307 FALSE, /* partial_inplace */
308 0x00ffffff, /* src_mask */
309 0x00ffffff, /* dst_mask */
310 TRUE), /* pcrel_offset */
311
312 /* BLX instruction for the Thumb. */
313 HOWTO (R_ARM_THM_XPC22, /* type */
314 2, /* rightshift */
315 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 316 24, /* bitsize */
7f266840
DJ		 317 TRUE, /* pc_relative */
318 0, /* bitpos */
319 complain_overflow_signed,/* complain_on_overflow */
320 bfd_elf_generic_reloc, /* special_function */
321 "R_ARM_THM_XPC22", /* name */
322 FALSE, /* partial_inplace */
7f6ab9f8
AM		 323 0x07ff2fff, /* src_mask */
324 0x07ff2fff, /* dst_mask */
7f266840
DJ		 325 TRUE), /* pcrel_offset */
326
ba93b8ac 327 /* Dynamic TLS relocations. */
7f266840 328
ba93b8ac 329 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 330 0, /* rightshift */
331 2, /* size (0 = byte, 1 = short, 2 = long) */
332 32, /* bitsize */
333 FALSE, /* pc_relative */
334 0, /* bitpos */
99059e56
RM		 335 complain_overflow_bitfield,/* complain_on_overflow */
336 bfd_elf_generic_reloc, /* special_function */
337 "R_ARM_TLS_DTPMOD32", /* name */
338 TRUE, /* partial_inplace */
339 0xffffffff, /* src_mask */
340 0xffffffff, /* dst_mask */
07d6d2b8 341 FALSE), /* pcrel_offset */
7f266840 342
ba93b8ac 343 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 344 0, /* rightshift */
345 2, /* size (0 = byte, 1 = short, 2 = long) */
346 32, /* bitsize */
347 FALSE, /* pc_relative */
348 0, /* bitpos */
99059e56
RM		 349 complain_overflow_bitfield,/* complain_on_overflow */
350 bfd_elf_generic_reloc, /* special_function */
351 "R_ARM_TLS_DTPOFF32", /* name */
352 TRUE, /* partial_inplace */
353 0xffffffff, /* src_mask */
354 0xffffffff, /* dst_mask */
07d6d2b8 355 FALSE), /* pcrel_offset */
7f266840 356
ba93b8ac 357 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 358 0, /* rightshift */
359 2, /* size (0 = byte, 1 = short, 2 = long) */
360 32, /* bitsize */
361 FALSE, /* pc_relative */
362 0, /* bitpos */
99059e56
RM		 363 complain_overflow_bitfield,/* complain_on_overflow */
364 bfd_elf_generic_reloc, /* special_function */
365 "R_ARM_TLS_TPOFF32", /* name */
366 TRUE, /* partial_inplace */
367 0xffffffff, /* src_mask */
368 0xffffffff, /* dst_mask */
07d6d2b8 369 FALSE), /* pcrel_offset */
7f266840
DJ		 370
371 /* Relocs used in ARM Linux */
372
373 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 374 0, /* rightshift */
375 2, /* size (0 = byte, 1 = short, 2 = long) */
376 32, /* bitsize */
377 FALSE, /* pc_relative */
378 0, /* bitpos */
99059e56
RM		 379 complain_overflow_bitfield,/* complain_on_overflow */
380 bfd_elf_generic_reloc, /* special_function */
381 "R_ARM_COPY", /* name */
382 TRUE, /* partial_inplace */
383 0xffffffff, /* src_mask */
384 0xffffffff, /* dst_mask */
07d6d2b8 385 FALSE), /* pcrel_offset */
7f266840
DJ		 386
387 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 388 0, /* rightshift */
389 2, /* size (0 = byte, 1 = short, 2 = long) */
390 32, /* bitsize */
391 FALSE, /* pc_relative */
392 0, /* bitpos */
99059e56
RM		 393 complain_overflow_bitfield,/* complain_on_overflow */
394 bfd_elf_generic_reloc, /* special_function */
395 "R_ARM_GLOB_DAT", /* name */
396 TRUE, /* partial_inplace */
397 0xffffffff, /* src_mask */
398 0xffffffff, /* dst_mask */
07d6d2b8 399 FALSE), /* pcrel_offset */
7f266840
DJ		 400
401 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 402 0, /* rightshift */
403 2, /* size (0 = byte, 1 = short, 2 = long) */
404 32, /* bitsize */
405 FALSE, /* pc_relative */
406 0, /* bitpos */
99059e56
RM		 407 complain_overflow_bitfield,/* complain_on_overflow */
408 bfd_elf_generic_reloc, /* special_function */
409 "R_ARM_JUMP_SLOT", /* name */
410 TRUE, /* partial_inplace */
411 0xffffffff, /* src_mask */
412 0xffffffff, /* dst_mask */
07d6d2b8 413 FALSE), /* pcrel_offset */
7f266840
DJ		 414
415 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 416 0, /* rightshift */
417 2, /* size (0 = byte, 1 = short, 2 = long) */
418 32, /* bitsize */
419 FALSE, /* pc_relative */
420 0, /* bitpos */
99059e56
RM		 421 complain_overflow_bitfield,/* complain_on_overflow */
422 bfd_elf_generic_reloc, /* special_function */
423 "R_ARM_RELATIVE", /* name */
424 TRUE, /* partial_inplace */
425 0xffffffff, /* src_mask */
426 0xffffffff, /* dst_mask */
07d6d2b8 427 FALSE), /* pcrel_offset */
7f266840 428
c19d1205 429 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 430 0, /* rightshift */
431 2, /* size (0 = byte, 1 = short, 2 = long) */
432 32, /* bitsize */
433 FALSE, /* pc_relative */
434 0, /* bitpos */
99059e56
RM		 435 complain_overflow_bitfield,/* complain_on_overflow */
436 bfd_elf_generic_reloc, /* special_function */
437 "R_ARM_GOTOFF32", /* name */
438 TRUE, /* partial_inplace */
439 0xffffffff, /* src_mask */
440 0xffffffff, /* dst_mask */
07d6d2b8 441 FALSE), /* pcrel_offset */
7f266840
DJ		 442
443 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 444 0, /* rightshift */
445 2, /* size (0 = byte, 1 = short, 2 = long) */
446 32, /* bitsize */
99059e56 447 TRUE, /* pc_relative */
07d6d2b8 448 0, /* bitpos */
99059e56
RM		 449 complain_overflow_bitfield,/* complain_on_overflow */
450 bfd_elf_generic_reloc, /* special_function */
451 "R_ARM_GOTPC", /* name */
452 TRUE, /* partial_inplace */
453 0xffffffff, /* src_mask */
454 0xffffffff, /* dst_mask */
455 TRUE), /* pcrel_offset */
7f266840
DJ		 456
457 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 458 0, /* rightshift */
459 2, /* size (0 = byte, 1 = short, 2 = long) */
460 32, /* bitsize */
99059e56 461 FALSE, /* pc_relative */
07d6d2b8 462 0, /* bitpos */
99059e56
RM		 463 complain_overflow_bitfield,/* complain_on_overflow */
464 bfd_elf_generic_reloc, /* special_function */
465 "R_ARM_GOT32", /* name */
466 TRUE, /* partial_inplace */
467 0xffffffff, /* src_mask */
468 0xffffffff, /* dst_mask */
469 FALSE), /* pcrel_offset */
7f266840
DJ		 470
471 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 472 2, /* rightshift */
473 2, /* size (0 = byte, 1 = short, 2 = long) */
474 24, /* bitsize */
99059e56 475 TRUE, /* pc_relative */
07d6d2b8 476 0, /* bitpos */
99059e56
RM		 477 complain_overflow_bitfield,/* complain_on_overflow */
478 bfd_elf_generic_reloc, /* special_function */
479 "R_ARM_PLT32", /* name */
480 FALSE, /* partial_inplace */
481 0x00ffffff, /* src_mask */
482 0x00ffffff, /* dst_mask */
483 TRUE), /* pcrel_offset */
7f266840
DJ		 484
485 HOWTO (R_ARM_CALL, /* type */
486 2, /* rightshift */
487 2, /* size (0 = byte, 1 = short, 2 = long) */
488 24, /* bitsize */
489 TRUE, /* pc_relative */
490 0, /* bitpos */
491 complain_overflow_signed,/* complain_on_overflow */
492 bfd_elf_generic_reloc, /* special_function */
493 "R_ARM_CALL", /* name */
494 FALSE, /* partial_inplace */
495 0x00ffffff, /* src_mask */
496 0x00ffffff, /* dst_mask */
497 TRUE), /* pcrel_offset */
498
499 HOWTO (R_ARM_JUMP24, /* type */
500 2, /* rightshift */
501 2, /* size (0 = byte, 1 = short, 2 = long) */
502 24, /* bitsize */
503 TRUE, /* pc_relative */
504 0, /* bitpos */
505 complain_overflow_signed,/* complain_on_overflow */
506 bfd_elf_generic_reloc, /* special_function */
507 "R_ARM_JUMP24", /* name */
508 FALSE, /* partial_inplace */
509 0x00ffffff, /* src_mask */
510 0x00ffffff, /* dst_mask */
511 TRUE), /* pcrel_offset */
512
c19d1205
ZW		 513 HOWTO (R_ARM_THM_JUMP24, /* type */
514 1, /* rightshift */
515 2, /* size (0 = byte, 1 = short, 2 = long) */
516 24, /* bitsize */
517 TRUE, /* pc_relative */
7f266840 518 0, /* bitpos */
c19d1205 519 complain_overflow_signed,/* complain_on_overflow */
7f266840 520 bfd_elf_generic_reloc, /* special_function */
c19d1205 521 "R_ARM_THM_JUMP24", /* name */
7f266840 522 FALSE, /* partial_inplace */
c19d1205
ZW		 523 0x07ff2fff, /* src_mask */
524 0x07ff2fff, /* dst_mask */
525 TRUE), /* pcrel_offset */
7f266840 526
c19d1205 527 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 528 0, /* rightshift */
c19d1205
ZW		 529 2, /* size (0 = byte, 1 = short, 2 = long) */
530 32, /* bitsize */
7f266840
DJ		 531 FALSE, /* pc_relative */
532 0, /* bitpos */
533 complain_overflow_dont,/* complain_on_overflow */
534 bfd_elf_generic_reloc, /* special_function */
c19d1205 535 "R_ARM_BASE_ABS", /* name */
7f266840 536 FALSE, /* partial_inplace */
c19d1205
ZW		 537 0xffffffff, /* src_mask */
538 0xffffffff, /* dst_mask */
7f266840
DJ		 539 FALSE), /* pcrel_offset */
540
541 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
542 0, /* rightshift */
543 2, /* size (0 = byte, 1 = short, 2 = long) */
544 12, /* bitsize */
545 TRUE, /* pc_relative */
546 0, /* bitpos */
547 complain_overflow_dont,/* complain_on_overflow */
548 bfd_elf_generic_reloc, /* special_function */
549 "R_ARM_ALU_PCREL_7_0", /* name */
550 FALSE, /* partial_inplace */
551 0x00000fff, /* src_mask */
552 0x00000fff, /* dst_mask */
553 TRUE), /* pcrel_offset */
554
555 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
556 0, /* rightshift */
557 2, /* size (0 = byte, 1 = short, 2 = long) */
558 12, /* bitsize */
559 TRUE, /* pc_relative */
560 8, /* bitpos */
561 complain_overflow_dont,/* complain_on_overflow */
562 bfd_elf_generic_reloc, /* special_function */
563 "R_ARM_ALU_PCREL_15_8",/* name */
564 FALSE, /* partial_inplace */
565 0x00000fff, /* src_mask */
566 0x00000fff, /* dst_mask */
567 TRUE), /* pcrel_offset */
568
569 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
570 0, /* rightshift */
571 2, /* size (0 = byte, 1 = short, 2 = long) */
572 12, /* bitsize */
573 TRUE, /* pc_relative */
574 16, /* bitpos */
575 complain_overflow_dont,/* complain_on_overflow */
576 bfd_elf_generic_reloc, /* special_function */
577 "R_ARM_ALU_PCREL_23_15",/* name */
578 FALSE, /* partial_inplace */
579 0x00000fff, /* src_mask */
580 0x00000fff, /* dst_mask */
581 TRUE), /* pcrel_offset */
582
583 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
584 0, /* rightshift */
585 2, /* size (0 = byte, 1 = short, 2 = long) */
586 12, /* bitsize */
587 FALSE, /* pc_relative */
588 0, /* bitpos */
589 complain_overflow_dont,/* complain_on_overflow */
590 bfd_elf_generic_reloc, /* special_function */
591 "R_ARM_LDR_SBREL_11_0",/* name */
592 FALSE, /* partial_inplace */
593 0x00000fff, /* src_mask */
594 0x00000fff, /* dst_mask */
595 FALSE), /* pcrel_offset */
596
597 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
598 0, /* rightshift */
599 2, /* size (0 = byte, 1 = short, 2 = long) */
600 8, /* bitsize */
601 FALSE, /* pc_relative */
602 12, /* bitpos */
603 complain_overflow_dont,/* complain_on_overflow */
604 bfd_elf_generic_reloc, /* special_function */
605 "R_ARM_ALU_SBREL_19_12",/* name */
606 FALSE, /* partial_inplace */
607 0x000ff000, /* src_mask */
608 0x000ff000, /* dst_mask */
609 FALSE), /* pcrel_offset */
610
611 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
612 0, /* rightshift */
613 2, /* size (0 = byte, 1 = short, 2 = long) */
614 8, /* bitsize */
615 FALSE, /* pc_relative */
616 20, /* bitpos */
617 complain_overflow_dont,/* complain_on_overflow */
618 bfd_elf_generic_reloc, /* special_function */
619 "R_ARM_ALU_SBREL_27_20",/* name */
620 FALSE, /* partial_inplace */
621 0x0ff00000, /* src_mask */
622 0x0ff00000, /* dst_mask */
623 FALSE), /* pcrel_offset */
624
625 HOWTO (R_ARM_TARGET1, /* type */
626 0, /* rightshift */
627 2, /* size (0 = byte, 1 = short, 2 = long) */
628 32, /* bitsize */
629 FALSE, /* pc_relative */
630 0, /* bitpos */
631 complain_overflow_dont,/* complain_on_overflow */
632 bfd_elf_generic_reloc, /* special_function */
633 "R_ARM_TARGET1", /* name */
634 FALSE, /* partial_inplace */
635 0xffffffff, /* src_mask */
636 0xffffffff, /* dst_mask */
637 FALSE), /* pcrel_offset */
638
639 HOWTO (R_ARM_ROSEGREL32, /* type */
640 0, /* rightshift */
641 2, /* size (0 = byte, 1 = short, 2 = long) */
642 32, /* bitsize */
643 FALSE, /* pc_relative */
644 0, /* bitpos */
645 complain_overflow_dont,/* complain_on_overflow */
646 bfd_elf_generic_reloc, /* special_function */
647 "R_ARM_ROSEGREL32", /* name */
648 FALSE, /* partial_inplace */
649 0xffffffff, /* src_mask */
650 0xffffffff, /* dst_mask */
651 FALSE), /* pcrel_offset */
652
653 HOWTO (R_ARM_V4BX, /* type */
654 0, /* rightshift */
655 2, /* size (0 = byte, 1 = short, 2 = long) */
656 32, /* bitsize */
657 FALSE, /* pc_relative */
658 0, /* bitpos */
659 complain_overflow_dont,/* complain_on_overflow */
660 bfd_elf_generic_reloc, /* special_function */
661 "R_ARM_V4BX", /* name */
662 FALSE, /* partial_inplace */
663 0xffffffff, /* src_mask */
664 0xffffffff, /* dst_mask */
665 FALSE), /* pcrel_offset */
666
667 HOWTO (R_ARM_TARGET2, /* type */
668 0, /* rightshift */
669 2, /* size (0 = byte, 1 = short, 2 = long) */
670 32, /* bitsize */
671 FALSE, /* pc_relative */
672 0, /* bitpos */
673 complain_overflow_signed,/* complain_on_overflow */
674 bfd_elf_generic_reloc, /* special_function */
675 "R_ARM_TARGET2", /* name */
676 FALSE, /* partial_inplace */
677 0xffffffff, /* src_mask */
678 0xffffffff, /* dst_mask */
679 TRUE), /* pcrel_offset */
680
681 HOWTO (R_ARM_PREL31, /* type */
682 0, /* rightshift */
683 2, /* size (0 = byte, 1 = short, 2 = long) */
684 31, /* bitsize */
685 TRUE, /* pc_relative */
686 0, /* bitpos */
687 complain_overflow_signed,/* complain_on_overflow */
688 bfd_elf_generic_reloc, /* special_function */
689 "R_ARM_PREL31", /* name */
690 FALSE, /* partial_inplace */
691 0x7fffffff, /* src_mask */
692 0x7fffffff, /* dst_mask */
693 TRUE), /* pcrel_offset */
c19d1205
ZW		 694
695 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
696 0, /* rightshift */
697 2, /* size (0 = byte, 1 = short, 2 = long) */
698 16, /* bitsize */
699 FALSE, /* pc_relative */
700 0, /* bitpos */
701 complain_overflow_dont,/* complain_on_overflow */
702 bfd_elf_generic_reloc, /* special_function */
703 "R_ARM_MOVW_ABS_NC", /* name */
704 FALSE, /* partial_inplace */
39623e12
PB		 705 0x000f0fff, /* src_mask */
706 0x000f0fff, /* dst_mask */
c19d1205
ZW		 707 FALSE), /* pcrel_offset */
708
709 HOWTO (R_ARM_MOVT_ABS, /* type */
710 0, /* rightshift */
711 2, /* size (0 = byte, 1 = short, 2 = long) */
712 16, /* bitsize */
713 FALSE, /* pc_relative */
714 0, /* bitpos */
715 complain_overflow_bitfield,/* complain_on_overflow */
716 bfd_elf_generic_reloc, /* special_function */
717 "R_ARM_MOVT_ABS", /* name */
718 FALSE, /* partial_inplace */
39623e12
PB		 719 0x000f0fff, /* src_mask */
720 0x000f0fff, /* dst_mask */
c19d1205
ZW		 721 FALSE), /* pcrel_offset */
722
723 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
724 0, /* rightshift */
725 2, /* size (0 = byte, 1 = short, 2 = long) */
726 16, /* bitsize */
727 TRUE, /* pc_relative */
728 0, /* bitpos */
729 complain_overflow_dont,/* complain_on_overflow */
730 bfd_elf_generic_reloc, /* special_function */
731 "R_ARM_MOVW_PREL_NC", /* name */
732 FALSE, /* partial_inplace */
39623e12
PB		 733 0x000f0fff, /* src_mask */
734 0x000f0fff, /* dst_mask */
c19d1205
ZW		 735 TRUE), /* pcrel_offset */
736
737 HOWTO (R_ARM_MOVT_PREL, /* type */
738 0, /* rightshift */
739 2, /* size (0 = byte, 1 = short, 2 = long) */
740 16, /* bitsize */
741 TRUE, /* pc_relative */
742 0, /* bitpos */
743 complain_overflow_bitfield,/* complain_on_overflow */
744 bfd_elf_generic_reloc, /* special_function */
745 "R_ARM_MOVT_PREL", /* name */
746 FALSE, /* partial_inplace */
39623e12
PB		 747 0x000f0fff, /* src_mask */
748 0x000f0fff, /* dst_mask */
c19d1205
ZW		 749 TRUE), /* pcrel_offset */
750
751 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
752 0, /* rightshift */
753 2, /* size (0 = byte, 1 = short, 2 = long) */
754 16, /* bitsize */
755 FALSE, /* pc_relative */
756 0, /* bitpos */
757 complain_overflow_dont,/* complain_on_overflow */
758 bfd_elf_generic_reloc, /* special_function */
759 "R_ARM_THM_MOVW_ABS_NC",/* name */
760 FALSE, /* partial_inplace */
761 0x040f70ff, /* src_mask */
762 0x040f70ff, /* dst_mask */
763 FALSE), /* pcrel_offset */
764
765 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
766 0, /* rightshift */
767 2, /* size (0 = byte, 1 = short, 2 = long) */
768 16, /* bitsize */
769 FALSE, /* pc_relative */
770 0, /* bitpos */
771 complain_overflow_bitfield,/* complain_on_overflow */
772 bfd_elf_generic_reloc, /* special_function */
773 "R_ARM_THM_MOVT_ABS", /* name */
774 FALSE, /* partial_inplace */
775 0x040f70ff, /* src_mask */
776 0x040f70ff, /* dst_mask */
777 FALSE), /* pcrel_offset */
778
779 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
780 0, /* rightshift */
781 2, /* size (0 = byte, 1 = short, 2 = long) */
782 16, /* bitsize */
783 TRUE, /* pc_relative */
784 0, /* bitpos */
785 complain_overflow_dont,/* complain_on_overflow */
786 bfd_elf_generic_reloc, /* special_function */
787 "R_ARM_THM_MOVW_PREL_NC",/* name */
788 FALSE, /* partial_inplace */
789 0x040f70ff, /* src_mask */
790 0x040f70ff, /* dst_mask */
791 TRUE), /* pcrel_offset */
792
793 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
794 0, /* rightshift */
795 2, /* size (0 = byte, 1 = short, 2 = long) */
796 16, /* bitsize */
797 TRUE, /* pc_relative */
798 0, /* bitpos */
799 complain_overflow_bitfield,/* complain_on_overflow */
800 bfd_elf_generic_reloc, /* special_function */
801 "R_ARM_THM_MOVT_PREL", /* name */
802 FALSE, /* partial_inplace */
803 0x040f70ff, /* src_mask */
804 0x040f70ff, /* dst_mask */
805 TRUE), /* pcrel_offset */
806
807 HOWTO (R_ARM_THM_JUMP19, /* type */
808 1, /* rightshift */
809 2, /* size (0 = byte, 1 = short, 2 = long) */
810 19, /* bitsize */
811 TRUE, /* pc_relative */
812 0, /* bitpos */
813 complain_overflow_signed,/* complain_on_overflow */
814 bfd_elf_generic_reloc, /* special_function */
815 "R_ARM_THM_JUMP19", /* name */
816 FALSE, /* partial_inplace */
817 0x043f2fff, /* src_mask */
818 0x043f2fff, /* dst_mask */
819 TRUE), /* pcrel_offset */
820
821 HOWTO (R_ARM_THM_JUMP6, /* type */
822 1, /* rightshift */
823 1, /* size (0 = byte, 1 = short, 2 = long) */
824 6, /* bitsize */
825 TRUE, /* pc_relative */
826 0, /* bitpos */
827 complain_overflow_unsigned,/* complain_on_overflow */
828 bfd_elf_generic_reloc, /* special_function */
829 "R_ARM_THM_JUMP6", /* name */
830 FALSE, /* partial_inplace */
831 0x02f8, /* src_mask */
832 0x02f8, /* dst_mask */
833 TRUE), /* pcrel_offset */
834
835 /* These are declared as 13-bit signed relocations because we can
836 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
837 versa. */
838 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
839 0, /* rightshift */
840 2, /* size (0 = byte, 1 = short, 2 = long) */
841 13, /* bitsize */
842 TRUE, /* pc_relative */
843 0, /* bitpos */
2cab6cc3 844 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 845 bfd_elf_generic_reloc, /* special_function */
846 "R_ARM_THM_ALU_PREL_11_0",/* name */
847 FALSE, /* partial_inplace */
2cab6cc3
MS		 848 0xffffffff, /* src_mask */
849 0xffffffff, /* dst_mask */
c19d1205
ZW		 850 TRUE), /* pcrel_offset */
851
852 HOWTO (R_ARM_THM_PC12, /* type */
853 0, /* rightshift */
854 2, /* size (0 = byte, 1 = short, 2 = long) */
855 13, /* bitsize */
856 TRUE, /* pc_relative */
857 0, /* bitpos */
2cab6cc3 858 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 859 bfd_elf_generic_reloc, /* special_function */
860 "R_ARM_THM_PC12", /* name */
861 FALSE, /* partial_inplace */
2cab6cc3
MS		 862 0xffffffff, /* src_mask */
863 0xffffffff, /* dst_mask */
c19d1205
ZW		 864 TRUE), /* pcrel_offset */
865
866 HOWTO (R_ARM_ABS32_NOI, /* type */
867 0, /* rightshift */
868 2, /* size (0 = byte, 1 = short, 2 = long) */
869 32, /* bitsize */
870 FALSE, /* pc_relative */
871 0, /* bitpos */
872 complain_overflow_dont,/* complain_on_overflow */
873 bfd_elf_generic_reloc, /* special_function */
874 "R_ARM_ABS32_NOI", /* name */
875 FALSE, /* partial_inplace */
876 0xffffffff, /* src_mask */
877 0xffffffff, /* dst_mask */
878 FALSE), /* pcrel_offset */
879
880 HOWTO (R_ARM_REL32_NOI, /* type */
881 0, /* rightshift */
882 2, /* size (0 = byte, 1 = short, 2 = long) */
883 32, /* bitsize */
884 TRUE, /* pc_relative */
885 0, /* bitpos */
886 complain_overflow_dont,/* complain_on_overflow */
887 bfd_elf_generic_reloc, /* special_function */
888 "R_ARM_REL32_NOI", /* name */
889 FALSE, /* partial_inplace */
890 0xffffffff, /* src_mask */
891 0xffffffff, /* dst_mask */
892 FALSE), /* pcrel_offset */
7f266840 893
4962c51a
MS		 894 /* Group relocations. */
895
896 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
897 0, /* rightshift */
898 2, /* size (0 = byte, 1 = short, 2 = long) */
899 32, /* bitsize */
900 TRUE, /* pc_relative */
901 0, /* bitpos */
902 complain_overflow_dont,/* complain_on_overflow */
903 bfd_elf_generic_reloc, /* special_function */
904 "R_ARM_ALU_PC_G0_NC", /* name */
905 FALSE, /* partial_inplace */
906 0xffffffff, /* src_mask */
907 0xffffffff, /* dst_mask */
908 TRUE), /* pcrel_offset */
909
07d6d2b8 910 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 911 0, /* rightshift */
912 2, /* size (0 = byte, 1 = short, 2 = long) */
913 32, /* bitsize */
914 TRUE, /* pc_relative */
915 0, /* bitpos */
916 complain_overflow_dont,/* complain_on_overflow */
917 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 918 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 919 FALSE, /* partial_inplace */
920 0xffffffff, /* src_mask */
921 0xffffffff, /* dst_mask */
922 TRUE), /* pcrel_offset */
923
924 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
925 0, /* rightshift */
926 2, /* size (0 = byte, 1 = short, 2 = long) */
927 32, /* bitsize */
928 TRUE, /* pc_relative */
929 0, /* bitpos */
930 complain_overflow_dont,/* complain_on_overflow */
931 bfd_elf_generic_reloc, /* special_function */
932 "R_ARM_ALU_PC_G1_NC", /* name */
933 FALSE, /* partial_inplace */
934 0xffffffff, /* src_mask */
935 0xffffffff, /* dst_mask */
936 TRUE), /* pcrel_offset */
937
07d6d2b8 938 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 939 0, /* rightshift */
940 2, /* size (0 = byte, 1 = short, 2 = long) */
941 32, /* bitsize */
942 TRUE, /* pc_relative */
943 0, /* bitpos */
944 complain_overflow_dont,/* complain_on_overflow */
945 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 946 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 947 FALSE, /* partial_inplace */
948 0xffffffff, /* src_mask */
949 0xffffffff, /* dst_mask */
950 TRUE), /* pcrel_offset */
951
07d6d2b8 952 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 953 0, /* rightshift */
954 2, /* size (0 = byte, 1 = short, 2 = long) */
955 32, /* bitsize */
956 TRUE, /* pc_relative */
957 0, /* bitpos */
958 complain_overflow_dont,/* complain_on_overflow */
959 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 960 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 961 FALSE, /* partial_inplace */
962 0xffffffff, /* src_mask */
963 0xffffffff, /* dst_mask */
964 TRUE), /* pcrel_offset */
965
07d6d2b8 966 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 967 0, /* rightshift */
968 2, /* size (0 = byte, 1 = short, 2 = long) */
969 32, /* bitsize */
970 TRUE, /* pc_relative */
971 0, /* bitpos */
972 complain_overflow_dont,/* complain_on_overflow */
973 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 974 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 975 FALSE, /* partial_inplace */
976 0xffffffff, /* src_mask */
977 0xffffffff, /* dst_mask */
978 TRUE), /* pcrel_offset */
979
07d6d2b8 980 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 981 0, /* rightshift */
982 2, /* size (0 = byte, 1 = short, 2 = long) */
983 32, /* bitsize */
984 TRUE, /* pc_relative */
985 0, /* bitpos */
986 complain_overflow_dont,/* complain_on_overflow */
987 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 988 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 989 FALSE, /* partial_inplace */
990 0xffffffff, /* src_mask */
991 0xffffffff, /* dst_mask */
992 TRUE), /* pcrel_offset */
993
07d6d2b8 994 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 995 0, /* rightshift */
996 2, /* size (0 = byte, 1 = short, 2 = long) */
997 32, /* bitsize */
998 TRUE, /* pc_relative */
999 0, /* bitpos */
1000 complain_overflow_dont,/* complain_on_overflow */
1001 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1002 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1003 FALSE, /* partial_inplace */
1004 0xffffffff, /* src_mask */
1005 0xffffffff, /* dst_mask */
1006 TRUE), /* pcrel_offset */
1007
07d6d2b8 1008 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1009 0, /* rightshift */
1010 2, /* size (0 = byte, 1 = short, 2 = long) */
1011 32, /* bitsize */
1012 TRUE, /* pc_relative */
1013 0, /* bitpos */
1014 complain_overflow_dont,/* complain_on_overflow */
1015 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1016 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1017 FALSE, /* partial_inplace */
1018 0xffffffff, /* src_mask */
1019 0xffffffff, /* dst_mask */
1020 TRUE), /* pcrel_offset */
1021
07d6d2b8 1022 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1023 0, /* rightshift */
1024 2, /* size (0 = byte, 1 = short, 2 = long) */
1025 32, /* bitsize */
1026 TRUE, /* pc_relative */
1027 0, /* bitpos */
1028 complain_overflow_dont,/* complain_on_overflow */
1029 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1030 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1031 FALSE, /* partial_inplace */
1032 0xffffffff, /* src_mask */
1033 0xffffffff, /* dst_mask */
1034 TRUE), /* pcrel_offset */
1035
07d6d2b8 1036 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1037 0, /* rightshift */
1038 2, /* size (0 = byte, 1 = short, 2 = long) */
1039 32, /* bitsize */
1040 TRUE, /* pc_relative */
1041 0, /* bitpos */
1042 complain_overflow_dont,/* complain_on_overflow */
1043 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1044 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1045 FALSE, /* partial_inplace */
1046 0xffffffff, /* src_mask */
1047 0xffffffff, /* dst_mask */
1048 TRUE), /* pcrel_offset */
1049
07d6d2b8 1050 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1051 0, /* rightshift */
1052 2, /* size (0 = byte, 1 = short, 2 = long) */
1053 32, /* bitsize */
1054 TRUE, /* pc_relative */
1055 0, /* bitpos */
1056 complain_overflow_dont,/* complain_on_overflow */
1057 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1058 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1059 FALSE, /* partial_inplace */
1060 0xffffffff, /* src_mask */
1061 0xffffffff, /* dst_mask */
1062 TRUE), /* pcrel_offset */
1063
07d6d2b8 1064 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1065 0, /* rightshift */
1066 2, /* size (0 = byte, 1 = short, 2 = long) */
1067 32, /* bitsize */
1068 TRUE, /* pc_relative */
1069 0, /* bitpos */
1070 complain_overflow_dont,/* complain_on_overflow */
1071 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1072 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1073 FALSE, /* partial_inplace */
1074 0xffffffff, /* src_mask */
1075 0xffffffff, /* dst_mask */
1076 TRUE), /* pcrel_offset */
1077
07d6d2b8 1078 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1079 0, /* rightshift */
1080 2, /* size (0 = byte, 1 = short, 2 = long) */
1081 32, /* bitsize */
1082 TRUE, /* pc_relative */
1083 0, /* bitpos */
1084 complain_overflow_dont,/* complain_on_overflow */
1085 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1086 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1087 FALSE, /* partial_inplace */
1088 0xffffffff, /* src_mask */
1089 0xffffffff, /* dst_mask */
1090 TRUE), /* pcrel_offset */
1091
07d6d2b8 1092 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1093 0, /* rightshift */
1094 2, /* size (0 = byte, 1 = short, 2 = long) */
1095 32, /* bitsize */
1096 TRUE, /* pc_relative */
1097 0, /* bitpos */
1098 complain_overflow_dont,/* complain_on_overflow */
1099 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1100 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1101 FALSE, /* partial_inplace */
1102 0xffffffff, /* src_mask */
1103 0xffffffff, /* dst_mask */
1104 TRUE), /* pcrel_offset */
1105
07d6d2b8 1106 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1107 0, /* rightshift */
1108 2, /* size (0 = byte, 1 = short, 2 = long) */
1109 32, /* bitsize */
1110 TRUE, /* pc_relative */
1111 0, /* bitpos */
1112 complain_overflow_dont,/* complain_on_overflow */
1113 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1114 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1115 FALSE, /* partial_inplace */
1116 0xffffffff, /* src_mask */
1117 0xffffffff, /* dst_mask */
1118 TRUE), /* pcrel_offset */
1119
07d6d2b8 1120 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1121 0, /* rightshift */
1122 2, /* size (0 = byte, 1 = short, 2 = long) */
1123 32, /* bitsize */
1124 TRUE, /* pc_relative */
1125 0, /* bitpos */
1126 complain_overflow_dont,/* complain_on_overflow */
1127 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1128 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1129 FALSE, /* partial_inplace */
1130 0xffffffff, /* src_mask */
1131 0xffffffff, /* dst_mask */
1132 TRUE), /* pcrel_offset */
1133
07d6d2b8 1134 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1135 0, /* rightshift */
1136 2, /* size (0 = byte, 1 = short, 2 = long) */
1137 32, /* bitsize */
1138 TRUE, /* pc_relative */
1139 0, /* bitpos */
1140 complain_overflow_dont,/* complain_on_overflow */
1141 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1142 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1143 FALSE, /* partial_inplace */
1144 0xffffffff, /* src_mask */
1145 0xffffffff, /* dst_mask */
1146 TRUE), /* pcrel_offset */
1147
07d6d2b8 1148 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1149 0, /* rightshift */
1150 2, /* size (0 = byte, 1 = short, 2 = long) */
1151 32, /* bitsize */
1152 TRUE, /* pc_relative */
1153 0, /* bitpos */
1154 complain_overflow_dont,/* complain_on_overflow */
1155 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1156 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1157 FALSE, /* partial_inplace */
1158 0xffffffff, /* src_mask */
1159 0xffffffff, /* dst_mask */
1160 TRUE), /* pcrel_offset */
1161
07d6d2b8 1162 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1163 0, /* rightshift */
1164 2, /* size (0 = byte, 1 = short, 2 = long) */
1165 32, /* bitsize */
1166 TRUE, /* pc_relative */
1167 0, /* bitpos */
1168 complain_overflow_dont,/* complain_on_overflow */
1169 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1170 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1171 FALSE, /* partial_inplace */
1172 0xffffffff, /* src_mask */
1173 0xffffffff, /* dst_mask */
1174 TRUE), /* pcrel_offset */
1175
07d6d2b8 1176 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1177 0, /* rightshift */
1178 2, /* size (0 = byte, 1 = short, 2 = long) */
1179 32, /* bitsize */
1180 TRUE, /* pc_relative */
1181 0, /* bitpos */
1182 complain_overflow_dont,/* complain_on_overflow */
1183 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1184 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1185 FALSE, /* partial_inplace */
1186 0xffffffff, /* src_mask */
1187 0xffffffff, /* dst_mask */
1188 TRUE), /* pcrel_offset */
1189
07d6d2b8 1190 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1191 0, /* rightshift */
1192 2, /* size (0 = byte, 1 = short, 2 = long) */
1193 32, /* bitsize */
1194 TRUE, /* pc_relative */
1195 0, /* bitpos */
1196 complain_overflow_dont,/* complain_on_overflow */
1197 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1198 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1199 FALSE, /* partial_inplace */
1200 0xffffffff, /* src_mask */
1201 0xffffffff, /* dst_mask */
1202 TRUE), /* pcrel_offset */
1203
07d6d2b8 1204 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1205 0, /* rightshift */
1206 2, /* size (0 = byte, 1 = short, 2 = long) */
1207 32, /* bitsize */
1208 TRUE, /* pc_relative */
1209 0, /* bitpos */
1210 complain_overflow_dont,/* complain_on_overflow */
1211 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1212 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1213 FALSE, /* partial_inplace */
1214 0xffffffff, /* src_mask */
1215 0xffffffff, /* dst_mask */
1216 TRUE), /* pcrel_offset */
1217
07d6d2b8 1218 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1219 0, /* rightshift */
1220 2, /* size (0 = byte, 1 = short, 2 = long) */
1221 32, /* bitsize */
1222 TRUE, /* pc_relative */
1223 0, /* bitpos */
1224 complain_overflow_dont,/* complain_on_overflow */
1225 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1226 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1227 FALSE, /* partial_inplace */
1228 0xffffffff, /* src_mask */
1229 0xffffffff, /* dst_mask */
1230 TRUE), /* pcrel_offset */
1231
07d6d2b8 1232 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1233 0, /* rightshift */
1234 2, /* size (0 = byte, 1 = short, 2 = long) */
1235 32, /* bitsize */
1236 TRUE, /* pc_relative */
1237 0, /* bitpos */
1238 complain_overflow_dont,/* complain_on_overflow */
1239 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1240 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1241 FALSE, /* partial_inplace */
1242 0xffffffff, /* src_mask */
1243 0xffffffff, /* dst_mask */
1244 TRUE), /* pcrel_offset */
1245
07d6d2b8 1246 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1247 0, /* rightshift */
1248 2, /* size (0 = byte, 1 = short, 2 = long) */
1249 32, /* bitsize */
1250 TRUE, /* pc_relative */
1251 0, /* bitpos */
1252 complain_overflow_dont,/* complain_on_overflow */
1253 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1254 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1255 FALSE, /* partial_inplace */
1256 0xffffffff, /* src_mask */
1257 0xffffffff, /* dst_mask */
1258 TRUE), /* pcrel_offset */
1259
07d6d2b8 1260 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1261 0, /* rightshift */
1262 2, /* size (0 = byte, 1 = short, 2 = long) */
1263 32, /* bitsize */
1264 TRUE, /* pc_relative */
1265 0, /* bitpos */
1266 complain_overflow_dont,/* complain_on_overflow */
1267 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1268 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1269 FALSE, /* partial_inplace */
1270 0xffffffff, /* src_mask */
1271 0xffffffff, /* dst_mask */
1272 TRUE), /* pcrel_offset */
1273
1274 /* End of group relocations. */
c19d1205 1275
c19d1205
ZW		 1276 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1277 0, /* rightshift */
1278 2, /* size (0 = byte, 1 = short, 2 = long) */
1279 16, /* bitsize */
1280 FALSE, /* pc_relative */
1281 0, /* bitpos */
1282 complain_overflow_dont,/* complain_on_overflow */
1283 bfd_elf_generic_reloc, /* special_function */
1284 "R_ARM_MOVW_BREL_NC", /* name */
1285 FALSE, /* partial_inplace */
1286 0x0000ffff, /* src_mask */
1287 0x0000ffff, /* dst_mask */
1288 FALSE), /* pcrel_offset */
1289
1290 HOWTO (R_ARM_MOVT_BREL, /* type */
1291 0, /* rightshift */
1292 2, /* size (0 = byte, 1 = short, 2 = long) */
1293 16, /* bitsize */
1294 FALSE, /* pc_relative */
1295 0, /* bitpos */
1296 complain_overflow_bitfield,/* complain_on_overflow */
1297 bfd_elf_generic_reloc, /* special_function */
1298 "R_ARM_MOVT_BREL", /* name */
1299 FALSE, /* partial_inplace */
1300 0x0000ffff, /* src_mask */
1301 0x0000ffff, /* dst_mask */
1302 FALSE), /* pcrel_offset */
1303
1304 HOWTO (R_ARM_MOVW_BREL, /* type */
1305 0, /* rightshift */
1306 2, /* size (0 = byte, 1 = short, 2 = long) */
1307 16, /* bitsize */
1308 FALSE, /* pc_relative */
1309 0, /* bitpos */
1310 complain_overflow_dont,/* complain_on_overflow */
1311 bfd_elf_generic_reloc, /* special_function */
1312 "R_ARM_MOVW_BREL", /* name */
1313 FALSE, /* partial_inplace */
1314 0x0000ffff, /* src_mask */
1315 0x0000ffff, /* dst_mask */
1316 FALSE), /* pcrel_offset */
1317
1318 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1319 0, /* rightshift */
1320 2, /* size (0 = byte, 1 = short, 2 = long) */
1321 16, /* bitsize */
1322 FALSE, /* pc_relative */
1323 0, /* bitpos */
1324 complain_overflow_dont,/* complain_on_overflow */
1325 bfd_elf_generic_reloc, /* special_function */
1326 "R_ARM_THM_MOVW_BREL_NC",/* name */
1327 FALSE, /* partial_inplace */
1328 0x040f70ff, /* src_mask */
1329 0x040f70ff, /* dst_mask */
1330 FALSE), /* pcrel_offset */
1331
1332 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1333 0, /* rightshift */
1334 2, /* size (0 = byte, 1 = short, 2 = long) */
1335 16, /* bitsize */
1336 FALSE, /* pc_relative */
1337 0, /* bitpos */
1338 complain_overflow_bitfield,/* complain_on_overflow */
1339 bfd_elf_generic_reloc, /* special_function */
1340 "R_ARM_THM_MOVT_BREL", /* name */
1341 FALSE, /* partial_inplace */
1342 0x040f70ff, /* src_mask */
1343 0x040f70ff, /* dst_mask */
1344 FALSE), /* pcrel_offset */
1345
1346 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1347 0, /* rightshift */
1348 2, /* size (0 = byte, 1 = short, 2 = long) */
1349 16, /* bitsize */
1350 FALSE, /* pc_relative */
1351 0, /* bitpos */
1352 complain_overflow_dont,/* complain_on_overflow */
1353 bfd_elf_generic_reloc, /* special_function */
1354 "R_ARM_THM_MOVW_BREL", /* name */
1355 FALSE, /* partial_inplace */
1356 0x040f70ff, /* src_mask */
1357 0x040f70ff, /* dst_mask */
1358 FALSE), /* pcrel_offset */
1359
0855e32b
NS		 1360 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1361 0, /* rightshift */
1362 2, /* size (0 = byte, 1 = short, 2 = long) */
1363 32, /* bitsize */
1364 FALSE, /* pc_relative */
1365 0, /* bitpos */
1366 complain_overflow_bitfield,/* complain_on_overflow */
1367 NULL, /* special_function */
1368 "R_ARM_TLS_GOTDESC", /* name */
1369 TRUE, /* partial_inplace */
1370 0xffffffff, /* src_mask */
1371 0xffffffff, /* dst_mask */
1372 FALSE), /* pcrel_offset */
1373
1374 HOWTO (R_ARM_TLS_CALL, /* type */
1375 0, /* rightshift */
1376 2, /* size (0 = byte, 1 = short, 2 = long) */
1377 24, /* bitsize */
1378 FALSE, /* pc_relative */
1379 0, /* bitpos */
1380 complain_overflow_dont,/* complain_on_overflow */
1381 bfd_elf_generic_reloc, /* special_function */
1382 "R_ARM_TLS_CALL", /* name */
1383 FALSE, /* partial_inplace */
1384 0x00ffffff, /* src_mask */
1385 0x00ffffff, /* dst_mask */
1386 FALSE), /* pcrel_offset */
1387
1388 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1389 0, /* rightshift */
1390 2, /* size (0 = byte, 1 = short, 2 = long) */
1391 0, /* bitsize */
1392 FALSE, /* pc_relative */
1393 0, /* bitpos */
1394 complain_overflow_bitfield,/* complain_on_overflow */
1395 bfd_elf_generic_reloc, /* special_function */
1396 "R_ARM_TLS_DESCSEQ", /* name */
1397 FALSE, /* partial_inplace */
1398 0x00000000, /* src_mask */
1399 0x00000000, /* dst_mask */
1400 FALSE), /* pcrel_offset */
1401
1402 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1403 0, /* rightshift */
1404 2, /* size (0 = byte, 1 = short, 2 = long) */
1405 24, /* bitsize */
1406 FALSE, /* pc_relative */
1407 0, /* bitpos */
1408 complain_overflow_dont,/* complain_on_overflow */
1409 bfd_elf_generic_reloc, /* special_function */
1410 "R_ARM_THM_TLS_CALL", /* name */
1411 FALSE, /* partial_inplace */
1412 0x07ff07ff, /* src_mask */
1413 0x07ff07ff, /* dst_mask */
1414 FALSE), /* pcrel_offset */
c19d1205
ZW		 1415
1416 HOWTO (R_ARM_PLT32_ABS, /* type */
1417 0, /* rightshift */
1418 2, /* size (0 = byte, 1 = short, 2 = long) */
1419 32, /* bitsize */
1420 FALSE, /* pc_relative */
1421 0, /* bitpos */
1422 complain_overflow_dont,/* complain_on_overflow */
1423 bfd_elf_generic_reloc, /* special_function */
1424 "R_ARM_PLT32_ABS", /* name */
1425 FALSE, /* partial_inplace */
1426 0xffffffff, /* src_mask */
1427 0xffffffff, /* dst_mask */
1428 FALSE), /* pcrel_offset */
1429
1430 HOWTO (R_ARM_GOT_ABS, /* type */
1431 0, /* rightshift */
1432 2, /* size (0 = byte, 1 = short, 2 = long) */
1433 32, /* bitsize */
1434 FALSE, /* pc_relative */
1435 0, /* bitpos */
1436 complain_overflow_dont,/* complain_on_overflow */
1437 bfd_elf_generic_reloc, /* special_function */
1438 "R_ARM_GOT_ABS", /* name */
1439 FALSE, /* partial_inplace */
1440 0xffffffff, /* src_mask */
1441 0xffffffff, /* dst_mask */
1442 FALSE), /* pcrel_offset */
1443
1444 HOWTO (R_ARM_GOT_PREL, /* type */
1445 0, /* rightshift */
1446 2, /* size (0 = byte, 1 = short, 2 = long) */
1447 32, /* bitsize */
1448 TRUE, /* pc_relative */
1449 0, /* bitpos */
1450 complain_overflow_dont, /* complain_on_overflow */
1451 bfd_elf_generic_reloc, /* special_function */
1452 "R_ARM_GOT_PREL", /* name */
1453 FALSE, /* partial_inplace */
1454 0xffffffff, /* src_mask */
1455 0xffffffff, /* dst_mask */
1456 TRUE), /* pcrel_offset */
1457
1458 HOWTO (R_ARM_GOT_BREL12, /* type */
1459 0, /* rightshift */
1460 2, /* size (0 = byte, 1 = short, 2 = long) */
1461 12, /* bitsize */
1462 FALSE, /* pc_relative */
1463 0, /* bitpos */
1464 complain_overflow_bitfield,/* complain_on_overflow */
1465 bfd_elf_generic_reloc, /* special_function */
1466 "R_ARM_GOT_BREL12", /* name */
1467 FALSE, /* partial_inplace */
1468 0x00000fff, /* src_mask */
1469 0x00000fff, /* dst_mask */
1470 FALSE), /* pcrel_offset */
1471
1472 HOWTO (R_ARM_GOTOFF12, /* type */
1473 0, /* rightshift */
1474 2, /* size (0 = byte, 1 = short, 2 = long) */
1475 12, /* bitsize */
1476 FALSE, /* pc_relative */
1477 0, /* bitpos */
1478 complain_overflow_bitfield,/* complain_on_overflow */
1479 bfd_elf_generic_reloc, /* special_function */
1480 "R_ARM_GOTOFF12", /* name */
1481 FALSE, /* partial_inplace */
1482 0x00000fff, /* src_mask */
1483 0x00000fff, /* dst_mask */
1484 FALSE), /* pcrel_offset */
1485
07d6d2b8 1486 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1487
1488 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1489 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1490 0, /* rightshift */
1491 2, /* size (0 = byte, 1 = short, 2 = long) */
1492 0, /* bitsize */
1493 FALSE, /* pc_relative */
1494 0, /* bitpos */
99059e56 1495 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1496 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1497 "R_ARM_GNU_VTENTRY", /* name */
1498 FALSE, /* partial_inplace */
1499 0, /* src_mask */
1500 0, /* dst_mask */
1501 FALSE), /* pcrel_offset */
c19d1205
ZW		 1502
1503 /* GNU extension to record C++ vtable hierarchy */
1504 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1505 0, /* rightshift */
1506 2, /* size (0 = byte, 1 = short, 2 = long) */
1507 0, /* bitsize */
1508 FALSE, /* pc_relative */
1509 0, /* bitpos */
99059e56 1510 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1511 NULL, /* special_function */
99059e56 1512 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1513 FALSE, /* partial_inplace */
1514 0, /* src_mask */
1515 0, /* dst_mask */
1516 FALSE), /* pcrel_offset */
c19d1205
ZW		 1517
1518 HOWTO (R_ARM_THM_JUMP11, /* type */
1519 1, /* rightshift */
1520 1, /* size (0 = byte, 1 = short, 2 = long) */
1521 11, /* bitsize */
1522 TRUE, /* pc_relative */
1523 0, /* bitpos */
1524 complain_overflow_signed, /* complain_on_overflow */
1525 bfd_elf_generic_reloc, /* special_function */
1526 "R_ARM_THM_JUMP11", /* name */
1527 FALSE, /* partial_inplace */
1528 0x000007ff, /* src_mask */
1529 0x000007ff, /* dst_mask */
1530 TRUE), /* pcrel_offset */
1531
1532 HOWTO (R_ARM_THM_JUMP8, /* type */
1533 1, /* rightshift */
1534 1, /* size (0 = byte, 1 = short, 2 = long) */
1535 8, /* bitsize */
1536 TRUE, /* pc_relative */
1537 0, /* bitpos */
1538 complain_overflow_signed, /* complain_on_overflow */
1539 bfd_elf_generic_reloc, /* special_function */
1540 "R_ARM_THM_JUMP8", /* name */
1541 FALSE, /* partial_inplace */
1542 0x000000ff, /* src_mask */
1543 0x000000ff, /* dst_mask */
1544 TRUE), /* pcrel_offset */
ba93b8ac 1545
c19d1205
ZW		 1546 /* TLS relocations */
1547 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1548 0, /* rightshift */
1549 2, /* size (0 = byte, 1 = short, 2 = long) */
1550 32, /* bitsize */
1551 FALSE, /* pc_relative */
1552 0, /* bitpos */
99059e56
RM		 1553 complain_overflow_bitfield,/* complain_on_overflow */
1554 NULL, /* special_function */
1555 "R_ARM_TLS_GD32", /* name */
1556 TRUE, /* partial_inplace */
1557 0xffffffff, /* src_mask */
1558 0xffffffff, /* dst_mask */
07d6d2b8 1559 FALSE), /* pcrel_offset */
ba93b8ac 1560
ba93b8ac 1561 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1562 0, /* rightshift */
1563 2, /* size (0 = byte, 1 = short, 2 = long) */
1564 32, /* bitsize */
1565 FALSE, /* pc_relative */
1566 0, /* bitpos */
99059e56
RM		 1567 complain_overflow_bitfield,/* complain_on_overflow */
1568 bfd_elf_generic_reloc, /* special_function */
1569 "R_ARM_TLS_LDM32", /* name */
1570 TRUE, /* partial_inplace */
1571 0xffffffff, /* src_mask */
1572 0xffffffff, /* dst_mask */
07d6d2b8 1573 FALSE), /* pcrel_offset */
ba93b8ac 1574
c19d1205 1575 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1576 0, /* rightshift */
1577 2, /* size (0 = byte, 1 = short, 2 = long) */
1578 32, /* bitsize */
1579 FALSE, /* pc_relative */
1580 0, /* bitpos */
99059e56
RM		 1581 complain_overflow_bitfield,/* complain_on_overflow */
1582 bfd_elf_generic_reloc, /* special_function */
1583 "R_ARM_TLS_LDO32", /* name */
1584 TRUE, /* partial_inplace */
1585 0xffffffff, /* src_mask */
1586 0xffffffff, /* dst_mask */
07d6d2b8 1587 FALSE), /* pcrel_offset */
ba93b8ac 1588
ba93b8ac 1589 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1590 0, /* rightshift */
1591 2, /* size (0 = byte, 1 = short, 2 = long) */
1592 32, /* bitsize */
1593 FALSE, /* pc_relative */
1594 0, /* bitpos */
99059e56
RM		 1595 complain_overflow_bitfield,/* complain_on_overflow */
1596 NULL, /* special_function */
1597 "R_ARM_TLS_IE32", /* name */
1598 TRUE, /* partial_inplace */
1599 0xffffffff, /* src_mask */
1600 0xffffffff, /* dst_mask */
07d6d2b8 1601 FALSE), /* pcrel_offset */
7f266840 1602
c19d1205 1603 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1604 0, /* rightshift */
1605 2, /* size (0 = byte, 1 = short, 2 = long) */
1606 32, /* bitsize */
1607 FALSE, /* pc_relative */
1608 0, /* bitpos */
99059e56 1609 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1610 NULL, /* special_function */
99059e56
RM		 1611 "R_ARM_TLS_LE32", /* name */
1612 TRUE, /* partial_inplace */
1613 0xffffffff, /* src_mask */
1614 0xffffffff, /* dst_mask */
07d6d2b8 1615 FALSE), /* pcrel_offset */
7f266840 1616
c19d1205
ZW		 1617 HOWTO (R_ARM_TLS_LDO12, /* type */
1618 0, /* rightshift */
1619 2, /* size (0 = byte, 1 = short, 2 = long) */
1620 12, /* bitsize */
1621 FALSE, /* pc_relative */
7f266840 1622 0, /* bitpos */
c19d1205 1623 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1624 bfd_elf_generic_reloc, /* special_function */
c19d1205 1625 "R_ARM_TLS_LDO12", /* name */
7f266840 1626 FALSE, /* partial_inplace */
c19d1205
ZW		 1627 0x00000fff, /* src_mask */
1628 0x00000fff, /* dst_mask */
1629 FALSE), /* pcrel_offset */
7f266840 1630
c19d1205
ZW		 1631 HOWTO (R_ARM_TLS_LE12, /* type */
1632 0, /* rightshift */
1633 2, /* size (0 = byte, 1 = short, 2 = long) */
1634 12, /* bitsize */
1635 FALSE, /* pc_relative */
7f266840 1636 0, /* bitpos */
c19d1205 1637 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1638 bfd_elf_generic_reloc, /* special_function */
c19d1205 1639 "R_ARM_TLS_LE12", /* name */
7f266840 1640 FALSE, /* partial_inplace */
c19d1205
ZW		 1641 0x00000fff, /* src_mask */
1642 0x00000fff, /* dst_mask */
1643 FALSE), /* pcrel_offset */
7f266840 1644
c19d1205 1645 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1646 0, /* rightshift */
1647 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1648 12, /* bitsize */
1649 FALSE, /* pc_relative */
7f266840 1650 0, /* bitpos */
c19d1205 1651 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1652 bfd_elf_generic_reloc, /* special_function */
c19d1205 1653 "R_ARM_TLS_IE12GP", /* name */
7f266840 1654 FALSE, /* partial_inplace */
c19d1205
ZW		 1655 0x00000fff, /* src_mask */
1656 0x00000fff, /* dst_mask */
1657 FALSE), /* pcrel_offset */
0855e32b 1658
34e77a92 1659 /* 112-127 private relocations. */
0855e32b
NS		 1660 EMPTY_HOWTO (112),
1661 EMPTY_HOWTO (113),
1662 EMPTY_HOWTO (114),
1663 EMPTY_HOWTO (115),
1664 EMPTY_HOWTO (116),
1665 EMPTY_HOWTO (117),
1666 EMPTY_HOWTO (118),
1667 EMPTY_HOWTO (119),
1668 EMPTY_HOWTO (120),
1669 EMPTY_HOWTO (121),
1670 EMPTY_HOWTO (122),
1671 EMPTY_HOWTO (123),
1672 EMPTY_HOWTO (124),
1673 EMPTY_HOWTO (125),
1674 EMPTY_HOWTO (126),
1675 EMPTY_HOWTO (127),
34e77a92
RS		 1676
1677 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1678 EMPTY_HOWTO (128),
1679
1680 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1681 0, /* rightshift */
1682 1, /* size (0 = byte, 1 = short, 2 = long) */
1683 0, /* bitsize */
1684 FALSE, /* pc_relative */
1685 0, /* bitpos */
1686 complain_overflow_bitfield,/* complain_on_overflow */
1687 bfd_elf_generic_reloc, /* special_function */
1688 "R_ARM_THM_TLS_DESCSEQ",/* name */
1689 FALSE, /* partial_inplace */
1690 0x00000000, /* src_mask */
1691 0x00000000, /* dst_mask */
1692 FALSE), /* pcrel_offset */
72d98d16
MG		 1693 EMPTY_HOWTO (130),
1694 EMPTY_HOWTO (131),
1695 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1696 0, /* rightshift. */
1697 1, /* size (0 = byte, 1 = short, 2 = long). */
1698 16, /* bitsize. */
1699 FALSE, /* pc_relative. */
1700 0, /* bitpos. */
1701 complain_overflow_bitfield,/* complain_on_overflow. */
1702 bfd_elf_generic_reloc, /* special_function. */
1703 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1704 FALSE, /* partial_inplace. */
1705 0x00000000, /* src_mask. */
1706 0x00000000, /* dst_mask. */
1707 FALSE), /* pcrel_offset. */
1708 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1709 0, /* rightshift. */
1710 1, /* size (0 = byte, 1 = short, 2 = long). */
1711 16, /* bitsize. */
1712 FALSE, /* pc_relative. */
1713 0, /* bitpos. */
1714 complain_overflow_bitfield,/* complain_on_overflow. */
1715 bfd_elf_generic_reloc, /* special_function. */
1716 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1717 FALSE, /* partial_inplace. */
1718 0x00000000, /* src_mask. */
1719 0x00000000, /* dst_mask. */
1720 FALSE), /* pcrel_offset. */
1721 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1722 0, /* rightshift. */
1723 1, /* size (0 = byte, 1 = short, 2 = long). */
1724 16, /* bitsize. */
1725 FALSE, /* pc_relative. */
1726 0, /* bitpos. */
1727 complain_overflow_bitfield,/* complain_on_overflow. */
1728 bfd_elf_generic_reloc, /* special_function. */
1729 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1730 FALSE, /* partial_inplace. */
1731 0x00000000, /* src_mask. */
1732 0x00000000, /* dst_mask. */
1733 FALSE), /* pcrel_offset. */
1734 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1735 0, /* rightshift. */
1736 1, /* size (0 = byte, 1 = short, 2 = long). */
1737 16, /* bitsize. */
1738 FALSE, /* pc_relative. */
1739 0, /* bitpos. */
1740 complain_overflow_bitfield,/* complain_on_overflow. */
1741 bfd_elf_generic_reloc, /* special_function. */
1742 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1743 FALSE, /* partial_inplace. */
1744 0x00000000, /* src_mask. */
1745 0x00000000, /* dst_mask. */
1746 FALSE), /* pcrel_offset. */
e5d6e09e
AV		 1747 /* Relocations for Armv8.1-M Mainline. */
1748 HOWTO (R_ARM_THM_BF16, /* type. */
1749 0, /* rightshift. */
1750 1, /* size (0 = byte, 1 = short, 2 = long). */
1751 16, /* bitsize. */
1752 TRUE, /* pc_relative. */
1753 0, /* bitpos. */
1754 complain_overflow_dont,/* do not complain_on_overflow. */
1755 bfd_elf_generic_reloc, /* special_function. */
1756 "R_ARM_THM_BF16", /* name. */
1757 FALSE, /* partial_inplace. */
1758 0x001f0ffe, /* src_mask. */
1759 0x001f0ffe, /* dst_mask. */
1760 TRUE), /* pcrel_offset. */
1889da70
AV		 1761 HOWTO (R_ARM_THM_BF12, /* type. */
1762 0, /* rightshift. */
1763 1, /* size (0 = byte, 1 = short, 2 = long). */
1764 12, /* bitsize. */
1765 TRUE, /* pc_relative. */
1766 0, /* bitpos. */
1767 complain_overflow_dont,/* do not complain_on_overflow. */
1768 bfd_elf_generic_reloc, /* special_function. */
1769 "R_ARM_THM_BF12", /* name. */
1770 FALSE, /* partial_inplace. */
1771 0x00010ffe, /* src_mask. */
1772 0x00010ffe, /* dst_mask. */
1773 TRUE), /* pcrel_offset. */
1caf72a5
AV		 1774 HOWTO (R_ARM_THM_BF18, /* type. */
1775 0, /* rightshift. */
1776 1, /* size (0 = byte, 1 = short, 2 = long). */
1777 18, /* bitsize. */
1778 TRUE, /* pc_relative. */
1779 0, /* bitpos. */
1780 complain_overflow_dont,/* do not complain_on_overflow. */
1781 bfd_elf_generic_reloc, /* special_function. */
1782 "R_ARM_THM_BF18", /* name. */
1783 FALSE, /* partial_inplace. */
1784 0x007f0ffe, /* src_mask. */
1785 0x007f0ffe, /* dst_mask. */
1786 TRUE), /* pcrel_offset. */
c19d1205
ZW		 1787};
1788
34e77a92 1789/* 160 onwards: */
5c5a4843 1790static reloc_howto_type elf32_arm_howto_table_2[8] =
34e77a92
RS		 1791{
1792 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1793 0, /* rightshift */
1794 2, /* size (0 = byte, 1 = short, 2 = long) */
1795 32, /* bitsize */
1796 FALSE, /* pc_relative */
1797 0, /* bitpos */
99059e56
RM		 1798 complain_overflow_bitfield,/* complain_on_overflow */
1799 bfd_elf_generic_reloc, /* special_function */
1800 "R_ARM_IRELATIVE", /* name */
1801 TRUE, /* partial_inplace */
1802 0xffffffff, /* src_mask */
1803 0xffffffff, /* dst_mask */
188fd7ae
CL		 1804 FALSE), /* pcrel_offset */
1805 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1806 0, /* rightshift */
1807 2, /* size (0 = byte, 1 = short, 2 = long) */
1808 32, /* bitsize */
1809 FALSE, /* pc_relative */
1810 0, /* bitpos */
1811 complain_overflow_bitfield,/* complain_on_overflow */
1812 bfd_elf_generic_reloc, /* special_function */
1813 "R_ARM_GOTFUNCDESC", /* name */
1814 FALSE, /* partial_inplace */
1815 0, /* src_mask */
1816 0xffffffff, /* dst_mask */
1817 FALSE), /* pcrel_offset */
1818 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1819 0, /* rightshift */
1820 2, /* size (0 = byte, 1 = short, 2 = long) */
1821 32, /* bitsize */
1822 FALSE, /* pc_relative */
1823 0, /* bitpos */
1824 complain_overflow_bitfield,/* complain_on_overflow */
1825 bfd_elf_generic_reloc, /* special_function */
1826 "R_ARM_GOTOFFFUNCDESC",/* name */
1827 FALSE, /* partial_inplace */
1828 0, /* src_mask */
1829 0xffffffff, /* dst_mask */
1830 FALSE), /* pcrel_offset */
1831 HOWTO (R_ARM_FUNCDESC, /* type */
1832 0, /* rightshift */
1833 2, /* size (0 = byte, 1 = short, 2 = long) */
1834 32, /* bitsize */
1835 FALSE, /* pc_relative */
1836 0, /* bitpos */
1837 complain_overflow_bitfield,/* complain_on_overflow */
1838 bfd_elf_generic_reloc, /* special_function */
1839 "R_ARM_FUNCDESC", /* name */
1840 FALSE, /* partial_inplace */
1841 0, /* src_mask */
1842 0xffffffff, /* dst_mask */
1843 FALSE), /* pcrel_offset */
1844 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1845 0, /* rightshift */
1846 2, /* size (0 = byte, 1 = short, 2 = long) */
1847 64, /* bitsize */
1848 FALSE, /* pc_relative */
1849 0, /* bitpos */
1850 complain_overflow_bitfield,/* complain_on_overflow */
1851 bfd_elf_generic_reloc, /* special_function */
1852 "R_ARM_FUNCDESC_VALUE",/* name */
1853 FALSE, /* partial_inplace */
1854 0, /* src_mask */
1855 0xffffffff, /* dst_mask */
1856 FALSE), /* pcrel_offset */
5c5a4843
CL		 1857 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1858 0, /* rightshift */
1859 2, /* size (0 = byte, 1 = short, 2 = long) */
1860 32, /* bitsize */
1861 FALSE, /* pc_relative */
1862 0, /* bitpos */
1863 complain_overflow_bitfield,/* complain_on_overflow */
1864 bfd_elf_generic_reloc, /* special_function */
1865 "R_ARM_TLS_GD32_FDPIC",/* name */
1866 FALSE, /* partial_inplace */
1867 0, /* src_mask */
1868 0xffffffff, /* dst_mask */
1869 FALSE), /* pcrel_offset */
1870 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1871 0, /* rightshift */
1872 2, /* size (0 = byte, 1 = short, 2 = long) */
1873 32, /* bitsize */
1874 FALSE, /* pc_relative */
1875 0, /* bitpos */
1876 complain_overflow_bitfield,/* complain_on_overflow */
1877 bfd_elf_generic_reloc, /* special_function */
1878 "R_ARM_TLS_LDM32_FDPIC",/* name */
1879 FALSE, /* partial_inplace */
1880 0, /* src_mask */
1881 0xffffffff, /* dst_mask */
1882 FALSE), /* pcrel_offset */
1883 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1884 0, /* rightshift */
1885 2, /* size (0 = byte, 1 = short, 2 = long) */
1886 32, /* bitsize */
1887 FALSE, /* pc_relative */
1888 0, /* bitpos */
1889 complain_overflow_bitfield,/* complain_on_overflow */
1890 bfd_elf_generic_reloc, /* special_function */
1891 "R_ARM_TLS_IE32_FDPIC",/* name */
1892 FALSE, /* partial_inplace */
1893 0, /* src_mask */
1894 0xffffffff, /* dst_mask */
1895 FALSE), /* pcrel_offset */
34e77a92 1896};
c19d1205 1897
34e77a92
RS		 1898/* 249-255 extended, currently unused, relocations: */
1899static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1900{
1901 HOWTO (R_ARM_RREL32, /* type */
1902 0, /* rightshift */
1903 0, /* size (0 = byte, 1 = short, 2 = long) */
1904 0, /* bitsize */
1905 FALSE, /* pc_relative */
1906 0, /* bitpos */
1907 complain_overflow_dont,/* complain_on_overflow */
1908 bfd_elf_generic_reloc, /* special_function */
1909 "R_ARM_RREL32", /* name */
1910 FALSE, /* partial_inplace */
1911 0, /* src_mask */
1912 0, /* dst_mask */
1913 FALSE), /* pcrel_offset */
1914
1915 HOWTO (R_ARM_RABS32, /* type */
1916 0, /* rightshift */
1917 0, /* size (0 = byte, 1 = short, 2 = long) */
1918 0, /* bitsize */
1919 FALSE, /* pc_relative */
1920 0, /* bitpos */
1921 complain_overflow_dont,/* complain_on_overflow */
1922 bfd_elf_generic_reloc, /* special_function */
1923 "R_ARM_RABS32", /* name */
1924 FALSE, /* partial_inplace */
1925 0, /* src_mask */
1926 0, /* dst_mask */
1927 FALSE), /* pcrel_offset */
1928
1929 HOWTO (R_ARM_RPC24, /* type */
1930 0, /* rightshift */
1931 0, /* size (0 = byte, 1 = short, 2 = long) */
1932 0, /* bitsize */
1933 FALSE, /* pc_relative */
1934 0, /* bitpos */
1935 complain_overflow_dont,/* complain_on_overflow */
1936 bfd_elf_generic_reloc, /* special_function */
1937 "R_ARM_RPC24", /* name */
1938 FALSE, /* partial_inplace */
1939 0, /* src_mask */
1940 0, /* dst_mask */
1941 FALSE), /* pcrel_offset */
1942
1943 HOWTO (R_ARM_RBASE, /* type */
1944 0, /* rightshift */
1945 0, /* size (0 = byte, 1 = short, 2 = long) */
1946 0, /* bitsize */
1947 FALSE, /* pc_relative */
1948 0, /* bitpos */
1949 complain_overflow_dont,/* complain_on_overflow */
1950 bfd_elf_generic_reloc, /* special_function */
1951 "R_ARM_RBASE", /* name */
1952 FALSE, /* partial_inplace */
1953 0, /* src_mask */
1954 0, /* dst_mask */
1955 FALSE) /* pcrel_offset */
1956};
1957
1958static reloc_howto_type *
1959elf32_arm_howto_from_type (unsigned int r_type)
1960{
906e58ca 1961 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1962 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1963
188fd7ae
CL		 1964 if (r_type >= R_ARM_IRELATIVE
1965 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1966 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1967
c19d1205 1968 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1969 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1970 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1971
c19d1205 1972 return NULL;
7f266840
DJ		 1973}
1974
f3185997
NC		 1975static bfd_boolean
1976elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1977 Elf_Internal_Rela * elf_reloc)
1978{
1979 unsigned int r_type;
1980
1981 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1982 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1983 {
1984 /* xgettext:c-format */
1985 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1986 abfd, r_type);
1987 bfd_set_error (bfd_error_bad_value);
1988 return FALSE;
1989 }
1990 return TRUE;
7f266840
DJ		 1991}
1992
1993struct elf32_arm_reloc_map
1994 {
1995 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1996 unsigned char elf_reloc_val;
7f266840
DJ		 1997 };
1998
1999/* All entries in this list must also be present in elf32_arm_howto_table. */
2000static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
2001 {
07d6d2b8 2002 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 2003 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 2004 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
2005 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 2006 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
2007 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
2008 {BFD_RELOC_32, R_ARM_ABS32},
2009 {BFD_RELOC_32_PCREL, R_ARM_REL32},
2010 {BFD_RELOC_8, R_ARM_ABS8},
2011 {BFD_RELOC_16, R_ARM_ABS16},
2012 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 2013 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 2014 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
2015 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
2016 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
2017 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
2018 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
2019 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 2020 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
2021 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
2022 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
2023 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
2024 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
2025 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
2026 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
2027 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 2028 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
2029 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
2030 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
2031 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 2032 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 2033 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
2034 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
2035 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 2036 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 2037 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 2038 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 2039 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 2040 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
2041 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2042 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2043 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2044 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 2045 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2046 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2047 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2048 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 2049 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2050 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2051 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2052 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
5c5a4843
CL		 2053 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2054 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2055 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
c19d1205
ZW		 2056 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2057 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 2058 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2059 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2060 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2061 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2062 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2063 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2064 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2065 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 2066 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2067 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2068 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2069 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2070 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2071 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2072 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2073 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2074 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2075 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2076 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2077 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2078 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2079 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2080 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2081 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2082 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2083 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2084 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2085 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2086 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2087 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2088 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2089 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2090 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2091 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2092 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2093 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2094 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2095 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2096 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2097 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
e5d6e09e 2098 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
1caf72a5 2099 {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16},
1889da70 2100 {BFD_RELOC_ARM_THUMB_BF13, R_ARM_THM_BF12},
1caf72a5 2101 {BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18}
7f266840
DJ		 2102 };
2103
2104static reloc_howto_type *
f1c71a59
ZW		 2105elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2106 bfd_reloc_code_real_type code)
7f266840
DJ		 2107{
2108 unsigned int i;
8029a119 2109
906e58ca 2110 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2111 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2112 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2113
c19d1205 2114 return NULL;
7f266840
DJ		 2115}
2116
157090f7
AM		 2117static reloc_howto_type *
2118elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2119 const char *r_name)
2120{
2121 unsigned int i;
2122
906e58ca 2123 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2124 if (elf32_arm_howto_table_1[i].name != NULL
2125 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2126 return &elf32_arm_howto_table_1[i];
2127
906e58ca 2128 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2129 if (elf32_arm_howto_table_2[i].name != NULL
2130 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2131 return &elf32_arm_howto_table_2[i];
2132
34e77a92
RS		 2133 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2134 if (elf32_arm_howto_table_3[i].name != NULL
2135 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2136 return &elf32_arm_howto_table_3[i];
2137
157090f7
AM		 2138 return NULL;
2139}
2140
906e58ca
NC		 2141/* Support for core dump NOTE sections. */
2142
7f266840 2143static bfd_boolean
f1c71a59 2144elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2145{
2146 int offset;
2147 size_t size;
2148
2149 switch (note->descsz)
2150 {
2151 default:
2152 return FALSE;
2153
8029a119 2154 case 148: /* Linux/ARM 32-bit. */
7f266840 2155 /* pr_cursig */
228e534f 2156 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2157
2158 /* pr_pid */
228e534f 2159 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2160
2161 /* pr_reg */
2162 offset = 72;
2163 size = 72;
2164
2165 break;
2166 }
2167
2168 /* Make a ".reg/999" section. */
2169 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2170 size, note->descpos + offset);
2171}
2172
2173static bfd_boolean
f1c71a59 2174elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2175{
2176 switch (note->descsz)
2177 {
2178 default:
2179 return FALSE;
2180
8029a119 2181 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2182 elf_tdata (abfd)->core->pid
4395ee08 2183 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2184 elf_tdata (abfd)->core->program
7f266840 2185 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2186 elf_tdata (abfd)->core->command
7f266840
DJ		 2187 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2188 }
2189
2190 /* Note that for some reason, a spurious space is tacked
2191 onto the end of the args in some (at least one anyway)
2192 implementations, so strip it off if it exists. */
7f266840 2193 {
228e534f 2194 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2195 int n = strlen (command);
2196
2197 if (0 < n && command[n - 1] == ' ')
2198 command[n - 1] = '\0';
2199 }
2200
2201 return TRUE;
2202}
2203
1f20dca5
UW		 2204static char *
2205elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2206 int note_type, ...)
2207{
2208 switch (note_type)
2209 {
2210 default:
2211 return NULL;
2212
2213 case NT_PRPSINFO:
2214 {
602f1657 2215 char data[124] ATTRIBUTE_NONSTRING;
1f20dca5
UW		 2216 va_list ap;
2217
2218 va_start (ap, note_type);
2219 memset (data, 0, sizeof (data));
2220 strncpy (data + 28, va_arg (ap, const char *), 16);
be3e27bb 2221#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2222 DIAGNOSTIC_PUSH;
be3e27bb 2223 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
95da9854
L		 2224 -Wstringop-truncation:
2225 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2226 */
95da9854
L		 2227 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2228#endif
1f20dca5 2229 strncpy (data + 44, va_arg (ap, const char *), 80);
be3e27bb 2230#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2231 DIAGNOSTIC_POP;
fe75810f 2232#endif
1f20dca5
UW		 2233 va_end (ap);
2234
2235 return elfcore_write_note (abfd, buf, bufsiz,
2236 "CORE", note_type, data, sizeof (data));
2237 }
2238
2239 case NT_PRSTATUS:
2240 {
2241 char data[148];
2242 va_list ap;
2243 long pid;
2244 int cursig;
2245 const void *greg;
2246
2247 va_start (ap, note_type);
2248 memset (data, 0, sizeof (data));
2249 pid = va_arg (ap, long);
2250 bfd_put_32 (abfd, pid, data + 24);
2251 cursig = va_arg (ap, int);
2252 bfd_put_16 (abfd, cursig, data + 12);
2253 greg = va_arg (ap, const void *);
2254 memcpy (data + 72, greg, 72);
2255 va_end (ap);
2256
2257 return elfcore_write_note (abfd, buf, bufsiz,
2258 "CORE", note_type, data, sizeof (data));
2259 }
2260 }
2261}
2262
07d6d2b8
AM		 2263#define TARGET_LITTLE_SYM arm_elf32_le_vec
2264#define TARGET_LITTLE_NAME "elf32-littlearm"
2265#define TARGET_BIG_SYM arm_elf32_be_vec
2266#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2267
2268#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2269#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2270#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2271
252b5132
RH		 2272typedef unsigned long int insn32;
2273typedef unsigned short int insn16;
2274
3a4a14e9
PB		 2275/* In lieu of proper flags, assume all EABIv4 or later objects are
2276 interworkable. */
57e8b36a 2277#define INTERWORK_FLAG(abfd) \
3a4a14e9 2278 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2279 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2280 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2281
252b5132
RH		 2282/* The linker script knows the section names for placement.
2283 The entry_names are used to do simple name mangling on the stubs.
2284 Given a function name, and its type, the stub can be found. The
9b485d32 2285 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2286#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2287#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2288
2289#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2290#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2291
c7b8f16e
JB		 2292#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2293#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2294
a504d23a
LA		 2295#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2296#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2297
845b51d6
PB		 2298#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2299#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2300
7413f23f
DJ		 2301#define STUB_ENTRY_NAME "__%s_veneer"
2302
4ba2ef8f
TP		 2303#define CMSE_PREFIX "__acle_se_"
2304
4d83e8d9
CL		 2305#define CMSE_STUB_NAME ".gnu.sgstubs"
2306
252b5132
RH		 2307/* The name of the dynamic interpreter. This is put in the .interp
2308 section. */
2309#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2310
cb10292c
CL		 2311/* FDPIC default stack size. */
2312#define DEFAULT_STACK_SIZE 0x8000
2313
0855e32b 2314static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2315{
2316 0xe08e0000, /* add r0, lr, r0 */
2317 0xe5901004, /* ldr r1, [r0,#4] */
2318 0xe12fff11, /* bx r1 */
2319};
0855e32b
NS		 2320
2321static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2322{
2323 0xe52d2004, /* push {r2} */
2324 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2325 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2326 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2327 0xe081100f, /* 2: add r1, pc */
2328 0xe12fff12, /* bx r2 */
2329 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2330 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2331 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2332};
0855e32b 2333
b4e87f2c
TC		 2334/* NOTE: [Thumb nop sequence]
2335 When adding code that transitions from Thumb to Arm the instruction that
2336 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2337 a nop for performance reasons. */
2338
7801f98f
CL		 2339/* ARM FDPIC PLT entry. */
2340/* The last 5 words contain PLT lazy fragment code and data. */
2341static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2342 {
2343 0xe59fc008, /* ldr r12, .L1 */
2344 0xe08cc009, /* add r12, r12, r9 */
2345 0xe59c9004, /* ldr r9, [r12, #4] */
2346 0xe59cf000, /* ldr pc, [r12] */
2347 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2348 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2349 0xe51fc00c, /* ldr r12, [pc, #-12] */
2350 0xe92d1000, /* push {r12} */
2351 0xe599c004, /* ldr r12, [r9, #4] */
2352 0xe599f000, /* ldr pc, [r9] */
2353 };
2354
59029f57
CL		 2355/* Thumb FDPIC PLT entry. */
2356/* The last 5 words contain PLT lazy fragment code and data. */
2357static const bfd_vma elf32_arm_fdpic_thumb_plt_entry [] =
2358 {
2359 0xc00cf8df, /* ldr.w r12, .L1 */
2360 0x0c09eb0c, /* add.w r12, r12, r9 */
2361 0x9004f8dc, /* ldr.w r9, [r12, #4] */
2362 0xf000f8dc, /* ldr.w pc, [r12] */
2363 0x00000000, /* .L1 .word foo(GOTOFFFUNCDESC) */
2364 0x00000000, /* .L2 .word foo(funcdesc_value_reloc_offset) */
2365 0xc008f85f, /* ldr.w r12, .L2 */
2366 0xcd04f84d, /* push {r12} */
2367 0xc004f8d9, /* ldr.w r12, [r9, #4] */
2368 0xf000f8d9, /* ldr.w pc, [r9] */
2369 };
2370
5e681ec4
PB		 2371#ifdef FOUR_WORD_PLT
2372
252b5132
RH		 2373/* The first entry in a procedure linkage table looks like
2374 this. It is set up so that any shared library function that is
59f2c4e7 2375 called before the relocation has been set up calls the dynamic
9b485d32 2376 linker first. */
e5a52504 2377static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2378{
2379 0xe52de004, /* str lr, [sp, #-4]! */
2380 0xe59fe010, /* ldr lr, [pc, #16] */
2381 0xe08fe00e, /* add lr, pc, lr */
2382 0xe5bef008, /* ldr pc, [lr, #8]! */
2383};
5e681ec4
PB		 2384
2385/* Subsequent entries in a procedure linkage table look like
2386 this. */
e5a52504 2387static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2388{
2389 0xe28fc600, /* add ip, pc, #NN */
2390 0xe28cca00, /* add ip, ip, #NN */
2391 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2392 0x00000000, /* unused */
2393};
5e681ec4 2394
eed94f8f 2395#else /* not FOUR_WORD_PLT */
5e681ec4 2396
5e681ec4
PB		 2397/* The first entry in a procedure linkage table looks like
2398 this. It is set up so that any shared library function that is
2399 called before the relocation has been set up calls the dynamic
2400 linker first. */
e5a52504 2401static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2402{
07d6d2b8
AM		 2403 0xe52de004, /* str lr, [sp, #-4]! */
2404 0xe59fe004, /* ldr lr, [pc, #4] */
2405 0xe08fe00e, /* add lr, pc, lr */
2406 0xe5bef008, /* ldr pc, [lr, #8]! */
2407 0x00000000, /* &GOT[0] - . */
b38cadfb 2408};
252b5132 2409
1db37fe6
YG		 2410/* By default subsequent entries in a procedure linkage table look like
2411 this. Offsets that don't fit into 28 bits will cause link error. */
2412static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2413{
2414 0xe28fc600, /* add ip, pc, #0xNN00000 */
2415 0xe28cca00, /* add ip, ip, #0xNN000 */
2416 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2417};
5e681ec4 2418
1db37fe6
YG		 2419/* When explicitly asked, we'll use this "long" entry format
2420 which can cope with arbitrary displacements. */
2421static const bfd_vma elf32_arm_plt_entry_long [] =
2422{
07d6d2b8
AM		 2423 0xe28fc200, /* add ip, pc, #0xN0000000 */
2424 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2425 0xe28cca00, /* add ip, ip, #0xNN000 */
2426 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2427};
2428
2429static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2430
eed94f8f
NC		 2431#endif /* not FOUR_WORD_PLT */
2432
2433/* The first entry in a procedure linkage table looks like this.
2434 It is set up so that any shared library function that is called before the
2435 relocation has been set up calls the dynamic linker first. */
2436static const bfd_vma elf32_thumb2_plt0_entry [] =
2437{
2438 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2439 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2440 0xf8dfb500, /* push {lr} */
2441 0x44fee008, /* ldr.w lr, [pc, #8] */
2442 /* add lr, pc */
eed94f8f 2443 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2444 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2445};
2446
2447/* Subsequent entries in a procedure linkage table for thumb only target
2448 look like this. */
2449static const bfd_vma elf32_thumb2_plt_entry [] =
2450{
2451 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2452 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2453 0x0c00f240, /* movw ip, #0xNNNN */
2454 0x0c00f2c0, /* movt ip, #0xNNNN */
2455 0xf8dc44fc, /* add ip, pc */
b4e87f2c
TC		 2456 0xe7fdf000 /* ldr.w pc, [ip] */
2457 /* b .-2 */
eed94f8f 2458};
252b5132 2459
00a97672
RS		 2460/* The format of the first entry in the procedure linkage table
2461 for a VxWorks executable. */
2462static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2463{
07d6d2b8
AM		 2464 0xe52dc008, /* str ip,[sp,#-8]! */
2465 0xe59fc000, /* ldr ip,[pc] */
2466 0xe59cf008, /* ldr pc,[ip,#8] */
2467 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2468};
00a97672
RS		 2469
2470/* The format of subsequent entries in a VxWorks executable. */
2471static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2472{
07d6d2b8
AM		 2473 0xe59fc000, /* ldr ip,[pc] */
2474 0xe59cf000, /* ldr pc,[ip] */
2475 0x00000000, /* .long @got */
2476 0xe59fc000, /* ldr ip,[pc] */
2477 0xea000000, /* b _PLT */
2478 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2479};
00a97672
RS		 2480
2481/* The format of entries in a VxWorks shared library. */
2482static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2483{
07d6d2b8
AM		 2484 0xe59fc000, /* ldr ip,[pc] */
2485 0xe79cf009, /* ldr pc,[ip,r9] */
2486 0x00000000, /* .long @got */
2487 0xe59fc000, /* ldr ip,[pc] */
2488 0xe599f008, /* ldr pc,[r9,#8] */
2489 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2490};
00a97672 2491
b7693d02
DJ		 2492/* An initial stub used if the PLT entry is referenced from Thumb code. */
2493#define PLT_THUMB_STUB_SIZE 4
2494static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2495{
2496 0x4778, /* bx pc */
b4e87f2c 2497 0xe7fd /* b .-2 */
b38cadfb 2498};
b7693d02 2499
e5a52504
MM		 2500/* The entries in a PLT when using a DLL-based target with multiple
2501 address spaces. */
906e58ca 2502static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2503{
07d6d2b8
AM		 2504 0xe51ff004, /* ldr pc, [pc, #-4] */
2505 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2506};
2507
2508/* The first entry in a procedure linkage table looks like
2509 this. It is set up so that any shared library function that is
2510 called before the relocation has been set up calls the dynamic
2511 linker first. */
2512static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2513{
2514 /* First bundle: */
2515 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2516 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2517 0xe08cc00f, /* add ip, ip, pc */
2518 0xe52dc008, /* str ip, [sp, #-8]! */
2519 /* Second bundle: */
edccdf7c
RM		 2520 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2521 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2522 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2523 0xe12fff1c, /* bx ip */
b38cadfb 2524 /* Third bundle: */
edccdf7c
RM		 2525 0xe320f000, /* nop */
2526 0xe320f000, /* nop */
2527 0xe320f000, /* nop */
b38cadfb
NC		 2528 /* .Lplt_tail: */
2529 0xe50dc004, /* str ip, [sp, #-4] */
2530 /* Fourth bundle: */
edccdf7c
RM		 2531 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2532 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2533 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2534 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2535};
2536#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2537
2538/* Subsequent entries in a procedure linkage table look like this. */
2539static const bfd_vma elf32_arm_nacl_plt_entry [] =
2540{
2541 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2542 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2543 0xe08cc00f, /* add ip, ip, pc */
2544 0xea000000, /* b .Lplt_tail */
2545};
e5a52504 2546
906e58ca
NC		 2547#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2548#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2549#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2550#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2551#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2552#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2553#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2554#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2555
461a49ca 2556enum stub_insn_type
b38cadfb
NC		 2557{
2558 THUMB16_TYPE = 1,
2559 THUMB32_TYPE,
2560 ARM_TYPE,
2561 DATA_TYPE
2562};
461a49ca 2563
48229727
JB		 2564#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2565/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2566 is inserted in arm_build_one_stub(). */
2567#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2568#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2569#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2570#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2571#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2572#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2573#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2574#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2575
2576typedef struct
2577{
07d6d2b8 2578 bfd_vma data;
b38cadfb 2579 enum stub_insn_type type;
07d6d2b8
AM		 2580 unsigned int r_type;
2581 int reloc_addend;
461a49ca
DJ		 2582} insn_sequence;
2583
b4e87f2c
TC		 2584/* See note [Thumb nop sequence] when adding a veneer. */
2585
fea2b4d6
CL		 2586/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2587 to reach the stub if necessary. */
461a49ca 2588static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2589{
07d6d2b8 2590 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2591 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2592};
906e58ca 2593
fea2b4d6
CL		 2594/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2595 available. */
461a49ca 2596static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2597{
07d6d2b8
AM		 2598 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2599 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2600 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2601};
906e58ca 2602
d3626fb0 2603/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2604static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2605{
07d6d2b8
AM		 2606 THUMB16_INSN (0xb401), /* push {r0} */
2607 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2608 THUMB16_INSN (0x4684), /* mov ip, r0 */
2609 THUMB16_INSN (0xbc01), /* pop {r0} */
2610 THUMB16_INSN (0x4760), /* bx ip */
2611 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2612 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2613};
906e58ca 2614
80c135e5
TP		 2615/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2616static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2617{
07d6d2b8 2618 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2619 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2620};
2621
d5a67c02
AV		 2622/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2623 M-profile architectures. */
2624static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2625{
2626 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2627 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2628 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2629};
2630
d3626fb0
CL		 2631/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2632 allowed. */
2633static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2634{
07d6d2b8 2635 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2636 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2637 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2638 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2639 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2640};
d3626fb0 2641
fea2b4d6
CL		 2642/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2643 available. */
461a49ca 2644static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2645{
07d6d2b8 2646 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2647 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8 2648 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2649 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2650};
906e58ca 2651
fea2b4d6
CL		 2652/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2653 one, when the destination is close enough. */
461a49ca 2654static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2655{
07d6d2b8 2656 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2657 THUMB16_INSN (0xe7fd), /* b .-2 */
b38cadfb
NC		 2658 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2659};
c820be07 2660
cf3eccff 2661/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2662 blx to reach the stub if necessary. */
cf3eccff 2663static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2664{
07d6d2b8
AM		 2665 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2666 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2667 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2668};
906e58ca 2669
cf3eccff
DJ		 2670/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2671 blx to reach the stub if necessary. We can not add into pc;
2672 it is not guaranteed to mode switch (different in ARMv6 and
2673 ARMv7). */
2674static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2675{
07d6d2b8
AM		 2676 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2677 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2678 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2679 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2680};
cf3eccff 2681
ebe24dd4
CL		 2682/* V4T ARM -> ARM long branch stub, PIC. */
2683static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2684{
07d6d2b8
AM		 2685 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2686 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2687 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2688 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2689};
ebe24dd4
CL		 2690
2691/* V4T Thumb -> ARM long branch stub, PIC. */
2692static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2693{
07d6d2b8 2694 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2695 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2696 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2697 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2698 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2699};
ebe24dd4 2700
d3626fb0
CL		 2701/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2702 architectures. */
ebe24dd4 2703static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2704{
07d6d2b8
AM		 2705 THUMB16_INSN (0xb401), /* push {r0} */
2706 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2707 THUMB16_INSN (0x46fc), /* mov ip, pc */
2708 THUMB16_INSN (0x4484), /* add ip, r0 */
2709 THUMB16_INSN (0xbc01), /* pop {r0} */
2710 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2711 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2712};
ebe24dd4 2713
d3626fb0
CL		 2714/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2715 allowed. */
2716static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2717{
07d6d2b8 2718 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2719 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2720 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2721 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2722 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2723 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2724};
d3626fb0 2725
0855e32b
NS		 2726/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2727 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2728static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2729{
07d6d2b8
AM		 2730 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2731 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2732 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2733};
2734
2735/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2736 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2737static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2738{
07d6d2b8 2739 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2740 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2741 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2742 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2743 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2744};
2745
7a89b94e
NC		 2746/* NaCl ARM -> ARM long branch stub. */
2747static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2748{
2749 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2750 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2751 ARM_INSN (0xe12fff1c), /* bx ip */
2752 ARM_INSN (0xe320f000), /* nop */
2753 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2754 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2755 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2756 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2757};
2758
2759/* NaCl ARM -> ARM long branch stub, PIC. */
2760static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2761{
2762 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2763 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2764 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2765 ARM_INSN (0xe12fff1c), /* bx ip */
2766 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2767 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2768 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2769 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2770};
2771
4ba2ef8f
TP		 2772/* Stub used for transition to secure state (aka SG veneer). */
2773static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2774{
2775 THUMB32_INSN (0xe97fe97f), /* sg. */
2776 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2777};
2778
7a89b94e 2779
48229727
JB		 2780/* Cortex-A8 erratum-workaround stubs. */
2781
2782/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2783 can't use a conditional branch to reach this stub). */
2784
2785static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2786{
07d6d2b8 2787 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2788 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2789 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2790};
48229727
JB		 2791
2792/* Stub used for b.w and bl.w instructions. */
2793
2794static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2795{
2796 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2797};
48229727
JB		 2798
2799static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2800{
2801 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2802};
48229727
JB		 2803
2804/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2805 instruction (which switches to ARM mode) to point to this stub. Jump to the
2806 real destination using an ARM-mode branch. */
2807
2808static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2809{
2810 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2811};
48229727 2812
9553db3c
NC		 2813/* For each section group there can be a specially created linker section
2814 to hold the stubs for that group. The name of the stub section is based
2815 upon the name of another section within that group with the suffix below
2816 applied.
2817
2818 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2819 create what appeared to be a linker stub section when it actually
2820 contained user code/data. For example, consider this fragment:
b38cadfb 2821
9553db3c
NC		 2822 const char * stubborn_problems[] = { "np" };
2823
2824 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2825 section called:
2826
2827 .data.rel.local.stubborn_problems
2828
2829 This then causes problems in arm32_arm_build_stubs() as it triggers:
2830
2831 // Ignore non-stub sections.
2832 if (!strstr (stub_sec->name, STUB_SUFFIX))
2833 continue;
2834
2835 And so the section would be ignored instead of being processed. Hence
2836 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2837 C identifier. */
2838#define STUB_SUFFIX ".__stub"
906e58ca 2839
738a79f6
CL		 2840/* One entry per long/short branch stub defined above. */
2841#define DEF_STUBS \
2842 DEF_STUB(long_branch_any_any) \
2843 DEF_STUB(long_branch_v4t_arm_thumb) \
2844 DEF_STUB(long_branch_thumb_only) \
2845 DEF_STUB(long_branch_v4t_thumb_thumb) \
2846 DEF_STUB(long_branch_v4t_thumb_arm) \
2847 DEF_STUB(short_branch_v4t_thumb_arm) \
2848 DEF_STUB(long_branch_any_arm_pic) \
2849 DEF_STUB(long_branch_any_thumb_pic) \
2850 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2851 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2852 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2853 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2854 DEF_STUB(long_branch_any_tls_pic) \
2855 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2856 DEF_STUB(long_branch_arm_nacl) \
2857 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2858 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2859 DEF_STUB(a8_veneer_b_cond) \
2860 DEF_STUB(a8_veneer_b) \
2861 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2862 DEF_STUB(a8_veneer_blx) \
2863 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2864 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2865
2866#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2867enum elf32_arm_stub_type
2868{
906e58ca 2869 arm_stub_none,
738a79f6 2870 DEF_STUBS
4f4faa4d 2871 max_stub_type
738a79f6
CL		 2872};
2873#undef DEF_STUB
2874
8d9d9490
TP		 2875/* Note the first a8_veneer type. */
2876const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2877
738a79f6
CL		 2878typedef struct
2879{
d3ce72d0 2880 const insn_sequence* template_sequence;
738a79f6
CL		 2881 int template_size;
2882} stub_def;
2883
2884#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2885static const stub_def stub_definitions[] =
2886{
738a79f6
CL		 2887 {NULL, 0},
2888 DEF_STUBS
906e58ca
NC		 2889};
2890
2891struct elf32_arm_stub_hash_entry
2892{
2893 /* Base hash table entry structure. */
2894 struct bfd_hash_entry root;
2895
2896 /* The stub section. */
2897 asection *stub_sec;
2898
2899 /* Offset within stub_sec of the beginning of this stub. */
2900 bfd_vma stub_offset;
2901
2902 /* Given the symbol's value and its section we can determine its final
2903 value when building the stubs (so the stub knows where to jump). */
2904 bfd_vma target_value;
2905 asection *target_section;
2906
8d9d9490
TP		 2907 /* Same as above but for the source of the branch to the stub. Used for
2908 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2909 such, source section does not need to be recorded since Cortex-A8 erratum
2910 workaround stubs are only generated when both source and target are in the
2911 same section. */
2912 bfd_vma source_value;
48229727
JB		 2913
2914 /* The instruction which caused this stub to be generated (only valid for
2915 Cortex-A8 erratum workaround stubs at present). */
2916 unsigned long orig_insn;
2917
461a49ca 2918 /* The stub type. */
906e58ca 2919 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2920 /* Its encoding size in bytes. */
2921 int stub_size;
2922 /* Its template. */
2923 const insn_sequence *stub_template;
2924 /* The size of the template (number of entries). */
2925 int stub_template_size;
906e58ca
NC		 2926
2927 /* The symbol table entry, if any, that this was derived from. */
2928 struct elf32_arm_link_hash_entry *h;
2929
35fc36a8
RS		 2930 /* Type of branch. */
2931 enum arm_st_branch_type branch_type;
906e58ca
NC		 2932
2933 /* Where this stub is being called from, or, in the case of combined
2934 stub sections, the first input section in the group. */
2935 asection *id_sec;
7413f23f
DJ		 2936
2937 /* The name for the local symbol at the start of this stub. The
2938 stub name in the hash table has to be unique; this does not, so
2939 it can be friendlier. */
2940 char *output_name;
906e58ca
NC		 2941};
2942
e489d0ae
PB		 2943/* Used to build a map of a section. This is required for mixed-endian
2944 code/data. */
2945
2946typedef struct elf32_elf_section_map
2947{
2948 bfd_vma vma;
2949 char type;
2950}
2951elf32_arm_section_map;
2952
c7b8f16e
JB		 2953/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2954
2955typedef enum
2956{
2957 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2958 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2959 VFP11_ERRATUM_ARM_VENEER,
2960 VFP11_ERRATUM_THUMB_VENEER
2961}
2962elf32_vfp11_erratum_type;
2963
2964typedef struct elf32_vfp11_erratum_list
2965{
2966 struct elf32_vfp11_erratum_list *next;
2967 bfd_vma vma;
2968 union
2969 {
2970 struct
2971 {
2972 struct elf32_vfp11_erratum_list *veneer;
2973 unsigned int vfp_insn;
2974 } b;
2975 struct
2976 {
2977 struct elf32_vfp11_erratum_list *branch;
2978 unsigned int id;
2979 } v;
2980 } u;
2981 elf32_vfp11_erratum_type type;
2982}
2983elf32_vfp11_erratum_list;
2984
a504d23a
LA		 2985/* Information about a STM32L4XX erratum veneer, or a branch to such a
2986 veneer. */
2987typedef enum
2988{
2989 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2990 STM32L4XX_ERRATUM_VENEER
2991}
2992elf32_stm32l4xx_erratum_type;
2993
2994typedef struct elf32_stm32l4xx_erratum_list
2995{
2996 struct elf32_stm32l4xx_erratum_list *next;
2997 bfd_vma vma;
2998 union
2999 {
3000 struct
3001 {
3002 struct elf32_stm32l4xx_erratum_list *veneer;
3003 unsigned int insn;
3004 } b;
3005 struct
3006 {
3007 struct elf32_stm32l4xx_erratum_list *branch;
3008 unsigned int id;
3009 } v;
3010 } u;
3011 elf32_stm32l4xx_erratum_type type;
3012}
3013elf32_stm32l4xx_erratum_list;
3014
2468f9c9
PB		 3015typedef enum
3016{
3017 DELETE_EXIDX_ENTRY,
3018 INSERT_EXIDX_CANTUNWIND_AT_END
3019}
3020arm_unwind_edit_type;
3021
3022/* A (sorted) list of edits to apply to an unwind table. */
3023typedef struct arm_unwind_table_edit
3024{
3025 arm_unwind_edit_type type;
3026 /* Note: we sometimes want to insert an unwind entry corresponding to a
3027 section different from the one we're currently writing out, so record the
3028 (text) section this edit relates to here. */
3029 asection *linked_section;
3030 unsigned int index;
3031 struct arm_unwind_table_edit *next;
3032}
3033arm_unwind_table_edit;
3034
8e3de13a 3035typedef struct _arm_elf_section_data
e489d0ae 3036{
2468f9c9 3037 /* Information about mapping symbols. */
e489d0ae 3038 struct bfd_elf_section_data elf;
8e3de13a 3039 unsigned int mapcount;
c7b8f16e 3040 unsigned int mapsize;
e489d0ae 3041 elf32_arm_section_map *map;
2468f9c9 3042 /* Information about CPU errata. */
c7b8f16e
JB		 3043 unsigned int erratumcount;
3044 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 3045 unsigned int stm32l4xx_erratumcount;
3046 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 3047 unsigned int additional_reloc_count;
2468f9c9
PB		 3048 /* Information about unwind tables. */
3049 union
3050 {
3051 /* Unwind info attached to a text section. */
3052 struct
3053 {
3054 asection *arm_exidx_sec;
3055 } text;
3056
3057 /* Unwind info attached to an .ARM.exidx section. */
3058 struct
3059 {
3060 arm_unwind_table_edit *unwind_edit_list;
3061 arm_unwind_table_edit *unwind_edit_tail;
3062 } exidx;
3063 } u;
8e3de13a
NC		 3064}
3065_arm_elf_section_data;
e489d0ae
PB		 3066
3067#define elf32_arm_section_data(sec) \
8e3de13a 3068 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 3069
48229727
JB		 3070/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3071 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3072 so may be created multiple times: we use an array of these entries whilst
3073 relaxing which we can refresh easily, then create stubs for each potentially
3074 erratum-triggering instruction once we've settled on a solution. */
3075
b38cadfb
NC		 3076struct a8_erratum_fix
3077{
48229727
JB		 3078 bfd *input_bfd;
3079 asection *section;
3080 bfd_vma offset;
8d9d9490 3081 bfd_vma target_offset;
48229727
JB		 3082 unsigned long orig_insn;
3083 char *stub_name;
3084 enum elf32_arm_stub_type stub_type;
35fc36a8 3085 enum arm_st_branch_type branch_type;
48229727
JB		 3086};
3087
3088/* A table of relocs applied to branches which might trigger Cortex-A8
3089 erratum. */
3090
b38cadfb
NC		 3091struct a8_erratum_reloc
3092{
48229727
JB		 3093 bfd_vma from;
3094 bfd_vma destination;
92750f34
DJ		 3095 struct elf32_arm_link_hash_entry *hash;
3096 const char *sym_name;
48229727 3097 unsigned int r_type;
35fc36a8 3098 enum arm_st_branch_type branch_type;
48229727
JB		 3099 bfd_boolean non_a8_stub;
3100};
3101
ba93b8ac
DJ		 3102/* The size of the thread control block. */
3103#define TCB_SIZE 8
3104
34e77a92
RS		 3105/* ARM-specific information about a PLT entry, over and above the usual
3106 gotplt_union. */
b38cadfb
NC		 3107struct arm_plt_info
3108{
34e77a92
RS		 3109 /* We reference count Thumb references to a PLT entry separately,
3110 so that we can emit the Thumb trampoline only if needed. */
3111 bfd_signed_vma thumb_refcount;
3112
3113 /* Some references from Thumb code may be eliminated by BL->BLX
3114 conversion, so record them separately. */
3115 bfd_signed_vma maybe_thumb_refcount;
3116
3117 /* How many of the recorded PLT accesses were from non-call relocations.
3118 This information is useful when deciding whether anything takes the
3119 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3120 non-call references to the function should resolve directly to the
3121 real runtime target. */
3122 unsigned int noncall_refcount;
3123
3124 /* Since PLT entries have variable size if the Thumb prologue is
3125 used, we need to record the index into .got.plt instead of
3126 recomputing it from the PLT offset. */
3127 bfd_signed_vma got_offset;
3128};
3129
3130/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 3131struct arm_local_iplt_info
3132{
34e77a92
RS		 3133 /* The information that is usually found in the generic ELF part of
3134 the hash table entry. */
3135 union gotplt_union root;
3136
3137 /* The information that is usually found in the ARM-specific part of
3138 the hash table entry. */
3139 struct arm_plt_info arm;
3140
3141 /* A list of all potential dynamic relocations against this symbol. */
3142 struct elf_dyn_relocs *dyn_relocs;
3143};
3144
e8b09b87
CL		 3145/* Structure to handle FDPIC support for local functions. */
3146struct fdpic_local {
3147 unsigned int funcdesc_cnt;
3148 unsigned int gotofffuncdesc_cnt;
3149 int funcdesc_offset;
3150};
3151
0ffa91dd 3152struct elf_arm_obj_tdata
ba93b8ac
DJ		 3153{
3154 struct elf_obj_tdata root;
3155
3156 /* tls_type for each local got entry. */
3157 char *local_got_tls_type;
ee065d83 3158
0855e32b
NS		 3159 /* GOTPLT entries for TLS descriptors. */
3160 bfd_vma *local_tlsdesc_gotent;
3161
34e77a92
RS		 3162 /* Information for local symbols that need entries in .iplt. */
3163 struct arm_local_iplt_info **local_iplt;
3164
bf21ed78
MS		 3165 /* Zero to warn when linking objects with incompatible enum sizes. */
3166 int no_enum_size_warning;
a9dc9481
JM		 3167
3168 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3169 int no_wchar_size_warning;
e8b09b87
CL		 3170
3171 /* Maintains FDPIC counters and funcdesc info. */
3172 struct fdpic_local *local_fdpic_cnts;
ba93b8ac
DJ		 3173};
3174
0ffa91dd
NC		 3175#define elf_arm_tdata(bfd) \
3176 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3177
0ffa91dd
NC		 3178#define elf32_arm_local_got_tls_type(bfd) \
3179 (elf_arm_tdata (bfd)->local_got_tls_type)
3180
0855e32b
NS		 3181#define elf32_arm_local_tlsdesc_gotent(bfd) \
3182 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3183
34e77a92
RS		 3184#define elf32_arm_local_iplt(bfd) \
3185 (elf_arm_tdata (bfd)->local_iplt)
3186
e8b09b87
CL		 3187#define elf32_arm_local_fdpic_cnts(bfd) \
3188 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3189
0ffa91dd
NC		 3190#define is_arm_elf(bfd) \
3191 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3192 && elf_tdata (bfd) != NULL \
4dfe6ac6 3193 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3194
3195static bfd_boolean
3196elf32_arm_mkobject (bfd *abfd)
3197{
0ffa91dd 3198 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3199 ARM_ELF_DATA);
ba93b8ac
DJ		 3200}
3201
ba93b8ac
DJ		 3202#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3203
e8b09b87
CL		 3204/* Structure to handle FDPIC support for extern functions. */
3205struct fdpic_global {
3206 unsigned int gotofffuncdesc_cnt;
3207 unsigned int gotfuncdesc_cnt;
3208 unsigned int funcdesc_cnt;
3209 int funcdesc_offset;
3210 int gotfuncdesc_offset;
3211};
3212
ba96a88f 3213/* Arm ELF linker hash entry. */
252b5132 3214struct elf32_arm_link_hash_entry
b38cadfb
NC		 3215{
3216 struct elf_link_hash_entry root;
252b5132 3217
b38cadfb
NC		 3218 /* Track dynamic relocs copied for this symbol. */
3219 struct elf_dyn_relocs *dyn_relocs;
b7693d02 3220
b38cadfb
NC		 3221 /* ARM-specific PLT information. */
3222 struct arm_plt_info plt;
ba93b8ac
DJ		 3223
3224#define GOT_UNKNOWN 0
3225#define GOT_NORMAL 1
3226#define GOT_TLS_GD 2
3227#define GOT_TLS_IE 4
0855e32b
NS		 3228#define GOT_TLS_GDESC 8
3229#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3230 unsigned int tls_type : 8;
34e77a92 3231
b38cadfb
NC		 3232 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3233 unsigned int is_iplt : 1;
34e77a92 3234
b38cadfb 3235 unsigned int unused : 23;
a4fd1a8e 3236
b38cadfb
NC		 3237 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3238 starting at the end of the jump table. */
3239 bfd_vma tlsdesc_got;
0855e32b 3240
b38cadfb
NC		 3241 /* The symbol marking the real symbol location for exported thumb
3242 symbols with Arm stubs. */
3243 struct elf_link_hash_entry *export_glue;
906e58ca 3244
b38cadfb 3245 /* A pointer to the most recently used stub hash entry against this
8029a119 3246 symbol. */
b38cadfb 3247 struct elf32_arm_stub_hash_entry *stub_cache;
e8b09b87
CL		 3248
3249 /* Counter for FDPIC relocations against this symbol. */
3250 struct fdpic_global fdpic_cnts;
b38cadfb 3251};
252b5132 3252
252b5132 3253/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3254#define elf32_arm_link_hash_traverse(table, func, info) \
3255 (elf_link_hash_traverse \
3256 (&(table)->root, \
b7693d02 3257 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3258 (info)))
3259
3260/* Get the ARM elf linker hash table from a link_info structure. */
3261#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3262 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3263 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3264
906e58ca
NC		 3265#define arm_stub_hash_lookup(table, string, create, copy) \
3266 ((struct elf32_arm_stub_hash_entry *) \
3267 bfd_hash_lookup ((table), (string), (create), (copy)))
3268
21d799b5
NC		 3269/* Array to keep track of which stub sections have been created, and
3270 information on stub grouping. */
3271struct map_stub
3272{
3273 /* This is the section to which stubs in the group will be
3274 attached. */
3275 asection *link_sec;
3276 /* The stub section. */
3277 asection *stub_sec;
3278};
3279
0855e32b
NS		 3280#define elf32_arm_compute_jump_table_size(htab) \
3281 ((htab)->next_tls_desc_index * 4)
3282
9b485d32 3283/* ARM ELF linker hash table. */
252b5132 3284struct elf32_arm_link_hash_table
906e58ca
NC		 3285{
3286 /* The main hash table. */
3287 struct elf_link_hash_table root;
252b5132 3288
906e58ca
NC		 3289 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3290 bfd_size_type thumb_glue_size;
252b5132 3291
906e58ca
NC		 3292 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3293 bfd_size_type arm_glue_size;
252b5132 3294
906e58ca
NC		 3295 /* The size in bytes of section containing the ARMv4 BX veneers. */
3296 bfd_size_type bx_glue_size;
845b51d6 3297
906e58ca
NC		 3298 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3299 veneer has been populated. */
3300 bfd_vma bx_glue_offset[15];
845b51d6 3301
906e58ca
NC		 3302 /* The size in bytes of the section containing glue for VFP11 erratum
3303 veneers. */
3304 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3305
a504d23a
LA		 3306 /* The size in bytes of the section containing glue for STM32L4XX erratum
3307 veneers. */
3308 bfd_size_type stm32l4xx_erratum_glue_size;
3309
48229727
JB		 3310 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3311 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3312 elf32_arm_write_section(). */
3313 struct a8_erratum_fix *a8_erratum_fixes;
3314 unsigned int num_a8_erratum_fixes;
3315
906e58ca
NC		 3316 /* An arbitrary input BFD chosen to hold the glue sections. */
3317 bfd * bfd_of_glue_owner;
ba96a88f 3318
906e58ca
NC		 3319 /* Nonzero to output a BE8 image. */
3320 int byteswap_code;
e489d0ae 3321
906e58ca
NC		 3322 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3323 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3324 int target1_is_rel;
9c504268 3325
906e58ca
NC		 3326 /* The relocation to use for R_ARM_TARGET2 relocations. */
3327 int target2_reloc;
eb043451 3328
906e58ca
NC		 3329 /* 0 = Ignore R_ARM_V4BX.
3330 1 = Convert BX to MOV PC.
3331 2 = Generate v4 interworing stubs. */
3332 int fix_v4bx;
319850b4 3333
48229727
JB		 3334 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3335 int fix_cortex_a8;
3336
2de70689
MGD		 3337 /* Whether we should fix the ARM1176 BLX immediate issue. */
3338 int fix_arm1176;
3339
906e58ca
NC		 3340 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3341 int use_blx;
33bfe774 3342
906e58ca
NC		 3343 /* What sort of code sequences we should look for which may trigger the
3344 VFP11 denorm erratum. */
3345 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3346
906e58ca
NC		 3347 /* Global counter for the number of fixes we have emitted. */
3348 int num_vfp11_fixes;
c7b8f16e 3349
a504d23a
LA		 3350 /* What sort of code sequences we should look for which may trigger the
3351 STM32L4XX erratum. */
3352 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3353
3354 /* Global counter for the number of fixes we have emitted. */
3355 int num_stm32l4xx_fixes;
3356
906e58ca
NC		 3357 /* Nonzero to force PIC branch veneers. */
3358 int pic_veneer;
27e55c4d 3359
906e58ca
NC		 3360 /* The number of bytes in the initial entry in the PLT. */
3361 bfd_size_type plt_header_size;
e5a52504 3362
906e58ca
NC		 3363 /* The number of bytes in the subsequent PLT etries. */
3364 bfd_size_type plt_entry_size;
e5a52504 3365
906e58ca
NC		 3366 /* True if the target system is VxWorks. */
3367 int vxworks_p;
00a97672 3368
906e58ca
NC		 3369 /* True if the target system is Symbian OS. */
3370 int symbian_p;
e5a52504 3371
b38cadfb
NC		 3372 /* True if the target system is Native Client. */
3373 int nacl_p;
3374
906e58ca 3375 /* True if the target uses REL relocations. */
f3185997 3376 bfd_boolean use_rel;
4e7fd91e 3377
54ddd295
TP		 3378 /* Nonzero if import library must be a secure gateway import library
3379 as per ARMv8-M Security Extensions. */
3380 int cmse_implib;
3381
0955507f
TP		 3382 /* The import library whose symbols' address must remain stable in
3383 the import library generated. */
3384 bfd *in_implib_bfd;
3385
0855e32b
NS		 3386 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3387 bfd_vma next_tls_desc_index;
3388
3389 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3390 bfd_vma num_tls_desc;
3391
906e58ca
NC		 3392 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3393 asection *srelplt2;
00a97672 3394
0855e32b
NS		 3395 /* The offset into splt of the PLT entry for the TLS descriptor
3396 resolver. Special values are 0, if not necessary (or not found
3397 to be necessary yet), and -1 if needed but not determined
3398 yet. */
3399 bfd_vma dt_tlsdesc_plt;
3400
3401 /* The offset into sgot of the GOT entry used by the PLT entry
3402 above. */
b38cadfb 3403 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3404
3405 /* Offset in .plt section of tls_arm_trampoline. */
3406 bfd_vma tls_trampoline;
3407
5c5a4843 3408 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
906e58ca
NC		 3409 union
3410 {
3411 bfd_signed_vma refcount;
3412 bfd_vma offset;
3413 } tls_ldm_got;
b7693d02 3414
87d72d41
AM		 3415 /* Small local sym cache. */
3416 struct sym_cache sym_cache;
906e58ca
NC		 3417
3418 /* For convenience in allocate_dynrelocs. */
3419 bfd * obfd;
3420
0855e32b
NS		 3421 /* The amount of space used by the reserved portion of the sgotplt
3422 section, plus whatever space is used by the jump slots. */
3423 bfd_vma sgotplt_jump_table_size;
3424
906e58ca
NC		 3425 /* The stub hash table. */
3426 struct bfd_hash_table stub_hash_table;
3427
3428 /* Linker stub bfd. */
3429 bfd *stub_bfd;
3430
3431 /* Linker call-backs. */
6bde4c52
TP		 3432 asection * (*add_stub_section) (const char *, asection *, asection *,
3433 unsigned int);
906e58ca
NC		 3434 void (*layout_sections_again) (void);
3435
3436 /* Array to keep track of which stub sections have been created, and
3437 information on stub grouping. */
21d799b5 3438 struct map_stub *stub_group;
906e58ca 3439
4ba2ef8f
TP		 3440 /* Input stub section holding secure gateway veneers. */
3441 asection *cmse_stub_sec;
3442
0955507f
TP		 3443 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3444 start to be allocated. */
3445 bfd_vma new_cmse_stub_offset;
3446
fe33d2fa 3447 /* Number of elements in stub_group. */
7292b3ac 3448 unsigned int top_id;
fe33d2fa 3449
906e58ca
NC		 3450 /* Assorted information used by elf32_arm_size_stubs. */
3451 unsigned int bfd_count;
7292b3ac 3452 unsigned int top_index;
906e58ca 3453 asection **input_list;
617a5ada
CL		 3454
3455 /* True if the target system uses FDPIC. */
3456 int fdpic_p;
e8b09b87
CL		 3457
3458 /* Fixup section. Used for FDPIC. */
3459 asection *srofixup;
906e58ca 3460};
252b5132 3461
e8b09b87
CL		 3462/* Add an FDPIC read-only fixup. */
3463static void
3464arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3465{
3466 bfd_vma fixup_offset;
3467
3468 fixup_offset = srofixup->reloc_count++ * 4;
3469 BFD_ASSERT (fixup_offset < srofixup->size);
3470 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3471}
3472
a504d23a
LA		 3473static inline int
3474ctz (unsigned int mask)
3475{
3476#if GCC_VERSION >= 3004
3477 return __builtin_ctz (mask);
3478#else
3479 unsigned int i;
3480
3481 for (i = 0; i < 8 * sizeof (mask); i++)
3482 {
3483 if (mask & 0x1)
3484 break;
3485 mask = (mask >> 1);
3486 }
3487 return i;
3488#endif
3489}
3490
3491static inline int
b25e998d 3492elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3493{
3494#if GCC_VERSION >= 3004
3495 return __builtin_popcount (mask);
3496#else
b25e998d
CG		 3497 unsigned int i;
3498 int sum = 0;
a504d23a
LA		 3499
3500 for (i = 0; i < 8 * sizeof (mask); i++)
3501 {
3502 if (mask & 0x1)
3503 sum++;
3504 mask = (mask >> 1);
3505 }
3506 return sum;
3507#endif
3508}
3509
e8b09b87
CL		 3510static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3511 asection *sreloc, Elf_Internal_Rela *rel);
3512
3513static void
3514arm_elf_fill_funcdesc(bfd *output_bfd,
3515 struct bfd_link_info *info,
3516 int *funcdesc_offset,
3517 int dynindx,
3518 int offset,
3519 bfd_vma addr,
3520 bfd_vma dynreloc_value,
3521 bfd_vma seg)
3522{
3523 if ((*funcdesc_offset & 1) == 0)
3524 {
3525 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3526 asection *sgot = globals->root.sgot;
3527
3528 if (bfd_link_pic(info))
3529 {
3530 asection *srelgot = globals->root.srelgot;
3531 Elf_Internal_Rela outrel;
3532
3533 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3534 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3535 outrel.r_addend = 0;
3536
3537 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3538 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3539 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3540 }
3541 else
3542 {
3543 struct elf_link_hash_entry *hgot = globals->root.hgot;
3544 bfd_vma got_value = hgot->root.u.def.value
3545 + hgot->root.u.def.section->output_section->vma
3546 + hgot->root.u.def.section->output_offset;
3547
3548 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3549 sgot->output_section->vma + sgot->output_offset
3550 + offset);
3551 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3552 sgot->output_section->vma + sgot->output_offset
3553 + offset + 4);
3554 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3555 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3556 }
3557 *funcdesc_offset |= 1;
3558 }
3559}
3560
780a67af
NC		 3561/* Create an entry in an ARM ELF linker hash table. */
3562
3563static struct bfd_hash_entry *
57e8b36a 3564elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3565 struct bfd_hash_table * table,
3566 const char * string)
780a67af
NC		 3567{
3568 struct elf32_arm_link_hash_entry * ret =
3569 (struct elf32_arm_link_hash_entry *) entry;
3570
3571 /* Allocate the structure if it has not already been allocated by a
3572 subclass. */
906e58ca 3573 if (ret == NULL)
21d799b5 3574 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3575 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3576 if (ret == NULL)
780a67af
NC		 3577 return (struct bfd_hash_entry *) ret;
3578
3579 /* Call the allocation method of the superclass. */
3580 ret = ((struct elf32_arm_link_hash_entry *)
3581 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3582 table, string));
57e8b36a 3583 if (ret != NULL)
b7693d02 3584 {
0bdcacaf 3585 ret->dyn_relocs = NULL;
ba93b8ac 3586 ret->tls_type = GOT_UNKNOWN;
0855e32b 3587 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3588 ret->plt.thumb_refcount = 0;
3589 ret->plt.maybe_thumb_refcount = 0;
3590 ret->plt.noncall_refcount = 0;
3591 ret->plt.got_offset = -1;
3592 ret->is_iplt = FALSE;
a4fd1a8e 3593 ret->export_glue = NULL;
906e58ca
NC		 3594
3595 ret->stub_cache = NULL;
e8b09b87
CL		 3596
3597 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3598 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3599 ret->fdpic_cnts.funcdesc_cnt = 0;
3600 ret->fdpic_cnts.funcdesc_offset = -1;
3601 ret->fdpic_cnts.gotfuncdesc_offset = -1;
b7693d02 3602 }
780a67af
NC		 3603
3604 return (struct bfd_hash_entry *) ret;
3605}
3606
34e77a92
RS		 3607/* Ensure that we have allocated bookkeeping structures for ABFD's local
3608 symbols. */
3609
3610static bfd_boolean
3611elf32_arm_allocate_local_sym_info (bfd *abfd)
3612{
3613 if (elf_local_got_refcounts (abfd) == NULL)
3614 {
3615 bfd_size_type num_syms;
3616 bfd_size_type size;
3617 char *data;
3618
3619 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3620 size = num_syms * (sizeof (bfd_signed_vma)
3621 + sizeof (struct arm_local_iplt_info *)
3622 + sizeof (bfd_vma)
e8b09b87
CL		 3623 + sizeof (char)
3624 + sizeof (struct fdpic_local));
34e77a92
RS		 3625 data = bfd_zalloc (abfd, size);
3626 if (data == NULL)
3627 return FALSE;
3628
e8b09b87
CL		 3629 elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
3630 data += num_syms * sizeof (struct fdpic_local);
3631
34e77a92
RS		 3632 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3633 data += num_syms * sizeof (bfd_signed_vma);
3634
3635 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3636 data += num_syms * sizeof (struct arm_local_iplt_info *);
3637
3638 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3639 data += num_syms * sizeof (bfd_vma);
3640
3641 elf32_arm_local_got_tls_type (abfd) = data;
3642 }
3643 return TRUE;
3644}
3645
3646/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3647 to input bfd ABFD. Create the information if it doesn't already exist.
3648 Return null if an allocation fails. */
3649
3650static struct arm_local_iplt_info *
3651elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3652{
3653 struct arm_local_iplt_info **ptr;
3654
3655 if (!elf32_arm_allocate_local_sym_info (abfd))
3656 return NULL;
3657
3658 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3659 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3660 if (*ptr == NULL)
3661 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3662 return *ptr;
3663}
3664
3665/* Try to obtain PLT information for the symbol with index R_SYMNDX
3666 in ABFD's symbol table. If the symbol is global, H points to its
3667 hash table entry, otherwise H is null.
3668
3669 Return true if the symbol does have PLT information. When returning
3670 true, point *ROOT_PLT at the target-independent reference count/offset
3671 union and *ARM_PLT at the ARM-specific information. */
3672
3673static bfd_boolean
4ba2ef8f
TP		 3674elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3675 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3676 unsigned long r_symndx, union gotplt_union **root_plt,
3677 struct arm_plt_info **arm_plt)
3678{
3679 struct arm_local_iplt_info *local_iplt;
3680
4ba2ef8f
TP		 3681 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3682 return FALSE;
3683
34e77a92
RS		 3684 if (h != NULL)
3685 {
3686 *root_plt = &h->root.plt;
3687 *arm_plt = &h->plt;
3688 return TRUE;
3689 }
3690
3691 if (elf32_arm_local_iplt (abfd) == NULL)
3692 return FALSE;
3693
3694 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3695 if (local_iplt == NULL)
3696 return FALSE;
3697
3698 *root_plt = &local_iplt->root;
3699 *arm_plt = &local_iplt->arm;
3700 return TRUE;
3701}
3702
59029f57
CL		 3703static bfd_boolean using_thumb_only (struct elf32_arm_link_hash_table *globals);
3704
34e77a92
RS		 3705/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3706 before it. */
3707
3708static bfd_boolean
3709elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3710 struct arm_plt_info *arm_plt)
3711{
3712 struct elf32_arm_link_hash_table *htab;
3713
3714 htab = elf32_arm_hash_table (info);
59029f57
CL		 3715
3716 return (!using_thumb_only(htab) && (arm_plt->thumb_refcount != 0
3717 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0)));
34e77a92
RS		 3718}
3719
3720/* Return a pointer to the head of the dynamic reloc list that should
3721 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3722 ABFD's symbol table. Return null if an error occurs. */
3723
3724static struct elf_dyn_relocs **
3725elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3726 Elf_Internal_Sym *isym)
3727{
3728 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3729 {
3730 struct arm_local_iplt_info *local_iplt;
3731
3732 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3733 if (local_iplt == NULL)
3734 return NULL;
3735 return &local_iplt->dyn_relocs;
3736 }
3737 else
3738 {
3739 /* Track dynamic relocs needed for local syms too.
3740 We really need local syms available to do this
3741 easily. Oh well. */
3742 asection *s;
3743 void *vpp;
3744
3745 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3746 if (s == NULL)
3747 abort ();
3748
3749 vpp = &elf_section_data (s)->local_dynrel;
3750 return (struct elf_dyn_relocs **) vpp;
3751 }
3752}
3753
906e58ca
NC		 3754/* Initialize an entry in the stub hash table. */
3755
3756static struct bfd_hash_entry *
3757stub_hash_newfunc (struct bfd_hash_entry *entry,
3758 struct bfd_hash_table *table,
3759 const char *string)
3760{
3761 /* Allocate the structure if it has not already been allocated by a
3762 subclass. */
3763 if (entry == NULL)
3764 {
21d799b5 3765 entry = (struct bfd_hash_entry *)
99059e56 3766 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3767 if (entry == NULL)
3768 return entry;
3769 }
3770
3771 /* Call the allocation method of the superclass. */
3772 entry = bfd_hash_newfunc (entry, table, string);
3773 if (entry != NULL)
3774 {
3775 struct elf32_arm_stub_hash_entry *eh;
3776
3777 /* Initialize the local fields. */
3778 eh = (struct elf32_arm_stub_hash_entry *) entry;
3779 eh->stub_sec = NULL;
0955507f 3780 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3781 eh->source_value = 0;
906e58ca
NC		 3782 eh->target_value = 0;
3783 eh->target_section = NULL;
cedfb179 3784 eh->orig_insn = 0;
906e58ca 3785 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3786 eh->stub_size = 0;
3787 eh->stub_template = NULL;
0955507f 3788 eh->stub_template_size = -1;
906e58ca
NC		 3789 eh->h = NULL;
3790 eh->id_sec = NULL;
d8d2f433 3791 eh->output_name = NULL;
906e58ca
NC		 3792 }
3793
3794 return entry;
3795}
3796
00a97672 3797/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3798 shortcuts to them in our hash table. */
3799
3800static bfd_boolean
57e8b36a 3801create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3802{
3803 struct elf32_arm_link_hash_table *htab;
3804
e5a52504 3805 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3806 if (htab == NULL)
3807 return FALSE;
3808
e5a52504
MM		 3809 /* BPABI objects never have a GOT, or associated sections. */
3810 if (htab->symbian_p)
3811 return TRUE;
3812
5e681ec4
PB		 3813 if (! _bfd_elf_create_got_section (dynobj, info))
3814 return FALSE;
3815
e8b09b87
CL		 3816 /* Also create .rofixup. */
3817 if (htab->fdpic_p)
3818 {
3819 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3820 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3821 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
fd361982
AM		 3822 if (htab->srofixup == NULL
3823 || !bfd_set_section_alignment (htab->srofixup, 2))
e8b09b87
CL		 3824 return FALSE;
3825 }
3826
5e681ec4
PB		 3827 return TRUE;
3828}
3829
34e77a92
RS		 3830/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3831
3832static bfd_boolean
3833create_ifunc_sections (struct bfd_link_info *info)
3834{
3835 struct elf32_arm_link_hash_table *htab;
3836 const struct elf_backend_data *bed;
3837 bfd *dynobj;
3838 asection *s;
3839 flagword flags;
b38cadfb 3840
34e77a92
RS		 3841 htab = elf32_arm_hash_table (info);
3842 dynobj = htab->root.dynobj;
3843 bed = get_elf_backend_data (dynobj);
3844 flags = bed->dynamic_sec_flags;
3845
3846 if (htab->root.iplt == NULL)
3847 {
3d4d4302
AM		 3848 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3849 flags | SEC_READONLY | SEC_CODE);
34e77a92 3850 if (s == NULL
fd361982 3851 || !bfd_set_section_alignment (s, bed->plt_alignment))
34e77a92
RS		 3852 return FALSE;
3853 htab->root.iplt = s;
3854 }
3855
3856 if (htab->root.irelplt == NULL)
3857 {
3d4d4302
AM		 3858 s = bfd_make_section_anyway_with_flags (dynobj,
3859 RELOC_SECTION (htab, ".iplt"),
3860 flags | SEC_READONLY);
34e77a92 3861 if (s == NULL
fd361982 3862 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3863 return FALSE;
3864 htab->root.irelplt = s;
3865 }
3866
3867 if (htab->root.igotplt == NULL)
3868 {
3d4d4302 3869 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92 3870 if (s == NULL
fd361982 3871 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3872 return FALSE;
3873 htab->root.igotplt = s;
3874 }
3875 return TRUE;
3876}
3877
eed94f8f
NC		 3878/* Determine if we're dealing with a Thumb only architecture. */
3879
3880static bfd_boolean
3881using_thumb_only (struct elf32_arm_link_hash_table *globals)
3882{
2fd158eb
TP		 3883 int arch;
3884 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3885 Tag_CPU_arch_profile);
eed94f8f 3886
2fd158eb
TP		 3887 if (profile)
3888 return profile == 'M';
eed94f8f 3889
2fd158eb 3890 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3891
60a019a0 3892 /* Force return logic to be reviewed for each new architecture. */
031254f2 3893 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0 3894
2fd158eb
TP		 3895 if (arch == TAG_CPU_ARCH_V6_M
3896 || arch == TAG_CPU_ARCH_V6S_M
3897 || arch == TAG_CPU_ARCH_V7E_M
3898 || arch == TAG_CPU_ARCH_V8M_BASE
031254f2
AV		 3899 || arch == TAG_CPU_ARCH_V8M_MAIN
3900 || arch == TAG_CPU_ARCH_V8_1M_MAIN)
2fd158eb 3901 return TRUE;
eed94f8f 3902
2fd158eb 3903 return FALSE;
eed94f8f
NC		 3904}
3905
3906/* Determine if we're dealing with a Thumb-2 object. */
3907
3908static bfd_boolean
3909using_thumb2 (struct elf32_arm_link_hash_table *globals)
3910{
60a019a0
TP		 3911 int arch;
3912 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3913 Tag_THUMB_ISA_use);
3914
3915 if (thumb_isa)
3916 return thumb_isa == 2;
3917
3918 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3919
3920 /* Force return logic to be reviewed for each new architecture. */
031254f2 3921 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 3922
3923 return (arch == TAG_CPU_ARCH_V6T2
3924 || arch == TAG_CPU_ARCH_V7
3925 || arch == TAG_CPU_ARCH_V7E_M
3926 || arch == TAG_CPU_ARCH_V8
bff0500d 3927 || arch == TAG_CPU_ARCH_V8R
031254f2
AV		 3928 || arch == TAG_CPU_ARCH_V8M_MAIN
3929 || arch == TAG_CPU_ARCH_V8_1M_MAIN);
eed94f8f
NC		 3930}
3931
5e866f5a
TP		 3932/* Determine whether Thumb-2 BL instruction is available. */
3933
3934static bfd_boolean
3935using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3936{
3937 int arch =
3938 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3939
3940 /* Force return logic to be reviewed for each new architecture. */
031254f2 3941 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
5e866f5a
TP		 3942
3943 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3944 return (arch == TAG_CPU_ARCH_V6T2
3945 || arch >= TAG_CPU_ARCH_V7);
3946}
3947
00a97672
RS		 3948/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3949 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3950 hash table. */
3951
3952static bfd_boolean
57e8b36a 3953elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3954{
3955 struct elf32_arm_link_hash_table *htab;
3956
3957 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3958 if (htab == NULL)
3959 return FALSE;
3960
362d30a1 3961 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3962 return FALSE;
3963
3964 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3965 return FALSE;
3966
00a97672
RS		 3967 if (htab->vxworks_p)
3968 {
3969 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3970 return FALSE;
3971
0e1862bb 3972 if (bfd_link_pic (info))
00a97672
RS		 3973 {
3974 htab->plt_header_size = 0;
3975 htab->plt_entry_size
3976 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3977 }
3978 else
3979 {
3980 htab->plt_header_size
3981 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3982 htab->plt_entry_size
3983 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3984 }
aebf9be7
NC		 3985
3986 if (elf_elfheader (dynobj))
3987 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3988 }
eed94f8f
NC		 3989 else
3990 {
3991 /* PR ld/16017
3992 Test for thumb only architectures. Note - we cannot just call
3993 using_thumb_only() as the attributes in the output bfd have not been
3994 initialised at this point, so instead we use the input bfd. */
3995 bfd * saved_obfd = htab->obfd;
3996
3997 htab->obfd = dynobj;
3998 if (using_thumb_only (htab))
3999 {
4000 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
4001 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
4002 }
4003 htab->obfd = saved_obfd;
4004 }
5e681ec4 4005
7801f98f
CL		 4006 if (htab->fdpic_p) {
4007 htab->plt_header_size = 0;
4008 if (info->flags & DF_BIND_NOW)
4009 htab->plt_entry_size = 4 * (ARRAY_SIZE(elf32_arm_fdpic_plt_entry) - 5);
4010 else
4011 htab->plt_entry_size = 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry);
4012 }
4013
362d30a1
RS		 4014 if (!htab->root.splt
4015 || !htab->root.srelplt
9d19e4fd
AM		 4016 || !htab->root.sdynbss
4017 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 4018 abort ();
4019
4020 return TRUE;
4021}
4022
906e58ca
NC		 4023/* Copy the extra info we tack onto an elf_link_hash_entry. */
4024
4025static void
4026elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
4027 struct elf_link_hash_entry *dir,
4028 struct elf_link_hash_entry *ind)
4029{
4030 struct elf32_arm_link_hash_entry *edir, *eind;
4031
4032 edir = (struct elf32_arm_link_hash_entry *) dir;
4033 eind = (struct elf32_arm_link_hash_entry *) ind;
4034
0bdcacaf 4035 if (eind->dyn_relocs != NULL)
906e58ca 4036 {
0bdcacaf 4037 if (edir->dyn_relocs != NULL)
906e58ca 4038 {
0bdcacaf
RS		 4039 struct elf_dyn_relocs **pp;
4040 struct elf_dyn_relocs *p;
906e58ca
NC		 4041
4042 /* Add reloc counts against the indirect sym to the direct sym
4043 list. Merge any entries against the same section. */
0bdcacaf 4044 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 4045 {
0bdcacaf 4046 struct elf_dyn_relocs *q;
906e58ca 4047
0bdcacaf
RS		 4048 for (q = edir->dyn_relocs; q != NULL; q = q->next)
4049 if (q->sec == p->sec)
906e58ca
NC		 4050 {
4051 q->pc_count += p->pc_count;
4052 q->count += p->count;
4053 *pp = p->next;
4054 break;
4055 }
4056 if (q == NULL)
4057 pp = &p->next;
4058 }
0bdcacaf 4059 *pp = edir->dyn_relocs;
906e58ca
NC		 4060 }
4061
0bdcacaf
RS		 4062 edir->dyn_relocs = eind->dyn_relocs;
4063 eind->dyn_relocs = NULL;
906e58ca
NC		 4064 }
4065
4066 if (ind->root.type == bfd_link_hash_indirect)
4067 {
4068 /* Copy over PLT info. */
34e77a92
RS		 4069 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
4070 eind->plt.thumb_refcount = 0;
4071 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
4072 eind->plt.maybe_thumb_refcount = 0;
4073 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
4074 eind->plt.noncall_refcount = 0;
4075
e8b09b87
CL		 4076 /* Copy FDPIC counters. */
4077 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
4078 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
4079 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
4080
34e77a92
RS		 4081 /* We should only allocate a function to .iplt once the final
4082 symbol information is known. */
4083 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 4084
4085 if (dir->got.refcount <= 0)
4086 {
4087 edir->tls_type = eind->tls_type;
4088 eind->tls_type = GOT_UNKNOWN;
4089 }
4090 }
4091
4092 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4093}
4094
68faa637
AM		 4095/* Destroy an ARM elf linker hash table. */
4096
4097static void
d495ab0d 4098elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 4099{
4100 struct elf32_arm_link_hash_table *ret
d495ab0d 4101 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 4102
4103 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 4104 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 4105}
4106
906e58ca
NC		 4107/* Create an ARM elf linker hash table. */
4108
4109static struct bfd_link_hash_table *
4110elf32_arm_link_hash_table_create (bfd *abfd)
4111{
4112 struct elf32_arm_link_hash_table *ret;
4113 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
4114
7bf52ea2 4115 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 4116 if (ret == NULL)
4117 return NULL;
4118
4119 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4120 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 4121 sizeof (struct elf32_arm_link_hash_entry),
4122 ARM_ELF_DATA))
906e58ca
NC		 4123 {
4124 free (ret);
4125 return NULL;
4126 }
4127
906e58ca 4128 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 4129 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 4130#ifdef FOUR_WORD_PLT
4131 ret->plt_header_size = 16;
4132 ret->plt_entry_size = 16;
4133#else
4134 ret->plt_header_size = 20;
1db37fe6 4135 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 4136#endif
f3185997 4137 ret->use_rel = TRUE;
906e58ca 4138 ret->obfd = abfd;
617a5ada 4139 ret->fdpic_p = 0;
906e58ca
NC		 4140
4141 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4142 sizeof (struct elf32_arm_stub_hash_entry)))
4143 {
d495ab0d 4144 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 4145 return NULL;
4146 }
d495ab0d 4147 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 4148
4149 return &ret->root.root;
4150}
4151
cd1dac3d
DG		 4152/* Determine what kind of NOPs are available. */
4153
4154static bfd_boolean
4155arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4156{
4157 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4158 Tag_CPU_arch);
cd1dac3d 4159
60a019a0 4160 /* Force return logic to be reviewed for each new architecture. */
031254f2 4161 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 4162
4163 return (arch == TAG_CPU_ARCH_V6T2
4164 || arch == TAG_CPU_ARCH_V6K
4165 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 4166 || arch == TAG_CPU_ARCH_V8
4167 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 4168}
4169
f4ac8484
DJ		 4170static bfd_boolean
4171arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4172{
4173 switch (stub_type)
4174 {
fea2b4d6 4175 case arm_stub_long_branch_thumb_only:
80c135e5 4176 case arm_stub_long_branch_thumb2_only:
d5a67c02 4177 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 4178 case arm_stub_long_branch_v4t_thumb_arm:
4179 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 4180 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 4181 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 4182 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 4183 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 4184 return TRUE;
4185 case arm_stub_none:
4186 BFD_FAIL ();
4187 return FALSE;
4188 break;
4189 default:
4190 return FALSE;
4191 }
4192}
4193
906e58ca
NC		 4194/* Determine the type of stub needed, if any, for a call. */
4195
4196static enum elf32_arm_stub_type
4197arm_type_of_stub (struct bfd_link_info *info,
4198 asection *input_sec,
4199 const Elf_Internal_Rela *rel,
34e77a92 4200 unsigned char st_type,
35fc36a8 4201 enum arm_st_branch_type *actual_branch_type,
906e58ca 4202 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 4203 bfd_vma destination,
4204 asection *sym_sec,
4205 bfd *input_bfd,
4206 const char *name)
906e58ca
NC		 4207{
4208 bfd_vma location;
4209 bfd_signed_vma branch_offset;
4210 unsigned int r_type;
4211 struct elf32_arm_link_hash_table * globals;
5e866f5a 4212 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 4213 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 4214 int use_plt = 0;
35fc36a8 4215 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 4216 union gotplt_union *root_plt;
4217 struct arm_plt_info *arm_plt;
d5a67c02
AV		 4218 int arch;
4219 int thumb2_movw;
906e58ca 4220
35fc36a8 4221 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 4222 return stub_type;
4223
906e58ca 4224 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4225 if (globals == NULL)
4226 return stub_type;
906e58ca
NC		 4227
4228 thumb_only = using_thumb_only (globals);
906e58ca 4229 thumb2 = using_thumb2 (globals);
5e866f5a 4230 thumb2_bl = using_thumb2_bl (globals);
906e58ca 4231
d5a67c02
AV		 4232 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4233
4234 /* True for architectures that implement the thumb2 movw instruction. */
4235 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4236
906e58ca
NC		 4237 /* Determine where the call point is. */
4238 location = (input_sec->output_offset
4239 + input_sec->output_section->vma
4240 + rel->r_offset);
4241
906e58ca
NC		 4242 r_type = ELF32_R_TYPE (rel->r_info);
4243
39f21624
NC		 4244 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4245 are considering a function call relocation. */
c5423981 4246 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 4247 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 4248 && branch_type == ST_BRANCH_TO_ARM)
4249 branch_type = ST_BRANCH_TO_THUMB;
4250
34e77a92
RS		 4251 /* For TLS call relocs, it is the caller's responsibility to provide
4252 the address of the appropriate trampoline. */
4253 if (r_type != R_ARM_TLS_CALL
4254 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 4255 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4256 ELF32_R_SYM (rel->r_info), &root_plt,
4257 &arm_plt)
34e77a92 4258 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 4259 {
34e77a92 4260 asection *splt;
fe33d2fa 4261
34e77a92
RS		 4262 if (hash == NULL || hash->is_iplt)
4263 splt = globals->root.iplt;
4264 else
4265 splt = globals->root.splt;
4266 if (splt != NULL)
b38cadfb 4267 {
34e77a92
RS		 4268 use_plt = 1;
4269
4270 /* Note when dealing with PLT entries: the main PLT stub is in
4271 ARM mode, so if the branch is in Thumb mode, another
4272 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4273 PLT stub. If a long branch stub is needed, we'll add a
4274 Thumb->Arm one and branch directly to the ARM PLT entry.
4275 Here, we have to check if a pre-PLT Thumb->ARM stub
4276 is needed and if it will be close enough. */
34e77a92
RS		 4277
4278 destination = (splt->output_section->vma
4279 + splt->output_offset
4280 + root_plt->offset);
4281 st_type = STT_FUNC;
2df2751d
CL		 4282
4283 /* Thumb branch/call to PLT: it can become a branch to ARM
4284 or to Thumb. We must perform the same checks and
4285 corrections as in elf32_arm_final_link_relocate. */
4286 if ((r_type == R_ARM_THM_CALL)
4287 || (r_type == R_ARM_THM_JUMP24))
4288 {
4289 if (globals->use_blx
4290 && r_type == R_ARM_THM_CALL
4291 && !thumb_only)
4292 {
4293 /* If the Thumb BLX instruction is available, convert
4294 the BL to a BLX instruction to call the ARM-mode
4295 PLT entry. */
4296 branch_type = ST_BRANCH_TO_ARM;
4297 }
4298 else
4299 {
4300 if (!thumb_only)
4301 /* Target the Thumb stub before the ARM PLT entry. */
4302 destination -= PLT_THUMB_STUB_SIZE;
4303 branch_type = ST_BRANCH_TO_THUMB;
4304 }
4305 }
4306 else
4307 {
4308 branch_type = ST_BRANCH_TO_ARM;
4309 }
34e77a92 4310 }
5fa9e92f 4311 }
34e77a92
RS		 4312 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4313 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4314
fe33d2fa
CL		 4315 branch_offset = (bfd_signed_vma)(destination - location);
4316
0855e32b 4317 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4318 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4319 {
5fa9e92f
CL		 4320 /* Handle cases where:
4321 - this call goes too far (different Thumb/Thumb2 max
99059e56 4322 distance)
155d87d7 4323 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4324 Thumb->Arm branch (not bl). A stub is needed in this case,
4325 but only if this call is not through a PLT entry. Indeed,
695344c0 4326 PLT stubs handle mode switching already. */
5e866f5a 4327 if ((!thumb2_bl
906e58ca
NC		 4328 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4329 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4330 || (thumb2_bl
906e58ca
NC		 4331 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4332 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4333 || (thumb2
4334 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4335 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4336 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4337 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4338 && (((r_type == R_ARM_THM_CALL
4339 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4340 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4341 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4342 && !use_plt))
906e58ca 4343 {
2df2751d
CL		 4344 /* If we need to insert a Thumb-Thumb long branch stub to a
4345 PLT, use one that branches directly to the ARM PLT
4346 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4347 stub, undo this now. */
695344c0
NC		 4348 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4349 {
4350 branch_type = ST_BRANCH_TO_ARM;
4351 branch_offset += PLT_THUMB_STUB_SIZE;
4352 }
2df2751d 4353
35fc36a8 4354 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4355 {
4356 /* Thumb to thumb. */
4357 if (!thumb_only)
4358 {
d5a67c02 4359 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4360 _bfd_error_handler
871b3ab2 4361 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4362 " section with SHF_ARM_PURECODE section"
4363 " attribute is only supported for M-profile"
90b6238f 4364 " targets that implement the movw instruction"),
10463f39 4365 input_bfd, input_sec);
d5a67c02 4366
0e1862bb 4367 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4368 /* PIC stubs. */
155d87d7 4369 ? ((globals->use_blx
9553db3c 4370 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4371 /* V5T and above. Stub starts with ARM code, so
4372 we must be able to switch mode before
4373 reaching it, which is only possible for 'bl'
4374 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4375 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4376 /* On V4T, use Thumb code only. */
d3626fb0 4377 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4378
4379 /* non-PIC stubs. */
155d87d7 4380 : ((globals->use_blx
9553db3c 4381 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4382 /* V5T and above. */
4383 ? arm_stub_long_branch_any_any
4384 /* V4T. */
d3626fb0 4385 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4386 }
4387 else
4388 {
d5a67c02
AV		 4389 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4390 stub_type = arm_stub_long_branch_thumb2_only_pure;
4391 else
4392 {
4393 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4394 _bfd_error_handler
871b3ab2 4395 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4396 " section with SHF_ARM_PURECODE section"
4397 " attribute is only supported for M-profile"
90b6238f 4398 " targets that implement the movw instruction"),
10463f39 4399 input_bfd, input_sec);
d5a67c02
AV		 4400
4401 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4402 /* PIC stub. */
4403 ? arm_stub_long_branch_thumb_only_pic
4404 /* non-PIC stub. */
4405 : (thumb2 ? arm_stub_long_branch_thumb2_only
4406 : arm_stub_long_branch_thumb_only);
4407 }
906e58ca
NC		 4408 }
4409 }
4410 else
4411 {
d5a67c02 4412 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4413 _bfd_error_handler
871b3ab2 4414 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4415 " section with SHF_ARM_PURECODE section"
4416 " attribute is only supported" " for M-profile"
90b6238f 4417 " targets that implement the movw instruction"),
10463f39 4418 input_bfd, input_sec);
d5a67c02 4419
906e58ca 4420 /* Thumb to arm. */
c820be07
NC		 4421 if (sym_sec != NULL
4422 && sym_sec->owner != NULL
4423 && !INTERWORK_FLAG (sym_sec->owner))
4424 {
4eca0228 4425 _bfd_error_handler
90b6238f
AM		 4426 (_("%pB(%s): warning: interworking not enabled;"
4427 " first occurrence: %pB: %s call to %s"),
4428 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4429 }
4430
0855e32b 4431 stub_type =
0e1862bb 4432 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4433 /* PIC stubs. */
0855e32b 4434 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4435 /* TLS PIC stubs. */
0855e32b
NS		 4436 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4437 : arm_stub_long_branch_v4t_thumb_tls_pic)
4438 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4439 /* V5T PIC and above. */
4440 ? arm_stub_long_branch_any_arm_pic
4441 /* V4T PIC stub. */
4442 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4443
4444 /* non-PIC stubs. */
0855e32b 4445 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4446 /* V5T and above. */
4447 ? arm_stub_long_branch_any_any
4448 /* V4T. */
4449 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4450
4451 /* Handle v4t short branches. */
fea2b4d6 4452 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4453 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4454 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4455 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4456 }
4457 }
4458 }
fe33d2fa
CL		 4459 else if (r_type == R_ARM_CALL
4460 || r_type == R_ARM_JUMP24
0855e32b
NS		 4461 || r_type == R_ARM_PLT32
4462 || r_type == R_ARM_TLS_CALL)
906e58ca 4463 {
d5a67c02 4464 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4465 _bfd_error_handler
871b3ab2 4466 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4467 " section with SHF_ARM_PURECODE section"
4468 " attribute is only supported for M-profile"
90b6238f 4469 " targets that implement the movw instruction"),
10463f39 4470 input_bfd, input_sec);
35fc36a8 4471 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4472 {
4473 /* Arm to thumb. */
c820be07
NC		 4474
4475 if (sym_sec != NULL
4476 && sym_sec->owner != NULL
4477 && !INTERWORK_FLAG (sym_sec->owner))
4478 {
4eca0228 4479 _bfd_error_handler
90b6238f
AM		 4480 (_("%pB(%s): warning: interworking not enabled;"
4481 " first occurrence: %pB: %s call to %s"),
4482 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4483 }
4484
4485 /* We have an extra 2-bytes reach because of
4486 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4487 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4488 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4489 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4490 || (r_type == R_ARM_JUMP24)
4491 || (r_type == R_ARM_PLT32))
906e58ca 4492 {
0e1862bb 4493 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4494 /* PIC stubs. */
ebe24dd4
CL		 4495 ? ((globals->use_blx)
4496 /* V5T and above. */
4497 ? arm_stub_long_branch_any_thumb_pic
4498 /* V4T stub. */
4499 : arm_stub_long_branch_v4t_arm_thumb_pic)
4500
c2b4a39d
CL		 4501 /* non-PIC stubs. */
4502 : ((globals->use_blx)
4503 /* V5T and above. */
4504 ? arm_stub_long_branch_any_any
4505 /* V4T. */
4506 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4507 }
4508 }
4509 else
4510 {
4511 /* Arm to arm. */
4512 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4513 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4514 {
0855e32b 4515 stub_type =
0e1862bb 4516 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4517 /* PIC stubs. */
0855e32b 4518 ? (r_type == R_ARM_TLS_CALL
6a631e86 4519 /* TLS PIC Stub. */
0855e32b 4520 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4521 : (globals->nacl_p
4522 ? arm_stub_long_branch_arm_nacl_pic
4523 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4524 /* non-PIC stubs. */
7a89b94e
NC		 4525 : (globals->nacl_p
4526 ? arm_stub_long_branch_arm_nacl
4527 : arm_stub_long_branch_any_any);
906e58ca
NC		 4528 }
4529 }
4530 }
4531
fe33d2fa
CL		 4532 /* If a stub is needed, record the actual destination type. */
4533 if (stub_type != arm_stub_none)
35fc36a8 4534 *actual_branch_type = branch_type;
fe33d2fa 4535
906e58ca
NC		 4536 return stub_type;
4537}
4538
4539/* Build a name for an entry in the stub hash table. */
4540
4541static char *
4542elf32_arm_stub_name (const asection *input_section,
4543 const asection *sym_sec,
4544 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4545 const Elf_Internal_Rela *rel,
4546 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4547{
4548 char *stub_name;
4549 bfd_size_type len;
4550
4551 if (hash)
4552 {
fe33d2fa 4553 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4554 stub_name = (char *) bfd_malloc (len);
906e58ca 4555 if (stub_name != NULL)
fe33d2fa 4556 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4557 input_section->id & 0xffffffff,
4558 hash->root.root.root.string,
fe33d2fa
CL		 4559 (int) rel->r_addend & 0xffffffff,
4560 (int) stub_type);
906e58ca
NC		 4561 }
4562 else
4563 {
fe33d2fa 4564 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4565 stub_name = (char *) bfd_malloc (len);
906e58ca 4566 if (stub_name != NULL)
fe33d2fa 4567 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4568 input_section->id & 0xffffffff,
4569 sym_sec->id & 0xffffffff,
0855e32b
NS		 4570 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4571 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4572 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4573 (int) rel->r_addend & 0xffffffff,
4574 (int) stub_type);
906e58ca
NC		 4575 }
4576
4577 return stub_name;
4578}
4579
4580/* Look up an entry in the stub hash. Stub entries are cached because
4581 creating the stub name takes a bit of time. */
4582
4583static struct elf32_arm_stub_hash_entry *
4584elf32_arm_get_stub_entry (const asection *input_section,
4585 const asection *sym_sec,
4586 struct elf_link_hash_entry *hash,
4587 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4588 struct elf32_arm_link_hash_table *htab,
4589 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4590{
4591 struct elf32_arm_stub_hash_entry *stub_entry;
4592 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4593 const asection *id_sec;
4594
4595 if ((input_section->flags & SEC_CODE) == 0)
4596 return NULL;
4597
4d83e8d9
CL		 4598 /* If the input section is the CMSE stubs one and it needs a long
4599 branch stub to reach it's final destination, give up with an
4600 error message: this is not supported. See PR ld/24709. */
4601 if (!strncmp (input_section->name, CMSE_STUB_NAME, strlen(CMSE_STUB_NAME)))
4602 {
4603 bfd *output_bfd = htab->obfd;
4604 asection *out_sec = bfd_get_section_by_name (output_bfd, CMSE_STUB_NAME);
4605
4606 _bfd_error_handler (_("ERROR: CMSE stub (%s section) too far "
4607 "(%#" PRIx64 ") from destination (%#" PRIx64 ")"),
4608 CMSE_STUB_NAME,
4609 (uint64_t)out_sec->output_section->vma
4610 + out_sec->output_offset,
4611 (uint64_t)sym_sec->output_section->vma
4612 + sym_sec->output_offset
4613 + h->root.root.u.def.value);
4614 /* Exit, rather than leave incompletely processed
4615 relocations. */
4616 xexit(1);
4617 }
4618
906e58ca
NC		 4619 /* If this input section is part of a group of sections sharing one
4620 stub section, then use the id of the first section in the group.
4621 Stub names need to include a section id, as there may well be
4622 more than one stub used to reach say, printf, and we need to
4623 distinguish between them. */
c2abbbeb 4624 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4625 id_sec = htab->stub_group[input_section->id].link_sec;
4626
4627 if (h != NULL && h->stub_cache != NULL
4628 && h->stub_cache->h == h
fe33d2fa
CL		 4629 && h->stub_cache->id_sec == id_sec
4630 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4631 {
4632 stub_entry = h->stub_cache;
4633 }
4634 else
4635 {
4636 char *stub_name;
4637
fe33d2fa 4638 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4639 if (stub_name == NULL)
4640 return NULL;
4641
4642 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4643 stub_name, FALSE, FALSE);
4644 if (h != NULL)
4645 h->stub_cache = stub_entry;
4646
4647 free (stub_name);
4648 }
4649
4650 return stub_entry;
4651}
4652
daa4adae
TP		 4653/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4654 section. */
4655
4656static bfd_boolean
4657arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4658{
4659 if (stub_type >= max_stub_type)
4660 abort (); /* Should be unreachable. */
4661
4ba2ef8f
TP		 4662 switch (stub_type)
4663 {
4664 case arm_stub_cmse_branch_thumb_only:
4665 return TRUE;
4666
4667 default:
4668 return FALSE;
4669 }
4670
4671 abort (); /* Should be unreachable. */
daa4adae
TP		 4672}
4673
4674/* Required alignment (as a power of 2) for the dedicated section holding
4675 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4676 with input sections. */
4677
4678static int
4679arm_dedicated_stub_output_section_required_alignment
4680 (enum elf32_arm_stub_type stub_type)
4681{
4682 if (stub_type >= max_stub_type)
4683 abort (); /* Should be unreachable. */
4684
4ba2ef8f
TP		 4685 switch (stub_type)
4686 {
4687 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4688 boundary. */
4689 case arm_stub_cmse_branch_thumb_only:
4690 return 5;
4691
4692 default:
4693 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4694 return 0;
4695 }
4696
4697 abort (); /* Should be unreachable. */
daa4adae
TP		 4698}
4699
4700/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4701 NULL if veneers of this type are interspersed with input sections. */
4702
4703static const char *
4704arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4705{
4706 if (stub_type >= max_stub_type)
4707 abort (); /* Should be unreachable. */
4708
4ba2ef8f
TP		 4709 switch (stub_type)
4710 {
4711 case arm_stub_cmse_branch_thumb_only:
4d83e8d9 4712 return CMSE_STUB_NAME;
4ba2ef8f
TP		 4713
4714 default:
4715 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4716 return NULL;
4717 }
4718
4719 abort (); /* Should be unreachable. */
daa4adae
TP		 4720}
4721
4722/* If veneers of type STUB_TYPE should go in a dedicated output section,
4723 returns the address of the hash table field in HTAB holding a pointer to the
4724 corresponding input section. Otherwise, returns NULL. */
4725
4726static asection **
4ba2ef8f
TP		 4727arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4728 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4729{
4730 if (stub_type >= max_stub_type)
4731 abort (); /* Should be unreachable. */
4732
4ba2ef8f
TP		 4733 switch (stub_type)
4734 {
4735 case arm_stub_cmse_branch_thumb_only:
4736 return &htab->cmse_stub_sec;
4737
4738 default:
4739 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4740 return NULL;
4741 }
4742
4743 abort (); /* Should be unreachable. */
daa4adae
TP		 4744}
4745
4746/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4747 is the section that branch into veneer and can be NULL if stub should go in
4748 a dedicated output section. Returns a pointer to the stub section, and the
4749 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4750 LINK_SEC_P may be NULL. */
906e58ca 4751
48229727
JB		 4752static asection *
4753elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4754 struct elf32_arm_link_hash_table *htab,
4755 enum elf32_arm_stub_type stub_type)
906e58ca 4756{
daa4adae
TP		 4757 asection *link_sec, *out_sec, **stub_sec_p;
4758 const char *stub_sec_prefix;
4759 bfd_boolean dedicated_output_section =
4760 arm_dedicated_stub_output_section_required (stub_type);
4761 int align;
906e58ca 4762
daa4adae 4763 if (dedicated_output_section)
906e58ca 4764 {
daa4adae
TP		 4765 bfd *output_bfd = htab->obfd;
4766 const char *out_sec_name =
4767 arm_dedicated_stub_output_section_name (stub_type);
4768 link_sec = NULL;
4769 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4770 stub_sec_prefix = out_sec_name;
4771 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4772 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4773 if (out_sec == NULL)
906e58ca 4774 {
90b6238f 4775 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4776 "section %s"), out_sec_name);
daa4adae 4777 return NULL;
906e58ca 4778 }
daa4adae
TP		 4779 }
4780 else
4781 {
c2abbbeb 4782 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4783 link_sec = htab->stub_group[section->id].link_sec;
4784 BFD_ASSERT (link_sec != NULL);
4785 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4786 if (*stub_sec_p == NULL)
4787 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4788 stub_sec_prefix = link_sec->name;
4789 out_sec = link_sec->output_section;
4790 align = htab->nacl_p ? 4 : 3;
906e58ca 4791 }
b38cadfb 4792
daa4adae
TP		 4793 if (*stub_sec_p == NULL)
4794 {
4795 size_t namelen;
4796 bfd_size_type len;
4797 char *s_name;
4798
4799 namelen = strlen (stub_sec_prefix);
4800 len = namelen + sizeof (STUB_SUFFIX);
4801 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4802 if (s_name == NULL)
4803 return NULL;
4804
4805 memcpy (s_name, stub_sec_prefix, namelen);
4806 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4807 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4808 align);
4809 if (*stub_sec_p == NULL)
4810 return NULL;
4811
4812 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4813 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4814 | SEC_KEEP;
4815 }
4816
4817 if (!dedicated_output_section)
4818 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4819
48229727
JB		 4820 if (link_sec_p)
4821 *link_sec_p = link_sec;
b38cadfb 4822
daa4adae 4823 return *stub_sec_p;
48229727
JB		 4824}
4825
4826/* Add a new stub entry to the stub hash. Not all fields of the new
4827 stub entry are initialised. */
4828
4829static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4830elf32_arm_add_stub (const char *stub_name, asection *section,
4831 struct elf32_arm_link_hash_table *htab,
4832 enum elf32_arm_stub_type stub_type)
48229727
JB		 4833{
4834 asection *link_sec;
4835 asection *stub_sec;
4836 struct elf32_arm_stub_hash_entry *stub_entry;
4837
daa4adae
TP		 4838 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4839 stub_type);
48229727
JB		 4840 if (stub_sec == NULL)
4841 return NULL;
906e58ca
NC		 4842
4843 /* Enter this entry into the linker stub hash table. */
4844 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4845 TRUE, FALSE);
4846 if (stub_entry == NULL)
4847 {
6bde4c52
TP		 4848 if (section == NULL)
4849 section = stub_sec;
871b3ab2 4850 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4851 section->owner, stub_name);
906e58ca
NC		 4852 return NULL;
4853 }
4854
4855 stub_entry->stub_sec = stub_sec;
0955507f 4856 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4857 stub_entry->id_sec = link_sec;
4858
906e58ca
NC		 4859 return stub_entry;
4860}
4861
4862/* Store an Arm insn into an output section not processed by
4863 elf32_arm_write_section. */
4864
4865static void
8029a119
NC		 4866put_arm_insn (struct elf32_arm_link_hash_table * htab,
4867 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4868{
4869 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4870 bfd_putl32 (val, ptr);
4871 else
4872 bfd_putb32 (val, ptr);
4873}
4874
4875/* Store a 16-bit Thumb insn into an output section not processed by
4876 elf32_arm_write_section. */
4877
4878static void
8029a119
NC		 4879put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4880 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4881{
4882 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4883 bfd_putl16 (val, ptr);
4884 else
4885 bfd_putb16 (val, ptr);
4886}
4887
a504d23a
LA		 4888/* Store a Thumb2 insn into an output section not processed by
4889 elf32_arm_write_section. */
4890
4891static void
4892put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4893 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4894{
4895 /* T2 instructions are 16-bit streamed. */
4896 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4897 {
4898 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4899 bfd_putl16 ((val & 0xffff), ptr + 2);
4900 }
4901 else
4902 {
4903 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4904 bfd_putb16 ((val & 0xffff), ptr + 2);
4905 }
4906}
4907
0855e32b
NS		 4908/* If it's possible to change R_TYPE to a more efficient access
4909 model, return the new reloc type. */
4910
4911static unsigned
b38cadfb 4912elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4913 struct elf_link_hash_entry *h)
4914{
4915 int is_local = (h == NULL);
4916
9cb09e33 4917 if (bfd_link_dll (info)
0e1862bb 4918 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4919 return r_type;
4920
b38cadfb 4921 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4922 switch (r_type)
4923 {
4924 case R_ARM_TLS_GOTDESC:
4925 case R_ARM_TLS_CALL:
4926 case R_ARM_THM_TLS_CALL:
4927 case R_ARM_TLS_DESCSEQ:
4928 case R_ARM_THM_TLS_DESCSEQ:
4929 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4930 }
4931
4932 return r_type;
4933}
4934
48229727
JB		 4935static bfd_reloc_status_type elf32_arm_final_link_relocate
4936 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4937 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4938 const char *, unsigned char, enum arm_st_branch_type,
4939 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4940
4563a860
JB		 4941static unsigned int
4942arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4943{
4944 switch (stub_type)
4945 {
4946 case arm_stub_a8_veneer_b_cond:
4947 case arm_stub_a8_veneer_b:
4948 case arm_stub_a8_veneer_bl:
4949 return 2;
4950
4951 case arm_stub_long_branch_any_any:
4952 case arm_stub_long_branch_v4t_arm_thumb:
4953 case arm_stub_long_branch_thumb_only:
80c135e5 4954 case arm_stub_long_branch_thumb2_only:
d5a67c02 4955 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4956 case arm_stub_long_branch_v4t_thumb_thumb:
4957 case arm_stub_long_branch_v4t_thumb_arm:
4958 case arm_stub_short_branch_v4t_thumb_arm:
4959 case arm_stub_long_branch_any_arm_pic:
4960 case arm_stub_long_branch_any_thumb_pic:
4961 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4962 case arm_stub_long_branch_v4t_arm_thumb_pic:
4963 case arm_stub_long_branch_v4t_thumb_arm_pic:
4964 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4965 case arm_stub_long_branch_any_tls_pic:
4966 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4967 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4968 case arm_stub_a8_veneer_blx:
4969 return 4;
b38cadfb 4970
7a89b94e
NC		 4971 case arm_stub_long_branch_arm_nacl:
4972 case arm_stub_long_branch_arm_nacl_pic:
4973 return 16;
4974
4563a860
JB		 4975 default:
4976 abort (); /* Should be unreachable. */
4977 }
4978}
4979
4f4faa4d
TP		 4980/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4981 veneering (TRUE) or have their own symbol (FALSE). */
4982
4983static bfd_boolean
4984arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4985{
4986 if (stub_type >= max_stub_type)
4987 abort (); /* Should be unreachable. */
4988
4ba2ef8f
TP		 4989 switch (stub_type)
4990 {
4991 case arm_stub_cmse_branch_thumb_only:
4992 return TRUE;
4993
4994 default:
4995 return FALSE;
4996 }
4997
4998 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4999}
5000
d7c5bd02
TP		 5001/* Returns the padding needed for the dedicated section used stubs of type
5002 STUB_TYPE. */
5003
5004static int
5005arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
5006{
5007 if (stub_type >= max_stub_type)
5008 abort (); /* Should be unreachable. */
5009
4ba2ef8f
TP		 5010 switch (stub_type)
5011 {
5012 case arm_stub_cmse_branch_thumb_only:
5013 return 32;
5014
5015 default:
5016 return 0;
5017 }
5018
5019 abort (); /* Should be unreachable. */
d7c5bd02
TP		 5020}
5021
0955507f
TP		 5022/* If veneers of type STUB_TYPE should go in a dedicated output section,
5023 returns the address of the hash table field in HTAB holding the offset at
5024 which new veneers should be layed out in the stub section. */
5025
5026static bfd_vma*
5027arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
5028 enum elf32_arm_stub_type stub_type)
5029{
5030 switch (stub_type)
5031 {
5032 case arm_stub_cmse_branch_thumb_only:
5033 return &htab->new_cmse_stub_offset;
5034
5035 default:
5036 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
5037 return NULL;
5038 }
5039}
5040
906e58ca
NC		 5041static bfd_boolean
5042arm_build_one_stub (struct bfd_hash_entry *gen_entry,
5043 void * in_arg)
5044{
7a89b94e 5045#define MAXRELOCS 3
0955507f 5046 bfd_boolean removed_sg_veneer;
906e58ca 5047 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 5048 struct elf32_arm_link_hash_table *globals;
906e58ca 5049 struct bfd_link_info *info;
906e58ca
NC		 5050 asection *stub_sec;
5051 bfd *stub_bfd;
906e58ca
NC		 5052 bfd_byte *loc;
5053 bfd_vma sym_value;
5054 int template_size;
5055 int size;
d3ce72d0 5056 const insn_sequence *template_sequence;
906e58ca 5057 int i;
48229727
JB		 5058 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
5059 int stub_reloc_offset[MAXRELOCS] = {0, 0};
5060 int nrelocs = 0;
0955507f 5061 int just_allocated = 0;
906e58ca
NC		 5062
5063 /* Massage our args to the form they really have. */
5064 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5065 info = (struct bfd_link_info *) in_arg;
5066
5067 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5068 if (globals == NULL)
5069 return FALSE;
906e58ca 5070
906e58ca
NC		 5071 stub_sec = stub_entry->stub_sec;
5072
4dfe6ac6 5073 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 5074 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
5075 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 5076 return TRUE;
fe33d2fa 5077
0955507f
TP		 5078 /* Assign a slot at the end of section if none assigned yet. */
5079 if (stub_entry->stub_offset == (bfd_vma) -1)
5080 {
5081 stub_entry->stub_offset = stub_sec->size;
5082 just_allocated = 1;
5083 }
906e58ca
NC		 5084 loc = stub_sec->contents + stub_entry->stub_offset;
5085
5086 stub_bfd = stub_sec->owner;
5087
906e58ca
NC		 5088 /* This is the address of the stub destination. */
5089 sym_value = (stub_entry->target_value
5090 + stub_entry->target_section->output_offset
5091 + stub_entry->target_section->output_section->vma);
5092
d3ce72d0 5093 template_sequence = stub_entry->stub_template;
461a49ca 5094 template_size = stub_entry->stub_template_size;
906e58ca
NC		 5095
5096 size = 0;
461a49ca 5097 for (i = 0; i < template_size; i++)
906e58ca 5098 {
d3ce72d0 5099 switch (template_sequence[i].type)
461a49ca
DJ		 5100 {
5101 case THUMB16_TYPE:
48229727 5102 {
d3ce72d0
NC		 5103 bfd_vma data = (bfd_vma) template_sequence[i].data;
5104 if (template_sequence[i].reloc_addend != 0)
48229727 5105 {
99059e56
RM		 5106 /* We've borrowed the reloc_addend field to mean we should
5107 insert a condition code into this (Thumb-1 branch)
5108 instruction. See THUMB16_BCOND_INSN. */
5109 BFD_ASSERT ((data & 0xff00) == 0xd000);
5110 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 5111 }
fe33d2fa 5112 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 5113 size += 2;
5114 }
461a49ca 5115 break;
906e58ca 5116
48229727 5117 case THUMB32_TYPE:
fe33d2fa
CL		 5118 bfd_put_16 (stub_bfd,
5119 (template_sequence[i].data >> 16) & 0xffff,
5120 loc + size);
5121 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5122 loc + size + 2);
99059e56
RM		 5123 if (template_sequence[i].r_type != R_ARM_NONE)
5124 {
5125 stub_reloc_idx[nrelocs] = i;
5126 stub_reloc_offset[nrelocs++] = size;
5127 }
5128 size += 4;
5129 break;
48229727 5130
461a49ca 5131 case ARM_TYPE:
fe33d2fa
CL		 5132 bfd_put_32 (stub_bfd, template_sequence[i].data,
5133 loc + size);
461a49ca
DJ		 5134 /* Handle cases where the target is encoded within the
5135 instruction. */
d3ce72d0 5136 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 5137 {
48229727
JB		 5138 stub_reloc_idx[nrelocs] = i;
5139 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5140 }
5141 size += 4;
5142 break;
5143
5144 case DATA_TYPE:
d3ce72d0 5145 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 5146 stub_reloc_idx[nrelocs] = i;
5147 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5148 size += 4;
5149 break;
5150
5151 default:
5152 BFD_FAIL ();
5153 return FALSE;
5154 }
906e58ca 5155 }
461a49ca 5156
0955507f
TP		 5157 if (just_allocated)
5158 stub_sec->size += size;
906e58ca 5159
461a49ca
DJ		 5160 /* Stub size has already been computed in arm_size_one_stub. Check
5161 consistency. */
5162 BFD_ASSERT (size == stub_entry->stub_size);
5163
906e58ca 5164 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 5165 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 5166 sym_value |= 1;
5167
0955507f
TP		 5168 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5169 to relocate in each stub. */
5170 removed_sg_veneer =
5171 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5172 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 5173
48229727 5174 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 5175 {
5176 Elf_Internal_Rela rel;
5177 bfd_boolean unresolved_reloc;
5178 char *error_message;
5179 bfd_vma points_to =
5180 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5181
5182 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5183 rel.r_info = ELF32_R_INFO (0,
5184 template_sequence[stub_reloc_idx[i]].r_type);
5185 rel.r_addend = 0;
5186
5187 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5188 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5189 template should refer back to the instruction after the original
5190 branch. We use target_section as Cortex-A8 erratum workaround stubs
5191 are only generated when both source and target are in the same
5192 section. */
5193 points_to = stub_entry->target_section->output_section->vma
5194 + stub_entry->target_section->output_offset
5195 + stub_entry->source_value;
5196
5197 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5198 (template_sequence[stub_reloc_idx[i]].r_type),
5199 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5200 points_to, info, stub_entry->target_section, "", STT_FUNC,
5201 stub_entry->branch_type,
5202 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5203 &error_message);
5204 }
906e58ca
NC		 5205
5206 return TRUE;
48229727 5207#undef MAXRELOCS
906e58ca
NC		 5208}
5209
48229727
JB		 5210/* Calculate the template, template size and instruction size for a stub.
5211 Return value is the instruction size. */
906e58ca 5212
48229727
JB		 5213static unsigned int
5214find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5215 const insn_sequence **stub_template,
5216 int *stub_template_size)
906e58ca 5217{
d3ce72d0 5218 const insn_sequence *template_sequence = NULL;
48229727
JB		 5219 int template_size = 0, i;
5220 unsigned int size;
906e58ca 5221
d3ce72d0 5222 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 5223 if (stub_template)
5224 *stub_template = template_sequence;
5225
48229727 5226 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 5227 if (stub_template_size)
5228 *stub_template_size = template_size;
906e58ca
NC		 5229
5230 size = 0;
461a49ca
DJ		 5231 for (i = 0; i < template_size; i++)
5232 {
d3ce72d0 5233 switch (template_sequence[i].type)
461a49ca
DJ		 5234 {
5235 case THUMB16_TYPE:
5236 size += 2;
5237 break;
5238
5239 case ARM_TYPE:
48229727 5240 case THUMB32_TYPE:
461a49ca
DJ		 5241 case DATA_TYPE:
5242 size += 4;
5243 break;
5244
5245 default:
5246 BFD_FAIL ();
2a229407 5247 return 0;
461a49ca
DJ		 5248 }
5249 }
5250
48229727
JB		 5251 return size;
5252}
5253
5254/* As above, but don't actually build the stub. Just bump offset so
5255 we know stub section sizes. */
5256
5257static bfd_boolean
5258arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 5259 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 5260{
5261 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 5262 const insn_sequence *template_sequence;
48229727
JB		 5263 int template_size, size;
5264
5265 /* Massage our args to the form they really have. */
5266 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 5267
5268 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
5269 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
5270
d3ce72d0 5271 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 5272 &template_size);
5273
0955507f
TP		 5274 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5275 if (stub_entry->stub_template_size)
5276 {
5277 stub_entry->stub_size = size;
5278 stub_entry->stub_template = template_sequence;
5279 stub_entry->stub_template_size = template_size;
5280 }
5281
5282 /* Already accounted for. */
5283 if (stub_entry->stub_offset != (bfd_vma) -1)
5284 return TRUE;
461a49ca 5285
906e58ca
NC		 5286 size = (size + 7) & ~7;
5287 stub_entry->stub_sec->size += size;
461a49ca 5288
906e58ca
NC		 5289 return TRUE;
5290}
5291
5292/* External entry points for sizing and building linker stubs. */
5293
5294/* Set up various things so that we can make a list of input sections
5295 for each output section included in the link. Returns -1 on error,
5296 0 when no stubs will be needed, and 1 on success. */
5297
5298int
5299elf32_arm_setup_section_lists (bfd *output_bfd,
5300 struct bfd_link_info *info)
5301{
5302 bfd *input_bfd;
5303 unsigned int bfd_count;
7292b3ac 5304 unsigned int top_id, top_index;
906e58ca
NC		 5305 asection *section;
5306 asection **input_list, **list;
5307 bfd_size_type amt;
5308 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5309
4dfe6ac6
NC		 5310 if (htab == NULL)
5311 return 0;
906e58ca
NC		 5312 if (! is_elf_hash_table (htab))
5313 return 0;
5314
5315 /* Count the number of input BFDs and find the top input section id. */
5316 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5317 input_bfd != NULL;
c72f2fb2 5318 input_bfd = input_bfd->link.next)
906e58ca
NC		 5319 {
5320 bfd_count += 1;
5321 for (section = input_bfd->sections;
5322 section != NULL;
5323 section = section->next)
5324 {
5325 if (top_id < section->id)
5326 top_id = section->id;
5327 }
5328 }
5329 htab->bfd_count = bfd_count;
5330
5331 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5332 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5333 if (htab->stub_group == NULL)
5334 return -1;
fe33d2fa 5335 htab->top_id = top_id;
906e58ca
NC		 5336
5337 /* We can't use output_bfd->section_count here to find the top output
5338 section index as some sections may have been removed, and
5339 _bfd_strip_section_from_output doesn't renumber the indices. */
5340 for (section = output_bfd->sections, top_index = 0;
5341 section != NULL;
5342 section = section->next)
5343 {
5344 if (top_index < section->index)
5345 top_index = section->index;
5346 }
5347
5348 htab->top_index = top_index;
5349 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5350 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5351 htab->input_list = input_list;
5352 if (input_list == NULL)
5353 return -1;
5354
5355 /* For sections we aren't interested in, mark their entries with a
5356 value we can check later. */
5357 list = input_list + top_index;
5358 do
5359 *list = bfd_abs_section_ptr;
5360 while (list-- != input_list);
5361
5362 for (section = output_bfd->sections;
5363 section != NULL;
5364 section = section->next)
5365 {
5366 if ((section->flags & SEC_CODE) != 0)
5367 input_list[section->index] = NULL;
5368 }
5369
5370 return 1;
5371}
5372
5373/* The linker repeatedly calls this function for each input section,
5374 in the order that input sections are linked into output sections.
5375 Build lists of input sections to determine groupings between which
5376 we may insert linker stubs. */
5377
5378void
5379elf32_arm_next_input_section (struct bfd_link_info *info,
5380 asection *isec)
5381{
5382 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5383
4dfe6ac6
NC		 5384 if (htab == NULL)
5385 return;
5386
906e58ca
NC		 5387 if (isec->output_section->index <= htab->top_index)
5388 {
5389 asection **list = htab->input_list + isec->output_section->index;
5390
a7470592 5391 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5392 {
5393 /* Steal the link_sec pointer for our list. */
5394#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5395 /* This happens to make the list in reverse order,
07d72278 5396 which we reverse later. */
906e58ca
NC		 5397 PREV_SEC (isec) = *list;
5398 *list = isec;
5399 }
5400 }
5401}
5402
5403/* See whether we can group stub sections together. Grouping stub
5404 sections may result in fewer stubs. More importantly, we need to
07d72278 5405 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5406 .fini output sections respectively, because glibc splits the
5407 _init and _fini functions into multiple parts. Putting a stub in
5408 the middle of a function is not a good idea. */
5409
5410static void
5411group_sections (struct elf32_arm_link_hash_table *htab,
5412 bfd_size_type stub_group_size,
07d72278 5413 bfd_boolean stubs_always_after_branch)
906e58ca 5414{
07d72278 5415 asection **list = htab->input_list;
906e58ca
NC		 5416
5417 do
5418 {
5419 asection *tail = *list;
07d72278 5420 asection *head;
906e58ca
NC		 5421
5422 if (tail == bfd_abs_section_ptr)
5423 continue;
5424
07d72278
DJ		 5425 /* Reverse the list: we must avoid placing stubs at the
5426 beginning of the section because the beginning of the text
5427 section may be required for an interrupt vector in bare metal
5428 code. */
5429#define NEXT_SEC PREV_SEC
e780aef2
CL		 5430 head = NULL;
5431 while (tail != NULL)
99059e56
RM		 5432 {
5433 /* Pop from tail. */
5434 asection *item = tail;
5435 tail = PREV_SEC (item);
e780aef2 5436
99059e56
RM		 5437 /* Push on head. */
5438 NEXT_SEC (item) = head;
5439 head = item;
5440 }
07d72278
DJ		 5441
5442 while (head != NULL)
906e58ca
NC		 5443 {
5444 asection *curr;
07d72278 5445 asection *next;
e780aef2
CL		 5446 bfd_vma stub_group_start = head->output_offset;
5447 bfd_vma end_of_next;
906e58ca 5448
07d72278 5449 curr = head;
e780aef2 5450 while (NEXT_SEC (curr) != NULL)
8cd931b7 5451 {
e780aef2
CL		 5452 next = NEXT_SEC (curr);
5453 end_of_next = next->output_offset + next->size;
5454 if (end_of_next - stub_group_start >= stub_group_size)
5455 /* End of NEXT is too far from start, so stop. */
8cd931b7 5456 break;
e780aef2
CL		 5457 /* Add NEXT to the group. */
5458 curr = next;
8cd931b7 5459 }
906e58ca 5460
07d72278 5461 /* OK, the size from the start to the start of CURR is less
906e58ca 5462 than stub_group_size and thus can be handled by one stub
07d72278 5463 section. (Or the head section is itself larger than
906e58ca
NC		 5464 stub_group_size, in which case we may be toast.)
5465 We should really be keeping track of the total size of
5466 stubs added here, as stubs contribute to the final output
7fb9f789 5467 section size. */
906e58ca
NC		 5468 do
5469 {
07d72278 5470 next = NEXT_SEC (head);
906e58ca 5471 /* Set up this stub group. */
07d72278 5472 htab->stub_group[head->id].link_sec = curr;
906e58ca 5473 }
07d72278 5474 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5475
5476 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5477 bytes after the stub section can be handled by it too. */
5478 if (!stubs_always_after_branch)
906e58ca 5479 {
e780aef2
CL		 5480 stub_group_start = curr->output_offset + curr->size;
5481
8cd931b7 5482 while (next != NULL)
906e58ca 5483 {
e780aef2
CL		 5484 end_of_next = next->output_offset + next->size;
5485 if (end_of_next - stub_group_start >= stub_group_size)
5486 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5487 break;
e780aef2 5488 /* Add NEXT to the stub group. */
07d72278
DJ		 5489 head = next;
5490 next = NEXT_SEC (head);
5491 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5492 }
5493 }
07d72278 5494 head = next;
906e58ca
NC		 5495 }
5496 }
07d72278 5497 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5498
5499 free (htab->input_list);
5500#undef PREV_SEC
07d72278 5501#undef NEXT_SEC
906e58ca
NC		 5502}
5503
48229727
JB		 5504/* Comparison function for sorting/searching relocations relating to Cortex-A8
5505 erratum fix. */
5506
5507static int
5508a8_reloc_compare (const void *a, const void *b)
5509{
21d799b5
NC		 5510 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5511 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5512
5513 if (ra->from < rb->from)
5514 return -1;
5515 else if (ra->from > rb->from)
5516 return 1;
5517 else
5518 return 0;
5519}
5520
5521static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5522 const char *, char **);
5523
5524/* Helper function to scan code for sequences which might trigger the Cortex-A8
5525 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5526 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5527 otherwise. */
5528
81694485
NC		 5529static bfd_boolean
5530cortex_a8_erratum_scan (bfd *input_bfd,
5531 struct bfd_link_info *info,
48229727
JB		 5532 struct a8_erratum_fix **a8_fixes_p,
5533 unsigned int *num_a8_fixes_p,
5534 unsigned int *a8_fix_table_size_p,
5535 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5536 unsigned int num_a8_relocs,
5537 unsigned prev_num_a8_fixes,
5538 bfd_boolean *stub_changed_p)
48229727
JB		 5539{
5540 asection *section;
5541 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5542 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5543 unsigned int num_a8_fixes = *num_a8_fixes_p;
5544 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5545
4dfe6ac6
NC		 5546 if (htab == NULL)
5547 return FALSE;
5548
48229727
JB		 5549 for (section = input_bfd->sections;
5550 section != NULL;
5551 section = section->next)
5552 {
5553 bfd_byte *contents = NULL;
5554 struct _arm_elf_section_data *sec_data;
5555 unsigned int span;
5556 bfd_vma base_vma;
5557
5558 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5559 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5560 || (section->flags & SEC_EXCLUDE) != 0
5561 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5562 || (section->output_section == bfd_abs_section_ptr))
5563 continue;
48229727
JB		 5564
5565 base_vma = section->output_section->vma + section->output_offset;
5566
5567 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5568 contents = elf_section_data (section)->this_hdr.contents;
48229727 5569 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5570 return TRUE;
48229727
JB		 5571
5572 sec_data = elf32_arm_section_data (section);
5573
5574 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5575 {
5576 unsigned int span_start = sec_data->map[span].vma;
5577 unsigned int span_end = (span == sec_data->mapcount - 1)
5578 ? section->size : sec_data->map[span + 1].vma;
5579 unsigned int i;
5580 char span_type = sec_data->map[span].type;
5581 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5582
5583 if (span_type != 't')
5584 continue;
5585
5586 /* Span is entirely within a single 4KB region: skip scanning. */
5587 if (((base_vma + span_start) & ~0xfff)
48229727 5588 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5589 continue;
5590
5591 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5592
5593 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5594 * The branch target is in the same 4KB region as the
5595 first half of the branch.
5596 * The instruction before the branch is a 32-bit
5597 length non-branch instruction. */
5598 for (i = span_start; i < span_end;)
5599 {
5600 unsigned int insn = bfd_getl16 (&contents[i]);
5601 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5602 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5603
99059e56
RM		 5604 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5605 insn_32bit = TRUE;
48229727
JB		 5606
5607 if (insn_32bit)
99059e56
RM		 5608 {
5609 /* Load the rest of the insn (in manual-friendly order). */
5610 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5611
5612 /* Encoding T4: B<c>.W. */
5613 is_b = (insn & 0xf800d000) == 0xf0009000;
5614 /* Encoding T1: BL<c>.W. */
5615 is_bl = (insn & 0xf800d000) == 0xf000d000;
5616 /* Encoding T2: BLX<c>.W. */
5617 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5618 /* Encoding T3: B<c>.W (not permitted in IT block). */
5619 is_bcc = (insn & 0xf800d000) == 0xf0008000
5620 && (insn & 0x07f00000) != 0x03800000;
5621 }
5622
5623 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5624
99059e56 5625 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5626 && insn_32bit
5627 && is_32bit_branch
5628 && last_was_32bit
5629 && ! last_was_branch)
99059e56
RM		 5630 {
5631 bfd_signed_vma offset = 0;
5632 bfd_boolean force_target_arm = FALSE;
48229727 5633 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5634 bfd_vma target;
5635 enum elf32_arm_stub_type stub_type = arm_stub_none;
5636 struct a8_erratum_reloc key, *found;
5637 bfd_boolean use_plt = FALSE;
48229727 5638
99059e56
RM		 5639 key.from = base_vma + i;
5640 found = (struct a8_erratum_reloc *)
5641 bsearch (&key, a8_relocs, num_a8_relocs,
5642 sizeof (struct a8_erratum_reloc),
5643 &a8_reloc_compare);
48229727
JB		 5644
5645 if (found)
5646 {
5647 char *error_message = NULL;
5648 struct elf_link_hash_entry *entry;
5649
5650 /* We don't care about the error returned from this
99059e56 5651 function, only if there is glue or not. */
48229727
JB		 5652 entry = find_thumb_glue (info, found->sym_name,
5653 &error_message);
5654
5655 if (entry)
5656 found->non_a8_stub = TRUE;
5657
92750f34 5658 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5659 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5660 && found->hash->root.plt.offset != (bfd_vma) -1)
5661 use_plt = TRUE;
5662
5663 if (found->r_type == R_ARM_THM_CALL)
5664 {
35fc36a8
RS		 5665 if (found->branch_type == ST_BRANCH_TO_ARM
5666 || use_plt)
92750f34
DJ		 5667 force_target_arm = TRUE;
5668 else
5669 force_target_thumb = TRUE;
5670 }
48229727
JB		 5671 }
5672
99059e56 5673 /* Check if we have an offending branch instruction. */
48229727
JB		 5674
5675 if (found && found->non_a8_stub)
5676 /* We've already made a stub for this instruction, e.g.
5677 it's a long branch or a Thumb->ARM stub. Assume that
5678 stub will suffice to work around the A8 erratum (see
5679 setting of always_after_branch above). */
5680 ;
99059e56
RM		 5681 else if (is_bcc)
5682 {
5683 offset = (insn & 0x7ff) << 1;
5684 offset |= (insn & 0x3f0000) >> 4;
5685 offset |= (insn & 0x2000) ? 0x40000 : 0;
5686 offset |= (insn & 0x800) ? 0x80000 : 0;
5687 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5688 if (offset & 0x100000)
5689 offset |= ~ ((bfd_signed_vma) 0xfffff);
5690 stub_type = arm_stub_a8_veneer_b_cond;
5691 }
5692 else if (is_b || is_bl || is_blx)
5693 {
5694 int s = (insn & 0x4000000) != 0;
5695 int j1 = (insn & 0x2000) != 0;
5696 int j2 = (insn & 0x800) != 0;
5697 int i1 = !(j1 ^ s);
5698 int i2 = !(j2 ^ s);
5699
5700 offset = (insn & 0x7ff) << 1;
5701 offset |= (insn & 0x3ff0000) >> 4;
5702 offset |= i2 << 22;
5703 offset |= i1 << 23;
5704 offset |= s << 24;
5705 if (offset & 0x1000000)
5706 offset |= ~ ((bfd_signed_vma) 0xffffff);
5707
5708 if (is_blx)
5709 offset &= ~ ((bfd_signed_vma) 3);
5710
5711 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5712 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5713 }
5714
5715 if (stub_type != arm_stub_none)
5716 {
5717 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5718
5719 /* The original instruction is a BL, but the target is
99059e56 5720 an ARM instruction. If we were not making a stub,
48229727
JB		 5721 the BL would have been converted to a BLX. Use the
5722 BLX stub instead in that case. */
5723 if (htab->use_blx && force_target_arm
5724 && stub_type == arm_stub_a8_veneer_bl)
5725 {
5726 stub_type = arm_stub_a8_veneer_blx;
5727 is_blx = TRUE;
5728 is_bl = FALSE;
5729 }
5730 /* Conversely, if the original instruction was
5731 BLX but the target is Thumb mode, use the BL
5732 stub. */
5733 else if (force_target_thumb
5734 && stub_type == arm_stub_a8_veneer_blx)
5735 {
5736 stub_type = arm_stub_a8_veneer_bl;
5737 is_blx = FALSE;
5738 is_bl = TRUE;
5739 }
5740
99059e56
RM		 5741 if (is_blx)
5742 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5743
99059e56
RM		 5744 /* If we found a relocation, use the proper destination,
5745 not the offset in the (unrelocated) instruction.
48229727
JB		 5746 Note this is always done if we switched the stub type
5747 above. */
99059e56
RM		 5748 if (found)
5749 offset =
81694485 5750 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5751
99059e56
RM		 5752 /* If the stub will use a Thumb-mode branch to a
5753 PLT target, redirect it to the preceding Thumb
5754 entry point. */
5755 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5756 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5757
99059e56 5758 target = pc_for_insn + offset;
48229727 5759
99059e56
RM		 5760 /* The BLX stub is ARM-mode code. Adjust the offset to
5761 take the different PC value (+8 instead of +4) into
48229727 5762 account. */
99059e56
RM		 5763 if (stub_type == arm_stub_a8_veneer_blx)
5764 offset += 4;
5765
5766 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5767 {
5768 char *stub_name = NULL;
5769
5770 if (num_a8_fixes == a8_fix_table_size)
5771 {
5772 a8_fix_table_size *= 2;
5773 a8_fixes = (struct a8_erratum_fix *)
5774 bfd_realloc (a8_fixes,
5775 sizeof (struct a8_erratum_fix)
5776 * a8_fix_table_size);
5777 }
48229727 5778
eb7c4339
NS		 5779 if (num_a8_fixes < prev_num_a8_fixes)
5780 {
5781 /* If we're doing a subsequent scan,
5782 check if we've found the same fix as
5783 before, and try and reuse the stub
5784 name. */
5785 stub_name = a8_fixes[num_a8_fixes].stub_name;
5786 if ((a8_fixes[num_a8_fixes].section != section)
5787 || (a8_fixes[num_a8_fixes].offset != i))
5788 {
5789 free (stub_name);
5790 stub_name = NULL;
5791 *stub_changed_p = TRUE;
5792 }
5793 }
5794
5795 if (!stub_name)
5796 {
21d799b5 5797 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5798 if (stub_name != NULL)
5799 sprintf (stub_name, "%x:%x", section->id, i);
5800 }
48229727 5801
99059e56
RM		 5802 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5803 a8_fixes[num_a8_fixes].section = section;
5804 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5805 a8_fixes[num_a8_fixes].target_offset =
5806 target - base_vma;
99059e56
RM		 5807 a8_fixes[num_a8_fixes].orig_insn = insn;
5808 a8_fixes[num_a8_fixes].stub_name = stub_name;
5809 a8_fixes[num_a8_fixes].stub_type = stub_type;
5810 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5811 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5812
99059e56
RM		 5813 num_a8_fixes++;
5814 }
5815 }
5816 }
48229727 5817
99059e56
RM		 5818 i += insn_32bit ? 4 : 2;
5819 last_was_32bit = insn_32bit;
48229727 5820 last_was_branch = is_32bit_branch;
99059e56
RM		 5821 }
5822 }
48229727
JB		 5823
5824 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5825 free (contents);
48229727 5826 }
fe33d2fa 5827
48229727
JB		 5828 *a8_fixes_p = a8_fixes;
5829 *num_a8_fixes_p = num_a8_fixes;
5830 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5831
81694485 5832 return FALSE;
48229727
JB		 5833}
5834
b715f643
TP		 5835/* Create or update a stub entry depending on whether the stub can already be
5836 found in HTAB. The stub is identified by:
5837 - its type STUB_TYPE
5838 - its source branch (note that several can share the same stub) whose
5839 section and relocation (if any) are given by SECTION and IRELA
5840 respectively
5841 - its target symbol whose input section, hash, name, value and branch type
5842 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5843 respectively
5844
5845 If found, the value of the stub's target symbol is updated from SYM_VALUE
5846 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5847 TRUE and the stub entry is initialized.
5848
0955507f
TP		 5849 Returns the stub that was created or updated, or NULL if an error
5850 occurred. */
b715f643 5851
0955507f 5852static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5853elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5854 enum elf32_arm_stub_type stub_type, asection *section,
5855 Elf_Internal_Rela *irela, asection *sym_sec,
5856 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5857 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5858 bfd_boolean *new_stub)
5859{
5860 const asection *id_sec;
5861 char *stub_name;
5862 struct elf32_arm_stub_hash_entry *stub_entry;
5863 unsigned int r_type;
4f4faa4d 5864 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5865
5866 BFD_ASSERT (stub_type != arm_stub_none);
5867 *new_stub = FALSE;
5868
4f4faa4d
TP		 5869 if (sym_claimed)
5870 stub_name = sym_name;
5871 else
5872 {
5873 BFD_ASSERT (irela);
5874 BFD_ASSERT (section);
c2abbbeb 5875 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5876
4f4faa4d
TP		 5877 /* Support for grouping stub sections. */
5878 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5879
4f4faa4d
TP		 5880 /* Get the name of this stub. */
5881 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5882 stub_type);
5883 if (!stub_name)
0955507f 5884 return NULL;
4f4faa4d 5885 }
b715f643
TP		 5886
5887 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5888 FALSE);
5889 /* The proper stub has already been created, just update its value. */
5890 if (stub_entry != NULL)
5891 {
4f4faa4d
TP		 5892 if (!sym_claimed)
5893 free (stub_name);
b715f643 5894 stub_entry->target_value = sym_value;
0955507f 5895 return stub_entry;
b715f643
TP		 5896 }
5897
daa4adae 5898 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5899 if (stub_entry == NULL)
5900 {
4f4faa4d
TP		 5901 if (!sym_claimed)
5902 free (stub_name);
0955507f 5903 return NULL;
b715f643
TP		 5904 }
5905
5906 stub_entry->target_value = sym_value;
5907 stub_entry->target_section = sym_sec;
5908 stub_entry->stub_type = stub_type;
5909 stub_entry->h = hash;
5910 stub_entry->branch_type = branch_type;
5911
4f4faa4d
TP		 5912 if (sym_claimed)
5913 stub_entry->output_name = sym_name;
5914 else
b715f643 5915 {
4f4faa4d
TP		 5916 if (sym_name == NULL)
5917 sym_name = "unnamed";
5918 stub_entry->output_name = (char *)
5919 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5920 + strlen (sym_name));
5921 if (stub_entry->output_name == NULL)
5922 {
5923 free (stub_name);
0955507f 5924 return NULL;
4f4faa4d 5925 }
b715f643 5926
4f4faa4d
TP		 5927 /* For historical reasons, use the existing names for ARM-to-Thumb and
5928 Thumb-to-ARM stubs. */
5929 r_type = ELF32_R_TYPE (irela->r_info);
5930 if ((r_type == (unsigned int) R_ARM_THM_CALL
5931 || r_type == (unsigned int) R_ARM_THM_JUMP24
5932 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5933 && branch_type == ST_BRANCH_TO_ARM)
5934 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5935 else if ((r_type == (unsigned int) R_ARM_CALL
5936 || r_type == (unsigned int) R_ARM_JUMP24)
5937 && branch_type == ST_BRANCH_TO_THUMB)
5938 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5939 else
5940 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5941 }
b715f643
TP		 5942
5943 *new_stub = TRUE;
0955507f 5944 return stub_entry;
b715f643
TP		 5945}
5946
4ba2ef8f
TP		 5947/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5948 gateway veneer to transition from non secure to secure state and create them
5949 accordingly.
5950
5951 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5952 defines the conditions that govern Secure Gateway veneer creation for a
5953 given symbol <SYM> as follows:
5954 - it has function type
5955 - it has non local binding
5956 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5957 same type, binding and value as <SYM> (called normal symbol).
5958 An entry function can handle secure state transition itself in which case
5959 its special symbol would have a different value from the normal symbol.
5960
5961 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5962 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5963 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5964 created.
4ba2ef8f 5965
0955507f 5966 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5967
5968static bfd_boolean
5969cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5970 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5971 int *cmse_stub_created)
4ba2ef8f
TP		 5972{
5973 const struct elf_backend_data *bed;
5974 Elf_Internal_Shdr *symtab_hdr;
5975 unsigned i, j, sym_count, ext_start;
5976 Elf_Internal_Sym *cmse_sym, *local_syms;
5977 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5978 enum arm_st_branch_type branch_type;
5979 char *sym_name, *lsym_name;
5980 bfd_vma sym_value;
5981 asection *section;
0955507f
TP		 5982 struct elf32_arm_stub_hash_entry *stub_entry;
5983 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5984
5985 bed = get_elf_backend_data (input_bfd);
5986 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5987 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5988 ext_start = symtab_hdr->sh_info;
5989 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5990 && out_attr[Tag_CPU_arch_profile].i == 'M');
5991
5992 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5993 if (local_syms == NULL)
5994 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5995 symtab_hdr->sh_info, 0, NULL, NULL,
5996 NULL);
5997 if (symtab_hdr->sh_info && local_syms == NULL)
5998 return FALSE;
5999
6000 /* Scan symbols. */
6001 for (i = 0; i < sym_count; i++)
6002 {
6003 cmse_invalid = FALSE;
6004
6005 if (i < ext_start)
6006 {
6007 cmse_sym = &local_syms[i];
4ba2ef8f
TP		 6008 sym_name = bfd_elf_string_from_elf_section (input_bfd,
6009 symtab_hdr->sh_link,
6010 cmse_sym->st_name);
baf46cd7
AM		 6011 if (!sym_name || !CONST_STRNEQ (sym_name, CMSE_PREFIX))
6012 continue;
6013
4ba2ef8f
TP		 6014 /* Special symbol with local binding. */
6015 cmse_invalid = TRUE;
6016 }
6017 else
6018 {
6019 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
6020 sym_name = (char *) cmse_hash->root.root.root.string;
baf46cd7 6021 if (!CONST_STRNEQ (sym_name, CMSE_PREFIX))
4ba2ef8f
TP		 6022 continue;
6023
6024 /* Special symbol has incorrect binding or type. */
6025 if ((cmse_hash->root.root.type != bfd_link_hash_defined
6026 && cmse_hash->root.root.type != bfd_link_hash_defweak)
6027 || cmse_hash->root.type != STT_FUNC)
6028 cmse_invalid = TRUE;
6029 }
6030
6031 if (!is_v8m)
6032 {
90b6238f
AM		 6033 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
6034 "ARMv8-M architecture or later"),
4eca0228 6035 input_bfd, sym_name);
4ba2ef8f
TP		 6036 is_v8m = TRUE; /* Avoid multiple warning. */
6037 ret = FALSE;
6038 }
6039
6040 if (cmse_invalid)
6041 {
90b6238f
AM		 6042 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
6043 " a global or weak function symbol"),
4eca0228 6044 input_bfd, sym_name);
4ba2ef8f
TP		 6045 ret = FALSE;
6046 if (i < ext_start)
6047 continue;
6048 }
6049
6050 sym_name += strlen (CMSE_PREFIX);
6051 hash = (struct elf32_arm_link_hash_entry *)
6052 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6053
6054 /* No associated normal symbol or it is neither global nor weak. */
6055 if (!hash
6056 || (hash->root.root.type != bfd_link_hash_defined
6057 && hash->root.root.type != bfd_link_hash_defweak)
6058 || hash->root.type != STT_FUNC)
6059 {
6060 /* Initialize here to avoid warning about use of possibly
6061 uninitialized variable. */
6062 j = 0;
6063
6064 if (!hash)
6065 {
6066 /* Searching for a normal symbol with local binding. */
6067 for (; j < ext_start; j++)
6068 {
6069 lsym_name =
6070 bfd_elf_string_from_elf_section (input_bfd,
6071 symtab_hdr->sh_link,
6072 local_syms[j].st_name);
6073 if (!strcmp (sym_name, lsym_name))
6074 break;
6075 }
6076 }
6077
6078 if (hash || j < ext_start)
6079 {
4eca0228 6080 _bfd_error_handler
90b6238f
AM		 6081 (_("%pB: invalid standard symbol `%s'; it must be "
6082 "a global or weak function symbol"),
6083 input_bfd, sym_name);
4ba2ef8f
TP		 6084 }
6085 else
4eca0228 6086 _bfd_error_handler
90b6238f 6087 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 6088 ret = FALSE;
6089 if (!hash)
6090 continue;
6091 }
6092
6093 sym_value = hash->root.root.u.def.value;
6094 section = hash->root.root.u.def.section;
6095
6096 if (cmse_hash->root.root.u.def.section != section)
6097 {
4eca0228 6098 _bfd_error_handler
90b6238f 6099 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 6100 input_bfd, sym_name);
6101 ret = FALSE;
6102 }
6103 if (cmse_hash->root.root.u.def.value != sym_value)
6104 continue; /* Ignore: could be an entry function starting with SG. */
6105
6106 /* If this section is a link-once section that will be discarded, then
6107 don't create any stubs. */
6108 if (section->output_section == NULL)
6109 {
4eca0228 6110 _bfd_error_handler
90b6238f 6111 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 6112 continue;
6113 }
6114
6115 if (hash->root.size == 0)
6116 {
4eca0228 6117 _bfd_error_handler
90b6238f 6118 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 6119 ret = FALSE;
6120 }
6121
6122 if (!ret)
6123 continue;
6124 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 6125 stub_entry
4ba2ef8f
TP		 6126 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6127 NULL, NULL, section, hash, sym_name,
6128 sym_value, branch_type, &new_stub);
6129
0955507f 6130 if (stub_entry == NULL)
4ba2ef8f
TP		 6131 ret = FALSE;
6132 else
6133 {
6134 BFD_ASSERT (new_stub);
0955507f 6135 (*cmse_stub_created)++;
4ba2ef8f
TP		 6136 }
6137 }
6138
6139 if (!symtab_hdr->contents)
6140 free (local_syms);
6141 return ret;
6142}
6143
0955507f
TP		 6144/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6145 code entry function, ie can be called from non secure code without using a
6146 veneer. */
6147
6148static bfd_boolean
6149cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6150{
42484486 6151 bfd_byte contents[4];
0955507f
TP		 6152 uint32_t first_insn;
6153 asection *section;
6154 file_ptr offset;
6155 bfd *abfd;
6156
6157 /* Defined symbol of function type. */
6158 if (hash->root.root.type != bfd_link_hash_defined
6159 && hash->root.root.type != bfd_link_hash_defweak)
6160 return FALSE;
6161 if (hash->root.type != STT_FUNC)
6162 return FALSE;
6163
6164 /* Read first instruction. */
6165 section = hash->root.root.u.def.section;
6166 abfd = section->owner;
6167 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 6168 if (!bfd_get_section_contents (abfd, section, contents, offset,
6169 sizeof (contents)))
0955507f
TP		 6170 return FALSE;
6171
42484486
TP		 6172 first_insn = bfd_get_32 (abfd, contents);
6173
6174 /* Starts by SG instruction. */
0955507f
TP		 6175 return first_insn == 0xe97fe97f;
6176}
6177
6178/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6179 secure gateway veneers (ie. the veneers was not in the input import library)
6180 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6181
6182static bfd_boolean
6183arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6184{
6185 struct elf32_arm_stub_hash_entry *stub_entry;
6186 struct bfd_link_info *info;
6187
6188 /* Massage our args to the form they really have. */
6189 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6190 info = (struct bfd_link_info *) gen_info;
6191
6192 if (info->out_implib_bfd)
6193 return TRUE;
6194
6195 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6196 return TRUE;
6197
6198 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 6199 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 6200
6201 return TRUE;
6202}
6203
6204/* Set offset of each secure gateway veneers so that its address remain
6205 identical to the one in the input import library referred by
6206 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6207 (present in input import library but absent from the executable being
6208 linked) or if new veneers appeared and there is no output import library
6209 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6210 number of secure gateway veneers found in the input import library.
6211
6212 The function returns whether an error occurred. If no error occurred,
6213 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6214 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6215 veneer observed set for new veneers to be layed out after. */
6216
6217static bfd_boolean
6218set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6219 struct elf32_arm_link_hash_table *htab,
6220 int *cmse_stub_created)
6221{
6222 long symsize;
6223 char *sym_name;
6224 flagword flags;
6225 long i, symcount;
6226 bfd *in_implib_bfd;
6227 asection *stub_out_sec;
6228 bfd_boolean ret = TRUE;
6229 Elf_Internal_Sym *intsym;
6230 const char *out_sec_name;
6231 bfd_size_type cmse_stub_size;
6232 asymbol **sympp = NULL, *sym;
6233 struct elf32_arm_link_hash_entry *hash;
6234 const insn_sequence *cmse_stub_template;
6235 struct elf32_arm_stub_hash_entry *stub_entry;
6236 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6237 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6238 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6239
6240 /* No input secure gateway import library. */
6241 if (!htab->in_implib_bfd)
6242 return TRUE;
6243
6244 in_implib_bfd = htab->in_implib_bfd;
6245 if (!htab->cmse_implib)
6246 {
871b3ab2 6247 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 6248 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 6249 return FALSE;
6250 }
6251
6252 /* Get symbol table size. */
6253 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6254 if (symsize < 0)
6255 return FALSE;
6256
6257 /* Read in the input secure gateway import library's symbol table. */
9a733151
AM		 6258 sympp = (asymbol **) bfd_malloc (symsize);
6259 if (sympp == NULL)
6260 return FALSE;
6261
0955507f
TP		 6262 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6263 if (symcount < 0)
6264 {
6265 ret = FALSE;
6266 goto free_sym_buf;
6267 }
6268
6269 htab->new_cmse_stub_offset = 0;
6270 cmse_stub_size =
6271 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6272 &cmse_stub_template,
6273 &cmse_stub_template_size);
6274 out_sec_name =
6275 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6276 stub_out_sec =
6277 bfd_get_section_by_name (htab->obfd, out_sec_name);
6278 if (stub_out_sec != NULL)
6279 cmse_stub_sec_vma = stub_out_sec->vma;
6280
6281 /* Set addresses of veneers mentionned in input secure gateway import
6282 library's symbol table. */
6283 for (i = 0; i < symcount; i++)
6284 {
6285 sym = sympp[i];
6286 flags = sym->flags;
6287 sym_name = (char *) bfd_asymbol_name (sym);
6288 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6289
6290 if (sym->section != bfd_abs_section_ptr
6291 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6292 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6293 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6294 != ST_BRANCH_TO_THUMB))
6295 {
90b6238f
AM		 6296 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6297 "symbol should be absolute, global and "
6298 "refer to Thumb functions"),
4eca0228 6299 in_implib_bfd, sym_name);
0955507f
TP		 6300 ret = FALSE;
6301 continue;
6302 }
6303
6304 veneer_value = bfd_asymbol_value (sym);
6305 stub_offset = veneer_value - cmse_stub_sec_vma;
6306 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6307 FALSE, FALSE);
6308 hash = (struct elf32_arm_link_hash_entry *)
6309 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6310
6311 /* Stub entry should have been created by cmse_scan or the symbol be of
6312 a secure function callable from non secure code. */
6313 if (!stub_entry && !hash)
6314 {
6315 bfd_boolean new_stub;
6316
4eca0228 6317 _bfd_error_handler
90b6238f 6318 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6319 hash = (struct elf32_arm_link_hash_entry *)
6320 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6321 stub_entry
6322 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6323 NULL, NULL, bfd_abs_section_ptr, hash,
6324 sym_name, veneer_value,
6325 ST_BRANCH_TO_THUMB, &new_stub);
6326 if (stub_entry == NULL)
6327 ret = FALSE;
6328 else
6329 {
6330 BFD_ASSERT (new_stub);
6331 new_cmse_stubs_created++;
6332 (*cmse_stub_created)++;
6333 }
6334 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6335 stub_entry->stub_offset = stub_offset;
6336 }
6337 /* Symbol found is not callable from non secure code. */
6338 else if (!stub_entry)
6339 {
6340 if (!cmse_entry_fct_p (hash))
6341 {
90b6238f 6342 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6343 sym_name);
0955507f
TP		 6344 ret = FALSE;
6345 }
6346 continue;
6347 }
6348 else
6349 {
6350 /* Only stubs for SG veneers should have been created. */
6351 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6352
6353 /* Check visibility hasn't changed. */
6354 if (!!(flags & BSF_GLOBAL)
6355 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6356 _bfd_error_handler
90b6238f 6357 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6358 sym_name);
6359
6360 stub_entry->stub_offset = stub_offset;
6361 }
6362
6363 /* Size should match that of a SG veneer. */
6364 if (intsym->st_size != cmse_stub_size)
6365 {
90b6238f 6366 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6367 in_implib_bfd, sym_name);
0955507f
TP		 6368 ret = FALSE;
6369 }
6370
6371 /* Previous veneer address is before current SG veneer section. */
6372 if (veneer_value < cmse_stub_sec_vma)
6373 {
6374 /* Avoid offset underflow. */
6375 if (stub_entry)
6376 stub_entry->stub_offset = 0;
6377 stub_offset = 0;
6378 ret = FALSE;
6379 }
6380
6381 /* Complain if stub offset not a multiple of stub size. */
6382 if (stub_offset % cmse_stub_size)
6383 {
4eca0228 6384 _bfd_error_handler
90b6238f
AM		 6385 (_("offset of veneer for entry function `%s' not a multiple of "
6386 "its size"), sym_name);
0955507f
TP		 6387 ret = FALSE;
6388 }
6389
6390 if (!ret)
6391 continue;
6392
6393 new_cmse_stubs_created--;
6394 if (veneer_value < cmse_stub_array_start)
6395 cmse_stub_array_start = veneer_value;
6396 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6397 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6398 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6399 }
6400
6401 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6402 {
6403 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6404 _bfd_error_handler
0955507f
TP		 6405 (_("new entry function(s) introduced but no output import library "
6406 "specified:"));
6407 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6408 }
6409
6410 if (cmse_stub_array_start != cmse_stub_sec_vma)
6411 {
4eca0228 6412 _bfd_error_handler
90b6238f 6413 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6414 out_sec_name);
6415 ret = FALSE;
6416 }
6417
6418free_sym_buf:
6419 free (sympp);
6420 return ret;
6421}
6422
906e58ca
NC		 6423/* Determine and set the size of the stub section for a final link.
6424
6425 The basic idea here is to examine all the relocations looking for
6426 PC-relative calls to a target that is unreachable with a "bl"
6427 instruction. */
6428
6429bfd_boolean
6430elf32_arm_size_stubs (bfd *output_bfd,
6431 bfd *stub_bfd,
6432 struct bfd_link_info *info,
6433 bfd_signed_vma group_size,
7a89b94e 6434 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6435 asection *,
7a89b94e 6436 unsigned int),
906e58ca
NC		 6437 void (*layout_sections_again) (void))
6438{
0955507f 6439 bfd_boolean ret = TRUE;
4ba2ef8f 6440 obj_attribute *out_attr;
0955507f 6441 int cmse_stub_created = 0;
906e58ca 6442 bfd_size_type stub_group_size;
4ba2ef8f 6443 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6444 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6445 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6446 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6447 struct a8_erratum_reloc *a8_relocs = NULL;
6448 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6449
4dfe6ac6
NC		 6450 if (htab == NULL)
6451 return FALSE;
6452
48229727
JB		 6453 if (htab->fix_cortex_a8)
6454 {
21d799b5 6455 a8_fixes = (struct a8_erratum_fix *)
99059e56 6456 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6457 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6458 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6459 }
906e58ca
NC		 6460
6461 /* Propagate mach to stub bfd, because it may not have been
6462 finalized when we created stub_bfd. */
6463 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6464 bfd_get_mach (output_bfd));
6465
6466 /* Stash our params away. */
6467 htab->stub_bfd = stub_bfd;
6468 htab->add_stub_section = add_stub_section;
6469 htab->layout_sections_again = layout_sections_again;
07d72278 6470 stubs_always_after_branch = group_size < 0;
48229727 6471
4ba2ef8f
TP		 6472 out_attr = elf_known_obj_attributes_proc (output_bfd);
6473 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6474
48229727
JB		 6475 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6476 as the first half of a 32-bit branch straddling two 4K pages. This is a
6477 crude way of enforcing that. */
6478 if (htab->fix_cortex_a8)
6479 stubs_always_after_branch = 1;
6480
906e58ca
NC		 6481 if (group_size < 0)
6482 stub_group_size = -group_size;
6483 else
6484 stub_group_size = group_size;
6485
6486 if (stub_group_size == 1)
6487 {
6488 /* Default values. */
6489 /* Thumb branch range is +-4MB has to be used as the default
6490 maximum size (a given section can contain both ARM and Thumb
6491 code, so the worst case has to be taken into account).
6492
6493 This value is 24K less than that, which allows for 2025
6494 12-byte stubs. If we exceed that, then we will fail to link.
6495 The user will have to relink with an explicit group size
6496 option. */
6497 stub_group_size = 4170000;
6498 }
6499
07d72278 6500 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6501
3ae046cc
NS		 6502 /* If we're applying the cortex A8 fix, we need to determine the
6503 program header size now, because we cannot change it later --
6504 that could alter section placements. Notice the A8 erratum fix
6505 ends up requiring the section addresses to remain unchanged
6506 modulo the page size. That's something we cannot represent
6507 inside BFD, and we don't want to force the section alignment to
6508 be the page size. */
6509 if (htab->fix_cortex_a8)
6510 (*htab->layout_sections_again) ();
6511
906e58ca
NC		 6512 while (1)
6513 {
6514 bfd *input_bfd;
6515 unsigned int bfd_indx;
6516 asection *stub_sec;
d7c5bd02 6517 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6518 bfd_boolean stub_changed = FALSE;
6519 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6520
48229727 6521 num_a8_fixes = 0;
906e58ca
NC		 6522 for (input_bfd = info->input_bfds, bfd_indx = 0;
6523 input_bfd != NULL;
c72f2fb2 6524 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6525 {
6526 Elf_Internal_Shdr *symtab_hdr;
6527 asection *section;
6528 Elf_Internal_Sym *local_syms = NULL;
6529
73d5efd7
AM		 6530 if (!is_arm_elf (input_bfd))
6531 continue;
6532 if ((input_bfd->flags & DYNAMIC) != 0
6533 && (elf_sym_hashes (input_bfd) == NULL
6534 || (elf_dyn_lib_class (input_bfd) & DYN_AS_NEEDED) != 0))
99059e56 6535 continue;
adbcc655 6536
48229727
JB		 6537 num_a8_relocs = 0;
6538
906e58ca
NC		 6539 /* We'll need the symbol table in a second. */
6540 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6541 if (symtab_hdr->sh_info == 0)
6542 continue;
6543
4ba2ef8f
TP		 6544 /* Limit scan of symbols to object file whose profile is
6545 Microcontroller to not hinder performance in the general case. */
6546 if (m_profile && first_veneer_scan)
6547 {
6548 struct elf_link_hash_entry **sym_hashes;
6549
6550 sym_hashes = elf_sym_hashes (input_bfd);
6551 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6552 &cmse_stub_created))
4ba2ef8f 6553 goto error_ret_free_local;
0955507f
TP		 6554
6555 if (cmse_stub_created != 0)
6556 stub_changed = TRUE;
4ba2ef8f
TP		 6557 }
6558
906e58ca
NC		 6559 /* Walk over each section attached to the input bfd. */
6560 for (section = input_bfd->sections;
6561 section != NULL;
6562 section = section->next)
6563 {
6564 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6565
6566 /* If there aren't any relocs, then there's nothing more
6567 to do. */
6568 if ((section->flags & SEC_RELOC) == 0
6569 || section->reloc_count == 0
6570 || (section->flags & SEC_CODE) == 0)
6571 continue;
6572
6573 /* If this section is a link-once section that will be
6574 discarded, then don't create any stubs. */
6575 if (section->output_section == NULL
6576 || section->output_section->owner != output_bfd)
6577 continue;
6578
6579 /* Get the relocs. */
6580 internal_relocs
6581 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6582 NULL, info->keep_memory);
6583 if (internal_relocs == NULL)
6584 goto error_ret_free_local;
6585
6586 /* Now examine each relocation. */
6587 irela = internal_relocs;
6588 irelaend = irela + section->reloc_count;
6589 for (; irela < irelaend; irela++)
6590 {
6591 unsigned int r_type, r_indx;
906e58ca
NC		 6592 asection *sym_sec;
6593 bfd_vma sym_value;
6594 bfd_vma destination;
6595 struct elf32_arm_link_hash_entry *hash;
7413f23f 6596 const char *sym_name;
34e77a92 6597 unsigned char st_type;
35fc36a8 6598 enum arm_st_branch_type branch_type;
48229727 6599 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6600
6601 r_type = ELF32_R_TYPE (irela->r_info);
6602 r_indx = ELF32_R_SYM (irela->r_info);
6603
6604 if (r_type >= (unsigned int) R_ARM_max)
6605 {
6606 bfd_set_error (bfd_error_bad_value);
6607 error_ret_free_internal:
6608 if (elf_section_data (section)->relocs == NULL)
6609 free (internal_relocs);
15dd01b1
TP		 6610 /* Fall through. */
6611 error_ret_free_local:
6612 if (local_syms != NULL
6613 && (symtab_hdr->contents
6614 != (unsigned char *) local_syms))
6615 free (local_syms);
6616 return FALSE;
906e58ca 6617 }
b38cadfb 6618
0855e32b
NS		 6619 hash = NULL;
6620 if (r_indx >= symtab_hdr->sh_info)
6621 hash = elf32_arm_hash_entry
6622 (elf_sym_hashes (input_bfd)
6623 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6624
0855e32b
NS		 6625 /* Only look for stubs on branch instructions, or
6626 non-relaxed TLSCALL */
906e58ca 6627 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6628 && (r_type != (unsigned int) R_ARM_THM_CALL)
6629 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6630 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6631 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6632 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6633 && (r_type != (unsigned int) R_ARM_PLT32)
6634 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6635 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6636 && r_type == elf32_arm_tls_transition
6637 (info, r_type, &hash->root)
6638 && ((hash ? hash->tls_type
6639 : (elf32_arm_local_got_tls_type
6640 (input_bfd)[r_indx]))
6641 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6642 continue;
6643
6644 /* Now determine the call target, its name, value,
6645 section. */
6646 sym_sec = NULL;
6647 sym_value = 0;
6648 destination = 0;
7413f23f 6649 sym_name = NULL;
b38cadfb 6650
0855e32b
NS		 6651 if (r_type == (unsigned int) R_ARM_TLS_CALL
6652 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6653 {
6654 /* A non-relaxed TLS call. The target is the
6655 plt-resident trampoline and nothing to do
6656 with the symbol. */
6657 BFD_ASSERT (htab->tls_trampoline > 0);
6658 sym_sec = htab->root.splt;
6659 sym_value = htab->tls_trampoline;
6660 hash = 0;
34e77a92 6661 st_type = STT_FUNC;
35fc36a8 6662 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6663 }
6664 else if (!hash)
906e58ca
NC		 6665 {
6666 /* It's a local symbol. */
6667 Elf_Internal_Sym *sym;
906e58ca
NC		 6668
6669 if (local_syms == NULL)
6670 {
6671 local_syms
6672 = (Elf_Internal_Sym *) symtab_hdr->contents;
6673 if (local_syms == NULL)
6674 local_syms
6675 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6676 symtab_hdr->sh_info, 0,
6677 NULL, NULL, NULL);
6678 if (local_syms == NULL)
6679 goto error_ret_free_internal;
6680 }
6681
6682 sym = local_syms + r_indx;
f6d250ce
TS		 6683 if (sym->st_shndx == SHN_UNDEF)
6684 sym_sec = bfd_und_section_ptr;
6685 else if (sym->st_shndx == SHN_ABS)
6686 sym_sec = bfd_abs_section_ptr;
6687 else if (sym->st_shndx == SHN_COMMON)
6688 sym_sec = bfd_com_section_ptr;
6689 else
6690 sym_sec =
6691 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6692
ffcb4889
NS		 6693 if (!sym_sec)
6694 /* This is an undefined symbol. It can never
6a631e86 6695 be resolved. */
ffcb4889 6696 continue;
fe33d2fa 6697
906e58ca
NC		 6698 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6699 sym_value = sym->st_value;
6700 destination = (sym_value + irela->r_addend
6701 + sym_sec->output_offset
6702 + sym_sec->output_section->vma);
34e77a92 6703 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6704 branch_type =
6705 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6706 sym_name
6707 = bfd_elf_string_from_elf_section (input_bfd,
6708 symtab_hdr->sh_link,
6709 sym->st_name);
906e58ca
NC		 6710 }
6711 else
6712 {
6713 /* It's an external symbol. */
906e58ca
NC		 6714 while (hash->root.root.type == bfd_link_hash_indirect
6715 || hash->root.root.type == bfd_link_hash_warning)
6716 hash = ((struct elf32_arm_link_hash_entry *)
6717 hash->root.root.u.i.link);
6718
6719 if (hash->root.root.type == bfd_link_hash_defined
6720 || hash->root.root.type == bfd_link_hash_defweak)
6721 {
6722 sym_sec = hash->root.root.u.def.section;
6723 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6724
6725 struct elf32_arm_link_hash_table *globals =
6726 elf32_arm_hash_table (info);
6727
6728 /* For a destination in a shared library,
6729 use the PLT stub as target address to
6730 decide whether a branch stub is
6731 needed. */
4dfe6ac6 6732 if (globals != NULL
362d30a1 6733 && globals->root.splt != NULL
4dfe6ac6 6734 && hash != NULL
022f8312
CL		 6735 && hash->root.plt.offset != (bfd_vma) -1)
6736 {
362d30a1 6737 sym_sec = globals->root.splt;
022f8312
CL		 6738 sym_value = hash->root.plt.offset;
6739 if (sym_sec->output_section != NULL)
6740 destination = (sym_value
6741 + sym_sec->output_offset
6742 + sym_sec->output_section->vma);
6743 }
6744 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6745 destination = (sym_value + irela->r_addend
6746 + sym_sec->output_offset
6747 + sym_sec->output_section->vma);
6748 }
69c5861e
CL		 6749 else if ((hash->root.root.type == bfd_link_hash_undefined)
6750 || (hash->root.root.type == bfd_link_hash_undefweak))
6751 {
6752 /* For a shared library, use the PLT stub as
6753 target address to decide whether a long
6754 branch stub is needed.
6755 For absolute code, they cannot be handled. */
6756 struct elf32_arm_link_hash_table *globals =
6757 elf32_arm_hash_table (info);
6758
4dfe6ac6 6759 if (globals != NULL
362d30a1 6760 && globals->root.splt != NULL
4dfe6ac6 6761 && hash != NULL
69c5861e
CL		 6762 && hash->root.plt.offset != (bfd_vma) -1)
6763 {
362d30a1 6764 sym_sec = globals->root.splt;
69c5861e
CL		 6765 sym_value = hash->root.plt.offset;
6766 if (sym_sec->output_section != NULL)
6767 destination = (sym_value
6768 + sym_sec->output_offset
6769 + sym_sec->output_section->vma);
6770 }
6771 else
6772 continue;
6773 }
906e58ca
NC		 6774 else
6775 {
6776 bfd_set_error (bfd_error_bad_value);
6777 goto error_ret_free_internal;
6778 }
34e77a92 6779 st_type = hash->root.type;
39d911fc
TP		 6780 branch_type =
6781 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6782 sym_name = hash->root.root.root.string;
906e58ca
NC		 6783 }
6784
48229727 6785 do
7413f23f 6786 {
b715f643 6787 bfd_boolean new_stub;
0955507f 6788 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6789
48229727
JB		 6790 /* Determine what (if any) linker stub is needed. */
6791 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6792 st_type, &branch_type,
6793 hash, destination, sym_sec,
48229727
JB		 6794 input_bfd, sym_name);
6795 if (stub_type == arm_stub_none)
6796 break;
6797
48229727
JB		 6798 /* We've either created a stub for this reloc already,
6799 or we are about to. */
0955507f 6800 stub_entry =
b715f643
TP		 6801 elf32_arm_create_stub (htab, stub_type, section, irela,
6802 sym_sec, hash,
6803 (char *) sym_name, sym_value,
6804 branch_type, &new_stub);
7413f23f 6805
0955507f 6806 created_stub = stub_entry != NULL;
b715f643
TP		 6807 if (!created_stub)
6808 goto error_ret_free_internal;
6809 else if (!new_stub)
6810 break;
99059e56 6811 else
b715f643 6812 stub_changed = TRUE;
99059e56
RM		 6813 }
6814 while (0);
6815
6816 /* Look for relocations which might trigger Cortex-A8
6817 erratum. */
6818 if (htab->fix_cortex_a8
6819 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6820 || r_type == (unsigned int) R_ARM_THM_JUMP19
6821 || r_type == (unsigned int) R_ARM_THM_CALL
6822 || r_type == (unsigned int) R_ARM_THM_XPC22))
6823 {
6824 bfd_vma from = section->output_section->vma
6825 + section->output_offset
6826 + irela->r_offset;
6827
6828 if ((from & 0xfff) == 0xffe)
6829 {
6830 /* Found a candidate. Note we haven't checked the
6831 destination is within 4K here: if we do so (and
6832 don't create an entry in a8_relocs) we can't tell
6833 that a branch should have been relocated when
6834 scanning later. */
6835 if (num_a8_relocs == a8_reloc_table_size)
6836 {
6837 a8_reloc_table_size *= 2;
6838 a8_relocs = (struct a8_erratum_reloc *)
6839 bfd_realloc (a8_relocs,
6840 sizeof (struct a8_erratum_reloc)
6841 * a8_reloc_table_size);
6842 }
6843
6844 a8_relocs[num_a8_relocs].from = from;
6845 a8_relocs[num_a8_relocs].destination = destination;
6846 a8_relocs[num_a8_relocs].r_type = r_type;
6847 a8_relocs[num_a8_relocs].branch_type = branch_type;
6848 a8_relocs[num_a8_relocs].sym_name = sym_name;
6849 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6850 a8_relocs[num_a8_relocs].hash = hash;
6851
6852 num_a8_relocs++;
6853 }
6854 }
906e58ca
NC		 6855 }
6856
99059e56
RM		 6857 /* We're done with the internal relocs, free them. */
6858 if (elf_section_data (section)->relocs == NULL)
6859 free (internal_relocs);
6860 }
48229727 6861
99059e56 6862 if (htab->fix_cortex_a8)
48229727 6863 {
99059e56
RM		 6864 /* Sort relocs which might apply to Cortex-A8 erratum. */
6865 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6866 sizeof (struct a8_erratum_reloc),
99059e56 6867 &a8_reloc_compare);
48229727 6868
99059e56
RM		 6869 /* Scan for branches which might trigger Cortex-A8 erratum. */
6870 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6871 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6872 a8_relocs, num_a8_relocs,
6873 prev_num_a8_fixes, &stub_changed)
6874 != 0)
48229727 6875 goto error_ret_free_local;
5e681ec4 6876 }
7f991970
AM		 6877
6878 if (local_syms != NULL
6879 && symtab_hdr->contents != (unsigned char *) local_syms)
6880 {
6881 if (!info->keep_memory)
6882 free (local_syms);
6883 else
6884 symtab_hdr->contents = (unsigned char *) local_syms;
6885 }
5e681ec4
PB		 6886 }
6887
0955507f
TP		 6888 if (first_veneer_scan
6889 && !set_cmse_veneer_addr_from_implib (info, htab,
6890 &cmse_stub_created))
6891 ret = FALSE;
6892
eb7c4339 6893 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6894 stub_changed = TRUE;
48229727 6895
906e58ca
NC		 6896 if (!stub_changed)
6897 break;
5e681ec4 6898
906e58ca
NC		 6899 /* OK, we've added some stubs. Find out the new size of the
6900 stub sections. */
6901 for (stub_sec = htab->stub_bfd->sections;
6902 stub_sec != NULL;
6903 stub_sec = stub_sec->next)
3e6b1042
DJ		 6904 {
6905 /* Ignore non-stub sections. */
6906 if (!strstr (stub_sec->name, STUB_SUFFIX))
6907 continue;
6908
6909 stub_sec->size = 0;
6910 }
b34b2d70 6911
0955507f
TP		 6912 /* Add new SG veneers after those already in the input import
6913 library. */
6914 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6915 stub_type++)
6916 {
6917 bfd_vma *start_offset_p;
6918 asection **stub_sec_p;
6919
6920 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6921 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6922 if (start_offset_p == NULL)
6923 continue;
6924
6925 BFD_ASSERT (stub_sec_p != NULL);
6926 if (*stub_sec_p != NULL)
6927 (*stub_sec_p)->size = *start_offset_p;
6928 }
6929
d7c5bd02 6930 /* Compute stub section size, considering padding. */
906e58ca 6931 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6932 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6933 stub_type++)
6934 {
6935 int size, padding;
6936 asection **stub_sec_p;
6937
6938 padding = arm_dedicated_stub_section_padding (stub_type);
6939 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6940 /* Skip if no stub input section or no stub section padding
6941 required. */
6942 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6943 continue;
6944 /* Stub section padding required but no dedicated section. */
6945 BFD_ASSERT (stub_sec_p);
6946
6947 size = (*stub_sec_p)->size;
6948 size = (size + padding - 1) & ~(padding - 1);
6949 (*stub_sec_p)->size = size;
6950 }
906e58ca 6951
48229727
JB		 6952 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6953 if (htab->fix_cortex_a8)
99059e56
RM		 6954 for (i = 0; i < num_a8_fixes; i++)
6955 {
48229727 6956 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6957 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6958
6959 if (stub_sec == NULL)
7f991970 6960 return FALSE;
48229727 6961
99059e56
RM		 6962 stub_sec->size
6963 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6964 NULL);
6965 }
48229727
JB		 6966
6967
906e58ca
NC		 6968 /* Ask the linker to do its stuff. */
6969 (*htab->layout_sections_again) ();
4ba2ef8f 6970 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6971 }
6972
48229727
JB		 6973 /* Add stubs for Cortex-A8 erratum fixes now. */
6974 if (htab->fix_cortex_a8)
6975 {
6976 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6977 {
6978 struct elf32_arm_stub_hash_entry *stub_entry;
6979 char *stub_name = a8_fixes[i].stub_name;
6980 asection *section = a8_fixes[i].section;
6981 unsigned int section_id = a8_fixes[i].section->id;
6982 asection *link_sec = htab->stub_group[section_id].link_sec;
6983 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6984 const insn_sequence *template_sequence;
6985 int template_size, size = 0;
6986
6987 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6988 TRUE, FALSE);
6989 if (stub_entry == NULL)
6990 {
871b3ab2 6991 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6992 section->owner, stub_name);
99059e56
RM		 6993 return FALSE;
6994 }
6995
6996 stub_entry->stub_sec = stub_sec;
0955507f 6997 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6998 stub_entry->id_sec = link_sec;
6999 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 7000 stub_entry->source_value = a8_fixes[i].offset;
99059e56 7001 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 7002 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 7003 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 7004 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 7005
99059e56
RM		 7006 size = find_stub_size_and_template (a8_fixes[i].stub_type,
7007 &template_sequence,
7008 &template_size);
48229727 7009
99059e56
RM		 7010 stub_entry->stub_size = size;
7011 stub_entry->stub_template = template_sequence;
7012 stub_entry->stub_template_size = template_size;
7013 }
48229727
JB		 7014
7015 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 7016 elf32_arm_write_section(). */
48229727
JB		 7017 htab->a8_erratum_fixes = a8_fixes;
7018 htab->num_a8_erratum_fixes = num_a8_fixes;
7019 }
7020 else
7021 {
7022 htab->a8_erratum_fixes = NULL;
7023 htab->num_a8_erratum_fixes = 0;
7024 }
0955507f 7025 return ret;
5e681ec4
PB		 7026}
7027
906e58ca
NC		 7028/* Build all the stubs associated with the current output file. The
7029 stubs are kept in a hash table attached to the main linker hash
7030 table. We also set up the .plt entries for statically linked PIC
7031 functions here. This function is called via arm_elf_finish in the
7032 linker. */
252b5132 7033
906e58ca
NC		 7034bfd_boolean
7035elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 7036{
906e58ca
NC		 7037 asection *stub_sec;
7038 struct bfd_hash_table *table;
0955507f 7039 enum elf32_arm_stub_type stub_type;
906e58ca 7040 struct elf32_arm_link_hash_table *htab;
252b5132 7041
906e58ca 7042 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 7043 if (htab == NULL)
7044 return FALSE;
252b5132 7045
906e58ca
NC		 7046 for (stub_sec = htab->stub_bfd->sections;
7047 stub_sec != NULL;
7048 stub_sec = stub_sec->next)
252b5132 7049 {
906e58ca
NC		 7050 bfd_size_type size;
7051
8029a119 7052 /* Ignore non-stub sections. */
906e58ca
NC		 7053 if (!strstr (stub_sec->name, STUB_SUFFIX))
7054 continue;
7055
d7c5bd02 7056 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 7057 must at least be done for stub section requiring padding and for SG
7058 veneers to ensure that a non secure code branching to a removed SG
7059 veneer causes an error. */
906e58ca 7060 size = stub_sec->size;
21d799b5 7061 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 7062 if (stub_sec->contents == NULL && size != 0)
7063 return FALSE;
0955507f 7064
906e58ca 7065 stub_sec->size = 0;
252b5132
RH		 7066 }
7067
0955507f
TP		 7068 /* Add new SG veneers after those already in the input import library. */
7069 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7070 {
7071 bfd_vma *start_offset_p;
7072 asection **stub_sec_p;
7073
7074 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
7075 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
7076 if (start_offset_p == NULL)
7077 continue;
7078
7079 BFD_ASSERT (stub_sec_p != NULL);
7080 if (*stub_sec_p != NULL)
7081 (*stub_sec_p)->size = *start_offset_p;
7082 }
7083
906e58ca
NC		 7084 /* Build the stubs as directed by the stub hash table. */
7085 table = &htab->stub_hash_table;
7086 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 7087 if (htab->fix_cortex_a8)
7088 {
7089 /* Place the cortex a8 stubs last. */
7090 htab->fix_cortex_a8 = -1;
7091 bfd_hash_traverse (table, arm_build_one_stub, info);
7092 }
252b5132 7093
906e58ca 7094 return TRUE;
252b5132
RH		 7095}
7096
9b485d32
NC		 7097/* Locate the Thumb encoded calling stub for NAME. */
7098
252b5132 7099static struct elf_link_hash_entry *
57e8b36a
NC		 7100find_thumb_glue (struct bfd_link_info *link_info,
7101 const char *name,
f2a9dd69 7102 char **error_message)
252b5132
RH		 7103{
7104 char *tmp_name;
7105 struct elf_link_hash_entry *hash;
7106 struct elf32_arm_link_hash_table *hash_table;
7107
7108 /* We need a pointer to the armelf specific hash table. */
7109 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7110 if (hash_table == NULL)
7111 return NULL;
252b5132 7112
21d799b5 7113 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7114 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7115
7116 BFD_ASSERT (tmp_name);
7117
7118 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7119
7120 hash = elf_link_hash_lookup
b34976b6 7121 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7122
b1657152 7123 if (hash == NULL
90b6238f
AM		 7124 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7125 "Thumb", tmp_name, name) == -1)
b1657152 7126 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7127
7128 free (tmp_name);
7129
7130 return hash;
7131}
7132
9b485d32
NC		 7133/* Locate the ARM encoded calling stub for NAME. */
7134
252b5132 7135static struct elf_link_hash_entry *
57e8b36a
NC		 7136find_arm_glue (struct bfd_link_info *link_info,
7137 const char *name,
f2a9dd69 7138 char **error_message)
252b5132
RH		 7139{
7140 char *tmp_name;
7141 struct elf_link_hash_entry *myh;
7142 struct elf32_arm_link_hash_table *hash_table;
7143
7144 /* We need a pointer to the elfarm specific hash table. */
7145 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7146 if (hash_table == NULL)
7147 return NULL;
252b5132 7148
21d799b5 7149 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7150 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7151
7152 BFD_ASSERT (tmp_name);
7153
7154 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7155
7156 myh = elf_link_hash_lookup
b34976b6 7157 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7158
b1657152 7159 if (myh == NULL
90b6238f
AM		 7160 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7161 "ARM", tmp_name, name) == -1)
b1657152 7162 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7163
7164 free (tmp_name);
7165
7166 return myh;
7167}
7168
8f6277f5 7169/* ARM->Thumb glue (static images):
252b5132
RH		 7170
7171 .arm
7172 __func_from_arm:
7173 ldr r12, __func_addr
7174 bx r12
7175 __func_addr:
906e58ca 7176 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 7177
26079076
PB		 7178 (v5t static images)
7179 .arm
7180 __func_from_arm:
7181 ldr pc, __func_addr
7182 __func_addr:
906e58ca 7183 .word func @ behave as if you saw a ARM_32 reloc.
26079076 7184
8f6277f5
PB		 7185 (relocatable images)
7186 .arm
7187 __func_from_arm:
7188 ldr r12, __func_offset
7189 add r12, r12, pc
7190 bx r12
7191 __func_offset:
8029a119 7192 .word func - . */
8f6277f5
PB		 7193
7194#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 7195static const insn32 a2t1_ldr_insn = 0xe59fc000;
7196static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7197static const insn32 a2t3_func_addr_insn = 0x00000001;
7198
26079076
PB		 7199#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7200static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7201static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7202
8f6277f5
PB		 7203#define ARM2THUMB_PIC_GLUE_SIZE 16
7204static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7205static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7206static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7207
07d6d2b8 7208/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 7209
07d6d2b8
AM		 7210 .thumb .thumb
7211 .align 2 .align 2
7212 __func_from_thumb: __func_from_thumb:
7213 bx pc push {r6, lr}
7214 nop ldr r6, __func_addr
7215 .arm mov lr, pc
7216 b func bx r6
99059e56
RM		 7217 .arm
7218 ;; back_to_thumb
7219 ldmia r13! {r6, lr}
7220 bx lr
7221 __func_addr:
07d6d2b8 7222 .word func */
252b5132
RH		 7223
7224#define THUMB2ARM_GLUE_SIZE 8
7225static const insn16 t2a1_bx_pc_insn = 0x4778;
7226static const insn16 t2a2_noop_insn = 0x46c0;
7227static const insn32 t2a3_b_insn = 0xea000000;
7228
c7b8f16e 7229#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 7230#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7231#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 7232
845b51d6
PB		 7233#define ARM_BX_VENEER_SIZE 12
7234static const insn32 armbx1_tst_insn = 0xe3100001;
7235static const insn32 armbx2_moveq_insn = 0x01a0f000;
7236static const insn32 armbx3_bx_insn = 0xe12fff10;
7237
7e392df6 7238#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 7239static void
7240arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 7241{
7242 asection * s;
8029a119 7243 bfd_byte * contents;
252b5132 7244
8029a119 7245 if (size == 0)
3e6b1042
DJ		 7246 {
7247 /* Do not include empty glue sections in the output. */
7248 if (abfd != NULL)
7249 {
3d4d4302 7250 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 7251 if (s != NULL)
7252 s->flags |= SEC_EXCLUDE;
7253 }
7254 return;
7255 }
252b5132 7256
8029a119 7257 BFD_ASSERT (abfd != NULL);
252b5132 7258
3d4d4302 7259 s = bfd_get_linker_section (abfd, name);
8029a119 7260 BFD_ASSERT (s != NULL);
252b5132 7261
b0f4fbf8 7262 contents = (bfd_byte *) bfd_zalloc (abfd, size);
252b5132 7263
8029a119
NC		 7264 BFD_ASSERT (s->size == size);
7265 s->contents = contents;
7266}
906e58ca 7267
8029a119
NC		 7268bfd_boolean
7269bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7270{
7271 struct elf32_arm_link_hash_table * globals;
906e58ca 7272
8029a119
NC		 7273 globals = elf32_arm_hash_table (info);
7274 BFD_ASSERT (globals != NULL);
906e58ca 7275
8029a119
NC		 7276 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7277 globals->arm_glue_size,
7278 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 7279
8029a119
NC		 7280 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7281 globals->thumb_glue_size,
7282 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 7283
8029a119
NC		 7284 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7285 globals->vfp11_erratum_glue_size,
7286 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 7287
a504d23a
LA		 7288 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7289 globals->stm32l4xx_erratum_glue_size,
7290 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7291
8029a119
NC		 7292 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7293 globals->bx_glue_size,
845b51d6
PB		 7294 ARM_BX_GLUE_SECTION_NAME);
7295
b34976b6 7296 return TRUE;
252b5132
RH		 7297}
7298
a4fd1a8e 7299/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7300 returns the symbol identifying the stub. */
7301
a4fd1a8e 7302static struct elf_link_hash_entry *
57e8b36a
NC		 7303record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7304 struct elf_link_hash_entry * h)
252b5132
RH		 7305{
7306 const char * name = h->root.root.string;
63b0f745 7307 asection * s;
252b5132
RH		 7308 char * tmp_name;
7309 struct elf_link_hash_entry * myh;
14a793b2 7310 struct bfd_link_hash_entry * bh;
252b5132 7311 struct elf32_arm_link_hash_table * globals;
dc810e39 7312 bfd_vma val;
2f475487 7313 bfd_size_type size;
252b5132
RH		 7314
7315 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7316 BFD_ASSERT (globals != NULL);
7317 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7318
3d4d4302 7319 s = bfd_get_linker_section
252b5132
RH		 7320 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7321
252b5132
RH		 7322 BFD_ASSERT (s != NULL);
7323
21d799b5 7324 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7325 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7326
7327 BFD_ASSERT (tmp_name);
7328
7329 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7330
7331 myh = elf_link_hash_lookup
b34976b6 7332 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7333
7334 if (myh != NULL)
7335 {
9b485d32 7336 /* We've already seen this guy. */
252b5132 7337 free (tmp_name);
a4fd1a8e 7338 return myh;
252b5132
RH		 7339 }
7340
57e8b36a
NC		 7341 /* The only trick here is using hash_table->arm_glue_size as the value.
7342 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7343 putting it. The +1 on the value marks that the stub has not been
7344 output yet - not that it is a Thumb function. */
14a793b2 7345 bh = NULL;
dc810e39
AM		 7346 val = globals->arm_glue_size + 1;
7347 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7348 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7349 NULL, TRUE, FALSE, &bh);
252b5132 7350
b7693d02
DJ		 7351 myh = (struct elf_link_hash_entry *) bh;
7352 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7353 myh->forced_local = 1;
7354
252b5132
RH		 7355 free (tmp_name);
7356
0e1862bb
L		 7357 if (bfd_link_pic (link_info)
7358 || globals->root.is_relocatable_executable
27e55c4d 7359 || globals->pic_veneer)
2f475487 7360 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7361 else if (globals->use_blx)
7362 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7363 else
2f475487
AM		 7364 size = ARM2THUMB_STATIC_GLUE_SIZE;
7365
7366 s->size += size;
7367 globals->arm_glue_size += size;
252b5132 7368
a4fd1a8e 7369 return myh;
252b5132
RH		 7370}
7371
845b51d6
PB		 7372/* Allocate space for ARMv4 BX veneers. */
7373
7374static void
7375record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7376{
7377 asection * s;
7378 struct elf32_arm_link_hash_table *globals;
7379 char *tmp_name;
7380 struct elf_link_hash_entry *myh;
7381 struct bfd_link_hash_entry *bh;
7382 bfd_vma val;
7383
7384 /* BX PC does not need a veneer. */
7385 if (reg == 15)
7386 return;
7387
7388 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7389 BFD_ASSERT (globals != NULL);
7390 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7391
7392 /* Check if this veneer has already been allocated. */
7393 if (globals->bx_glue_offset[reg])
7394 return;
7395
3d4d4302 7396 s = bfd_get_linker_section
845b51d6
PB		 7397 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7398
7399 BFD_ASSERT (s != NULL);
7400
7401 /* Add symbol for veneer. */
21d799b5
NC		 7402 tmp_name = (char *)
7403 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7404
845b51d6 7405 BFD_ASSERT (tmp_name);
906e58ca 7406
845b51d6 7407 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7408
845b51d6
PB		 7409 myh = elf_link_hash_lookup
7410 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7411
845b51d6 7412 BFD_ASSERT (myh == NULL);
906e58ca 7413
845b51d6
PB		 7414 bh = NULL;
7415 val = globals->bx_glue_size;
7416 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7417 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7418 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7419
7420 myh = (struct elf_link_hash_entry *) bh;
7421 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7422 myh->forced_local = 1;
7423
7424 s->size += ARM_BX_VENEER_SIZE;
7425 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7426 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7427}
7428
7429
c7b8f16e
JB		 7430/* Add an entry to the code/data map for section SEC. */
7431
7432static void
7433elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7434{
7435 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7436 unsigned int newidx;
906e58ca 7437
c7b8f16e
JB		 7438 if (sec_data->map == NULL)
7439 {
21d799b5 7440 sec_data->map = (elf32_arm_section_map *)
99059e56 7441 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7442 sec_data->mapcount = 0;
7443 sec_data->mapsize = 1;
7444 }
906e58ca 7445
c7b8f16e 7446 newidx = sec_data->mapcount++;
906e58ca 7447
c7b8f16e
JB		 7448 if (sec_data->mapcount > sec_data->mapsize)
7449 {
7450 sec_data->mapsize *= 2;
21d799b5 7451 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7452 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7453 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7454 }
7455
7456 if (sec_data->map)
7457 {
7458 sec_data->map[newidx].vma = vma;
7459 sec_data->map[newidx].type = type;
c7b8f16e 7460 }
c7b8f16e
JB		 7461}
7462
7463
7464/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7465 veneers are handled for now. */
7466
7467static bfd_vma
7468record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7469 elf32_vfp11_erratum_list *branch,
7470 bfd *branch_bfd,
7471 asection *branch_sec,
7472 unsigned int offset)
c7b8f16e
JB		 7473{
7474 asection *s;
7475 struct elf32_arm_link_hash_table *hash_table;
7476 char *tmp_name;
7477 struct elf_link_hash_entry *myh;
7478 struct bfd_link_hash_entry *bh;
7479 bfd_vma val;
7480 struct _arm_elf_section_data *sec_data;
c7b8f16e 7481 elf32_vfp11_erratum_list *newerr;
906e58ca 7482
c7b8f16e 7483 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7484 BFD_ASSERT (hash_table != NULL);
7485 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7486
3d4d4302 7487 s = bfd_get_linker_section
c7b8f16e 7488 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7489
c7b8f16e 7490 sec_data = elf32_arm_section_data (s);
906e58ca 7491
c7b8f16e 7492 BFD_ASSERT (s != NULL);
906e58ca 7493
21d799b5 7494 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7495 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7496
c7b8f16e 7497 BFD_ASSERT (tmp_name);
906e58ca 7498
c7b8f16e
JB		 7499 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7500 hash_table->num_vfp11_fixes);
906e58ca 7501
c7b8f16e
JB		 7502 myh = elf_link_hash_lookup
7503 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7504
c7b8f16e 7505 BFD_ASSERT (myh == NULL);
906e58ca 7506
c7b8f16e
JB		 7507 bh = NULL;
7508 val = hash_table->vfp11_erratum_glue_size;
7509 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7510 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7511 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7512
7513 myh = (struct elf_link_hash_entry *) bh;
7514 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7515 myh->forced_local = 1;
7516
7517 /* Link veneer back to calling location. */
c7e2358a 7518 sec_data->erratumcount += 1;
21d799b5
NC		 7519 newerr = (elf32_vfp11_erratum_list *)
7520 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7521
c7b8f16e
JB		 7522 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7523 newerr->vma = -1;
7524 newerr->u.v.branch = branch;
7525 newerr->u.v.id = hash_table->num_vfp11_fixes;
7526 branch->u.b.veneer = newerr;
7527
7528 newerr->next = sec_data->erratumlist;
7529 sec_data->erratumlist = newerr;
7530
7531 /* A symbol for the return from the veneer. */
7532 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7533 hash_table->num_vfp11_fixes);
7534
7535 myh = elf_link_hash_lookup
7536 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7537
c7b8f16e
JB		 7538 if (myh != NULL)
7539 abort ();
7540
7541 bh = NULL;
7542 val = offset + 4;
7543 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7544 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7545
c7b8f16e
JB		 7546 myh = (struct elf_link_hash_entry *) bh;
7547 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7548 myh->forced_local = 1;
7549
7550 free (tmp_name);
906e58ca 7551
c7b8f16e
JB		 7552 /* Generate a mapping symbol for the veneer section, and explicitly add an
7553 entry for that symbol to the code/data map for the section. */
7554 if (hash_table->vfp11_erratum_glue_size == 0)
7555 {
7556 bh = NULL;
7557 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7558 ever requires this erratum fix. */
c7b8f16e
JB		 7559 _bfd_generic_link_add_one_symbol (link_info,
7560 hash_table->bfd_of_glue_owner, "$a",
7561 BSF_LOCAL, s, 0, NULL,
99059e56 7562 TRUE, FALSE, &bh);
c7b8f16e
JB		 7563
7564 myh = (struct elf_link_hash_entry *) bh;
7565 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7566 myh->forced_local = 1;
906e58ca 7567
c7b8f16e 7568 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7569 BFDs. We must make a note of this generated mapping symbol
7570 ourselves so that code byteswapping works properly in
7571 elf32_arm_write_section. */
c7b8f16e
JB		 7572 elf32_arm_section_map_add (s, 'a', 0);
7573 }
906e58ca 7574
c7b8f16e
JB		 7575 s->size += VFP11_ERRATUM_VENEER_SIZE;
7576 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7577 hash_table->num_vfp11_fixes++;
906e58ca 7578
c7b8f16e
JB		 7579 /* The offset of the veneer. */
7580 return val;
7581}
7582
a504d23a
LA		 7583/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7584 veneers need to be handled because used only in Cortex-M. */
7585
7586static bfd_vma
7587record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7588 elf32_stm32l4xx_erratum_list *branch,
7589 bfd *branch_bfd,
7590 asection *branch_sec,
7591 unsigned int offset,
7592 bfd_size_type veneer_size)
7593{
7594 asection *s;
7595 struct elf32_arm_link_hash_table *hash_table;
7596 char *tmp_name;
7597 struct elf_link_hash_entry *myh;
7598 struct bfd_link_hash_entry *bh;
7599 bfd_vma val;
7600 struct _arm_elf_section_data *sec_data;
7601 elf32_stm32l4xx_erratum_list *newerr;
7602
7603 hash_table = elf32_arm_hash_table (link_info);
7604 BFD_ASSERT (hash_table != NULL);
7605 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7606
7607 s = bfd_get_linker_section
7608 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7609
7610 BFD_ASSERT (s != NULL);
7611
7612 sec_data = elf32_arm_section_data (s);
7613
7614 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7615 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7616
7617 BFD_ASSERT (tmp_name);
7618
7619 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7620 hash_table->num_stm32l4xx_fixes);
7621
7622 myh = elf_link_hash_lookup
7623 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7624
7625 BFD_ASSERT (myh == NULL);
7626
7627 bh = NULL;
7628 val = hash_table->stm32l4xx_erratum_glue_size;
7629 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7630 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7631 NULL, TRUE, FALSE, &bh);
7632
7633 myh = (struct elf_link_hash_entry *) bh;
7634 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7635 myh->forced_local = 1;
7636
7637 /* Link veneer back to calling location. */
7638 sec_data->stm32l4xx_erratumcount += 1;
7639 newerr = (elf32_stm32l4xx_erratum_list *)
7640 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7641
7642 newerr->type = STM32L4XX_ERRATUM_VENEER;
7643 newerr->vma = -1;
7644 newerr->u.v.branch = branch;
7645 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7646 branch->u.b.veneer = newerr;
7647
7648 newerr->next = sec_data->stm32l4xx_erratumlist;
7649 sec_data->stm32l4xx_erratumlist = newerr;
7650
7651 /* A symbol for the return from the veneer. */
7652 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7653 hash_table->num_stm32l4xx_fixes);
7654
7655 myh = elf_link_hash_lookup
7656 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7657
7658 if (myh != NULL)
7659 abort ();
7660
7661 bh = NULL;
7662 val = offset + 4;
7663 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7664 branch_sec, val, NULL, TRUE, FALSE, &bh);
7665
7666 myh = (struct elf_link_hash_entry *) bh;
7667 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7668 myh->forced_local = 1;
7669
7670 free (tmp_name);
7671
7672 /* Generate a mapping symbol for the veneer section, and explicitly add an
7673 entry for that symbol to the code/data map for the section. */
7674 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7675 {
7676 bh = NULL;
7677 /* Creates a THUMB symbol since there is no other choice. */
7678 _bfd_generic_link_add_one_symbol (link_info,
7679 hash_table->bfd_of_glue_owner, "$t",
7680 BSF_LOCAL, s, 0, NULL,
7681 TRUE, FALSE, &bh);
7682
7683 myh = (struct elf_link_hash_entry *) bh;
7684 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7685 myh->forced_local = 1;
7686
7687 /* The elf32_arm_init_maps function only cares about symbols from input
7688 BFDs. We must make a note of this generated mapping symbol
7689 ourselves so that code byteswapping works properly in
7690 elf32_arm_write_section. */
7691 elf32_arm_section_map_add (s, 't', 0);
7692 }
7693
7694 s->size += veneer_size;
7695 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7696 hash_table->num_stm32l4xx_fixes++;
7697
7698 /* The offset of the veneer. */
7699 return val;
7700}
7701
8029a119 7702#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7703 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7704 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7705
7706/* Create a fake section for use by the ARM backend of the linker. */
7707
7708static bfd_boolean
7709arm_make_glue_section (bfd * abfd, const char * name)
7710{
7711 asection * sec;
7712
3d4d4302 7713 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7714 if (sec != NULL)
7715 /* Already made. */
7716 return TRUE;
7717
3d4d4302 7718 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7719
7720 if (sec == NULL
fd361982 7721 || !bfd_set_section_alignment (sec, 2))
8029a119
NC		 7722 return FALSE;
7723
7724 /* Set the gc mark to prevent the section from being removed by garbage
7725 collection, despite the fact that no relocs refer to this section. */
7726 sec->gc_mark = 1;
7727
7728 return TRUE;
7729}
7730
1db37fe6
YG		 7731/* Set size of .plt entries. This function is called from the
7732 linker scripts in ld/emultempl/{armelf}.em. */
7733
7734void
7735bfd_elf32_arm_use_long_plt (void)
7736{
7737 elf32_arm_use_long_plt_entry = TRUE;
7738}
7739
8afb0e02
NC		 7740/* Add the glue sections to ABFD. This function is called from the
7741 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7742
b34976b6 7743bfd_boolean
57e8b36a
NC		 7744bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7745 struct bfd_link_info *info)
252b5132 7746{
a504d23a
LA		 7747 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7748 bfd_boolean dostm32l4xx = globals
7749 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7750 bfd_boolean addglue;
7751
8afb0e02
NC		 7752 /* If we are only performing a partial
7753 link do not bother adding the glue. */
0e1862bb 7754 if (bfd_link_relocatable (info))
b34976b6 7755 return TRUE;
252b5132 7756
a504d23a 7757 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7758 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7759 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7760 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7761
7762 if (!dostm32l4xx)
7763 return addglue;
7764
7765 return addglue
7766 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7767}
7768
daa4adae
TP		 7769/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7770 ensures they are not marked for deletion by
7771 strip_excluded_output_sections () when veneers are going to be created
7772 later. Not doing so would trigger assert on empty section size in
7773 lang_size_sections_1 (). */
7774
7775void
7776bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7777{
7778 enum elf32_arm_stub_type stub_type;
7779
7780 /* If we are only performing a partial
7781 link do not bother adding the glue. */
7782 if (bfd_link_relocatable (info))
7783 return;
7784
7785 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7786 {
7787 asection *out_sec;
7788 const char *out_sec_name;
7789
7790 if (!arm_dedicated_stub_output_section_required (stub_type))
7791 continue;
7792
7793 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7794 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7795 if (out_sec != NULL)
7796 out_sec->flags |= SEC_KEEP;
7797 }
7798}
7799
8afb0e02
NC		 7800/* Select a BFD to be used to hold the sections used by the glue code.
7801 This function is called from the linker scripts in ld/emultempl/
8029a119 7802 {armelf/pe}.em. */
8afb0e02 7803
b34976b6 7804bfd_boolean
57e8b36a 7805bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7806{
7807 struct elf32_arm_link_hash_table *globals;
7808
7809 /* If we are only performing a partial link
7810 do not bother getting a bfd to hold the glue. */
0e1862bb 7811 if (bfd_link_relocatable (info))
b34976b6 7812 return TRUE;
8afb0e02 7813
b7693d02
DJ		 7814 /* Make sure we don't attach the glue sections to a dynamic object. */
7815 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7816
8afb0e02 7817 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7818 BFD_ASSERT (globals != NULL);
7819
7820 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7821 return TRUE;
8afb0e02 7822
252b5132
RH		 7823 /* Save the bfd for later use. */
7824 globals->bfd_of_glue_owner = abfd;
cedb70c5 7825
b34976b6 7826 return TRUE;
252b5132
RH		 7827}
7828
906e58ca
NC		 7829static void
7830check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7831{
2de70689
MGD		 7832 int cpu_arch;
7833
b38cadfb 7834 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7835 Tag_CPU_arch);
7836
7837 if (globals->fix_arm1176)
7838 {
7839 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7840 globals->use_blx = 1;
7841 }
7842 else
7843 {
7844 if (cpu_arch > TAG_CPU_ARCH_V4T)
7845 globals->use_blx = 1;
7846 }
39b41c9c
PB		 7847}
7848
b34976b6 7849bfd_boolean
57e8b36a 7850bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7851 struct bfd_link_info *link_info)
252b5132
RH		 7852{
7853 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7854 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7855 Elf_Internal_Rela *irel, *irelend;
7856 bfd_byte *contents = NULL;
252b5132
RH		 7857
7858 asection *sec;
7859 struct elf32_arm_link_hash_table *globals;
7860
7861 /* If we are only performing a partial link do not bother
7862 to construct any glue. */
0e1862bb 7863 if (bfd_link_relocatable (link_info))
b34976b6 7864 return TRUE;
252b5132 7865
39ce1a6a
NC		 7866 /* Here we have a bfd that is to be included on the link. We have a
7867 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7868 globals = elf32_arm_hash_table (link_info);
252b5132 7869 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7870
7871 check_use_blx (globals);
252b5132 7872
d504ffc8 7873 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7874 {
90b6238f 7875 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7876 abfd);
e489d0ae
PB		 7877 return FALSE;
7878 }
f21f3fe0 7879
39ce1a6a
NC		 7880 /* PR 5398: If we have not decided to include any loadable sections in
7881 the output then we will not have a glue owner bfd. This is OK, it
7882 just means that there is nothing else for us to do here. */
7883 if (globals->bfd_of_glue_owner == NULL)
7884 return TRUE;
7885
252b5132
RH		 7886 /* Rummage around all the relocs and map the glue vectors. */
7887 sec = abfd->sections;
7888
7889 if (sec == NULL)
b34976b6 7890 return TRUE;
252b5132
RH		 7891
7892 for (; sec != NULL; sec = sec->next)
7893 {
7894 if (sec->reloc_count == 0)
7895 continue;
7896
2f475487
AM		 7897 if ((sec->flags & SEC_EXCLUDE) != 0)
7898 continue;
7899
0ffa91dd 7900 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7901
9b485d32 7902 /* Load the relocs. */
6cdc0ccc 7903 internal_relocs
906e58ca 7904 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7905
6cdc0ccc
AM		 7906 if (internal_relocs == NULL)
7907 goto error_return;
252b5132 7908
6cdc0ccc
AM		 7909 irelend = internal_relocs + sec->reloc_count;
7910 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7911 {
7912 long r_type;
7913 unsigned long r_index;
252b5132
RH		 7914
7915 struct elf_link_hash_entry *h;
7916
7917 r_type = ELF32_R_TYPE (irel->r_info);
7918 r_index = ELF32_R_SYM (irel->r_info);
7919
9b485d32 7920 /* These are the only relocation types we care about. */
ba96a88f 7921 if ( r_type != R_ARM_PC24
845b51d6 7922 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7923 continue;
7924
7925 /* Get the section contents if we haven't done so already. */
7926 if (contents == NULL)
7927 {
7928 /* Get cached copy if it exists. */
7929 if (elf_section_data (sec)->this_hdr.contents != NULL)
7930 contents = elf_section_data (sec)->this_hdr.contents;
7931 else
7932 {
7933 /* Go get them off disk. */
57e8b36a 7934 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7935 goto error_return;
7936 }
7937 }
7938
845b51d6
PB		 7939 if (r_type == R_ARM_V4BX)
7940 {
7941 int reg;
7942
7943 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7944 record_arm_bx_glue (link_info, reg);
7945 continue;
7946 }
7947
a7c10850 7948 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7949 h = NULL;
7950
9b485d32 7951 /* We don't care about local symbols. */
252b5132
RH		 7952 if (r_index < symtab_hdr->sh_info)
7953 continue;
7954
9b485d32 7955 /* This is an external symbol. */
252b5132
RH		 7956 r_index -= symtab_hdr->sh_info;
7957 h = (struct elf_link_hash_entry *)
7958 elf_sym_hashes (abfd)[r_index];
7959
7960 /* If the relocation is against a static symbol it must be within
7961 the current section and so cannot be a cross ARM/Thumb relocation. */
7962 if (h == NULL)
7963 continue;
7964
d504ffc8
DJ		 7965 /* If the call will go through a PLT entry then we do not need
7966 glue. */
362d30a1 7967 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7968 continue;
7969
252b5132
RH		 7970 switch (r_type)
7971 {
7972 case R_ARM_PC24:
7973 /* This one is a call from arm code. We need to look up
99059e56
RM		 7974 the target of the call. If it is a thumb target, we
7975 insert glue. */
39d911fc
TP		 7976 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7977 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7978 record_arm_to_thumb_glue (link_info, h);
7979 break;
7980
252b5132 7981 default:
c6596c5e 7982 abort ();
252b5132
RH		 7983 }
7984 }
6cdc0ccc
AM		 7985
7986 if (contents != NULL
7987 && elf_section_data (sec)->this_hdr.contents != contents)
7988 free (contents);
7989 contents = NULL;
7990
7991 if (internal_relocs != NULL
7992 && elf_section_data (sec)->relocs != internal_relocs)
7993 free (internal_relocs);
7994 internal_relocs = NULL;
252b5132
RH		 7995 }
7996
b34976b6 7997 return TRUE;
9a5aca8c 7998
252b5132 7999error_return:
6cdc0ccc
AM		 8000 if (contents != NULL
8001 && elf_section_data (sec)->this_hdr.contents != contents)
8002 free (contents);
8003 if (internal_relocs != NULL
8004 && elf_section_data (sec)->relocs != internal_relocs)
8005 free (internal_relocs);
9a5aca8c 8006
b34976b6 8007 return FALSE;
252b5132 8008}
7e392df6 8009#endif
252b5132 8010
eb043451 8011
c7b8f16e
JB		 8012/* Initialise maps of ARM/Thumb/data for input BFDs. */
8013
8014void
8015bfd_elf32_arm_init_maps (bfd *abfd)
8016{
8017 Elf_Internal_Sym *isymbuf;
8018 Elf_Internal_Shdr *hdr;
8019 unsigned int i, localsyms;
8020
af1f4419
NC		 8021 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
8022 if (! is_arm_elf (abfd))
8023 return;
8024
c7b8f16e
JB		 8025 if ((abfd->flags & DYNAMIC) != 0)
8026 return;
8027
0ffa91dd 8028 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 8029 localsyms = hdr->sh_info;
8030
8031 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
8032 should contain the number of local symbols, which should come before any
8033 global symbols. Mapping symbols are always local. */
8034 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
8035 NULL);
8036
8037 /* No internal symbols read? Skip this BFD. */
8038 if (isymbuf == NULL)
8039 return;
8040
8041 for (i = 0; i < localsyms; i++)
8042 {
8043 Elf_Internal_Sym *isym = &isymbuf[i];
8044 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
8045 const char *name;
906e58ca 8046
c7b8f16e 8047 if (sec != NULL
99059e56
RM		 8048 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
8049 {
8050 name = bfd_elf_string_from_elf_section (abfd,
8051 hdr->sh_link, isym->st_name);
906e58ca 8052
99059e56 8053 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 8054 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 8055 elf32_arm_section_map_add (sec, name[1], isym->st_value);
8056 }
c7b8f16e
JB		 8057 }
8058}
8059
8060
48229727
JB		 8061/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8062 say what they wanted. */
8063
8064void
8065bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
8066{
8067 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8068 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8069
4dfe6ac6
NC		 8070 if (globals == NULL)
8071 return;
8072
48229727
JB		 8073 if (globals->fix_cortex_a8 == -1)
8074 {
8075 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8076 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
8077 && (out_attr[Tag_CPU_arch_profile].i == 'A'
8078 || out_attr[Tag_CPU_arch_profile].i == 0))
8079 globals->fix_cortex_a8 = 1;
8080 else
8081 globals->fix_cortex_a8 = 0;
8082 }
8083}
8084
8085
c7b8f16e
JB		 8086void
8087bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
8088{
8089 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 8090 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 8091
4dfe6ac6
NC		 8092 if (globals == NULL)
8093 return;
c7b8f16e
JB		 8094 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8095 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
8096 {
8097 switch (globals->vfp11_fix)
99059e56
RM		 8098 {
8099 case BFD_ARM_VFP11_FIX_DEFAULT:
8100 case BFD_ARM_VFP11_FIX_NONE:
8101 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8102 break;
8103
8104 default:
8105 /* Give a warning, but do as the user requests anyway. */
871b3ab2 8106 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 8107 "workaround is not necessary for target architecture"), obfd);
8108 }
c7b8f16e
JB		 8109 }
8110 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
8111 /* For earlier architectures, we might need the workaround, but do not
8112 enable it by default. If users is running with broken hardware, they
8113 must enable the erratum fix explicitly. */
8114 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8115}
8116
a504d23a
LA		 8117void
8118bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8119{
8120 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8121 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8122
8123 if (globals == NULL)
8124 return;
8125
8126 /* We assume only Cortex-M4 may require the fix. */
8127 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8128 || out_attr[Tag_CPU_arch_profile].i != 'M')
8129 {
8130 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8131 /* Give a warning, but do as the user requests anyway. */
4eca0228 8132 _bfd_error_handler
871b3ab2 8133 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 8134 "workaround is not necessary for target architecture"), obfd);
8135 }
8136}
c7b8f16e 8137
906e58ca
NC		 8138enum bfd_arm_vfp11_pipe
8139{
c7b8f16e
JB		 8140 VFP11_FMAC,
8141 VFP11_LS,
8142 VFP11_DS,
8143 VFP11_BAD
8144};
8145
8146/* Return a VFP register number. This is encoded as RX:X for single-precision
8147 registers, or X:RX for double-precision registers, where RX is the group of
8148 four bits in the instruction encoding and X is the single extension bit.
8149 RX and X fields are specified using their lowest (starting) bit. The return
8150 value is:
8151
8152 0...31: single-precision registers s0...s31
8153 32...63: double-precision registers d0...d31.
906e58ca 8154
c7b8f16e
JB		 8155 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8156 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 8157
c7b8f16e
JB		 8158static unsigned int
8159bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 8160 unsigned int x)
c7b8f16e
JB		 8161{
8162 if (is_double)
8163 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8164 else
8165 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8166}
8167
8168/* Set bits in *WMASK according to a register number REG as encoded by
8169 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8170
8171static void
8172bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8173{
8174 if (reg < 32)
8175 *wmask |= 1 << reg;
8176 else if (reg < 48)
8177 *wmask |= 3 << ((reg - 32) * 2);
8178}
8179
8180/* Return TRUE if WMASK overwrites anything in REGS. */
8181
8182static bfd_boolean
8183bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8184{
8185 int i;
906e58ca 8186
c7b8f16e
JB		 8187 for (i = 0; i < numregs; i++)
8188 {
8189 unsigned int reg = regs[i];
8190
8191 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 8192 return TRUE;
906e58ca 8193
c7b8f16e
JB		 8194 reg -= 32;
8195
8196 if (reg >= 16)
99059e56 8197 continue;
906e58ca 8198
c7b8f16e 8199 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 8200 return TRUE;
c7b8f16e 8201 }
906e58ca 8202
c7b8f16e
JB		 8203 return FALSE;
8204}
8205
8206/* In this function, we're interested in two things: finding input registers
8207 for VFP data-processing instructions, and finding the set of registers which
8208 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8209 hold the written set, so FLDM etc. are easy to deal with (we're only
8210 interested in 32 SP registers or 16 dp registers, due to the VFP version
8211 implemented by the chip in question). DP registers are marked by setting
8212 both SP registers in the write mask). */
8213
8214static enum bfd_arm_vfp11_pipe
8215bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 8216 int *numregs)
c7b8f16e 8217{
91d6fa6a 8218 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 8219 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8220
8221 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8222 {
8223 unsigned int pqrs;
8224 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8225 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8226
8227 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 8228 | ((insn & 0x00300000) >> 19)
8229 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 8230
8231 switch (pqrs)
99059e56
RM		 8232 {
8233 case 0: /* fmac[sd]. */
8234 case 1: /* fnmac[sd]. */
8235 case 2: /* fmsc[sd]. */
8236 case 3: /* fnmsc[sd]. */
8237 vpipe = VFP11_FMAC;
8238 bfd_arm_vfp11_write_mask (destmask, fd);
8239 regs[0] = fd;
8240 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8241 regs[2] = fm;
8242 *numregs = 3;
8243 break;
8244
8245 case 4: /* fmul[sd]. */
8246 case 5: /* fnmul[sd]. */
8247 case 6: /* fadd[sd]. */
8248 case 7: /* fsub[sd]. */
8249 vpipe = VFP11_FMAC;
8250 goto vfp_binop;
8251
8252 case 8: /* fdiv[sd]. */
8253 vpipe = VFP11_DS;
8254 vfp_binop:
8255 bfd_arm_vfp11_write_mask (destmask, fd);
8256 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8257 regs[1] = fm;
8258 *numregs = 2;
8259 break;
8260
8261 case 15: /* extended opcode. */
8262 {
8263 unsigned int extn = ((insn >> 15) & 0x1e)
8264 | ((insn >> 7) & 1);
8265
8266 switch (extn)
8267 {
8268 case 0: /* fcpy[sd]. */
8269 case 1: /* fabs[sd]. */
8270 case 2: /* fneg[sd]. */
8271 case 8: /* fcmp[sd]. */
8272 case 9: /* fcmpe[sd]. */
8273 case 10: /* fcmpz[sd]. */
8274 case 11: /* fcmpez[sd]. */
8275 case 16: /* fuito[sd]. */
8276 case 17: /* fsito[sd]. */
8277 case 24: /* ftoui[sd]. */
8278 case 25: /* ftouiz[sd]. */
8279 case 26: /* ftosi[sd]. */
8280 case 27: /* ftosiz[sd]. */
8281 /* These instructions will not bounce due to underflow. */
8282 *numregs = 0;
8283 vpipe = VFP11_FMAC;
8284 break;
8285
8286 case 3: /* fsqrt[sd]. */
8287 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8288 registers to cause the erratum in previous instructions. */
8289 bfd_arm_vfp11_write_mask (destmask, fd);
8290 vpipe = VFP11_DS;
8291 break;
8292
8293 case 15: /* fcvt{ds,sd}. */
8294 {
8295 int rnum = 0;
8296
8297 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8298
8299 /* Only FCVTSD can underflow. */
99059e56
RM		 8300 if ((insn & 0x100) != 0)
8301 regs[rnum++] = fm;
c7b8f16e 8302
99059e56 8303 *numregs = rnum;
c7b8f16e 8304
99059e56
RM		 8305 vpipe = VFP11_FMAC;
8306 }
8307 break;
c7b8f16e 8308
99059e56
RM		 8309 default:
8310 return VFP11_BAD;
8311 }
8312 }
8313 break;
c7b8f16e 8314
99059e56
RM		 8315 default:
8316 return VFP11_BAD;
8317 }
c7b8f16e
JB		 8318 }
8319 /* Two-register transfer. */
8320 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8321 {
8322 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8323
c7b8f16e
JB		 8324 if ((insn & 0x100000) == 0)
8325 {
99059e56
RM		 8326 if (is_double)
8327 bfd_arm_vfp11_write_mask (destmask, fm);
8328 else
8329 {
8330 bfd_arm_vfp11_write_mask (destmask, fm);
8331 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8332 }
c7b8f16e
JB		 8333 }
8334
91d6fa6a 8335 vpipe = VFP11_LS;
c7b8f16e
JB		 8336 }
8337 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8338 {
8339 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8340 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8341
c7b8f16e 8342 switch (puw)
99059e56
RM		 8343 {
8344 case 0: /* Two-reg transfer. We should catch these above. */
8345 abort ();
906e58ca 8346
99059e56
RM		 8347 case 2: /* fldm[sdx]. */
8348 case 3:
8349 case 5:
8350 {
8351 unsigned int i, offset = insn & 0xff;
c7b8f16e 8352
99059e56
RM		 8353 if (is_double)
8354 offset >>= 1;
c7b8f16e 8355
99059e56
RM		 8356 for (i = fd; i < fd + offset; i++)
8357 bfd_arm_vfp11_write_mask (destmask, i);
8358 }
8359 break;
906e58ca 8360
99059e56
RM		 8361 case 4: /* fld[sd]. */
8362 case 6:
8363 bfd_arm_vfp11_write_mask (destmask, fd);
8364 break;
906e58ca 8365
99059e56
RM		 8366 default:
8367 return VFP11_BAD;
8368 }
c7b8f16e 8369
91d6fa6a 8370 vpipe = VFP11_LS;
c7b8f16e
JB		 8371 }
8372 /* Single-register transfer. Note L==0. */
8373 else if ((insn & 0x0f100e10) == 0x0e000a10)
8374 {
8375 unsigned int opcode = (insn >> 21) & 7;
8376 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8377
8378 switch (opcode)
99059e56
RM		 8379 {
8380 case 0: /* fmsr/fmdlr. */
8381 case 1: /* fmdhr. */
8382 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8383 destination register. I don't know if this is exactly right,
8384 but it is the conservative choice. */
8385 bfd_arm_vfp11_write_mask (destmask, fn);
8386 break;
8387
8388 case 7: /* fmxr. */
8389 break;
8390 }
c7b8f16e 8391
91d6fa6a 8392 vpipe = VFP11_LS;
c7b8f16e
JB		 8393 }
8394
91d6fa6a 8395 return vpipe;
c7b8f16e
JB		 8396}
8397
8398
8399static int elf32_arm_compare_mapping (const void * a, const void * b);
8400
8401
8402/* Look for potentially-troublesome code sequences which might trigger the
8403 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8404 (available from ARM) for details of the erratum. A short version is
8405 described in ld.texinfo. */
8406
8407bfd_boolean
8408bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8409{
8410 asection *sec;
8411 bfd_byte *contents = NULL;
8412 int state = 0;
8413 int regs[3], numregs = 0;
8414 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8415 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8416
4dfe6ac6
NC		 8417 if (globals == NULL)
8418 return FALSE;
8419
c7b8f16e
JB		 8420 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8421 The states transition as follows:
906e58ca 8422
c7b8f16e 8423 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8424 A VFP FMAC-pipeline instruction has been seen. Fill
8425 regs[0]..regs[numregs-1] with its input operands. Remember this
8426 instruction in 'first_fmac'.
c7b8f16e
JB		 8427
8428 1 -> 2
99059e56
RM		 8429 Any instruction, except for a VFP instruction which overwrites
8430 regs[*].
906e58ca 8431
c7b8f16e
JB		 8432 1 -> 3 [ -> 0 ] or
8433 2 -> 3 [ -> 0 ]
99059e56
RM		 8434 A VFP instruction has been seen which overwrites any of regs[*].
8435 We must make a veneer! Reset state to 0 before examining next
8436 instruction.
906e58ca 8437
c7b8f16e 8438 2 -> 0
99059e56
RM		 8439 If we fail to match anything in state 2, reset to state 0 and reset
8440 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8441
8442 If the VFP11 vector mode is in use, there must be at least two unrelated
8443 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8444 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8445
8446 /* If we are only performing a partial link do not bother
8447 to construct any glue. */
0e1862bb 8448 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8449 return TRUE;
8450
0ffa91dd
NC		 8451 /* Skip if this bfd does not correspond to an ELF image. */
8452 if (! is_arm_elf (abfd))
8453 return TRUE;
906e58ca 8454
c7b8f16e
JB		 8455 /* We should have chosen a fix type by the time we get here. */
8456 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8457
8458 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8459 return TRUE;
2e6030b9 8460
33a7ffc2
JM		 8461 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8462 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8463 return TRUE;
8464
c7b8f16e
JB		 8465 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8466 {
8467 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8468 struct _arm_elf_section_data *sec_data;
8469
8470 /* If we don't have executable progbits, we're not interested in this
99059e56 8471 section. Also skip if section is to be excluded. */
c7b8f16e 8472 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8473 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8474 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8475 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8476 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8477 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8478 continue;
c7b8f16e
JB		 8479
8480 sec_data = elf32_arm_section_data (sec);
906e58ca 8481
c7b8f16e 8482 if (sec_data->mapcount == 0)
99059e56 8483 continue;
906e58ca 8484
c7b8f16e
JB		 8485 if (elf_section_data (sec)->this_hdr.contents != NULL)
8486 contents = elf_section_data (sec)->this_hdr.contents;
8487 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8488 goto error_return;
8489
8490 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8491 elf32_arm_compare_mapping);
8492
8493 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8494 {
8495 unsigned int span_start = sec_data->map[span].vma;
8496 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8497 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8498 char span_type = sec_data->map[span].type;
8499
8500 /* FIXME: Only ARM mode is supported at present. We may need to
8501 support Thumb-2 mode also at some point. */
8502 if (span_type != 'a')
8503 continue;
8504
8505 for (i = span_start; i < span_end;)
8506 {
8507 unsigned int next_i = i + 4;
8508 unsigned int insn = bfd_big_endian (abfd)
8509 ? (contents[i] << 24)
8510 | (contents[i + 1] << 16)
8511 | (contents[i + 2] << 8)
8512 | contents[i + 3]
8513 : (contents[i + 3] << 24)
8514 | (contents[i + 2] << 16)
8515 | (contents[i + 1] << 8)
8516 | contents[i];
8517 unsigned int writemask = 0;
8518 enum bfd_arm_vfp11_pipe vpipe;
8519
8520 switch (state)
8521 {
8522 case 0:
8523 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8524 &numregs);
8525 /* I'm assuming the VFP11 erratum can trigger with denorm
8526 operands on either the FMAC or the DS pipeline. This might
8527 lead to slightly overenthusiastic veneer insertion. */
8528 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8529 {
8530 state = use_vector ? 1 : 2;
8531 first_fmac = i;
8532 veneer_of_insn = insn;
8533 }
8534 break;
8535
8536 case 1:
8537 {
8538 int other_regs[3], other_numregs;
8539 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8540 other_regs,
99059e56
RM		 8541 &other_numregs);
8542 if (vpipe != VFP11_BAD
8543 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8544 numregs))
99059e56
RM		 8545 state = 3;
8546 else
8547 state = 2;
8548 }
8549 break;
8550
8551 case 2:
8552 {
8553 int other_regs[3], other_numregs;
8554 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8555 other_regs,
99059e56
RM		 8556 &other_numregs);
8557 if (vpipe != VFP11_BAD
8558 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8559 numregs))
99059e56
RM		 8560 state = 3;
8561 else
8562 {
8563 state = 0;
8564 next_i = first_fmac + 4;
8565 }
8566 }
8567 break;
8568
8569 case 3:
8570 abort (); /* Should be unreachable. */
8571 }
8572
8573 if (state == 3)
8574 {
8575 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8576 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8577
8578 elf32_arm_section_data (sec)->erratumcount += 1;
8579
8580 newerr->u.b.vfp_insn = veneer_of_insn;
8581
8582 switch (span_type)
8583 {
8584 case 'a':
8585 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8586 break;
8587
8588 default:
8589 abort ();
8590 }
8591
8592 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8593 first_fmac);
8594
99059e56 8595 newerr->vma = -1;
c7b8f16e 8596
99059e56
RM		 8597 newerr->next = sec_data->erratumlist;
8598 sec_data->erratumlist = newerr;
c7b8f16e 8599
99059e56
RM		 8600 state = 0;
8601 }
c7b8f16e 8602
99059e56
RM		 8603 i = next_i;
8604 }
8605 }
906e58ca 8606
c7b8f16e 8607 if (contents != NULL
99059e56
RM		 8608 && elf_section_data (sec)->this_hdr.contents != contents)
8609 free (contents);
c7b8f16e
JB		 8610 contents = NULL;
8611 }
8612
8613 return TRUE;
8614
8615error_return:
8616 if (contents != NULL
8617 && elf_section_data (sec)->this_hdr.contents != contents)
8618 free (contents);
906e58ca 8619
c7b8f16e
JB		 8620 return FALSE;
8621}
8622
8623/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8624 after sections have been laid out, using specially-named symbols. */
8625
8626void
8627bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8628 struct bfd_link_info *link_info)
8629{
8630 asection *sec;
8631 struct elf32_arm_link_hash_table *globals;
8632 char *tmp_name;
906e58ca 8633
0e1862bb 8634 if (bfd_link_relocatable (link_info))
c7b8f16e 8635 return;
2e6030b9
MS		 8636
8637 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8638 if (! is_arm_elf (abfd))
2e6030b9
MS		 8639 return;
8640
c7b8f16e 8641 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8642 if (globals == NULL)
8643 return;
906e58ca 8644
21d799b5 8645 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8646 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8647
8648 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8649 {
8650 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8651 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8652
c7b8f16e 8653 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8654 {
8655 struct elf_link_hash_entry *myh;
8656 bfd_vma vma;
8657
8658 switch (errnode->type)
8659 {
8660 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8661 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8662 /* Find veneer symbol. */
8663 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8664 errnode->u.b.veneer->u.v.id);
8665
99059e56
RM		 8666 myh = elf_link_hash_lookup
8667 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8668
a504d23a 8669 if (myh == NULL)
90b6238f
AM		 8670 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8671 abfd, "VFP11", tmp_name);
a504d23a
LA		 8672
8673 vma = myh->root.u.def.section->output_section->vma
8674 + myh->root.u.def.section->output_offset
8675 + myh->root.u.def.value;
8676
8677 errnode->u.b.veneer->vma = vma;
8678 break;
8679
8680 case VFP11_ERRATUM_ARM_VENEER:
8681 case VFP11_ERRATUM_THUMB_VENEER:
8682 /* Find return location. */
8683 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8684 errnode->u.v.id);
8685
8686 myh = elf_link_hash_lookup
8687 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8688
8689 if (myh == NULL)
90b6238f
AM		 8690 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8691 abfd, "VFP11", tmp_name);
a504d23a
LA		 8692
8693 vma = myh->root.u.def.section->output_section->vma
8694 + myh->root.u.def.section->output_offset
8695 + myh->root.u.def.value;
8696
8697 errnode->u.v.branch->vma = vma;
8698 break;
8699
8700 default:
8701 abort ();
8702 }
8703 }
8704 }
8705
8706 free (tmp_name);
8707}
8708
8709/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8710 return locations after sections have been laid out, using
8711 specially-named symbols. */
8712
8713void
8714bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8715 struct bfd_link_info *link_info)
8716{
8717 asection *sec;
8718 struct elf32_arm_link_hash_table *globals;
8719 char *tmp_name;
8720
8721 if (bfd_link_relocatable (link_info))
8722 return;
8723
8724 /* Skip if this bfd does not correspond to an ELF image. */
8725 if (! is_arm_elf (abfd))
8726 return;
8727
8728 globals = elf32_arm_hash_table (link_info);
8729 if (globals == NULL)
8730 return;
8731
8732 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8733 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8734
8735 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8736 {
8737 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8738 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8739
8740 for (; errnode != NULL; errnode = errnode->next)
8741 {
8742 struct elf_link_hash_entry *myh;
8743 bfd_vma vma;
8744
8745 switch (errnode->type)
8746 {
8747 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8748 /* Find veneer symbol. */
8749 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8750 errnode->u.b.veneer->u.v.id);
8751
8752 myh = elf_link_hash_lookup
8753 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8754
8755 if (myh == NULL)
90b6238f
AM		 8756 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8757 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8758
8759 vma = myh->root.u.def.section->output_section->vma
8760 + myh->root.u.def.section->output_offset
8761 + myh->root.u.def.value;
8762
8763 errnode->u.b.veneer->vma = vma;
8764 break;
8765
8766 case STM32L4XX_ERRATUM_VENEER:
8767 /* Find return location. */
8768 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8769 errnode->u.v.id);
8770
8771 myh = elf_link_hash_lookup
8772 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8773
8774 if (myh == NULL)
90b6238f
AM		 8775 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8776 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8777
8778 vma = myh->root.u.def.section->output_section->vma
8779 + myh->root.u.def.section->output_offset
8780 + myh->root.u.def.value;
8781
8782 errnode->u.v.branch->vma = vma;
8783 break;
8784
8785 default:
8786 abort ();
8787 }
8788 }
8789 }
8790
8791 free (tmp_name);
8792}
8793
8794static inline bfd_boolean
8795is_thumb2_ldmia (const insn32 insn)
8796{
8797 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8798 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8799 return (insn & 0xffd02000) == 0xe8900000;
8800}
8801
8802static inline bfd_boolean
8803is_thumb2_ldmdb (const insn32 insn)
8804{
8805 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8806 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8807 return (insn & 0xffd02000) == 0xe9100000;
8808}
8809
8810static inline bfd_boolean
8811is_thumb2_vldm (const insn32 insn)
8812{
8813 /* A6.5 Extension register load or store instruction
8814 A7.7.229
9239bbd3
CM		 8815 We look for SP 32-bit and DP 64-bit registers.
8816 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8817 <list> is consecutive 64-bit registers
8818 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8819 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8820 <list> is consecutive 32-bit registers
8821 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8822 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8823 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8824 return
9239bbd3
CM		 8825 (((insn & 0xfe100f00) == 0xec100b00) ||
8826 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8827 && /* (IA without !). */
8828 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8829 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8830 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8831 /* (DB with !). */
8832 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8833}
8834
8835/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8836 VLDM opcode and:
8837 - computes the number and the mode of memory accesses
8838 - decides if the replacement should be done:
8839 . replaces only if > 8-word accesses
8840 . or (testing purposes only) replaces all accesses. */
8841
8842static bfd_boolean
8843stm32l4xx_need_create_replacing_stub (const insn32 insn,
8844 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8845{
9239bbd3 8846 int nb_words = 0;
a504d23a
LA		 8847
8848 /* The field encoding the register list is the same for both LDMIA
8849 and LDMDB encodings. */
8850 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8851 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8852 else if (is_thumb2_vldm (insn))
9239bbd3 8853 nb_words = (insn & 0xff);
a504d23a
LA		 8854
8855 /* DEFAULT mode accounts for the real bug condition situation,
8856 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8857 return
9239bbd3 8858 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8859 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8860}
8861
8862/* Look for potentially-troublesome code sequences which might trigger
8863 the STM STM32L4XX erratum. */
8864
8865bfd_boolean
8866bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8867 struct bfd_link_info *link_info)
8868{
8869 asection *sec;
8870 bfd_byte *contents = NULL;
8871 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8872
8873 if (globals == NULL)
8874 return FALSE;
8875
8876 /* If we are only performing a partial link do not bother
8877 to construct any glue. */
8878 if (bfd_link_relocatable (link_info))
8879 return TRUE;
8880
8881 /* Skip if this bfd does not correspond to an ELF image. */
8882 if (! is_arm_elf (abfd))
8883 return TRUE;
8884
8885 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8886 return TRUE;
8887
8888 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8889 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8890 return TRUE;
8891
8892 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8893 {
8894 unsigned int i, span;
8895 struct _arm_elf_section_data *sec_data;
8896
8897 /* If we don't have executable progbits, we're not interested in this
8898 section. Also skip if section is to be excluded. */
8899 if (elf_section_type (sec) != SHT_PROGBITS
8900 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8901 || (sec->flags & SEC_EXCLUDE) != 0
8902 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8903 || sec->output_section == bfd_abs_section_ptr
8904 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8905 continue;
8906
8907 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8908
a504d23a
LA		 8909 if (sec_data->mapcount == 0)
8910 continue;
c7b8f16e 8911
a504d23a
LA		 8912 if (elf_section_data (sec)->this_hdr.contents != NULL)
8913 contents = elf_section_data (sec)->this_hdr.contents;
8914 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8915 goto error_return;
c7b8f16e 8916
a504d23a
LA		 8917 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8918 elf32_arm_compare_mapping);
c7b8f16e 8919
a504d23a
LA		 8920 for (span = 0; span < sec_data->mapcount; span++)
8921 {
8922 unsigned int span_start = sec_data->map[span].vma;
8923 unsigned int span_end = (span == sec_data->mapcount - 1)
8924 ? sec->size : sec_data->map[span + 1].vma;
8925 char span_type = sec_data->map[span].type;
8926 int itblock_current_pos = 0;
c7b8f16e 8927
a504d23a
LA		 8928 /* Only Thumb2 mode need be supported with this CM4 specific
8929 code, we should not encounter any arm mode eg span_type
8930 != 'a'. */
8931 if (span_type != 't')
8932 continue;
c7b8f16e 8933
a504d23a
LA		 8934 for (i = span_start; i < span_end;)
8935 {
8936 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8937 bfd_boolean insn_32bit = FALSE;
8938 bfd_boolean is_ldm = FALSE;
8939 bfd_boolean is_vldm = FALSE;
8940 bfd_boolean is_not_last_in_it_block = FALSE;
8941
8942 /* The first 16-bits of all 32-bit thumb2 instructions start
8943 with opcode[15..13]=0b111 and the encoded op1 can be anything
8944 except opcode[12..11]!=0b00.
8945 See 32-bit Thumb instruction encoding. */
8946 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8947 insn_32bit = TRUE;
c7b8f16e 8948
a504d23a
LA		 8949 /* Compute the predicate that tells if the instruction
8950 is concerned by the IT block
8951 - Creates an error if there is a ldm that is not
8952 last in the IT block thus cannot be replaced
8953 - Otherwise we can create a branch at the end of the
8954 IT block, it will be controlled naturally by IT
8955 with the proper pseudo-predicate
8956 - So the only interesting predicate is the one that
8957 tells that we are not on the last item of an IT
8958 block. */
8959 if (itblock_current_pos != 0)
8960 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8961
a504d23a
LA		 8962 if (insn_32bit)
8963 {
8964 /* Load the rest of the insn (in manual-friendly order). */
8965 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8966 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8967 is_vldm = is_thumb2_vldm (insn);
8968
8969 /* Veneers are created for (v)ldm depending on
8970 option flags and memory accesses conditions; but
8971 if the instruction is not the last instruction of
8972 an IT block, we cannot create a jump there, so we
8973 bail out. */
5025eb7c
AO		 8974 if ((is_ldm || is_vldm)
8975 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8976 (insn, globals->stm32l4xx_fix))
8977 {
8978 if (is_not_last_in_it_block)
8979 {
4eca0228 8980 _bfd_error_handler
695344c0 8981 /* xgettext:c-format */
871b3ab2 8982 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8983 " in non-last IT block instruction:"
8984 " STM32L4XX veneer cannot be generated; "
8985 "use gcc option -mrestrict-it to generate"
8986 " only one instruction per IT block"),
d42c267e 8987 abfd, sec, i);
a504d23a
LA		 8988 }
8989 else
8990 {
8991 elf32_stm32l4xx_erratum_list *newerr =
8992 (elf32_stm32l4xx_erratum_list *)
8993 bfd_zmalloc
8994 (sizeof (elf32_stm32l4xx_erratum_list));
8995
8996 elf32_arm_section_data (sec)
8997 ->stm32l4xx_erratumcount += 1;
8998 newerr->u.b.insn = insn;
8999 /* We create only thumb branches. */
9000 newerr->type =
9001 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
9002 record_stm32l4xx_erratum_veneer
9003 (link_info, newerr, abfd, sec,
9004 i,
9005 is_ldm ?
9006 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
9007 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
9008 newerr->vma = -1;
9009 newerr->next = sec_data->stm32l4xx_erratumlist;
9010 sec_data->stm32l4xx_erratumlist = newerr;
9011 }
9012 }
9013 }
9014 else
9015 {
9016 /* A7.7.37 IT p208
9017 IT blocks are only encoded in T1
9018 Encoding T1: IT{x{y{z}}} <firstcond>
9019 1 0 1 1 - 1 1 1 1 - firstcond - mask
9020 if mask = '0000' then see 'related encodings'
9021 We don't deal with UNPREDICTABLE, just ignore these.
9022 There can be no nested IT blocks so an IT block
9023 is naturally a new one for which it is worth
9024 computing its size. */
5025eb7c
AO		 9025 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
9026 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 9027 /* If we have a new IT block we compute its size. */
9028 if (is_newitblock)
9029 {
9030 /* Compute the number of instructions controlled
9031 by the IT block, it will be used to decide
9032 whether we are inside an IT block or not. */
9033 unsigned int mask = insn & 0x000f;
9034 itblock_current_pos = 4 - ctz (mask);
9035 }
9036 }
9037
9038 i += insn_32bit ? 4 : 2;
99059e56
RM		 9039 }
9040 }
a504d23a
LA		 9041
9042 if (contents != NULL
9043 && elf_section_data (sec)->this_hdr.contents != contents)
9044 free (contents);
9045 contents = NULL;
c7b8f16e 9046 }
906e58ca 9047
a504d23a
LA		 9048 return TRUE;
9049
9050error_return:
9051 if (contents != NULL
9052 && elf_section_data (sec)->this_hdr.contents != contents)
9053 free (contents);
c7b8f16e 9054
a504d23a
LA		 9055 return FALSE;
9056}
c7b8f16e 9057
eb043451
PB		 9058/* Set target relocation values needed during linking. */
9059
9060void
68c39892 9061bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 9062 struct bfd_link_info *link_info,
68c39892 9063 struct elf32_arm_params *params)
eb043451
PB		 9064{
9065 struct elf32_arm_link_hash_table *globals;
9066
9067 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9068 if (globals == NULL)
9069 return;
eb043451 9070
68c39892 9071 globals->target1_is_rel = params->target1_is_rel;
29e9b073
CL		 9072 if (globals->fdpic_p)
9073 globals->target2_reloc = R_ARM_GOT32;
9074 else if (strcmp (params->target2_type, "rel") == 0)
eb043451 9075 globals->target2_reloc = R_ARM_REL32;
68c39892 9076 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 9077 globals->target2_reloc = R_ARM_ABS32;
68c39892 9078 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 9079 globals->target2_reloc = R_ARM_GOT_PREL;
9080 else
9081 {
90b6238f 9082 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 9083 params->target2_type);
eb043451 9084 }
68c39892
TP		 9085 globals->fix_v4bx = params->fix_v4bx;
9086 globals->use_blx |= params->use_blx;
9087 globals->vfp11_fix = params->vfp11_denorm_fix;
9088 globals->stm32l4xx_fix = params->stm32l4xx_fix;
e8b09b87
CL		 9089 if (globals->fdpic_p)
9090 globals->pic_veneer = 1;
9091 else
9092 globals->pic_veneer = params->pic_veneer;
68c39892
TP		 9093 globals->fix_cortex_a8 = params->fix_cortex_a8;
9094 globals->fix_arm1176 = params->fix_arm1176;
9095 globals->cmse_implib = params->cmse_implib;
9096 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 9097
0ffa91dd 9098 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 9099 elf_arm_tdata (output_bfd)->no_enum_size_warning
9100 = params->no_enum_size_warning;
9101 elf_arm_tdata (output_bfd)->no_wchar_size_warning
9102 = params->no_wchar_size_warning;
eb043451 9103}
eb043451 9104
12a0a0fd 9105/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 9106
12a0a0fd
PB		 9107static void
9108insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
9109{
9110 bfd_vma upper;
9111 bfd_vma lower;
9112 int reloc_sign;
9113
9114 BFD_ASSERT ((offset & 1) == 0);
9115
9116 upper = bfd_get_16 (abfd, insn);
9117 lower = bfd_get_16 (abfd, insn + 2);
9118 reloc_sign = (offset < 0) ? 1 : 0;
9119 upper = (upper & ~(bfd_vma) 0x7ff)
9120 | ((offset >> 12) & 0x3ff)
9121 | (reloc_sign << 10);
906e58ca 9122 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 9123 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9124 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9125 | ((offset >> 1) & 0x7ff);
9126 bfd_put_16 (abfd, upper, insn);
9127 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 9128}
9129
9b485d32
NC		 9130/* Thumb code calling an ARM function. */
9131
252b5132 9132static int
57e8b36a 9133elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9134 const char * name,
9135 bfd * input_bfd,
9136 bfd * output_bfd,
9137 asection * input_section,
9138 bfd_byte * hit_data,
9139 asection * sym_sec,
9140 bfd_vma offset,
9141 bfd_signed_vma addend,
9142 bfd_vma val,
f2a9dd69 9143 char **error_message)
252b5132 9144{
bcbdc74c 9145 asection * s = 0;
dc810e39 9146 bfd_vma my_offset;
252b5132 9147 long int ret_offset;
bcbdc74c
NC		 9148 struct elf_link_hash_entry * myh;
9149 struct elf32_arm_link_hash_table * globals;
252b5132 9150
f2a9dd69 9151 myh = find_thumb_glue (info, name, error_message);
252b5132 9152 if (myh == NULL)
b34976b6 9153 return FALSE;
252b5132
RH		 9154
9155 globals = elf32_arm_hash_table (info);
252b5132
RH		 9156 BFD_ASSERT (globals != NULL);
9157 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9158
9159 my_offset = myh->root.u.def.value;
9160
3d4d4302
AM		 9161 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9162 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 9163
9164 BFD_ASSERT (s != NULL);
9165 BFD_ASSERT (s->contents != NULL);
9166 BFD_ASSERT (s->output_section != NULL);
9167
9168 if ((my_offset & 0x01) == 0x01)
9169 {
9170 if (sym_sec != NULL
9171 && sym_sec->owner != NULL
9172 && !INTERWORK_FLAG (sym_sec->owner))
9173 {
4eca0228 9174 _bfd_error_handler
90b6238f
AM		 9175 (_("%pB(%s): warning: interworking not enabled;"
9176 " first occurrence: %pB: %s call to %s"),
9177 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 9178
b34976b6 9179 return FALSE;
252b5132
RH		 9180 }
9181
9182 --my_offset;
9183 myh->root.u.def.value = my_offset;
9184
52ab56c2
PB		 9185 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9186 s->contents + my_offset);
252b5132 9187
52ab56c2
PB		 9188 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9189 s->contents + my_offset + 2);
252b5132
RH		 9190
9191 ret_offset =
9b485d32
NC		 9192 /* Address of destination of the stub. */
9193 ((bfd_signed_vma) val)
252b5132 9194 - ((bfd_signed_vma)
57e8b36a
NC		 9195 /* Offset from the start of the current section
9196 to the start of the stubs. */
9b485d32
NC		 9197 (s->output_offset
9198 /* Offset of the start of this stub from the start of the stubs. */
9199 + my_offset
9200 /* Address of the start of the current section. */
9201 + s->output_section->vma)
9202 /* The branch instruction is 4 bytes into the stub. */
9203 + 4
9204 /* ARM branches work from the pc of the instruction + 8. */
9205 + 8);
252b5132 9206
52ab56c2
PB		 9207 put_arm_insn (globals, output_bfd,
9208 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9209 s->contents + my_offset + 4);
252b5132
RH		 9210 }
9211
9212 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9213
427bfd90
NC		 9214 /* Now go back and fix up the original BL insn to point to here. */
9215 ret_offset =
9216 /* Address of where the stub is located. */
9217 (s->output_section->vma + s->output_offset + my_offset)
9218 /* Address of where the BL is located. */
57e8b36a
NC		 9219 - (input_section->output_section->vma + input_section->output_offset
9220 + offset)
427bfd90
NC		 9221 /* Addend in the relocation. */
9222 - addend
9223 /* Biassing for PC-relative addressing. */
9224 - 8;
252b5132 9225
12a0a0fd 9226 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 9227
b34976b6 9228 return TRUE;
252b5132
RH		 9229}
9230
a4fd1a8e 9231/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 9232
a4fd1a8e
PB		 9233static struct elf_link_hash_entry *
9234elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9235 const char * name,
9236 bfd * input_bfd,
9237 bfd * output_bfd,
9238 asection * sym_sec,
9239 bfd_vma val,
9240 asection * s,
9241 char ** error_message)
252b5132 9242{
dc810e39 9243 bfd_vma my_offset;
252b5132 9244 long int ret_offset;
bcbdc74c
NC		 9245 struct elf_link_hash_entry * myh;
9246 struct elf32_arm_link_hash_table * globals;
252b5132 9247
f2a9dd69 9248 myh = find_arm_glue (info, name, error_message);
252b5132 9249 if (myh == NULL)
a4fd1a8e 9250 return NULL;
252b5132
RH		 9251
9252 globals = elf32_arm_hash_table (info);
252b5132
RH		 9253 BFD_ASSERT (globals != NULL);
9254 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9255
9256 my_offset = myh->root.u.def.value;
252b5132
RH		 9257
9258 if ((my_offset & 0x01) == 0x01)
9259 {
9260 if (sym_sec != NULL
9261 && sym_sec->owner != NULL
9262 && !INTERWORK_FLAG (sym_sec->owner))
9263 {
4eca0228 9264 _bfd_error_handler
90b6238f
AM		 9265 (_("%pB(%s): warning: interworking not enabled;"
9266 " first occurrence: %pB: %s call to %s"),
9267 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 9268 }
9b485d32 9269
252b5132
RH		 9270 --my_offset;
9271 myh->root.u.def.value = my_offset;
9272
0e1862bb
L		 9273 if (bfd_link_pic (info)
9274 || globals->root.is_relocatable_executable
27e55c4d 9275 || globals->pic_veneer)
8f6277f5
PB		 9276 {
9277 /* For relocatable objects we can't use absolute addresses,
9278 so construct the address from a relative offset. */
9279 /* TODO: If the offset is small it's probably worth
9280 constructing the address with adds. */
52ab56c2
PB		 9281 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9282 s->contents + my_offset);
9283 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9284 s->contents + my_offset + 4);
9285 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9286 s->contents + my_offset + 8);
8f6277f5
PB		 9287 /* Adjust the offset by 4 for the position of the add,
9288 and 8 for the pipeline offset. */
9289 ret_offset = (val - (s->output_offset
9290 + s->output_section->vma
9291 + my_offset + 12))
9292 | 1;
9293 bfd_put_32 (output_bfd, ret_offset,
9294 s->contents + my_offset + 12);
9295 }
26079076
PB		 9296 else if (globals->use_blx)
9297 {
9298 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9299 s->contents + my_offset);
9300
9301 /* It's a thumb address. Add the low order bit. */
9302 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9303 s->contents + my_offset + 4);
9304 }
8f6277f5
PB		 9305 else
9306 {
52ab56c2
PB		 9307 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9308 s->contents + my_offset);
252b5132 9309
52ab56c2
PB		 9310 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9311 s->contents + my_offset + 4);
252b5132 9312
8f6277f5
PB		 9313 /* It's a thumb address. Add the low order bit. */
9314 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9315 s->contents + my_offset + 8);
8029a119
NC		 9316
9317 my_offset += 12;
8f6277f5 9318 }
252b5132
RH		 9319 }
9320
9321 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9322
a4fd1a8e
PB		 9323 return myh;
9324}
9325
9326/* Arm code calling a Thumb function. */
9327
9328static int
9329elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9330 const char * name,
9331 bfd * input_bfd,
9332 bfd * output_bfd,
9333 asection * input_section,
9334 bfd_byte * hit_data,
9335 asection * sym_sec,
9336 bfd_vma offset,
9337 bfd_signed_vma addend,
9338 bfd_vma val,
f2a9dd69 9339 char **error_message)
a4fd1a8e
PB		 9340{
9341 unsigned long int tmp;
9342 bfd_vma my_offset;
9343 asection * s;
9344 long int ret_offset;
9345 struct elf_link_hash_entry * myh;
9346 struct elf32_arm_link_hash_table * globals;
9347
9348 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9349 BFD_ASSERT (globals != NULL);
9350 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9351
3d4d4302
AM		 9352 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9353 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9354 BFD_ASSERT (s != NULL);
9355 BFD_ASSERT (s->contents != NULL);
9356 BFD_ASSERT (s->output_section != NULL);
9357
9358 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9359 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9360 if (!myh)
9361 return FALSE;
9362
9363 my_offset = myh->root.u.def.value;
252b5132
RH		 9364 tmp = bfd_get_32 (input_bfd, hit_data);
9365 tmp = tmp & 0xFF000000;
9366
9b485d32 9367 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9368 ret_offset = (s->output_offset
9369 + my_offset
9370 + s->output_section->vma
9371 - (input_section->output_offset
9372 + input_section->output_section->vma
9373 + offset + addend)
9374 - 8);
9a5aca8c 9375
252b5132
RH		 9376 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9377
dc810e39 9378 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9379
b34976b6 9380 return TRUE;
252b5132
RH		 9381}
9382
a4fd1a8e
PB		 9383/* Populate Arm stub for an exported Thumb function. */
9384
9385static bfd_boolean
9386elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9387{
9388 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9389 asection * s;
9390 struct elf_link_hash_entry * myh;
9391 struct elf32_arm_link_hash_entry *eh;
9392 struct elf32_arm_link_hash_table * globals;
9393 asection *sec;
9394 bfd_vma val;
f2a9dd69 9395 char *error_message;
a4fd1a8e 9396
906e58ca 9397 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9398 /* Allocate stubs for exported Thumb functions on v4t. */
9399 if (eh->export_glue == NULL)
9400 return TRUE;
9401
9402 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9403 BFD_ASSERT (globals != NULL);
9404 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9405
3d4d4302
AM		 9406 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9407 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9408 BFD_ASSERT (s != NULL);
9409 BFD_ASSERT (s->contents != NULL);
9410 BFD_ASSERT (s->output_section != NULL);
9411
9412 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9413
9414 BFD_ASSERT (sec->output_section != NULL);
9415
a4fd1a8e
PB		 9416 val = eh->export_glue->root.u.def.value + sec->output_offset
9417 + sec->output_section->vma;
8029a119 9418
a4fd1a8e
PB		 9419 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9420 h->root.u.def.section->owner,
f2a9dd69
DJ		 9421 globals->obfd, sec, val, s,
9422 &error_message);
a4fd1a8e
PB		 9423 BFD_ASSERT (myh);
9424 return TRUE;
9425}
9426
845b51d6
PB		 9427/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9428
9429static bfd_vma
9430elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9431{
9432 bfd_byte *p;
9433 bfd_vma glue_addr;
9434 asection *s;
9435 struct elf32_arm_link_hash_table *globals;
9436
9437 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9438 BFD_ASSERT (globals != NULL);
9439 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9440
3d4d4302
AM		 9441 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9442 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9443 BFD_ASSERT (s != NULL);
9444 BFD_ASSERT (s->contents != NULL);
9445 BFD_ASSERT (s->output_section != NULL);
9446
9447 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9448
9449 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9450
9451 if ((globals->bx_glue_offset[reg] & 1) == 0)
9452 {
9453 p = s->contents + glue_addr;
9454 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9455 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9456 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9457 globals->bx_glue_offset[reg] |= 1;
9458 }
9459
9460 return glue_addr + s->output_section->vma + s->output_offset;
9461}
9462
a4fd1a8e
PB		 9463/* Generate Arm stubs for exported Thumb symbols. */
9464static void
906e58ca 9465elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9466 struct bfd_link_info *link_info)
9467{
9468 struct elf32_arm_link_hash_table * globals;
9469
8029a119
NC		 9470 if (link_info == NULL)
9471 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9472 return;
9473
9474 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9475 if (globals == NULL)
9476 return;
9477
84c08195
PB		 9478 /* If blx is available then exported Thumb symbols are OK and there is
9479 nothing to do. */
a4fd1a8e
PB		 9480 if (globals->use_blx)
9481 return;
9482
9483 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9484 link_info);
9485}
9486
47beaa6a
RS		 9487/* Reserve space for COUNT dynamic relocations in relocation selection
9488 SRELOC. */
9489
9490static void
9491elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9492 bfd_size_type count)
9493{
9494 struct elf32_arm_link_hash_table *htab;
9495
9496 htab = elf32_arm_hash_table (info);
9497 BFD_ASSERT (htab->root.dynamic_sections_created);
9498 if (sreloc == NULL)
9499 abort ();
9500 sreloc->size += RELOC_SIZE (htab) * count;
9501}
9502
34e77a92
RS		 9503/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9504 dynamic, the relocations should go in SRELOC, otherwise they should
9505 go in the special .rel.iplt section. */
9506
9507static void
9508elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9509 bfd_size_type count)
9510{
9511 struct elf32_arm_link_hash_table *htab;
9512
9513 htab = elf32_arm_hash_table (info);
9514 if (!htab->root.dynamic_sections_created)
9515 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9516 else
9517 {
9518 BFD_ASSERT (sreloc != NULL);
9519 sreloc->size += RELOC_SIZE (htab) * count;
9520 }
9521}
9522
47beaa6a
RS		 9523/* Add relocation REL to the end of relocation section SRELOC. */
9524
9525static void
9526elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9527 asection *sreloc, Elf_Internal_Rela *rel)
9528{
9529 bfd_byte *loc;
9530 struct elf32_arm_link_hash_table *htab;
9531
9532 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9533 if (!htab->root.dynamic_sections_created
9534 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9535 sreloc = htab->root.irelplt;
47beaa6a
RS		 9536 if (sreloc == NULL)
9537 abort ();
9538 loc = sreloc->contents;
9539 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9540 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9541 abort ();
9542 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9543}
9544
34e77a92
RS		 9545/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9546 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9547 to .plt. */
9548
9549static void
9550elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9551 bfd_boolean is_iplt_entry,
9552 union gotplt_union *root_plt,
9553 struct arm_plt_info *arm_plt)
9554{
9555 struct elf32_arm_link_hash_table *htab;
9556 asection *splt;
9557 asection *sgotplt;
9558
9559 htab = elf32_arm_hash_table (info);
9560
9561 if (is_iplt_entry)
9562 {
9563 splt = htab->root.iplt;
9564 sgotplt = htab->root.igotplt;
9565
99059e56
RM		 9566 /* NaCl uses a special first entry in .iplt too. */
9567 if (htab->nacl_p && splt->size == 0)
9568 splt->size += htab->plt_header_size;
9569
34e77a92
RS		 9570 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9571 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9572 }
9573 else
9574 {
9575 splt = htab->root.splt;
9576 sgotplt = htab->root.sgotplt;
9577
7801f98f
CL		 9578 if (htab->fdpic_p)
9579 {
9580 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9581 /* For lazy binding, relocations will be put into .rel.plt, in
9582 .rel.got otherwise. */
9583 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9584 if (info->flags & DF_BIND_NOW)
9585 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9586 else
9587 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9588 }
9589 else
9590 {
9591 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9592 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9593 }
34e77a92
RS		 9594
9595 /* If this is the first .plt entry, make room for the special
9596 first entry. */
9597 if (splt->size == 0)
9598 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9599
9600 htab->next_tls_desc_index++;
34e77a92
RS		 9601 }
9602
9603 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9604 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9605 splt->size += PLT_THUMB_STUB_SIZE;
9606 root_plt->offset = splt->size;
9607 splt->size += htab->plt_entry_size;
9608
9609 if (!htab->symbian_p)
9610 {
9611 /* We also need to make an entry in the .got.plt section, which
9612 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9613 if (is_iplt_entry)
9614 arm_plt->got_offset = sgotplt->size;
9615 else
9616 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
7801f98f
CL		 9617 if (htab->fdpic_p)
9618 /* Function descriptor takes 64 bits in GOT. */
4b24dd1a 9619 sgotplt->size += 8;
7801f98f
CL		 9620 else
9621 sgotplt->size += 4;
34e77a92
RS		 9622 }
9623}
9624
b38cadfb
NC		 9625static bfd_vma
9626arm_movw_immediate (bfd_vma value)
9627{
9628 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9629}
9630
9631static bfd_vma
9632arm_movt_immediate (bfd_vma value)
9633{
9634 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9635}
9636
34e77a92
RS		 9637/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9638 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9639 Otherwise, DYNINDX is the index of the symbol in the dynamic
9640 symbol table and SYM_VALUE is undefined.
9641
9642 ROOT_PLT points to the offset of the PLT entry from the start of its
9643 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9644 bookkeeping information.
34e77a92 9645
57460bcf
NC		 9646 Returns FALSE if there was a problem. */
9647
9648static bfd_boolean
34e77a92
RS		 9649elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9650 union gotplt_union *root_plt,
9651 struct arm_plt_info *arm_plt,
9652 int dynindx, bfd_vma sym_value)
9653{
9654 struct elf32_arm_link_hash_table *htab;
9655 asection *sgot;
9656 asection *splt;
9657 asection *srel;
9658 bfd_byte *loc;
9659 bfd_vma plt_index;
9660 Elf_Internal_Rela rel;
9661 bfd_vma plt_header_size;
9662 bfd_vma got_header_size;
9663
9664 htab = elf32_arm_hash_table (info);
9665
9666 /* Pick the appropriate sections and sizes. */
9667 if (dynindx == -1)
9668 {
9669 splt = htab->root.iplt;
9670 sgot = htab->root.igotplt;
9671 srel = htab->root.irelplt;
9672
9673 /* There are no reserved entries in .igot.plt, and no special
9674 first entry in .iplt. */
9675 got_header_size = 0;
9676 plt_header_size = 0;
9677 }
9678 else
9679 {
9680 splt = htab->root.splt;
9681 sgot = htab->root.sgotplt;
9682 srel = htab->root.srelplt;
9683
9684 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9685 plt_header_size = htab->plt_header_size;
9686 }
9687 BFD_ASSERT (splt != NULL && srel != NULL);
9688
9689 /* Fill in the entry in the procedure linkage table. */
9690 if (htab->symbian_p)
9691 {
9692 BFD_ASSERT (dynindx >= 0);
9693 put_arm_insn (htab, output_bfd,
9694 elf32_arm_symbian_plt_entry[0],
9695 splt->contents + root_plt->offset);
9696 bfd_put_32 (output_bfd,
9697 elf32_arm_symbian_plt_entry[1],
9698 splt->contents + root_plt->offset + 4);
9699
9700 /* Fill in the entry in the .rel.plt section. */
9701 rel.r_offset = (splt->output_section->vma
9702 + splt->output_offset
9703 + root_plt->offset + 4);
9704 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9705
9706 /* Get the index in the procedure linkage table which
9707 corresponds to this symbol. This is the index of this symbol
9708 in all the symbols for which we are making plt entries. The
9709 first entry in the procedure linkage table is reserved. */
9710 plt_index = ((root_plt->offset - plt_header_size)
9711 / htab->plt_entry_size);
9712 }
9713 else
9714 {
9715 bfd_vma got_offset, got_address, plt_address;
9716 bfd_vma got_displacement, initial_got_entry;
9717 bfd_byte * ptr;
9718
9719 BFD_ASSERT (sgot != NULL);
9720
9721 /* Get the offset into the .(i)got.plt table of the entry that
9722 corresponds to this function. */
9723 got_offset = (arm_plt->got_offset & -2);
9724
9725 /* Get the index in the procedure linkage table which
9726 corresponds to this symbol. This is the index of this symbol
9727 in all the symbols for which we are making plt entries.
9728 After the reserved .got.plt entries, all symbols appear in
9729 the same order as in .plt. */
7801f98f 9730 if (htab->fdpic_p)
4b24dd1a
AM		 9731 /* Function descriptor takes 8 bytes. */
9732 plt_index = (got_offset - got_header_size) / 8;
7801f98f 9733 else
4b24dd1a 9734 plt_index = (got_offset - got_header_size) / 4;
34e77a92
RS		 9735
9736 /* Calculate the address of the GOT entry. */
9737 got_address = (sgot->output_section->vma
9738 + sgot->output_offset
9739 + got_offset);
9740
9741 /* ...and the address of the PLT entry. */
9742 plt_address = (splt->output_section->vma
9743 + splt->output_offset
9744 + root_plt->offset);
9745
9746 ptr = splt->contents + root_plt->offset;
0e1862bb 9747 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9748 {
9749 unsigned int i;
9750 bfd_vma val;
9751
9752 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9753 {
9754 val = elf32_arm_vxworks_shared_plt_entry[i];
9755 if (i == 2)
9756 val |= got_address - sgot->output_section->vma;
9757 if (i == 5)
9758 val |= plt_index * RELOC_SIZE (htab);
9759 if (i == 2 || i == 5)
9760 bfd_put_32 (output_bfd, val, ptr);
9761 else
9762 put_arm_insn (htab, output_bfd, val, ptr);
9763 }
9764 }
9765 else if (htab->vxworks_p)
9766 {
9767 unsigned int i;
9768 bfd_vma val;
9769
9770 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9771 {
9772 val = elf32_arm_vxworks_exec_plt_entry[i];
9773 if (i == 2)
9774 val |= got_address;
9775 if (i == 4)
9776 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9777 if (i == 5)
9778 val |= plt_index * RELOC_SIZE (htab);
9779 if (i == 2 || i == 5)
9780 bfd_put_32 (output_bfd, val, ptr);
9781 else
9782 put_arm_insn (htab, output_bfd, val, ptr);
9783 }
9784
9785 loc = (htab->srelplt2->contents
9786 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9787
9788 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9789 referencing the GOT for this PLT entry. */
9790 rel.r_offset = plt_address + 8;
9791 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9792 rel.r_addend = got_offset;
9793 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9794 loc += RELOC_SIZE (htab);
9795
9796 /* Create the R_ARM_ABS32 relocation referencing the
9797 beginning of the PLT for this GOT entry. */
9798 rel.r_offset = got_address;
9799 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9800 rel.r_addend = 0;
9801 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9802 }
b38cadfb
NC		 9803 else if (htab->nacl_p)
9804 {
9805 /* Calculate the displacement between the PLT slot and the
9806 common tail that's part of the special initial PLT slot. */
6034aab8 9807 int32_t tail_displacement
b38cadfb
NC		 9808 = ((splt->output_section->vma + splt->output_offset
9809 + ARM_NACL_PLT_TAIL_OFFSET)
9810 - (plt_address + htab->plt_entry_size + 4));
9811 BFD_ASSERT ((tail_displacement & 3) == 0);
9812 tail_displacement >>= 2;
9813
9814 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9815 || (-tail_displacement & 0xff000000) == 0);
9816
9817 /* Calculate the displacement between the PLT slot and the entry
9818 in the GOT. The offset accounts for the value produced by
9819 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9820 got_displacement = (got_address
99059e56 9821 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9822
9823 /* NaCl does not support interworking at all. */
9824 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9825
9826 put_arm_insn (htab, output_bfd,
9827 elf32_arm_nacl_plt_entry[0]
9828 | arm_movw_immediate (got_displacement),
9829 ptr + 0);
9830 put_arm_insn (htab, output_bfd,
9831 elf32_arm_nacl_plt_entry[1]
9832 | arm_movt_immediate (got_displacement),
9833 ptr + 4);
9834 put_arm_insn (htab, output_bfd,
9835 elf32_arm_nacl_plt_entry[2],
9836 ptr + 8);
9837 put_arm_insn (htab, output_bfd,
9838 elf32_arm_nacl_plt_entry[3]
9839 | (tail_displacement & 0x00ffffff),
9840 ptr + 12);
9841 }
7801f98f
CL		 9842 else if (htab->fdpic_p)
9843 {
59029f57
CL		 9844 const bfd_vma *plt_entry = using_thumb_only(htab)
9845 ? elf32_arm_fdpic_thumb_plt_entry
9846 : elf32_arm_fdpic_plt_entry;
9847
7801f98f
CL		 9848 /* Fill-up Thumb stub if needed. */
9849 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9850 {
9851 put_thumb_insn (htab, output_bfd,
9852 elf32_arm_plt_thumb_stub[0], ptr - 4);
9853 put_thumb_insn (htab, output_bfd,
9854 elf32_arm_plt_thumb_stub[1], ptr - 2);
9855 }
59029f57
CL		 9856 /* As we are using 32 bit instructions even for the Thumb
9857 version, we have to use 'put_arm_insn' instead of
9858 'put_thumb_insn'. */
9859 put_arm_insn(htab, output_bfd, plt_entry[0], ptr + 0);
9860 put_arm_insn(htab, output_bfd, plt_entry[1], ptr + 4);
9861 put_arm_insn(htab, output_bfd, plt_entry[2], ptr + 8);
9862 put_arm_insn(htab, output_bfd, plt_entry[3], ptr + 12);
7801f98f
CL		 9863 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9864
9865 if (!(info->flags & DF_BIND_NOW))
9866 {
9867 /* funcdesc_value_reloc_offset. */
9868 bfd_put_32 (output_bfd,
9869 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9870 ptr + 20);
59029f57
CL		 9871 put_arm_insn(htab, output_bfd, plt_entry[6], ptr + 24);
9872 put_arm_insn(htab, output_bfd, plt_entry[7], ptr + 28);
9873 put_arm_insn(htab, output_bfd, plt_entry[8], ptr + 32);
9874 put_arm_insn(htab, output_bfd, plt_entry[9], ptr + 36);
7801f98f
CL		 9875 }
9876 }
57460bcf
NC		 9877 else if (using_thumb_only (htab))
9878 {
eed94f8f 9879 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9880 if (!using_thumb2 (htab))
eed94f8f
NC		 9881 {
9882 /* FIXME: We ought to be able to generate thumb-1 PLT
9883 instructions... */
90b6238f 9884 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9885 output_bfd);
9886 return FALSE;
9887 }
57460bcf 9888
eed94f8f
NC		 9889 /* Calculate the displacement between the PLT slot and the entry in
9890 the GOT. The 12-byte offset accounts for the value produced by
9891 adding to pc in the 3rd instruction of the PLT stub. */
9892 got_displacement = got_address - (plt_address + 12);
9893
9894 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9895 instead of 'put_thumb_insn'. */
9896 put_arm_insn (htab, output_bfd,
9897 elf32_thumb2_plt_entry[0]
9898 | ((got_displacement & 0x000000ff) << 16)
9899 | ((got_displacement & 0x00000700) << 20)
9900 | ((got_displacement & 0x00000800) >> 1)
9901 | ((got_displacement & 0x0000f000) >> 12),
9902 ptr + 0);
9903 put_arm_insn (htab, output_bfd,
9904 elf32_thumb2_plt_entry[1]
9905 | ((got_displacement & 0x00ff0000) )
9906 | ((got_displacement & 0x07000000) << 4)
9907 | ((got_displacement & 0x08000000) >> 17)
9908 | ((got_displacement & 0xf0000000) >> 28),
9909 ptr + 4);
9910 put_arm_insn (htab, output_bfd,
9911 elf32_thumb2_plt_entry[2],
9912 ptr + 8);
9913 put_arm_insn (htab, output_bfd,
9914 elf32_thumb2_plt_entry[3],
9915 ptr + 12);
57460bcf 9916 }
34e77a92
RS		 9917 else
9918 {
9919 /* Calculate the displacement between the PLT slot and the
9920 entry in the GOT. The eight-byte offset accounts for the
9921 value produced by adding to pc in the first instruction
9922 of the PLT stub. */
9923 got_displacement = got_address - (plt_address + 8);
9924
34e77a92
RS		 9925 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9926 {
9927 put_thumb_insn (htab, output_bfd,
9928 elf32_arm_plt_thumb_stub[0], ptr - 4);
9929 put_thumb_insn (htab, output_bfd,
9930 elf32_arm_plt_thumb_stub[1], ptr - 2);
9931 }
9932
1db37fe6
YG		 9933 if (!elf32_arm_use_long_plt_entry)
9934 {
9935 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9936
9937 put_arm_insn (htab, output_bfd,
9938 elf32_arm_plt_entry_short[0]
9939 | ((got_displacement & 0x0ff00000) >> 20),
9940 ptr + 0);
9941 put_arm_insn (htab, output_bfd,
9942 elf32_arm_plt_entry_short[1]
9943 | ((got_displacement & 0x000ff000) >> 12),
9944 ptr+ 4);
9945 put_arm_insn (htab, output_bfd,
9946 elf32_arm_plt_entry_short[2]
9947 | (got_displacement & 0x00000fff),
9948 ptr + 8);
34e77a92 9949#ifdef FOUR_WORD_PLT
1db37fe6 9950 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9951#endif
1db37fe6
YG		 9952 }
9953 else
9954 {
9955 put_arm_insn (htab, output_bfd,
9956 elf32_arm_plt_entry_long[0]
9957 | ((got_displacement & 0xf0000000) >> 28),
9958 ptr + 0);
9959 put_arm_insn (htab, output_bfd,
9960 elf32_arm_plt_entry_long[1]
9961 | ((got_displacement & 0x0ff00000) >> 20),
9962 ptr + 4);
9963 put_arm_insn (htab, output_bfd,
9964 elf32_arm_plt_entry_long[2]
9965 | ((got_displacement & 0x000ff000) >> 12),
9966 ptr+ 8);
9967 put_arm_insn (htab, output_bfd,
9968 elf32_arm_plt_entry_long[3]
9969 | (got_displacement & 0x00000fff),
9970 ptr + 12);
9971 }
34e77a92
RS		 9972 }
9973
9974 /* Fill in the entry in the .rel(a).(i)plt section. */
9975 rel.r_offset = got_address;
9976 rel.r_addend = 0;
9977 if (dynindx == -1)
9978 {
9979 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9980 The dynamic linker or static executable then calls SYM_VALUE
9981 to determine the correct run-time value of the .igot.plt entry. */
9982 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9983 initial_got_entry = sym_value;
9984 }
9985 else
9986 {
7801f98f
CL		 9987 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9988 used by PLT entry. */
9989 if (htab->fdpic_p)
9990 {
9991 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
9992 initial_got_entry = 0;
9993 }
9994 else
9995 {
9996 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9997 initial_got_entry = (splt->output_section->vma
9998 + splt->output_offset);
9999 }
34e77a92
RS		 10000 }
10001
10002 /* Fill in the entry in the global offset table. */
10003 bfd_put_32 (output_bfd, initial_got_entry,
10004 sgot->contents + got_offset);
7801f98f
CL		 10005
10006 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
10007 {
10008 /* Setup initial funcdesc value. */
10009 /* FIXME: we don't support lazy binding because there is a
10010 race condition between both words getting written and
10011 some other thread attempting to read them. The ARM
10012 architecture does not have an atomic 64 bit load/store
10013 instruction that could be used to prevent it; it is
10014 recommended that threaded FDPIC applications run with the
10015 LD_BIND_NOW environment variable set. */
10016 bfd_put_32(output_bfd, plt_address + 0x18,
10017 sgot->contents + got_offset);
10018 bfd_put_32(output_bfd, -1 /*TODO*/,
10019 sgot->contents + got_offset + 4);
10020 }
34e77a92
RS		 10021 }
10022
aba8c3de
WN		 10023 if (dynindx == -1)
10024 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
10025 else
10026 {
7801f98f
CL		 10027 if (htab->fdpic_p)
10028 {
10029 /* For FDPIC we put PLT relocationss into .rel.got when not
10030 lazy binding otherwise we put them in .rel.plt. For now,
10031 we don't support lazy binding so put it in .rel.got. */
10032 if (info->flags & DF_BIND_NOW)
10033 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelgot, &rel);
10034 else
10035 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelplt, &rel);
10036 }
10037 else
10038 {
10039 loc = srel->contents + plt_index * RELOC_SIZE (htab);
10040 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
10041 }
aba8c3de 10042 }
57460bcf
NC		 10043
10044 return TRUE;
34e77a92
RS		 10045}
10046
eb043451
PB		 10047/* Some relocations map to different relocations depending on the
10048 target. Return the real relocation. */
8029a119 10049
eb043451
PB		 10050static int
10051arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
10052 int r_type)
10053{
10054 switch (r_type)
10055 {
10056 case R_ARM_TARGET1:
10057 if (globals->target1_is_rel)
10058 return R_ARM_REL32;
10059 else
10060 return R_ARM_ABS32;
10061
10062 case R_ARM_TARGET2:
10063 return globals->target2_reloc;
10064
10065 default:
10066 return r_type;
10067 }
10068}
eb043451 10069
ba93b8ac
DJ		 10070/* Return the base VMA address which should be subtracted from real addresses
10071 when resolving @dtpoff relocation.
10072 This is PT_TLS segment p_vaddr. */
10073
10074static bfd_vma
10075dtpoff_base (struct bfd_link_info *info)
10076{
10077 /* If tls_sec is NULL, we should have signalled an error already. */
10078 if (elf_hash_table (info)->tls_sec == NULL)
10079 return 0;
10080 return elf_hash_table (info)->tls_sec->vma;
10081}
10082
10083/* Return the relocation value for @tpoff relocation
10084 if STT_TLS virtual address is ADDRESS. */
10085
10086static bfd_vma
10087tpoff (struct bfd_link_info *info, bfd_vma address)
10088{
10089 struct elf_link_hash_table *htab = elf_hash_table (info);
10090 bfd_vma base;
10091
10092 /* If tls_sec is NULL, we should have signalled an error already. */
10093 if (htab->tls_sec == NULL)
10094 return 0;
10095 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
10096 return address - htab->tls_sec->vma + base;
10097}
10098
00a97672
RS		 10099/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10100 VALUE is the relocation value. */
10101
10102static bfd_reloc_status_type
10103elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
10104{
10105 if (value > 0xfff)
10106 return bfd_reloc_overflow;
10107
10108 value |= bfd_get_32 (abfd, data) & 0xfffff000;
10109 bfd_put_32 (abfd, value, data);
10110 return bfd_reloc_ok;
10111}
10112
0855e32b
NS		 10113/* Handle TLS relaxations. Relaxing is possible for symbols that use
10114 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10115 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10116
10117 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10118 is to then call final_link_relocate. Return other values in the
62672b10
NS		 10119 case of error.
10120
10121 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10122 the pre-relaxed code. It would be nice if the relocs were updated
10123 to match the optimization. */
0855e32b 10124
b38cadfb 10125static bfd_reloc_status_type
0855e32b 10126elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 10127 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 10128 Elf_Internal_Rela *rel, unsigned long is_local)
10129{
10130 unsigned long insn;
b38cadfb 10131
0855e32b
NS		 10132 switch (ELF32_R_TYPE (rel->r_info))
10133 {
10134 default:
10135 return bfd_reloc_notsupported;
b38cadfb 10136
0855e32b
NS		 10137 case R_ARM_TLS_GOTDESC:
10138 if (is_local)
10139 insn = 0;
10140 else
10141 {
10142 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10143 if (insn & 1)
10144 insn -= 5; /* THUMB */
10145 else
10146 insn -= 8; /* ARM */
10147 }
10148 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10149 return bfd_reloc_continue;
10150
10151 case R_ARM_THM_TLS_DESCSEQ:
10152 /* Thumb insn. */
10153 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10154 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10155 {
10156 if (is_local)
10157 /* nop */
10158 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10159 }
10160 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10161 {
10162 if (is_local)
10163 /* nop */
10164 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10165 else
10166 /* ldr rx,[ry] */
10167 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10168 }
10169 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10170 {
10171 if (is_local)
10172 /* nop */
10173 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10174 else
10175 /* mov r0, rx */
10176 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10177 contents + rel->r_offset);
10178 }
10179 else
10180 {
10181 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10182 /* It's a 32 bit instruction, fetch the rest of it for
10183 error generation. */
10184 insn = (insn << 16)
10185 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 10186 _bfd_error_handler
695344c0 10187 /* xgettext:c-format */
2dcf00ce 10188 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10189 "unexpected %s instruction '%#lx' in TLS trampoline"),
10190 input_bfd, input_sec, (uint64_t) rel->r_offset,
10191 "Thumb", insn);
0855e32b
NS		 10192 return bfd_reloc_notsupported;
10193 }
10194 break;
b38cadfb 10195
0855e32b
NS		 10196 case R_ARM_TLS_DESCSEQ:
10197 /* arm insn. */
10198 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10199 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10200 {
10201 if (is_local)
10202 /* mov rx, ry */
10203 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10204 contents + rel->r_offset);
10205 }
10206 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10207 {
10208 if (is_local)
10209 /* nop */
10210 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10211 else
10212 /* ldr rx,[ry] */
10213 bfd_put_32 (input_bfd, insn & 0xfffff000,
10214 contents + rel->r_offset);
10215 }
10216 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10217 {
10218 if (is_local)
10219 /* nop */
10220 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10221 else
10222 /* mov r0, rx */
10223 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10224 contents + rel->r_offset);
10225 }
10226 else
10227 {
4eca0228 10228 _bfd_error_handler
695344c0 10229 /* xgettext:c-format */
2dcf00ce 10230 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10231 "unexpected %s instruction '%#lx' in TLS trampoline"),
10232 input_bfd, input_sec, (uint64_t) rel->r_offset,
10233 "ARM", insn);
0855e32b
NS		 10234 return bfd_reloc_notsupported;
10235 }
10236 break;
10237
10238 case R_ARM_TLS_CALL:
10239 /* GD->IE relaxation, turn the instruction into 'nop' or
10240 'ldr r0, [pc,r0]' */
10241 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10242 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10243 break;
b38cadfb 10244
0855e32b 10245 case R_ARM_THM_TLS_CALL:
6a631e86 10246 /* GD->IE relaxation. */
0855e32b
NS		 10247 if (!is_local)
10248 /* add r0,pc; ldr r0, [r0] */
10249 insn = 0x44786800;
60a019a0 10250 else if (using_thumb2 (globals))
0855e32b
NS		 10251 /* nop.w */
10252 insn = 0xf3af8000;
10253 else
10254 /* nop; nop */
10255 insn = 0xbf00bf00;
b38cadfb 10256
0855e32b
NS		 10257 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10258 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10259 break;
10260 }
10261 return bfd_reloc_ok;
10262}
10263
4962c51a
MS		 10264/* For a given value of n, calculate the value of G_n as required to
10265 deal with group relocations. We return it in the form of an
10266 encoded constant-and-rotation, together with the final residual. If n is
10267 specified as less than zero, then final_residual is filled with the
10268 input value and no further action is performed. */
10269
10270static bfd_vma
10271calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10272{
10273 int current_n;
10274 bfd_vma g_n;
10275 bfd_vma encoded_g_n = 0;
10276 bfd_vma residual = value; /* Also known as Y_n. */
10277
10278 for (current_n = 0; current_n <= n; current_n++)
10279 {
10280 int shift;
10281
10282 /* Calculate which part of the value to mask. */
10283 if (residual == 0)
99059e56 10284 shift = 0;
4962c51a 10285 else
99059e56
RM		 10286 {
10287 int msb;
10288
10289 /* Determine the most significant bit in the residual and
10290 align the resulting value to a 2-bit boundary. */
10291 for (msb = 30; msb >= 0; msb -= 2)
10292 if (residual & (3 << msb))
10293 break;
10294
10295 /* The desired shift is now (msb - 6), or zero, whichever
10296 is the greater. */
10297 shift = msb - 6;
10298 if (shift < 0)
10299 shift = 0;
10300 }
4962c51a
MS		 10301
10302 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10303 g_n = residual & (0xff << shift);
10304 encoded_g_n = (g_n >> shift)
99059e56 10305 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 10306
10307 /* Calculate the residual for the next time around. */
10308 residual &= ~g_n;
10309 }
10310
10311 *final_residual = residual;
10312
10313 return encoded_g_n;
10314}
10315
10316/* Given an ARM instruction, determine whether it is an ADD or a SUB.
10317 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 10318
4962c51a 10319static int
906e58ca 10320identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 10321{
10322 int opcode = insn & 0x1e00000;
10323
10324 if (opcode == 1 << 23) /* ADD */
10325 return 1;
10326
10327 if (opcode == 1 << 22) /* SUB */
10328 return -1;
10329
10330 return 0;
10331}
10332
252b5132 10333/* Perform a relocation as part of a final link. */
9b485d32 10334
252b5132 10335static bfd_reloc_status_type
07d6d2b8
AM		 10336elf32_arm_final_link_relocate (reloc_howto_type * howto,
10337 bfd * input_bfd,
10338 bfd * output_bfd,
10339 asection * input_section,
10340 bfd_byte * contents,
10341 Elf_Internal_Rela * rel,
10342 bfd_vma value,
10343 struct bfd_link_info * info,
10344 asection * sym_sec,
10345 const char * sym_name,
10346 unsigned char st_type,
10347 enum arm_st_branch_type branch_type,
0945cdfd 10348 struct elf_link_hash_entry * h,
07d6d2b8
AM		 10349 bfd_boolean * unresolved_reloc_p,
10350 char ** error_message)
10351{
10352 unsigned long r_type = howto->type;
10353 unsigned long r_symndx;
10354 bfd_byte * hit_data = contents + rel->r_offset;
10355 bfd_vma * local_got_offsets;
10356 bfd_vma * local_tlsdesc_gotents;
10357 asection * sgot;
10358 asection * splt;
10359 asection * sreloc = NULL;
10360 asection * srelgot;
10361 bfd_vma addend;
10362 bfd_signed_vma signed_addend;
10363 unsigned char dynreloc_st_type;
10364 bfd_vma dynreloc_value;
ba96a88f 10365 struct elf32_arm_link_hash_table * globals;
34e77a92 10366 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 10367 union gotplt_union *root_plt;
10368 struct arm_plt_info *arm_plt;
10369 bfd_vma plt_offset;
10370 bfd_vma gotplt_offset;
10371 bfd_boolean has_iplt_entry;
10372 bfd_boolean resolved_to_zero;
f21f3fe0 10373
9c504268 10374 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 10375 if (globals == NULL)
10376 return bfd_reloc_notsupported;
9c504268 10377
0ffa91dd 10378 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 10379 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 10380
10381 /* Some relocation types map to different relocations depending on the
9c504268 10382 target. We pick the right one here. */
eb043451 10383 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 10384
10385 /* It is possible to have linker relaxations on some TLS access
10386 models. Update our information here. */
10387 r_type = elf32_arm_tls_transition (info, r_type, h);
10388
eb043451
PB		 10389 if (r_type != howto->type)
10390 howto = elf32_arm_howto_from_type (r_type);
9c504268 10391
34e77a92 10392 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 10393 sgot = globals->root.sgot;
252b5132 10394 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 10395 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10396
34e77a92
RS		 10397 if (globals->root.dynamic_sections_created)
10398 srelgot = globals->root.srelgot;
10399 else
10400 srelgot = NULL;
10401
252b5132
RH		 10402 r_symndx = ELF32_R_SYM (rel->r_info);
10403
4e7fd91e 10404 if (globals->use_rel)
ba96a88f 10405 {
4e7fd91e
PB		 10406 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
10407
10408 if (addend & ((howto->src_mask + 1) >> 1))
10409 {
10410 signed_addend = -1;
10411 signed_addend &= ~ howto->src_mask;
10412 signed_addend |= addend;
10413 }
10414 else
10415 signed_addend = addend;
ba96a88f
NC		 10416 }
10417 else
4e7fd91e 10418 addend = signed_addend = rel->r_addend;
f21f3fe0 10419
39f21624
NC		 10420 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10421 are resolving a function call relocation. */
10422 if (using_thumb_only (globals)
10423 && (r_type == R_ARM_THM_CALL
10424 || r_type == R_ARM_THM_JUMP24)
10425 && branch_type == ST_BRANCH_TO_ARM)
10426 branch_type = ST_BRANCH_TO_THUMB;
10427
34e77a92
RS		 10428 /* Record the symbol information that should be used in dynamic
10429 relocations. */
10430 dynreloc_st_type = st_type;
10431 dynreloc_value = value;
10432 if (branch_type == ST_BRANCH_TO_THUMB)
10433 dynreloc_value |= 1;
10434
10435 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10436 VALUE appropriately for relocations that we resolve at link time. */
10437 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10438 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10439 &arm_plt)
34e77a92
RS		 10440 && root_plt->offset != (bfd_vma) -1)
10441 {
10442 plt_offset = root_plt->offset;
10443 gotplt_offset = arm_plt->got_offset;
10444
10445 if (h == NULL || eh->is_iplt)
10446 {
10447 has_iplt_entry = TRUE;
10448 splt = globals->root.iplt;
10449
10450 /* Populate .iplt entries here, because not all of them will
10451 be seen by finish_dynamic_symbol. The lower bit is set if
10452 we have already populated the entry. */
10453 if (plt_offset & 1)
10454 plt_offset--;
10455 else
10456 {
57460bcf
NC		 10457 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10458 -1, dynreloc_value))
10459 root_plt->offset |= 1;
10460 else
10461 return bfd_reloc_notsupported;
34e77a92
RS		 10462 }
10463
10464 /* Static relocations always resolve to the .iplt entry. */
10465 st_type = STT_FUNC;
10466 value = (splt->output_section->vma
10467 + splt->output_offset
10468 + plt_offset);
10469 branch_type = ST_BRANCH_TO_ARM;
10470
10471 /* If there are non-call relocations that resolve to the .iplt
10472 entry, then all dynamic ones must too. */
10473 if (arm_plt->noncall_refcount != 0)
10474 {
10475 dynreloc_st_type = st_type;
10476 dynreloc_value = value;
10477 }
10478 }
10479 else
10480 /* We populate the .plt entry in finish_dynamic_symbol. */
10481 splt = globals->root.splt;
10482 }
10483 else
10484 {
10485 splt = NULL;
10486 plt_offset = (bfd_vma) -1;
10487 gotplt_offset = (bfd_vma) -1;
10488 }
10489
95b03e4a
L		 10490 resolved_to_zero = (h != NULL
10491 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10492
252b5132
RH		 10493 switch (r_type)
10494 {
10495 case R_ARM_NONE:
28a094c2
DJ		 10496 /* We don't need to find a value for this symbol. It's just a
10497 marker. */
10498 *unresolved_reloc_p = FALSE;
252b5132
RH		 10499 return bfd_reloc_ok;
10500
00a97672
RS		 10501 case R_ARM_ABS12:
10502 if (!globals->vxworks_p)
10503 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10504 /* Fall through. */
00a97672 10505
252b5132
RH		 10506 case R_ARM_PC24:
10507 case R_ARM_ABS32:
bb224fc3 10508 case R_ARM_ABS32_NOI:
252b5132 10509 case R_ARM_REL32:
bb224fc3 10510 case R_ARM_REL32_NOI:
5b5bb741
PB		 10511 case R_ARM_CALL:
10512 case R_ARM_JUMP24:
dfc5f959 10513 case R_ARM_XPC25:
eb043451 10514 case R_ARM_PREL31:
7359ea65 10515 case R_ARM_PLT32:
7359ea65
DJ		 10516 /* Handle relocations which should use the PLT entry. ABS32/REL32
10517 will use the symbol's value, which may point to a PLT entry, but we
10518 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10519 branches in this object should go to it, except if the PLT is too
10520 far away, in which case a long branch stub should be inserted. */
bb224fc3 10521 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10522 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10523 && r_type != R_ARM_CALL
10524 && r_type != R_ARM_JUMP24
10525 && r_type != R_ARM_PLT32)
34e77a92 10526 && plt_offset != (bfd_vma) -1)
7359ea65 10527 {
34e77a92
RS		 10528 /* If we've created a .plt section, and assigned a PLT entry
10529 to this function, it must either be a STT_GNU_IFUNC reference
10530 or not be known to bind locally. In other cases, we should
10531 have cleared the PLT entry by now. */
10532 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10533
10534 value = (splt->output_section->vma
10535 + splt->output_offset
34e77a92 10536 + plt_offset);
0945cdfd 10537 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10538 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10539 contents, rel->r_offset, value,
00a97672 10540 rel->r_addend);
7359ea65
DJ		 10541 }
10542
67687978
PB		 10543 /* When generating a shared object or relocatable executable, these
10544 relocations are copied into the output file to be resolved at
10545 run time. */
0e1862bb 10546 if ((bfd_link_pic (info)
e8b09b87
CL		 10547 || globals->root.is_relocatable_executable
10548 || globals->fdpic_p)
7359ea65 10549 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10550 && !(globals->vxworks_p
3348747a
NS		 10551 && strcmp (input_section->output_section->name,
10552 ".tls_vars") == 0)
bb224fc3 10553 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10554 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10555 && !(input_bfd == globals->stub_bfd
10556 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10557 && (h == NULL
95b03e4a
L		 10558 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10559 && !resolved_to_zero)
7359ea65
DJ		 10560 || h->root.type != bfd_link_hash_undefweak)
10561 && r_type != R_ARM_PC24
5b5bb741
PB		 10562 && r_type != R_ARM_CALL
10563 && r_type != R_ARM_JUMP24
ee06dc07 10564 && r_type != R_ARM_PREL31
7359ea65 10565 && r_type != R_ARM_PLT32)
252b5132 10566 {
947216bf 10567 Elf_Internal_Rela outrel;
b34976b6 10568 bfd_boolean skip, relocate;
e8b09b87 10569 int isrofixup = 0;
f21f3fe0 10570
52db4ec2
JW		 10571 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10572 && !h->def_regular)
10573 {
10574 char *v = _("shared object");
10575
0e1862bb 10576 if (bfd_link_executable (info))
52db4ec2
JW		 10577 v = _("PIE executable");
10578
4eca0228 10579 _bfd_error_handler
871b3ab2 10580 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10581 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10582 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10583 return bfd_reloc_notsupported;
10584 }
10585
0945cdfd
DJ		 10586 *unresolved_reloc_p = FALSE;
10587
34e77a92 10588 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10589 {
83bac4b0
NC		 10590 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10591 ! globals->use_rel);
f21f3fe0 10592
83bac4b0 10593 if (sreloc == NULL)
252b5132 10594 return bfd_reloc_notsupported;
252b5132 10595 }
f21f3fe0 10596
b34976b6
AM		 10597 skip = FALSE;
10598 relocate = FALSE;
f21f3fe0 10599
00a97672 10600 outrel.r_addend = addend;
c629eae0
JJ		 10601 outrel.r_offset =
10602 _bfd_elf_section_offset (output_bfd, info, input_section,
10603 rel->r_offset);
10604 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10605 skip = TRUE;
0bb2d96a 10606 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10607 skip = TRUE, relocate = TRUE;
252b5132
RH		 10608 outrel.r_offset += (input_section->output_section->vma
10609 + input_section->output_offset);
f21f3fe0 10610
252b5132 10611 if (skip)
0bb2d96a 10612 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10613 else if (h != NULL
10614 && h->dynindx != -1
0e1862bb 10615 && (!bfd_link_pic (info)
1dcb9720
JW		 10616 || !(bfd_link_pie (info)
10617 || SYMBOLIC_BIND (info, h))
f5385ebf 10618 || !h->def_regular))
5e681ec4 10619 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10620 else
10621 {
a16385dc
MM		 10622 int symbol;
10623
5e681ec4 10624 /* This symbol is local, or marked to become local. */
e8b09b87
CL		 10625 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10626 || (globals->fdpic_p && !bfd_link_pic(info)));
a16385dc 10627 if (globals->symbian_p)
6366ff1e 10628 {
74541ad4
AM		 10629 asection *osec;
10630
6366ff1e
MM		 10631 /* On Symbian OS, the data segment and text segement
10632 can be relocated independently. Therefore, we
10633 must indicate the segment to which this
10634 relocation is relative. The BPABI allows us to
10635 use any symbol in the right segment; we just use
10636 the section symbol as it is convenient. (We
10637 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10638 will not appear in the dynamic symbol table.)
10639
10640 Note that the dynamic linker ignores the section
10641 symbol value, so we don't subtract osec->vma
10642 from the emitted reloc addend. */
10dbd1f3 10643 if (sym_sec)
74541ad4 10644 osec = sym_sec->output_section;
10dbd1f3 10645 else
74541ad4
AM		 10646 osec = input_section->output_section;
10647 symbol = elf_section_data (osec)->dynindx;
10648 if (symbol == 0)
10649 {
10650 struct elf_link_hash_table *htab = elf_hash_table (info);
10651
10652 if ((osec->flags & SEC_READONLY) == 0
10653 && htab->data_index_section != NULL)
10654 osec = htab->data_index_section;
10655 else
10656 osec = htab->text_index_section;
10657 symbol = elf_section_data (osec)->dynindx;
10658 }
6366ff1e
MM		 10659 BFD_ASSERT (symbol != 0);
10660 }
a16385dc
MM		 10661 else
10662 /* On SVR4-ish systems, the dynamic loader cannot
10663 relocate the text and data segments independently,
10664 so the symbol does not matter. */
10665 symbol = 0;
34e77a92
RS		 10666 if (dynreloc_st_type == STT_GNU_IFUNC)
10667 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10668 to the .iplt entry. Instead, every non-call reference
10669 must use an R_ARM_IRELATIVE relocation to obtain the
10670 correct run-time address. */
10671 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
e8b09b87
CL		 10672 else if (globals->fdpic_p && !bfd_link_pic(info))
10673 isrofixup = 1;
34e77a92
RS		 10674 else
10675 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10676 if (globals->use_rel)
10677 relocate = TRUE;
10678 else
34e77a92 10679 outrel.r_addend += dynreloc_value;
252b5132 10680 }
f21f3fe0 10681
e8b09b87
CL		 10682 if (isrofixup)
10683 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
10684 else
10685 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10686
f21f3fe0 10687 /* If this reloc is against an external symbol, we do not want to
252b5132 10688 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10689 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10690 if (! relocate)
10691 return bfd_reloc_ok;
9a5aca8c 10692
f21f3fe0 10693 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10694 contents, rel->r_offset,
10695 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10696 }
10697 else switch (r_type)
10698 {
00a97672
RS		 10699 case R_ARM_ABS12:
10700 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10701
dfc5f959 10702 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10703 case R_ARM_CALL:
10704 case R_ARM_JUMP24:
8029a119 10705 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10706 case R_ARM_PLT32:
906e58ca 10707 {
906e58ca
NC		 10708 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10709
dfc5f959 10710 if (r_type == R_ARM_XPC25)
252b5132 10711 {
dfc5f959
NC		 10712 /* Check for Arm calling Arm function. */
10713 /* FIXME: Should we translate the instruction into a BL
10714 instruction instead ? */
35fc36a8 10715 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10716 _bfd_error_handler
90b6238f
AM		 10717 (_("\%pB: warning: %s BLX instruction targets"
10718 " %s function '%s'"),
10719 input_bfd, "ARM",
10720 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10721 }
155d87d7 10722 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10723 {
10724 /* Check for Arm calling Thumb function. */
35fc36a8 10725 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10726 {
f2a9dd69
DJ		 10727 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10728 output_bfd, input_section,
10729 hit_data, sym_sec, rel->r_offset,
10730 signed_addend, value,
10731 error_message))
10732 return bfd_reloc_ok;
10733 else
10734 return bfd_reloc_dangerous;
dfc5f959 10735 }
252b5132 10736 }
ba96a88f 10737
906e58ca 10738 /* Check if a stub has to be inserted because the
8029a119 10739 destination is too far or we are changing mode. */
155d87d7
CL		 10740 if ( r_type == R_ARM_CALL
10741 || r_type == R_ARM_JUMP24
10742 || r_type == R_ARM_PLT32)
906e58ca 10743 {
fe33d2fa
CL		 10744 enum elf32_arm_stub_type stub_type = arm_stub_none;
10745 struct elf32_arm_link_hash_entry *hash;
10746
10747 hash = (struct elf32_arm_link_hash_entry *) h;
10748 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10749 st_type, &branch_type,
10750 hash, value, sym_sec,
fe33d2fa 10751 input_bfd, sym_name);
5fa9e92f 10752
fe33d2fa 10753 if (stub_type != arm_stub_none)
906e58ca
NC		 10754 {
10755 /* The target is out of reach, so redirect the
10756 branch to the local stub for this function. */
906e58ca
NC		 10757 stub_entry = elf32_arm_get_stub_entry (input_section,
10758 sym_sec, h,
fe33d2fa
CL		 10759 rel, globals,
10760 stub_type);
9cd3e4e5
NC		 10761 {
10762 if (stub_entry != NULL)
10763 value = (stub_entry->stub_offset
10764 + stub_entry->stub_sec->output_offset
10765 + stub_entry->stub_sec->output_section->vma);
10766
10767 if (plt_offset != (bfd_vma) -1)
10768 *unresolved_reloc_p = FALSE;
10769 }
906e58ca 10770 }
fe33d2fa
CL		 10771 else
10772 {
10773 /* If the call goes through a PLT entry, make sure to
10774 check distance to the right destination address. */
34e77a92 10775 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10776 {
10777 value = (splt->output_section->vma
10778 + splt->output_offset
34e77a92 10779 + plt_offset);
fe33d2fa
CL		 10780 *unresolved_reloc_p = FALSE;
10781 /* The PLT entry is in ARM mode, regardless of the
10782 target function. */
35fc36a8 10783 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10784 }
10785 }
906e58ca
NC		 10786 }
10787
dea514f5
PB		 10788 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10789 where:
10790 S is the address of the symbol in the relocation.
10791 P is address of the instruction being relocated.
10792 A is the addend (extracted from the instruction) in bytes.
10793
10794 S is held in 'value'.
10795 P is the base address of the section containing the
10796 instruction plus the offset of the reloc into that
10797 section, ie:
10798 (input_section->output_section->vma +
10799 input_section->output_offset +
10800 rel->r_offset).
10801 A is the addend, converted into bytes, ie:
10802 (signed_addend * 4)
10803
10804 Note: None of these operations have knowledge of the pipeline
10805 size of the processor, thus it is up to the assembler to
10806 encode this information into the addend. */
10807 value -= (input_section->output_section->vma
10808 + input_section->output_offset);
10809 value -= rel->r_offset;
4e7fd91e
PB		 10810 if (globals->use_rel)
10811 value += (signed_addend << howto->size);
10812 else
10813 /* RELA addends do not have to be adjusted by howto->size. */
10814 value += signed_addend;
23080146 10815
dcb5e6e6
NC		 10816 signed_addend = value;
10817 signed_addend >>= howto->rightshift;
9a5aca8c 10818
5ab79981 10819 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10820 the next instruction unless a PLT entry will be created.
77b4f08f 10821 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10822 The jump to the next instruction is optimized as a NOP depending
10823 on the architecture. */
ffcb4889 10824 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10825 && plt_offset == (bfd_vma) -1)
77b4f08f 10826 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10827 {
cd1dac3d
DG		 10828 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10829
10830 if (arch_has_arm_nop (globals))
10831 value |= 0x0320f000;
10832 else
10833 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10834 }
10835 else
59f2c4e7 10836 {
9b485d32 10837 /* Perform a signed range check. */
dcb5e6e6 10838 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10839 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10840 return bfd_reloc_overflow;
9a5aca8c 10841
5ab79981 10842 addend = (value & 2);
39b41c9c 10843
5ab79981
PB		 10844 value = (signed_addend & howto->dst_mask)
10845 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10846
5ab79981
PB		 10847 if (r_type == R_ARM_CALL)
10848 {
155d87d7 10849 /* Set the H bit in the BLX instruction. */
35fc36a8 10850 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10851 {
10852 if (addend)
10853 value |= (1 << 24);
10854 else
10855 value &= ~(bfd_vma)(1 << 24);
10856 }
10857
5ab79981 10858 /* Select the correct instruction (BL or BLX). */
906e58ca 10859 /* Only if we are not handling a BL to a stub. In this
8029a119 10860 case, mode switching is performed by the stub. */
35fc36a8 10861 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10862 value |= (1 << 28);
63e1a0fc 10863 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10864 {
10865 value &= ~(bfd_vma)(1 << 28);
10866 value |= (1 << 24);
10867 }
39b41c9c
PB		 10868 }
10869 }
906e58ca 10870 }
252b5132 10871 break;
f21f3fe0 10872
252b5132
RH		 10873 case R_ARM_ABS32:
10874 value += addend;
35fc36a8 10875 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10876 value |= 1;
10877 break;
f21f3fe0 10878
bb224fc3
MS		 10879 case R_ARM_ABS32_NOI:
10880 value += addend;
10881 break;
10882
252b5132 10883 case R_ARM_REL32:
a8bc6c78 10884 value += addend;
35fc36a8 10885 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10886 value |= 1;
252b5132 10887 value -= (input_section->output_section->vma
62efb346 10888 + input_section->output_offset + rel->r_offset);
252b5132 10889 break;
eb043451 10890
bb224fc3
MS		 10891 case R_ARM_REL32_NOI:
10892 value += addend;
10893 value -= (input_section->output_section->vma
10894 + input_section->output_offset + rel->r_offset);
10895 break;
10896
eb043451
PB		 10897 case R_ARM_PREL31:
10898 value -= (input_section->output_section->vma
10899 + input_section->output_offset + rel->r_offset);
10900 value += signed_addend;
10901 if (! h || h->root.type != bfd_link_hash_undefweak)
10902 {
8029a119 10903 /* Check for overflow. */
eb043451
PB		 10904 if ((value ^ (value >> 1)) & (1 << 30))
10905 return bfd_reloc_overflow;
10906 }
10907 value &= 0x7fffffff;
10908 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10909 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10910 value |= 1;
10911 break;
252b5132 10912 }
f21f3fe0 10913
252b5132
RH		 10914 bfd_put_32 (input_bfd, value, hit_data);
10915 return bfd_reloc_ok;
10916
10917 case R_ARM_ABS8:
fd0fd00c
MJ		 10918 /* PR 16202: Refectch the addend using the correct size. */
10919 if (globals->use_rel)
10920 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10921 value += addend;
4e67d4ca
DG		 10922
10923 /* There is no way to tell whether the user intended to use a signed or
10924 unsigned addend. When checking for overflow we accept either,
10925 as specified by the AAELF. */
10926 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10927 return bfd_reloc_overflow;
10928
10929 bfd_put_8 (input_bfd, value, hit_data);
10930 return bfd_reloc_ok;
10931
10932 case R_ARM_ABS16:
fd0fd00c
MJ		 10933 /* PR 16202: Refectch the addend using the correct size. */
10934 if (globals->use_rel)
10935 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10936 value += addend;
10937
4e67d4ca
DG		 10938 /* See comment for R_ARM_ABS8. */
10939 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10940 return bfd_reloc_overflow;
10941
10942 bfd_put_16 (input_bfd, value, hit_data);
10943 return bfd_reloc_ok;
10944
252b5132 10945 case R_ARM_THM_ABS5:
9b485d32 10946 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10947 if (globals->use_rel)
10948 {
10949 /* Need to refetch addend. */
10950 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10951 /* ??? Need to determine shift amount from operand size. */
10952 addend >>= howto->rightshift;
10953 }
252b5132
RH		 10954 value += addend;
10955
10956 /* ??? Isn't value unsigned? */
10957 if ((long) value > 0x1f || (long) value < -0x10)
10958 return bfd_reloc_overflow;
10959
10960 /* ??? Value needs to be properly shifted into place first. */
10961 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10962 bfd_put_16 (input_bfd, value, hit_data);
10963 return bfd_reloc_ok;
10964
2cab6cc3
MS		 10965 case R_ARM_THM_ALU_PREL_11_0:
10966 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10967 {
10968 bfd_vma insn;
10969 bfd_signed_vma relocation;
10970
10971 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10972 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10973
99059e56
RM		 10974 if (globals->use_rel)
10975 {
10976 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10977 | ((insn & (1 << 26)) >> 15);
10978 if (insn & 0xf00000)
10979 signed_addend = -signed_addend;
10980 }
2cab6cc3
MS		 10981
10982 relocation = value + signed_addend;
79f08007 10983 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10984 + input_section->output_offset
10985 + rel->r_offset);
2cab6cc3 10986
8c65b54f
CS		 10987 /* PR 21523: Use an absolute value. The user of this reloc will
10988 have already selected an ADD or SUB insn appropriately. */
453f8e1e 10989 value = llabs (relocation);
2cab6cc3 10990
99059e56
RM		 10991 if (value >= 0x1000)
10992 return bfd_reloc_overflow;
2cab6cc3 10993
e645cf40
AG		 10994 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10995 if (branch_type == ST_BRANCH_TO_THUMB)
10996 value |= 1;
10997
2cab6cc3 10998 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10999 | ((value & 0x700) << 4)
11000 | ((value & 0x800) << 15);
11001 if (relocation < 0)
11002 insn |= 0xa00000;
2cab6cc3
MS		 11003
11004 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11005 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11006
99059e56 11007 return bfd_reloc_ok;
2cab6cc3
MS		 11008 }
11009
e1ec24c6
NC		 11010 case R_ARM_THM_PC8:
11011 /* PR 10073: This reloc is not generated by the GNU toolchain,
11012 but it is supported for compatibility with third party libraries
11013 generated by other compilers, specifically the ARM/IAR. */
11014 {
11015 bfd_vma insn;
11016 bfd_signed_vma relocation;
11017
11018 insn = bfd_get_16 (input_bfd, hit_data);
11019
99059e56 11020 if (globals->use_rel)
79f08007 11021 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 11022
11023 relocation = value + addend;
79f08007 11024 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11025 + input_section->output_offset
11026 + rel->r_offset);
e1ec24c6 11027
b6518b38 11028 value = relocation;
e1ec24c6
NC		 11029
11030 /* We do not check for overflow of this reloc. Although strictly
11031 speaking this is incorrect, it appears to be necessary in order
11032 to work with IAR generated relocs. Since GCC and GAS do not
11033 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
11034 a problem for them. */
11035 value &= 0x3fc;
11036
11037 insn = (insn & 0xff00) | (value >> 2);
11038
11039 bfd_put_16 (input_bfd, insn, hit_data);
11040
99059e56 11041 return bfd_reloc_ok;
e1ec24c6
NC		 11042 }
11043
2cab6cc3
MS		 11044 case R_ARM_THM_PC12:
11045 /* Corresponds to: ldr.w reg, [pc, #offset]. */
11046 {
11047 bfd_vma insn;
11048 bfd_signed_vma relocation;
11049
11050 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 11051 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 11052
99059e56
RM		 11053 if (globals->use_rel)
11054 {
11055 signed_addend = insn & 0xfff;
11056 if (!(insn & (1 << 23)))
11057 signed_addend = -signed_addend;
11058 }
2cab6cc3
MS		 11059
11060 relocation = value + signed_addend;
79f08007 11061 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11062 + input_section->output_offset
11063 + rel->r_offset);
2cab6cc3 11064
b6518b38 11065 value = relocation;
2cab6cc3 11066
99059e56
RM		 11067 if (value >= 0x1000)
11068 return bfd_reloc_overflow;
2cab6cc3
MS		 11069
11070 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 11071 if (relocation >= 0)
11072 insn |= (1 << 23);
2cab6cc3
MS		 11073
11074 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11075 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11076
99059e56 11077 return bfd_reloc_ok;
2cab6cc3
MS		 11078 }
11079
dfc5f959 11080 case R_ARM_THM_XPC22:
c19d1205 11081 case R_ARM_THM_CALL:
bd97cb95 11082 case R_ARM_THM_JUMP24:
dfc5f959 11083 /* Thumb BL (branch long instruction). */
252b5132 11084 {
b34976b6 11085 bfd_vma relocation;
99059e56 11086 bfd_vma reloc_sign;
b34976b6
AM		 11087 bfd_boolean overflow = FALSE;
11088 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11089 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 11090 bfd_signed_vma reloc_signed_max;
11091 bfd_signed_vma reloc_signed_min;
b34976b6 11092 bfd_vma check;
252b5132 11093 bfd_signed_vma signed_check;
e95de063 11094 int bitsize;
cd1dac3d 11095 const int thumb2 = using_thumb2 (globals);
5e866f5a 11096 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 11097
5ab79981 11098 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 11099 the next instruction unless a PLT entry will be created.
11100 The jump to the next instruction is optimized as a NOP.W for
11101 Thumb-2 enabled architectures. */
19540007 11102 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 11103 && plt_offset == (bfd_vma) -1)
5ab79981 11104 {
60a019a0 11105 if (thumb2)
cd1dac3d
DG		 11106 {
11107 bfd_put_16 (input_bfd, 0xf3af, hit_data);
11108 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
11109 }
11110 else
11111 {
11112 bfd_put_16 (input_bfd, 0xe000, hit_data);
11113 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11114 }
5ab79981
PB		 11115 return bfd_reloc_ok;
11116 }
11117
e95de063 11118 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 11119 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 11120 if (globals->use_rel)
11121 {
99059e56
RM		 11122 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11123 bfd_vma upper = upper_insn & 0x3ff;
11124 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 11125 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11126 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 11127 bfd_vma i1 = j1 ^ s ? 0 : 1;
11128 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 11129
99059e56
RM		 11130 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11131 /* Sign extend. */
11132 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 11133
4e7fd91e
PB		 11134 signed_addend = addend;
11135 }
cb1afa5c 11136
dfc5f959
NC		 11137 if (r_type == R_ARM_THM_XPC22)
11138 {
11139 /* Check for Thumb to Thumb call. */
11140 /* FIXME: Should we translate the instruction into a BL
11141 instruction instead ? */
35fc36a8 11142 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 11143 _bfd_error_handler
90b6238f
AM		 11144 (_("%pB: warning: %s BLX instruction targets"
11145 " %s function '%s'"),
11146 input_bfd, "Thumb",
11147 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 11148 }
11149 else
252b5132 11150 {
dfc5f959
NC		 11151 /* If it is not a call to Thumb, assume call to Arm.
11152 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 11153 function call at all, but rather a long jump. Calls through
11154 the PLT do not require stubs. */
34e77a92 11155 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 11156 {
bd97cb95 11157 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11158 {
11159 /* Convert BL to BLX. */
11160 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11161 }
155d87d7
CL		 11162 else if (( r_type != R_ARM_THM_CALL)
11163 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 11164 {
11165 if (elf32_thumb_to_arm_stub
11166 (info, sym_name, input_bfd, output_bfd, input_section,
11167 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11168 error_message))
11169 return bfd_reloc_ok;
11170 else
11171 return bfd_reloc_dangerous;
11172 }
da5938a2 11173 }
35fc36a8
RS		 11174 else if (branch_type == ST_BRANCH_TO_THUMB
11175 && globals->use_blx
bd97cb95 11176 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11177 {
11178 /* Make sure this is a BL. */
11179 lower_insn |= 0x1800;
11180 }
252b5132 11181 }
f21f3fe0 11182
fe33d2fa 11183 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 11184 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 11185 {
11186 /* Check if a stub has to be inserted because the destination
8029a119 11187 is too far. */
fe33d2fa
CL		 11188 struct elf32_arm_stub_hash_entry *stub_entry;
11189 struct elf32_arm_link_hash_entry *hash;
11190
11191 hash = (struct elf32_arm_link_hash_entry *) h;
11192
11193 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 11194 st_type, &branch_type,
11195 hash, value, sym_sec,
fe33d2fa
CL		 11196 input_bfd, sym_name);
11197
11198 if (stub_type != arm_stub_none)
906e58ca
NC		 11199 {
11200 /* The target is out of reach or we are changing modes, so
11201 redirect the branch to the local stub for this
11202 function. */
11203 stub_entry = elf32_arm_get_stub_entry (input_section,
11204 sym_sec, h,
fe33d2fa
CL		 11205 rel, globals,
11206 stub_type);
906e58ca 11207 if (stub_entry != NULL)
9cd3e4e5
NC		 11208 {
11209 value = (stub_entry->stub_offset
11210 + stub_entry->stub_sec->output_offset
11211 + stub_entry->stub_sec->output_section->vma);
11212
11213 if (plt_offset != (bfd_vma) -1)
11214 *unresolved_reloc_p = FALSE;
11215 }
906e58ca 11216
f4ac8484 11217 /* If this call becomes a call to Arm, force BLX. */
155d87d7 11218 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 11219 {
11220 if ((stub_entry
11221 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 11222 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 11223 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11224 }
906e58ca
NC		 11225 }
11226 }
11227
fe33d2fa 11228 /* Handle calls via the PLT. */
34e77a92 11229 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 11230 {
11231 value = (splt->output_section->vma
11232 + splt->output_offset
34e77a92 11233 + plt_offset);
fe33d2fa 11234
eed94f8f
NC		 11235 if (globals->use_blx
11236 && r_type == R_ARM_THM_CALL
11237 && ! using_thumb_only (globals))
fe33d2fa
CL		 11238 {
11239 /* If the Thumb BLX instruction is available, convert
11240 the BL to a BLX instruction to call the ARM-mode
11241 PLT entry. */
11242 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 11243 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 11244 }
11245 else
11246 {
eed94f8f
NC		 11247 if (! using_thumb_only (globals))
11248 /* Target the Thumb stub before the ARM PLT entry. */
11249 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 11250 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 11251 }
11252 *unresolved_reloc_p = FALSE;
11253 }
11254
ba96a88f 11255 relocation = value + signed_addend;
f21f3fe0 11256
252b5132 11257 relocation -= (input_section->output_section->vma
ba96a88f
NC		 11258 + input_section->output_offset
11259 + rel->r_offset);
9a5aca8c 11260
252b5132
RH		 11261 check = relocation >> howto->rightshift;
11262
11263 /* If this is a signed value, the rightshift just dropped
11264 leading 1 bits (assuming twos complement). */
11265 if ((bfd_signed_vma) relocation >= 0)
11266 signed_check = check;
11267 else
11268 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11269
e95de063
MS		 11270 /* Calculate the permissable maximum and minimum values for
11271 this relocation according to whether we're relocating for
11272 Thumb-2 or not. */
11273 bitsize = howto->bitsize;
5e866f5a 11274 if (!thumb2_bl)
e95de063 11275 bitsize -= 2;
f6ebfac0 11276 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 11277 reloc_signed_min = ~reloc_signed_max;
11278
252b5132 11279 /* Assumes two's complement. */
ba96a88f 11280 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 11281 overflow = TRUE;
252b5132 11282
bd97cb95 11283 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 11284 /* For a BLX instruction, make sure that the relocation is rounded up
11285 to a word boundary. This follows the semantics of the instruction
11286 which specifies that bit 1 of the target address will come from bit
11287 1 of the base address. */
11288 relocation = (relocation + 2) & ~ 3;
cb1afa5c 11289
e95de063
MS		 11290 /* Put RELOCATION back into the insn. Assumes two's complement.
11291 We use the Thumb-2 encoding, which is safe even if dealing with
11292 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 11293 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 11294 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 11295 | ((relocation >> 12) & 0x3ff)
11296 | (reloc_sign << 10);
906e58ca 11297 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 11298 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11299 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11300 | ((relocation >> 1) & 0x7ff);
c62e1cc3 11301
252b5132
RH		 11302 /* Put the relocated value back in the object file: */
11303 bfd_put_16 (input_bfd, upper_insn, hit_data);
11304 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11305
11306 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11307 }
11308 break;
11309
c19d1205
ZW		 11310 case R_ARM_THM_JUMP19:
11311 /* Thumb32 conditional branch instruction. */
11312 {
11313 bfd_vma relocation;
11314 bfd_boolean overflow = FALSE;
11315 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11316 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 11317 bfd_signed_vma reloc_signed_max = 0xffffe;
11318 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 11319 bfd_signed_vma signed_check;
07d6d2b8 11320 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 11321 struct elf32_arm_stub_hash_entry *stub_entry;
11322 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 11323
11324 /* Need to refetch the addend, reconstruct the top three bits,
11325 and squish the two 11 bit pieces together. */
11326 if (globals->use_rel)
11327 {
11328 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 11329 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 11330 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11331 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11332 bfd_vma lower = (lower_insn & 0x07ff);
11333
a00a1f35
MS		 11334 upper |= J1 << 6;
11335 upper |= J2 << 7;
11336 upper |= (!S) << 8;
c19d1205
ZW		 11337 upper -= 0x0100; /* Sign extend. */
11338
11339 addend = (upper << 12) | (lower << 1);
11340 signed_addend = addend;
11341 }
11342
bd97cb95 11343 /* Handle calls via the PLT. */
34e77a92 11344 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 11345 {
11346 value = (splt->output_section->vma
11347 + splt->output_offset
34e77a92 11348 + plt_offset);
bd97cb95
DJ		 11349 /* Target the Thumb stub before the ARM PLT entry. */
11350 value -= PLT_THUMB_STUB_SIZE;
11351 *unresolved_reloc_p = FALSE;
11352 }
11353
c5423981
TG		 11354 hash = (struct elf32_arm_link_hash_entry *)h;
11355
11356 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 11357 st_type, &branch_type,
11358 hash, value, sym_sec,
11359 input_bfd, sym_name);
c5423981
TG		 11360 if (stub_type != arm_stub_none)
11361 {
11362 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 11363 sym_sec, h,
11364 rel, globals,
11365 stub_type);
c5423981
TG		 11366 if (stub_entry != NULL)
11367 {
07d6d2b8
AM		 11368 value = (stub_entry->stub_offset
11369 + stub_entry->stub_sec->output_offset
11370 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 11371 }
11372 }
c19d1205 11373
99059e56 11374 relocation = value + signed_addend;
c19d1205
ZW		 11375 relocation -= (input_section->output_section->vma
11376 + input_section->output_offset
11377 + rel->r_offset);
a00a1f35 11378 signed_check = (bfd_signed_vma) relocation;
c19d1205 11379
c19d1205
ZW		 11380 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11381 overflow = TRUE;
11382
11383 /* Put RELOCATION back into the insn. */
11384 {
11385 bfd_vma S = (relocation & 0x00100000) >> 20;
11386 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11387 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11388 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11389 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11390
a00a1f35 11391 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 11392 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11393 }
11394
11395 /* Put the relocated value back in the object file: */
11396 bfd_put_16 (input_bfd, upper_insn, hit_data);
11397 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11398
11399 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11400 }
11401
11402 case R_ARM_THM_JUMP11:
11403 case R_ARM_THM_JUMP8:
11404 case R_ARM_THM_JUMP6:
51c5503b
NC		 11405 /* Thumb B (branch) instruction). */
11406 {
6cf9e9fe 11407 bfd_signed_vma relocation;
51c5503b
NC		 11408 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11409 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11410 bfd_signed_vma signed_check;
11411
c19d1205
ZW		 11412 /* CZB cannot jump backward. */
11413 if (r_type == R_ARM_THM_JUMP6)
11414 reloc_signed_min = 0;
11415
4e7fd91e 11416 if (globals->use_rel)
6cf9e9fe 11417 {
4e7fd91e
PB		 11418 /* Need to refetch addend. */
11419 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
11420 if (addend & ((howto->src_mask + 1) >> 1))
11421 {
11422 signed_addend = -1;
11423 signed_addend &= ~ howto->src_mask;
11424 signed_addend |= addend;
11425 }
11426 else
11427 signed_addend = addend;
11428 /* The value in the insn has been right shifted. We need to
11429 undo this, so that we can perform the address calculation
11430 in terms of bytes. */
11431 signed_addend <<= howto->rightshift;
6cf9e9fe 11432 }
6cf9e9fe 11433 relocation = value + signed_addend;
51c5503b
NC		 11434
11435 relocation -= (input_section->output_section->vma
11436 + input_section->output_offset
11437 + rel->r_offset);
11438
6cf9e9fe
NC		 11439 relocation >>= howto->rightshift;
11440 signed_check = relocation;
c19d1205
ZW		 11441
11442 if (r_type == R_ARM_THM_JUMP6)
11443 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11444 else
11445 relocation &= howto->dst_mask;
51c5503b 11446 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11447
51c5503b
NC		 11448 bfd_put_16 (input_bfd, relocation, hit_data);
11449
11450 /* Assumes two's complement. */
11451 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11452 return bfd_reloc_overflow;
11453
11454 return bfd_reloc_ok;
11455 }
cedb70c5 11456
8375c36b
PB		 11457 case R_ARM_ALU_PCREL7_0:
11458 case R_ARM_ALU_PCREL15_8:
11459 case R_ARM_ALU_PCREL23_15:
11460 {
11461 bfd_vma insn;
11462 bfd_vma relocation;
11463
11464 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11465 if (globals->use_rel)
11466 {
11467 /* Extract the addend. */
11468 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11469 signed_addend = addend;
11470 }
8375c36b
PB		 11471 relocation = value + signed_addend;
11472
11473 relocation -= (input_section->output_section->vma
11474 + input_section->output_offset
11475 + rel->r_offset);
11476 insn = (insn & ~0xfff)
11477 | ((howto->bitpos << 7) & 0xf00)
11478 | ((relocation >> howto->bitpos) & 0xff);
11479 bfd_put_32 (input_bfd, value, hit_data);
11480 }
11481 return bfd_reloc_ok;
11482
252b5132
RH		 11483 case R_ARM_GNU_VTINHERIT:
11484 case R_ARM_GNU_VTENTRY:
11485 return bfd_reloc_ok;
11486
c19d1205 11487 case R_ARM_GOTOFF32:
252b5132 11488 /* Relocation is relative to the start of the
99059e56 11489 global offset table. */
252b5132
RH		 11490
11491 BFD_ASSERT (sgot != NULL);
11492 if (sgot == NULL)
99059e56 11493 return bfd_reloc_notsupported;
9a5aca8c 11494
cedb70c5 11495 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11496 address by one, so that attempts to call the function pointer will
11497 correctly interpret it as Thumb code. */
35fc36a8 11498 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11499 value += 1;
11500
252b5132 11501 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11502 calculation. We always want the start of .got. If we
11503 define _GLOBAL_OFFSET_TABLE in a different way, as is
11504 permitted by the ABI, we might have to change this
11505 calculation. */
252b5132 11506 value -= sgot->output_section->vma;
f21f3fe0 11507 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11508 contents, rel->r_offset, value,
00a97672 11509 rel->r_addend);
252b5132
RH		 11510
11511 case R_ARM_GOTPC:
a7c10850 11512 /* Use global offset table as symbol value. */
252b5132 11513 BFD_ASSERT (sgot != NULL);
f21f3fe0 11514
252b5132 11515 if (sgot == NULL)
99059e56 11516 return bfd_reloc_notsupported;
252b5132 11517
0945cdfd 11518 *unresolved_reloc_p = FALSE;
252b5132 11519 value = sgot->output_section->vma;
f21f3fe0 11520 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11521 contents, rel->r_offset, value,
00a97672 11522 rel->r_addend);
f21f3fe0 11523
252b5132 11524 case R_ARM_GOT32:
eb043451 11525 case R_ARM_GOT_PREL:
252b5132 11526 /* Relocation is to the entry for this symbol in the
99059e56 11527 global offset table. */
252b5132
RH		 11528 if (sgot == NULL)
11529 return bfd_reloc_notsupported;
f21f3fe0 11530
34e77a92
RS		 11531 if (dynreloc_st_type == STT_GNU_IFUNC
11532 && plt_offset != (bfd_vma) -1
11533 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11534 {
11535 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11536 symbol, and the relocation resolves directly to the runtime
11537 target rather than to the .iplt entry. This means that any
11538 .got entry would be the same value as the .igot.plt entry,
11539 so there's no point creating both. */
11540 sgot = globals->root.igotplt;
11541 value = sgot->output_offset + gotplt_offset;
11542 }
11543 else if (h != NULL)
252b5132
RH		 11544 {
11545 bfd_vma off;
f21f3fe0 11546
252b5132
RH		 11547 off = h->got.offset;
11548 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11549 if ((off & 1) != 0)
252b5132 11550 {
b436d854
RS		 11551 /* We have already processsed one GOT relocation against
11552 this symbol. */
11553 off &= ~1;
11554 if (globals->root.dynamic_sections_created
11555 && !SYMBOL_REFERENCES_LOCAL (info, h))
11556 *unresolved_reloc_p = FALSE;
11557 }
11558 else
11559 {
11560 Elf_Internal_Rela outrel;
e8b09b87 11561 int isrofixup = 0;
b436d854 11562
e8b09b87
CL		 11563 if (((h->dynindx != -1) || globals->fdpic_p)
11564 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11565 {
11566 /* If the symbol doesn't resolve locally in a static
11567 object, we have an undefined reference. If the
11568 symbol doesn't resolve locally in a dynamic object,
11569 it should be resolved by the dynamic linker. */
11570 if (globals->root.dynamic_sections_created)
11571 {
11572 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11573 *unresolved_reloc_p = FALSE;
11574 }
11575 else
11576 outrel.r_info = 0;
11577 outrel.r_addend = 0;
11578 }
252b5132
RH		 11579 else
11580 {
34e77a92 11581 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11582 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11583 else if (bfd_link_pic (info)
11584 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11585 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11586 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11587 else
2376f038
EB		 11588 {
11589 outrel.r_info = 0;
11590 if (globals->fdpic_p)
11591 isrofixup = 1;
11592 }
34e77a92 11593 outrel.r_addend = dynreloc_value;
b436d854 11594 }
ee29b9fb 11595
b436d854
RS		 11596 /* The GOT entry is initialized to zero by default.
11597 See if we should install a different value. */
11598 if (outrel.r_addend != 0
2376f038 11599 && (globals->use_rel || outrel.r_info == 0))
b436d854
RS		 11600 {
11601 bfd_put_32 (output_bfd, outrel.r_addend,
11602 sgot->contents + off);
11603 outrel.r_addend = 0;
252b5132 11604 }
f21f3fe0 11605
2376f038
EB		 11606 if (isrofixup)
11607 arm_elf_add_rofixup (output_bfd,
11608 elf32_arm_hash_table(info)->srofixup,
11609 sgot->output_section->vma
11610 + sgot->output_offset + off);
11611
11612 else if (outrel.r_info != 0)
b436d854
RS		 11613 {
11614 outrel.r_offset = (sgot->output_section->vma
11615 + sgot->output_offset
11616 + off);
11617 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11618 }
2376f038 11619
b436d854
RS		 11620 h->got.offset |= 1;
11621 }
252b5132
RH		 11622 value = sgot->output_offset + off;
11623 }
11624 else
11625 {
11626 bfd_vma off;
f21f3fe0 11627
5025eb7c
AO		 11628 BFD_ASSERT (local_got_offsets != NULL
11629 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11630
252b5132 11631 off = local_got_offsets[r_symndx];
f21f3fe0 11632
252b5132
RH		 11633 /* The offset must always be a multiple of 4. We use the
11634 least significant bit to record whether we have already
9b485d32 11635 generated the necessary reloc. */
252b5132
RH		 11636 if ((off & 1) != 0)
11637 off &= ~1;
11638 else
11639 {
2376f038
EB		 11640 Elf_Internal_Rela outrel;
11641 int isrofixup = 0;
f21f3fe0 11642
2376f038
EB		 11643 if (dynreloc_st_type == STT_GNU_IFUNC)
11644 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11645 else if (bfd_link_pic (info))
11646 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11647 else
252b5132 11648 {
2376f038
EB		 11649 outrel.r_info = 0;
11650 if (globals->fdpic_p)
11651 isrofixup = 1;
11652 }
11653
11654 /* The GOT entry is initialized to zero by default.
11655 See if we should install a different value. */
11656 if (globals->use_rel || outrel.r_info == 0)
11657 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
11658
11659 if (isrofixup)
11660 arm_elf_add_rofixup (output_bfd,
11661 globals->srofixup,
11662 sgot->output_section->vma
11663 + sgot->output_offset + off);
f21f3fe0 11664
2376f038
EB		 11665 else if (outrel.r_info != 0)
11666 {
34e77a92 11667 outrel.r_addend = addend + dynreloc_value;
252b5132 11668 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11669 + sgot->output_offset
252b5132 11670 + off);
47beaa6a 11671 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11672 }
f21f3fe0 11673
252b5132
RH		 11674 local_got_offsets[r_symndx] |= 1;
11675 }
f21f3fe0 11676
252b5132
RH		 11677 value = sgot->output_offset + off;
11678 }
eb043451
PB		 11679 if (r_type != R_ARM_GOT32)
11680 value += sgot->output_section->vma;
9a5aca8c 11681
f21f3fe0 11682 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11683 contents, rel->r_offset, value,
00a97672 11684 rel->r_addend);
f21f3fe0 11685
ba93b8ac
DJ		 11686 case R_ARM_TLS_LDO32:
11687 value = value - dtpoff_base (info);
11688
11689 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11690 contents, rel->r_offset, value,
11691 rel->r_addend);
ba93b8ac
DJ		 11692
11693 case R_ARM_TLS_LDM32:
5c5a4843 11694 case R_ARM_TLS_LDM32_FDPIC:
ba93b8ac
DJ		 11695 {
11696 bfd_vma off;
11697
362d30a1 11698 if (sgot == NULL)
ba93b8ac
DJ		 11699 abort ();
11700
11701 off = globals->tls_ldm_got.offset;
11702
11703 if ((off & 1) != 0)
11704 off &= ~1;
11705 else
11706 {
11707 /* If we don't know the module number, create a relocation
11708 for it. */
9cb09e33 11709 if (bfd_link_dll (info))
ba93b8ac
DJ		 11710 {
11711 Elf_Internal_Rela outrel;
ba93b8ac 11712
362d30a1 11713 if (srelgot == NULL)
ba93b8ac
DJ		 11714 abort ();
11715
00a97672 11716 outrel.r_addend = 0;
362d30a1
RS		 11717 outrel.r_offset = (sgot->output_section->vma
11718 + sgot->output_offset + off);
ba93b8ac
DJ		 11719 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11720
00a97672
RS		 11721 if (globals->use_rel)
11722 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11723 sgot->contents + off);
ba93b8ac 11724
47beaa6a 11725 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11726 }
11727 else
362d30a1 11728 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11729
11730 globals->tls_ldm_got.offset |= 1;
11731 }
11732
5c5a4843 11733 if (r_type == R_ARM_TLS_LDM32_FDPIC)
e8b09b87
CL		 11734 {
11735 bfd_put_32(output_bfd,
11736 globals->root.sgot->output_offset + off,
11737 contents + rel->r_offset);
11738
11739 return bfd_reloc_ok;
11740 }
11741 else
11742 {
11743 value = sgot->output_section->vma + sgot->output_offset + off
11744 - (input_section->output_section->vma
11745 + input_section->output_offset + rel->r_offset);
ba93b8ac 11746
e8b09b87
CL		 11747 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11748 contents, rel->r_offset, value,
11749 rel->r_addend);
11750 }
ba93b8ac
DJ		 11751 }
11752
0855e32b
NS		 11753 case R_ARM_TLS_CALL:
11754 case R_ARM_THM_TLS_CALL:
ba93b8ac 11755 case R_ARM_TLS_GD32:
5c5a4843 11756 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 11757 case R_ARM_TLS_IE32:
5c5a4843 11758 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 11759 case R_ARM_TLS_GOTDESC:
11760 case R_ARM_TLS_DESCSEQ:
11761 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11762 {
0855e32b
NS		 11763 bfd_vma off, offplt;
11764 int indx = 0;
ba93b8ac
DJ		 11765 char tls_type;
11766
0855e32b 11767 BFD_ASSERT (sgot != NULL);
ba93b8ac 11768
ba93b8ac
DJ		 11769 if (h != NULL)
11770 {
11771 bfd_boolean dyn;
11772 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11773 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11774 bfd_link_pic (info),
11775 h)
11776 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11777 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11778 {
11779 *unresolved_reloc_p = FALSE;
11780 indx = h->dynindx;
11781 }
11782 off = h->got.offset;
0855e32b 11783 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11784 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11785 }
11786 else
11787 {
0855e32b 11788 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11789 off = local_got_offsets[r_symndx];
0855e32b 11790 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11791 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11792 }
11793
0855e32b 11794 /* Linker relaxations happens from one of the
b38cadfb 11795 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11796 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11797 tls_type = GOT_TLS_IE;
0855e32b
NS		 11798
11799 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11800
11801 if ((off & 1) != 0)
11802 off &= ~1;
11803 else
11804 {
11805 bfd_boolean need_relocs = FALSE;
11806 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11807 int cur_off = off;
11808
11809 /* The GOT entries have not been initialized yet. Do it
11810 now, and emit any relocations. If both an IE GOT and a
11811 GD GOT are necessary, we emit the GD first. */
11812
9cb09e33 11813 if ((bfd_link_dll (info) || indx != 0)
ba93b8ac 11814 && (h == NULL
95b03e4a
L		 11815 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11816 && !resolved_to_zero)
ba93b8ac
DJ		 11817 || h->root.type != bfd_link_hash_undefweak))
11818 {
11819 need_relocs = TRUE;
0855e32b 11820 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11821 }
11822
0855e32b
NS		 11823 if (tls_type & GOT_TLS_GDESC)
11824 {
47beaa6a
RS		 11825 bfd_byte *loc;
11826
0855e32b
NS		 11827 /* We should have relaxed, unless this is an undefined
11828 weak symbol. */
11829 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
9cb09e33 11830 || bfd_link_dll (info));
0855e32b 11831 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11832 <= globals->root.sgotplt->size);
0855e32b
NS		 11833
11834 outrel.r_addend = 0;
11835 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11836 + globals->root.sgotplt->output_offset
11837 + offplt
11838 + globals->sgotplt_jump_table_size);
b38cadfb 11839
0855e32b
NS		 11840 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11841 sreloc = globals->root.srelplt;
11842 loc = sreloc->contents;
11843 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11844 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11845 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11846
11847 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11848
11849 /* For globals, the first word in the relocation gets
11850 the relocation index and the top bit set, or zero,
11851 if we're binding now. For locals, it gets the
11852 symbol's offset in the tls section. */
99059e56 11853 bfd_put_32 (output_bfd,
0855e32b
NS		 11854 !h ? value - elf_hash_table (info)->tls_sec->vma
11855 : info->flags & DF_BIND_NOW ? 0
11856 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11857 globals->root.sgotplt->contents + offplt
11858 + globals->sgotplt_jump_table_size);
11859
0855e32b 11860 /* Second word in the relocation is always zero. */
99059e56 11861 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11862 globals->root.sgotplt->contents + offplt
11863 + globals->sgotplt_jump_table_size + 4);
0855e32b 11864 }
ba93b8ac
DJ		 11865 if (tls_type & GOT_TLS_GD)
11866 {
11867 if (need_relocs)
11868 {
00a97672 11869 outrel.r_addend = 0;
362d30a1
RS		 11870 outrel.r_offset = (sgot->output_section->vma
11871 + sgot->output_offset
00a97672 11872 + cur_off);
ba93b8ac 11873 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11874
00a97672
RS		 11875 if (globals->use_rel)
11876 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11877 sgot->contents + cur_off);
00a97672 11878
47beaa6a 11879 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11880
11881 if (indx == 0)
11882 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11883 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11884 else
11885 {
00a97672 11886 outrel.r_addend = 0;
ba93b8ac
DJ		 11887 outrel.r_info = ELF32_R_INFO (indx,
11888 R_ARM_TLS_DTPOFF32);
11889 outrel.r_offset += 4;
00a97672
RS		 11890
11891 if (globals->use_rel)
11892 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11893 sgot->contents + cur_off + 4);
00a97672 11894
47beaa6a
RS		 11895 elf32_arm_add_dynreloc (output_bfd, info,
11896 srelgot, &outrel);
ba93b8ac
DJ		 11897 }
11898 }
11899 else
11900 {
11901 /* If we are not emitting relocations for a
11902 general dynamic reference, then we must be in a
11903 static link or an executable link with the
11904 symbol binding locally. Mark it as belonging
11905 to module 1, the executable. */
11906 bfd_put_32 (output_bfd, 1,
362d30a1 11907 sgot->contents + cur_off);
ba93b8ac 11908 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11909 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11910 }
11911
11912 cur_off += 8;
11913 }
11914
11915 if (tls_type & GOT_TLS_IE)
11916 {
11917 if (need_relocs)
11918 {
00a97672
RS		 11919 if (indx == 0)
11920 outrel.r_addend = value - dtpoff_base (info);
11921 else
11922 outrel.r_addend = 0;
362d30a1
RS		 11923 outrel.r_offset = (sgot->output_section->vma
11924 + sgot->output_offset
ba93b8ac
DJ		 11925 + cur_off);
11926 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11927
00a97672
RS		 11928 if (globals->use_rel)
11929 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11930 sgot->contents + cur_off);
ba93b8ac 11931
47beaa6a 11932 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11933 }
11934 else
11935 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11936 sgot->contents + cur_off);
ba93b8ac
DJ		 11937 cur_off += 4;
11938 }
11939
11940 if (h != NULL)
11941 h->got.offset |= 1;
11942 else
11943 local_got_offsets[r_symndx] |= 1;
11944 }
11945
5c5a4843 11946 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
ba93b8ac 11947 off += 8;
0855e32b
NS		 11948 else if (tls_type & GOT_TLS_GDESC)
11949 off = offplt;
11950
11951 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11952 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11953 {
11954 bfd_signed_vma offset;
12352d3f
PB		 11955 /* TLS stubs are arm mode. The original symbol is a
11956 data object, so branch_type is bogus. */
11957 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11958 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11959 = arm_type_of_stub (info, input_section, rel,
11960 st_type, &branch_type,
0855e32b
NS		 11961 (struct elf32_arm_link_hash_entry *)h,
11962 globals->tls_trampoline, globals->root.splt,
11963 input_bfd, sym_name);
11964
11965 if (stub_type != arm_stub_none)
11966 {
11967 struct elf32_arm_stub_hash_entry *stub_entry
11968 = elf32_arm_get_stub_entry
11969 (input_section, globals->root.splt, 0, rel,
11970 globals, stub_type);
11971 offset = (stub_entry->stub_offset
11972 + stub_entry->stub_sec->output_offset
11973 + stub_entry->stub_sec->output_section->vma);
11974 }
11975 else
11976 offset = (globals->root.splt->output_section->vma
11977 + globals->root.splt->output_offset
11978 + globals->tls_trampoline);
11979
11980 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11981 {
11982 unsigned long inst;
b38cadfb
NC		 11983
11984 offset -= (input_section->output_section->vma
11985 + input_section->output_offset
11986 + rel->r_offset + 8);
0855e32b
NS		 11987
11988 inst = offset >> 2;
11989 inst &= 0x00ffffff;
11990 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11991 }
11992 else
11993 {
11994 /* Thumb blx encodes the offset in a complicated
11995 fashion. */
11996 unsigned upper_insn, lower_insn;
11997 unsigned neg;
11998
b38cadfb
NC		 11999 offset -= (input_section->output_section->vma
12000 + input_section->output_offset
0855e32b 12001 + rel->r_offset + 4);
b38cadfb 12002
12352d3f
PB		 12003 if (stub_type != arm_stub_none
12004 && arm_stub_is_thumb (stub_type))
12005 {
12006 lower_insn = 0xd000;
12007 }
12008 else
12009 {
12010 lower_insn = 0xc000;
6a631e86 12011 /* Round up the offset to a word boundary. */
12352d3f
PB		 12012 offset = (offset + 2) & ~2;
12013 }
12014
0855e32b
NS		 12015 neg = offset < 0;
12016 upper_insn = (0xf000
12017 | ((offset >> 12) & 0x3ff)
12018 | (neg << 10));
12352d3f 12019 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 12020 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 12021 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 12022 bfd_put_16 (input_bfd, upper_insn, hit_data);
12023 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12024 return bfd_reloc_ok;
12025 }
12026 }
12027 /* These relocations needs special care, as besides the fact
12028 they point somewhere in .gotplt, the addend must be
12029 adjusted accordingly depending on the type of instruction
6a631e86 12030 we refer to. */
0855e32b
NS		 12031 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
12032 {
12033 unsigned long data, insn;
12034 unsigned thumb;
b38cadfb 12035
b627f562 12036 data = bfd_get_signed_32 (input_bfd, hit_data);
0855e32b 12037 thumb = data & 1;
b627f562 12038 data &= ~1ul;
b38cadfb 12039
0855e32b
NS		 12040 if (thumb)
12041 {
12042 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
12043 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
12044 insn = (insn << 16)
12045 | bfd_get_16 (input_bfd,
12046 contents + rel->r_offset - data + 2);
12047 if ((insn & 0xf800c000) == 0xf000c000)
12048 /* bl/blx */
12049 value = -6;
12050 else if ((insn & 0xffffff00) == 0x4400)
12051 /* add */
12052 value = -5;
12053 else
12054 {
4eca0228 12055 _bfd_error_handler
695344c0 12056 /* xgettext:c-format */
2dcf00ce 12057 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12058 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12059 "referenced by TLS_GOTDESC"),
12060 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12061 "Thumb", insn);
0855e32b
NS		 12062 return bfd_reloc_notsupported;
12063 }
12064 }
12065 else
12066 {
12067 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
12068
12069 switch (insn >> 24)
12070 {
12071 case 0xeb: /* bl */
12072 case 0xfa: /* blx */
12073 value = -4;
12074 break;
12075
12076 case 0xe0: /* add */
12077 value = -8;
12078 break;
b38cadfb 12079
0855e32b 12080 default:
4eca0228 12081 _bfd_error_handler
695344c0 12082 /* xgettext:c-format */
2dcf00ce 12083 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12084 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12085 "referenced by TLS_GOTDESC"),
12086 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12087 "ARM", insn);
0855e32b
NS		 12088 return bfd_reloc_notsupported;
12089 }
12090 }
b38cadfb 12091
0855e32b
NS		 12092 value += ((globals->root.sgotplt->output_section->vma
12093 + globals->root.sgotplt->output_offset + off)
12094 - (input_section->output_section->vma
12095 + input_section->output_offset
12096 + rel->r_offset)
12097 + globals->sgotplt_jump_table_size);
12098 }
12099 else
12100 value = ((globals->root.sgot->output_section->vma
12101 + globals->root.sgot->output_offset + off)
12102 - (input_section->output_section->vma
12103 + input_section->output_offset + rel->r_offset));
ba93b8ac 12104
5c5a4843
CL		 12105 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
12106 r_type == R_ARM_TLS_IE32_FDPIC))
e8b09b87
CL		 12107 {
12108 /* For FDPIC relocations, resolve to the offset of the GOT
12109 entry from the start of GOT. */
12110 bfd_put_32(output_bfd,
12111 globals->root.sgot->output_offset + off,
12112 contents + rel->r_offset);
12113
12114 return bfd_reloc_ok;
12115 }
12116 else
12117 {
12118 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12119 contents, rel->r_offset, value,
12120 rel->r_addend);
12121 }
ba93b8ac
DJ		 12122 }
12123
12124 case R_ARM_TLS_LE32:
3cbc1e5e 12125 if (bfd_link_dll (info))
ba93b8ac 12126 {
4eca0228 12127 _bfd_error_handler
695344c0 12128 /* xgettext:c-format */
2dcf00ce
AM		 12129 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12130 "in shared object"),
12131 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 12132 return bfd_reloc_notsupported;
ba93b8ac
DJ		 12133 }
12134 else
12135 value = tpoff (info, value);
906e58ca 12136
ba93b8ac 12137 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 12138 contents, rel->r_offset, value,
12139 rel->r_addend);
ba93b8ac 12140
319850b4
JB		 12141 case R_ARM_V4BX:
12142 if (globals->fix_v4bx)
845b51d6
PB		 12143 {
12144 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 12145
845b51d6
PB		 12146 /* Ensure that we have a BX instruction. */
12147 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 12148
845b51d6
PB		 12149 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12150 {
12151 /* Branch to veneer. */
12152 bfd_vma glue_addr;
12153 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12154 glue_addr -= input_section->output_section->vma
12155 + input_section->output_offset
12156 + rel->r_offset + 8;
12157 insn = (insn & 0xf0000000) | 0x0a000000
12158 | ((glue_addr >> 2) & 0x00ffffff);
12159 }
12160 else
12161 {
12162 /* Preserve Rm (lowest four bits) and the condition code
12163 (highest four bits). Other bits encode MOV PC,Rm. */
12164 insn = (insn & 0xf000000f) | 0x01a0f000;
12165 }
319850b4 12166
845b51d6
PB		 12167 bfd_put_32 (input_bfd, insn, hit_data);
12168 }
319850b4
JB		 12169 return bfd_reloc_ok;
12170
b6895b4f
PB		 12171 case R_ARM_MOVW_ABS_NC:
12172 case R_ARM_MOVT_ABS:
12173 case R_ARM_MOVW_PREL_NC:
12174 case R_ARM_MOVT_PREL:
92f5d02b
MS		 12175 /* Until we properly support segment-base-relative addressing then
12176 we assume the segment base to be zero, as for the group relocations.
12177 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12178 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12179 case R_ARM_MOVW_BREL_NC:
12180 case R_ARM_MOVW_BREL:
12181 case R_ARM_MOVT_BREL:
b6895b4f
PB		 12182 {
12183 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12184
12185 if (globals->use_rel)
12186 {
12187 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 12188 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12189 }
92f5d02b 12190
b6895b4f 12191 value += signed_addend;
b6895b4f
PB		 12192
12193 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12194 value -= (input_section->output_section->vma
12195 + input_section->output_offset + rel->r_offset);
12196
92f5d02b 12197 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 12198 return bfd_reloc_overflow;
92f5d02b 12199
35fc36a8 12200 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12201 value |= 1;
12202
12203 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 12204 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 12205 value >>= 16;
12206
12207 insn &= 0xfff0f000;
12208 insn |= value & 0xfff;
12209 insn |= (value & 0xf000) << 4;
12210 bfd_put_32 (input_bfd, insn, hit_data);
12211 }
12212 return bfd_reloc_ok;
12213
12214 case R_ARM_THM_MOVW_ABS_NC:
12215 case R_ARM_THM_MOVT_ABS:
12216 case R_ARM_THM_MOVW_PREL_NC:
12217 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 12218 /* Until we properly support segment-base-relative addressing then
12219 we assume the segment base to be zero, as for the above relocations.
12220 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12221 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12222 as R_ARM_THM_MOVT_ABS. */
12223 case R_ARM_THM_MOVW_BREL_NC:
12224 case R_ARM_THM_MOVW_BREL:
12225 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 12226 {
12227 bfd_vma insn;
906e58ca 12228
b6895b4f
PB		 12229 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12230 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12231
12232 if (globals->use_rel)
12233 {
12234 addend = ((insn >> 4) & 0xf000)
12235 | ((insn >> 15) & 0x0800)
12236 | ((insn >> 4) & 0x0700)
07d6d2b8 12237 | (insn & 0x00ff);
39623e12 12238 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12239 }
92f5d02b 12240
b6895b4f 12241 value += signed_addend;
b6895b4f
PB		 12242
12243 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12244 value -= (input_section->output_section->vma
12245 + input_section->output_offset + rel->r_offset);
12246
92f5d02b 12247 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 12248 return bfd_reloc_overflow;
92f5d02b 12249
35fc36a8 12250 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12251 value |= 1;
12252
12253 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 12254 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 12255 value >>= 16;
12256
12257 insn &= 0xfbf08f00;
12258 insn |= (value & 0xf000) << 4;
12259 insn |= (value & 0x0800) << 15;
12260 insn |= (value & 0x0700) << 4;
12261 insn |= (value & 0x00ff);
12262
12263 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12264 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12265 }
12266 return bfd_reloc_ok;
12267
4962c51a
MS		 12268 case R_ARM_ALU_PC_G0_NC:
12269 case R_ARM_ALU_PC_G1_NC:
12270 case R_ARM_ALU_PC_G0:
12271 case R_ARM_ALU_PC_G1:
12272 case R_ARM_ALU_PC_G2:
12273 case R_ARM_ALU_SB_G0_NC:
12274 case R_ARM_ALU_SB_G1_NC:
12275 case R_ARM_ALU_SB_G0:
12276 case R_ARM_ALU_SB_G1:
12277 case R_ARM_ALU_SB_G2:
12278 {
12279 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12280 bfd_vma pc = input_section->output_section->vma
4962c51a 12281 + input_section->output_offset + rel->r_offset;
31a91d61 12282 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12283 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 12284 bfd_vma residual;
12285 bfd_vma g_n;
4962c51a 12286 bfd_signed_vma signed_value;
99059e56
RM		 12287 int group = 0;
12288
12289 /* Determine which group of bits to select. */
12290 switch (r_type)
12291 {
12292 case R_ARM_ALU_PC_G0_NC:
12293 case R_ARM_ALU_PC_G0:
12294 case R_ARM_ALU_SB_G0_NC:
12295 case R_ARM_ALU_SB_G0:
12296 group = 0;
12297 break;
12298
12299 case R_ARM_ALU_PC_G1_NC:
12300 case R_ARM_ALU_PC_G1:
12301 case R_ARM_ALU_SB_G1_NC:
12302 case R_ARM_ALU_SB_G1:
12303 group = 1;
12304 break;
12305
12306 case R_ARM_ALU_PC_G2:
12307 case R_ARM_ALU_SB_G2:
12308 group = 2;
12309 break;
12310
12311 default:
12312 abort ();
12313 }
12314
12315 /* If REL, extract the addend from the insn. If RELA, it will
12316 have already been fetched for us. */
4962c51a 12317 if (globals->use_rel)
99059e56
RM		 12318 {
12319 int negative;
12320 bfd_vma constant = insn & 0xff;
12321 bfd_vma rotation = (insn & 0xf00) >> 8;
12322
12323 if (rotation == 0)
12324 signed_addend = constant;
12325 else
12326 {
12327 /* Compensate for the fact that in the instruction, the
12328 rotation is stored in multiples of 2 bits. */
12329 rotation *= 2;
12330
12331 /* Rotate "constant" right by "rotation" bits. */
12332 signed_addend = (constant >> rotation) |
12333 (constant << (8 * sizeof (bfd_vma) - rotation));
12334 }
12335
12336 /* Determine if the instruction is an ADD or a SUB.
12337 (For REL, this determines the sign of the addend.) */
12338 negative = identify_add_or_sub (insn);
12339 if (negative == 0)
12340 {
4eca0228 12341 _bfd_error_handler
695344c0 12342 /* xgettext:c-format */
90b6238f 12343 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 12344 "are allowed for ALU group relocations"),
12345 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 12346 return bfd_reloc_overflow;
12347 }
12348
12349 signed_addend *= negative;
12350 }
4962c51a
MS		 12351
12352 /* Compute the value (X) to go in the place. */
99059e56
RM		 12353 if (r_type == R_ARM_ALU_PC_G0_NC
12354 || r_type == R_ARM_ALU_PC_G1_NC
12355 || r_type == R_ARM_ALU_PC_G0
12356 || r_type == R_ARM_ALU_PC_G1
12357 || r_type == R_ARM_ALU_PC_G2)
12358 /* PC relative. */
12359 signed_value = value - pc + signed_addend;
12360 else
12361 /* Section base relative. */
12362 signed_value = value - sb + signed_addend;
12363
12364 /* If the target symbol is a Thumb function, then set the
12365 Thumb bit in the address. */
35fc36a8 12366 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 12367 signed_value |= 1;
12368
99059e56
RM		 12369 /* Calculate the value of the relevant G_n, in encoded
12370 constant-with-rotation format. */
b6518b38
NC		 12371 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12372 group, &residual);
99059e56
RM		 12373
12374 /* Check for overflow if required. */
12375 if ((r_type == R_ARM_ALU_PC_G0
12376 || r_type == R_ARM_ALU_PC_G1
12377 || r_type == R_ARM_ALU_PC_G2
12378 || r_type == R_ARM_ALU_SB_G0
12379 || r_type == R_ARM_ALU_SB_G1
12380 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12381 {
4eca0228 12382 _bfd_error_handler
695344c0 12383 /* xgettext:c-format */
90b6238f 12384 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12385 "splitting %#" PRIx64 " for group relocation %s"),
12386 input_bfd, input_section, (uint64_t) rel->r_offset,
12387 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12388 howto->name);
99059e56
RM		 12389 return bfd_reloc_overflow;
12390 }
12391
12392 /* Mask out the value and the ADD/SUB part of the opcode; take care
12393 not to destroy the S bit. */
12394 insn &= 0xff1ff000;
12395
12396 /* Set the opcode according to whether the value to go in the
12397 place is negative. */
12398 if (signed_value < 0)
12399 insn |= 1 << 22;
12400 else
12401 insn |= 1 << 23;
12402
12403 /* Encode the offset. */
12404 insn |= g_n;
4962c51a
MS		 12405
12406 bfd_put_32 (input_bfd, insn, hit_data);
12407 }
12408 return bfd_reloc_ok;
12409
12410 case R_ARM_LDR_PC_G0:
12411 case R_ARM_LDR_PC_G1:
12412 case R_ARM_LDR_PC_G2:
12413 case R_ARM_LDR_SB_G0:
12414 case R_ARM_LDR_SB_G1:
12415 case R_ARM_LDR_SB_G2:
12416 {
12417 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12418 bfd_vma pc = input_section->output_section->vma
4962c51a 12419 + input_section->output_offset + rel->r_offset;
31a91d61 12420 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12421 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12422 bfd_vma residual;
4962c51a 12423 bfd_signed_vma signed_value;
99059e56
RM		 12424 int group = 0;
12425
12426 /* Determine which groups of bits to calculate. */
12427 switch (r_type)
12428 {
12429 case R_ARM_LDR_PC_G0:
12430 case R_ARM_LDR_SB_G0:
12431 group = 0;
12432 break;
12433
12434 case R_ARM_LDR_PC_G1:
12435 case R_ARM_LDR_SB_G1:
12436 group = 1;
12437 break;
12438
12439 case R_ARM_LDR_PC_G2:
12440 case R_ARM_LDR_SB_G2:
12441 group = 2;
12442 break;
12443
12444 default:
12445 abort ();
12446 }
12447
12448 /* If REL, extract the addend from the insn. If RELA, it will
12449 have already been fetched for us. */
4962c51a 12450 if (globals->use_rel)
99059e56
RM		 12451 {
12452 int negative = (insn & (1 << 23)) ? 1 : -1;
12453 signed_addend = negative * (insn & 0xfff);
12454 }
4962c51a
MS		 12455
12456 /* Compute the value (X) to go in the place. */
99059e56
RM		 12457 if (r_type == R_ARM_LDR_PC_G0
12458 || r_type == R_ARM_LDR_PC_G1
12459 || r_type == R_ARM_LDR_PC_G2)
12460 /* PC relative. */
12461 signed_value = value - pc + signed_addend;
12462 else
12463 /* Section base relative. */
12464 signed_value = value - sb + signed_addend;
12465
12466 /* Calculate the value of the relevant G_{n-1} to obtain
12467 the residual at that stage. */
b6518b38
NC		 12468 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12469 group - 1, &residual);
99059e56
RM		 12470
12471 /* Check for overflow. */
12472 if (residual >= 0x1000)
12473 {
4eca0228 12474 _bfd_error_handler
695344c0 12475 /* xgettext:c-format */
90b6238f 12476 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12477 "splitting %#" PRIx64 " for group relocation %s"),
12478 input_bfd, input_section, (uint64_t) rel->r_offset,
12479 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12480 howto->name);
99059e56
RM		 12481 return bfd_reloc_overflow;
12482 }
12483
12484 /* Mask out the value and U bit. */
12485 insn &= 0xff7ff000;
12486
12487 /* Set the U bit if the value to go in the place is non-negative. */
12488 if (signed_value >= 0)
12489 insn |= 1 << 23;
12490
12491 /* Encode the offset. */
12492 insn |= residual;
4962c51a
MS		 12493
12494 bfd_put_32 (input_bfd, insn, hit_data);
12495 }
12496 return bfd_reloc_ok;
12497
12498 case R_ARM_LDRS_PC_G0:
12499 case R_ARM_LDRS_PC_G1:
12500 case R_ARM_LDRS_PC_G2:
12501 case R_ARM_LDRS_SB_G0:
12502 case R_ARM_LDRS_SB_G1:
12503 case R_ARM_LDRS_SB_G2:
12504 {
12505 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12506 bfd_vma pc = input_section->output_section->vma
4962c51a 12507 + input_section->output_offset + rel->r_offset;
31a91d61 12508 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12509 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12510 bfd_vma residual;
4962c51a 12511 bfd_signed_vma signed_value;
99059e56
RM		 12512 int group = 0;
12513
12514 /* Determine which groups of bits to calculate. */
12515 switch (r_type)
12516 {
12517 case R_ARM_LDRS_PC_G0:
12518 case R_ARM_LDRS_SB_G0:
12519 group = 0;
12520 break;
12521
12522 case R_ARM_LDRS_PC_G1:
12523 case R_ARM_LDRS_SB_G1:
12524 group = 1;
12525 break;
12526
12527 case R_ARM_LDRS_PC_G2:
12528 case R_ARM_LDRS_SB_G2:
12529 group = 2;
12530 break;
12531
12532 default:
12533 abort ();
12534 }
12535
12536 /* If REL, extract the addend from the insn. If RELA, it will
12537 have already been fetched for us. */
4962c51a 12538 if (globals->use_rel)
99059e56
RM		 12539 {
12540 int negative = (insn & (1 << 23)) ? 1 : -1;
12541 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12542 }
4962c51a
MS		 12543
12544 /* Compute the value (X) to go in the place. */
99059e56
RM		 12545 if (r_type == R_ARM_LDRS_PC_G0
12546 || r_type == R_ARM_LDRS_PC_G1
12547 || r_type == R_ARM_LDRS_PC_G2)
12548 /* PC relative. */
12549 signed_value = value - pc + signed_addend;
12550 else
12551 /* Section base relative. */
12552 signed_value = value - sb + signed_addend;
12553
12554 /* Calculate the value of the relevant G_{n-1} to obtain
12555 the residual at that stage. */
b6518b38
NC		 12556 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12557 group - 1, &residual);
99059e56
RM		 12558
12559 /* Check for overflow. */
12560 if (residual >= 0x100)
12561 {
4eca0228 12562 _bfd_error_handler
695344c0 12563 /* xgettext:c-format */
90b6238f 12564 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12565 "splitting %#" PRIx64 " for group relocation %s"),
12566 input_bfd, input_section, (uint64_t) rel->r_offset,
12567 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12568 howto->name);
99059e56
RM		 12569 return bfd_reloc_overflow;
12570 }
12571
12572 /* Mask out the value and U bit. */
12573 insn &= 0xff7ff0f0;
12574
12575 /* Set the U bit if the value to go in the place is non-negative. */
12576 if (signed_value >= 0)
12577 insn |= 1 << 23;
12578
12579 /* Encode the offset. */
12580 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12581
12582 bfd_put_32 (input_bfd, insn, hit_data);
12583 }
12584 return bfd_reloc_ok;
12585
12586 case R_ARM_LDC_PC_G0:
12587 case R_ARM_LDC_PC_G1:
12588 case R_ARM_LDC_PC_G2:
12589 case R_ARM_LDC_SB_G0:
12590 case R_ARM_LDC_SB_G1:
12591 case R_ARM_LDC_SB_G2:
12592 {
12593 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12594 bfd_vma pc = input_section->output_section->vma
4962c51a 12595 + input_section->output_offset + rel->r_offset;
31a91d61 12596 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12597 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12598 bfd_vma residual;
4962c51a 12599 bfd_signed_vma signed_value;
99059e56
RM		 12600 int group = 0;
12601
12602 /* Determine which groups of bits to calculate. */
12603 switch (r_type)
12604 {
12605 case R_ARM_LDC_PC_G0:
12606 case R_ARM_LDC_SB_G0:
12607 group = 0;
12608 break;
12609
12610 case R_ARM_LDC_PC_G1:
12611 case R_ARM_LDC_SB_G1:
12612 group = 1;
12613 break;
12614
12615 case R_ARM_LDC_PC_G2:
12616 case R_ARM_LDC_SB_G2:
12617 group = 2;
12618 break;
12619
12620 default:
12621 abort ();
12622 }
12623
12624 /* If REL, extract the addend from the insn. If RELA, it will
12625 have already been fetched for us. */
4962c51a 12626 if (globals->use_rel)
99059e56
RM		 12627 {
12628 int negative = (insn & (1 << 23)) ? 1 : -1;
12629 signed_addend = negative * ((insn & 0xff) << 2);
12630 }
4962c51a
MS		 12631
12632 /* Compute the value (X) to go in the place. */
99059e56
RM		 12633 if (r_type == R_ARM_LDC_PC_G0
12634 || r_type == R_ARM_LDC_PC_G1
12635 || r_type == R_ARM_LDC_PC_G2)
12636 /* PC relative. */
12637 signed_value = value - pc + signed_addend;
12638 else
12639 /* Section base relative. */
12640 signed_value = value - sb + signed_addend;
12641
12642 /* Calculate the value of the relevant G_{n-1} to obtain
12643 the residual at that stage. */
b6518b38
NC		 12644 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12645 group - 1, &residual);
99059e56
RM		 12646
12647 /* Check for overflow. (The absolute value to go in the place must be
12648 divisible by four and, after having been divided by four, must
12649 fit in eight bits.) */
12650 if ((residual & 0x3) != 0 || residual >= 0x400)
12651 {
4eca0228 12652 _bfd_error_handler
695344c0 12653 /* xgettext:c-format */
90b6238f 12654 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12655 "splitting %#" PRIx64 " for group relocation %s"),
12656 input_bfd, input_section, (uint64_t) rel->r_offset,
12657 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12658 howto->name);
99059e56
RM		 12659 return bfd_reloc_overflow;
12660 }
12661
12662 /* Mask out the value and U bit. */
12663 insn &= 0xff7fff00;
12664
12665 /* Set the U bit if the value to go in the place is non-negative. */
12666 if (signed_value >= 0)
12667 insn |= 1 << 23;
12668
12669 /* Encode the offset. */
12670 insn |= residual >> 2;
4962c51a
MS		 12671
12672 bfd_put_32 (input_bfd, insn, hit_data);
12673 }
12674 return bfd_reloc_ok;
12675
72d98d16
MG		 12676 case R_ARM_THM_ALU_ABS_G0_NC:
12677 case R_ARM_THM_ALU_ABS_G1_NC:
12678 case R_ARM_THM_ALU_ABS_G2_NC:
12679 case R_ARM_THM_ALU_ABS_G3_NC:
12680 {
12681 const int shift_array[4] = {0, 8, 16, 24};
12682 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12683 bfd_vma addr = value;
12684 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12685
12686 /* Compute address. */
12687 if (globals->use_rel)
12688 signed_addend = insn & 0xff;
12689 addr += signed_addend;
12690 if (branch_type == ST_BRANCH_TO_THUMB)
12691 addr |= 1;
12692 /* Clean imm8 insn. */
12693 insn &= 0xff00;
12694 /* And update with correct part of address. */
12695 insn |= (addr >> shift) & 0xff;
12696 /* Update insn. */
12697 bfd_put_16 (input_bfd, insn, hit_data);
12698 }
12699
12700 *unresolved_reloc_p = FALSE;
12701 return bfd_reloc_ok;
12702
e8b09b87
CL		 12703 case R_ARM_GOTOFFFUNCDESC:
12704 {
4b24dd1a 12705 if (h == NULL)
e8b09b87
CL		 12706 {
12707 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12708 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12709 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12710 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12711 bfd_vma seg = -1;
12712
12713 if (bfd_link_pic(info) && dynindx == 0)
12714 abort();
12715
12716 /* Resolve relocation. */
12717 bfd_put_32(output_bfd, (offset + sgot->output_offset)
12718 , contents + rel->r_offset);
12719 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12720 not done yet. */
12721 arm_elf_fill_funcdesc(output_bfd, info,
12722 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12723 dynindx, offset, addr, dynreloc_value, seg);
12724 }
12725 else
12726 {
12727 int dynindx;
12728 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12729 bfd_vma addr;
12730 bfd_vma seg = -1;
12731
12732 /* For static binaries, sym_sec can be null. */
12733 if (sym_sec)
12734 {
12735 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12736 addr = dynreloc_value - sym_sec->output_section->vma;
12737 }
12738 else
12739 {
12740 dynindx = 0;
12741 addr = 0;
12742 }
12743
12744 if (bfd_link_pic(info) && dynindx == 0)
12745 abort();
12746
12747 /* This case cannot occur since funcdesc is allocated by
12748 the dynamic loader so we cannot resolve the relocation. */
12749 if (h->dynindx != -1)
12750 abort();
12751
12752 /* Resolve relocation. */
12753 bfd_put_32(output_bfd, (offset + sgot->output_offset),
12754 contents + rel->r_offset);
12755 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12756 arm_elf_fill_funcdesc(output_bfd, info,
12757 &eh->fdpic_cnts.funcdesc_offset,
12758 dynindx, offset, addr, dynreloc_value, seg);
12759 }
12760 }
12761 *unresolved_reloc_p = FALSE;
12762 return bfd_reloc_ok;
12763
12764 case R_ARM_GOTFUNCDESC:
12765 {
4b24dd1a 12766 if (h != NULL)
e8b09b87
CL		 12767 {
12768 Elf_Internal_Rela outrel;
12769
12770 /* Resolve relocation. */
12771 bfd_put_32(output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12772 + sgot->output_offset),
12773 contents + rel->r_offset);
12774 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12775 if(h->dynindx == -1)
12776 {
12777 int dynindx;
12778 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12779 bfd_vma addr;
12780 bfd_vma seg = -1;
12781
12782 /* For static binaries sym_sec can be null. */
12783 if (sym_sec)
12784 {
12785 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12786 addr = dynreloc_value - sym_sec->output_section->vma;
12787 }
12788 else
12789 {
12790 dynindx = 0;
12791 addr = 0;
12792 }
12793
12794 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12795 arm_elf_fill_funcdesc(output_bfd, info,
12796 &eh->fdpic_cnts.funcdesc_offset,
12797 dynindx, offset, addr, dynreloc_value, seg);
12798 }
12799
12800 /* Add a dynamic relocation on GOT entry if not already done. */
12801 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12802 {
12803 if (h->dynindx == -1)
12804 {
12805 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12806 if (h->root.type == bfd_link_hash_undefweak)
12807 bfd_put_32(output_bfd, 0, sgot->contents
12808 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12809 else
12810 bfd_put_32(output_bfd, sgot->output_section->vma
12811 + sgot->output_offset
12812 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12813 sgot->contents
12814 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12815 }
12816 else
12817 {
12818 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12819 }
12820 outrel.r_offset = sgot->output_section->vma
12821 + sgot->output_offset
12822 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12823 outrel.r_addend = 0;
12824 if (h->dynindx == -1 && !bfd_link_pic(info))
12825 if (h->root.type == bfd_link_hash_undefweak)
4b24dd1a 12826 arm_elf_add_rofixup(output_bfd, globals->srofixup, -1);
e8b09b87 12827 else
4b24dd1a
AM		 12828 arm_elf_add_rofixup(output_bfd, globals->srofixup,
12829 outrel.r_offset);
e8b09b87
CL		 12830 else
12831 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12832 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12833 }
12834 }
12835 else
12836 {
12837 /* Such relocation on static function should not have been
12838 emitted by the compiler. */
12839 abort();
12840 }
12841 }
12842 *unresolved_reloc_p = FALSE;
12843 return bfd_reloc_ok;
12844
12845 case R_ARM_FUNCDESC:
12846 {
4b24dd1a 12847 if (h == NULL)
e8b09b87
CL		 12848 {
12849 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12850 Elf_Internal_Rela outrel;
12851 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12852 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12853 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12854 bfd_vma seg = -1;
12855
12856 if (bfd_link_pic(info) && dynindx == 0)
12857 abort();
12858
12859 /* Replace static FUNCDESC relocation with a
12860 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12861 executable. */
12862 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12863 outrel.r_offset = input_section->output_section->vma
12864 + input_section->output_offset + rel->r_offset;
12865 outrel.r_addend = 0;
12866 if (bfd_link_pic(info))
12867 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12868 else
12869 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12870
12871 bfd_put_32 (input_bfd, sgot->output_section->vma
12872 + sgot->output_offset + offset, hit_data);
12873
12874 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12875 arm_elf_fill_funcdesc(output_bfd, info,
12876 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12877 dynindx, offset, addr, dynreloc_value, seg);
12878 }
12879 else
12880 {
12881 if (h->dynindx == -1)
12882 {
12883 int dynindx;
12884 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12885 bfd_vma addr;
12886 bfd_vma seg = -1;
12887 Elf_Internal_Rela outrel;
12888
12889 /* For static binaries sym_sec can be null. */
12890 if (sym_sec)
12891 {
12892 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12893 addr = dynreloc_value - sym_sec->output_section->vma;
12894 }
12895 else
12896 {
12897 dynindx = 0;
12898 addr = 0;
12899 }
12900
12901 if (bfd_link_pic(info) && dynindx == 0)
12902 abort();
12903
12904 /* Replace static FUNCDESC relocation with a
12905 R_ARM_RELATIVE dynamic relocation. */
12906 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12907 outrel.r_offset = input_section->output_section->vma
12908 + input_section->output_offset + rel->r_offset;
12909 outrel.r_addend = 0;
12910 if (bfd_link_pic(info))
12911 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12912 else
12913 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12914
12915 bfd_put_32 (input_bfd, sgot->output_section->vma
12916 + sgot->output_offset + offset, hit_data);
12917
12918 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12919 arm_elf_fill_funcdesc(output_bfd, info,
12920 &eh->fdpic_cnts.funcdesc_offset,
12921 dynindx, offset, addr, dynreloc_value, seg);
12922 }
12923 else
12924 {
12925 Elf_Internal_Rela outrel;
12926
12927 /* Add a dynamic relocation. */
12928 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12929 outrel.r_offset = input_section->output_section->vma
12930 + input_section->output_offset + rel->r_offset;
12931 outrel.r_addend = 0;
12932 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12933 }
12934 }
12935 }
12936 *unresolved_reloc_p = FALSE;
12937 return bfd_reloc_ok;
12938
e5d6e09e
AV		 12939 case R_ARM_THM_BF16:
12940 {
12941 bfd_vma relocation;
12942 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12943 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12944
12945 if (globals->use_rel)
12946 {
12947 bfd_vma immA = (upper_insn & 0x001f);
12948 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12949 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12950 addend = (immA << 12);
12951 addend |= (immB << 2);
12952 addend |= (immC << 1);
12953 addend |= 1;
12954 /* Sign extend. */
e6f65e75 12955 signed_addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
e5d6e09e
AV		 12956 }
12957
e6f65e75 12958 relocation = value + signed_addend;
e5d6e09e
AV		 12959 relocation -= (input_section->output_section->vma
12960 + input_section->output_offset
12961 + rel->r_offset);
12962
12963 /* Put RELOCATION back into the insn. */
12964 {
12965 bfd_vma immA = (relocation & 0x0001f000) >> 12;
12966 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12967 bfd_vma immC = (relocation & 0x00000002) >> 1;
12968
12969 upper_insn = (upper_insn & 0xffe0) | immA;
12970 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12971 }
12972
12973 /* Put the relocated value back in the object file: */
12974 bfd_put_16 (input_bfd, upper_insn, hit_data);
12975 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12976
12977 return bfd_reloc_ok;
12978 }
12979
1889da70
AV		 12980 case R_ARM_THM_BF12:
12981 {
12982 bfd_vma relocation;
12983 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12984 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12985
12986 if (globals->use_rel)
12987 {
12988 bfd_vma immA = (upper_insn & 0x0001);
12989 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12990 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12991 addend = (immA << 12);
12992 addend |= (immB << 2);
12993 addend |= (immC << 1);
12994 addend |= 1;
12995 /* Sign extend. */
12996 addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
e6f65e75 12997 signed_addend = addend;
1889da70
AV		 12998 }
12999
e6f65e75 13000 relocation = value + signed_addend;
1889da70
AV		 13001 relocation -= (input_section->output_section->vma
13002 + input_section->output_offset
13003 + rel->r_offset);
13004
13005 /* Put RELOCATION back into the insn. */
13006 {
13007 bfd_vma immA = (relocation & 0x00001000) >> 12;
13008 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13009 bfd_vma immC = (relocation & 0x00000002) >> 1;
13010
13011 upper_insn = (upper_insn & 0xfffe) | immA;
13012 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13013 }
13014
13015 /* Put the relocated value back in the object file: */
13016 bfd_put_16 (input_bfd, upper_insn, hit_data);
13017 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13018
13019 return bfd_reloc_ok;
13020 }
13021
1caf72a5
AV		 13022 case R_ARM_THM_BF18:
13023 {
13024 bfd_vma relocation;
13025 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
13026 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
13027
13028 if (globals->use_rel)
13029 {
13030 bfd_vma immA = (upper_insn & 0x007f);
13031 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
13032 bfd_vma immC = (lower_insn & 0x0800) >> 11;
13033 addend = (immA << 12);
13034 addend |= (immB << 2);
13035 addend |= (immC << 1);
13036 addend |= 1;
13037 /* Sign extend. */
13038 addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
e6f65e75 13039 signed_addend = addend;
1caf72a5
AV		 13040 }
13041
e6f65e75 13042 relocation = value + signed_addend;
1caf72a5
AV		 13043 relocation -= (input_section->output_section->vma
13044 + input_section->output_offset
13045 + rel->r_offset);
13046
13047 /* Put RELOCATION back into the insn. */
13048 {
13049 bfd_vma immA = (relocation & 0x0007f000) >> 12;
13050 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13051 bfd_vma immC = (relocation & 0x00000002) >> 1;
13052
13053 upper_insn = (upper_insn & 0xff80) | immA;
13054 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13055 }
13056
13057 /* Put the relocated value back in the object file: */
13058 bfd_put_16 (input_bfd, upper_insn, hit_data);
13059 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13060
13061 return bfd_reloc_ok;
13062 }
13063
252b5132
RH		 13064 default:
13065 return bfd_reloc_notsupported;
13066 }
13067}
13068
98c1d4aa
NC		 13069/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13070static void
07d6d2b8
AM		 13071arm_add_to_rel (bfd * abfd,
13072 bfd_byte * address,
57e8b36a 13073 reloc_howto_type * howto,
07d6d2b8 13074 bfd_signed_vma increment)
98c1d4aa 13075{
98c1d4aa
NC		 13076 bfd_signed_vma addend;
13077
bd97cb95
DJ		 13078 if (howto->type == R_ARM_THM_CALL
13079 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 13080 {
9a5aca8c
AM		 13081 int upper_insn, lower_insn;
13082 int upper, lower;
98c1d4aa 13083
9a5aca8c
AM		 13084 upper_insn = bfd_get_16 (abfd, address);
13085 lower_insn = bfd_get_16 (abfd, address + 2);
13086 upper = upper_insn & 0x7ff;
13087 lower = lower_insn & 0x7ff;
13088
13089 addend = (upper << 12) | (lower << 1);
ddda4409 13090 addend += increment;
9a5aca8c 13091 addend >>= 1;
98c1d4aa 13092
9a5aca8c
AM		 13093 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
13094 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
13095
dc810e39
AM		 13096 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
13097 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 13098 }
13099 else
13100 {
07d6d2b8 13101 bfd_vma contents;
9a5aca8c
AM		 13102
13103 contents = bfd_get_32 (abfd, address);
13104
13105 /* Get the (signed) value from the instruction. */
13106 addend = contents & howto->src_mask;
13107 if (addend & ((howto->src_mask + 1) >> 1))
13108 {
13109 bfd_signed_vma mask;
13110
13111 mask = -1;
13112 mask &= ~ howto->src_mask;
13113 addend |= mask;
13114 }
13115
13116 /* Add in the increment, (which is a byte value). */
13117 switch (howto->type)
13118 {
13119 default:
13120 addend += increment;
13121 break;
13122
13123 case R_ARM_PC24:
c6596c5e 13124 case R_ARM_PLT32:
5b5bb741
PB		 13125 case R_ARM_CALL:
13126 case R_ARM_JUMP24:
9a5aca8c 13127 addend <<= howto->size;
dc810e39 13128 addend += increment;
9a5aca8c
AM		 13129
13130 /* Should we check for overflow here ? */
13131
13132 /* Drop any undesired bits. */
13133 addend >>= howto->rightshift;
13134 break;
13135 }
13136
13137 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
13138
13139 bfd_put_32 (abfd, contents, address);
ddda4409 13140 }
98c1d4aa 13141}
252b5132 13142
ba93b8ac
DJ		 13143#define IS_ARM_TLS_RELOC(R_TYPE) \
13144 ((R_TYPE) == R_ARM_TLS_GD32 \
5c5a4843 13145 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
ba93b8ac
DJ		 13146 || (R_TYPE) == R_ARM_TLS_LDO32 \
13147 || (R_TYPE) == R_ARM_TLS_LDM32 \
5c5a4843 13148 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
ba93b8ac
DJ		 13149 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13150 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13151 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13152 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b 13153 || (R_TYPE) == R_ARM_TLS_IE32 \
5c5a4843 13154 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
0855e32b
NS		 13155 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13156
13157/* Specific set of relocations for the gnu tls dialect. */
13158#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13159 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13160 || (R_TYPE) == R_ARM_TLS_CALL \
13161 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13162 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13163 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 13164
252b5132 13165/* Relocate an ARM ELF section. */
906e58ca 13166
b34976b6 13167static bfd_boolean
07d6d2b8 13168elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 13169 struct bfd_link_info * info,
07d6d2b8
AM		 13170 bfd * input_bfd,
13171 asection * input_section,
13172 bfd_byte * contents,
13173 Elf_Internal_Rela * relocs,
13174 Elf_Internal_Sym * local_syms,
13175 asection ** local_sections)
252b5132 13176{
b34976b6
AM		 13177 Elf_Internal_Shdr *symtab_hdr;
13178 struct elf_link_hash_entry **sym_hashes;
13179 Elf_Internal_Rela *rel;
13180 Elf_Internal_Rela *relend;
13181 const char *name;
b32d3aa2 13182 struct elf32_arm_link_hash_table * globals;
252b5132 13183
4e7fd91e 13184 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13185 if (globals == NULL)
13186 return FALSE;
b491616a 13187
0ffa91dd 13188 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 13189 sym_hashes = elf_sym_hashes (input_bfd);
13190
13191 rel = relocs;
13192 relend = relocs + input_section->reloc_count;
13193 for (; rel < relend; rel++)
13194 {
07d6d2b8
AM		 13195 int r_type;
13196 reloc_howto_type * howto;
13197 unsigned long r_symndx;
13198 Elf_Internal_Sym * sym;
13199 asection * sec;
252b5132 13200 struct elf_link_hash_entry * h;
07d6d2b8
AM		 13201 bfd_vma relocation;
13202 bfd_reloc_status_type r;
13203 arelent bfd_reloc;
13204 char sym_type;
13205 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 13206 char *error_message = NULL;
f21f3fe0 13207
252b5132 13208 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 13209 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 13210 r_type = arm_real_reloc_type (globals, r_type);
252b5132 13211
ba96a88f 13212 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 13213 || r_type == R_ARM_GNU_VTINHERIT)
13214 continue;
252b5132 13215
47aeb64c
NC		 13216 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
13217
13218 if (howto == NULL)
13219 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 13220
252b5132
RH		 13221 h = NULL;
13222 sym = NULL;
13223 sec = NULL;
9b485d32 13224
252b5132
RH		 13225 if (r_symndx < symtab_hdr->sh_info)
13226 {
13227 sym = local_syms + r_symndx;
ba93b8ac 13228 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 13229 sec = local_sections[r_symndx];
ffcb4889
NS		 13230
13231 /* An object file might have a reference to a local
13232 undefined symbol. This is a daft object file, but we
13233 should at least do something about it. V4BX & NONE
13234 relocations do not use the symbol and are explicitly
77b4f08f
TS		 13235 allowed to use the undefined symbol, so allow those.
13236 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 13237 if (r_type != R_ARM_V4BX
13238 && r_type != R_ARM_NONE
77b4f08f 13239 && r_symndx != STN_UNDEF
ffcb4889
NS		 13240 && bfd_is_und_section (sec)
13241 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 13242 (*info->callbacks->undefined_symbol)
13243 (info, bfd_elf_string_from_elf_section
13244 (input_bfd, symtab_hdr->sh_link, sym->st_name),
13245 input_bfd, input_section,
13246 rel->r_offset, TRUE);
b38cadfb 13247
4e7fd91e 13248 if (globals->use_rel)
f8df10f4 13249 {
4e7fd91e
PB		 13250 relocation = (sec->output_section->vma
13251 + sec->output_offset
13252 + sym->st_value);
0e1862bb 13253 if (!bfd_link_relocatable (info)
ab96bf03
AM		 13254 && (sec->flags & SEC_MERGE)
13255 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 13256 {
4e7fd91e
PB		 13257 asection *msec;
13258 bfd_vma addend, value;
13259
39623e12 13260 switch (r_type)
4e7fd91e 13261 {
39623e12
PB		 13262 case R_ARM_MOVW_ABS_NC:
13263 case R_ARM_MOVT_ABS:
13264 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13265 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13266 addend = (addend ^ 0x8000) - 0x8000;
13267 break;
f8df10f4 13268
39623e12
PB		 13269 case R_ARM_THM_MOVW_ABS_NC:
13270 case R_ARM_THM_MOVT_ABS:
13271 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13272 << 16;
13273 value |= bfd_get_16 (input_bfd,
13274 contents + rel->r_offset + 2);
13275 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13276 | ((value & 0x04000000) >> 15);
13277 addend = (addend ^ 0x8000) - 0x8000;
13278 break;
f8df10f4 13279
39623e12
PB		 13280 default:
13281 if (howto->rightshift
13282 || (howto->src_mask & (howto->src_mask + 1)))
13283 {
4eca0228 13284 _bfd_error_handler
695344c0 13285 /* xgettext:c-format */
2dcf00ce
AM		 13286 (_("%pB(%pA+%#" PRIx64 "): "
13287 "%s relocation against SEC_MERGE section"),
39623e12 13288 input_bfd, input_section,
2dcf00ce 13289 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 13290 return FALSE;
13291 }
13292
13293 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13294
13295 /* Get the (signed) value from the instruction. */
13296 addend = value & howto->src_mask;
13297 if (addend & ((howto->src_mask + 1) >> 1))
13298 {
13299 bfd_signed_vma mask;
13300
13301 mask = -1;
13302 mask &= ~ howto->src_mask;
13303 addend |= mask;
13304 }
13305 break;
4e7fd91e 13306 }
39623e12 13307
4e7fd91e
PB		 13308 msec = sec;
13309 addend =
13310 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13311 - relocation;
13312 addend += msec->output_section->vma + msec->output_offset;
39623e12 13313
cc643b88 13314 /* Cases here must match those in the preceding
39623e12
PB		 13315 switch statement. */
13316 switch (r_type)
13317 {
13318 case R_ARM_MOVW_ABS_NC:
13319 case R_ARM_MOVT_ABS:
13320 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13321 | (addend & 0xfff);
13322 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13323 break;
13324
13325 case R_ARM_THM_MOVW_ABS_NC:
13326 case R_ARM_THM_MOVT_ABS:
13327 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13328 | (addend & 0xff) | ((addend & 0x0800) << 15);
13329 bfd_put_16 (input_bfd, value >> 16,
13330 contents + rel->r_offset);
13331 bfd_put_16 (input_bfd, value,
13332 contents + rel->r_offset + 2);
13333 break;
13334
13335 default:
13336 value = (value & ~ howto->dst_mask)
13337 | (addend & howto->dst_mask);
13338 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13339 break;
13340 }
f8df10f4 13341 }
f8df10f4 13342 }
4e7fd91e
PB		 13343 else
13344 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 13345 }
13346 else
13347 {
62d887d4 13348 bfd_boolean warned, ignored;
560e09e9 13349
b2a8e766
AM		 13350 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13351 r_symndx, symtab_hdr, sym_hashes,
13352 h, sec, relocation,
62d887d4 13353 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 13354
13355 sym_type = h->type;
252b5132
RH		 13356 }
13357
dbaa2011 13358 if (sec != NULL && discarded_section (sec))
e4067dbb 13359 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 13360 rel, 1, relend, howto, 0, contents);
ab96bf03 13361
0e1862bb 13362 if (bfd_link_relocatable (info))
ab96bf03
AM		 13363 {
13364 /* This is a relocatable link. We don't have to change
13365 anything, unless the reloc is against a section symbol,
13366 in which case we have to adjust according to where the
13367 section symbol winds up in the output section. */
13368 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13369 {
13370 if (globals->use_rel)
13371 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13372 howto, (bfd_signed_vma) sec->output_offset);
13373 else
13374 rel->r_addend += sec->output_offset;
13375 }
13376 continue;
13377 }
13378
252b5132
RH		 13379 if (h != NULL)
13380 name = h->root.root.string;
13381 else
13382 {
13383 name = (bfd_elf_string_from_elf_section
13384 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13385 if (name == NULL || *name == '\0')
fd361982 13386 name = bfd_section_name (sec);
252b5132 13387 }
f21f3fe0 13388
cf35638d 13389 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 13390 && r_type != R_ARM_NONE
13391 && (h == NULL
13392 || h->root.type == bfd_link_hash_defined
13393 || h->root.type == bfd_link_hash_defweak)
13394 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13395 {
4eca0228 13396 _bfd_error_handler
ba93b8ac 13397 ((sym_type == STT_TLS
695344c0 13398 /* xgettext:c-format */
2dcf00ce 13399 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 13400 /* xgettext:c-format */
2dcf00ce 13401 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 13402 input_bfd,
13403 input_section,
2dcf00ce 13404 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 13405 howto->name,
13406 name);
13407 }
13408
0855e32b 13409 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 13410 done, i.e., the relaxation produced the final output we want,
13411 and we won't let anybody mess with it. Also, we have to do
13412 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 13413 both in relaxed and non-relaxed cases. */
39d911fc
TP		 13414 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13415 || (IS_ARM_TLS_GNU_RELOC (r_type)
13416 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13417 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13418 & GOT_TLS_GDESC)))
13419 {
13420 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13421 contents, rel, h == NULL);
13422 /* This may have been marked unresolved because it came from
13423 a shared library. But we've just dealt with that. */
13424 unresolved_reloc = 0;
13425 }
13426 else
13427 r = bfd_reloc_continue;
b38cadfb 13428
39d911fc
TP		 13429 if (r == bfd_reloc_continue)
13430 {
13431 unsigned char branch_type =
13432 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13433 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13434
13435 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13436 input_section, contents, rel,
13437 relocation, info, sec, name,
13438 sym_type, branch_type, h,
13439 &unresolved_reloc,
13440 &error_message);
13441 }
0945cdfd
DJ		 13442
13443 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13444 because such sections are not SEC_ALLOC and thus ld.so will
13445 not process them. */
13446 if (unresolved_reloc
99059e56
RM		 13447 && !((input_section->flags & SEC_DEBUGGING) != 0
13448 && h->def_dynamic)
1d5316ab
AM		 13449 && _bfd_elf_section_offset (output_bfd, info, input_section,
13450 rel->r_offset) != (bfd_vma) -1)
0945cdfd 13451 {
4eca0228 13452 _bfd_error_handler
695344c0 13453 /* xgettext:c-format */
2dcf00ce
AM		 13454 (_("%pB(%pA+%#" PRIx64 "): "
13455 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 13456 input_bfd,
13457 input_section,
2dcf00ce 13458 (uint64_t) rel->r_offset,
843fe662
L		 13459 howto->name,
13460 h->root.root.string);
0945cdfd
DJ		 13461 return FALSE;
13462 }
252b5132
RH		 13463
13464 if (r != bfd_reloc_ok)
13465 {
252b5132
RH		 13466 switch (r)
13467 {
13468 case bfd_reloc_overflow:
cf919dfd
PB		 13469 /* If the overflowing reloc was to an undefined symbol,
13470 we have already printed one error message and there
13471 is no point complaining again. */
1a72702b
AM		 13472 if (!h || h->root.type != bfd_link_hash_undefined)
13473 (*info->callbacks->reloc_overflow)
13474 (info, (h ? &h->root : NULL), name, howto->name,
13475 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13476 break;
13477
13478 case bfd_reloc_undefined:
1a72702b
AM		 13479 (*info->callbacks->undefined_symbol)
13480 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 13481 break;
13482
13483 case bfd_reloc_outofrange:
f2a9dd69 13484 error_message = _("out of range");
252b5132
RH		 13485 goto common_error;
13486
13487 case bfd_reloc_notsupported:
f2a9dd69 13488 error_message = _("unsupported relocation");
252b5132
RH		 13489 goto common_error;
13490
13491 case bfd_reloc_dangerous:
f2a9dd69 13492 /* error_message should already be set. */
252b5132
RH		 13493 goto common_error;
13494
13495 default:
f2a9dd69 13496 error_message = _("unknown error");
8029a119 13497 /* Fall through. */
252b5132
RH		 13498
13499 common_error:
f2a9dd69 13500 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 13501 (*info->callbacks->reloc_dangerous)
13502 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13503 break;
13504 }
13505 }
13506 }
13507
b34976b6 13508 return TRUE;
252b5132
RH		 13509}
13510
91d6fa6a 13511/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 13512 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 13513 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 13514 maintaining that condition). */
13515
13516static void
13517add_unwind_table_edit (arm_unwind_table_edit **head,
13518 arm_unwind_table_edit **tail,
13519 arm_unwind_edit_type type,
13520 asection *linked_section,
91d6fa6a 13521 unsigned int tindex)
2468f9c9 13522{
21d799b5
NC		 13523 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13524 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 13525
2468f9c9
PB		 13526 new_edit->type = type;
13527 new_edit->linked_section = linked_section;
91d6fa6a 13528 new_edit->index = tindex;
b38cadfb 13529
91d6fa6a 13530 if (tindex > 0)
2468f9c9
PB		 13531 {
13532 new_edit->next = NULL;
13533
13534 if (*tail)
13535 (*tail)->next = new_edit;
13536
13537 (*tail) = new_edit;
13538
13539 if (!*head)
13540 (*head) = new_edit;
13541 }
13542 else
13543 {
13544 new_edit->next = *head;
13545
13546 if (!*tail)
13547 *tail = new_edit;
13548
13549 *head = new_edit;
13550 }
13551}
13552
13553static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13554
13555/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13556static void
13557adjust_exidx_size(asection *exidx_sec, int adjust)
13558{
13559 asection *out_sec;
13560
13561 if (!exidx_sec->rawsize)
13562 exidx_sec->rawsize = exidx_sec->size;
13563
fd361982 13564 bfd_set_section_size (exidx_sec, exidx_sec->size + adjust);
2468f9c9
PB		 13565 out_sec = exidx_sec->output_section;
13566 /* Adjust size of output section. */
fd361982 13567 bfd_set_section_size (out_sec, out_sec->size +adjust);
2468f9c9
PB		 13568}
13569
13570/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13571static void
13572insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
13573{
13574 struct _arm_elf_section_data *exidx_arm_data;
13575
13576 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13577 add_unwind_table_edit (
13578 &exidx_arm_data->u.exidx.unwind_edit_list,
13579 &exidx_arm_data->u.exidx.unwind_edit_tail,
13580 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13581
491d01d3
YU		 13582 exidx_arm_data->additional_reloc_count++;
13583
2468f9c9
PB		 13584 adjust_exidx_size(exidx_sec, 8);
13585}
13586
13587/* Scan .ARM.exidx tables, and create a list describing edits which should be
13588 made to those tables, such that:
b38cadfb 13589
2468f9c9
PB		 13590 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13591 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 13592 codes which have been inlined into the index).
2468f9c9 13593
85fdf906
AH		 13594 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13595
2468f9c9 13596 The edits are applied when the tables are written
b38cadfb 13597 (in elf32_arm_write_section). */
2468f9c9
PB		 13598
13599bfd_boolean
13600elf32_arm_fix_exidx_coverage (asection **text_section_order,
13601 unsigned int num_text_sections,
85fdf906
AH		 13602 struct bfd_link_info *info,
13603 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 13604{
13605 bfd *inp;
13606 unsigned int last_second_word = 0, i;
13607 asection *last_exidx_sec = NULL;
13608 asection *last_text_sec = NULL;
13609 int last_unwind_type = -1;
13610
13611 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13612 text sections. */
c72f2fb2 13613 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 13614 {
13615 asection *sec;
b38cadfb 13616
2468f9c9 13617 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 13618 {
2468f9c9
PB		 13619 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13620 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 13621
dec9d5df 13622 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 13623 continue;
b38cadfb 13624
2468f9c9
PB		 13625 if (elf_sec->linked_to)
13626 {
13627 Elf_Internal_Shdr *linked_hdr
99059e56 13628 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 13629 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 13630 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 13631
13632 if (linked_sec_arm_data == NULL)
99059e56 13633 continue;
2468f9c9
PB		 13634
13635 /* Link this .ARM.exidx section back from the text section it
99059e56 13636 describes. */
2468f9c9
PB		 13637 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13638 }
13639 }
13640 }
13641
13642 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13643 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 13644 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 13645
13646 for (i = 0; i < num_text_sections; i++)
13647 {
13648 asection *sec = text_section_order[i];
13649 asection *exidx_sec;
13650 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13651 struct _arm_elf_section_data *exidx_arm_data;
13652 bfd_byte *contents = NULL;
13653 int deleted_exidx_bytes = 0;
13654 bfd_vma j;
13655 arm_unwind_table_edit *unwind_edit_head = NULL;
13656 arm_unwind_table_edit *unwind_edit_tail = NULL;
13657 Elf_Internal_Shdr *hdr;
13658 bfd *ibfd;
13659
13660 if (arm_data == NULL)
99059e56 13661 continue;
2468f9c9
PB		 13662
13663 exidx_sec = arm_data->u.text.arm_exidx_sec;
13664 if (exidx_sec == NULL)
13665 {
13666 /* Section has no unwind data. */
13667 if (last_unwind_type == 0 || !last_exidx_sec)
13668 continue;
13669
13670 /* Ignore zero sized sections. */
13671 if (sec->size == 0)
13672 continue;
13673
13674 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13675 last_unwind_type = 0;
13676 continue;
13677 }
13678
22a8f80e
PB		 13679 /* Skip /DISCARD/ sections. */
13680 if (bfd_is_abs_section (exidx_sec->output_section))
13681 continue;
13682
2468f9c9
PB		 13683 hdr = &elf_section_data (exidx_sec)->this_hdr;
13684 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 13685 continue;
b38cadfb 13686
2468f9c9
PB		 13687 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13688 if (exidx_arm_data == NULL)
99059e56 13689 continue;
b38cadfb 13690
2468f9c9 13691 ibfd = exidx_sec->owner;
b38cadfb 13692
2468f9c9
PB		 13693 if (hdr->contents != NULL)
13694 contents = hdr->contents;
13695 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13696 /* An error? */
13697 continue;
13698
ac06903d
YU		 13699 if (last_unwind_type > 0)
13700 {
13701 unsigned int first_word = bfd_get_32 (ibfd, contents);
13702 /* Add cantunwind if first unwind item does not match section
13703 start. */
13704 if (first_word != sec->vma)
13705 {
13706 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13707 last_unwind_type = 0;
13708 }
13709 }
13710
2468f9c9
PB		 13711 for (j = 0; j < hdr->sh_size; j += 8)
13712 {
13713 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13714 int unwind_type;
13715 int elide = 0;
13716
13717 /* An EXIDX_CANTUNWIND entry. */
13718 if (second_word == 1)
13719 {
13720 if (last_unwind_type == 0)
13721 elide = 1;
13722 unwind_type = 0;
13723 }
13724 /* Inlined unwinding data. Merge if equal to previous. */
13725 else if ((second_word & 0x80000000) != 0)
13726 {
85fdf906
AH		 13727 if (merge_exidx_entries
13728 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 13729 elide = 1;
13730 unwind_type = 1;
13731 last_second_word = second_word;
13732 }
13733 /* Normal table entry. In theory we could merge these too,
13734 but duplicate entries are likely to be much less common. */
13735 else
13736 unwind_type = 2;
13737
491d01d3 13738 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 13739 {
13740 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13741 DELETE_EXIDX_ENTRY, NULL, j / 8);
13742
13743 deleted_exidx_bytes += 8;
13744 }
13745
13746 last_unwind_type = unwind_type;
13747 }
13748
13749 /* Free contents if we allocated it ourselves. */
13750 if (contents != hdr->contents)
99059e56 13751 free (contents);
2468f9c9
PB		 13752
13753 /* Record edits to be applied later (in elf32_arm_write_section). */
13754 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13755 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 13756
2468f9c9
PB		 13757 if (deleted_exidx_bytes > 0)
13758 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
13759
13760 last_exidx_sec = exidx_sec;
13761 last_text_sec = sec;
13762 }
13763
13764 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 13765 if (!bfd_link_relocatable (info) && last_exidx_sec
13766 && last_unwind_type != 0)
2468f9c9
PB		 13767 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13768
13769 return TRUE;
13770}
13771
3e6b1042
DJ		 13772static bfd_boolean
13773elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13774 bfd *ibfd, const char *name)
13775{
13776 asection *sec, *osec;
13777
3d4d4302 13778 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 13779 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13780 return TRUE;
13781
13782 osec = sec->output_section;
13783 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13784 return TRUE;
13785
13786 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13787 sec->output_offset, sec->size))
13788 return FALSE;
13789
13790 return TRUE;
13791}
13792
13793static bfd_boolean
13794elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13795{
13796 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 13797 asection *sec, *osec;
3e6b1042 13798
4dfe6ac6
NC		 13799 if (globals == NULL)
13800 return FALSE;
13801
3e6b1042
DJ		 13802 /* Invoke the regular ELF backend linker to do all the work. */
13803 if (!bfd_elf_final_link (abfd, info))
13804 return FALSE;
13805
fe33d2fa
CL		 13806 /* Process stub sections (eg BE8 encoding, ...). */
13807 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 13808 unsigned int i;
cdb21a0a
NS		 13809 for (i=0; i<htab->top_id; i++)
13810 {
13811 sec = htab->stub_group[i].stub_sec;
13812 /* Only process it once, in its link_sec slot. */
13813 if (sec && i == htab->stub_group[i].link_sec->id)
13814 {
13815 osec = sec->output_section;
13816 elf32_arm_write_section (abfd, info, sec, sec->contents);
13817 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13818 sec->output_offset, sec->size))
13819 return FALSE;
13820 }
fe33d2fa 13821 }
fe33d2fa 13822
3e6b1042
DJ		 13823 /* Write out any glue sections now that we have created all the
13824 stubs. */
13825 if (globals->bfd_of_glue_owner != NULL)
13826 {
13827 if (! elf32_arm_output_glue_section (info, abfd,
13828 globals->bfd_of_glue_owner,
13829 ARM2THUMB_GLUE_SECTION_NAME))
13830 return FALSE;
13831
13832 if (! elf32_arm_output_glue_section (info, abfd,
13833 globals->bfd_of_glue_owner,
13834 THUMB2ARM_GLUE_SECTION_NAME))
13835 return FALSE;
13836
13837 if (! elf32_arm_output_glue_section (info, abfd,
13838 globals->bfd_of_glue_owner,
13839 VFP11_ERRATUM_VENEER_SECTION_NAME))
13840 return FALSE;
13841
a504d23a
LA		 13842 if (! elf32_arm_output_glue_section (info, abfd,
13843 globals->bfd_of_glue_owner,
13844 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13845 return FALSE;
13846
3e6b1042
DJ		 13847 if (! elf32_arm_output_glue_section (info, abfd,
13848 globals->bfd_of_glue_owner,
13849 ARM_BX_GLUE_SECTION_NAME))
13850 return FALSE;
13851 }
13852
13853 return TRUE;
13854}
13855
5968a7b8
NC		 13856/* Return a best guess for the machine number based on the attributes. */
13857
13858static unsigned int
13859bfd_arm_get_mach_from_attributes (bfd * abfd)
13860{
13861 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13862
13863 switch (arch)
13864 {
c0c468d5 13865 case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
5968a7b8
NC		 13866 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13867 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13868 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13869
13870 case TAG_CPU_ARCH_V5TE:
13871 {
13872 char * name;
13873
13874 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13875 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13876
13877 if (name)
13878 {
13879 if (strcmp (name, "IWMMXT2") == 0)
13880 return bfd_mach_arm_iWMMXt2;
13881
13882 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13883 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13884
13885 if (strcmp (name, "XSCALE") == 0)
13886 {
13887 int wmmx;
13888
13889 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13890 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13891 switch (wmmx)
13892 {
13893 case 1: return bfd_mach_arm_iWMMXt;
13894 case 2: return bfd_mach_arm_iWMMXt2;
13895 default: return bfd_mach_arm_XScale;
13896 }
13897 }
5968a7b8
NC		 13898 }
13899
13900 return bfd_mach_arm_5TE;
13901 }
13902
c0c468d5
TP		 13903 case TAG_CPU_ARCH_V5TEJ:
13904 return bfd_mach_arm_5TEJ;
13905 case TAG_CPU_ARCH_V6:
13906 return bfd_mach_arm_6;
13907 case TAG_CPU_ARCH_V6KZ:
13908 return bfd_mach_arm_6KZ;
13909 case TAG_CPU_ARCH_V6T2:
13910 return bfd_mach_arm_6T2;
13911 case TAG_CPU_ARCH_V6K:
13912 return bfd_mach_arm_6K;
13913 case TAG_CPU_ARCH_V7:
13914 return bfd_mach_arm_7;
13915 case TAG_CPU_ARCH_V6_M:
13916 return bfd_mach_arm_6M;
13917 case TAG_CPU_ARCH_V6S_M:
13918 return bfd_mach_arm_6SM;
13919 case TAG_CPU_ARCH_V7E_M:
13920 return bfd_mach_arm_7EM;
13921 case TAG_CPU_ARCH_V8:
13922 return bfd_mach_arm_8;
13923 case TAG_CPU_ARCH_V8R:
13924 return bfd_mach_arm_8R;
13925 case TAG_CPU_ARCH_V8M_BASE:
13926 return bfd_mach_arm_8M_BASE;
13927 case TAG_CPU_ARCH_V8M_MAIN:
13928 return bfd_mach_arm_8M_MAIN;
031254f2
AV		 13929 case TAG_CPU_ARCH_V8_1M_MAIN:
13930 return bfd_mach_arm_8_1M_MAIN;
c0c468d5 13931
5968a7b8 13932 default:
c0c468d5
TP		 13933 /* Force entry to be added for any new known Tag_CPU_arch value. */
13934 BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
13935
13936 /* Unknown Tag_CPU_arch value. */
5968a7b8
NC		 13937 return bfd_mach_arm_unknown;
13938 }
13939}
13940
c178919b
NC		 13941/* Set the right machine number. */
13942
13943static bfd_boolean
57e8b36a 13944elf32_arm_object_p (bfd *abfd)
c178919b 13945{
5a6c6817 13946 unsigned int mach;
57e8b36a 13947
5a6c6817 13948 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13949
5968a7b8
NC		 13950 if (mach == bfd_mach_arm_unknown)
13951 {
13952 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13953 mach = bfd_mach_arm_ep9312;
13954 else
13955 mach = bfd_arm_get_mach_from_attributes (abfd);
13956 }
c178919b 13957
5968a7b8 13958 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13959 return TRUE;
13960}
13961
fc830a83 13962/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13963
b34976b6 13964static bfd_boolean
57e8b36a 13965elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13966{
13967 if (elf_flags_init (abfd)
13968 && elf_elfheader (abfd)->e_flags != flags)
13969 {
fc830a83
NC		 13970 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13971 {
fd2ec330 13972 if (flags & EF_ARM_INTERWORK)
4eca0228 13973 _bfd_error_handler
90b6238f 13974 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13975 abfd);
fc830a83 13976 else
d003868e 13977 _bfd_error_handler
90b6238f 13978 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13979 abfd);
fc830a83 13980 }
252b5132
RH		 13981 }
13982 else
13983 {
13984 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13985 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13986 }
13987
b34976b6 13988 return TRUE;
252b5132
RH		 13989}
13990
fc830a83 13991/* Copy backend specific data from one object module to another. */
9b485d32 13992
b34976b6 13993static bfd_boolean
57e8b36a 13994elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13995{
13996 flagword in_flags;
13997 flagword out_flags;
13998
0ffa91dd 13999 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 14000 return TRUE;
252b5132 14001
fc830a83 14002 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 14003 out_flags = elf_elfheader (obfd)->e_flags;
14004
fc830a83
NC		 14005 if (elf_flags_init (obfd)
14006 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
14007 && in_flags != out_flags)
252b5132 14008 {
252b5132 14009 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 14010 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 14011 return FALSE;
252b5132
RH		 14012
14013 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 14014 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 14015 return FALSE;
252b5132
RH		 14016
14017 /* If the src and dest have different interworking flags
99059e56 14018 then turn off the interworking bit. */
fd2ec330 14019 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 14020 {
fd2ec330 14021 if (out_flags & EF_ARM_INTERWORK)
d003868e 14022 _bfd_error_handler
90b6238f 14023 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 14024 obfd, ibfd);
252b5132 14025
fd2ec330 14026 in_flags &= ~EF_ARM_INTERWORK;
252b5132 14027 }
1006ba19
PB		 14028
14029 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 14030 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
14031 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 14032 }
14033
14034 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 14035 elf_flags_init (obfd) = TRUE;
252b5132 14036
e2349352 14037 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 14038}
14039
14040/* Values for Tag_ABI_PCS_R9_use. */
14041enum
14042{
14043 AEABI_R9_V6,
14044 AEABI_R9_SB,
14045 AEABI_R9_TLS,
14046 AEABI_R9_unused
14047};
14048
14049/* Values for Tag_ABI_PCS_RW_data. */
14050enum
14051{
14052 AEABI_PCS_RW_data_absolute,
14053 AEABI_PCS_RW_data_PCrel,
14054 AEABI_PCS_RW_data_SBrel,
14055 AEABI_PCS_RW_data_unused
14056};
14057
14058/* Values for Tag_ABI_enum_size. */
14059enum
14060{
14061 AEABI_enum_unused,
14062 AEABI_enum_short,
14063 AEABI_enum_wide,
14064 AEABI_enum_forced_wide
14065};
14066
104d59d1
JM		 14067/* Determine whether an object attribute tag takes an integer, a
14068 string or both. */
906e58ca 14069
104d59d1
JM		 14070static int
14071elf32_arm_obj_attrs_arg_type (int tag)
14072{
14073 if (tag == Tag_compatibility)
3483fe2e 14074 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 14075 else if (tag == Tag_nodefaults)
3483fe2e
AS		 14076 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
14077 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
14078 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 14079 else if (tag < 32)
3483fe2e 14080 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 14081 else
3483fe2e 14082 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 14083}
14084
5aa6ff7c
AS		 14085/* The ABI defines that Tag_conformance should be emitted first, and that
14086 Tag_nodefaults should be second (if either is defined). This sets those
14087 two positions, and bumps up the position of all the remaining tags to
14088 compensate. */
14089static int
14090elf32_arm_obj_attrs_order (int num)
14091{
3de4a297 14092 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 14093 return Tag_conformance;
3de4a297 14094 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 14095 return Tag_nodefaults;
14096 if ((num - 2) < Tag_nodefaults)
14097 return num - 2;
14098 if ((num - 1) < Tag_conformance)
14099 return num - 1;
14100 return num;
14101}
14102
e8b36cd1
JM		 14103/* Attribute numbers >=64 (mod 128) can be safely ignored. */
14104static bfd_boolean
14105elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
14106{
14107 if ((tag & 127) < 64)
14108 {
14109 _bfd_error_handler
90b6238f 14110 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 14111 abfd, tag);
14112 bfd_set_error (bfd_error_bad_value);
14113 return FALSE;
14114 }
14115 else
14116 {
14117 _bfd_error_handler
90b6238f 14118 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 14119 abfd, tag);
14120 return TRUE;
14121 }
14122}
14123
91e22acd
AS		 14124/* Read the architecture from the Tag_also_compatible_with attribute, if any.
14125 Returns -1 if no architecture could be read. */
14126
14127static int
14128get_secondary_compatible_arch (bfd *abfd)
14129{
14130 obj_attribute *attr =
14131 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
14132
14133 /* Note: the tag and its argument below are uleb128 values, though
14134 currently-defined values fit in one byte for each. */
14135 if (attr->s
14136 && attr->s[0] == Tag_CPU_arch
14137 && (attr->s[1] & 128) != 128
14138 && attr->s[2] == 0)
14139 return attr->s[1];
14140
14141 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14142 return -1;
14143}
14144
14145/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14146 The tag is removed if ARCH is -1. */
14147
8e79c3df 14148static void
91e22acd 14149set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 14150{
91e22acd
AS		 14151 obj_attribute *attr =
14152 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 14153
91e22acd
AS		 14154 if (arch == -1)
14155 {
14156 attr->s = NULL;
14157 return;
8e79c3df 14158 }
91e22acd
AS		 14159
14160 /* Note: the tag and its argument below are uleb128 values, though
14161 currently-defined values fit in one byte for each. */
14162 if (!attr->s)
21d799b5 14163 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 14164 attr->s[0] = Tag_CPU_arch;
14165 attr->s[1] = arch;
14166 attr->s[2] = '\0';
8e79c3df
CM		 14167}
14168
91e22acd
AS		 14169/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14170 into account. */
14171
14172static int
14173tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
14174 int newtag, int secondary_compat)
8e79c3df 14175{
91e22acd
AS		 14176#define T(X) TAG_CPU_ARCH_##X
14177 int tagl, tagh, result;
14178 const int v6t2[] =
14179 {
14180 T(V6T2), /* PRE_V4. */
14181 T(V6T2), /* V4. */
14182 T(V6T2), /* V4T. */
14183 T(V6T2), /* V5T. */
14184 T(V6T2), /* V5TE. */
14185 T(V6T2), /* V5TEJ. */
14186 T(V6T2), /* V6. */
14187 T(V7), /* V6KZ. */
14188 T(V6T2) /* V6T2. */
14189 };
14190 const int v6k[] =
14191 {
14192 T(V6K), /* PRE_V4. */
14193 T(V6K), /* V4. */
14194 T(V6K), /* V4T. */
14195 T(V6K), /* V5T. */
14196 T(V6K), /* V5TE. */
14197 T(V6K), /* V5TEJ. */
14198 T(V6K), /* V6. */
14199 T(V6KZ), /* V6KZ. */
14200 T(V7), /* V6T2. */
14201 T(V6K) /* V6K. */
14202 };
14203 const int v7[] =
14204 {
14205 T(V7), /* PRE_V4. */
14206 T(V7), /* V4. */
14207 T(V7), /* V4T. */
14208 T(V7), /* V5T. */
14209 T(V7), /* V5TE. */
14210 T(V7), /* V5TEJ. */
14211 T(V7), /* V6. */
14212 T(V7), /* V6KZ. */
14213 T(V7), /* V6T2. */
14214 T(V7), /* V6K. */
14215 T(V7) /* V7. */
14216 };
14217 const int v6_m[] =
14218 {
07d6d2b8
AM		 14219 -1, /* PRE_V4. */
14220 -1, /* V4. */
91e22acd
AS		 14221 T(V6K), /* V4T. */
14222 T(V6K), /* V5T. */
14223 T(V6K), /* V5TE. */
14224 T(V6K), /* V5TEJ. */
14225 T(V6K), /* V6. */
14226 T(V6KZ), /* V6KZ. */
14227 T(V7), /* V6T2. */
14228 T(V6K), /* V6K. */
14229 T(V7), /* V7. */
14230 T(V6_M) /* V6_M. */
14231 };
14232 const int v6s_m[] =
14233 {
07d6d2b8
AM		 14234 -1, /* PRE_V4. */
14235 -1, /* V4. */
91e22acd
AS		 14236 T(V6K), /* V4T. */
14237 T(V6K), /* V5T. */
14238 T(V6K), /* V5TE. */
14239 T(V6K), /* V5TEJ. */
14240 T(V6K), /* V6. */
14241 T(V6KZ), /* V6KZ. */
14242 T(V7), /* V6T2. */
14243 T(V6K), /* V6K. */
14244 T(V7), /* V7. */
14245 T(V6S_M), /* V6_M. */
14246 T(V6S_M) /* V6S_M. */
14247 };
9e3c6df6
PB		 14248 const int v7e_m[] =
14249 {
07d6d2b8
AM		 14250 -1, /* PRE_V4. */
14251 -1, /* V4. */
9e3c6df6
PB		 14252 T(V7E_M), /* V4T. */
14253 T(V7E_M), /* V5T. */
14254 T(V7E_M), /* V5TE. */
14255 T(V7E_M), /* V5TEJ. */
14256 T(V7E_M), /* V6. */
14257 T(V7E_M), /* V6KZ. */
14258 T(V7E_M), /* V6T2. */
14259 T(V7E_M), /* V6K. */
14260 T(V7E_M), /* V7. */
14261 T(V7E_M), /* V6_M. */
14262 T(V7E_M), /* V6S_M. */
14263 T(V7E_M) /* V7E_M. */
14264 };
bca38921
MGD		 14265 const int v8[] =
14266 {
14267 T(V8), /* PRE_V4. */
14268 T(V8), /* V4. */
14269 T(V8), /* V4T. */
14270 T(V8), /* V5T. */
14271 T(V8), /* V5TE. */
14272 T(V8), /* V5TEJ. */
14273 T(V8), /* V6. */
14274 T(V8), /* V6KZ. */
14275 T(V8), /* V6T2. */
14276 T(V8), /* V6K. */
14277 T(V8), /* V7. */
14278 T(V8), /* V6_M. */
14279 T(V8), /* V6S_M. */
14280 T(V8), /* V7E_M. */
14281 T(V8) /* V8. */
14282 };
bff0500d
TP		 14283 const int v8r[] =
14284 {
14285 T(V8R), /* PRE_V4. */
14286 T(V8R), /* V4. */
14287 T(V8R), /* V4T. */
14288 T(V8R), /* V5T. */
14289 T(V8R), /* V5TE. */
14290 T(V8R), /* V5TEJ. */
14291 T(V8R), /* V6. */
14292 T(V8R), /* V6KZ. */
14293 T(V8R), /* V6T2. */
14294 T(V8R), /* V6K. */
14295 T(V8R), /* V7. */
14296 T(V8R), /* V6_M. */
14297 T(V8R), /* V6S_M. */
14298 T(V8R), /* V7E_M. */
14299 T(V8), /* V8. */
14300 T(V8R), /* V8R. */
14301 };
2fd158eb
TP		 14302 const int v8m_baseline[] =
14303 {
14304 -1, /* PRE_V4. */
14305 -1, /* V4. */
14306 -1, /* V4T. */
14307 -1, /* V5T. */
14308 -1, /* V5TE. */
14309 -1, /* V5TEJ. */
14310 -1, /* V6. */
14311 -1, /* V6KZ. */
14312 -1, /* V6T2. */
14313 -1, /* V6K. */
14314 -1, /* V7. */
14315 T(V8M_BASE), /* V6_M. */
14316 T(V8M_BASE), /* V6S_M. */
14317 -1, /* V7E_M. */
14318 -1, /* V8. */
bff0500d 14319 -1, /* V8R. */
2fd158eb
TP		 14320 T(V8M_BASE) /* V8-M BASELINE. */
14321 };
14322 const int v8m_mainline[] =
14323 {
14324 -1, /* PRE_V4. */
14325 -1, /* V4. */
14326 -1, /* V4T. */
14327 -1, /* V5T. */
14328 -1, /* V5TE. */
14329 -1, /* V5TEJ. */
14330 -1, /* V6. */
14331 -1, /* V6KZ. */
14332 -1, /* V6T2. */
14333 -1, /* V6K. */
14334 T(V8M_MAIN), /* V7. */
14335 T(V8M_MAIN), /* V6_M. */
14336 T(V8M_MAIN), /* V6S_M. */
14337 T(V8M_MAIN), /* V7E_M. */
14338 -1, /* V8. */
bff0500d 14339 -1, /* V8R. */
2fd158eb
TP		 14340 T(V8M_MAIN), /* V8-M BASELINE. */
14341 T(V8M_MAIN) /* V8-M MAINLINE. */
14342 };
031254f2
AV		 14343 const int v8_1m_mainline[] =
14344 {
14345 -1, /* PRE_V4. */
14346 -1, /* V4. */
14347 -1, /* V4T. */
14348 -1, /* V5T. */
14349 -1, /* V5TE. */
14350 -1, /* V5TEJ. */
14351 -1, /* V6. */
14352 -1, /* V6KZ. */
14353 -1, /* V6T2. */
14354 -1, /* V6K. */
14355 T(V8_1M_MAIN), /* V7. */
14356 T(V8_1M_MAIN), /* V6_M. */
14357 T(V8_1M_MAIN), /* V6S_M. */
14358 T(V8_1M_MAIN), /* V7E_M. */
14359 -1, /* V8. */
14360 -1, /* V8R. */
14361 T(V8_1M_MAIN), /* V8-M BASELINE. */
14362 T(V8_1M_MAIN), /* V8-M MAINLINE. */
14363 -1, /* Unused (18). */
14364 -1, /* Unused (19). */
14365 -1, /* Unused (20). */
14366 T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
14367 };
91e22acd
AS		 14368 const int v4t_plus_v6_m[] =
14369 {
14370 -1, /* PRE_V4. */
14371 -1, /* V4. */
14372 T(V4T), /* V4T. */
14373 T(V5T), /* V5T. */
14374 T(V5TE), /* V5TE. */
14375 T(V5TEJ), /* V5TEJ. */
14376 T(V6), /* V6. */
14377 T(V6KZ), /* V6KZ. */
14378 T(V6T2), /* V6T2. */
14379 T(V6K), /* V6K. */
14380 T(V7), /* V7. */
14381 T(V6_M), /* V6_M. */
14382 T(V6S_M), /* V6S_M. */
9e3c6df6 14383 T(V7E_M), /* V7E_M. */
bca38921 14384 T(V8), /* V8. */
bff0500d 14385 -1, /* V8R. */
2fd158eb
TP		 14386 T(V8M_BASE), /* V8-M BASELINE. */
14387 T(V8M_MAIN), /* V8-M MAINLINE. */
031254f2
AV		 14388 -1, /* Unused (18). */
14389 -1, /* Unused (19). */
14390 -1, /* Unused (20). */
14391 T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
91e22acd
AS		 14392 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14393 };
14394 const int *comb[] =
14395 {
14396 v6t2,
14397 v6k,
14398 v7,
14399 v6_m,
14400 v6s_m,
9e3c6df6 14401 v7e_m,
bca38921 14402 v8,
bff0500d 14403 v8r,
2fd158eb
TP		 14404 v8m_baseline,
14405 v8m_mainline,
031254f2
AV		 14406 NULL,
14407 NULL,
14408 NULL,
14409 v8_1m_mainline,
91e22acd
AS		 14410 /* Pseudo-architecture. */
14411 v4t_plus_v6_m
14412 };
14413
14414 /* Check we've not got a higher architecture than we know about. */
14415
9e3c6df6 14416 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 14417 {
90b6238f 14418 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 14419 return -1;
14420 }
14421
14422 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14423
14424 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14425 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14426 oldtag = T(V4T_PLUS_V6_M);
14427
14428 /* And override the new tag if we have a Tag_also_compatible_with on the
14429 input. */
14430
14431 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14432 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14433 newtag = T(V4T_PLUS_V6_M);
14434
14435 tagl = (oldtag < newtag) ? oldtag : newtag;
14436 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14437
14438 /* Architectures before V6KZ add features monotonically. */
14439 if (tagh <= TAG_CPU_ARCH_V6KZ)
14440 return result;
14441
4ed7ed8d 14442 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 14443
14444 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14445 as the canonical version. */
14446 if (result == T(V4T_PLUS_V6_M))
14447 {
14448 result = T(V4T);
14449 *secondary_compat_out = T(V6_M);
14450 }
14451 else
14452 *secondary_compat_out = -1;
14453
14454 if (result == -1)
14455 {
90b6238f 14456 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 14457 ibfd, oldtag, newtag);
14458 return -1;
14459 }
14460
14461 return result;
14462#undef T
8e79c3df
CM		 14463}
14464
ac56ee8f
MGD		 14465/* Query attributes object to see if integer divide instructions may be
14466 present in an object. */
14467static bfd_boolean
14468elf32_arm_attributes_accept_div (const obj_attribute *attr)
14469{
14470 int arch = attr[Tag_CPU_arch].i;
14471 int profile = attr[Tag_CPU_arch_profile].i;
14472
14473 switch (attr[Tag_DIV_use].i)
14474 {
14475 case 0:
14476 /* Integer divide allowed if instruction contained in archetecture. */
14477 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14478 return TRUE;
14479 else if (arch >= TAG_CPU_ARCH_V7E_M)
14480 return TRUE;
14481 else
14482 return FALSE;
14483
14484 case 1:
14485 /* Integer divide explicitly prohibited. */
14486 return FALSE;
14487
14488 default:
14489 /* Unrecognised case - treat as allowing divide everywhere. */
14490 case 2:
14491 /* Integer divide allowed in ARM state. */
14492 return TRUE;
14493 }
14494}
14495
14496/* Query attributes object to see if integer divide instructions are
14497 forbidden to be in the object. This is not the inverse of
14498 elf32_arm_attributes_accept_div. */
14499static bfd_boolean
14500elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14501{
14502 return attr[Tag_DIV_use].i == 1;
14503}
14504
ee065d83
PB		 14505/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14506 are conflicting attributes. */
906e58ca 14507
ee065d83 14508static bfd_boolean
50e03d47 14509elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 14510{
50e03d47 14511 bfd *obfd = info->output_bfd;
104d59d1
JM		 14512 obj_attribute *in_attr;
14513 obj_attribute *out_attr;
ee065d83
PB		 14514 /* Some tags have 0 = don't care, 1 = strong requirement,
14515 2 = weak requirement. */
91e22acd 14516 static const int order_021[3] = {0, 2, 1};
ee065d83 14517 int i;
91e22acd 14518 bfd_boolean result = TRUE;
9274e9de 14519 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 14520
3e6b1042
DJ		 14521 /* Skip the linker stubs file. This preserves previous behavior
14522 of accepting unknown attributes in the first input file - but
14523 is that a bug? */
14524 if (ibfd->flags & BFD_LINKER_CREATED)
14525 return TRUE;
14526
9274e9de
TG		 14527 /* Skip any input that hasn't attribute section.
14528 This enables to link object files without attribute section with
14529 any others. */
14530 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14531 return TRUE;
14532
104d59d1 14533 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 14534 {
14535 /* This is the first object. Copy the attributes. */
104d59d1 14536 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 14537
cd21e546
MGD		 14538 out_attr = elf_known_obj_attributes_proc (obfd);
14539
004ae526
PB		 14540 /* Use the Tag_null value to indicate the attributes have been
14541 initialized. */
cd21e546 14542 out_attr[0].i = 1;
004ae526 14543
cd21e546
MGD		 14544 /* We do not output objects with Tag_MPextension_use_legacy - we move
14545 the attribute's value to Tag_MPextension_use. */
14546 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14547 {
14548 if (out_attr[Tag_MPextension_use].i != 0
14549 && out_attr[Tag_MPextension_use_legacy].i
99059e56 14550 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 14551 {
14552 _bfd_error_handler
871b3ab2 14553 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 14554 "Tag_MPextension_use attributes"), ibfd);
14555 result = FALSE;
14556 }
14557
14558 out_attr[Tag_MPextension_use] =
14559 out_attr[Tag_MPextension_use_legacy];
14560 out_attr[Tag_MPextension_use_legacy].type = 0;
14561 out_attr[Tag_MPextension_use_legacy].i = 0;
14562 }
14563
14564 return result;
ee065d83
PB		 14565 }
14566
104d59d1
JM		 14567 in_attr = elf_known_obj_attributes_proc (ibfd);
14568 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 14569 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14570 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14571 {
5c294fee
TG		 14572 /* Ignore mismatches if the object doesn't use floating point or is
14573 floating point ABI independent. */
14574 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14575 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14576 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 14577 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 14578 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14579 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 14580 {
14581 _bfd_error_handler
871b3ab2 14582 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 14583 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14584 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 14585 result = FALSE;
ee065d83
PB		 14586 }
14587 }
14588
3de4a297 14589 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 14590 {
14591 /* Merge this attribute with existing attributes. */
14592 switch (i)
14593 {
14594 case Tag_CPU_raw_name:
14595 case Tag_CPU_name:
6a631e86 14596 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 14597 break;
14598
14599 case Tag_ABI_optimization_goals:
14600 case Tag_ABI_FP_optimization_goals:
14601 /* Use the first value seen. */
14602 break;
14603
14604 case Tag_CPU_arch:
91e22acd
AS		 14605 {
14606 int secondary_compat = -1, secondary_compat_out = -1;
14607 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 14608 int arch_attr;
14609 static const char *name_table[] =
14610 {
91e22acd
AS		 14611 /* These aren't real CPU names, but we can't guess
14612 that from the architecture version alone. */
14613 "Pre v4",
14614 "ARM v4",
14615 "ARM v4T",
14616 "ARM v5T",
14617 "ARM v5TE",
14618 "ARM v5TEJ",
14619 "ARM v6",
14620 "ARM v6KZ",
14621 "ARM v6T2",
14622 "ARM v6K",
14623 "ARM v7",
14624 "ARM v6-M",
bca38921 14625 "ARM v6S-M",
2fd158eb
TP		 14626 "ARM v8",
14627 "",
14628 "ARM v8-M.baseline",
14629 "ARM v8-M.mainline",
91e22acd
AS		 14630 };
14631
14632 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14633 secondary_compat = get_secondary_compatible_arch (ibfd);
14634 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 14635 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14636 &secondary_compat_out,
14637 in_attr[i].i,
14638 secondary_compat);
14639
14640 /* Return with error if failed to merge. */
14641 if (arch_attr == -1)
14642 return FALSE;
14643
14644 out_attr[i].i = arch_attr;
14645
91e22acd
AS		 14646 set_secondary_compatible_arch (obfd, secondary_compat_out);
14647
14648 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14649 if (out_attr[i].i == saved_out_attr)
14650 ; /* Leave the names alone. */
14651 else if (out_attr[i].i == in_attr[i].i)
14652 {
14653 /* The output architecture has been changed to match the
14654 input architecture. Use the input names. */
14655 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14656 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14657 : NULL;
14658 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14659 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14660 : NULL;
14661 }
14662 else
14663 {
14664 out_attr[Tag_CPU_name].s = NULL;
14665 out_attr[Tag_CPU_raw_name].s = NULL;
14666 }
14667
14668 /* If we still don't have a value for Tag_CPU_name,
14669 make one up now. Tag_CPU_raw_name remains blank. */
14670 if (out_attr[Tag_CPU_name].s == NULL
14671 && out_attr[i].i < ARRAY_SIZE (name_table))
14672 out_attr[Tag_CPU_name].s =
14673 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14674 }
14675 break;
14676
ee065d83
PB		 14677 case Tag_ARM_ISA_use:
14678 case Tag_THUMB_ISA_use:
ee065d83 14679 case Tag_WMMX_arch:
91e22acd
AS		 14680 case Tag_Advanced_SIMD_arch:
14681 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 14682 case Tag_ABI_FP_rounding:
ee065d83
PB		 14683 case Tag_ABI_FP_exceptions:
14684 case Tag_ABI_FP_user_exceptions:
14685 case Tag_ABI_FP_number_model:
75375b3e 14686 case Tag_FP_HP_extension:
91e22acd
AS		 14687 case Tag_CPU_unaligned_access:
14688 case Tag_T2EE_use:
91e22acd 14689 case Tag_MPextension_use:
a7ad558c 14690 case Tag_MVE_arch:
ee065d83
PB		 14691 /* Use the largest value specified. */
14692 if (in_attr[i].i > out_attr[i].i)
14693 out_attr[i].i = in_attr[i].i;
14694 break;
14695
75375b3e 14696 case Tag_ABI_align_preserved:
91e22acd
AS		 14697 case Tag_ABI_PCS_RO_data:
14698 /* Use the smallest value specified. */
14699 if (in_attr[i].i < out_attr[i].i)
14700 out_attr[i].i = in_attr[i].i;
14701 break;
14702
75375b3e 14703 case Tag_ABI_align_needed:
91e22acd 14704 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 14705 && (in_attr[Tag_ABI_align_preserved].i == 0
14706 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 14707 {
91e22acd
AS		 14708 /* This error message should be enabled once all non-conformant
14709 binaries in the toolchain have had the attributes set
14710 properly.
ee065d83 14711 _bfd_error_handler
871b3ab2 14712 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 14713 obfd, ibfd);
14714 result = FALSE; */
ee065d83 14715 }
91e22acd
AS		 14716 /* Fall through. */
14717 case Tag_ABI_FP_denormal:
14718 case Tag_ABI_PCS_GOT_use:
14719 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14720 value if greater than 2 (for future-proofing). */
14721 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14722 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14723 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 14724 out_attr[i].i = in_attr[i].i;
14725 break;
91e22acd 14726
75375b3e
MGD		 14727 case Tag_Virtualization_use:
14728 /* The virtualization tag effectively stores two bits of
14729 information: the intended use of TrustZone (in bit 0), and the
14730 intended use of Virtualization (in bit 1). */
14731 if (out_attr[i].i == 0)
14732 out_attr[i].i = in_attr[i].i;
14733 else if (in_attr[i].i != 0
14734 && in_attr[i].i != out_attr[i].i)
14735 {
14736 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14737 out_attr[i].i = 3;
14738 else
14739 {
14740 _bfd_error_handler
871b3ab2
AM		 14741 (_("error: %pB: unable to merge virtualization attributes "
14742 "with %pB"),
75375b3e
MGD		 14743 obfd, ibfd);
14744 result = FALSE;
14745 }
14746 }
14747 break;
91e22acd
AS		 14748
14749 case Tag_CPU_arch_profile:
14750 if (out_attr[i].i != in_attr[i].i)
14751 {
14752 /* 0 will merge with anything.
14753 'A' and 'S' merge to 'A'.
14754 'R' and 'S' merge to 'R'.
99059e56 14755 'M' and 'A|R|S' is an error. */
91e22acd
AS		 14756 if (out_attr[i].i == 0
14757 || (out_attr[i].i == 'S'
14758 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14759 out_attr[i].i = in_attr[i].i;
14760 else if (in_attr[i].i == 0
14761 || (in_attr[i].i == 'S'
14762 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 14763 ; /* Do nothing. */
91e22acd
AS		 14764 else
14765 {
14766 _bfd_error_handler
90b6238f 14767 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 14768 ibfd,
14769 in_attr[i].i ? in_attr[i].i : '0',
14770 out_attr[i].i ? out_attr[i].i : '0');
14771 result = FALSE;
14772 }
14773 }
14774 break;
15afaa63
TP		 14775
14776 case Tag_DSP_extension:
14777 /* No need to change output value if any of:
14778 - pre (<=) ARMv5T input architecture (do not have DSP)
14779 - M input profile not ARMv7E-M and do not have DSP. */
14780 if (in_attr[Tag_CPU_arch].i <= 3
14781 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14782 && in_attr[Tag_CPU_arch].i != 13
14783 && in_attr[i].i == 0))
14784 ; /* Do nothing. */
14785 /* Output value should be 0 if DSP part of architecture, ie.
14786 - post (>=) ARMv5te architecture output
14787 - A, R or S profile output or ARMv7E-M output architecture. */
14788 else if (out_attr[Tag_CPU_arch].i >= 4
14789 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14790 || out_attr[Tag_CPU_arch_profile].i == 'R'
14791 || out_attr[Tag_CPU_arch_profile].i == 'S'
14792 || out_attr[Tag_CPU_arch].i == 13))
14793 out_attr[i].i = 0;
14794 /* Otherwise, DSP instructions are added and not part of output
14795 architecture. */
14796 else
14797 out_attr[i].i = 1;
14798 break;
14799
75375b3e 14800 case Tag_FP_arch:
62f3b8c8 14801 {
4547cb56
NC		 14802 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14803 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14804 when it's 0. It might mean absence of FP hardware if
99654aaf 14805 Tag_FP_arch is zero. */
4547cb56 14806
a715796b 14807#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 14808 static const struct
14809 {
14810 int ver;
14811 int regs;
bca38921 14812 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 14813 {
14814 {0, 0},
14815 {1, 16},
14816 {2, 16},
14817 {3, 32},
14818 {3, 16},
14819 {4, 32},
bca38921 14820 {4, 16},
a715796b
TG		 14821 {8, 32},
14822 {8, 16}
62f3b8c8
PB		 14823 };
14824 int ver;
14825 int regs;
14826 int newval;
14827
4547cb56
NC		 14828 /* If the output has no requirement about FP hardware,
14829 follow the requirement of the input. */
14830 if (out_attr[i].i == 0)
14831 {
4ec192e6
RE		 14832 /* This assert is still reasonable, we shouldn't
14833 produce the suspicious build attribute
14834 combination (See below for in_attr). */
4547cb56
NC		 14835 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14836 out_attr[i].i = in_attr[i].i;
14837 out_attr[Tag_ABI_HardFP_use].i
14838 = in_attr[Tag_ABI_HardFP_use].i;
14839 break;
14840 }
14841 /* If the input has no requirement about FP hardware, do
14842 nothing. */
14843 else if (in_attr[i].i == 0)
14844 {
4ec192e6
RE		 14845 /* We used to assert that Tag_ABI_HardFP_use was
14846 zero here, but we should never assert when
14847 consuming an object file that has suspicious
14848 build attributes. The single precision variant
14849 of 'no FP architecture' is still 'no FP
14850 architecture', so we just ignore the tag in this
14851 case. */
4547cb56
NC		 14852 break;
14853 }
14854
14855 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 14856 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 14857
14858 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14859 do nothing. */
14860 if (in_attr[Tag_ABI_HardFP_use].i == 0
14861 && out_attr[Tag_ABI_HardFP_use].i == 0)
14862 ;
14863 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 14864 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 14865 else if (in_attr[Tag_ABI_HardFP_use].i
14866 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 14867 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 14868
14869 /* Now we can handle Tag_FP_arch. */
14870
bca38921
MGD		 14871 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14872 pick the biggest. */
14873 if (in_attr[i].i >= VFP_VERSION_COUNT
14874 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 14875 {
14876 out_attr[i] = in_attr[i];
14877 break;
14878 }
14879 /* The output uses the superset of input features
14880 (ISA version) and registers. */
14881 ver = vfp_versions[in_attr[i].i].ver;
14882 if (ver < vfp_versions[out_attr[i].i].ver)
14883 ver = vfp_versions[out_attr[i].i].ver;
14884 regs = vfp_versions[in_attr[i].i].regs;
14885 if (regs < vfp_versions[out_attr[i].i].regs)
14886 regs = vfp_versions[out_attr[i].i].regs;
14887 /* This assumes all possible supersets are also a valid
99059e56 14888 options. */
bca38921 14889 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 14890 {
14891 if (regs == vfp_versions[newval].regs
14892 && ver == vfp_versions[newval].ver)
14893 break;
14894 }
14895 out_attr[i].i = newval;
14896 }
b1cc4aeb 14897 break;
ee065d83
PB		 14898 case Tag_PCS_config:
14899 if (out_attr[i].i == 0)
14900 out_attr[i].i = in_attr[i].i;
b6009aca 14901 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14902 {
14903 /* It's sometimes ok to mix different configs, so this is only
99059e56 14904 a warning. */
ee065d83 14905 _bfd_error_handler
90b6238f 14906 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14907 }
14908 break;
14909 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14910 if (in_attr[i].i != out_attr[i].i
14911 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14912 && in_attr[i].i != AEABI_R9_unused)
14913 {
14914 _bfd_error_handler
90b6238f 14915 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14916 result = FALSE;
ee065d83
PB		 14917 }
14918 if (out_attr[i].i == AEABI_R9_unused)
14919 out_attr[i].i = in_attr[i].i;
14920 break;
14921 case Tag_ABI_PCS_RW_data:
14922 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14923 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14924 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14925 {
14926 _bfd_error_handler
871b3ab2 14927 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14928 ibfd);
91e22acd 14929 result = FALSE;
ee065d83
PB		 14930 }
14931 /* Use the smallest value specified. */
14932 if (in_attr[i].i < out_attr[i].i)
14933 out_attr[i].i = in_attr[i].i;
14934 break;
ee065d83 14935 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14936 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14937 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14938 {
14939 _bfd_error_handler
871b3ab2 14940 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14941 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14942 }
a9dc9481 14943 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14944 out_attr[i].i = in_attr[i].i;
14945 break;
ee065d83
PB		 14946 case Tag_ABI_enum_size:
14947 if (in_attr[i].i != AEABI_enum_unused)
14948 {
14949 if (out_attr[i].i == AEABI_enum_unused
14950 || out_attr[i].i == AEABI_enum_forced_wide)
14951 {
14952 /* The existing object is compatible with anything.
14953 Use whatever requirements the new object has. */
14954 out_attr[i].i = in_attr[i].i;
14955 }
14956 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14957 && out_attr[i].i != in_attr[i].i
0ffa91dd 14958 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14959 {
91e22acd 14960 static const char *aeabi_enum_names[] =
bf21ed78 14961 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14962 const char *in_name =
14963 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14964 ? aeabi_enum_names[in_attr[i].i]
14965 : "<unknown>";
14966 const char *out_name =
14967 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14968 ? aeabi_enum_names[out_attr[i].i]
14969 : "<unknown>";
ee065d83 14970 _bfd_error_handler
871b3ab2 14971 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14972 ibfd, in_name, out_name);
ee065d83
PB		 14973 }
14974 }
14975 break;
14976 case Tag_ABI_VFP_args:
14977 /* Aready done. */
14978 break;
14979 case Tag_ABI_WMMX_args:
14980 if (in_attr[i].i != out_attr[i].i)
14981 {
14982 _bfd_error_handler
871b3ab2 14983 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14984 ibfd, obfd);
91e22acd 14985 result = FALSE;
ee065d83
PB		 14986 }
14987 break;
7b86a9fa
AS		 14988 case Tag_compatibility:
14989 /* Merged in target-independent code. */
14990 break;
91e22acd 14991 case Tag_ABI_HardFP_use:
4547cb56 14992 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14993 break;
14994 case Tag_ABI_FP_16bit_format:
14995 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14996 {
14997 if (in_attr[i].i != out_attr[i].i)
14998 {
14999 _bfd_error_handler
871b3ab2 15000 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 15001 ibfd, obfd);
15002 result = FALSE;
15003 }
15004 }
15005 if (in_attr[i].i != 0)
15006 out_attr[i].i = in_attr[i].i;
15007 break;
7b86a9fa 15008
cd21e546 15009 case Tag_DIV_use:
ac56ee8f
MGD		 15010 /* A value of zero on input means that the divide instruction may
15011 be used if available in the base architecture as specified via
15012 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
15013 the user did not want divide instructions. A value of 2
15014 explicitly means that divide instructions were allowed in ARM
15015 and Thumb state. */
15016 if (in_attr[i].i == out_attr[i].i)
15017 /* Do nothing. */ ;
15018 else if (elf32_arm_attributes_forbid_div (in_attr)
15019 && !elf32_arm_attributes_accept_div (out_attr))
15020 out_attr[i].i = 1;
15021 else if (elf32_arm_attributes_forbid_div (out_attr)
15022 && elf32_arm_attributes_accept_div (in_attr))
15023 out_attr[i].i = in_attr[i].i;
15024 else if (in_attr[i].i == 2)
15025 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 15026 break;
15027
15028 case Tag_MPextension_use_legacy:
15029 /* We don't output objects with Tag_MPextension_use_legacy - we
15030 move the value to Tag_MPextension_use. */
15031 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
15032 {
15033 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
15034 {
15035 _bfd_error_handler
871b3ab2 15036 (_("%pB has both the current and legacy "
b38cadfb 15037 "Tag_MPextension_use attributes"),
cd21e546
MGD		 15038 ibfd);
15039 result = FALSE;
15040 }
15041 }
15042
15043 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
15044 out_attr[Tag_MPextension_use] = in_attr[i];
15045
15046 break;
15047
91e22acd 15048 case Tag_nodefaults:
2d0bb761
AS		 15049 /* This tag is set if it exists, but the value is unused (and is
15050 typically zero). We don't actually need to do anything here -
15051 the merge happens automatically when the type flags are merged
15052 below. */
91e22acd
AS		 15053 break;
15054 case Tag_also_compatible_with:
15055 /* Already done in Tag_CPU_arch. */
15056 break;
15057 case Tag_conformance:
15058 /* Keep the attribute if it matches. Throw it away otherwise.
15059 No attribute means no claim to conform. */
15060 if (!in_attr[i].s || !out_attr[i].s
15061 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
15062 out_attr[i].s = NULL;
15063 break;
3cfad14c 15064
91e22acd 15065 default:
e8b36cd1
JM		 15066 result
15067 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 15068 }
15069
15070 /* If out_attr was copied from in_attr then it won't have a type yet. */
15071 if (in_attr[i].type && !out_attr[i].type)
15072 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 15073 }
15074
104d59d1 15075 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 15076 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 15077 return FALSE;
ee065d83 15078
104d59d1 15079 /* Check for any attributes not known on ARM. */
e8b36cd1 15080 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 15081
91e22acd 15082 return result;
252b5132
RH		 15083}
15084
3a4a14e9
PB		 15085
15086/* Return TRUE if the two EABI versions are incompatible. */
15087
15088static bfd_boolean
15089elf32_arm_versions_compatible (unsigned iver, unsigned over)
15090{
15091 /* v4 and v5 are the same spec before and after it was released,
15092 so allow mixing them. */
15093 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
15094 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
15095 return TRUE;
15096
15097 return (iver == over);
15098}
15099
252b5132
RH		 15100/* Merge backend specific data from an object file to the output
15101 object file when linking. */
9b485d32 15102
b34976b6 15103static bfd_boolean
50e03d47 15104elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 15105
9b485d32
NC		 15106/* Display the flags field. */
15107
b34976b6 15108static bfd_boolean
57e8b36a 15109elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 15110{
fc830a83
NC		 15111 FILE * file = (FILE *) ptr;
15112 unsigned long flags;
252b5132
RH		 15113
15114 BFD_ASSERT (abfd != NULL && ptr != NULL);
15115
15116 /* Print normal ELF private data. */
15117 _bfd_elf_print_private_bfd_data (abfd, ptr);
15118
fc830a83 15119 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 15120 /* Ignore init flag - it may not be set, despite the flags field
15121 containing valid data. */
252b5132 15122
9b485d32 15123 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 15124
fc830a83
NC		 15125 switch (EF_ARM_EABI_VERSION (flags))
15126 {
15127 case EF_ARM_EABI_UNKNOWN:
4cc11e76 15128 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 15129 official ARM ELF extended ABI. Hence they are only decoded if
15130 the EABI version is not set. */
fd2ec330 15131 if (flags & EF_ARM_INTERWORK)
9b485d32 15132 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 15133
fd2ec330 15134 if (flags & EF_ARM_APCS_26)
6c571f00 15135 fprintf (file, " [APCS-26]");
fc830a83 15136 else
6c571f00 15137 fprintf (file, " [APCS-32]");
9a5aca8c 15138
96a846ea
RE		 15139 if (flags & EF_ARM_VFP_FLOAT)
15140 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 15141 else if (flags & EF_ARM_MAVERICK_FLOAT)
15142 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 15143 else
15144 fprintf (file, _(" [FPA float format]"));
15145
fd2ec330 15146 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 15147 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 15148
fd2ec330 15149 if (flags & EF_ARM_PIC)
9b485d32 15150 fprintf (file, _(" [position independent]"));
fc830a83 15151
fd2ec330 15152 if (flags & EF_ARM_NEW_ABI)
9b485d32 15153 fprintf (file, _(" [new ABI]"));
9a5aca8c 15154
fd2ec330 15155 if (flags & EF_ARM_OLD_ABI)
9b485d32 15156 fprintf (file, _(" [old ABI]"));
9a5aca8c 15157
fd2ec330 15158 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 15159 fprintf (file, _(" [software FP]"));
9a5aca8c 15160
96a846ea
RE		 15161 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
15162 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 15163 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
15164 | EF_ARM_MAVERICK_FLOAT);
fc830a83 15165 break;
9a5aca8c 15166
fc830a83 15167 case EF_ARM_EABI_VER1:
9b485d32 15168 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 15169
fc830a83 15170 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 15171 fprintf (file, _(" [sorted symbol table]"));
fc830a83 15172 else
9b485d32 15173 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 15174
fc830a83
NC		 15175 flags &= ~ EF_ARM_SYMSARESORTED;
15176 break;
9a5aca8c 15177
fd2ec330
PB		 15178 case EF_ARM_EABI_VER2:
15179 fprintf (file, _(" [Version2 EABI]"));
15180
15181 if (flags & EF_ARM_SYMSARESORTED)
15182 fprintf (file, _(" [sorted symbol table]"));
15183 else
15184 fprintf (file, _(" [unsorted symbol table]"));
15185
15186 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
15187 fprintf (file, _(" [dynamic symbols use segment index]"));
15188
15189 if (flags & EF_ARM_MAPSYMSFIRST)
15190 fprintf (file, _(" [mapping symbols precede others]"));
15191
99e4ae17 15192 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 15193 | EF_ARM_MAPSYMSFIRST);
15194 break;
15195
d507cf36
PB		 15196 case EF_ARM_EABI_VER3:
15197 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 15198 break;
15199
15200 case EF_ARM_EABI_VER4:
15201 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 15202 goto eabi;
d507cf36 15203
3a4a14e9
PB		 15204 case EF_ARM_EABI_VER5:
15205 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 15206
15207 if (flags & EF_ARM_ABI_FLOAT_SOFT)
15208 fprintf (file, _(" [soft-float ABI]"));
15209
15210 if (flags & EF_ARM_ABI_FLOAT_HARD)
15211 fprintf (file, _(" [hard-float ABI]"));
15212
15213 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
15214
3a4a14e9 15215 eabi:
d507cf36
PB		 15216 if (flags & EF_ARM_BE8)
15217 fprintf (file, _(" [BE8]"));
15218
15219 if (flags & EF_ARM_LE8)
15220 fprintf (file, _(" [LE8]"));
15221
15222 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
15223 break;
15224
fc830a83 15225 default:
9b485d32 15226 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 15227 break;
15228 }
252b5132 15229
fc830a83 15230 flags &= ~ EF_ARM_EABIMASK;
252b5132 15231
fc830a83 15232 if (flags & EF_ARM_RELEXEC)
9b485d32 15233 fprintf (file, _(" [relocatable executable]"));
252b5132 15234
18a20338
CL		 15235 if (flags & EF_ARM_PIC)
15236 fprintf (file, _(" [position independent]"));
15237
15238 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
15239 fprintf (file, _(" [FDPIC ABI supplement]"));
15240
15241 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 15242
15243 if (flags)
9b485d32 15244 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 15245
252b5132
RH		 15246 fputc ('\n', file);
15247
b34976b6 15248 return TRUE;
252b5132
RH		 15249}
15250
15251static int
57e8b36a 15252elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 15253{
2f0ca46a
NC		 15254 switch (ELF_ST_TYPE (elf_sym->st_info))
15255 {
15256 case STT_ARM_TFUNC:
15257 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 15258
2f0ca46a
NC		 15259 case STT_ARM_16BIT:
15260 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15261 This allows us to distinguish between data used by Thumb instructions
15262 and non-data (which is probably code) inside Thumb regions of an
15263 executable. */
1a0eb693 15264 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 15265 return ELF_ST_TYPE (elf_sym->st_info);
15266 break;
9a5aca8c 15267
ce855c42
NC		 15268 default:
15269 break;
2f0ca46a
NC		 15270 }
15271
15272 return type;
252b5132 15273}
f21f3fe0 15274
252b5132 15275static asection *
07adf181
AM		 15276elf32_arm_gc_mark_hook (asection *sec,
15277 struct bfd_link_info *info,
15278 Elf_Internal_Rela *rel,
15279 struct elf_link_hash_entry *h,
15280 Elf_Internal_Sym *sym)
252b5132
RH		 15281{
15282 if (h != NULL)
07adf181 15283 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 15284 {
15285 case R_ARM_GNU_VTINHERIT:
15286 case R_ARM_GNU_VTENTRY:
07adf181
AM		 15287 return NULL;
15288 }
9ad5cbcf 15289
07adf181 15290 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 15291}
15292
780a67af
NC		 15293/* Look through the relocs for a section during the first phase. */
15294
b34976b6 15295static bfd_boolean
57e8b36a
NC		 15296elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
15297 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 15298{
b34976b6
AM		 15299 Elf_Internal_Shdr *symtab_hdr;
15300 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 15301 const Elf_Internal_Rela *rel;
15302 const Elf_Internal_Rela *rel_end;
15303 bfd *dynobj;
5e681ec4 15304 asection *sreloc;
5e681ec4 15305 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 15306 bfd_boolean call_reloc_p;
15307 bfd_boolean may_become_dynamic_p;
15308 bfd_boolean may_need_local_target_p;
ce98a316 15309 unsigned long nsyms;
9a5aca8c 15310
0e1862bb 15311 if (bfd_link_relocatable (info))
b34976b6 15312 return TRUE;
9a5aca8c 15313
0ffa91dd
NC		 15314 BFD_ASSERT (is_arm_elf (abfd));
15315
5e681ec4 15316 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15317 if (htab == NULL)
15318 return FALSE;
15319
5e681ec4 15320 sreloc = NULL;
9a5aca8c 15321
67687978
PB		 15322 /* Create dynamic sections for relocatable executables so that we can
15323 copy relocations. */
15324 if (htab->root.is_relocatable_executable
15325 && ! htab->root.dynamic_sections_created)
15326 {
15327 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15328 return FALSE;
15329 }
15330
cbc704f3
RS		 15331 if (htab->root.dynobj == NULL)
15332 htab->root.dynobj = abfd;
34e77a92
RS		 15333 if (!create_ifunc_sections (info))
15334 return FALSE;
cbc704f3
RS		 15335
15336 dynobj = htab->root.dynobj;
15337
0ffa91dd 15338 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 15339 sym_hashes = elf_sym_hashes (abfd);
ce98a316 15340 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 15341
252b5132
RH		 15342 rel_end = relocs + sec->reloc_count;
15343 for (rel = relocs; rel < rel_end; rel++)
15344 {
34e77a92 15345 Elf_Internal_Sym *isym;
252b5132 15346 struct elf_link_hash_entry *h;
b7693d02 15347 struct elf32_arm_link_hash_entry *eh;
d42c267e 15348 unsigned int r_symndx;
eb043451 15349 int r_type;
9a5aca8c 15350
252b5132 15351 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 15352 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 15353 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 15354
ce98a316
NC		 15355 if (r_symndx >= nsyms
15356 /* PR 9934: It is possible to have relocations that do not
15357 refer to symbols, thus it is also possible to have an
15358 object file containing relocations but no symbol table. */
cf35638d 15359 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 15360 {
871b3ab2 15361 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 15362 r_symndx);
ba93b8ac
DJ		 15363 return FALSE;
15364 }
15365
34e77a92
RS		 15366 h = NULL;
15367 isym = NULL;
15368 if (nsyms > 0)
973a3492 15369 {
34e77a92
RS		 15370 if (r_symndx < symtab_hdr->sh_info)
15371 {
15372 /* A local symbol. */
15373 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
15374 abfd, r_symndx);
15375 if (isym == NULL)
15376 return FALSE;
15377 }
15378 else
15379 {
15380 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15381 while (h->root.type == bfd_link_hash_indirect
15382 || h->root.type == bfd_link_hash_warning)
15383 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15384 }
973a3492 15385 }
9a5aca8c 15386
b7693d02
DJ		 15387 eh = (struct elf32_arm_link_hash_entry *) h;
15388
f6e32f6d
RS		 15389 call_reloc_p = FALSE;
15390 may_become_dynamic_p = FALSE;
15391 may_need_local_target_p = FALSE;
15392
0855e32b
NS		 15393 /* Could be done earlier, if h were already available. */
15394 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 15395 switch (r_type)
99059e56 15396 {
e8b09b87
CL		 15397 case R_ARM_GOTOFFFUNCDESC:
15398 {
15399 if (h == NULL)
15400 {
15401 if (!elf32_arm_allocate_local_sym_info (abfd))
15402 return FALSE;
15403 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].gotofffuncdesc_cnt += 1;
15404 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15405 }
15406 else
15407 {
15408 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15409 }
15410 }
15411 break;
15412
15413 case R_ARM_GOTFUNCDESC:
15414 {
15415 if (h == NULL)
15416 {
15417 /* Such a relocation is not supposed to be generated
15418 by gcc on a static function. */
15419 /* Anyway if needed it could be handled. */
15420 abort();
15421 }
15422 else
15423 {
15424 eh->fdpic_cnts.gotfuncdesc_cnt++;
15425 }
15426 }
15427 break;
15428
15429 case R_ARM_FUNCDESC:
15430 {
15431 if (h == NULL)
15432 {
15433 if (!elf32_arm_allocate_local_sym_info (abfd))
15434 return FALSE;
15435 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_cnt += 1;
15436 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15437 }
15438 else
15439 {
15440 eh->fdpic_cnts.funcdesc_cnt++;
15441 }
15442 }
15443 break;
15444
5e681ec4 15445 case R_ARM_GOT32:
eb043451 15446 case R_ARM_GOT_PREL:
ba93b8ac 15447 case R_ARM_TLS_GD32:
5c5a4843 15448 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 15449 case R_ARM_TLS_IE32:
5c5a4843 15450 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 15451 case R_ARM_TLS_GOTDESC:
15452 case R_ARM_TLS_DESCSEQ:
15453 case R_ARM_THM_TLS_DESCSEQ:
15454 case R_ARM_TLS_CALL:
15455 case R_ARM_THM_TLS_CALL:
5e681ec4 15456 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 15457 {
15458 int tls_type, old_tls_type;
5e681ec4 15459
ba93b8ac
DJ		 15460 switch (r_type)
15461 {
15462 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
5c5a4843 15463 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
b38cadfb 15464
ba93b8ac 15465 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
5c5a4843 15466 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
b38cadfb 15467
0855e32b
NS		 15468 case R_ARM_TLS_GOTDESC:
15469 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15470 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15471 tls_type = GOT_TLS_GDESC; break;
b38cadfb 15472
ba93b8ac
DJ		 15473 default: tls_type = GOT_NORMAL; break;
15474 }
252b5132 15475
0e1862bb 15476 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 15477 info->flags |= DF_STATIC_TLS;
15478
ba93b8ac
DJ		 15479 if (h != NULL)
15480 {
15481 h->got.refcount++;
15482 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15483 }
15484 else
15485 {
ba93b8ac 15486 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 15487 if (!elf32_arm_allocate_local_sym_info (abfd))
15488 return FALSE;
15489 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 15490 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15491 }
15492
0855e32b 15493 /* If a variable is accessed with both tls methods, two
99059e56 15494 slots may be created. */
0855e32b
NS		 15495 if (GOT_TLS_GD_ANY_P (old_tls_type)
15496 && GOT_TLS_GD_ANY_P (tls_type))
15497 tls_type |= old_tls_type;
15498
15499 /* We will already have issued an error message if there
15500 is a TLS/non-TLS mismatch, based on the symbol
15501 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 15502 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15503 && tls_type != GOT_NORMAL)
15504 tls_type |= old_tls_type;
15505
0855e32b 15506 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 15507 method, we're able to relax. Turn off the GDESC flag,
15508 without messing up with any other kind of tls types
6a631e86 15509 that may be involved. */
0855e32b
NS		 15510 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15511 tls_type &= ~GOT_TLS_GDESC;
15512
ba93b8ac
DJ		 15513 if (old_tls_type != tls_type)
15514 {
15515 if (h != NULL)
15516 elf32_arm_hash_entry (h)->tls_type = tls_type;
15517 else
15518 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15519 }
15520 }
8029a119 15521 /* Fall through. */
ba93b8ac
DJ		 15522
15523 case R_ARM_TLS_LDM32:
5c5a4843
CL		 15524 case R_ARM_TLS_LDM32_FDPIC:
15525 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
ba93b8ac 15526 htab->tls_ldm_got.refcount++;
8029a119 15527 /* Fall through. */
252b5132 15528
c19d1205 15529 case R_ARM_GOTOFF32:
5e681ec4 15530 case R_ARM_GOTPC:
cbc704f3
RS		 15531 if (htab->root.sgot == NULL
15532 && !create_got_section (htab->root.dynobj, info))
15533 return FALSE;
252b5132
RH		 15534 break;
15535
252b5132 15536 case R_ARM_PC24:
7359ea65 15537 case R_ARM_PLT32:
5b5bb741
PB		 15538 case R_ARM_CALL:
15539 case R_ARM_JUMP24:
eb043451 15540 case R_ARM_PREL31:
c19d1205 15541 case R_ARM_THM_CALL:
bd97cb95
DJ		 15542 case R_ARM_THM_JUMP24:
15543 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 15544 call_reloc_p = TRUE;
15545 may_need_local_target_p = TRUE;
15546 break;
15547
15548 case R_ARM_ABS12:
15549 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15550 ldr __GOTT_INDEX__ offsets. */
15551 if (!htab->vxworks_p)
15552 {
15553 may_need_local_target_p = TRUE;
15554 break;
15555 }
aebf9be7 15556 else goto jump_over;
9eaff861 15557
f6e32f6d 15558 /* Fall through. */
39623e12 15559
96c23d59
JM		 15560 case R_ARM_MOVW_ABS_NC:
15561 case R_ARM_MOVT_ABS:
15562 case R_ARM_THM_MOVW_ABS_NC:
15563 case R_ARM_THM_MOVT_ABS:
0e1862bb 15564 if (bfd_link_pic (info))
96c23d59 15565 {
4eca0228 15566 _bfd_error_handler
871b3ab2 15567 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 15568 abfd, elf32_arm_howto_table_1[r_type].name,
15569 (h) ? h->root.root.string : "a local symbol");
15570 bfd_set_error (bfd_error_bad_value);
15571 return FALSE;
15572 }
15573
15574 /* Fall through. */
39623e12
PB		 15575 case R_ARM_ABS32:
15576 case R_ARM_ABS32_NOI:
aebf9be7 15577 jump_over:
0e1862bb 15578 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 15579 {
15580 h->pointer_equality_needed = 1;
15581 }
15582 /* Fall through. */
39623e12
PB		 15583 case R_ARM_REL32:
15584 case R_ARM_REL32_NOI:
b6895b4f
PB		 15585 case R_ARM_MOVW_PREL_NC:
15586 case R_ARM_MOVT_PREL:
b6895b4f
PB		 15587 case R_ARM_THM_MOVW_PREL_NC:
15588 case R_ARM_THM_MOVT_PREL:
39623e12 15589
b7693d02 15590 /* Should the interworking branches be listed here? */
e8b09b87
CL		 15591 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15592 || htab->fdpic_p)
34e77a92
RS		 15593 && (sec->flags & SEC_ALLOC) != 0)
15594 {
15595 if (h == NULL
469a3493 15596 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 15597 {
15598 /* In shared libraries and relocatable executables,
15599 we treat local relative references as calls;
15600 see the related SYMBOL_CALLS_LOCAL code in
15601 allocate_dynrelocs. */
15602 call_reloc_p = TRUE;
15603 may_need_local_target_p = TRUE;
15604 }
15605 else
15606 /* We are creating a shared library or relocatable
15607 executable, and this is a reloc against a global symbol,
15608 or a non-PC-relative reloc against a local symbol.
15609 We may need to copy the reloc into the output. */
15610 may_become_dynamic_p = TRUE;
15611 }
f6e32f6d
RS		 15612 else
15613 may_need_local_target_p = TRUE;
252b5132
RH		 15614 break;
15615
99059e56
RM		 15616 /* This relocation describes the C++ object vtable hierarchy.
15617 Reconstruct it for later use during GC. */
15618 case R_ARM_GNU_VTINHERIT:
15619 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15620 return FALSE;
15621 break;
15622
15623 /* This relocation describes which C++ vtable entries are actually
15624 used. Record for later use during GC. */
15625 case R_ARM_GNU_VTENTRY:
a0ea3a14 15626 if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
99059e56
RM		 15627 return FALSE;
15628 break;
15629 }
f6e32f6d
RS		 15630
15631 if (h != NULL)
15632 {
15633 if (call_reloc_p)
15634 /* We may need a .plt entry if the function this reloc
15635 refers to is in a different object, regardless of the
15636 symbol's type. We can't tell for sure yet, because
15637 something later might force the symbol local. */
15638 h->needs_plt = 1;
15639 else if (may_need_local_target_p)
15640 /* If this reloc is in a read-only section, we might
15641 need a copy reloc. We can't check reliably at this
15642 stage whether the section is read-only, as input
15643 sections have not yet been mapped to output sections.
15644 Tentatively set the flag for now, and correct in
15645 adjust_dynamic_symbol. */
15646 h->non_got_ref = 1;
15647 }
15648
34e77a92
RS		 15649 if (may_need_local_target_p
15650 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 15651 {
34e77a92
RS		 15652 union gotplt_union *root_plt;
15653 struct arm_plt_info *arm_plt;
15654 struct arm_local_iplt_info *local_iplt;
15655
15656 if (h != NULL)
15657 {
15658 root_plt = &h->plt;
15659 arm_plt = &eh->plt;
15660 }
15661 else
15662 {
15663 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15664 if (local_iplt == NULL)
15665 return FALSE;
15666 root_plt = &local_iplt->root;
15667 arm_plt = &local_iplt->arm;
15668 }
15669
f6e32f6d
RS		 15670 /* If the symbol is a function that doesn't bind locally,
15671 this relocation will need a PLT entry. */
a8c887dd
NC		 15672 if (root_plt->refcount != -1)
15673 root_plt->refcount += 1;
34e77a92
RS		 15674
15675 if (!call_reloc_p)
15676 arm_plt->noncall_refcount++;
f6e32f6d
RS		 15677
15678 /* It's too early to use htab->use_blx here, so we have to
15679 record possible blx references separately from
15680 relocs that definitely need a thumb stub. */
15681
15682 if (r_type == R_ARM_THM_CALL)
34e77a92 15683 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 15684
15685 if (r_type == R_ARM_THM_JUMP24
15686 || r_type == R_ARM_THM_JUMP19)
34e77a92 15687 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 15688 }
15689
15690 if (may_become_dynamic_p)
15691 {
15692 struct elf_dyn_relocs *p, **head;
15693
15694 /* Create a reloc section in dynobj. */
15695 if (sreloc == NULL)
15696 {
15697 sreloc = _bfd_elf_make_dynamic_reloc_section
15698 (sec, dynobj, 2, abfd, ! htab->use_rel);
15699
15700 if (sreloc == NULL)
15701 return FALSE;
15702
15703 /* BPABI objects never have dynamic relocations mapped. */
15704 if (htab->symbian_p)
15705 {
15706 flagword flags;
15707
fd361982 15708 flags = bfd_section_flags (sreloc);
f6e32f6d 15709 flags &= ~(SEC_LOAD | SEC_ALLOC);
fd361982 15710 bfd_set_section_flags (sreloc, flags);
f6e32f6d
RS		 15711 }
15712 }
15713
15714 /* If this is a global symbol, count the number of
15715 relocations we need for this symbol. */
15716 if (h != NULL)
15717 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
15718 else
15719 {
34e77a92
RS		 15720 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15721 if (head == NULL)
f6e32f6d 15722 return FALSE;
f6e32f6d
RS		 15723 }
15724
15725 p = *head;
15726 if (p == NULL || p->sec != sec)
15727 {
15728 bfd_size_type amt = sizeof *p;
15729
15730 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15731 if (p == NULL)
15732 return FALSE;
15733 p->next = *head;
15734 *head = p;
15735 p->sec = sec;
15736 p->count = 0;
15737 p->pc_count = 0;
15738 }
15739
469a3493 15740 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 15741 p->pc_count += 1;
15742 p->count += 1;
e8b09b87
CL		 15743 if (h == NULL && htab->fdpic_p && !bfd_link_pic(info)
15744 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI) {
15745 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15746 that will become rofixup. */
15747 /* This is due to the fact that we suppose all will become rofixup. */
15748 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15749 _bfd_error_handler
15750 (_("FDPIC does not yet support %s relocation"
15751 " to become dynamic for executable"),
15752 elf32_arm_howto_table_1[r_type].name);
15753 abort();
15754 }
f6e32f6d 15755 }
252b5132 15756 }
f21f3fe0 15757
b34976b6 15758 return TRUE;
252b5132
RH		 15759}
15760
9eaff861
AO		 15761static void
15762elf32_arm_update_relocs (asection *o,
15763 struct bfd_elf_section_reloc_data *reldata)
15764{
15765 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15766 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15767 const struct elf_backend_data *bed;
15768 _arm_elf_section_data *eado;
15769 struct bfd_link_order *p;
15770 bfd_byte *erela_head, *erela;
15771 Elf_Internal_Rela *irela_head, *irela;
15772 Elf_Internal_Shdr *rel_hdr;
15773 bfd *abfd;
15774 unsigned int count;
15775
15776 eado = get_arm_elf_section_data (o);
15777
15778 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15779 return;
15780
15781 abfd = o->owner;
15782 bed = get_elf_backend_data (abfd);
15783 rel_hdr = reldata->hdr;
15784
15785 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15786 {
15787 swap_in = bed->s->swap_reloc_in;
15788 swap_out = bed->s->swap_reloc_out;
15789 }
15790 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15791 {
15792 swap_in = bed->s->swap_reloca_in;
15793 swap_out = bed->s->swap_reloca_out;
15794 }
15795 else
15796 abort ();
15797
15798 erela_head = rel_hdr->contents;
15799 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15800 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15801
15802 erela = erela_head;
15803 irela = irela_head;
15804 count = 0;
15805
15806 for (p = o->map_head.link_order; p; p = p->next)
15807 {
15808 if (p->type == bfd_section_reloc_link_order
15809 || p->type == bfd_symbol_reloc_link_order)
15810 {
15811 (*swap_in) (abfd, erela, irela);
15812 erela += rel_hdr->sh_entsize;
15813 irela++;
15814 count++;
15815 }
15816 else if (p->type == bfd_indirect_link_order)
15817 {
15818 struct bfd_elf_section_reloc_data *input_reldata;
15819 arm_unwind_table_edit *edit_list, *edit_tail;
15820 _arm_elf_section_data *eadi;
15821 bfd_size_type j;
15822 bfd_vma offset;
15823 asection *i;
15824
15825 i = p->u.indirect.section;
15826
15827 eadi = get_arm_elf_section_data (i);
15828 edit_list = eadi->u.exidx.unwind_edit_list;
15829 edit_tail = eadi->u.exidx.unwind_edit_tail;
539300fb 15830 offset = i->output_offset;
9eaff861
AO		 15831
15832 if (eadi->elf.rel.hdr &&
15833 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15834 input_reldata = &eadi->elf.rel;
15835 else if (eadi->elf.rela.hdr &&
15836 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15837 input_reldata = &eadi->elf.rela;
15838 else
15839 abort ();
15840
15841 if (edit_list)
15842 {
15843 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15844 {
15845 arm_unwind_table_edit *edit_node, *edit_next;
15846 bfd_vma bias;
c48182bf 15847 bfd_vma reloc_index;
9eaff861
AO		 15848
15849 (*swap_in) (abfd, erela, irela);
c48182bf 15850 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 15851
15852 bias = 0;
15853 edit_node = edit_list;
15854 for (edit_next = edit_list;
c48182bf 15855 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 15856 edit_next = edit_node->next)
15857 {
15858 bias++;
15859 edit_node = edit_next;
15860 }
15861
15862 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 15863 || edit_node->index != reloc_index)
9eaff861
AO		 15864 {
15865 irela->r_offset -= bias * 8;
15866 irela++;
15867 count++;
15868 }
15869
15870 erela += rel_hdr->sh_entsize;
15871 }
15872
15873 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15874 {
15875 /* New relocation entity. */
15876 asection *text_sec = edit_tail->linked_section;
15877 asection *text_out = text_sec->output_section;
15878 bfd_vma exidx_offset = offset + i->size - 8;
15879
15880 irela->r_addend = 0;
15881 irela->r_offset = exidx_offset;
15882 irela->r_info = ELF32_R_INFO
15883 (text_out->target_index, R_ARM_PREL31);
15884 irela++;
15885 count++;
15886 }
15887 }
15888 else
15889 {
15890 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15891 {
15892 (*swap_in) (abfd, erela, irela);
15893 erela += rel_hdr->sh_entsize;
15894 irela++;
15895 }
15896
15897 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15898 }
15899 }
15900 }
15901
15902 reldata->count = count;
15903 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15904
15905 erela = erela_head;
15906 irela = irela_head;
15907 while (count > 0)
15908 {
15909 (*swap_out) (abfd, irela, erela);
15910 erela += rel_hdr->sh_entsize;
15911 irela++;
15912 count--;
15913 }
15914
15915 free (irela_head);
15916
15917 /* Hashes are no longer valid. */
15918 free (reldata->hashes);
15919 reldata->hashes = NULL;
15920}
15921
6a5bb875 15922/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15923 required if the corresponding code section is marked. Similarly, ARMv8-M
15924 secure entry functions can only be referenced by SG veneers which are
15925 created after the GC process. They need to be marked in case they reside in
15926 their own section (as would be the case if code was compiled with
15927 -ffunction-sections). */
6a5bb875
PB		 15928
15929static bfd_boolean
906e58ca
NC		 15930elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15931 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15932{
15933 bfd *sub;
15934 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15935 asection *cmse_sec;
15936 obj_attribute *out_attr;
15937 Elf_Internal_Shdr *symtab_hdr;
15938 unsigned i, sym_count, ext_start;
15939 const struct elf_backend_data *bed;
15940 struct elf_link_hash_entry **sym_hashes;
15941 struct elf32_arm_link_hash_entry *cmse_hash;
15942 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
bb32413f
SP		 15943 bfd_boolean debug_sec_need_to_be_marked = FALSE;
15944 asection *isec;
6a5bb875 15945
7f6ab9f8
AM		 15946 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15947
4ba2ef8f
TP		 15948 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15949 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15950 && out_attr[Tag_CPU_arch_profile].i == 'M';
15951
6a5bb875
PB		 15952 /* Marking EH data may cause additional code sections to be marked,
15953 requiring multiple passes. */
15954 again = TRUE;
15955 while (again)
15956 {
15957 again = FALSE;
c72f2fb2 15958 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15959 {
15960 asection *o;
15961
0ffa91dd 15962 if (! is_arm_elf (sub))
6a5bb875
PB		 15963 continue;
15964
15965 elf_shdrp = elf_elfsections (sub);
15966 for (o = sub->sections; o != NULL; o = o->next)
15967 {
15968 Elf_Internal_Shdr *hdr;
0ffa91dd 15969
6a5bb875 15970 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15971 if (hdr->sh_type == SHT_ARM_EXIDX
15972 && hdr->sh_link
15973 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15974 && !o->gc_mark
15975 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15976 {
15977 again = TRUE;
15978 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15979 return FALSE;
15980 }
15981 }
4ba2ef8f
TP		 15982
15983 /* Mark section holding ARMv8-M secure entry functions. We mark all
15984 of them so no need for a second browsing. */
15985 if (is_v8m && first_bfd_browse)
15986 {
15987 sym_hashes = elf_sym_hashes (sub);
15988 bed = get_elf_backend_data (sub);
15989 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15990 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15991 ext_start = symtab_hdr->sh_info;
15992
15993 /* Scan symbols. */
15994 for (i = ext_start; i < sym_count; i++)
15995 {
15996 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15997
15998 /* Assume it is a special symbol. If not, cmse_scan will
15999 warn about it and user can do something about it. */
baf46cd7
AM		 16000 if (CONST_STRNEQ (cmse_hash->root.root.root.string,
16001 CMSE_PREFIX))
4ba2ef8f
TP		 16002 {
16003 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 16004 if (!cmse_sec->gc_mark
16005 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f 16006 return FALSE;
bb32413f
SP		 16007 /* The debug sections related to these secure entry
16008 functions are marked on enabling below flag. */
16009 debug_sec_need_to_be_marked = TRUE;
4ba2ef8f
TP		 16010 }
16011 }
bb32413f
SP		 16012
16013 if (debug_sec_need_to_be_marked)
16014 {
16015 /* Looping over all the sections of the object file containing
16016 Armv8-M secure entry functions and marking all the debug
16017 sections. */
16018 for (isec = sub->sections; isec != NULL; isec = isec->next)
16019 {
16020 /* If not a debug sections, skip it. */
16021 if (!isec->gc_mark && (isec->flags & SEC_DEBUGGING))
16022 isec->gc_mark = 1 ;
16023 }
16024 debug_sec_need_to_be_marked = FALSE;
16025 }
4ba2ef8f 16026 }
6a5bb875 16027 }
4ba2ef8f 16028 first_bfd_browse = FALSE;
6a5bb875
PB		 16029 }
16030
16031 return TRUE;
16032}
16033
3c9458e9
NC		 16034/* Treat mapping symbols as special target symbols. */
16035
16036static bfd_boolean
16037elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
16038{
b0796911
PB		 16039 return bfd_is_arm_special_symbol_name (sym->name,
16040 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 16041}
16042
e7679060
AM		 16043/* If the ELF symbol SYM might be a function in SEC, return the
16044 function size and set *CODE_OFF to the function's entry point,
16045 otherwise return zero. */
252b5132 16046
e7679060
AM		 16047static bfd_size_type
16048elf32_arm_maybe_function_sym (const asymbol *sym, asection *sec,
16049 bfd_vma *code_off)
16050{
16051 bfd_size_type size;
252b5132 16052
e7679060
AM		 16053 if ((sym->flags & (BSF_SECTION_SYM | BSF_FILE | BSF_OBJECT
16054 | BSF_THREAD_LOCAL | BSF_RELC | BSF_SRELC)) != 0
16055 || sym->section != sec)
16056 return 0;
252b5132 16057
e7679060
AM		 16058 if (!(sym->flags & BSF_SYNTHETIC))
16059 switch (ELF_ST_TYPE (((elf_symbol_type *) sym)->internal_elf_sym.st_info))
16060 {
252b5132
RH		 16061 case STT_FUNC:
16062 case STT_ARM_TFUNC:
9d2da7ca 16063 case STT_NOTYPE:
252b5132 16064 break;
e7679060
AM		 16065 default:
16066 return 0;
16067 }
0367ecfb 16068
e7679060
AM		 16069 if ((sym->flags & BSF_LOCAL)
16070 && bfd_is_arm_special_symbol_name (sym->name,
16071 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
16072 return 0;
0367ecfb 16073
e7679060
AM		 16074 *code_off = sym->value;
16075 size = 0;
16076 if (!(sym->flags & BSF_SYNTHETIC))
16077 size = ((elf_symbol_type *) sym)->internal_elf_sym.st_size;
16078 if (size == 0)
16079 size = 1;
16080 return size;
252b5132
RH		 16081}
16082
4ab527b0 16083static bfd_boolean
07d6d2b8 16084elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 16085 const char ** filename_ptr,
16086 const char ** functionname_ptr,
16087 unsigned int * line_ptr)
16088{
16089 bfd_boolean found;
16090 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
16091 functionname_ptr, line_ptr,
16092 & elf_tdata (abfd)->dwarf2_find_line_info);
16093 return found;
16094}
16095
63c1f59d
AM		 16096/* Find dynamic relocs for H that apply to read-only sections. */
16097
16098static asection *
16099readonly_dynrelocs (struct elf_link_hash_entry *h)
16100{
16101 struct elf_dyn_relocs *p;
16102
16103 for (p = elf32_arm_hash_entry (h)->dyn_relocs; p != NULL; p = p->next)
16104 {
16105 asection *s = p->sec->output_section;
16106
16107 if (s != NULL && (s->flags & SEC_READONLY) != 0)
16108 return p->sec;
16109 }
16110 return NULL;
16111}
16112
252b5132
RH		 16113/* Adjust a symbol defined by a dynamic object and referenced by a
16114 regular object. The current definition is in some section of the
16115 dynamic object, but we're not including those sections. We have to
16116 change the definition to something the rest of the link can
16117 understand. */
16118
b34976b6 16119static bfd_boolean
57e8b36a
NC		 16120elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
16121 struct elf_link_hash_entry * h)
252b5132
RH		 16122{
16123 bfd * dynobj;
5474d94f 16124 asection *s, *srel;
b7693d02 16125 struct elf32_arm_link_hash_entry * eh;
67687978 16126 struct elf32_arm_link_hash_table *globals;
252b5132 16127
67687978 16128 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16129 if (globals == NULL)
16130 return FALSE;
16131
252b5132
RH		 16132 dynobj = elf_hash_table (info)->dynobj;
16133
16134 /* Make sure we know what is going on here. */
16135 BFD_ASSERT (dynobj != NULL
f5385ebf 16136 && (h->needs_plt
34e77a92 16137 || h->type == STT_GNU_IFUNC
60d67dc8 16138 || h->is_weakalias
f5385ebf
AM		 16139 || (h->def_dynamic
16140 && h->ref_regular
16141 && !h->def_regular)));
252b5132 16142
b7693d02
DJ		 16143 eh = (struct elf32_arm_link_hash_entry *) h;
16144
252b5132
RH		 16145 /* If this is a function, put it in the procedure linkage table. We
16146 will fill in the contents of the procedure linkage table later,
16147 when we know the address of the .got section. */
34e77a92 16148 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 16149 {
34e77a92
RS		 16150 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16151 symbol binds locally. */
5e681ec4 16152 if (h->plt.refcount <= 0
34e77a92
RS		 16153 || (h->type != STT_GNU_IFUNC
16154 && (SYMBOL_CALLS_LOCAL (info, h)
16155 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16156 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 16157 {
16158 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 16159 file, but the symbol was never referred to by a dynamic
16160 object, or if all references were garbage collected. In
16161 such a case, we don't actually need to build a procedure
16162 linkage table, and we can just do a PC24 reloc instead. */
16163 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16164 eh->plt.thumb_refcount = 0;
16165 eh->plt.maybe_thumb_refcount = 0;
16166 eh->plt.noncall_refcount = 0;
f5385ebf 16167 h->needs_plt = 0;
252b5132
RH		 16168 }
16169
b34976b6 16170 return TRUE;
252b5132 16171 }
5e681ec4 16172 else
b7693d02
DJ		 16173 {
16174 /* It's possible that we incorrectly decided a .plt reloc was
16175 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16176 in check_relocs. We can't decide accurately between function
16177 and non-function syms in check-relocs; Objects loaded later in
16178 the link may change h->type. So fix it now. */
16179 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16180 eh->plt.thumb_refcount = 0;
16181 eh->plt.maybe_thumb_refcount = 0;
16182 eh->plt.noncall_refcount = 0;
b7693d02 16183 }
252b5132
RH		 16184
16185 /* If this is a weak symbol, and there is a real definition, the
16186 processor independent code will have arranged for us to see the
16187 real definition first, and we can just use the same value. */
60d67dc8 16188 if (h->is_weakalias)
252b5132 16189 {
60d67dc8
AM		 16190 struct elf_link_hash_entry *def = weakdef (h);
16191 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
16192 h->root.u.def.section = def->root.u.def.section;
16193 h->root.u.def.value = def->root.u.def.value;
b34976b6 16194 return TRUE;
252b5132
RH		 16195 }
16196
ba93b8ac
DJ		 16197 /* If there are no non-GOT references, we do not need a copy
16198 relocation. */
16199 if (!h->non_got_ref)
16200 return TRUE;
16201
252b5132
RH		 16202 /* This is a reference to a symbol defined by a dynamic object which
16203 is not a function. */
16204
16205 /* If we are creating a shared library, we must presume that the
16206 only references to the symbol are via the global offset table.
16207 For such cases we need not do anything here; the relocations will
67687978
PB		 16208 be handled correctly by relocate_section. Relocatable executables
16209 can reference data in shared objects directly, so we don't need to
16210 do anything here. */
0e1862bb 16211 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 16212 return TRUE;
252b5132
RH		 16213
16214 /* We must allocate the symbol in our .dynbss section, which will
16215 become part of the .bss section of the executable. There will be
16216 an entry for this symbol in the .dynsym section. The dynamic
16217 object will contain position independent code, so all references
16218 from the dynamic object to this symbol will go through the global
16219 offset table. The dynamic linker will use the .dynsym entry to
16220 determine the address it must put in the global offset table, so
16221 both the dynamic object and the regular object will refer to the
16222 same memory location for the variable. */
5522f910
NC		 16223 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16224 linker to copy the initial value out of the dynamic object and into
16225 the runtime process image. We need to remember the offset into the
00a97672 16226 .rel(a).bss section we are going to use. */
5474d94f
AM		 16227 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
16228 {
16229 s = globals->root.sdynrelro;
16230 srel = globals->root.sreldynrelro;
16231 }
16232 else
16233 {
16234 s = globals->root.sdynbss;
16235 srel = globals->root.srelbss;
16236 }
5522f910
NC		 16237 if (info->nocopyreloc == 0
16238 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 16239 && h->size != 0)
252b5132 16240 {
47beaa6a 16241 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 16242 h->needs_copy = 1;
252b5132
RH		 16243 }
16244
6cabe1ea 16245 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 16246}
16247
5e681ec4
PB		 16248/* Allocate space in .plt, .got and associated reloc sections for
16249 dynamic relocs. */
16250
16251static bfd_boolean
47beaa6a 16252allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 16253{
16254 struct bfd_link_info *info;
16255 struct elf32_arm_link_hash_table *htab;
16256 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 16257 struct elf_dyn_relocs *p;
5e681ec4
PB		 16258
16259 if (h->root.type == bfd_link_hash_indirect)
16260 return TRUE;
16261
e6a6bb22
AM		 16262 eh = (struct elf32_arm_link_hash_entry *) h;
16263
5e681ec4
PB		 16264 info = (struct bfd_link_info *) inf;
16265 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16266 if (htab == NULL)
16267 return FALSE;
5e681ec4 16268
34e77a92 16269 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 16270 && h->plt.refcount > 0)
16271 {
16272 /* Make sure this symbol is output as a dynamic symbol.
16273 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16274 if (h->dynindx == -1 && !h->forced_local
16275 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16276 {
c152c796 16277 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16278 return FALSE;
16279 }
16280
34e77a92
RS		 16281 /* If the call in the PLT entry binds locally, the associated
16282 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16283 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16284 than the .plt section. */
16285 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16286 {
16287 eh->is_iplt = 1;
16288 if (eh->plt.noncall_refcount == 0
16289 && SYMBOL_REFERENCES_LOCAL (info, h))
16290 /* All non-call references can be resolved directly.
16291 This means that they can (and in some cases, must)
16292 resolve directly to the run-time target, rather than
16293 to the PLT. That in turns means that any .got entry
16294 would be equal to the .igot.plt entry, so there's
16295 no point having both. */
16296 h->got.refcount = 0;
16297 }
16298
0e1862bb 16299 if (bfd_link_pic (info)
34e77a92 16300 || eh->is_iplt
7359ea65 16301 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 16302 {
34e77a92 16303 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 16304
5e681ec4
PB		 16305 /* If this symbol is not defined in a regular file, and we are
16306 not generating a shared library, then set the symbol to this
16307 location in the .plt. This is required to make function
16308 pointers compare as equal between the normal executable and
16309 the shared library. */
0e1862bb 16310 if (! bfd_link_pic (info)
f5385ebf 16311 && !h->def_regular)
5e681ec4 16312 {
34e77a92 16313 h->root.u.def.section = htab->root.splt;
5e681ec4 16314 h->root.u.def.value = h->plt.offset;
5e681ec4 16315
67d74e43
DJ		 16316 /* Make sure the function is not marked as Thumb, in case
16317 it is the target of an ABS32 relocation, which will
16318 point to the PLT entry. */
39d911fc 16319 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 16320 }
022f8312 16321
00a97672
RS		 16322 /* VxWorks executables have a second set of relocations for
16323 each PLT entry. They go in a separate relocation section,
16324 which is processed by the kernel loader. */
0e1862bb 16325 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 16326 {
16327 /* There is a relocation for the initial PLT entry:
16328 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16329 if (h->plt.offset == htab->plt_header_size)
47beaa6a 16330 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 16331
16332 /* There are two extra relocations for each subsequent
16333 PLT entry: an R_ARM_32 relocation for the GOT entry,
16334 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 16335 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 16336 }
5e681ec4
PB		 16337 }
16338 else
16339 {
16340 h->plt.offset = (bfd_vma) -1;
f5385ebf 16341 h->needs_plt = 0;
5e681ec4
PB		 16342 }
16343 }
16344 else
16345 {
16346 h->plt.offset = (bfd_vma) -1;
f5385ebf 16347 h->needs_plt = 0;
5e681ec4
PB		 16348 }
16349
0855e32b
NS		 16350 eh = (struct elf32_arm_link_hash_entry *) h;
16351 eh->tlsdesc_got = (bfd_vma) -1;
16352
5e681ec4
PB		 16353 if (h->got.refcount > 0)
16354 {
16355 asection *s;
16356 bfd_boolean dyn;
ba93b8ac
DJ		 16357 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16358 int indx;
5e681ec4
PB		 16359
16360 /* Make sure this symbol is output as a dynamic symbol.
16361 Undefined weak syms won't yet be marked as dynamic. */
e8b09b87 16362 if (htab->root.dynamic_sections_created && h->dynindx == -1 && !h->forced_local
6c699715 16363 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16364 {
c152c796 16365 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16366 return FALSE;
16367 }
16368
e5a52504
MM		 16369 if (!htab->symbian_p)
16370 {
362d30a1 16371 s = htab->root.sgot;
e5a52504 16372 h->got.offset = s->size;
ba93b8ac
DJ		 16373
16374 if (tls_type == GOT_UNKNOWN)
16375 abort ();
16376
16377 if (tls_type == GOT_NORMAL)
16378 /* Non-TLS symbols need one GOT slot. */
16379 s->size += 4;
16380 else
16381 {
99059e56
RM		 16382 if (tls_type & GOT_TLS_GDESC)
16383 {
0855e32b 16384 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 16385 eh->tlsdesc_got
0855e32b
NS		 16386 = (htab->root.sgotplt->size
16387 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 16388 htab->root.sgotplt->size += 8;
16389 h->got.offset = (bfd_vma) -2;
34e77a92 16390 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16391 reloc in the middle of .got.plt. */
99059e56
RM		 16392 htab->num_tls_desc++;
16393 }
0855e32b 16394
ba93b8ac 16395 if (tls_type & GOT_TLS_GD)
0855e32b 16396 {
5c5a4843
CL		 16397 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16398 consecutive GOT slots. If the symbol is both GD
16399 and GDESC, got.offset may have been
16400 overwritten. */
0855e32b
NS		 16401 h->got.offset = s->size;
16402 s->size += 8;
16403 }
16404
ba93b8ac 16405 if (tls_type & GOT_TLS_IE)
5c5a4843
CL		 16406 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16407 slot. */
ba93b8ac
DJ		 16408 s->size += 4;
16409 }
16410
e5a52504 16411 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 16412
16413 indx = 0;
0e1862bb
L		 16414 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
16415 bfd_link_pic (info),
16416 h)
16417 && (!bfd_link_pic (info)
ba93b8ac
DJ		 16418 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16419 indx = h->dynindx;
16420
16421 if (tls_type != GOT_NORMAL
9cb09e33 16422 && (bfd_link_dll (info) || indx != 0)
ba93b8ac
DJ		 16423 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16424 || h->root.type != bfd_link_hash_undefweak))
16425 {
16426 if (tls_type & GOT_TLS_IE)
47beaa6a 16427 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16428
16429 if (tls_type & GOT_TLS_GD)
47beaa6a 16430 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16431
b38cadfb 16432 if (tls_type & GOT_TLS_GDESC)
0855e32b 16433 {
47beaa6a 16434 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 16435 /* GDESC needs a trampoline to jump to. */
16436 htab->tls_trampoline = -1;
16437 }
16438
16439 /* Only GD needs it. GDESC just emits one relocation per
16440 2 entries. */
b38cadfb 16441 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 16442 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16443 }
e8b09b87
CL		 16444 else if (((indx != -1) || htab->fdpic_p)
16445 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 16446 {
16447 if (htab->root.dynamic_sections_created)
16448 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16449 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16450 }
34e77a92
RS		 16451 else if (h->type == STT_GNU_IFUNC
16452 && eh->plt.noncall_refcount == 0)
16453 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16454 they all resolve dynamically instead. Reserve room for the
16455 GOT entry's R_ARM_IRELATIVE relocation. */
16456 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 16457 else if (bfd_link_pic (info)
16458 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16459 || h->root.type != bfd_link_hash_undefweak))
b436d854 16460 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 16461 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16462 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16463 /* Reserve room for rofixup for FDPIC executable. */
16464 /* TLS relocs do not need space since they are completely
16465 resolved. */
16466 htab->srofixup->size += 4;
e5a52504 16467 }
5e681ec4
PB		 16468 }
16469 else
16470 h->got.offset = (bfd_vma) -1;
16471
e8b09b87
CL		 16472 /* FDPIC support. */
16473 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16474 {
16475 /* Symbol musn't be exported. */
16476 if (h->dynindx != -1)
16477 abort();
16478
16479 /* We only allocate one function descriptor with its associated relocation. */
16480 if (eh->fdpic_cnts.funcdesc_offset == -1)
16481 {
16482 asection *s = htab->root.sgot;
16483
16484 eh->fdpic_cnts.funcdesc_offset = s->size;
16485 s->size += 8;
16486 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16487 if (bfd_link_pic(info))
16488 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16489 else
16490 htab->srofixup->size += 8;
16491 }
16492 }
16493
16494 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16495 {
16496 asection *s = htab->root.sgot;
16497
16498 if (htab->root.dynamic_sections_created && h->dynindx == -1
16499 && !h->forced_local)
16500 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16501 return FALSE;
16502
16503 if (h->dynindx == -1)
16504 {
16505 /* We only allocate one function descriptor with its associated relocation. q */
16506 if (eh->fdpic_cnts.funcdesc_offset == -1)
16507 {
16508
16509 eh->fdpic_cnts.funcdesc_offset = s->size;
16510 s->size += 8;
16511 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16512 if (bfd_link_pic(info))
16513 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16514 else
16515 htab->srofixup->size += 8;
16516 }
16517 }
16518
16519 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16520 R_ARM_RELATIVE/rofixup relocation on it. */
16521 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16522 s->size += 4;
16523 if (h->dynindx == -1 && !bfd_link_pic(info))
4b24dd1a 16524 htab->srofixup->size += 4;
e8b09b87 16525 else
4b24dd1a 16526 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16527 }
16528
16529 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16530 {
16531 if (htab->root.dynamic_sections_created && h->dynindx == -1
16532 && !h->forced_local)
16533 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16534 return FALSE;
16535
16536 if (h->dynindx == -1)
16537 {
16538 /* We only allocate one function descriptor with its associated relocation. */
16539 if (eh->fdpic_cnts.funcdesc_offset == -1)
16540 {
16541 asection *s = htab->root.sgot;
16542
16543 eh->fdpic_cnts.funcdesc_offset = s->size;
16544 s->size += 8;
16545 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16546 if (bfd_link_pic(info))
16547 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16548 else
16549 htab->srofixup->size += 8;
16550 }
16551 }
16552 if (h->dynindx == -1 && !bfd_link_pic(info))
16553 {
16554 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16555 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16556 }
16557 else
16558 {
16559 /* Will need one dynamic reloc per reference. will be either
16560 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16561 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16562 eh->fdpic_cnts.funcdesc_cnt);
16563 }
16564 }
16565
a4fd1a8e
PB		 16566 /* Allocate stubs for exported Thumb functions on v4t. */
16567 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 16568 && h->def_regular
39d911fc 16569 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 16570 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16571 {
16572 struct elf_link_hash_entry * th;
16573 struct bfd_link_hash_entry * bh;
16574 struct elf_link_hash_entry * myh;
16575 char name[1024];
16576 asection *s;
16577 bh = NULL;
16578 /* Create a new symbol to regist the real location of the function. */
16579 s = h->root.u.def.section;
906e58ca 16580 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 16581 _bfd_generic_link_add_one_symbol (info, s->owner,
16582 name, BSF_GLOBAL, s,
16583 h->root.u.def.value,
16584 NULL, TRUE, FALSE, &bh);
16585
16586 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 16587 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 16588 myh->forced_local = 1;
39d911fc 16589 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 16590 eh->export_glue = myh;
16591 th = record_arm_to_thumb_glue (info, h);
16592 /* Point the symbol at the stub. */
16593 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 16594 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 16595 h->root.u.def.section = th->root.u.def.section;
16596 h->root.u.def.value = th->root.u.def.value & ~1;
16597 }
16598
0bdcacaf 16599 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 16600 return TRUE;
16601
16602 /* In the shared -Bsymbolic case, discard space allocated for
16603 dynamic pc-relative relocs against symbols which turn out to be
16604 defined in regular objects. For the normal shared case, discard
16605 space for pc-relative relocs that have become local due to symbol
16606 visibility changes. */
16607
e8b09b87 16608 if (bfd_link_pic (info) || htab->root.is_relocatable_executable || htab->fdpic_p)
5e681ec4 16609 {
469a3493
RM		 16610 /* Relocs that use pc_count are PC-relative forms, which will appear
16611 on something like ".long foo - ." or "movw REG, foo - .". We want
16612 calls to protected symbols to resolve directly to the function
16613 rather than going via the plt. If people want function pointer
16614 comparisons to work as expected then they should avoid writing
16615 assembly like ".long foo - .". */
ba93b8ac
DJ		 16616 if (SYMBOL_CALLS_LOCAL (info, h))
16617 {
0bdcacaf 16618 struct elf_dyn_relocs **pp;
ba93b8ac 16619
0bdcacaf 16620 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 16621 {
16622 p->count -= p->pc_count;
16623 p->pc_count = 0;
16624 if (p->count == 0)
16625 *pp = p->next;
16626 else
16627 pp = &p->next;
16628 }
16629 }
16630
4dfe6ac6 16631 if (htab->vxworks_p)
3348747a 16632 {
0bdcacaf 16633 struct elf_dyn_relocs **pp;
3348747a 16634
0bdcacaf 16635 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 16636 {
0bdcacaf 16637 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 16638 *pp = p->next;
16639 else
16640 pp = &p->next;
16641 }
16642 }
16643
ba93b8ac 16644 /* Also discard relocs on undefined weak syms with non-default
99059e56 16645 visibility. */
0bdcacaf 16646 if (eh->dyn_relocs != NULL
5e681ec4 16647 && h->root.type == bfd_link_hash_undefweak)
22d606e9 16648 {
95b03e4a
L		 16649 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16650 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
0bdcacaf 16651 eh->dyn_relocs = NULL;
22d606e9
AM		 16652
16653 /* Make sure undefined weak symbols are output as a dynamic
16654 symbol in PIEs. */
e8b09b87 16655 else if (htab->root.dynamic_sections_created && h->dynindx == -1
22d606e9
AM		 16656 && !h->forced_local)
16657 {
16658 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16659 return FALSE;
16660 }
16661 }
16662
67687978
PB		 16663 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16664 && h->root.type == bfd_link_hash_new)
16665 {
16666 /* Output absolute symbols so that we can create relocations
16667 against them. For normal symbols we output a relocation
16668 against the section that contains them. */
16669 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16670 return FALSE;
16671 }
16672
5e681ec4
PB		 16673 }
16674 else
16675 {
16676 /* For the non-shared case, discard space for relocs against
16677 symbols which turn out to need copy relocs or are not
16678 dynamic. */
16679
f5385ebf
AM		 16680 if (!h->non_got_ref
16681 && ((h->def_dynamic
16682 && !h->def_regular)
5e681ec4
PB		 16683 || (htab->root.dynamic_sections_created
16684 && (h->root.type == bfd_link_hash_undefweak
16685 || h->root.type == bfd_link_hash_undefined))))
16686 {
16687 /* Make sure this symbol is output as a dynamic symbol.
16688 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16689 if (h->dynindx == -1 && !h->forced_local
16690 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16691 {
c152c796 16692 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16693 return FALSE;
16694 }
16695
16696 /* If that succeeded, we know we'll be keeping all the
16697 relocs. */
16698 if (h->dynindx != -1)
16699 goto keep;
16700 }
16701
0bdcacaf 16702 eh->dyn_relocs = NULL;
5e681ec4
PB		 16703
16704 keep: ;
16705 }
16706
16707 /* Finally, allocate space. */
0bdcacaf 16708 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 16709 {
0bdcacaf 16710 asection *sreloc = elf_section_data (p->sec)->sreloc;
e8b09b87 16711
34e77a92
RS		 16712 if (h->type == STT_GNU_IFUNC
16713 && eh->plt.noncall_refcount == 0
16714 && SYMBOL_REFERENCES_LOCAL (info, h))
16715 elf32_arm_allocate_irelocs (info, sreloc, p->count);
e8b09b87
CL		 16716 else if (h->dynindx != -1 && (!bfd_link_pic(info) || !info->symbolic || !h->def_regular))
16717 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16718 else if (htab->fdpic_p && !bfd_link_pic(info))
16719 htab->srofixup->size += 4 * p->count;
34e77a92
RS		 16720 else
16721 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 16722 }
16723
16724 return TRUE;
16725}
16726
63c1f59d
AM		 16727/* Set DF_TEXTREL if we find any dynamic relocs that apply to
16728 read-only sections. */
08d1f311
DJ		 16729
16730static bfd_boolean
63c1f59d 16731maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p)
08d1f311 16732{
63c1f59d 16733 asection *sec;
08d1f311 16734
63c1f59d
AM		 16735 if (h->root.type == bfd_link_hash_indirect)
16736 return TRUE;
08d1f311 16737
63c1f59d
AM		 16738 sec = readonly_dynrelocs (h);
16739 if (sec != NULL)
16740 {
16741 struct bfd_link_info *info = (struct bfd_link_info *) info_p;
08d1f311 16742
63c1f59d
AM		 16743 info->flags |= DF_TEXTREL;
16744 info->callbacks->minfo
c1c8c1ef 16745 (_("%pB: dynamic relocation against `%pT' in read-only section `%pA'\n"),
63c1f59d 16746 sec->owner, h->root.root.string, sec);
08d1f311 16747
63c1f59d
AM		 16748 /* Not an error, just cut short the traversal. */
16749 return FALSE;
08d1f311 16750 }
cb10292c 16751
08d1f311
DJ		 16752 return TRUE;
16753}
16754
d504ffc8
DJ		 16755void
16756bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16757 int byteswap_code)
16758{
16759 struct elf32_arm_link_hash_table *globals;
16760
16761 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16762 if (globals == NULL)
16763 return;
16764
d504ffc8
DJ		 16765 globals->byteswap_code = byteswap_code;
16766}
16767
252b5132
RH		 16768/* Set the sizes of the dynamic sections. */
16769
b34976b6 16770static bfd_boolean
57e8b36a
NC		 16771elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16772 struct bfd_link_info * info)
252b5132
RH		 16773{
16774 bfd * dynobj;
16775 asection * s;
b34976b6
AM		 16776 bfd_boolean plt;
16777 bfd_boolean relocs;
5e681ec4
PB		 16778 bfd *ibfd;
16779 struct elf32_arm_link_hash_table *htab;
252b5132 16780
5e681ec4 16781 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16782 if (htab == NULL)
16783 return FALSE;
16784
252b5132
RH		 16785 dynobj = elf_hash_table (info)->dynobj;
16786 BFD_ASSERT (dynobj != NULL);
39b41c9c 16787 check_use_blx (htab);
252b5132
RH		 16788
16789 if (elf_hash_table (info)->dynamic_sections_created)
16790 {
16791 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 16792 if (bfd_link_executable (info) && !info->nointerp)
252b5132 16793 {
3d4d4302 16794 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 16795 BFD_ASSERT (s != NULL);
eea6121a 16796 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 16797 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16798 }
16799 }
5e681ec4
PB		 16800
16801 /* Set up .got offsets for local syms, and space for local dynamic
16802 relocs. */
c72f2fb2 16803 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 16804 {
5e681ec4
PB		 16805 bfd_signed_vma *local_got;
16806 bfd_signed_vma *end_local_got;
34e77a92 16807 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 16808 char *local_tls_type;
0855e32b 16809 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 16810 bfd_size_type locsymcount;
16811 Elf_Internal_Shdr *symtab_hdr;
16812 asection *srel;
4dfe6ac6 16813 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 16814 unsigned int symndx;
e8b09b87 16815 struct fdpic_local *local_fdpic_cnts;
5e681ec4 16816
0ffa91dd 16817 if (! is_arm_elf (ibfd))
5e681ec4
PB		 16818 continue;
16819
16820 for (s = ibfd->sections; s != NULL; s = s->next)
16821 {
0bdcacaf 16822 struct elf_dyn_relocs *p;
5e681ec4 16823
0bdcacaf 16824 for (p = (struct elf_dyn_relocs *)
99059e56 16825 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 16826 {
0bdcacaf
RS		 16827 if (!bfd_is_abs_section (p->sec)
16828 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 16829 {
16830 /* Input section has been discarded, either because
16831 it is a copy of a linkonce section or due to
16832 linker script /DISCARD/, so we'll be discarding
16833 the relocs too. */
16834 }
3348747a 16835 else if (is_vxworks
0bdcacaf 16836 && strcmp (p->sec->output_section->name,
3348747a
NS		 16837 ".tls_vars") == 0)
16838 {
16839 /* Relocations in vxworks .tls_vars sections are
16840 handled specially by the loader. */
16841 }
5e681ec4
PB		 16842 else if (p->count != 0)
16843 {
0bdcacaf 16844 srel = elf_section_data (p->sec)->sreloc;
e8b09b87
CL		 16845 if (htab->fdpic_p && !bfd_link_pic(info))
16846 htab->srofixup->size += 4 * p->count;
16847 else
16848 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 16849 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 16850 info->flags |= DF_TEXTREL;
16851 }
16852 }
16853 }
16854
16855 local_got = elf_local_got_refcounts (ibfd);
16856 if (!local_got)
16857 continue;
16858
0ffa91dd 16859 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 16860 locsymcount = symtab_hdr->sh_info;
16861 end_local_got = local_got + locsymcount;
34e77a92 16862 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 16863 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 16864 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
e8b09b87 16865 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
34e77a92 16866 symndx = 0;
362d30a1
RS		 16867 s = htab->root.sgot;
16868 srel = htab->root.srelgot;
0855e32b 16869 for (; local_got < end_local_got;
34e77a92 16870 ++local_got, ++local_iplt_ptr, ++local_tls_type,
e8b09b87 16871 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
5e681ec4 16872 {
0855e32b 16873 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92 16874 local_iplt = *local_iplt_ptr;
e8b09b87
CL		 16875
16876 /* FDPIC support. */
16877 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16878 {
16879 if (local_fdpic_cnts->funcdesc_offset == -1)
16880 {
16881 local_fdpic_cnts->funcdesc_offset = s->size;
16882 s->size += 8;
16883
16884 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16885 if (bfd_link_pic(info))
16886 elf32_arm_allocate_dynrelocs (info, srel, 1);
16887 else
16888 htab->srofixup->size += 8;
16889 }
16890 }
16891
16892 if (local_fdpic_cnts->funcdesc_cnt > 0)
16893 {
16894 if (local_fdpic_cnts->funcdesc_offset == -1)
16895 {
16896 local_fdpic_cnts->funcdesc_offset = s->size;
16897 s->size += 8;
16898
16899 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16900 if (bfd_link_pic(info))
16901 elf32_arm_allocate_dynrelocs (info, srel, 1);
16902 else
16903 htab->srofixup->size += 8;
16904 }
16905
16906 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16907 if (bfd_link_pic(info))
16908 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16909 else
16910 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16911 }
16912
34e77a92
RS		 16913 if (local_iplt != NULL)
16914 {
16915 struct elf_dyn_relocs *p;
16916
16917 if (local_iplt->root.refcount > 0)
16918 {
16919 elf32_arm_allocate_plt_entry (info, TRUE,
16920 &local_iplt->root,
16921 &local_iplt->arm);
16922 if (local_iplt->arm.noncall_refcount == 0)
16923 /* All references to the PLT are calls, so all
16924 non-call references can resolve directly to the
16925 run-time target. This means that the .got entry
16926 would be the same as the .igot.plt entry, so there's
16927 no point creating both. */
16928 *local_got = 0;
16929 }
16930 else
16931 {
16932 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
16933 local_iplt->root.offset = (bfd_vma) -1;
16934 }
16935
16936 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
16937 {
16938 asection *psrel;
16939
16940 psrel = elf_section_data (p->sec)->sreloc;
16941 if (local_iplt->arm.noncall_refcount == 0)
16942 elf32_arm_allocate_irelocs (info, psrel, p->count);
16943 else
16944 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
16945 }
16946 }
5e681ec4
PB		 16947 if (*local_got > 0)
16948 {
34e77a92
RS		 16949 Elf_Internal_Sym *isym;
16950
eea6121a 16951 *local_got = s->size;
ba93b8ac
DJ		 16952 if (*local_tls_type & GOT_TLS_GD)
16953 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16954 s->size += 8;
0855e32b
NS		 16955 if (*local_tls_type & GOT_TLS_GDESC)
16956 {
16957 *local_tlsdesc_gotent = htab->root.sgotplt->size
16958 - elf32_arm_compute_jump_table_size (htab);
16959 htab->root.sgotplt->size += 8;
16960 *local_got = (bfd_vma) -2;
34e77a92 16961 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16962 reloc in the middle of .got.plt. */
99059e56 16963 htab->num_tls_desc++;
0855e32b 16964 }
ba93b8ac
DJ		 16965 if (*local_tls_type & GOT_TLS_IE)
16966 s->size += 4;
ba93b8ac 16967
0855e32b
NS		 16968 if (*local_tls_type & GOT_NORMAL)
16969 {
16970 /* If the symbol is both GD and GDESC, *local_got
16971 may have been overwritten. */
16972 *local_got = s->size;
16973 s->size += 4;
16974 }
16975
34e77a92
RS		 16976 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
16977 if (isym == NULL)
16978 return FALSE;
16979
16980 /* If all references to an STT_GNU_IFUNC PLT are calls,
16981 then all non-call references, including this GOT entry,
16982 resolve directly to the run-time target. */
16983 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
16984 && (local_iplt == NULL
16985 || local_iplt->arm.noncall_refcount == 0))
16986 elf32_arm_allocate_irelocs (info, srel, 1);
e8b09b87 16987 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
0855e32b 16988 {
e8b09b87 16989 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
3064e1ff 16990 elf32_arm_allocate_dynrelocs (info, srel, 1);
e8b09b87
CL		 16991 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
16992 htab->srofixup->size += 4;
99059e56 16993
e8b09b87
CL		 16994 if ((bfd_link_pic (info) || htab->fdpic_p)
16995 && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 16996 {
16997 elf32_arm_allocate_dynrelocs (info,
16998 htab->root.srelplt, 1);
16999 htab->tls_trampoline = -1;
17000 }
0855e32b 17001 }
5e681ec4
PB		 17002 }
17003 else
17004 *local_got = (bfd_vma) -1;
17005 }
252b5132
RH		 17006 }
17007
ba93b8ac
DJ		 17008 if (htab->tls_ldm_got.refcount > 0)
17009 {
17010 /* Allocate two GOT entries and one dynamic relocation (if necessary)
5c5a4843 17011 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
362d30a1
RS		 17012 htab->tls_ldm_got.offset = htab->root.sgot->size;
17013 htab->root.sgot->size += 8;
0e1862bb 17014 if (bfd_link_pic (info))
47beaa6a 17015 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 17016 }
17017 else
17018 htab->tls_ldm_got.offset = -1;
17019
e8b09b87
CL		 17020 /* At the very end of the .rofixup section is a pointer to the GOT,
17021 reserve space for it. */
17022 if (htab->fdpic_p && htab->srofixup != NULL)
17023 htab->srofixup->size += 4;
17024
5e681ec4
PB		 17025 /* Allocate global sym .plt and .got entries, and space for global
17026 sym dynamic relocs. */
47beaa6a 17027 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 17028
d504ffc8 17029 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 17030 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 17031 {
0ffa91dd 17032 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 17033 continue;
17034
c7b8f16e
JB		 17035 /* Initialise mapping tables for code/data. */
17036 bfd_elf32_arm_init_maps (ibfd);
906e58ca 17037
c7b8f16e 17038 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 17039 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
17040 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 17041 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 17042 }
d504ffc8 17043
3e6b1042
DJ		 17044 /* Allocate space for the glue sections now that we've sized them. */
17045 bfd_elf32_arm_allocate_interworking_sections (info);
17046
0855e32b
NS		 17047 /* For every jump slot reserved in the sgotplt, reloc_count is
17048 incremented. However, when we reserve space for TLS descriptors,
17049 it's not incremented, so in order to compute the space reserved
17050 for them, it suffices to multiply the reloc count by the jump
17051 slot size. */
17052 if (htab->root.srelplt)
17053 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
17054
17055 if (htab->tls_trampoline)
17056 {
17057 if (htab->root.splt->size == 0)
17058 htab->root.splt->size += htab->plt_header_size;
b38cadfb 17059
0855e32b
NS		 17060 htab->tls_trampoline = htab->root.splt->size;
17061 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 17062
0855e32b 17063 /* If we're not using lazy TLS relocations, don't generate the
99059e56 17064 PLT and GOT entries they require. */
0855e32b
NS		 17065 if (!(info->flags & DF_BIND_NOW))
17066 {
17067 htab->dt_tlsdesc_got = htab->root.sgot->size;
17068 htab->root.sgot->size += 4;
17069
17070 htab->dt_tlsdesc_plt = htab->root.splt->size;
17071 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
17072 }
17073 }
17074
252b5132
RH		 17075 /* The check_relocs and adjust_dynamic_symbol entry points have
17076 determined the sizes of the various dynamic sections. Allocate
17077 memory for them. */
b34976b6
AM		 17078 plt = FALSE;
17079 relocs = FALSE;
252b5132
RH		 17080 for (s = dynobj->sections; s != NULL; s = s->next)
17081 {
17082 const char * name;
252b5132
RH		 17083
17084 if ((s->flags & SEC_LINKER_CREATED) == 0)
17085 continue;
17086
17087 /* It's OK to base decisions on the section name, because none
17088 of the dynobj section names depend upon the input files. */
fd361982 17089 name = bfd_section_name (s);
252b5132 17090
34e77a92 17091 if (s == htab->root.splt)
252b5132 17092 {
c456f082
AM		 17093 /* Remember whether there is a PLT. */
17094 plt = s->size != 0;
252b5132 17095 }
0112cd26 17096 else if (CONST_STRNEQ (name, ".rel"))
252b5132 17097 {
c456f082 17098 if (s->size != 0)
252b5132 17099 {
252b5132 17100 /* Remember whether there are any reloc sections other
00a97672 17101 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 17102 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 17103 relocs = TRUE;
252b5132
RH		 17104
17105 /* We use the reloc_count field as a counter if we need
17106 to copy relocs into the output file. */
17107 s->reloc_count = 0;
17108 }
17109 }
34e77a92
RS		 17110 else if (s != htab->root.sgot
17111 && s != htab->root.sgotplt
17112 && s != htab->root.iplt
17113 && s != htab->root.igotplt
5474d94f 17114 && s != htab->root.sdynbss
e8b09b87
CL		 17115 && s != htab->root.sdynrelro
17116 && s != htab->srofixup)
252b5132
RH		 17117 {
17118 /* It's not one of our sections, so don't allocate space. */
17119 continue;
17120 }
17121
c456f082 17122 if (s->size == 0)
252b5132 17123 {
c456f082 17124 /* If we don't need this section, strip it from the
00a97672
RS		 17125 output file. This is mostly to handle .rel(a).bss and
17126 .rel(a).plt. We must create both sections in
c456f082
AM		 17127 create_dynamic_sections, because they must be created
17128 before the linker maps input sections to output
17129 sections. The linker does that before
17130 adjust_dynamic_symbol is called, and it is that
17131 function which decides whether anything needs to go
17132 into these sections. */
8423293d 17133 s->flags |= SEC_EXCLUDE;
252b5132
RH		 17134 continue;
17135 }
17136
c456f082
AM		 17137 if ((s->flags & SEC_HAS_CONTENTS) == 0)
17138 continue;
17139
252b5132 17140 /* Allocate memory for the section contents. */
21d799b5 17141 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 17142 if (s->contents == NULL)
b34976b6 17143 return FALSE;
252b5132
RH		 17144 }
17145
17146 if (elf_hash_table (info)->dynamic_sections_created)
17147 {
17148 /* Add some entries to the .dynamic section. We fill in the
17149 values later, in elf32_arm_finish_dynamic_sections, but we
17150 must add the entries now so that we get the correct size for
17151 the .dynamic section. The DT_DEBUG entry is filled in by the
17152 dynamic linker and used by the debugger. */
dc810e39 17153#define add_dynamic_entry(TAG, VAL) \
5a580b3a 17154 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 17155
0e1862bb 17156 if (bfd_link_executable (info))
252b5132 17157 {
dc810e39 17158 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 17159 return FALSE;
252b5132
RH		 17160 }
17161
17162 if (plt)
17163 {
dc810e39
AM		 17164 if ( !add_dynamic_entry (DT_PLTGOT, 0)
17165 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 17166 || !add_dynamic_entry (DT_PLTREL,
17167 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 17168 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 17169 return FALSE;
0855e32b 17170
5025eb7c
AO		 17171 if (htab->dt_tlsdesc_plt
17172 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
17173 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 17174 return FALSE;
252b5132
RH		 17175 }
17176
17177 if (relocs)
17178 {
00a97672
RS		 17179 if (htab->use_rel)
17180 {
17181 if (!add_dynamic_entry (DT_REL, 0)
17182 || !add_dynamic_entry (DT_RELSZ, 0)
17183 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
17184 return FALSE;
17185 }
17186 else
17187 {
17188 if (!add_dynamic_entry (DT_RELA, 0)
17189 || !add_dynamic_entry (DT_RELASZ, 0)
17190 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
17191 return FALSE;
17192 }
252b5132
RH		 17193 }
17194
08d1f311
DJ		 17195 /* If any dynamic relocs apply to a read-only section,
17196 then we need a DT_TEXTREL entry. */
17197 if ((info->flags & DF_TEXTREL) == 0)
63c1f59d 17198 elf_link_hash_traverse (&htab->root, maybe_set_textrel, info);
08d1f311 17199
99e4ae17 17200 if ((info->flags & DF_TEXTREL) != 0)
252b5132 17201 {
dc810e39 17202 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 17203 return FALSE;
252b5132 17204 }
7a2b07ff
NS		 17205 if (htab->vxworks_p
17206 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
17207 return FALSE;
252b5132 17208 }
8532796c 17209#undef add_dynamic_entry
252b5132 17210
b34976b6 17211 return TRUE;
252b5132
RH		 17212}
17213
0855e32b
NS		 17214/* Size sections even though they're not dynamic. We use it to setup
17215 _TLS_MODULE_BASE_, if needed. */
17216
17217static bfd_boolean
17218elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 17219 struct bfd_link_info *info)
0855e32b
NS		 17220{
17221 asection *tls_sec;
cb10292c
CL		 17222 struct elf32_arm_link_hash_table *htab;
17223
17224 htab = elf32_arm_hash_table (info);
0855e32b 17225
0e1862bb 17226 if (bfd_link_relocatable (info))
0855e32b
NS		 17227 return TRUE;
17228
17229 tls_sec = elf_hash_table (info)->tls_sec;
17230
17231 if (tls_sec)
17232 {
17233 struct elf_link_hash_entry *tlsbase;
17234
17235 tlsbase = elf_link_hash_lookup
17236 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
17237
17238 if (tlsbase)
99059e56
RM		 17239 {
17240 struct bfd_link_hash_entry *bh = NULL;
0855e32b 17241 const struct elf_backend_data *bed
99059e56 17242 = get_elf_backend_data (output_bfd);
0855e32b 17243
99059e56 17244 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 17245 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
17246 tls_sec, 0, NULL, FALSE,
17247 bed->collect, &bh)))
17248 return FALSE;
b38cadfb 17249
99059e56
RM		 17250 tlsbase->type = STT_TLS;
17251 tlsbase = (struct elf_link_hash_entry *)bh;
17252 tlsbase->def_regular = 1;
17253 tlsbase->other = STV_HIDDEN;
17254 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 17255 }
17256 }
cb10292c
CL		 17257
17258 if (htab->fdpic_p && !bfd_link_relocatable (info)
17259 && !bfd_elf_stack_segment_size (output_bfd, info,
17260 "__stacksize", DEFAULT_STACK_SIZE))
17261 return FALSE;
17262
0855e32b
NS		 17263 return TRUE;
17264}
17265
252b5132
RH		 17266/* Finish up dynamic symbol handling. We set the contents of various
17267 dynamic sections here. */
17268
b34976b6 17269static bfd_boolean
906e58ca
NC		 17270elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17271 struct bfd_link_info * info,
17272 struct elf_link_hash_entry * h,
17273 Elf_Internal_Sym * sym)
252b5132 17274{
e5a52504 17275 struct elf32_arm_link_hash_table *htab;
b7693d02 17276 struct elf32_arm_link_hash_entry *eh;
252b5132 17277
e5a52504 17278 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17279 if (htab == NULL)
17280 return FALSE;
17281
b7693d02 17282 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 17283
17284 if (h->plt.offset != (bfd_vma) -1)
17285 {
34e77a92 17286 if (!eh->is_iplt)
e5a52504 17287 {
34e77a92 17288 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 17289 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17290 h->dynindx, 0))
17291 return FALSE;
e5a52504 17292 }
57e8b36a 17293
f5385ebf 17294 if (!h->def_regular)
252b5132
RH		 17295 {
17296 /* Mark the symbol as undefined, rather than as defined in
3a635617 17297 the .plt section. */
252b5132 17298 sym->st_shndx = SHN_UNDEF;
3a635617 17299 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 17300 Otherwise, the PLT entry would provide a definition for
17301 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 17302 and so the symbol would never be NULL. Leave the value if
17303 there were any relocations where pointer equality matters
17304 (this is a clue for the dynamic linker, to make function
17305 pointer comparisons work between an application and shared
17306 library). */
97323ad1 17307 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 17308 sym->st_value = 0;
252b5132 17309 }
34e77a92
RS		 17310 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17311 {
17312 /* At least one non-call relocation references this .iplt entry,
17313 so the .iplt entry is the function's canonical address. */
17314 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 17315 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 17316 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17317 (output_bfd, htab->root.iplt->output_section));
17318 sym->st_value = (h->plt.offset
17319 + htab->root.iplt->output_section->vma
17320 + htab->root.iplt->output_offset);
17321 }
252b5132
RH		 17322 }
17323
f5385ebf 17324 if (h->needs_copy)
252b5132
RH		 17325 {
17326 asection * s;
947216bf 17327 Elf_Internal_Rela rel;
252b5132
RH		 17328
17329 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 17330 BFD_ASSERT (h->dynindx != -1
17331 && (h->root.type == bfd_link_hash_defined
17332 || h->root.type == bfd_link_hash_defweak));
17333
00a97672 17334 rel.r_addend = 0;
252b5132
RH		 17335 rel.r_offset = (h->root.u.def.value
17336 + h->root.u.def.section->output_section->vma
17337 + h->root.u.def.section->output_offset);
17338 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 17339 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 17340 s = htab->root.sreldynrelro;
17341 else
17342 s = htab->root.srelbss;
47beaa6a 17343 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 17344 }
17345
00a97672 17346 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
fac7bd64
CL		 17347 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17348 it is relative to the ".got" section. */
9637f6ef 17349 if (h == htab->root.hdynamic
fac7bd64 17350 || (!htab->fdpic_p && !htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 17351 sym->st_shndx = SHN_ABS;
17352
b34976b6 17353 return TRUE;
252b5132
RH		 17354}
17355
0855e32b
NS		 17356static void
17357arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17358 void *contents,
17359 const unsigned long *template, unsigned count)
17360{
17361 unsigned ix;
b38cadfb 17362
0855e32b
NS		 17363 for (ix = 0; ix != count; ix++)
17364 {
17365 unsigned long insn = template[ix];
17366
17367 /* Emit mov pc,rx if bx is not permitted. */
17368 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17369 insn = (insn & 0xf000000f) | 0x01a0f000;
17370 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17371 }
17372}
17373
99059e56
RM		 17374/* Install the special first PLT entry for elf32-arm-nacl. Unlike
17375 other variants, NaCl needs this entry in a static executable's
17376 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17377 zero. For .iplt really only the last bundle is useful, and .iplt
17378 could have a shorter first entry, with each individual PLT entry's
17379 relative branch calculated differently so it targets the last
17380 bundle instead of the instruction before it (labelled .Lplt_tail
17381 above). But it's simpler to keep the size and layout of PLT0
17382 consistent with the dynamic case, at the cost of some dead code at
17383 the start of .iplt and the one dead store to the stack at the start
17384 of .Lplt_tail. */
17385static void
17386arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17387 asection *plt, bfd_vma got_displacement)
17388{
17389 unsigned int i;
17390
17391 put_arm_insn (htab, output_bfd,
17392 elf32_arm_nacl_plt0_entry[0]
17393 | arm_movw_immediate (got_displacement),
17394 plt->contents + 0);
17395 put_arm_insn (htab, output_bfd,
17396 elf32_arm_nacl_plt0_entry[1]
17397 | arm_movt_immediate (got_displacement),
17398 plt->contents + 4);
17399
17400 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17401 put_arm_insn (htab, output_bfd,
17402 elf32_arm_nacl_plt0_entry[i],
17403 plt->contents + (i * 4));
17404}
17405
252b5132
RH		 17406/* Finish up the dynamic sections. */
17407
b34976b6 17408static bfd_boolean
57e8b36a 17409elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 17410{
17411 bfd * dynobj;
17412 asection * sgot;
17413 asection * sdyn;
4dfe6ac6
NC		 17414 struct elf32_arm_link_hash_table *htab;
17415
17416 htab = elf32_arm_hash_table (info);
17417 if (htab == NULL)
17418 return FALSE;
252b5132
RH		 17419
17420 dynobj = elf_hash_table (info)->dynobj;
17421
362d30a1 17422 sgot = htab->root.sgotplt;
894891db
NC		 17423 /* A broken linker script might have discarded the dynamic sections.
17424 Catch this here so that we do not seg-fault later on. */
17425 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17426 return FALSE;
3d4d4302 17427 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 17428
17429 if (elf_hash_table (info)->dynamic_sections_created)
17430 {
17431 asection *splt;
17432 Elf32_External_Dyn *dyncon, *dynconend;
17433
362d30a1 17434 splt = htab->root.splt;
24a1ba0f 17435 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 17436 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 17437
17438 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 17439 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 17440
252b5132
RH		 17441 for (; dyncon < dynconend; dyncon++)
17442 {
17443 Elf_Internal_Dyn dyn;
17444 const char * name;
17445 asection * s;
17446
17447 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17448
17449 switch (dyn.d_tag)
17450 {
229fcec5
MM		 17451 unsigned int type;
17452
252b5132 17453 default:
7a2b07ff
NS		 17454 if (htab->vxworks_p
17455 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17456 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 17457 break;
17458
229fcec5
MM		 17459 case DT_HASH:
17460 name = ".hash";
17461 goto get_vma_if_bpabi;
17462 case DT_STRTAB:
17463 name = ".dynstr";
17464 goto get_vma_if_bpabi;
17465 case DT_SYMTAB:
17466 name = ".dynsym";
17467 goto get_vma_if_bpabi;
c0042f5d
MM		 17468 case DT_VERSYM:
17469 name = ".gnu.version";
17470 goto get_vma_if_bpabi;
17471 case DT_VERDEF:
17472 name = ".gnu.version_d";
17473 goto get_vma_if_bpabi;
17474 case DT_VERNEED:
17475 name = ".gnu.version_r";
17476 goto get_vma_if_bpabi;
17477
252b5132 17478 case DT_PLTGOT:
4ade44b7 17479 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 17480 goto get_vma;
17481 case DT_JMPREL:
00a97672 17482 name = RELOC_SECTION (htab, ".plt");
252b5132 17483 get_vma:
4ade44b7 17484 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 17485 if (s == NULL)
17486 {
4eca0228 17487 _bfd_error_handler
4ade44b7 17488 (_("could not find section %s"), name);
05456594
NC		 17489 bfd_set_error (bfd_error_invalid_operation);
17490 return FALSE;
17491 }
229fcec5 17492 if (!htab->symbian_p)
4ade44b7 17493 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 17494 else
17495 /* In the BPABI, tags in the PT_DYNAMIC section point
17496 at the file offset, not the memory address, for the
17497 convenience of the post linker. */
4ade44b7 17498 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 17499 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17500 break;
17501
229fcec5
MM		 17502 get_vma_if_bpabi:
17503 if (htab->symbian_p)
17504 goto get_vma;
17505 break;
17506
252b5132 17507 case DT_PLTRELSZ:
362d30a1 17508 s = htab->root.srelplt;
252b5132 17509 BFD_ASSERT (s != NULL);
eea6121a 17510 dyn.d_un.d_val = s->size;
252b5132
RH		 17511 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17512 break;
906e58ca 17513
252b5132 17514 case DT_RELSZ:
00a97672 17515 case DT_RELASZ:
229fcec5
MM		 17516 case DT_REL:
17517 case DT_RELA:
229fcec5
MM		 17518 /* In the BPABI, the DT_REL tag must point at the file
17519 offset, not the VMA, of the first relocation
17520 section. So, we use code similar to that in
17521 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 17522 relocation section, since relocation sections are
17523 never allocated under the BPABI. PLT relocs are also
17524 included. */
229fcec5
MM		 17525 if (htab->symbian_p)
17526 {
17527 unsigned int i;
17528 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
17529 ? SHT_REL : SHT_RELA);
17530 dyn.d_un.d_val = 0;
17531 for (i = 1; i < elf_numsections (output_bfd); i++)
17532 {
906e58ca 17533 Elf_Internal_Shdr *hdr
229fcec5
MM		 17534 = elf_elfsections (output_bfd)[i];
17535 if (hdr->sh_type == type)
17536 {
906e58ca 17537 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 17538 || dyn.d_tag == DT_RELASZ)
17539 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 17540 else if ((ufile_ptr) hdr->sh_offset
17541 <= dyn.d_un.d_val - 1)
229fcec5
MM		 17542 dyn.d_un.d_val = hdr->sh_offset;
17543 }
17544 }
17545 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17546 }
252b5132 17547 break;
88f7bcd5 17548
0855e32b 17549 case DT_TLSDESC_PLT:
99059e56 17550 s = htab->root.splt;
0855e32b
NS		 17551 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
17552 + htab->dt_tlsdesc_plt);
17553 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17554 break;
17555
17556 case DT_TLSDESC_GOT:
99059e56 17557 s = htab->root.sgot;
0855e32b 17558 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 17559 + htab->dt_tlsdesc_got);
0855e32b
NS		 17560 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17561 break;
17562
88f7bcd5
NC		 17563 /* Set the bottom bit of DT_INIT/FINI if the
17564 corresponding function is Thumb. */
17565 case DT_INIT:
17566 name = info->init_function;
17567 goto get_sym;
17568 case DT_FINI:
17569 name = info->fini_function;
17570 get_sym:
17571 /* If it wasn't set by elf_bfd_final_link
4cc11e76 17572 then there is nothing to adjust. */
88f7bcd5
NC		 17573 if (dyn.d_un.d_val != 0)
17574 {
17575 struct elf_link_hash_entry * eh;
17576
17577 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 17578 FALSE, FALSE, TRUE);
39d911fc
TP		 17579 if (eh != NULL
17580 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17581 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 17582 {
17583 dyn.d_un.d_val |= 1;
b34976b6 17584 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 17585 }
17586 }
17587 break;
252b5132
RH		 17588 }
17589 }
17590
24a1ba0f 17591 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 17592 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 17593 {
00a97672
RS		 17594 const bfd_vma *plt0_entry;
17595 bfd_vma got_address, plt_address, got_displacement;
17596
17597 /* Calculate the addresses of the GOT and PLT. */
17598 got_address = sgot->output_section->vma + sgot->output_offset;
17599 plt_address = splt->output_section->vma + splt->output_offset;
17600
17601 if (htab->vxworks_p)
17602 {
17603 /* The VxWorks GOT is relocated by the dynamic linker.
17604 Therefore, we must emit relocations rather than simply
17605 computing the values now. */
17606 Elf_Internal_Rela rel;
17607
17608 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 17609 put_arm_insn (htab, output_bfd, plt0_entry[0],
17610 splt->contents + 0);
17611 put_arm_insn (htab, output_bfd, plt0_entry[1],
17612 splt->contents + 4);
17613 put_arm_insn (htab, output_bfd, plt0_entry[2],
17614 splt->contents + 8);
00a97672
RS		 17615 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17616
8029a119 17617 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 17618 rel.r_offset = plt_address + 12;
17619 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17620 rel.r_addend = 0;
17621 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17622 htab->srelplt2->contents);
17623 }
b38cadfb 17624 else if (htab->nacl_p)
99059e56
RM		 17625 arm_nacl_put_plt0 (htab, output_bfd, splt,
17626 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 17627 else if (using_thumb_only (htab))
17628 {
17629 got_displacement = got_address - (plt_address + 12);
17630
17631 plt0_entry = elf32_thumb2_plt0_entry;
17632 put_arm_insn (htab, output_bfd, plt0_entry[0],
17633 splt->contents + 0);
17634 put_arm_insn (htab, output_bfd, plt0_entry[1],
17635 splt->contents + 4);
17636 put_arm_insn (htab, output_bfd, plt0_entry[2],
17637 splt->contents + 8);
17638
17639 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17640 }
00a97672
RS		 17641 else
17642 {
17643 got_displacement = got_address - (plt_address + 16);
17644
17645 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 17646 put_arm_insn (htab, output_bfd, plt0_entry[0],
17647 splt->contents + 0);
17648 put_arm_insn (htab, output_bfd, plt0_entry[1],
17649 splt->contents + 4);
17650 put_arm_insn (htab, output_bfd, plt0_entry[2],
17651 splt->contents + 8);
17652 put_arm_insn (htab, output_bfd, plt0_entry[3],
17653 splt->contents + 12);
5e681ec4 17654
5e681ec4 17655#ifdef FOUR_WORD_PLT
00a97672
RS		 17656 /* The displacement value goes in the otherwise-unused
17657 last word of the second entry. */
17658 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 17659#else
00a97672 17660 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 17661#endif
00a97672 17662 }
f7a74f8c 17663 }
252b5132
RH		 17664
17665 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17666 really seem like the right value. */
74541ad4
AM		 17667 if (splt->output_section->owner == output_bfd)
17668 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 17669
0855e32b
NS		 17670 if (htab->dt_tlsdesc_plt)
17671 {
17672 bfd_vma got_address
17673 = sgot->output_section->vma + sgot->output_offset;
17674 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17675 + htab->root.sgot->output_offset);
17676 bfd_vma plt_address
17677 = splt->output_section->vma + splt->output_offset;
17678
b38cadfb 17679 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17680 splt->contents + htab->dt_tlsdesc_plt,
17681 dl_tlsdesc_lazy_trampoline, 6);
17682
17683 bfd_put_32 (output_bfd,
17684 gotplt_address + htab->dt_tlsdesc_got
17685 - (plt_address + htab->dt_tlsdesc_plt)
17686 - dl_tlsdesc_lazy_trampoline[6],
17687 splt->contents + htab->dt_tlsdesc_plt + 24);
17688 bfd_put_32 (output_bfd,
17689 got_address - (plt_address + htab->dt_tlsdesc_plt)
17690 - dl_tlsdesc_lazy_trampoline[7],
17691 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
17692 }
17693
17694 if (htab->tls_trampoline)
17695 {
b38cadfb 17696 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17697 splt->contents + htab->tls_trampoline,
17698 tls_trampoline, 3);
17699#ifdef FOUR_WORD_PLT
17700 bfd_put_32 (output_bfd, 0x00000000,
17701 splt->contents + htab->tls_trampoline + 12);
b38cadfb 17702#endif
0855e32b
NS		 17703 }
17704
0e1862bb
L		 17705 if (htab->vxworks_p
17706 && !bfd_link_pic (info)
17707 && htab->root.splt->size > 0)
00a97672
RS		 17708 {
17709 /* Correct the .rel(a).plt.unloaded relocations. They will have
17710 incorrect symbol indexes. */
17711 int num_plts;
eed62c48 17712 unsigned char *p;
00a97672 17713
362d30a1 17714 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 17715 / htab->plt_entry_size);
17716 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17717
17718 for (; num_plts; num_plts--)
17719 {
17720 Elf_Internal_Rela rel;
17721
17722 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17723 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17724 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17725 p += RELOC_SIZE (htab);
17726
17727 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17728 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17729 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17730 p += RELOC_SIZE (htab);
17731 }
17732 }
252b5132
RH		 17733 }
17734
99059e56
RM		 17735 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
17736 /* NaCl uses a special first entry in .iplt too. */
17737 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17738
252b5132 17739 /* Fill in the first three entries in the global offset table. */
229fcec5 17740 if (sgot)
252b5132 17741 {
229fcec5
MM		 17742 if (sgot->size > 0)
17743 {
17744 if (sdyn == NULL)
17745 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17746 else
17747 bfd_put_32 (output_bfd,
17748 sdyn->output_section->vma + sdyn->output_offset,
17749 sgot->contents);
17750 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17751 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17752 }
252b5132 17753
229fcec5
MM		 17754 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17755 }
252b5132 17756
e8b09b87
CL		 17757 /* At the very end of the .rofixup section is a pointer to the GOT. */
17758 if (htab->fdpic_p && htab->srofixup != NULL)
17759 {
17760 struct elf_link_hash_entry *hgot = htab->root.hgot;
17761
17762 bfd_vma got_value = hgot->root.u.def.value
17763 + hgot->root.u.def.section->output_section->vma
17764 + hgot->root.u.def.section->output_offset;
17765
17766 arm_elf_add_rofixup(output_bfd, htab->srofixup, got_value);
17767
17768 /* Make sure we allocated and generated the same number of fixups. */
17769 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17770 }
17771
b34976b6 17772 return TRUE;
252b5132
RH		 17773}
17774
ed7e9d0b
AM		 17775static bfd_boolean
17776elf32_arm_init_file_header (bfd *abfd, struct bfd_link_info *link_info)
ba96a88f 17777{
9b485d32 17778 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 17779 struct elf32_arm_link_hash_table *globals;
ac4c9b04 17780 struct elf_segment_map *m;
ba96a88f 17781
ed7e9d0b
AM		 17782 if (!_bfd_elf_init_file_header (abfd, link_info))
17783 return FALSE;
17784
ba96a88f
NC		 17785 i_ehdrp = elf_elfheader (abfd);
17786
94a3258f
PB		 17787 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17788 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
ba96a88f 17789 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 17790
93204d3a
PB		 17791 if (link_info)
17792 {
17793 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 17794 if (globals != NULL && globals->byteswap_code)
93204d3a 17795 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 17796
17797 if (globals->fdpic_p)
17798 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 17799 }
3bfcb652
NC		 17800
17801 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17802 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17803 {
17804 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 17805 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 17806 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17807 else
17808 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17809 }
ac4c9b04
MG		 17810
17811 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 17812 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 17813 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17814 {
17815 unsigned int j;
17816
17817 if (m->count == 0)
17818 continue;
17819 for (j = 0; j < m->count; j++)
17820 {
f0728ee3 17821 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 17822 break;
17823 }
17824 if (j == m->count)
17825 {
17826 m->p_flags = PF_X;
17827 m->p_flags_valid = 1;
17828 }
17829 }
ed7e9d0b 17830 return TRUE;
ba96a88f
NC		 17831}
17832
99e4ae17 17833static enum elf_reloc_type_class
7e612e98
AM		 17834elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17835 const asection *rel_sec ATTRIBUTE_UNUSED,
17836 const Elf_Internal_Rela *rela)
99e4ae17 17837{
f51e552e 17838 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 17839 {
17840 case R_ARM_RELATIVE:
17841 return reloc_class_relative;
17842 case R_ARM_JUMP_SLOT:
17843 return reloc_class_plt;
17844 case R_ARM_COPY:
17845 return reloc_class_copy;
109575d7
JW		 17846 case R_ARM_IRELATIVE:
17847 return reloc_class_ifunc;
99e4ae17
AJ		 17848 default:
17849 return reloc_class_normal;
17850 }
17851}
17852
e489d0ae 17853static void
cc364be6 17854arm_final_write_processing (bfd *abfd)
e16bb312 17855{
5a6c6817 17856 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 17857}
17858
cc364be6
AM		 17859static bfd_boolean
17860elf32_arm_final_write_processing (bfd *abfd)
06f44071 17861{
cc364be6
AM		 17862 arm_final_write_processing (abfd);
17863 return _bfd_elf_final_write_processing (abfd);
06f44071
AM		 17864}
17865
40a18ebd
NC		 17866/* Return TRUE if this is an unwinding table entry. */
17867
17868static bfd_boolean
17869is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17870{
0112cd26
NC		 17871 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
17872 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 17873}
17874
17875
17876/* Set the type and flags for an ARM section. We do this by
17877 the section name, which is a hack, but ought to work. */
17878
17879static bfd_boolean
17880elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17881{
17882 const char * name;
17883
fd361982 17884 name = bfd_section_name (sec);
40a18ebd
NC		 17885
17886 if (is_arm_elf_unwind_section_name (abfd, name))
17887 {
17888 hdr->sh_type = SHT_ARM_EXIDX;
17889 hdr->sh_flags |= SHF_LINK_ORDER;
17890 }
ac4c9b04 17891
f0728ee3
AV		 17892 if (sec->flags & SEC_ELF_PURECODE)
17893 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 17894
40a18ebd
NC		 17895 return TRUE;
17896}
17897
6dc132d9
L		 17898/* Handle an ARM specific section when reading an object file. This is
17899 called when bfd_section_from_shdr finds a section with an unknown
17900 type. */
40a18ebd
NC		 17901
17902static bfd_boolean
17903elf32_arm_section_from_shdr (bfd *abfd,
17904 Elf_Internal_Shdr * hdr,
6dc132d9
L		 17905 const char *name,
17906 int shindex)
40a18ebd
NC		 17907{
17908 /* There ought to be a place to keep ELF backend specific flags, but
17909 at the moment there isn't one. We just keep track of the
17910 sections by their name, instead. Fortunately, the ABI gives
17911 names for all the ARM specific sections, so we will probably get
17912 away with this. */
17913 switch (hdr->sh_type)
17914 {
17915 case SHT_ARM_EXIDX:
0951f019
RE		 17916 case SHT_ARM_PREEMPTMAP:
17917 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 17918 break;
17919
17920 default:
17921 return FALSE;
17922 }
17923
6dc132d9 17924 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 17925 return FALSE;
17926
17927 return TRUE;
17928}
e489d0ae 17929
44444f50
NC		 17930static _arm_elf_section_data *
17931get_arm_elf_section_data (asection * sec)
17932{
47b2e99c
JZ		 17933 if (sec && sec->owner && is_arm_elf (sec->owner))
17934 return elf32_arm_section_data (sec);
44444f50
NC		 17935 else
17936 return NULL;
8e3de13a
NC		 17937}
17938
4e617b1e
PB		 17939typedef struct
17940{
57402f1e 17941 void *flaginfo;
4e617b1e 17942 struct bfd_link_info *info;
91a5743d
PB		 17943 asection *sec;
17944 int sec_shndx;
6e0b88f1
AM		 17945 int (*func) (void *, const char *, Elf_Internal_Sym *,
17946 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 17947} output_arch_syminfo;
17948
17949enum map_symbol_type
17950{
17951 ARM_MAP_ARM,
17952 ARM_MAP_THUMB,
17953 ARM_MAP_DATA
17954};
17955
17956
7413f23f 17957/* Output a single mapping symbol. */
4e617b1e
PB		 17958
17959static bfd_boolean
7413f23f
DJ		 17960elf32_arm_output_map_sym (output_arch_syminfo *osi,
17961 enum map_symbol_type type,
17962 bfd_vma offset)
4e617b1e
PB		 17963{
17964 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 17965 Elf_Internal_Sym sym;
17966
91a5743d
PB		 17967 sym.st_value = osi->sec->output_section->vma
17968 + osi->sec->output_offset
17969 + offset;
4e617b1e
PB		 17970 sym.st_size = 0;
17971 sym.st_other = 0;
17972 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 17973 sym.st_shndx = osi->sec_shndx;
35fc36a8 17974 sym.st_target_internal = 0;
fe33d2fa 17975 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 17976 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 17977}
17978
34e77a92
RS		 17979/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17980 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 17981
17982static bfd_boolean
34e77a92
RS		 17983elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
17984 bfd_boolean is_iplt_entry_p,
17985 union gotplt_union *root_plt,
17986 struct arm_plt_info *arm_plt)
4e617b1e 17987{
4e617b1e 17988 struct elf32_arm_link_hash_table *htab;
34e77a92 17989 bfd_vma addr, plt_header_size;
4e617b1e 17990
34e77a92 17991 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 17992 return TRUE;
17993
4dfe6ac6
NC		 17994 htab = elf32_arm_hash_table (osi->info);
17995 if (htab == NULL)
17996 return FALSE;
17997
34e77a92
RS		 17998 if (is_iplt_entry_p)
17999 {
18000 osi->sec = htab->root.iplt;
18001 plt_header_size = 0;
18002 }
18003 else
18004 {
18005 osi->sec = htab->root.splt;
18006 plt_header_size = htab->plt_header_size;
18007 }
18008 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
18009 (osi->info->output_bfd, osi->sec->output_section));
18010
18011 addr = root_plt->offset & -2;
4e617b1e
PB		 18012 if (htab->symbian_p)
18013 {
7413f23f 18014 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18015 return FALSE;
7413f23f 18016 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 18017 return FALSE;
18018 }
18019 else if (htab->vxworks_p)
18020 {
7413f23f 18021 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18022 return FALSE;
7413f23f 18023 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 18024 return FALSE;
7413f23f 18025 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 18026 return FALSE;
7413f23f 18027 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 18028 return FALSE;
18029 }
b38cadfb
NC		 18030 else if (htab->nacl_p)
18031 {
18032 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
18033 return FALSE;
18034 }
7801f98f
CL		 18035 else if (htab->fdpic_p)
18036 {
59029f57
CL		 18037 enum map_symbol_type type = using_thumb_only(htab)
18038 ? ARM_MAP_THUMB
18039 : ARM_MAP_ARM;
18040
7801f98f 18041 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
4b24dd1a
AM		 18042 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
18043 return FALSE;
59029f57 18044 if (!elf32_arm_output_map_sym (osi, type, addr))
4b24dd1a 18045 return FALSE;
7801f98f 18046 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
4b24dd1a 18047 return FALSE;
7801f98f 18048 if (htab->plt_entry_size == 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry))
4b24dd1a
AM		 18049 if (!elf32_arm_output_map_sym (osi, type, addr + 24))
18050 return FALSE;
7801f98f 18051 }
eed94f8f
NC		 18052 else if (using_thumb_only (htab))
18053 {
18054 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
18055 return FALSE;
6a631e86 18056 }
4e617b1e
PB		 18057 else
18058 {
34e77a92 18059 bfd_boolean thumb_stub_p;
bd97cb95 18060
34e77a92
RS		 18061 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
18062 if (thumb_stub_p)
4e617b1e 18063 {
7413f23f 18064 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 18065 return FALSE;
18066 }
18067#ifdef FOUR_WORD_PLT
7413f23f 18068 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18069 return FALSE;
7413f23f 18070 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 18071 return FALSE;
18072#else
906e58ca 18073 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 18074 so only need to output a mapping symbol for the first PLT entry and
18075 entries with thumb thunks. */
34e77a92 18076 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 18077 {
7413f23f 18078 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 18079 return FALSE;
18080 }
18081#endif
18082 }
18083
18084 return TRUE;
18085}
18086
34e77a92
RS		 18087/* Output mapping symbols for PLT entries associated with H. */
18088
18089static bfd_boolean
18090elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
18091{
18092 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
18093 struct elf32_arm_link_hash_entry *eh;
18094
18095 if (h->root.type == bfd_link_hash_indirect)
18096 return TRUE;
18097
18098 if (h->root.type == bfd_link_hash_warning)
18099 /* When warning symbols are created, they **replace** the "real"
18100 entry in the hash table, thus we never get to see the real
18101 symbol in a hash traversal. So look at it now. */
18102 h = (struct elf_link_hash_entry *) h->root.u.i.link;
18103
18104 eh = (struct elf32_arm_link_hash_entry *) h;
18105 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
18106 &h->plt, &eh->plt);
18107}
18108
4f4faa4d
TP		 18109/* Bind a veneered symbol to its veneer identified by its hash entry
18110 STUB_ENTRY. The veneered location thus loose its symbol. */
18111
18112static void
18113arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
18114{
18115 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
18116
18117 BFD_ASSERT (hash);
18118 hash->root.root.u.def.section = stub_entry->stub_sec;
18119 hash->root.root.u.def.value = stub_entry->stub_offset;
18120 hash->root.size = stub_entry->stub_size;
18121}
18122
7413f23f
DJ		 18123/* Output a single local symbol for a generated stub. */
18124
18125static bfd_boolean
18126elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
18127 bfd_vma offset, bfd_vma size)
18128{
7413f23f
DJ		 18129 Elf_Internal_Sym sym;
18130
7413f23f
DJ		 18131 sym.st_value = osi->sec->output_section->vma
18132 + osi->sec->output_offset
18133 + offset;
18134 sym.st_size = size;
18135 sym.st_other = 0;
18136 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
18137 sym.st_shndx = osi->sec_shndx;
35fc36a8 18138 sym.st_target_internal = 0;
57402f1e 18139 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 18140}
4e617b1e 18141
da5938a2 18142static bfd_boolean
8029a119
NC		 18143arm_map_one_stub (struct bfd_hash_entry * gen_entry,
18144 void * in_arg)
da5938a2
NC		 18145{
18146 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 18147 asection *stub_sec;
18148 bfd_vma addr;
7413f23f 18149 char *stub_name;
9a008db3 18150 output_arch_syminfo *osi;
d3ce72d0 18151 const insn_sequence *template_sequence;
461a49ca
DJ		 18152 enum stub_insn_type prev_type;
18153 int size;
18154 int i;
18155 enum map_symbol_type sym_type;
da5938a2
NC		 18156
18157 /* Massage our args to the form they really have. */
18158 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 18159 osi = (output_arch_syminfo *) in_arg;
da5938a2 18160
da5938a2
NC		 18161 stub_sec = stub_entry->stub_sec;
18162
18163 /* Ensure this stub is attached to the current section being
7413f23f 18164 processed. */
da5938a2
NC		 18165 if (stub_sec != osi->sec)
18166 return TRUE;
18167
7413f23f 18168 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 18169 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 18170
18171 if (arm_stub_sym_claimed (stub_entry->stub_type))
18172 arm_stub_claim_sym (stub_entry);
18173 else
7413f23f 18174 {
4f4faa4d
TP		 18175 stub_name = stub_entry->output_name;
18176 switch (template_sequence[0].type)
18177 {
18178 case ARM_TYPE:
18179 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
18180 stub_entry->stub_size))
18181 return FALSE;
18182 break;
18183 case THUMB16_TYPE:
18184 case THUMB32_TYPE:
18185 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
18186 stub_entry->stub_size))
18187 return FALSE;
18188 break;
18189 default:
18190 BFD_FAIL ();
18191 return 0;
18192 }
7413f23f 18193 }
da5938a2 18194
461a49ca
DJ		 18195 prev_type = DATA_TYPE;
18196 size = 0;
18197 for (i = 0; i < stub_entry->stub_template_size; i++)
18198 {
d3ce72d0 18199 switch (template_sequence[i].type)
461a49ca
DJ		 18200 {
18201 case ARM_TYPE:
18202 sym_type = ARM_MAP_ARM;
18203 break;
18204
18205 case THUMB16_TYPE:
48229727 18206 case THUMB32_TYPE:
461a49ca
DJ		 18207 sym_type = ARM_MAP_THUMB;
18208 break;
18209
18210 case DATA_TYPE:
18211 sym_type = ARM_MAP_DATA;
18212 break;
18213
18214 default:
18215 BFD_FAIL ();
4e31c731 18216 return FALSE;
461a49ca
DJ		 18217 }
18218
d3ce72d0 18219 if (template_sequence[i].type != prev_type)
461a49ca 18220 {
d3ce72d0 18221 prev_type = template_sequence[i].type;
461a49ca
DJ		 18222 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
18223 return FALSE;
18224 }
18225
d3ce72d0 18226 switch (template_sequence[i].type)
461a49ca
DJ		 18227 {
18228 case ARM_TYPE:
48229727 18229 case THUMB32_TYPE:
461a49ca
DJ		 18230 size += 4;
18231 break;
18232
18233 case THUMB16_TYPE:
18234 size += 2;
18235 break;
18236
18237 case DATA_TYPE:
18238 size += 4;
18239 break;
18240
18241 default:
18242 BFD_FAIL ();
4e31c731 18243 return FALSE;
461a49ca
DJ		 18244 }
18245 }
18246
da5938a2
NC		 18247 return TRUE;
18248}
18249
33811162
DG		 18250/* Output mapping symbols for linker generated sections,
18251 and for those data-only sections that do not have a
18252 $d. */
4e617b1e
PB		 18253
18254static bfd_boolean
18255elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 18256 struct bfd_link_info *info,
57402f1e 18257 void *flaginfo,
6e0b88f1
AM		 18258 int (*func) (void *, const char *,
18259 Elf_Internal_Sym *,
18260 asection *,
18261 struct elf_link_hash_entry *))
4e617b1e
PB		 18262{
18263 output_arch_syminfo osi;
18264 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 18265 bfd_vma offset;
18266 bfd_size_type size;
33811162 18267 bfd *input_bfd;
4e617b1e
PB		 18268
18269 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 18270 if (htab == NULL)
18271 return FALSE;
18272
906e58ca 18273 check_use_blx (htab);
91a5743d 18274
57402f1e 18275 osi.flaginfo = flaginfo;
4e617b1e
PB		 18276 osi.info = info;
18277 osi.func = func;
906e58ca 18278
33811162
DG		 18279 /* Add a $d mapping symbol to data-only sections that
18280 don't have any mapping symbol. This may result in (harmless) redundant
18281 mapping symbols. */
18282 for (input_bfd = info->input_bfds;
18283 input_bfd != NULL;
c72f2fb2 18284 input_bfd = input_bfd->link.next)
33811162
DG		 18285 {
18286 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18287 for (osi.sec = input_bfd->sections;
18288 osi.sec != NULL;
18289 osi.sec = osi.sec->next)
18290 {
18291 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 18292 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18293 != 0)
33811162
DG		 18294 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18295 == SEC_HAS_CONTENTS
18296 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 18297 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 18298 && osi.sec->size > 0
18299 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 18300 {
18301 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18302 (output_bfd, osi.sec->output_section);
18303 if (osi.sec_shndx != (int)SHN_BAD)
18304 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18305 }
18306 }
18307 }
18308
91a5743d
PB		 18309 /* ARM->Thumb glue. */
18310 if (htab->arm_glue_size > 0)
18311 {
3d4d4302
AM		 18312 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18313 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 18314
18315 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18316 (output_bfd, osi.sec->output_section);
0e1862bb 18317 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 18318 || htab->pic_veneer)
18319 size = ARM2THUMB_PIC_GLUE_SIZE;
18320 else if (htab->use_blx)
18321 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18322 else
18323 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 18324
91a5743d
PB		 18325 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18326 {
7413f23f
DJ		 18327 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18328 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 18329 }
18330 }
18331
18332 /* Thumb->ARM glue. */
18333 if (htab->thumb_glue_size > 0)
18334 {
3d4d4302
AM		 18335 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18336 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 18337
18338 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18339 (output_bfd, osi.sec->output_section);
18340 size = THUMB2ARM_GLUE_SIZE;
18341
18342 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18343 {
7413f23f
DJ		 18344 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18345 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 18346 }
18347 }
18348
845b51d6
PB		 18349 /* ARMv4 BX veneers. */
18350 if (htab->bx_glue_size > 0)
18351 {
3d4d4302
AM		 18352 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18353 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 18354
18355 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18356 (output_bfd, osi.sec->output_section);
18357
7413f23f 18358 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 18359 }
18360
8029a119
NC		 18361 /* Long calls stubs. */
18362 if (htab->stub_bfd && htab->stub_bfd->sections)
18363 {
da5938a2 18364 asection* stub_sec;
8029a119 18365
da5938a2
NC		 18366 for (stub_sec = htab->stub_bfd->sections;
18367 stub_sec != NULL;
8029a119
NC		 18368 stub_sec = stub_sec->next)
18369 {
18370 /* Ignore non-stub sections. */
18371 if (!strstr (stub_sec->name, STUB_SUFFIX))
18372 continue;
da5938a2 18373
8029a119 18374 osi.sec = stub_sec;
da5938a2 18375
8029a119
NC		 18376 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18377 (output_bfd, osi.sec->output_section);
da5938a2 18378
8029a119
NC		 18379 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18380 }
18381 }
da5938a2 18382
91a5743d 18383 /* Finally, output mapping symbols for the PLT. */
34e77a92 18384 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 18385 {
34e77a92
RS		 18386 osi.sec = htab->root.splt;
18387 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18388 (output_bfd, osi.sec->output_section));
18389
18390 /* Output mapping symbols for the plt header. SymbianOS does not have a
18391 plt header. */
18392 if (htab->vxworks_p)
18393 {
18394 /* VxWorks shared libraries have no PLT header. */
0e1862bb 18395 if (!bfd_link_pic (info))
34e77a92
RS		 18396 {
18397 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18398 return FALSE;
18399 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18400 return FALSE;
18401 }
18402 }
b38cadfb
NC		 18403 else if (htab->nacl_p)
18404 {
18405 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18406 return FALSE;
18407 }
59029f57 18408 else if (using_thumb_only (htab) && !htab->fdpic_p)
eed94f8f
NC		 18409 {
18410 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18411 return FALSE;
18412 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18413 return FALSE;
18414 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18415 return FALSE;
18416 }
e8b09b87 18417 else if (!htab->symbian_p && !htab->fdpic_p)
4e617b1e 18418 {
7413f23f 18419 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 18420 return FALSE;
34e77a92
RS		 18421#ifndef FOUR_WORD_PLT
18422 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 18423 return FALSE;
34e77a92 18424#endif
4e617b1e
PB		 18425 }
18426 }
99059e56
RM		 18427 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
18428 {
18429 /* NaCl uses a special first entry in .iplt too. */
18430 osi.sec = htab->root.iplt;
18431 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18432 (output_bfd, osi.sec->output_section));
18433 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18434 return FALSE;
18435 }
34e77a92
RS		 18436 if ((htab->root.splt && htab->root.splt->size > 0)
18437 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 18438 {
34e77a92
RS		 18439 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18440 for (input_bfd = info->input_bfds;
18441 input_bfd != NULL;
c72f2fb2 18442 input_bfd = input_bfd->link.next)
34e77a92
RS		 18443 {
18444 struct arm_local_iplt_info **local_iplt;
18445 unsigned int i, num_syms;
4e617b1e 18446
34e77a92
RS		 18447 local_iplt = elf32_arm_local_iplt (input_bfd);
18448 if (local_iplt != NULL)
18449 {
18450 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18451 for (i = 0; i < num_syms; i++)
18452 if (local_iplt[i] != NULL
18453 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
18454 &local_iplt[i]->root,
18455 &local_iplt[i]->arm))
18456 return FALSE;
18457 }
18458 }
18459 }
0855e32b
NS		 18460 if (htab->dt_tlsdesc_plt != 0)
18461 {
18462 /* Mapping symbols for the lazy tls trampoline. */
18463 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
18464 return FALSE;
b38cadfb 18465
0855e32b
NS		 18466 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18467 htab->dt_tlsdesc_plt + 24))
18468 return FALSE;
18469 }
18470 if (htab->tls_trampoline != 0)
18471 {
18472 /* Mapping symbols for the tls trampoline. */
18473 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18474 return FALSE;
18475#ifdef FOUR_WORD_PLT
18476 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18477 htab->tls_trampoline + 12))
18478 return FALSE;
b38cadfb 18479#endif
0855e32b 18480 }
b38cadfb 18481
4e617b1e
PB		 18482 return TRUE;
18483}
18484
54ddd295
TP		 18485/* Filter normal symbols of CMSE entry functions of ABFD to include in
18486 the import library. All SYMCOUNT symbols of ABFD can be examined
18487 from their pointers in SYMS. Pointers of symbols to keep should be
18488 stored continuously at the beginning of that array.
18489
18490 Returns the number of symbols to keep. */
18491
18492static unsigned int
18493elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18494 struct bfd_link_info *info,
18495 asymbol **syms, long symcount)
18496{
18497 size_t maxnamelen;
18498 char *cmse_name;
18499 long src_count, dst_count = 0;
18500 struct elf32_arm_link_hash_table *htab;
18501
18502 htab = elf32_arm_hash_table (info);
18503 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18504 symcount = 0;
18505
18506 maxnamelen = 128;
18507 cmse_name = (char *) bfd_malloc (maxnamelen);
18508 for (src_count = 0; src_count < symcount; src_count++)
18509 {
18510 struct elf32_arm_link_hash_entry *cmse_hash;
18511 asymbol *sym;
18512 flagword flags;
18513 char *name;
18514 size_t namelen;
18515
18516 sym = syms[src_count];
18517 flags = sym->flags;
18518 name = (char *) bfd_asymbol_name (sym);
18519
18520 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18521 continue;
18522 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18523 continue;
18524
18525 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18526 if (namelen > maxnamelen)
18527 {
18528 cmse_name = (char *)
18529 bfd_realloc (cmse_name, namelen);
18530 maxnamelen = namelen;
18531 }
18532 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18533 cmse_hash = (struct elf32_arm_link_hash_entry *)
18534 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
18535
18536 if (!cmse_hash
18537 || (cmse_hash->root.root.type != bfd_link_hash_defined
18538 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18539 || cmse_hash->root.type != STT_FUNC)
18540 continue;
18541
54ddd295
TP		 18542 syms[dst_count++] = sym;
18543 }
18544 free (cmse_name);
18545
18546 syms[dst_count] = NULL;
18547
18548 return dst_count;
18549}
18550
18551/* Filter symbols of ABFD to include in the import library. All
18552 SYMCOUNT symbols of ABFD can be examined from their pointers in
18553 SYMS. Pointers of symbols to keep should be stored continuously at
18554 the beginning of that array.
18555
18556 Returns the number of symbols to keep. */
18557
18558static unsigned int
18559elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18560 struct bfd_link_info *info,
18561 asymbol **syms, long symcount)
18562{
18563 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18564
046734ff
TP		 18565 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18566 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18567 library to be a relocatable object file. */
18568 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 18569 if (globals->cmse_implib)
18570 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18571 else
18572 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18573}
18574
e489d0ae
PB		 18575/* Allocate target specific section data. */
18576
18577static bfd_boolean
18578elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18579{
f592407e
AM		 18580 if (!sec->used_by_bfd)
18581 {
18582 _arm_elf_section_data *sdata;
18583 bfd_size_type amt = sizeof (*sdata);
e489d0ae 18584
21d799b5 18585 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 18586 if (sdata == NULL)
18587 return FALSE;
18588 sec->used_by_bfd = sdata;
18589 }
e489d0ae
PB		 18590
18591 return _bfd_elf_new_section_hook (abfd, sec);
18592}
18593
18594
18595/* Used to order a list of mapping symbols by address. */
18596
18597static int
18598elf32_arm_compare_mapping (const void * a, const void * b)
18599{
7f6a71ff
JM		 18600 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18601 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18602
18603 if (amap->vma > bmap->vma)
18604 return 1;
18605 else if (amap->vma < bmap->vma)
18606 return -1;
18607 else if (amap->type > bmap->type)
18608 /* Ensure results do not depend on the host qsort for objects with
18609 multiple mapping symbols at the same address by sorting on type
18610 after vma. */
18611 return 1;
18612 else if (amap->type < bmap->type)
18613 return -1;
18614 else
18615 return 0;
e489d0ae
PB		 18616}
18617
2468f9c9
PB		 18618/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18619
18620static unsigned long
18621offset_prel31 (unsigned long addr, bfd_vma offset)
18622{
18623 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18624}
18625
18626/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18627 relocations. */
18628
18629static void
18630copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18631{
18632 unsigned long first_word = bfd_get_32 (output_bfd, from);
18633 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 18634
2468f9c9
PB		 18635 /* High bit of first word is supposed to be zero. */
18636 if ((first_word & 0x80000000ul) == 0)
18637 first_word = offset_prel31 (first_word, offset);
b38cadfb 18638
2468f9c9
PB		 18639 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18640 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18641 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18642 second_word = offset_prel31 (second_word, offset);
b38cadfb 18643
2468f9c9
PB		 18644 bfd_put_32 (output_bfd, first_word, to);
18645 bfd_put_32 (output_bfd, second_word, to + 4);
18646}
e489d0ae 18647
48229727
JB		 18648/* Data for make_branch_to_a8_stub(). */
18649
b38cadfb
NC		 18650struct a8_branch_to_stub_data
18651{
48229727
JB		 18652 asection *writing_section;
18653 bfd_byte *contents;
18654};
18655
18656
18657/* Helper to insert branches to Cortex-A8 erratum stubs in the right
18658 places for a particular section. */
18659
18660static bfd_boolean
18661make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 18662 void *in_arg)
48229727
JB		 18663{
18664 struct elf32_arm_stub_hash_entry *stub_entry;
18665 struct a8_branch_to_stub_data *data;
18666 bfd_byte *contents;
18667 unsigned long branch_insn;
18668 bfd_vma veneered_insn_loc, veneer_entry_loc;
18669 bfd_signed_vma branch_offset;
18670 bfd *abfd;
8d9d9490 18671 unsigned int loc;
48229727
JB		 18672
18673 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18674 data = (struct a8_branch_to_stub_data *) in_arg;
18675
18676 if (stub_entry->target_section != data->writing_section
4563a860 18677 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 18678 return TRUE;
18679
18680 contents = data->contents;
18681
8d9d9490
TP		 18682 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18683 generated when both source and target are in the same section. */
48229727
JB		 18684 veneered_insn_loc = stub_entry->target_section->output_section->vma
18685 + stub_entry->target_section->output_offset
8d9d9490 18686 + stub_entry->source_value;
48229727
JB		 18687
18688 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18689 + stub_entry->stub_sec->output_offset
18690 + stub_entry->stub_offset;
18691
18692 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18693 veneered_insn_loc &= ~3u;
18694
18695 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18696
18697 abfd = stub_entry->target_section->owner;
8d9d9490 18698 loc = stub_entry->source_value;
48229727
JB		 18699
18700 /* We attempt to avoid this condition by setting stubs_always_after_branch
18701 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18702 This check is just to be on the safe side... */
18703 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18704 {
871b3ab2 18705 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 18706 "allocated in unsafe location"), abfd);
48229727
JB		 18707 return FALSE;
18708 }
18709
18710 switch (stub_entry->stub_type)
18711 {
18712 case arm_stub_a8_veneer_b:
18713 case arm_stub_a8_veneer_b_cond:
18714 branch_insn = 0xf0009000;
18715 goto jump24;
18716
18717 case arm_stub_a8_veneer_blx:
18718 branch_insn = 0xf000e800;
18719 goto jump24;
18720
18721 case arm_stub_a8_veneer_bl:
18722 {
18723 unsigned int i1, j1, i2, j2, s;
18724
18725 branch_insn = 0xf000d000;
18726
18727 jump24:
18728 if (branch_offset < -16777216 || branch_offset > 16777214)
18729 {
18730 /* There's not much we can do apart from complain if this
18731 happens. */
871b3ab2 18732 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 18733 "of range (input file too large)"), abfd);
48229727
JB		 18734 return FALSE;
18735 }
18736
18737 /* i1 = not(j1 eor s), so:
18738 not i1 = j1 eor s
18739 j1 = (not i1) eor s. */
18740
18741 branch_insn |= (branch_offset >> 1) & 0x7ff;
18742 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18743 i2 = (branch_offset >> 22) & 1;
18744 i1 = (branch_offset >> 23) & 1;
18745 s = (branch_offset >> 24) & 1;
18746 j1 = (!i1) ^ s;
18747 j2 = (!i2) ^ s;
18748 branch_insn |= j2 << 11;
18749 branch_insn |= j1 << 13;
18750 branch_insn |= s << 26;
18751 }
18752 break;
18753
18754 default:
18755 BFD_FAIL ();
18756 return FALSE;
18757 }
18758
8d9d9490
TP		 18759 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18760 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 18761
18762 return TRUE;
18763}
18764
a504d23a
LA		 18765/* Beginning of stm32l4xx work-around. */
18766
18767/* Functions encoding instructions necessary for the emission of the
18768 fix-stm32l4xx-629360.
18769 Encoding is extracted from the
18770 ARM (C) Architecture Reference Manual
18771 ARMv7-A and ARMv7-R edition
18772 ARM DDI 0406C.b (ID072512). */
18773
18774static inline bfd_vma
82188b29 18775create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 18776{
18777 /* A8.8.18 B (A8-334)
18778 B target_address (Encoding T4). */
18779 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18780 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18781 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18782
a504d23a
LA		 18783 int s = ((branch_offset & 0x1000000) >> 24);
18784 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18785 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18786
18787 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18788 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18789
18790 bfd_vma patched_inst = 0xf0009000
18791 | s << 26 /* S. */
18792 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18793 | j1 << 13 /* J1. */
18794 | j2 << 11 /* J2. */
18795 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18796
18797 return patched_inst;
18798}
18799
18800static inline bfd_vma
18801create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18802{
18803 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18804 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18805 bfd_vma patched_inst = 0xe8900000
18806 | (/*W=*/wback << 21)
18807 | (base_reg << 16)
18808 | (reg_mask & 0x0000ffff);
18809
18810 return patched_inst;
18811}
18812
18813static inline bfd_vma
18814create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18815{
18816 /* A8.8.60 LDMDB/LDMEA (A8-402)
18817 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18818 bfd_vma patched_inst = 0xe9100000
18819 | (/*W=*/wback << 21)
18820 | (base_reg << 16)
18821 | (reg_mask & 0x0000ffff);
18822
18823 return patched_inst;
18824}
18825
18826static inline bfd_vma
18827create_instruction_mov (int target_reg, int source_reg)
18828{
18829 /* A8.8.103 MOV (register) (A8-486)
18830 MOV Rd, Rm (Encoding T1). */
18831 bfd_vma patched_inst = 0x4600
18832 | (target_reg & 0x7)
18833 | ((target_reg & 0x8) >> 3) << 7
18834 | (source_reg << 3);
18835
18836 return patched_inst;
18837}
18838
18839static inline bfd_vma
18840create_instruction_sub (int target_reg, int source_reg, int value)
18841{
18842 /* A8.8.221 SUB (immediate) (A8-708)
18843 SUB Rd, Rn, #value (Encoding T3). */
18844 bfd_vma patched_inst = 0xf1a00000
18845 | (target_reg << 8)
18846 | (source_reg << 16)
18847 | (/*S=*/0 << 20)
18848 | ((value & 0x800) >> 11) << 26
18849 | ((value & 0x700) >> 8) << 12
18850 | (value & 0x0ff);
18851
18852 return patched_inst;
18853}
18854
18855static inline bfd_vma
9239bbd3 18856create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 18857 int first_reg)
18858{
18859 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18860 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18861 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 18862 | (/*W=*/wback << 21)
18863 | (base_reg << 16)
9239bbd3
CM		 18864 | (num_words & 0x000000ff)
18865 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 18866 | (first_reg & 0x00000001) << 22;
18867
18868 return patched_inst;
18869}
18870
18871static inline bfd_vma
9239bbd3
CM		 18872create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18873 int first_reg)
a504d23a
LA		 18874{
18875 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18876 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18877 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 18878 | (base_reg << 16)
9239bbd3
CM		 18879 | (num_words & 0x000000ff)
18880 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 18881 | (first_reg & 0x00000001) << 22;
18882
18883 return patched_inst;
18884}
18885
18886static inline bfd_vma
18887create_instruction_udf_w (int value)
18888{
18889 /* A8.8.247 UDF (A8-758)
18890 Undefined (Encoding T2). */
18891 bfd_vma patched_inst = 0xf7f0a000
18892 | (value & 0x00000fff)
18893 | (value & 0x000f0000) << 16;
18894
18895 return patched_inst;
18896}
18897
18898static inline bfd_vma
18899create_instruction_udf (int value)
18900{
18901 /* A8.8.247 UDF (A8-758)
18902 Undefined (Encoding T1). */
18903 bfd_vma patched_inst = 0xde00
18904 | (value & 0xff);
18905
18906 return patched_inst;
18907}
18908
18909/* Functions writing an instruction in memory, returning the next
18910 memory position to write to. */
18911
18912static inline bfd_byte *
18913push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18914 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18915{
18916 put_thumb2_insn (htab, output_bfd, insn, pt);
18917 return pt + 4;
18918}
18919
18920static inline bfd_byte *
18921push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
18922 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18923{
18924 put_thumb_insn (htab, output_bfd, insn, pt);
18925 return pt + 2;
18926}
18927
18928/* Function filling up a region in memory with T1 and T2 UDFs taking
18929 care of alignment. */
18930
18931static bfd_byte *
18932stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 18933 bfd * output_bfd,
18934 const bfd_byte * const base_stub_contents,
18935 bfd_byte * const from_stub_contents,
18936 const bfd_byte * const end_stub_contents)
a504d23a
LA		 18937{
18938 bfd_byte *current_stub_contents = from_stub_contents;
18939
18940 /* Fill the remaining of the stub with deterministic contents : UDF
18941 instructions.
18942 Check if realignment is needed on modulo 4 frontier using T1, to
18943 further use T2. */
18944 if ((current_stub_contents < end_stub_contents)
18945 && !((current_stub_contents - base_stub_contents) % 2)
18946 && ((current_stub_contents - base_stub_contents) % 4))
18947 current_stub_contents =
18948 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18949 create_instruction_udf (0));
18950
18951 for (; current_stub_contents < end_stub_contents;)
18952 current_stub_contents =
18953 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18954 create_instruction_udf_w (0));
18955
18956 return current_stub_contents;
18957}
18958
18959/* Functions writing the stream of instructions equivalent to the
18960 derived sequence for ldmia, ldmdb, vldm respectively. */
18961
18962static void
18963stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
18964 bfd * output_bfd,
18965 const insn32 initial_insn,
18966 const bfd_byte *const initial_insn_addr,
18967 bfd_byte *const base_stub_contents)
18968{
18969 int wback = (initial_insn & 0x00200000) >> 21;
18970 int ri, rn = (initial_insn & 0x000F0000) >> 16;
18971 int insn_all_registers = initial_insn & 0x0000ffff;
18972 int insn_low_registers, insn_high_registers;
18973 int usable_register_mask;
b25e998d 18974 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18975 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18976 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
18977 bfd_byte *current_stub_contents = base_stub_contents;
18978
18979 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
18980
18981 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18982 smaller than 8 registers load sequences that do not cause the
18983 hardware issue. */
18984 if (nb_registers <= 8)
18985 {
18986 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18987 current_stub_contents =
18988 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18989 initial_insn);
18990
18991 /* B initial_insn_addr+4. */
18992 if (!restore_pc)
18993 current_stub_contents =
18994 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18995 create_instruction_branch_absolute
82188b29 18996 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18997
18998 /* Fill the remaining of the stub with deterministic contents. */
18999 current_stub_contents =
19000 stm32l4xx_fill_stub_udf (htab, output_bfd,
19001 base_stub_contents, current_stub_contents,
19002 base_stub_contents +
19003 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19004
19005 return;
19006 }
19007
19008 /* - reg_list[13] == 0. */
19009 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
19010
19011 /* - reg_list[14] & reg_list[15] != 1. */
19012 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19013
19014 /* - if (wback==1) reg_list[rn] == 0. */
19015 BFD_ASSERT (!wback || !restore_rn);
19016
19017 /* - nb_registers > 8. */
b25e998d 19018 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19019
19020 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19021
19022 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
19023 - One with the 7 lowest registers (register mask 0x007F)
19024 This LDM will finally contain between 2 and 7 registers
19025 - One with the 7 highest registers (register mask 0xDF80)
19026 This ldm will finally contain between 2 and 7 registers. */
19027 insn_low_registers = insn_all_registers & 0x007F;
19028 insn_high_registers = insn_all_registers & 0xDF80;
19029
19030 /* A spare register may be needed during this veneer to temporarily
19031 handle the base register. This register will be restored with the
19032 last LDM operation.
19033 The usable register may be any general purpose register (that
19034 excludes PC, SP, LR : register mask is 0x1FFF). */
19035 usable_register_mask = 0x1FFF;
19036
19037 /* Generate the stub function. */
19038 if (wback)
19039 {
19040 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
19041 current_stub_contents =
19042 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19043 create_instruction_ldmia
19044 (rn, /*wback=*/1, insn_low_registers));
19045
19046 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
19047 current_stub_contents =
19048 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19049 create_instruction_ldmia
19050 (rn, /*wback=*/1, insn_high_registers));
19051 if (!restore_pc)
19052 {
19053 /* B initial_insn_addr+4. */
19054 current_stub_contents =
19055 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19056 create_instruction_branch_absolute
82188b29 19057 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19058 }
19059 }
19060 else /* if (!wback). */
19061 {
19062 ri = rn;
19063
19064 /* If Rn is not part of the high-register-list, move it there. */
19065 if (!(insn_high_registers & (1 << rn)))
19066 {
19067 /* Choose a Ri in the high-register-list that will be restored. */
19068 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19069
19070 /* MOV Ri, Rn. */
19071 current_stub_contents =
19072 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19073 create_instruction_mov (ri, rn));
19074 }
19075
19076 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
19077 current_stub_contents =
19078 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19079 create_instruction_ldmia
19080 (ri, /*wback=*/1, insn_low_registers));
19081
19082 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
19083 current_stub_contents =
19084 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19085 create_instruction_ldmia
19086 (ri, /*wback=*/0, insn_high_registers));
19087
19088 if (!restore_pc)
19089 {
19090 /* B initial_insn_addr+4. */
19091 current_stub_contents =
19092 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19093 create_instruction_branch_absolute
82188b29 19094 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19095 }
19096 }
19097
19098 /* Fill the remaining of the stub with deterministic contents. */
19099 current_stub_contents =
19100 stm32l4xx_fill_stub_udf (htab, output_bfd,
19101 base_stub_contents, current_stub_contents,
19102 base_stub_contents +
19103 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19104}
19105
19106static void
19107stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
19108 bfd * output_bfd,
19109 const insn32 initial_insn,
19110 const bfd_byte *const initial_insn_addr,
19111 bfd_byte *const base_stub_contents)
19112{
19113 int wback = (initial_insn & 0x00200000) >> 21;
19114 int ri, rn = (initial_insn & 0x000f0000) >> 16;
19115 int insn_all_registers = initial_insn & 0x0000ffff;
19116 int insn_low_registers, insn_high_registers;
19117 int usable_register_mask;
19118 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
19119 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 19120 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 19121 bfd_byte *current_stub_contents = base_stub_contents;
19122
19123 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
19124
19125 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19126 smaller than 8 registers load sequences that do not cause the
19127 hardware issue. */
19128 if (nb_registers <= 8)
19129 {
19130 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19131 current_stub_contents =
19132 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19133 initial_insn);
19134
19135 /* B initial_insn_addr+4. */
19136 current_stub_contents =
19137 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19138 create_instruction_branch_absolute
82188b29 19139 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19140
19141 /* Fill the remaining of the stub with deterministic contents. */
19142 current_stub_contents =
19143 stm32l4xx_fill_stub_udf (htab, output_bfd,
19144 base_stub_contents, current_stub_contents,
19145 base_stub_contents +
19146 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19147
19148 return;
19149 }
19150
19151 /* - reg_list[13] == 0. */
19152 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
19153
19154 /* - reg_list[14] & reg_list[15] != 1. */
19155 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19156
19157 /* - if (wback==1) reg_list[rn] == 0. */
19158 BFD_ASSERT (!wback || !restore_rn);
19159
19160 /* - nb_registers > 8. */
b25e998d 19161 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19162
19163 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19164
19165 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19166 - One with the 7 lowest registers (register mask 0x007F)
19167 This LDM will finally contain between 2 and 7 registers
19168 - One with the 7 highest registers (register mask 0xDF80)
19169 This ldm will finally contain between 2 and 7 registers. */
19170 insn_low_registers = insn_all_registers & 0x007F;
19171 insn_high_registers = insn_all_registers & 0xDF80;
19172
19173 /* A spare register may be needed during this veneer to temporarily
19174 handle the base register. This register will be restored with
19175 the last LDM operation.
19176 The usable register may be any general purpose register (that excludes
19177 PC, SP, LR : register mask is 0x1FFF). */
19178 usable_register_mask = 0x1FFF;
19179
19180 /* Generate the stub function. */
19181 if (!wback && !restore_pc && !restore_rn)
19182 {
19183 /* Choose a Ri in the low-register-list that will be restored. */
19184 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19185
19186 /* MOV Ri, Rn. */
19187 current_stub_contents =
19188 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19189 create_instruction_mov (ri, rn));
19190
19191 /* LDMDB Ri!, {R-high-register-list}. */
19192 current_stub_contents =
19193 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19194 create_instruction_ldmdb
19195 (ri, /*wback=*/1, insn_high_registers));
19196
19197 /* LDMDB Ri, {R-low-register-list}. */
19198 current_stub_contents =
19199 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19200 create_instruction_ldmdb
19201 (ri, /*wback=*/0, insn_low_registers));
19202
19203 /* B initial_insn_addr+4. */
19204 current_stub_contents =
19205 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19206 create_instruction_branch_absolute
82188b29 19207 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19208 }
19209 else if (wback && !restore_pc && !restore_rn)
19210 {
19211 /* LDMDB Rn!, {R-high-register-list}. */
19212 current_stub_contents =
19213 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19214 create_instruction_ldmdb
19215 (rn, /*wback=*/1, insn_high_registers));
19216
19217 /* LDMDB Rn!, {R-low-register-list}. */
19218 current_stub_contents =
19219 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19220 create_instruction_ldmdb
19221 (rn, /*wback=*/1, insn_low_registers));
19222
19223 /* B initial_insn_addr+4. */
19224 current_stub_contents =
19225 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19226 create_instruction_branch_absolute
82188b29 19227 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19228 }
19229 else if (!wback && restore_pc && !restore_rn)
19230 {
19231 /* Choose a Ri in the high-register-list that will be restored. */
19232 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19233
19234 /* SUB Ri, Rn, #(4*nb_registers). */
19235 current_stub_contents =
19236 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19237 create_instruction_sub (ri, rn, (4 * nb_registers)));
19238
19239 /* LDMIA Ri!, {R-low-register-list}. */
19240 current_stub_contents =
19241 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19242 create_instruction_ldmia
19243 (ri, /*wback=*/1, insn_low_registers));
19244
19245 /* LDMIA Ri, {R-high-register-list}. */
19246 current_stub_contents =
19247 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19248 create_instruction_ldmia
19249 (ri, /*wback=*/0, insn_high_registers));
19250 }
19251 else if (wback && restore_pc && !restore_rn)
19252 {
19253 /* Choose a Ri in the high-register-list that will be restored. */
19254 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19255
19256 /* SUB Rn, Rn, #(4*nb_registers) */
19257 current_stub_contents =
19258 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19259 create_instruction_sub (rn, rn, (4 * nb_registers)));
19260
19261 /* MOV Ri, Rn. */
19262 current_stub_contents =
19263 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19264 create_instruction_mov (ri, rn));
19265
19266 /* LDMIA Ri!, {R-low-register-list}. */
19267 current_stub_contents =
19268 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19269 create_instruction_ldmia
19270 (ri, /*wback=*/1, insn_low_registers));
19271
19272 /* LDMIA Ri, {R-high-register-list}. */
19273 current_stub_contents =
19274 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19275 create_instruction_ldmia
19276 (ri, /*wback=*/0, insn_high_registers));
19277 }
19278 else if (!wback && !restore_pc && restore_rn)
19279 {
19280 ri = rn;
19281 if (!(insn_low_registers & (1 << rn)))
19282 {
19283 /* Choose a Ri in the low-register-list that will be restored. */
19284 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19285
19286 /* MOV Ri, Rn. */
19287 current_stub_contents =
19288 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19289 create_instruction_mov (ri, rn));
19290 }
19291
19292 /* LDMDB Ri!, {R-high-register-list}. */
19293 current_stub_contents =
19294 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19295 create_instruction_ldmdb
19296 (ri, /*wback=*/1, insn_high_registers));
19297
19298 /* LDMDB Ri, {R-low-register-list}. */
19299 current_stub_contents =
19300 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19301 create_instruction_ldmdb
19302 (ri, /*wback=*/0, insn_low_registers));
19303
19304 /* B initial_insn_addr+4. */
19305 current_stub_contents =
19306 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19307 create_instruction_branch_absolute
82188b29 19308 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19309 }
19310 else if (!wback && restore_pc && restore_rn)
19311 {
19312 ri = rn;
19313 if (!(insn_high_registers & (1 << rn)))
19314 {
19315 /* Choose a Ri in the high-register-list that will be restored. */
19316 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19317 }
19318
19319 /* SUB Ri, Rn, #(4*nb_registers). */
19320 current_stub_contents =
19321 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19322 create_instruction_sub (ri, rn, (4 * nb_registers)));
19323
19324 /* LDMIA Ri!, {R-low-register-list}. */
19325 current_stub_contents =
19326 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19327 create_instruction_ldmia
19328 (ri, /*wback=*/1, insn_low_registers));
19329
19330 /* LDMIA Ri, {R-high-register-list}. */
19331 current_stub_contents =
19332 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19333 create_instruction_ldmia
19334 (ri, /*wback=*/0, insn_high_registers));
19335 }
19336 else if (wback && restore_rn)
19337 {
19338 /* The assembler should not have accepted to encode this. */
19339 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19340 "undefined behavior.\n");
19341 }
19342
19343 /* Fill the remaining of the stub with deterministic contents. */
19344 current_stub_contents =
19345 stm32l4xx_fill_stub_udf (htab, output_bfd,
19346 base_stub_contents, current_stub_contents,
19347 base_stub_contents +
19348 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19349
19350}
19351
19352static void
19353stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19354 bfd * output_bfd,
19355 const insn32 initial_insn,
19356 const bfd_byte *const initial_insn_addr,
19357 bfd_byte *const base_stub_contents)
19358{
9239bbd3 19359 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 19360 bfd_byte *current_stub_contents = base_stub_contents;
19361
19362 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19363
19364 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 19365 smaller than 8 words load sequences that do not cause the
a504d23a 19366 hardware issue. */
9239bbd3 19367 if (num_words <= 8)
a504d23a
LA		 19368 {
19369 /* Untouched instruction. */
19370 current_stub_contents =
19371 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19372 initial_insn);
19373
19374 /* B initial_insn_addr+4. */
19375 current_stub_contents =
19376 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19377 create_instruction_branch_absolute
82188b29 19378 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19379 }
19380 else
19381 {
9eaff861 19382 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 19383 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 19384 bfd_boolean is_ia_nobang = /* (IA without !). */
19385 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19386 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
19387 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19388 bfd_boolean is_db_bang = /* (DB with !). */
19389 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 19390 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 19391 /* d = UInt (Vd:D);. */
9239bbd3 19392 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 19393 | (((unsigned int)initial_insn << 9) >> 31);
19394
9239bbd3
CM		 19395 /* Compute the number of 8-words chunks needed to split. */
19396 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 19397 int chunk;
19398
19399 /* The test coverage has been done assuming the following
19400 hypothesis that exactly one of the previous is_ predicates is
19401 true. */
9239bbd3
CM		 19402 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19403 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 19404
9239bbd3 19405 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 19406 cases, then we emit the adjustments:
19407
19408 vldm rx, {...}
19409 -> vldm rx!, {8_words_or_less} for each needed 8_word
19410 -> sub rx, rx, #size (list)
19411
19412 vldm rx!, {...}
19413 -> vldm rx!, {8_words_or_less} for each needed 8_word
19414 This also handles vpop instruction (when rx is sp)
19415
19416 vldmd rx!, {...}
19417 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 19418 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 19419 {
9239bbd3
CM		 19420 bfd_vma new_insn = 0;
19421
a504d23a
LA		 19422 if (is_ia_nobang || is_ia_bang)
19423 {
9239bbd3
CM		 19424 new_insn = create_instruction_vldmia
19425 (base_reg,
19426 is_dp,
19427 /*wback= . */1,
19428 chunks - (chunk + 1) ?
19429 8 : num_words - chunk * 8,
19430 first_reg + chunk * 8);
a504d23a
LA		 19431 }
19432 else if (is_db_bang)
19433 {
9239bbd3
CM		 19434 new_insn = create_instruction_vldmdb
19435 (base_reg,
19436 is_dp,
19437 chunks - (chunk + 1) ?
19438 8 : num_words - chunk * 8,
19439 first_reg + chunk * 8);
a504d23a 19440 }
9239bbd3
CM		 19441
19442 if (new_insn)
19443 current_stub_contents =
19444 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19445 new_insn);
a504d23a
LA		 19446 }
19447
19448 /* Only this case requires the base register compensation
19449 subtract. */
19450 if (is_ia_nobang)
19451 {
19452 current_stub_contents =
19453 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19454 create_instruction_sub
9239bbd3 19455 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 19456 }
19457
19458 /* B initial_insn_addr+4. */
19459 current_stub_contents =
19460 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19461 create_instruction_branch_absolute
82188b29 19462 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19463 }
19464
19465 /* Fill the remaining of the stub with deterministic contents. */
19466 current_stub_contents =
19467 stm32l4xx_fill_stub_udf (htab, output_bfd,
19468 base_stub_contents, current_stub_contents,
19469 base_stub_contents +
19470 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19471}
19472
19473static void
19474stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19475 bfd * output_bfd,
19476 const insn32 wrong_insn,
19477 const bfd_byte *const wrong_insn_addr,
19478 bfd_byte *const stub_contents)
19479{
19480 if (is_thumb2_ldmia (wrong_insn))
19481 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19482 wrong_insn, wrong_insn_addr,
19483 stub_contents);
19484 else if (is_thumb2_ldmdb (wrong_insn))
19485 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19486 wrong_insn, wrong_insn_addr,
19487 stub_contents);
19488 else if (is_thumb2_vldm (wrong_insn))
19489 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19490 wrong_insn, wrong_insn_addr,
19491 stub_contents);
19492}
19493
19494/* End of stm32l4xx work-around. */
19495
19496
e489d0ae
PB		 19497/* Do code byteswapping. Return FALSE afterwards so that the section is
19498 written out as normal. */
19499
19500static bfd_boolean
c7b8f16e 19501elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 19502 struct bfd_link_info *link_info,
19503 asection *sec,
e489d0ae
PB		 19504 bfd_byte *contents)
19505{
48229727 19506 unsigned int mapcount, errcount;
8e3de13a 19507 _arm_elf_section_data *arm_data;
c7b8f16e 19508 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 19509 elf32_arm_section_map *map;
c7b8f16e 19510 elf32_vfp11_erratum_list *errnode;
a504d23a 19511 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 19512 bfd_vma ptr;
19513 bfd_vma end;
c7b8f16e 19514 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 19515 bfd_byte tmp;
48229727 19516 unsigned int i;
57e8b36a 19517
4dfe6ac6
NC		 19518 if (globals == NULL)
19519 return FALSE;
19520
8e3de13a
NC		 19521 /* If this section has not been allocated an _arm_elf_section_data
19522 structure then we cannot record anything. */
19523 arm_data = get_arm_elf_section_data (sec);
19524 if (arm_data == NULL)
19525 return FALSE;
19526
19527 mapcount = arm_data->mapcount;
19528 map = arm_data->map;
c7b8f16e
JB		 19529 errcount = arm_data->erratumcount;
19530
19531 if (errcount != 0)
19532 {
19533 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19534
19535 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 19536 errnode = errnode->next)
19537 {
19538 bfd_vma target = errnode->vma - offset;
19539
19540 switch (errnode->type)
19541 {
19542 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19543 {
19544 bfd_vma branch_to_veneer;
19545 /* Original condition code of instruction, plus bit mask for
19546 ARM B instruction. */
19547 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19548 | 0x0a000000;
c7b8f16e
JB		 19549
19550 /* The instruction is before the label. */
91d6fa6a 19551 target -= 4;
c7b8f16e
JB		 19552
19553 /* Above offset included in -4 below. */
19554 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 19555 - errnode->vma - 4;
c7b8f16e
JB		 19556
19557 if ((signed) branch_to_veneer < -(1 << 25)
19558 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 19559 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19560 "range"), output_bfd);
c7b8f16e 19561
99059e56
RM		 19562 insn |= (branch_to_veneer >> 2) & 0xffffff;
19563 contents[endianflip ^ target] = insn & 0xff;
19564 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19565 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19566 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19567 }
19568 break;
c7b8f16e
JB		 19569
19570 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 19571 {
19572 bfd_vma branch_from_veneer;
19573 unsigned int insn;
c7b8f16e 19574
99059e56
RM		 19575 /* Take size of veneer into account. */
19576 branch_from_veneer = errnode->u.v.branch->vma
19577 - errnode->vma - 12;
c7b8f16e
JB		 19578
19579 if ((signed) branch_from_veneer < -(1 << 25)
19580 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 19581 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19582 "range"), output_bfd);
c7b8f16e 19583
99059e56
RM		 19584 /* Original instruction. */
19585 insn = errnode->u.v.branch->u.b.vfp_insn;
19586 contents[endianflip ^ target] = insn & 0xff;
19587 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19588 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19589 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19590
19591 /* Branch back to insn after original insn. */
19592 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19593 contents[endianflip ^ (target + 4)] = insn & 0xff;
19594 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19595 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19596 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19597 }
19598 break;
c7b8f16e 19599
99059e56
RM		 19600 default:
19601 abort ();
19602 }
19603 }
c7b8f16e 19604 }
e489d0ae 19605
a504d23a
LA		 19606 if (arm_data->stm32l4xx_erratumcount != 0)
19607 {
19608 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19609 stm32l4xx_errnode != 0;
19610 stm32l4xx_errnode = stm32l4xx_errnode->next)
19611 {
19612 bfd_vma target = stm32l4xx_errnode->vma - offset;
19613
19614 switch (stm32l4xx_errnode->type)
19615 {
19616 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19617 {
19618 unsigned int insn;
19619 bfd_vma branch_to_veneer =
19620 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19621
19622 if ((signed) branch_to_veneer < -(1 << 24)
19623 || (signed) branch_to_veneer >= (1 << 24))
19624 {
19625 bfd_vma out_of_range =
19626 ((signed) branch_to_veneer < -(1 << 24)) ?
19627 - branch_to_veneer - (1 << 24) :
19628 ((signed) branch_to_veneer >= (1 << 24)) ?
19629 branch_to_veneer - (1 << 24) : 0;
19630
4eca0228 19631 _bfd_error_handler
2dcf00ce 19632 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 19633 "cannot create STM32L4XX veneer; "
19634 "jump out of range by %" PRId64 " bytes; "
19635 "cannot encode branch instruction"),
a504d23a 19636 output_bfd,
2dcf00ce
AM		 19637 (uint64_t) (stm32l4xx_errnode->vma - 4),
19638 (int64_t) out_of_range);
a504d23a
LA		 19639 continue;
19640 }
19641
19642 insn = create_instruction_branch_absolute
82188b29 19643 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a 19644
a2699ef2
AM		 19645 /* The instruction is before the label. */
19646 target -= 4;
19647
a504d23a
LA		 19648 put_thumb2_insn (globals, output_bfd,
19649 (bfd_vma) insn, contents + target);
19650 }
19651 break;
19652
19653 case STM32L4XX_ERRATUM_VENEER:
19654 {
82188b29
NC		 19655 bfd_byte * veneer;
19656 bfd_byte * veneer_r;
a504d23a
LA		 19657 unsigned int insn;
19658
82188b29
NC		 19659 veneer = contents + target;
19660 veneer_r = veneer
19661 + stm32l4xx_errnode->u.b.veneer->vma
19662 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 19663
19664 if ((signed) (veneer_r - veneer -
19665 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19666 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19667 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19668 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19669 || (signed) (veneer_r - veneer) >= (1 << 24))
19670 {
90b6238f
AM		 19671 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19672 "veneer"), output_bfd);
a504d23a
LA		 19673 continue;
19674 }
19675
19676 /* Original instruction. */
19677 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19678
19679 stm32l4xx_create_replacing_stub
19680 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19681 }
19682 break;
19683
19684 default:
19685 abort ();
19686 }
19687 }
19688 }
19689
2468f9c9
PB		 19690 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19691 {
19692 arm_unwind_table_edit *edit_node
99059e56 19693 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 19694 /* Now, sec->size is the size of the section we will write. The original
99059e56 19695 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 19696 markers) was sec->rawsize. (This isn't the case if we perform no
19697 edits, then rawsize will be zero and we should use size). */
21d799b5 19698 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 19699 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19700 unsigned int in_index, out_index;
19701 bfd_vma add_to_offsets = 0;
19702
19703 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 19704 {
2468f9c9
PB		 19705 if (edit_node)
19706 {
19707 unsigned int edit_index = edit_node->index;
b38cadfb 19708
2468f9c9 19709 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 19710 {
2468f9c9
PB		 19711 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19712 contents + in_index * 8, add_to_offsets);
19713 out_index++;
19714 in_index++;
19715 }
19716 else if (in_index == edit_index
19717 || (in_index * 8 >= input_size
19718 && edit_index == UINT_MAX))
99059e56 19719 {
2468f9c9
PB		 19720 switch (edit_node->type)
19721 {
19722 case DELETE_EXIDX_ENTRY:
19723 in_index++;
19724 add_to_offsets += 8;
19725 break;
b38cadfb 19726
2468f9c9
PB		 19727 case INSERT_EXIDX_CANTUNWIND_AT_END:
19728 {
99059e56 19729 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 19730 bfd_vma text_offset = text_sec->output_section->vma
19731 + text_sec->output_offset
19732 + text_sec->size;
19733 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 19734 unsigned long prel31_offset;
2468f9c9
PB		 19735
19736 /* Note: this is meant to be equivalent to an
19737 R_ARM_PREL31 relocation. These synthetic
19738 EXIDX_CANTUNWIND markers are not relocated by the
19739 usual BFD method. */
19740 prel31_offset = (text_offset - exidx_offset)
19741 & 0x7ffffffful;
491d01d3
YU		 19742 if (bfd_link_relocatable (link_info))
19743 {
19744 /* Here relocation for new EXIDX_CANTUNWIND is
19745 created, so there is no need to
19746 adjust offset by hand. */
19747 prel31_offset = text_sec->output_offset
19748 + text_sec->size;
491d01d3 19749 }
2468f9c9
PB		 19750
19751 /* First address we can't unwind. */
19752 bfd_put_32 (output_bfd, prel31_offset,
19753 &edited_contents[out_index * 8]);
19754
19755 /* Code for EXIDX_CANTUNWIND. */
19756 bfd_put_32 (output_bfd, 0x1,
19757 &edited_contents[out_index * 8 + 4]);
19758
19759 out_index++;
19760 add_to_offsets -= 8;
19761 }
19762 break;
19763 }
b38cadfb 19764
2468f9c9
PB		 19765 edit_node = edit_node->next;
19766 }
19767 }
19768 else
19769 {
19770 /* No more edits, copy remaining entries verbatim. */
19771 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19772 contents + in_index * 8, add_to_offsets);
19773 out_index++;
19774 in_index++;
19775 }
19776 }
19777
19778 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19779 bfd_set_section_contents (output_bfd, sec->output_section,
19780 edited_contents,
19781 (file_ptr) sec->output_offset, sec->size);
19782
19783 return TRUE;
19784 }
19785
48229727
JB		 19786 /* Fix code to point to Cortex-A8 erratum stubs. */
19787 if (globals->fix_cortex_a8)
19788 {
19789 struct a8_branch_to_stub_data data;
19790
19791 data.writing_section = sec;
19792 data.contents = contents;
19793
a504d23a
LA		 19794 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19795 & data);
48229727
JB		 19796 }
19797
e489d0ae
PB		 19798 if (mapcount == 0)
19799 return FALSE;
19800
c7b8f16e 19801 if (globals->byteswap_code)
e489d0ae 19802 {
c7b8f16e 19803 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 19804
c7b8f16e
JB		 19805 ptr = map[0].vma;
19806 for (i = 0; i < mapcount; i++)
99059e56
RM		 19807 {
19808 if (i == mapcount - 1)
c7b8f16e 19809 end = sec->size;
99059e56
RM		 19810 else
19811 end = map[i + 1].vma;
e489d0ae 19812
99059e56 19813 switch (map[i].type)
e489d0ae 19814 {
c7b8f16e
JB		 19815 case 'a':
19816 /* Byte swap code words. */
19817 while (ptr + 3 < end)
99059e56
RM		 19818 {
19819 tmp = contents[ptr];
19820 contents[ptr] = contents[ptr + 3];
19821 contents[ptr + 3] = tmp;
19822 tmp = contents[ptr + 1];
19823 contents[ptr + 1] = contents[ptr + 2];
19824 contents[ptr + 2] = tmp;
19825 ptr += 4;
19826 }
c7b8f16e 19827 break;
e489d0ae 19828
c7b8f16e
JB		 19829 case 't':
19830 /* Byte swap code halfwords. */
19831 while (ptr + 1 < end)
99059e56
RM		 19832 {
19833 tmp = contents[ptr];
19834 contents[ptr] = contents[ptr + 1];
19835 contents[ptr + 1] = tmp;
19836 ptr += 2;
19837 }
c7b8f16e
JB		 19838 break;
19839
19840 case 'd':
19841 /* Leave data alone. */
19842 break;
19843 }
99059e56
RM		 19844 ptr = end;
19845 }
e489d0ae 19846 }
8e3de13a 19847
93204d3a 19848 free (map);
47b2e99c 19849 arm_data->mapcount = -1;
c7b8f16e 19850 arm_data->mapsize = 0;
8e3de13a 19851 arm_data->map = NULL;
8e3de13a 19852
e489d0ae
PB		 19853 return FALSE;
19854}
19855
0beaef2b
PB		 19856/* Mangle thumb function symbols as we read them in. */
19857
8384fb8f 19858static bfd_boolean
0beaef2b
PB		 19859elf32_arm_swap_symbol_in (bfd * abfd,
19860 const void *psrc,
19861 const void *pshn,
19862 Elf_Internal_Sym *dst)
19863{
8384fb8f
AM		 19864 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19865 return FALSE;
39d911fc 19866 dst->st_target_internal = 0;
0beaef2b
PB		 19867
19868 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 19869 the address. */
63e1a0fc
PB		 19870 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19871 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 19872 {
63e1a0fc
PB		 19873 if (dst->st_value & 1)
19874 {
19875 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 19876 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19877 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 19878 }
19879 else
39d911fc 19880 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 19881 }
19882 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19883 {
19884 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 19885 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 19886 }
35fc36a8 19887 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 19888 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 19889 else
39d911fc 19890 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 19891
8384fb8f 19892 return TRUE;
0beaef2b
PB		 19893}
19894
19895
19896/* Mangle thumb function symbols as we write them out. */
19897
19898static void
19899elf32_arm_swap_symbol_out (bfd *abfd,
19900 const Elf_Internal_Sym *src,
19901 void *cdst,
19902 void *shndx)
19903{
19904 Elf_Internal_Sym newsym;
19905
19906 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19907 of the address set, as per the new EABI. We do this unconditionally
19908 because objcopy does not set the elf header flags until after
19909 it writes out the symbol table. */
39d911fc 19910 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 19911 {
19912 newsym = *src;
34e77a92
RS		 19913 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19914 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 19915 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 19916 {
19917 /* Do this only for defined symbols. At link type, the static
19918 linker will simulate the work of dynamic linker of resolving
19919 symbols and will carry over the thumbness of found symbols to
19920 the output symbol table. It's not clear how it happens, but
19921 the thumbness of undefined symbols can well be different at
19922 runtime, and writing '1' for them will be confusing for users
19923 and possibly for dynamic linker itself.
19924 */
19925 newsym.st_value |= 1;
19926 }
906e58ca 19927
0beaef2b
PB		 19928 src = &newsym;
19929 }
19930 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
19931}
19932
b294bdf8
MM		 19933/* Add the PT_ARM_EXIDX program header. */
19934
19935static bfd_boolean
906e58ca 19936elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 19937 struct bfd_link_info *info ATTRIBUTE_UNUSED)
19938{
19939 struct elf_segment_map *m;
19940 asection *sec;
19941
19942 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19943 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19944 {
19945 /* If there is already a PT_ARM_EXIDX header, then we do not
19946 want to add another one. This situation arises when running
19947 "strip"; the input binary already has the header. */
12bd6957 19948 m = elf_seg_map (abfd);
b294bdf8
MM		 19949 while (m && m->p_type != PT_ARM_EXIDX)
19950 m = m->next;
19951 if (!m)
19952 {
21d799b5 19953 m = (struct elf_segment_map *)
99059e56 19954 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 19955 if (m == NULL)
19956 return FALSE;
19957 m->p_type = PT_ARM_EXIDX;
19958 m->count = 1;
19959 m->sections[0] = sec;
19960
12bd6957
AM		 19961 m->next = elf_seg_map (abfd);
19962 elf_seg_map (abfd) = m;
b294bdf8
MM		 19963 }
19964 }
19965
19966 return TRUE;
19967}
19968
19969/* We may add a PT_ARM_EXIDX program header. */
19970
19971static int
a6b96beb
AM		 19972elf32_arm_additional_program_headers (bfd *abfd,
19973 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 19974{
19975 asection *sec;
19976
19977 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19978 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19979 return 1;
19980 else
19981 return 0;
19982}
19983
34e77a92
RS		 19984/* Hook called by the linker routine which adds symbols from an object
19985 file. */
19986
19987static bfd_boolean
19988elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
19989 Elf_Internal_Sym *sym, const char **namep,
19990 flagword *flagsp, asection **secp, bfd_vma *valp)
19991{
c792917c
NC		 19992 if (elf32_arm_hash_table (info) == NULL)
19993 return FALSE;
19994
34e77a92
RS		 19995 if (elf32_arm_hash_table (info)->vxworks_p
19996 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
19997 flagsp, secp, valp))
19998 return FALSE;
19999
20000 return TRUE;
20001}
20002
0beaef2b 20003/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 20004const struct elf_size_info elf32_arm_size_info =
20005{
0beaef2b
PB		 20006 sizeof (Elf32_External_Ehdr),
20007 sizeof (Elf32_External_Phdr),
20008 sizeof (Elf32_External_Shdr),
20009 sizeof (Elf32_External_Rel),
20010 sizeof (Elf32_External_Rela),
20011 sizeof (Elf32_External_Sym),
20012 sizeof (Elf32_External_Dyn),
20013 sizeof (Elf_External_Note),
20014 4,
20015 1,
20016 32, 2,
20017 ELFCLASS32, EV_CURRENT,
20018 bfd_elf32_write_out_phdrs,
20019 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 20020 bfd_elf32_checksum_contents,
0beaef2b
PB		 20021 bfd_elf32_write_relocs,
20022 elf32_arm_swap_symbol_in,
20023 elf32_arm_swap_symbol_out,
20024 bfd_elf32_slurp_reloc_table,
20025 bfd_elf32_slurp_symbol_table,
20026 bfd_elf32_swap_dyn_in,
20027 bfd_elf32_swap_dyn_out,
20028 bfd_elf32_swap_reloc_in,
20029 bfd_elf32_swap_reloc_out,
20030 bfd_elf32_swap_reloca_in,
20031 bfd_elf32_swap_reloca_out
20032};
20033
685e70ae
VK		 20034static bfd_vma
20035read_code32 (const bfd *abfd, const bfd_byte *addr)
20036{
20037 /* V7 BE8 code is always little endian. */
20038 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20039 return bfd_getl32 (addr);
20040
20041 return bfd_get_32 (abfd, addr);
20042}
20043
20044static bfd_vma
20045read_code16 (const bfd *abfd, const bfd_byte *addr)
20046{
20047 /* V7 BE8 code is always little endian. */
20048 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20049 return bfd_getl16 (addr);
20050
20051 return bfd_get_16 (abfd, addr);
20052}
20053
6a631e86
YG		 20054/* Return size of plt0 entry starting at ADDR
20055 or (bfd_vma) -1 if size can not be determined. */
20056
20057static bfd_vma
20058elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
20059{
20060 bfd_vma first_word;
20061 bfd_vma plt0_size;
20062
685e70ae 20063 first_word = read_code32 (abfd, addr);
6a631e86
YG		 20064
20065 if (first_word == elf32_arm_plt0_entry[0])
20066 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
20067 else if (first_word == elf32_thumb2_plt0_entry[0])
20068 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
20069 else
20070 /* We don't yet handle this PLT format. */
20071 return (bfd_vma) -1;
20072
20073 return plt0_size;
20074}
20075
20076/* Return size of plt entry starting at offset OFFSET
20077 of plt section located at address START
20078 or (bfd_vma) -1 if size can not be determined. */
20079
20080static bfd_vma
20081elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
20082{
20083 bfd_vma first_insn;
20084 bfd_vma plt_size = 0;
20085 const bfd_byte *addr = start + offset;
20086
20087 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 20088 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 20089 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
20090
20091 /* Respect Thumb stub if necessary. */
685e70ae 20092 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 20093 {
20094 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
20095 }
20096
20097 /* Strip immediate from first add. */
685e70ae 20098 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 20099
20100#ifdef FOUR_WORD_PLT
20101 if (first_insn == elf32_arm_plt_entry[0])
20102 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
20103#else
20104 if (first_insn == elf32_arm_plt_entry_long[0])
20105 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
20106 else if (first_insn == elf32_arm_plt_entry_short[0])
20107 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
20108#endif
20109 else
20110 /* We don't yet handle this PLT format. */
20111 return (bfd_vma) -1;
20112
20113 return plt_size;
20114}
20115
20116/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
20117
20118static long
20119elf32_arm_get_synthetic_symtab (bfd *abfd,
20120 long symcount ATTRIBUTE_UNUSED,
20121 asymbol **syms ATTRIBUTE_UNUSED,
20122 long dynsymcount,
20123 asymbol **dynsyms,
20124 asymbol **ret)
20125{
20126 asection *relplt;
20127 asymbol *s;
20128 arelent *p;
20129 long count, i, n;
20130 size_t size;
20131 Elf_Internal_Shdr *hdr;
20132 char *names;
20133 asection *plt;
20134 bfd_vma offset;
20135 bfd_byte *data;
20136
20137 *ret = NULL;
20138
20139 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
20140 return 0;
20141
20142 if (dynsymcount <= 0)
20143 return 0;
20144
20145 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
20146 if (relplt == NULL)
20147 return 0;
20148
20149 hdr = &elf_section_data (relplt)->this_hdr;
20150 if (hdr->sh_link != elf_dynsymtab (abfd)
20151 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
20152 return 0;
20153
20154 plt = bfd_get_section_by_name (abfd, ".plt");
20155 if (plt == NULL)
20156 return 0;
20157
20158 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
20159 return -1;
20160
20161 data = plt->contents;
20162 if (data == NULL)
20163 {
20164 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
20165 return -1;
20166 bfd_cache_section_contents((asection *) plt, data);
20167 }
20168
20169 count = relplt->size / hdr->sh_entsize;
20170 size = count * sizeof (asymbol);
20171 p = relplt->relocation;
20172 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20173 {
20174 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
20175 if (p->addend != 0)
20176 size += sizeof ("+0x") - 1 + 8;
20177 }
20178
20179 s = *ret = (asymbol *) bfd_malloc (size);
20180 if (s == NULL)
20181 return -1;
20182
20183 offset = elf32_arm_plt0_size (abfd, data);
20184 if (offset == (bfd_vma) -1)
20185 return -1;
20186
20187 names = (char *) (s + count);
20188 p = relplt->relocation;
20189 n = 0;
20190 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20191 {
20192 size_t len;
20193
20194 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
20195 if (plt_size == (bfd_vma) -1)
20196 break;
20197
20198 *s = **p->sym_ptr_ptr;
20199 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20200 we are defining a symbol, ensure one of them is set. */
20201 if ((s->flags & BSF_LOCAL) == 0)
20202 s->flags |= BSF_GLOBAL;
20203 s->flags |= BSF_SYNTHETIC;
20204 s->section = plt;
20205 s->value = offset;
20206 s->name = names;
20207 s->udata.p = NULL;
20208 len = strlen ((*p->sym_ptr_ptr)->name);
20209 memcpy (names, (*p->sym_ptr_ptr)->name, len);
20210 names += len;
20211 if (p->addend != 0)
20212 {
20213 char buf[30], *a;
20214
20215 memcpy (names, "+0x", sizeof ("+0x") - 1);
20216 names += sizeof ("+0x") - 1;
20217 bfd_sprintf_vma (abfd, buf, p->addend);
20218 for (a = buf; *a == '0'; ++a)
20219 ;
20220 len = strlen (a);
20221 memcpy (names, a, len);
20222 names += len;
20223 }
20224 memcpy (names, "@plt", sizeof ("@plt"));
20225 names += sizeof ("@plt");
20226 ++s, ++n;
20227 offset += plt_size;
20228 }
20229
20230 return n;
20231}
20232
ac4c9b04
MG		 20233static bfd_boolean
20234elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
20235{
f0728ee3
AV		 20236 if (hdr->sh_flags & SHF_ARM_PURECODE)
20237 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 20238 return TRUE;
20239}
20240
20241static flagword
20242elf32_arm_lookup_section_flags (char *flag_name)
20243{
f0728ee3
AV		 20244 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
20245 return SHF_ARM_PURECODE;
ac4c9b04
MG		 20246
20247 return SEC_NO_FLAGS;
20248}
20249
491d01d3
YU		 20250static unsigned int
20251elf32_arm_count_additional_relocs (asection *sec)
20252{
20253 struct _arm_elf_section_data *arm_data;
20254 arm_data = get_arm_elf_section_data (sec);
5025eb7c 20255
6342be70 20256 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 20257}
20258
5522f910 20259/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 20260 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 20261 FALSE otherwise. ISECTION is the best guess matching section from the
20262 input bfd IBFD, but it might be NULL. */
20263
20264static bfd_boolean
20265elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20266 bfd *obfd ATTRIBUTE_UNUSED,
20267 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20268 Elf_Internal_Shdr *osection)
20269{
20270 switch (osection->sh_type)
20271 {
20272 case SHT_ARM_EXIDX:
20273 {
20274 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20275 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20276 unsigned i = 0;
20277
20278 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20279 osection->sh_info = 0;
20280
20281 /* The sh_link field must be set to the text section associated with
20282 this index section. Unfortunately the ARM EHABI does not specify
20283 exactly how to determine this association. Our caller does try
20284 to match up OSECTION with its corresponding input section however
20285 so that is a good first guess. */
20286 if (isection != NULL
20287 && osection->bfd_section != NULL
20288 && isection->bfd_section != NULL
20289 && isection->bfd_section->output_section != NULL
20290 && isection->bfd_section->output_section == osection->bfd_section
20291 && iheaders != NULL
20292 && isection->sh_link > 0
20293 && isection->sh_link < elf_numsections (ibfd)
20294 && iheaders[isection->sh_link]->bfd_section != NULL
20295 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20296 )
20297 {
20298 for (i = elf_numsections (obfd); i-- > 0;)
20299 if (oheaders[i]->bfd_section
20300 == iheaders[isection->sh_link]->bfd_section->output_section)
20301 break;
20302 }
9eaff861 20303
5522f910
NC		 20304 if (i == 0)
20305 {
20306 /* Failing that we have to find a matching section ourselves. If
20307 we had the output section name available we could compare that
20308 with input section names. Unfortunately we don't. So instead
20309 we use a simple heuristic and look for the nearest executable
20310 section before this one. */
20311 for (i = elf_numsections (obfd); i-- > 0;)
20312 if (oheaders[i] == osection)
20313 break;
20314 if (i == 0)
20315 break;
20316
20317 while (i-- > 0)
20318 if (oheaders[i]->sh_type == SHT_PROGBITS
20319 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20320 == (SHF_ALLOC | SHF_EXECINSTR))
20321 break;
20322 }
20323
20324 if (i)
20325 {
20326 osection->sh_link = i;
20327 /* If the text section was part of a group
20328 then the index section should be too. */
20329 if (oheaders[i]->sh_flags & SHF_GROUP)
20330 osection->sh_flags |= SHF_GROUP;
20331 return TRUE;
20332 }
20333 }
20334 break;
20335
20336 case SHT_ARM_PREEMPTMAP:
20337 osection->sh_flags = SHF_ALLOC;
20338 break;
20339
20340 case SHT_ARM_ATTRIBUTES:
20341 case SHT_ARM_DEBUGOVERLAY:
20342 case SHT_ARM_OVERLAYSECTION:
20343 default:
20344 break;
20345 }
20346
20347 return FALSE;
20348}
20349
d691934d
NC		 20350/* Returns TRUE if NAME is an ARM mapping symbol.
20351 Traditionally the symbols $a, $d and $t have been used.
20352 The ARM ELF standard also defines $x (for A64 code). It also allows a
20353 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20354 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20355 not support them here. $t.x indicates the start of ThumbEE instructions. */
20356
20357static bfd_boolean
20358is_arm_mapping_symbol (const char * name)
20359{
20360 return name != NULL /* Paranoia. */
20361 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20362 the mapping symbols could have acquired a prefix.
20363 We do not support this here, since such symbols no
20364 longer conform to the ARM ELF ABI. */
20365 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20366 && (name[2] == 0 || name[2] == '.');
20367 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20368 any characters that follow the period are legal characters for the body
20369 of a symbol's name. For now we just assume that this is the case. */
20370}
20371
fca2a38f
NC		 20372/* Make sure that mapping symbols in object files are not removed via the
20373 "strip --strip-unneeded" tool. These symbols are needed in order to
20374 correctly generate interworking veneers, and for byte swapping code
20375 regions. Once an object file has been linked, it is safe to remove the
20376 symbols as they will no longer be needed. */
20377
20378static void
20379elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20380{
20381 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 20382 && sym->section != bfd_abs_section_ptr
d691934d 20383 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 20384 sym->flags |= BSF_KEEP;
20385}
20386
5522f910
NC		 20387#undef elf_backend_copy_special_section_fields
20388#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20389
252b5132 20390#define ELF_ARCH bfd_arch_arm
ae95ffa6 20391#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 20392#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 20393#ifdef __QNXTARGET__
20394#define ELF_MAXPAGESIZE 0x1000
20395#else
7572ca89 20396#define ELF_MAXPAGESIZE 0x10000
d0facd1b 20397#endif
b1342370 20398#define ELF_MINPAGESIZE 0x1000
24718e3b 20399#define ELF_COMMONPAGESIZE 0x1000
252b5132 20400
07d6d2b8 20401#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 20402
99e4ae17
AJ		 20403#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20404#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 20405#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20406#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 20407#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 20408#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 20409#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8 20410#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 20411#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 20412#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 20413#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 20414#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 20415
07d6d2b8 20416#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
e7679060 20417#define elf_backend_maybe_function_sym elf32_arm_maybe_function_sym
07d6d2b8 20418#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 20419#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 20420#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 20421#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 20422#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 20423#define elf_backend_write_section elf32_arm_write_section
252b5132 20424#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 20425#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 20426#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20427#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20428#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 20429#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 20430#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ed7e9d0b 20431#define elf_backend_init_file_header elf32_arm_init_file_header
99e4ae17 20432#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 20433#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 20434#define elf_backend_fake_sections elf32_arm_fake_sections
20435#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20436#define elf_backend_final_write_processing elf32_arm_final_write_processing
20437#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 20438#define elf_backend_size_info elf32_arm_size_info
b294bdf8 20439#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 20440#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20441#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 20442#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 20443#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 20444#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 20445#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 20446#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 20447
20448#define elf_backend_can_refcount 1
20449#define elf_backend_can_gc_sections 1
20450#define elf_backend_plt_readonly 1
20451#define elf_backend_want_got_plt 1
20452#define elf_backend_want_plt_sym 0
5474d94f 20453#define elf_backend_want_dynrelro 1
906e58ca
NC		 20454#define elf_backend_may_use_rel_p 1
20455#define elf_backend_may_use_rela_p 0
4e7fd91e 20456#define elf_backend_default_use_rela_p 0
64f52338 20457#define elf_backend_dtrel_excludes_plt 1
252b5132 20458
04f7c78d 20459#define elf_backend_got_header_size 12
b68a20d6 20460#define elf_backend_extern_protected_data 1
04f7c78d 20461
07d6d2b8 20462#undef elf_backend_obj_attrs_vendor
906e58ca 20463#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 20464#undef elf_backend_obj_attrs_section
906e58ca 20465#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 20466#undef elf_backend_obj_attrs_arg_type
906e58ca 20467#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 20468#undef elf_backend_obj_attrs_section_type
104d59d1 20469#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 20470#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 20471#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 20472
07d6d2b8 20473#undef elf_backend_section_flags
ac4c9b04 20474#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 20475#undef elf_backend_lookup_section_flags_hook
20476#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 20477
a2f63b2e
MR		 20478#define elf_backend_linux_prpsinfo32_ugid16 TRUE
20479
252b5132 20480#include "elf32-target.h"
7f266840 20481
b38cadfb
NC		 20482/* Native Client targets. */
20483
20484#undef TARGET_LITTLE_SYM
6d00b590 20485#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 20486#undef TARGET_LITTLE_NAME
20487#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20488#undef TARGET_BIG_SYM
6d00b590 20489#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 20490#undef TARGET_BIG_NAME
20491#define TARGET_BIG_NAME "elf32-bigarm-nacl"
20492
20493/* Like elf32_arm_link_hash_table_create -- but overrides
20494 appropriately for NaCl. */
20495
20496static struct bfd_link_hash_table *
20497elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20498{
20499 struct bfd_link_hash_table *ret;
20500
20501 ret = elf32_arm_link_hash_table_create (abfd);
20502 if (ret)
20503 {
20504 struct elf32_arm_link_hash_table *htab
20505 = (struct elf32_arm_link_hash_table *) ret;
20506
20507 htab->nacl_p = 1;
20508
20509 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20510 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20511 }
20512 return ret;
20513}
20514
20515/* Since NaCl doesn't use the ARM-specific unwind format, we don't
20516 really need to use elf32_arm_modify_segment_map. But we do it
20517 anyway just to reduce gratuitous differences with the stock ARM backend. */
20518
20519static bfd_boolean
20520elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20521{
20522 return (elf32_arm_modify_segment_map (abfd, info)
20523 && nacl_modify_segment_map (abfd, info));
20524}
20525
cc364be6
AM		 20526static bfd_boolean
20527elf32_arm_nacl_final_write_processing (bfd *abfd)
887badb3 20528{
cc364be6
AM		 20529 arm_final_write_processing (abfd);
20530 return nacl_final_write_processing (abfd);
887badb3
RM		 20531}
20532
6a631e86
YG		 20533static bfd_vma
20534elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20535 const arelent *rel ATTRIBUTE_UNUSED)
20536{
20537 return plt->vma
20538 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20539 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20540}
887badb3 20541
b38cadfb 20542#undef elf32_bed
6a631e86 20543#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 20544#undef bfd_elf32_bfd_link_hash_table_create
20545#define bfd_elf32_bfd_link_hash_table_create \
20546 elf32_arm_nacl_link_hash_table_create
20547#undef elf_backend_plt_alignment
6a631e86 20548#define elf_backend_plt_alignment 4
b38cadfb
NC		 20549#undef elf_backend_modify_segment_map
20550#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
6d6c25c8
AM		 20551#undef elf_backend_modify_headers
20552#define elf_backend_modify_headers nacl_modify_headers
887badb3
RM		 20553#undef elf_backend_final_write_processing
20554#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 20555#undef bfd_elf32_get_synthetic_symtab
20556#undef elf_backend_plt_sym_val
20557#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 20558#undef elf_backend_copy_special_section_fields
b38cadfb 20559
887badb3
RM		 20560#undef ELF_MINPAGESIZE
20561#undef ELF_COMMONPAGESIZE
20562
b38cadfb
NC		 20563
20564#include "elf32-target.h"
20565
20566/* Reset to defaults. */
20567#undef elf_backend_plt_alignment
20568#undef elf_backend_modify_segment_map
20569#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
6d6c25c8 20570#undef elf_backend_modify_headers
887badb3
RM		 20571#undef elf_backend_final_write_processing
20572#define elf_backend_final_write_processing elf32_arm_final_write_processing
20573#undef ELF_MINPAGESIZE
20574#define ELF_MINPAGESIZE 0x1000
20575#undef ELF_COMMONPAGESIZE
20576#define ELF_COMMONPAGESIZE 0x1000
20577
b38cadfb 20578
617a5ada
CL		 20579/* FDPIC Targets. */
20580
20581#undef TARGET_LITTLE_SYM
20582#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20583#undef TARGET_LITTLE_NAME
20584#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20585#undef TARGET_BIG_SYM
20586#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20587#undef TARGET_BIG_NAME
20588#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20589#undef elf_match_priority
20590#define elf_match_priority 128
18a20338
CL		 20591#undef ELF_OSABI
20592#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 20593
20594/* Like elf32_arm_link_hash_table_create -- but overrides
20595 appropriately for FDPIC. */
20596
20597static struct bfd_link_hash_table *
20598elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20599{
20600 struct bfd_link_hash_table *ret;
20601
20602 ret = elf32_arm_link_hash_table_create (abfd);
20603 if (ret)
20604 {
20605 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20606
20607 htab->fdpic_p = 1;
20608 }
20609 return ret;
20610}
20611
e8b09b87
CL		 20612/* We need dynamic symbols for every section, since segments can
20613 relocate independently. */
20614static bfd_boolean
20615elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20616 struct bfd_link_info *info
20617 ATTRIBUTE_UNUSED,
20618 asection *p ATTRIBUTE_UNUSED)
20619{
20620 switch (elf_section_data (p)->this_hdr.sh_type)
20621 {
20622 case SHT_PROGBITS:
20623 case SHT_NOBITS:
20624 /* If sh_type is yet undecided, assume it could be
20625 SHT_PROGBITS/SHT_NOBITS. */
20626 case SHT_NULL:
20627 return FALSE;
20628
20629 /* There shouldn't be section relative relocations
20630 against any other section. */
20631 default:
20632 return TRUE;
20633 }
20634}
20635
617a5ada
CL		 20636#undef elf32_bed
20637#define elf32_bed elf32_arm_fdpic_bed
20638
20639#undef bfd_elf32_bfd_link_hash_table_create
4b24dd1a 20640#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
617a5ada 20641
e8b09b87
CL		 20642#undef elf_backend_omit_section_dynsym
20643#define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20644
617a5ada 20645#include "elf32-target.h"
e8b09b87 20646
617a5ada 20647#undef elf_match_priority
18a20338 20648#undef ELF_OSABI
e8b09b87 20649#undef elf_backend_omit_section_dynsym
617a5ada 20650
906e58ca 20651/* VxWorks Targets. */
4e7fd91e 20652
07d6d2b8
AM		 20653#undef TARGET_LITTLE_SYM
20654#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20655#undef TARGET_LITTLE_NAME
20656#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20657#undef TARGET_BIG_SYM
20658#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20659#undef TARGET_BIG_NAME
20660#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 20661
20662/* Like elf32_arm_link_hash_table_create -- but overrides
20663 appropriately for VxWorks. */
906e58ca 20664
4e7fd91e
PB		 20665static struct bfd_link_hash_table *
20666elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20667{
20668 struct bfd_link_hash_table *ret;
20669
20670 ret = elf32_arm_link_hash_table_create (abfd);
20671 if (ret)
20672 {
20673 struct elf32_arm_link_hash_table *htab
00a97672 20674 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 20675 htab->use_rel = 0;
00a97672 20676 htab->vxworks_p = 1;
4e7fd91e
PB		 20677 }
20678 return ret;
906e58ca 20679}
4e7fd91e 20680
cc364be6
AM		 20681static bfd_boolean
20682elf32_arm_vxworks_final_write_processing (bfd *abfd)
00a97672 20683{
cc364be6
AM		 20684 arm_final_write_processing (abfd);
20685 return elf_vxworks_final_write_processing (abfd);
00a97672
RS		 20686}
20687
906e58ca 20688#undef elf32_bed
4e7fd91e
PB		 20689#define elf32_bed elf32_arm_vxworks_bed
20690
906e58ca
NC		 20691#undef bfd_elf32_bfd_link_hash_table_create
20692#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 20693#undef elf_backend_final_write_processing
20694#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20695#undef elf_backend_emit_relocs
9eaff861 20696#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 20697
906e58ca 20698#undef elf_backend_may_use_rel_p
00a97672 20699#define elf_backend_may_use_rel_p 0
906e58ca 20700#undef elf_backend_may_use_rela_p
00a97672 20701#define elf_backend_may_use_rela_p 1
906e58ca 20702#undef elf_backend_default_use_rela_p
00a97672 20703#define elf_backend_default_use_rela_p 1
906e58ca 20704#undef elf_backend_want_plt_sym
00a97672 20705#define elf_backend_want_plt_sym 1
906e58ca 20706#undef ELF_MAXPAGESIZE
00a97672 20707#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 20708
20709#include "elf32-target.h"
20710
20711
21d799b5
NC		 20712/* Merge backend specific data from an object file to the output
20713 object file when linking. */
20714
20715static bfd_boolean
50e03d47 20716elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 20717{
50e03d47 20718 bfd *obfd = info->output_bfd;
21d799b5
NC		 20719 flagword out_flags;
20720 flagword in_flags;
20721 bfd_boolean flags_compatible = TRUE;
20722 asection *sec;
20723
cc643b88 20724 /* Check if we have the same endianness. */
50e03d47 20725 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 20726 return FALSE;
20727
20728 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20729 return TRUE;
20730
50e03d47 20731 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 20732 return FALSE;
20733
20734 /* The input BFD must have had its flags initialised. */
20735 /* The following seems bogus to me -- The flags are initialized in
20736 the assembler but I don't think an elf_flags_init field is
20737 written into the object. */
20738 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20739
20740 in_flags = elf_elfheader (ibfd)->e_flags;
20741 out_flags = elf_elfheader (obfd)->e_flags;
20742
20743 /* In theory there is no reason why we couldn't handle this. However
20744 in practice it isn't even close to working and there is no real
20745 reason to want it. */
20746 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20747 && !(ibfd->flags & DYNAMIC)
20748 && (in_flags & EF_ARM_BE8))
20749 {
871b3ab2 20750 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 20751 ibfd);
20752 return FALSE;
20753 }
20754
20755 if (!elf_flags_init (obfd))
20756 {
20757 /* If the input is the default architecture and had the default
20758 flags then do not bother setting the flags for the output
20759 architecture, instead allow future merges to do this. If no
20760 future merges ever set these flags then they will retain their
99059e56
RM		 20761 uninitialised values, which surprise surprise, correspond
20762 to the default values. */
21d799b5
NC		 20763 if (bfd_get_arch_info (ibfd)->the_default
20764 && elf_elfheader (ibfd)->e_flags == 0)
20765 return TRUE;
20766
20767 elf_flags_init (obfd) = TRUE;
20768 elf_elfheader (obfd)->e_flags = in_flags;
20769
20770 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20771 && bfd_get_arch_info (obfd)->the_default)
20772 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20773
20774 return TRUE;
20775 }
20776
20777 /* Determine what should happen if the input ARM architecture
20778 does not match the output ARM architecture. */
20779 if (! bfd_arm_merge_machines (ibfd, obfd))
20780 return FALSE;
20781
20782 /* Identical flags must be compatible. */
20783 if (in_flags == out_flags)
20784 return TRUE;
20785
20786 /* Check to see if the input BFD actually contains any sections. If
20787 not, its flags may not have been initialised either, but it
20788 cannot actually cause any incompatiblity. Do not short-circuit
20789 dynamic objects; their section list may be emptied by
20790 elf_link_add_object_symbols.
20791
20792 Also check to see if there are no code sections in the input.
20793 In this case there is no need to check for code specific flags.
20794 XXX - do we need to worry about floating-point format compatability
20795 in data sections ? */
20796 if (!(ibfd->flags & DYNAMIC))
20797 {
20798 bfd_boolean null_input_bfd = TRUE;
20799 bfd_boolean only_data_sections = TRUE;
20800
20801 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20802 {
20803 /* Ignore synthetic glue sections. */
20804 if (strcmp (sec->name, ".glue_7")
20805 && strcmp (sec->name, ".glue_7t"))
20806 {
fd361982 20807 if ((bfd_section_flags (sec)
21d799b5
NC		 20808 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20809 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 20810 only_data_sections = FALSE;
21d799b5
NC		 20811
20812 null_input_bfd = FALSE;
20813 break;
20814 }
20815 }
20816
20817 if (null_input_bfd || only_data_sections)
20818 return TRUE;
20819 }
20820
20821 /* Complain about various flag mismatches. */
20822 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20823 EF_ARM_EABI_VERSION (out_flags)))
20824 {
20825 _bfd_error_handler
90b6238f 20826 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 20827 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20828 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 20829 return FALSE;
20830 }
20831
20832 /* Not sure what needs to be checked for EABI versions >= 1. */
20833 /* VxWorks libraries do not use these flags. */
20834 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20835 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20836 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20837 {
20838 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20839 {
20840 _bfd_error_handler
871b3ab2 20841 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 20842 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20843 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 20844 flags_compatible = FALSE;
20845 }
20846
20847 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20848 {
20849 if (in_flags & EF_ARM_APCS_FLOAT)
20850 _bfd_error_handler
871b3ab2 20851 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 20852 ibfd, obfd);
20853 else
20854 _bfd_error_handler
871b3ab2 20855 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 20856 ibfd, obfd);
20857
20858 flags_compatible = FALSE;
20859 }
20860
20861 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20862 {
20863 if (in_flags & EF_ARM_VFP_FLOAT)
20864 _bfd_error_handler
90b6238f
AM		 20865 (_("error: %pB uses %s instructions, whereas %pB does not"),
20866 ibfd, "VFP", obfd);
21d799b5
NC		 20867 else
20868 _bfd_error_handler
90b6238f
AM		 20869 (_("error: %pB uses %s instructions, whereas %pB does not"),
20870 ibfd, "FPA", obfd);
21d799b5
NC		 20871
20872 flags_compatible = FALSE;
20873 }
20874
20875 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20876 {
20877 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20878 _bfd_error_handler
90b6238f
AM		 20879 (_("error: %pB uses %s instructions, whereas %pB does not"),
20880 ibfd, "Maverick", obfd);
21d799b5
NC		 20881 else
20882 _bfd_error_handler
90b6238f
AM		 20883 (_("error: %pB does not use %s instructions, whereas %pB does"),
20884 ibfd, "Maverick", obfd);
21d799b5
NC		 20885
20886 flags_compatible = FALSE;
20887 }
20888
20889#ifdef EF_ARM_SOFT_FLOAT
20890 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20891 {
20892 /* We can allow interworking between code that is VFP format
20893 layout, and uses either soft float or integer regs for
20894 passing floating point arguments and results. We already
20895 know that the APCS_FLOAT flags match; similarly for VFP
20896 flags. */
20897 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20898 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20899 {
20900 if (in_flags & EF_ARM_SOFT_FLOAT)
20901 _bfd_error_handler
871b3ab2 20902 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 20903 ibfd, obfd);
20904 else
20905 _bfd_error_handler
871b3ab2 20906 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 20907 ibfd, obfd);
20908
20909 flags_compatible = FALSE;
20910 }
20911 }
20912#endif
20913
20914 /* Interworking mismatch is only a warning. */
20915 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
20916 {
20917 if (in_flags & EF_ARM_INTERWORK)
20918 {
20919 _bfd_error_handler
90b6238f 20920 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 20921 ibfd, obfd);
20922 }
20923 else
20924 {
20925 _bfd_error_handler
90b6238f 20926 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 20927 ibfd, obfd);
20928 }
20929 }
20930 }
20931
20932 return flags_compatible;
20933}
20934
20935
906e58ca 20936/* Symbian OS Targets. */
7f266840 20937
07d6d2b8
AM		 20938#undef TARGET_LITTLE_SYM
20939#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
20940#undef TARGET_LITTLE_NAME
20941#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
20942#undef TARGET_BIG_SYM
20943#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
20944#undef TARGET_BIG_NAME
20945#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 20946
20947/* Like elf32_arm_link_hash_table_create -- but overrides
20948 appropriately for Symbian OS. */
906e58ca 20949
7f266840
DJ		 20950static struct bfd_link_hash_table *
20951elf32_arm_symbian_link_hash_table_create (bfd *abfd)
20952{
20953 struct bfd_link_hash_table *ret;
20954
20955 ret = elf32_arm_link_hash_table_create (abfd);
20956 if (ret)
20957 {
20958 struct elf32_arm_link_hash_table *htab
20959 = (struct elf32_arm_link_hash_table *)ret;
20960 /* There is no PLT header for Symbian OS. */
20961 htab->plt_header_size = 0;
95720a86
DJ		 20962 /* The PLT entries are each one instruction and one word. */
20963 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 20964 htab->symbian_p = 1;
33bfe774
JB		 20965 /* Symbian uses armv5t or above, so use_blx is always true. */
20966 htab->use_blx = 1;
67687978 20967 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 20968 }
20969 return ret;
906e58ca 20970}
7f266840 20971
b35d266b 20972static const struct bfd_elf_special_section
551b43fd 20973elf32_arm_symbian_special_sections[] =
7f266840 20974{
5cd3778d
MM		 20975 /* In a BPABI executable, the dynamic linking sections do not go in
20976 the loadable read-only segment. The post-linker may wish to
20977 refer to these sections, but they are not part of the final
20978 program image. */
07d6d2b8
AM		 20979 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
20980 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
20981 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
20982 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
20983 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 20984 /* These sections do not need to be writable as the SymbianOS
20985 postlinker will arrange things so that no dynamic relocation is
20986 required. */
07d6d2b8
AM		 20987 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
20988 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 20989 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 20990 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 20991};
20992
c3c76620 20993static void
906e58ca 20994elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 20995 struct bfd_link_info *link_info)
c3c76620
MM		 20996{
20997 /* BPABI objects are never loaded directly by an OS kernel; they are
20998 processed by a postlinker first, into an OS-specific format. If
20999 the D_PAGED bit is set on the file, BFD will align segments on
21000 page boundaries, so that an OS can directly map the file. With
21001 BPABI objects, that just results in wasted space. In addition,
21002 because we clear the D_PAGED bit, map_sections_to_segments will
21003 recognize that the program headers should not be mapped into any
21004 loadable segment. */
21005 abfd->flags &= ~D_PAGED;
906e58ca 21006 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 21007}
7f266840
DJ		 21008
21009static bfd_boolean
906e58ca 21010elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 21011 struct bfd_link_info *info)
7f266840
DJ		 21012{
21013 struct elf_segment_map *m;
21014 asection *dynsec;
21015
7f266840
DJ		 21016 /* BPABI shared libraries and executables should have a PT_DYNAMIC
21017 segment. However, because the .dynamic section is not marked
21018 with SEC_LOAD, the generic ELF code will not create such a
21019 segment. */
21020 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
21021 if (dynsec)
21022 {
12bd6957 21023 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 21024 if (m->p_type == PT_DYNAMIC)
21025 break;
21026
21027 if (m == NULL)
21028 {
21029 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 21030 m->next = elf_seg_map (abfd);
21031 elf_seg_map (abfd) = m;
8ded5a0f 21032 }
7f266840
DJ		 21033 }
21034
b294bdf8
MM		 21035 /* Also call the generic arm routine. */
21036 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 21037}
21038
95720a86
DJ		 21039/* Return address for Ith PLT stub in section PLT, for relocation REL
21040 or (bfd_vma) -1 if it should not be included. */
21041
21042static bfd_vma
21043elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
21044 const arelent *rel ATTRIBUTE_UNUSED)
21045{
21046 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
21047}
21048
8029a119 21049#undef elf32_bed
7f266840
DJ		 21050#define elf32_bed elf32_arm_symbian_bed
21051
21052/* The dynamic sections are not allocated on SymbianOS; the postlinker
21053 will process them and then discard them. */
906e58ca 21054#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 21055#define ELF_DYNAMIC_SEC_FLAGS \
21056 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
21057
9eaff861 21058#undef elf_backend_emit_relocs
c3c76620 21059
906e58ca
NC		 21060#undef bfd_elf32_bfd_link_hash_table_create
21061#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
21062#undef elf_backend_special_sections
07d6d2b8 21063#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 21064#undef elf_backend_begin_write_processing
21065#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
21066#undef elf_backend_final_write_processing
21067#define elf_backend_final_write_processing elf32_arm_final_write_processing
21068
21069#undef elf_backend_modify_segment_map
7f266840
DJ		 21070#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
21071
21072/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 21073#undef elf_backend_got_header_size
7f266840
DJ		 21074#define elf_backend_got_header_size 0
21075
21076/* Similarly, there is no .got.plt section. */
906e58ca 21077#undef elf_backend_want_got_plt
7f266840
DJ		 21078#define elf_backend_want_got_plt 0
21079
906e58ca 21080#undef elf_backend_plt_sym_val
95720a86
DJ		 21081#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
21082
906e58ca 21083#undef elf_backend_may_use_rel_p
00a97672 21084#define elf_backend_may_use_rel_p 1
906e58ca 21085#undef elf_backend_may_use_rela_p
00a97672 21086#define elf_backend_may_use_rela_p 0
906e58ca 21087#undef elf_backend_default_use_rela_p
00a97672 21088#define elf_backend_default_use_rela_p 0
906e58ca 21089#undef elf_backend_want_plt_sym
00a97672 21090#define elf_backend_want_plt_sym 0
64f52338
AM		 21091#undef elf_backend_dtrel_excludes_plt
21092#define elf_backend_dtrel_excludes_plt 0
906e58ca 21093#undef ELF_MAXPAGESIZE
00a97672 21094#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 21095
7f266840 21096#include "elf32-target.h"
GDB Binutils - Deliverables
This page took 3.320621 seconds and 4 git commands to generate.