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Fix erroroneous use of '%zu' in elfcore_grok_win32pstatus
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
b3adc24a 2 Copyright (C) 1998-2020 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
00a97672 25#include "libiberty.h"
7f266840
DJ		 26#include "libbfd.h"
27#include "elf-bfd.h"
b38cadfb 28#include "elf-nacl.h"
00a97672 29#include "elf-vxworks.h"
ee065d83 30#include "elf/arm.h"
f37164d7
AM		 31#include "elf32-arm.h"
32#include "cpu-arm.h"
7f266840 33
00a97672
RS		 34/* Return the relocation section associated with NAME. HTAB is the
35 bfd's elf32_arm_link_hash_entry. */
36#define RELOC_SECTION(HTAB, NAME) \
37 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
38
39/* Return size of a relocation entry. HTAB is the bfd's
40 elf32_arm_link_hash_entry. */
41#define RELOC_SIZE(HTAB) \
42 ((HTAB)->use_rel \
43 ? sizeof (Elf32_External_Rel) \
44 : sizeof (Elf32_External_Rela))
45
46/* Return function to swap relocations in. HTAB is the bfd's
47 elf32_arm_link_hash_entry. */
48#define SWAP_RELOC_IN(HTAB) \
49 ((HTAB)->use_rel \
50 ? bfd_elf32_swap_reloc_in \
51 : bfd_elf32_swap_reloca_in)
52
53/* Return function to swap relocations out. HTAB is the bfd's
54 elf32_arm_link_hash_entry. */
55#define SWAP_RELOC_OUT(HTAB) \
56 ((HTAB)->use_rel \
57 ? bfd_elf32_swap_reloc_out \
58 : bfd_elf32_swap_reloca_out)
59
f3185997 60#define elf_info_to_howto NULL
07d6d2b8 61#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 62
63#define ARM_ELF_ABI_VERSION 0
64#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
65
79f08007
YZ		 66/* The Adjusted Place, as defined by AAELF. */
67#define Pa(X) ((X) & 0xfffffffc)
68
3e6b1042
DJ		 69static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
70 struct bfd_link_info *link_info,
71 asection *sec,
72 bfd_byte *contents);
73
7f266840
DJ		 74/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
75 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
76 in that slot. */
77
c19d1205 78static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 79{
8029a119 80 /* No relocation. */
7f266840
DJ		 81 HOWTO (R_ARM_NONE, /* type */
82 0, /* rightshift */
6346d5ca 83 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 84 0, /* bitsize */
85 FALSE, /* pc_relative */
86 0, /* bitpos */
87 complain_overflow_dont,/* complain_on_overflow */
88 bfd_elf_generic_reloc, /* special_function */
89 "R_ARM_NONE", /* name */
90 FALSE, /* partial_inplace */
91 0, /* src_mask */
92 0, /* dst_mask */
93 FALSE), /* pcrel_offset */
94
95 HOWTO (R_ARM_PC24, /* type */
96 2, /* rightshift */
97 2, /* size (0 = byte, 1 = short, 2 = long) */
98 24, /* bitsize */
99 TRUE, /* pc_relative */
100 0, /* bitpos */
101 complain_overflow_signed,/* complain_on_overflow */
102 bfd_elf_generic_reloc, /* special_function */
103 "R_ARM_PC24", /* name */
104 FALSE, /* partial_inplace */
105 0x00ffffff, /* src_mask */
106 0x00ffffff, /* dst_mask */
107 TRUE), /* pcrel_offset */
108
109 /* 32 bit absolute */
110 HOWTO (R_ARM_ABS32, /* type */
111 0, /* rightshift */
112 2, /* size (0 = byte, 1 = short, 2 = long) */
113 32, /* bitsize */
114 FALSE, /* pc_relative */
115 0, /* bitpos */
116 complain_overflow_bitfield,/* complain_on_overflow */
117 bfd_elf_generic_reloc, /* special_function */
118 "R_ARM_ABS32", /* name */
119 FALSE, /* partial_inplace */
120 0xffffffff, /* src_mask */
121 0xffffffff, /* dst_mask */
122 FALSE), /* pcrel_offset */
123
124 /* standard 32bit pc-relative reloc */
125 HOWTO (R_ARM_REL32, /* type */
126 0, /* rightshift */
127 2, /* size (0 = byte, 1 = short, 2 = long) */
128 32, /* bitsize */
129 TRUE, /* pc_relative */
130 0, /* bitpos */
131 complain_overflow_bitfield,/* complain_on_overflow */
132 bfd_elf_generic_reloc, /* special_function */
133 "R_ARM_REL32", /* name */
134 FALSE, /* partial_inplace */
135 0xffffffff, /* src_mask */
136 0xffffffff, /* dst_mask */
137 TRUE), /* pcrel_offset */
138
c19d1205 139 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 140 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 141 0, /* rightshift */
142 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 143 32, /* bitsize */
144 TRUE, /* pc_relative */
7f266840 145 0, /* bitpos */
4962c51a 146 complain_overflow_dont,/* complain_on_overflow */
7f266840 147 bfd_elf_generic_reloc, /* special_function */
4962c51a 148 "R_ARM_LDR_PC_G0", /* name */
7f266840 149 FALSE, /* partial_inplace */
4962c51a
MS		 150 0xffffffff, /* src_mask */
151 0xffffffff, /* dst_mask */
152 TRUE), /* pcrel_offset */
7f266840
DJ		 153
154 /* 16 bit absolute */
155 HOWTO (R_ARM_ABS16, /* type */
156 0, /* rightshift */
157 1, /* size (0 = byte, 1 = short, 2 = long) */
158 16, /* bitsize */
159 FALSE, /* pc_relative */
160 0, /* bitpos */
161 complain_overflow_bitfield,/* complain_on_overflow */
162 bfd_elf_generic_reloc, /* special_function */
163 "R_ARM_ABS16", /* name */
164 FALSE, /* partial_inplace */
165 0x0000ffff, /* src_mask */
166 0x0000ffff, /* dst_mask */
167 FALSE), /* pcrel_offset */
168
169 /* 12 bit absolute */
170 HOWTO (R_ARM_ABS12, /* type */
171 0, /* rightshift */
172 2, /* size (0 = byte, 1 = short, 2 = long) */
173 12, /* bitsize */
174 FALSE, /* pc_relative */
175 0, /* bitpos */
176 complain_overflow_bitfield,/* complain_on_overflow */
177 bfd_elf_generic_reloc, /* special_function */
178 "R_ARM_ABS12", /* name */
179 FALSE, /* partial_inplace */
00a97672
RS		 180 0x00000fff, /* src_mask */
181 0x00000fff, /* dst_mask */
7f266840
DJ		 182 FALSE), /* pcrel_offset */
183
184 HOWTO (R_ARM_THM_ABS5, /* type */
185 6, /* rightshift */
186 1, /* size (0 = byte, 1 = short, 2 = long) */
187 5, /* bitsize */
188 FALSE, /* pc_relative */
189 0, /* bitpos */
190 complain_overflow_bitfield,/* complain_on_overflow */
191 bfd_elf_generic_reloc, /* special_function */
192 "R_ARM_THM_ABS5", /* name */
193 FALSE, /* partial_inplace */
194 0x000007e0, /* src_mask */
195 0x000007e0, /* dst_mask */
196 FALSE), /* pcrel_offset */
197
198 /* 8 bit absolute */
199 HOWTO (R_ARM_ABS8, /* type */
200 0, /* rightshift */
201 0, /* size (0 = byte, 1 = short, 2 = long) */
202 8, /* bitsize */
203 FALSE, /* pc_relative */
204 0, /* bitpos */
205 complain_overflow_bitfield,/* complain_on_overflow */
206 bfd_elf_generic_reloc, /* special_function */
207 "R_ARM_ABS8", /* name */
208 FALSE, /* partial_inplace */
209 0x000000ff, /* src_mask */
210 0x000000ff, /* dst_mask */
211 FALSE), /* pcrel_offset */
212
213 HOWTO (R_ARM_SBREL32, /* type */
214 0, /* rightshift */
215 2, /* size (0 = byte, 1 = short, 2 = long) */
216 32, /* bitsize */
217 FALSE, /* pc_relative */
218 0, /* bitpos */
219 complain_overflow_dont,/* complain_on_overflow */
220 bfd_elf_generic_reloc, /* special_function */
221 "R_ARM_SBREL32", /* name */
222 FALSE, /* partial_inplace */
223 0xffffffff, /* src_mask */
224 0xffffffff, /* dst_mask */
225 FALSE), /* pcrel_offset */
226
c19d1205 227 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 228 1, /* rightshift */
229 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 230 24, /* bitsize */
7f266840
DJ		 231 TRUE, /* pc_relative */
232 0, /* bitpos */
233 complain_overflow_signed,/* complain_on_overflow */
234 bfd_elf_generic_reloc, /* special_function */
c19d1205 235 "R_ARM_THM_CALL", /* name */
7f266840 236 FALSE, /* partial_inplace */
7f6ab9f8
AM		 237 0x07ff2fff, /* src_mask */
238 0x07ff2fff, /* dst_mask */
7f266840
DJ		 239 TRUE), /* pcrel_offset */
240
07d6d2b8 241 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 242 1, /* rightshift */
243 1, /* size (0 = byte, 1 = short, 2 = long) */
244 8, /* bitsize */
245 TRUE, /* pc_relative */
246 0, /* bitpos */
247 complain_overflow_signed,/* complain_on_overflow */
248 bfd_elf_generic_reloc, /* special_function */
249 "R_ARM_THM_PC8", /* name */
250 FALSE, /* partial_inplace */
251 0x000000ff, /* src_mask */
252 0x000000ff, /* dst_mask */
253 TRUE), /* pcrel_offset */
254
c19d1205 255 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 256 1, /* rightshift */
257 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 258 32, /* bitsize */
259 FALSE, /* pc_relative */
7f266840
DJ		 260 0, /* bitpos */
261 complain_overflow_signed,/* complain_on_overflow */
262 bfd_elf_generic_reloc, /* special_function */
c19d1205 263 "R_ARM_BREL_ADJ", /* name */
7f266840 264 FALSE, /* partial_inplace */
c19d1205
ZW		 265 0xffffffff, /* src_mask */
266 0xffffffff, /* dst_mask */
267 FALSE), /* pcrel_offset */
7f266840 268
0855e32b 269 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 270 0, /* rightshift */
0855e32b
NS		 271 2, /* size (0 = byte, 1 = short, 2 = long) */
272 32, /* bitsize */
7f266840
DJ		 273 FALSE, /* pc_relative */
274 0, /* bitpos */
0855e32b 275 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 276 bfd_elf_generic_reloc, /* special_function */
0855e32b 277 "R_ARM_TLS_DESC", /* name */
7f266840 278 FALSE, /* partial_inplace */
0855e32b
NS		 279 0xffffffff, /* src_mask */
280 0xffffffff, /* dst_mask */
7f266840
DJ		 281 FALSE), /* pcrel_offset */
282
283 HOWTO (R_ARM_THM_SWI8, /* type */
284 0, /* rightshift */
285 0, /* size (0 = byte, 1 = short, 2 = long) */
286 0, /* bitsize */
287 FALSE, /* pc_relative */
288 0, /* bitpos */
289 complain_overflow_signed,/* complain_on_overflow */
290 bfd_elf_generic_reloc, /* special_function */
291 "R_ARM_SWI8", /* name */
292 FALSE, /* partial_inplace */
293 0x00000000, /* src_mask */
294 0x00000000, /* dst_mask */
295 FALSE), /* pcrel_offset */
296
297 /* BLX instruction for the ARM. */
298 HOWTO (R_ARM_XPC25, /* type */
299 2, /* rightshift */
300 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 301 24, /* bitsize */
7f266840
DJ		 302 TRUE, /* pc_relative */
303 0, /* bitpos */
304 complain_overflow_signed,/* complain_on_overflow */
305 bfd_elf_generic_reloc, /* special_function */
306 "R_ARM_XPC25", /* name */
307 FALSE, /* partial_inplace */
308 0x00ffffff, /* src_mask */
309 0x00ffffff, /* dst_mask */
310 TRUE), /* pcrel_offset */
311
312 /* BLX instruction for the Thumb. */
313 HOWTO (R_ARM_THM_XPC22, /* type */
314 2, /* rightshift */
315 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 316 24, /* bitsize */
7f266840
DJ		 317 TRUE, /* pc_relative */
318 0, /* bitpos */
319 complain_overflow_signed,/* complain_on_overflow */
320 bfd_elf_generic_reloc, /* special_function */
321 "R_ARM_THM_XPC22", /* name */
322 FALSE, /* partial_inplace */
7f6ab9f8
AM		 323 0x07ff2fff, /* src_mask */
324 0x07ff2fff, /* dst_mask */
7f266840
DJ		 325 TRUE), /* pcrel_offset */
326
ba93b8ac 327 /* Dynamic TLS relocations. */
7f266840 328
ba93b8ac 329 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 330 0, /* rightshift */
331 2, /* size (0 = byte, 1 = short, 2 = long) */
332 32, /* bitsize */
333 FALSE, /* pc_relative */
334 0, /* bitpos */
99059e56
RM		 335 complain_overflow_bitfield,/* complain_on_overflow */
336 bfd_elf_generic_reloc, /* special_function */
337 "R_ARM_TLS_DTPMOD32", /* name */
338 TRUE, /* partial_inplace */
339 0xffffffff, /* src_mask */
340 0xffffffff, /* dst_mask */
07d6d2b8 341 FALSE), /* pcrel_offset */
7f266840 342
ba93b8ac 343 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 344 0, /* rightshift */
345 2, /* size (0 = byte, 1 = short, 2 = long) */
346 32, /* bitsize */
347 FALSE, /* pc_relative */
348 0, /* bitpos */
99059e56
RM		 349 complain_overflow_bitfield,/* complain_on_overflow */
350 bfd_elf_generic_reloc, /* special_function */
351 "R_ARM_TLS_DTPOFF32", /* name */
352 TRUE, /* partial_inplace */
353 0xffffffff, /* src_mask */
354 0xffffffff, /* dst_mask */
07d6d2b8 355 FALSE), /* pcrel_offset */
7f266840 356
ba93b8ac 357 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 358 0, /* rightshift */
359 2, /* size (0 = byte, 1 = short, 2 = long) */
360 32, /* bitsize */
361 FALSE, /* pc_relative */
362 0, /* bitpos */
99059e56
RM		 363 complain_overflow_bitfield,/* complain_on_overflow */
364 bfd_elf_generic_reloc, /* special_function */
365 "R_ARM_TLS_TPOFF32", /* name */
366 TRUE, /* partial_inplace */
367 0xffffffff, /* src_mask */
368 0xffffffff, /* dst_mask */
07d6d2b8 369 FALSE), /* pcrel_offset */
7f266840
DJ		 370
371 /* Relocs used in ARM Linux */
372
373 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 374 0, /* rightshift */
375 2, /* size (0 = byte, 1 = short, 2 = long) */
376 32, /* bitsize */
377 FALSE, /* pc_relative */
378 0, /* bitpos */
99059e56
RM		 379 complain_overflow_bitfield,/* complain_on_overflow */
380 bfd_elf_generic_reloc, /* special_function */
381 "R_ARM_COPY", /* name */
382 TRUE, /* partial_inplace */
383 0xffffffff, /* src_mask */
384 0xffffffff, /* dst_mask */
07d6d2b8 385 FALSE), /* pcrel_offset */
7f266840
DJ		 386
387 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 388 0, /* rightshift */
389 2, /* size (0 = byte, 1 = short, 2 = long) */
390 32, /* bitsize */
391 FALSE, /* pc_relative */
392 0, /* bitpos */
99059e56
RM		 393 complain_overflow_bitfield,/* complain_on_overflow */
394 bfd_elf_generic_reloc, /* special_function */
395 "R_ARM_GLOB_DAT", /* name */
396 TRUE, /* partial_inplace */
397 0xffffffff, /* src_mask */
398 0xffffffff, /* dst_mask */
07d6d2b8 399 FALSE), /* pcrel_offset */
7f266840
DJ		 400
401 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 402 0, /* rightshift */
403 2, /* size (0 = byte, 1 = short, 2 = long) */
404 32, /* bitsize */
405 FALSE, /* pc_relative */
406 0, /* bitpos */
99059e56
RM		 407 complain_overflow_bitfield,/* complain_on_overflow */
408 bfd_elf_generic_reloc, /* special_function */
409 "R_ARM_JUMP_SLOT", /* name */
410 TRUE, /* partial_inplace */
411 0xffffffff, /* src_mask */
412 0xffffffff, /* dst_mask */
07d6d2b8 413 FALSE), /* pcrel_offset */
7f266840
DJ		 414
415 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 416 0, /* rightshift */
417 2, /* size (0 = byte, 1 = short, 2 = long) */
418 32, /* bitsize */
419 FALSE, /* pc_relative */
420 0, /* bitpos */
99059e56
RM		 421 complain_overflow_bitfield,/* complain_on_overflow */
422 bfd_elf_generic_reloc, /* special_function */
423 "R_ARM_RELATIVE", /* name */
424 TRUE, /* partial_inplace */
425 0xffffffff, /* src_mask */
426 0xffffffff, /* dst_mask */
07d6d2b8 427 FALSE), /* pcrel_offset */
7f266840 428
c19d1205 429 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 430 0, /* rightshift */
431 2, /* size (0 = byte, 1 = short, 2 = long) */
432 32, /* bitsize */
433 FALSE, /* pc_relative */
434 0, /* bitpos */
99059e56
RM		 435 complain_overflow_bitfield,/* complain_on_overflow */
436 bfd_elf_generic_reloc, /* special_function */
437 "R_ARM_GOTOFF32", /* name */
438 TRUE, /* partial_inplace */
439 0xffffffff, /* src_mask */
440 0xffffffff, /* dst_mask */
07d6d2b8 441 FALSE), /* pcrel_offset */
7f266840
DJ		 442
443 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 444 0, /* rightshift */
445 2, /* size (0 = byte, 1 = short, 2 = long) */
446 32, /* bitsize */
99059e56 447 TRUE, /* pc_relative */
07d6d2b8 448 0, /* bitpos */
99059e56
RM		 449 complain_overflow_bitfield,/* complain_on_overflow */
450 bfd_elf_generic_reloc, /* special_function */
451 "R_ARM_GOTPC", /* name */
452 TRUE, /* partial_inplace */
453 0xffffffff, /* src_mask */
454 0xffffffff, /* dst_mask */
455 TRUE), /* pcrel_offset */
7f266840
DJ		 456
457 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 458 0, /* rightshift */
459 2, /* size (0 = byte, 1 = short, 2 = long) */
460 32, /* bitsize */
99059e56 461 FALSE, /* pc_relative */
07d6d2b8 462 0, /* bitpos */
99059e56
RM		 463 complain_overflow_bitfield,/* complain_on_overflow */
464 bfd_elf_generic_reloc, /* special_function */
465 "R_ARM_GOT32", /* name */
466 TRUE, /* partial_inplace */
467 0xffffffff, /* src_mask */
468 0xffffffff, /* dst_mask */
469 FALSE), /* pcrel_offset */
7f266840
DJ		 470
471 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 472 2, /* rightshift */
473 2, /* size (0 = byte, 1 = short, 2 = long) */
474 24, /* bitsize */
99059e56 475 TRUE, /* pc_relative */
07d6d2b8 476 0, /* bitpos */
99059e56
RM		 477 complain_overflow_bitfield,/* complain_on_overflow */
478 bfd_elf_generic_reloc, /* special_function */
479 "R_ARM_PLT32", /* name */
480 FALSE, /* partial_inplace */
481 0x00ffffff, /* src_mask */
482 0x00ffffff, /* dst_mask */
483 TRUE), /* pcrel_offset */
7f266840
DJ		 484
485 HOWTO (R_ARM_CALL, /* type */
486 2, /* rightshift */
487 2, /* size (0 = byte, 1 = short, 2 = long) */
488 24, /* bitsize */
489 TRUE, /* pc_relative */
490 0, /* bitpos */
491 complain_overflow_signed,/* complain_on_overflow */
492 bfd_elf_generic_reloc, /* special_function */
493 "R_ARM_CALL", /* name */
494 FALSE, /* partial_inplace */
495 0x00ffffff, /* src_mask */
496 0x00ffffff, /* dst_mask */
497 TRUE), /* pcrel_offset */
498
499 HOWTO (R_ARM_JUMP24, /* type */
500 2, /* rightshift */
501 2, /* size (0 = byte, 1 = short, 2 = long) */
502 24, /* bitsize */
503 TRUE, /* pc_relative */
504 0, /* bitpos */
505 complain_overflow_signed,/* complain_on_overflow */
506 bfd_elf_generic_reloc, /* special_function */
507 "R_ARM_JUMP24", /* name */
508 FALSE, /* partial_inplace */
509 0x00ffffff, /* src_mask */
510 0x00ffffff, /* dst_mask */
511 TRUE), /* pcrel_offset */
512
c19d1205
ZW		 513 HOWTO (R_ARM_THM_JUMP24, /* type */
514 1, /* rightshift */
515 2, /* size (0 = byte, 1 = short, 2 = long) */
516 24, /* bitsize */
517 TRUE, /* pc_relative */
7f266840 518 0, /* bitpos */
c19d1205 519 complain_overflow_signed,/* complain_on_overflow */
7f266840 520 bfd_elf_generic_reloc, /* special_function */
c19d1205 521 "R_ARM_THM_JUMP24", /* name */
7f266840 522 FALSE, /* partial_inplace */
c19d1205
ZW		 523 0x07ff2fff, /* src_mask */
524 0x07ff2fff, /* dst_mask */
525 TRUE), /* pcrel_offset */
7f266840 526
c19d1205 527 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 528 0, /* rightshift */
c19d1205
ZW		 529 2, /* size (0 = byte, 1 = short, 2 = long) */
530 32, /* bitsize */
7f266840
DJ		 531 FALSE, /* pc_relative */
532 0, /* bitpos */
533 complain_overflow_dont,/* complain_on_overflow */
534 bfd_elf_generic_reloc, /* special_function */
c19d1205 535 "R_ARM_BASE_ABS", /* name */
7f266840 536 FALSE, /* partial_inplace */
c19d1205
ZW		 537 0xffffffff, /* src_mask */
538 0xffffffff, /* dst_mask */
7f266840
DJ		 539 FALSE), /* pcrel_offset */
540
541 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
542 0, /* rightshift */
543 2, /* size (0 = byte, 1 = short, 2 = long) */
544 12, /* bitsize */
545 TRUE, /* pc_relative */
546 0, /* bitpos */
547 complain_overflow_dont,/* complain_on_overflow */
548 bfd_elf_generic_reloc, /* special_function */
549 "R_ARM_ALU_PCREL_7_0", /* name */
550 FALSE, /* partial_inplace */
551 0x00000fff, /* src_mask */
552 0x00000fff, /* dst_mask */
553 TRUE), /* pcrel_offset */
554
555 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
556 0, /* rightshift */
557 2, /* size (0 = byte, 1 = short, 2 = long) */
558 12, /* bitsize */
559 TRUE, /* pc_relative */
560 8, /* bitpos */
561 complain_overflow_dont,/* complain_on_overflow */
562 bfd_elf_generic_reloc, /* special_function */
563 "R_ARM_ALU_PCREL_15_8",/* name */
564 FALSE, /* partial_inplace */
565 0x00000fff, /* src_mask */
566 0x00000fff, /* dst_mask */
567 TRUE), /* pcrel_offset */
568
569 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
570 0, /* rightshift */
571 2, /* size (0 = byte, 1 = short, 2 = long) */
572 12, /* bitsize */
573 TRUE, /* pc_relative */
574 16, /* bitpos */
575 complain_overflow_dont,/* complain_on_overflow */
576 bfd_elf_generic_reloc, /* special_function */
577 "R_ARM_ALU_PCREL_23_15",/* name */
578 FALSE, /* partial_inplace */
579 0x00000fff, /* src_mask */
580 0x00000fff, /* dst_mask */
581 TRUE), /* pcrel_offset */
582
583 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
584 0, /* rightshift */
585 2, /* size (0 = byte, 1 = short, 2 = long) */
586 12, /* bitsize */
587 FALSE, /* pc_relative */
588 0, /* bitpos */
589 complain_overflow_dont,/* complain_on_overflow */
590 bfd_elf_generic_reloc, /* special_function */
591 "R_ARM_LDR_SBREL_11_0",/* name */
592 FALSE, /* partial_inplace */
593 0x00000fff, /* src_mask */
594 0x00000fff, /* dst_mask */
595 FALSE), /* pcrel_offset */
596
597 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
598 0, /* rightshift */
599 2, /* size (0 = byte, 1 = short, 2 = long) */
600 8, /* bitsize */
601 FALSE, /* pc_relative */
602 12, /* bitpos */
603 complain_overflow_dont,/* complain_on_overflow */
604 bfd_elf_generic_reloc, /* special_function */
605 "R_ARM_ALU_SBREL_19_12",/* name */
606 FALSE, /* partial_inplace */
607 0x000ff000, /* src_mask */
608 0x000ff000, /* dst_mask */
609 FALSE), /* pcrel_offset */
610
611 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
612 0, /* rightshift */
613 2, /* size (0 = byte, 1 = short, 2 = long) */
614 8, /* bitsize */
615 FALSE, /* pc_relative */
616 20, /* bitpos */
617 complain_overflow_dont,/* complain_on_overflow */
618 bfd_elf_generic_reloc, /* special_function */
619 "R_ARM_ALU_SBREL_27_20",/* name */
620 FALSE, /* partial_inplace */
621 0x0ff00000, /* src_mask */
622 0x0ff00000, /* dst_mask */
623 FALSE), /* pcrel_offset */
624
625 HOWTO (R_ARM_TARGET1, /* type */
626 0, /* rightshift */
627 2, /* size (0 = byte, 1 = short, 2 = long) */
628 32, /* bitsize */
629 FALSE, /* pc_relative */
630 0, /* bitpos */
631 complain_overflow_dont,/* complain_on_overflow */
632 bfd_elf_generic_reloc, /* special_function */
633 "R_ARM_TARGET1", /* name */
634 FALSE, /* partial_inplace */
635 0xffffffff, /* src_mask */
636 0xffffffff, /* dst_mask */
637 FALSE), /* pcrel_offset */
638
639 HOWTO (R_ARM_ROSEGREL32, /* type */
640 0, /* rightshift */
641 2, /* size (0 = byte, 1 = short, 2 = long) */
642 32, /* bitsize */
643 FALSE, /* pc_relative */
644 0, /* bitpos */
645 complain_overflow_dont,/* complain_on_overflow */
646 bfd_elf_generic_reloc, /* special_function */
647 "R_ARM_ROSEGREL32", /* name */
648 FALSE, /* partial_inplace */
649 0xffffffff, /* src_mask */
650 0xffffffff, /* dst_mask */
651 FALSE), /* pcrel_offset */
652
653 HOWTO (R_ARM_V4BX, /* type */
654 0, /* rightshift */
655 2, /* size (0 = byte, 1 = short, 2 = long) */
656 32, /* bitsize */
657 FALSE, /* pc_relative */
658 0, /* bitpos */
659 complain_overflow_dont,/* complain_on_overflow */
660 bfd_elf_generic_reloc, /* special_function */
661 "R_ARM_V4BX", /* name */
662 FALSE, /* partial_inplace */
663 0xffffffff, /* src_mask */
664 0xffffffff, /* dst_mask */
665 FALSE), /* pcrel_offset */
666
667 HOWTO (R_ARM_TARGET2, /* type */
668 0, /* rightshift */
669 2, /* size (0 = byte, 1 = short, 2 = long) */
670 32, /* bitsize */
671 FALSE, /* pc_relative */
672 0, /* bitpos */
673 complain_overflow_signed,/* complain_on_overflow */
674 bfd_elf_generic_reloc, /* special_function */
675 "R_ARM_TARGET2", /* name */
676 FALSE, /* partial_inplace */
677 0xffffffff, /* src_mask */
678 0xffffffff, /* dst_mask */
679 TRUE), /* pcrel_offset */
680
681 HOWTO (R_ARM_PREL31, /* type */
682 0, /* rightshift */
683 2, /* size (0 = byte, 1 = short, 2 = long) */
684 31, /* bitsize */
685 TRUE, /* pc_relative */
686 0, /* bitpos */
687 complain_overflow_signed,/* complain_on_overflow */
688 bfd_elf_generic_reloc, /* special_function */
689 "R_ARM_PREL31", /* name */
690 FALSE, /* partial_inplace */
691 0x7fffffff, /* src_mask */
692 0x7fffffff, /* dst_mask */
693 TRUE), /* pcrel_offset */
c19d1205
ZW		 694
695 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
696 0, /* rightshift */
697 2, /* size (0 = byte, 1 = short, 2 = long) */
698 16, /* bitsize */
699 FALSE, /* pc_relative */
700 0, /* bitpos */
701 complain_overflow_dont,/* complain_on_overflow */
702 bfd_elf_generic_reloc, /* special_function */
703 "R_ARM_MOVW_ABS_NC", /* name */
704 FALSE, /* partial_inplace */
39623e12
PB		 705 0x000f0fff, /* src_mask */
706 0x000f0fff, /* dst_mask */
c19d1205
ZW		 707 FALSE), /* pcrel_offset */
708
709 HOWTO (R_ARM_MOVT_ABS, /* type */
710 0, /* rightshift */
711 2, /* size (0 = byte, 1 = short, 2 = long) */
712 16, /* bitsize */
713 FALSE, /* pc_relative */
714 0, /* bitpos */
715 complain_overflow_bitfield,/* complain_on_overflow */
716 bfd_elf_generic_reloc, /* special_function */
717 "R_ARM_MOVT_ABS", /* name */
718 FALSE, /* partial_inplace */
39623e12
PB		 719 0x000f0fff, /* src_mask */
720 0x000f0fff, /* dst_mask */
c19d1205
ZW		 721 FALSE), /* pcrel_offset */
722
723 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
724 0, /* rightshift */
725 2, /* size (0 = byte, 1 = short, 2 = long) */
726 16, /* bitsize */
727 TRUE, /* pc_relative */
728 0, /* bitpos */
729 complain_overflow_dont,/* complain_on_overflow */
730 bfd_elf_generic_reloc, /* special_function */
731 "R_ARM_MOVW_PREL_NC", /* name */
732 FALSE, /* partial_inplace */
39623e12
PB		 733 0x000f0fff, /* src_mask */
734 0x000f0fff, /* dst_mask */
c19d1205
ZW		 735 TRUE), /* pcrel_offset */
736
737 HOWTO (R_ARM_MOVT_PREL, /* type */
738 0, /* rightshift */
739 2, /* size (0 = byte, 1 = short, 2 = long) */
740 16, /* bitsize */
741 TRUE, /* pc_relative */
742 0, /* bitpos */
743 complain_overflow_bitfield,/* complain_on_overflow */
744 bfd_elf_generic_reloc, /* special_function */
745 "R_ARM_MOVT_PREL", /* name */
746 FALSE, /* partial_inplace */
39623e12
PB		 747 0x000f0fff, /* src_mask */
748 0x000f0fff, /* dst_mask */
c19d1205
ZW		 749 TRUE), /* pcrel_offset */
750
751 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
752 0, /* rightshift */
753 2, /* size (0 = byte, 1 = short, 2 = long) */
754 16, /* bitsize */
755 FALSE, /* pc_relative */
756 0, /* bitpos */
757 complain_overflow_dont,/* complain_on_overflow */
758 bfd_elf_generic_reloc, /* special_function */
759 "R_ARM_THM_MOVW_ABS_NC",/* name */
760 FALSE, /* partial_inplace */
761 0x040f70ff, /* src_mask */
762 0x040f70ff, /* dst_mask */
763 FALSE), /* pcrel_offset */
764
765 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
766 0, /* rightshift */
767 2, /* size (0 = byte, 1 = short, 2 = long) */
768 16, /* bitsize */
769 FALSE, /* pc_relative */
770 0, /* bitpos */
771 complain_overflow_bitfield,/* complain_on_overflow */
772 bfd_elf_generic_reloc, /* special_function */
773 "R_ARM_THM_MOVT_ABS", /* name */
774 FALSE, /* partial_inplace */
775 0x040f70ff, /* src_mask */
776 0x040f70ff, /* dst_mask */
777 FALSE), /* pcrel_offset */
778
779 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
780 0, /* rightshift */
781 2, /* size (0 = byte, 1 = short, 2 = long) */
782 16, /* bitsize */
783 TRUE, /* pc_relative */
784 0, /* bitpos */
785 complain_overflow_dont,/* complain_on_overflow */
786 bfd_elf_generic_reloc, /* special_function */
787 "R_ARM_THM_MOVW_PREL_NC",/* name */
788 FALSE, /* partial_inplace */
789 0x040f70ff, /* src_mask */
790 0x040f70ff, /* dst_mask */
791 TRUE), /* pcrel_offset */
792
793 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
794 0, /* rightshift */
795 2, /* size (0 = byte, 1 = short, 2 = long) */
796 16, /* bitsize */
797 TRUE, /* pc_relative */
798 0, /* bitpos */
799 complain_overflow_bitfield,/* complain_on_overflow */
800 bfd_elf_generic_reloc, /* special_function */
801 "R_ARM_THM_MOVT_PREL", /* name */
802 FALSE, /* partial_inplace */
803 0x040f70ff, /* src_mask */
804 0x040f70ff, /* dst_mask */
805 TRUE), /* pcrel_offset */
806
807 HOWTO (R_ARM_THM_JUMP19, /* type */
808 1, /* rightshift */
809 2, /* size (0 = byte, 1 = short, 2 = long) */
810 19, /* bitsize */
811 TRUE, /* pc_relative */
812 0, /* bitpos */
813 complain_overflow_signed,/* complain_on_overflow */
814 bfd_elf_generic_reloc, /* special_function */
815 "R_ARM_THM_JUMP19", /* name */
816 FALSE, /* partial_inplace */
817 0x043f2fff, /* src_mask */
818 0x043f2fff, /* dst_mask */
819 TRUE), /* pcrel_offset */
820
821 HOWTO (R_ARM_THM_JUMP6, /* type */
822 1, /* rightshift */
823 1, /* size (0 = byte, 1 = short, 2 = long) */
824 6, /* bitsize */
825 TRUE, /* pc_relative */
826 0, /* bitpos */
827 complain_overflow_unsigned,/* complain_on_overflow */
828 bfd_elf_generic_reloc, /* special_function */
829 "R_ARM_THM_JUMP6", /* name */
830 FALSE, /* partial_inplace */
831 0x02f8, /* src_mask */
832 0x02f8, /* dst_mask */
833 TRUE), /* pcrel_offset */
834
835 /* These are declared as 13-bit signed relocations because we can
836 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
837 versa. */
838 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
839 0, /* rightshift */
840 2, /* size (0 = byte, 1 = short, 2 = long) */
841 13, /* bitsize */
842 TRUE, /* pc_relative */
843 0, /* bitpos */
2cab6cc3 844 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 845 bfd_elf_generic_reloc, /* special_function */
846 "R_ARM_THM_ALU_PREL_11_0",/* name */
847 FALSE, /* partial_inplace */
2cab6cc3
MS		 848 0xffffffff, /* src_mask */
849 0xffffffff, /* dst_mask */
c19d1205
ZW		 850 TRUE), /* pcrel_offset */
851
852 HOWTO (R_ARM_THM_PC12, /* type */
853 0, /* rightshift */
854 2, /* size (0 = byte, 1 = short, 2 = long) */
855 13, /* bitsize */
856 TRUE, /* pc_relative */
857 0, /* bitpos */
2cab6cc3 858 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 859 bfd_elf_generic_reloc, /* special_function */
860 "R_ARM_THM_PC12", /* name */
861 FALSE, /* partial_inplace */
2cab6cc3
MS		 862 0xffffffff, /* src_mask */
863 0xffffffff, /* dst_mask */
c19d1205
ZW		 864 TRUE), /* pcrel_offset */
865
866 HOWTO (R_ARM_ABS32_NOI, /* type */
867 0, /* rightshift */
868 2, /* size (0 = byte, 1 = short, 2 = long) */
869 32, /* bitsize */
870 FALSE, /* pc_relative */
871 0, /* bitpos */
872 complain_overflow_dont,/* complain_on_overflow */
873 bfd_elf_generic_reloc, /* special_function */
874 "R_ARM_ABS32_NOI", /* name */
875 FALSE, /* partial_inplace */
876 0xffffffff, /* src_mask */
877 0xffffffff, /* dst_mask */
878 FALSE), /* pcrel_offset */
879
880 HOWTO (R_ARM_REL32_NOI, /* type */
881 0, /* rightshift */
882 2, /* size (0 = byte, 1 = short, 2 = long) */
883 32, /* bitsize */
884 TRUE, /* pc_relative */
885 0, /* bitpos */
886 complain_overflow_dont,/* complain_on_overflow */
887 bfd_elf_generic_reloc, /* special_function */
888 "R_ARM_REL32_NOI", /* name */
889 FALSE, /* partial_inplace */
890 0xffffffff, /* src_mask */
891 0xffffffff, /* dst_mask */
892 FALSE), /* pcrel_offset */
7f266840 893
4962c51a
MS		 894 /* Group relocations. */
895
896 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
897 0, /* rightshift */
898 2, /* size (0 = byte, 1 = short, 2 = long) */
899 32, /* bitsize */
900 TRUE, /* pc_relative */
901 0, /* bitpos */
902 complain_overflow_dont,/* complain_on_overflow */
903 bfd_elf_generic_reloc, /* special_function */
904 "R_ARM_ALU_PC_G0_NC", /* name */
905 FALSE, /* partial_inplace */
906 0xffffffff, /* src_mask */
907 0xffffffff, /* dst_mask */
908 TRUE), /* pcrel_offset */
909
07d6d2b8 910 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 911 0, /* rightshift */
912 2, /* size (0 = byte, 1 = short, 2 = long) */
913 32, /* bitsize */
914 TRUE, /* pc_relative */
915 0, /* bitpos */
916 complain_overflow_dont,/* complain_on_overflow */
917 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 918 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 919 FALSE, /* partial_inplace */
920 0xffffffff, /* src_mask */
921 0xffffffff, /* dst_mask */
922 TRUE), /* pcrel_offset */
923
924 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
925 0, /* rightshift */
926 2, /* size (0 = byte, 1 = short, 2 = long) */
927 32, /* bitsize */
928 TRUE, /* pc_relative */
929 0, /* bitpos */
930 complain_overflow_dont,/* complain_on_overflow */
931 bfd_elf_generic_reloc, /* special_function */
932 "R_ARM_ALU_PC_G1_NC", /* name */
933 FALSE, /* partial_inplace */
934 0xffffffff, /* src_mask */
935 0xffffffff, /* dst_mask */
936 TRUE), /* pcrel_offset */
937
07d6d2b8 938 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 939 0, /* rightshift */
940 2, /* size (0 = byte, 1 = short, 2 = long) */
941 32, /* bitsize */
942 TRUE, /* pc_relative */
943 0, /* bitpos */
944 complain_overflow_dont,/* complain_on_overflow */
945 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 946 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 947 FALSE, /* partial_inplace */
948 0xffffffff, /* src_mask */
949 0xffffffff, /* dst_mask */
950 TRUE), /* pcrel_offset */
951
07d6d2b8 952 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 953 0, /* rightshift */
954 2, /* size (0 = byte, 1 = short, 2 = long) */
955 32, /* bitsize */
956 TRUE, /* pc_relative */
957 0, /* bitpos */
958 complain_overflow_dont,/* complain_on_overflow */
959 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 960 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 961 FALSE, /* partial_inplace */
962 0xffffffff, /* src_mask */
963 0xffffffff, /* dst_mask */
964 TRUE), /* pcrel_offset */
965
07d6d2b8 966 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 967 0, /* rightshift */
968 2, /* size (0 = byte, 1 = short, 2 = long) */
969 32, /* bitsize */
970 TRUE, /* pc_relative */
971 0, /* bitpos */
972 complain_overflow_dont,/* complain_on_overflow */
973 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 974 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 975 FALSE, /* partial_inplace */
976 0xffffffff, /* src_mask */
977 0xffffffff, /* dst_mask */
978 TRUE), /* pcrel_offset */
979
07d6d2b8 980 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 981 0, /* rightshift */
982 2, /* size (0 = byte, 1 = short, 2 = long) */
983 32, /* bitsize */
984 TRUE, /* pc_relative */
985 0, /* bitpos */
986 complain_overflow_dont,/* complain_on_overflow */
987 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 988 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 989 FALSE, /* partial_inplace */
990 0xffffffff, /* src_mask */
991 0xffffffff, /* dst_mask */
992 TRUE), /* pcrel_offset */
993
07d6d2b8 994 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 995 0, /* rightshift */
996 2, /* size (0 = byte, 1 = short, 2 = long) */
997 32, /* bitsize */
998 TRUE, /* pc_relative */
999 0, /* bitpos */
1000 complain_overflow_dont,/* complain_on_overflow */
1001 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1002 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1003 FALSE, /* partial_inplace */
1004 0xffffffff, /* src_mask */
1005 0xffffffff, /* dst_mask */
1006 TRUE), /* pcrel_offset */
1007
07d6d2b8 1008 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1009 0, /* rightshift */
1010 2, /* size (0 = byte, 1 = short, 2 = long) */
1011 32, /* bitsize */
1012 TRUE, /* pc_relative */
1013 0, /* bitpos */
1014 complain_overflow_dont,/* complain_on_overflow */
1015 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1016 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1017 FALSE, /* partial_inplace */
1018 0xffffffff, /* src_mask */
1019 0xffffffff, /* dst_mask */
1020 TRUE), /* pcrel_offset */
1021
07d6d2b8 1022 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1023 0, /* rightshift */
1024 2, /* size (0 = byte, 1 = short, 2 = long) */
1025 32, /* bitsize */
1026 TRUE, /* pc_relative */
1027 0, /* bitpos */
1028 complain_overflow_dont,/* complain_on_overflow */
1029 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1030 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1031 FALSE, /* partial_inplace */
1032 0xffffffff, /* src_mask */
1033 0xffffffff, /* dst_mask */
1034 TRUE), /* pcrel_offset */
1035
07d6d2b8 1036 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1037 0, /* rightshift */
1038 2, /* size (0 = byte, 1 = short, 2 = long) */
1039 32, /* bitsize */
1040 TRUE, /* pc_relative */
1041 0, /* bitpos */
1042 complain_overflow_dont,/* complain_on_overflow */
1043 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1044 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1045 FALSE, /* partial_inplace */
1046 0xffffffff, /* src_mask */
1047 0xffffffff, /* dst_mask */
1048 TRUE), /* pcrel_offset */
1049
07d6d2b8 1050 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1051 0, /* rightshift */
1052 2, /* size (0 = byte, 1 = short, 2 = long) */
1053 32, /* bitsize */
1054 TRUE, /* pc_relative */
1055 0, /* bitpos */
1056 complain_overflow_dont,/* complain_on_overflow */
1057 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1058 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1059 FALSE, /* partial_inplace */
1060 0xffffffff, /* src_mask */
1061 0xffffffff, /* dst_mask */
1062 TRUE), /* pcrel_offset */
1063
07d6d2b8 1064 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1065 0, /* rightshift */
1066 2, /* size (0 = byte, 1 = short, 2 = long) */
1067 32, /* bitsize */
1068 TRUE, /* pc_relative */
1069 0, /* bitpos */
1070 complain_overflow_dont,/* complain_on_overflow */
1071 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1072 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1073 FALSE, /* partial_inplace */
1074 0xffffffff, /* src_mask */
1075 0xffffffff, /* dst_mask */
1076 TRUE), /* pcrel_offset */
1077
07d6d2b8 1078 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1079 0, /* rightshift */
1080 2, /* size (0 = byte, 1 = short, 2 = long) */
1081 32, /* bitsize */
1082 TRUE, /* pc_relative */
1083 0, /* bitpos */
1084 complain_overflow_dont,/* complain_on_overflow */
1085 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1086 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1087 FALSE, /* partial_inplace */
1088 0xffffffff, /* src_mask */
1089 0xffffffff, /* dst_mask */
1090 TRUE), /* pcrel_offset */
1091
07d6d2b8 1092 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1093 0, /* rightshift */
1094 2, /* size (0 = byte, 1 = short, 2 = long) */
1095 32, /* bitsize */
1096 TRUE, /* pc_relative */
1097 0, /* bitpos */
1098 complain_overflow_dont,/* complain_on_overflow */
1099 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1100 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1101 FALSE, /* partial_inplace */
1102 0xffffffff, /* src_mask */
1103 0xffffffff, /* dst_mask */
1104 TRUE), /* pcrel_offset */
1105
07d6d2b8 1106 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1107 0, /* rightshift */
1108 2, /* size (0 = byte, 1 = short, 2 = long) */
1109 32, /* bitsize */
1110 TRUE, /* pc_relative */
1111 0, /* bitpos */
1112 complain_overflow_dont,/* complain_on_overflow */
1113 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1114 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1115 FALSE, /* partial_inplace */
1116 0xffffffff, /* src_mask */
1117 0xffffffff, /* dst_mask */
1118 TRUE), /* pcrel_offset */
1119
07d6d2b8 1120 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1121 0, /* rightshift */
1122 2, /* size (0 = byte, 1 = short, 2 = long) */
1123 32, /* bitsize */
1124 TRUE, /* pc_relative */
1125 0, /* bitpos */
1126 complain_overflow_dont,/* complain_on_overflow */
1127 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1128 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1129 FALSE, /* partial_inplace */
1130 0xffffffff, /* src_mask */
1131 0xffffffff, /* dst_mask */
1132 TRUE), /* pcrel_offset */
1133
07d6d2b8 1134 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1135 0, /* rightshift */
1136 2, /* size (0 = byte, 1 = short, 2 = long) */
1137 32, /* bitsize */
1138 TRUE, /* pc_relative */
1139 0, /* bitpos */
1140 complain_overflow_dont,/* complain_on_overflow */
1141 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1142 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1143 FALSE, /* partial_inplace */
1144 0xffffffff, /* src_mask */
1145 0xffffffff, /* dst_mask */
1146 TRUE), /* pcrel_offset */
1147
07d6d2b8 1148 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1149 0, /* rightshift */
1150 2, /* size (0 = byte, 1 = short, 2 = long) */
1151 32, /* bitsize */
1152 TRUE, /* pc_relative */
1153 0, /* bitpos */
1154 complain_overflow_dont,/* complain_on_overflow */
1155 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1156 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1157 FALSE, /* partial_inplace */
1158 0xffffffff, /* src_mask */
1159 0xffffffff, /* dst_mask */
1160 TRUE), /* pcrel_offset */
1161
07d6d2b8 1162 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1163 0, /* rightshift */
1164 2, /* size (0 = byte, 1 = short, 2 = long) */
1165 32, /* bitsize */
1166 TRUE, /* pc_relative */
1167 0, /* bitpos */
1168 complain_overflow_dont,/* complain_on_overflow */
1169 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1170 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1171 FALSE, /* partial_inplace */
1172 0xffffffff, /* src_mask */
1173 0xffffffff, /* dst_mask */
1174 TRUE), /* pcrel_offset */
1175
07d6d2b8 1176 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1177 0, /* rightshift */
1178 2, /* size (0 = byte, 1 = short, 2 = long) */
1179 32, /* bitsize */
1180 TRUE, /* pc_relative */
1181 0, /* bitpos */
1182 complain_overflow_dont,/* complain_on_overflow */
1183 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1184 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1185 FALSE, /* partial_inplace */
1186 0xffffffff, /* src_mask */
1187 0xffffffff, /* dst_mask */
1188 TRUE), /* pcrel_offset */
1189
07d6d2b8 1190 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1191 0, /* rightshift */
1192 2, /* size (0 = byte, 1 = short, 2 = long) */
1193 32, /* bitsize */
1194 TRUE, /* pc_relative */
1195 0, /* bitpos */
1196 complain_overflow_dont,/* complain_on_overflow */
1197 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1198 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1199 FALSE, /* partial_inplace */
1200 0xffffffff, /* src_mask */
1201 0xffffffff, /* dst_mask */
1202 TRUE), /* pcrel_offset */
1203
07d6d2b8 1204 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1205 0, /* rightshift */
1206 2, /* size (0 = byte, 1 = short, 2 = long) */
1207 32, /* bitsize */
1208 TRUE, /* pc_relative */
1209 0, /* bitpos */
1210 complain_overflow_dont,/* complain_on_overflow */
1211 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1212 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1213 FALSE, /* partial_inplace */
1214 0xffffffff, /* src_mask */
1215 0xffffffff, /* dst_mask */
1216 TRUE), /* pcrel_offset */
1217
07d6d2b8 1218 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1219 0, /* rightshift */
1220 2, /* size (0 = byte, 1 = short, 2 = long) */
1221 32, /* bitsize */
1222 TRUE, /* pc_relative */
1223 0, /* bitpos */
1224 complain_overflow_dont,/* complain_on_overflow */
1225 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1226 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1227 FALSE, /* partial_inplace */
1228 0xffffffff, /* src_mask */
1229 0xffffffff, /* dst_mask */
1230 TRUE), /* pcrel_offset */
1231
07d6d2b8 1232 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1233 0, /* rightshift */
1234 2, /* size (0 = byte, 1 = short, 2 = long) */
1235 32, /* bitsize */
1236 TRUE, /* pc_relative */
1237 0, /* bitpos */
1238 complain_overflow_dont,/* complain_on_overflow */
1239 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1240 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1241 FALSE, /* partial_inplace */
1242 0xffffffff, /* src_mask */
1243 0xffffffff, /* dst_mask */
1244 TRUE), /* pcrel_offset */
1245
07d6d2b8 1246 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1247 0, /* rightshift */
1248 2, /* size (0 = byte, 1 = short, 2 = long) */
1249 32, /* bitsize */
1250 TRUE, /* pc_relative */
1251 0, /* bitpos */
1252 complain_overflow_dont,/* complain_on_overflow */
1253 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1254 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1255 FALSE, /* partial_inplace */
1256 0xffffffff, /* src_mask */
1257 0xffffffff, /* dst_mask */
1258 TRUE), /* pcrel_offset */
1259
07d6d2b8 1260 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1261 0, /* rightshift */
1262 2, /* size (0 = byte, 1 = short, 2 = long) */
1263 32, /* bitsize */
1264 TRUE, /* pc_relative */
1265 0, /* bitpos */
1266 complain_overflow_dont,/* complain_on_overflow */
1267 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1268 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1269 FALSE, /* partial_inplace */
1270 0xffffffff, /* src_mask */
1271 0xffffffff, /* dst_mask */
1272 TRUE), /* pcrel_offset */
1273
1274 /* End of group relocations. */
c19d1205 1275
c19d1205
ZW		 1276 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1277 0, /* rightshift */
1278 2, /* size (0 = byte, 1 = short, 2 = long) */
1279 16, /* bitsize */
1280 FALSE, /* pc_relative */
1281 0, /* bitpos */
1282 complain_overflow_dont,/* complain_on_overflow */
1283 bfd_elf_generic_reloc, /* special_function */
1284 "R_ARM_MOVW_BREL_NC", /* name */
1285 FALSE, /* partial_inplace */
1286 0x0000ffff, /* src_mask */
1287 0x0000ffff, /* dst_mask */
1288 FALSE), /* pcrel_offset */
1289
1290 HOWTO (R_ARM_MOVT_BREL, /* type */
1291 0, /* rightshift */
1292 2, /* size (0 = byte, 1 = short, 2 = long) */
1293 16, /* bitsize */
1294 FALSE, /* pc_relative */
1295 0, /* bitpos */
1296 complain_overflow_bitfield,/* complain_on_overflow */
1297 bfd_elf_generic_reloc, /* special_function */
1298 "R_ARM_MOVT_BREL", /* name */
1299 FALSE, /* partial_inplace */
1300 0x0000ffff, /* src_mask */
1301 0x0000ffff, /* dst_mask */
1302 FALSE), /* pcrel_offset */
1303
1304 HOWTO (R_ARM_MOVW_BREL, /* type */
1305 0, /* rightshift */
1306 2, /* size (0 = byte, 1 = short, 2 = long) */
1307 16, /* bitsize */
1308 FALSE, /* pc_relative */
1309 0, /* bitpos */
1310 complain_overflow_dont,/* complain_on_overflow */
1311 bfd_elf_generic_reloc, /* special_function */
1312 "R_ARM_MOVW_BREL", /* name */
1313 FALSE, /* partial_inplace */
1314 0x0000ffff, /* src_mask */
1315 0x0000ffff, /* dst_mask */
1316 FALSE), /* pcrel_offset */
1317
1318 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1319 0, /* rightshift */
1320 2, /* size (0 = byte, 1 = short, 2 = long) */
1321 16, /* bitsize */
1322 FALSE, /* pc_relative */
1323 0, /* bitpos */
1324 complain_overflow_dont,/* complain_on_overflow */
1325 bfd_elf_generic_reloc, /* special_function */
1326 "R_ARM_THM_MOVW_BREL_NC",/* name */
1327 FALSE, /* partial_inplace */
1328 0x040f70ff, /* src_mask */
1329 0x040f70ff, /* dst_mask */
1330 FALSE), /* pcrel_offset */
1331
1332 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1333 0, /* rightshift */
1334 2, /* size (0 = byte, 1 = short, 2 = long) */
1335 16, /* bitsize */
1336 FALSE, /* pc_relative */
1337 0, /* bitpos */
1338 complain_overflow_bitfield,/* complain_on_overflow */
1339 bfd_elf_generic_reloc, /* special_function */
1340 "R_ARM_THM_MOVT_BREL", /* name */
1341 FALSE, /* partial_inplace */
1342 0x040f70ff, /* src_mask */
1343 0x040f70ff, /* dst_mask */
1344 FALSE), /* pcrel_offset */
1345
1346 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1347 0, /* rightshift */
1348 2, /* size (0 = byte, 1 = short, 2 = long) */
1349 16, /* bitsize */
1350 FALSE, /* pc_relative */
1351 0, /* bitpos */
1352 complain_overflow_dont,/* complain_on_overflow */
1353 bfd_elf_generic_reloc, /* special_function */
1354 "R_ARM_THM_MOVW_BREL", /* name */
1355 FALSE, /* partial_inplace */
1356 0x040f70ff, /* src_mask */
1357 0x040f70ff, /* dst_mask */
1358 FALSE), /* pcrel_offset */
1359
0855e32b
NS		 1360 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1361 0, /* rightshift */
1362 2, /* size (0 = byte, 1 = short, 2 = long) */
1363 32, /* bitsize */
1364 FALSE, /* pc_relative */
1365 0, /* bitpos */
1366 complain_overflow_bitfield,/* complain_on_overflow */
1367 NULL, /* special_function */
1368 "R_ARM_TLS_GOTDESC", /* name */
1369 TRUE, /* partial_inplace */
1370 0xffffffff, /* src_mask */
1371 0xffffffff, /* dst_mask */
1372 FALSE), /* pcrel_offset */
1373
1374 HOWTO (R_ARM_TLS_CALL, /* type */
1375 0, /* rightshift */
1376 2, /* size (0 = byte, 1 = short, 2 = long) */
1377 24, /* bitsize */
1378 FALSE, /* pc_relative */
1379 0, /* bitpos */
1380 complain_overflow_dont,/* complain_on_overflow */
1381 bfd_elf_generic_reloc, /* special_function */
1382 "R_ARM_TLS_CALL", /* name */
1383 FALSE, /* partial_inplace */
1384 0x00ffffff, /* src_mask */
1385 0x00ffffff, /* dst_mask */
1386 FALSE), /* pcrel_offset */
1387
1388 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1389 0, /* rightshift */
1390 2, /* size (0 = byte, 1 = short, 2 = long) */
1391 0, /* bitsize */
1392 FALSE, /* pc_relative */
1393 0, /* bitpos */
1394 complain_overflow_bitfield,/* complain_on_overflow */
1395 bfd_elf_generic_reloc, /* special_function */
1396 "R_ARM_TLS_DESCSEQ", /* name */
1397 FALSE, /* partial_inplace */
1398 0x00000000, /* src_mask */
1399 0x00000000, /* dst_mask */
1400 FALSE), /* pcrel_offset */
1401
1402 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1403 0, /* rightshift */
1404 2, /* size (0 = byte, 1 = short, 2 = long) */
1405 24, /* bitsize */
1406 FALSE, /* pc_relative */
1407 0, /* bitpos */
1408 complain_overflow_dont,/* complain_on_overflow */
1409 bfd_elf_generic_reloc, /* special_function */
1410 "R_ARM_THM_TLS_CALL", /* name */
1411 FALSE, /* partial_inplace */
1412 0x07ff07ff, /* src_mask */
1413 0x07ff07ff, /* dst_mask */
1414 FALSE), /* pcrel_offset */
c19d1205
ZW		 1415
1416 HOWTO (R_ARM_PLT32_ABS, /* type */
1417 0, /* rightshift */
1418 2, /* size (0 = byte, 1 = short, 2 = long) */
1419 32, /* bitsize */
1420 FALSE, /* pc_relative */
1421 0, /* bitpos */
1422 complain_overflow_dont,/* complain_on_overflow */
1423 bfd_elf_generic_reloc, /* special_function */
1424 "R_ARM_PLT32_ABS", /* name */
1425 FALSE, /* partial_inplace */
1426 0xffffffff, /* src_mask */
1427 0xffffffff, /* dst_mask */
1428 FALSE), /* pcrel_offset */
1429
1430 HOWTO (R_ARM_GOT_ABS, /* type */
1431 0, /* rightshift */
1432 2, /* size (0 = byte, 1 = short, 2 = long) */
1433 32, /* bitsize */
1434 FALSE, /* pc_relative */
1435 0, /* bitpos */
1436 complain_overflow_dont,/* complain_on_overflow */
1437 bfd_elf_generic_reloc, /* special_function */
1438 "R_ARM_GOT_ABS", /* name */
1439 FALSE, /* partial_inplace */
1440 0xffffffff, /* src_mask */
1441 0xffffffff, /* dst_mask */
1442 FALSE), /* pcrel_offset */
1443
1444 HOWTO (R_ARM_GOT_PREL, /* type */
1445 0, /* rightshift */
1446 2, /* size (0 = byte, 1 = short, 2 = long) */
1447 32, /* bitsize */
1448 TRUE, /* pc_relative */
1449 0, /* bitpos */
1450 complain_overflow_dont, /* complain_on_overflow */
1451 bfd_elf_generic_reloc, /* special_function */
1452 "R_ARM_GOT_PREL", /* name */
1453 FALSE, /* partial_inplace */
1454 0xffffffff, /* src_mask */
1455 0xffffffff, /* dst_mask */
1456 TRUE), /* pcrel_offset */
1457
1458 HOWTO (R_ARM_GOT_BREL12, /* type */
1459 0, /* rightshift */
1460 2, /* size (0 = byte, 1 = short, 2 = long) */
1461 12, /* bitsize */
1462 FALSE, /* pc_relative */
1463 0, /* bitpos */
1464 complain_overflow_bitfield,/* complain_on_overflow */
1465 bfd_elf_generic_reloc, /* special_function */
1466 "R_ARM_GOT_BREL12", /* name */
1467 FALSE, /* partial_inplace */
1468 0x00000fff, /* src_mask */
1469 0x00000fff, /* dst_mask */
1470 FALSE), /* pcrel_offset */
1471
1472 HOWTO (R_ARM_GOTOFF12, /* type */
1473 0, /* rightshift */
1474 2, /* size (0 = byte, 1 = short, 2 = long) */
1475 12, /* bitsize */
1476 FALSE, /* pc_relative */
1477 0, /* bitpos */
1478 complain_overflow_bitfield,/* complain_on_overflow */
1479 bfd_elf_generic_reloc, /* special_function */
1480 "R_ARM_GOTOFF12", /* name */
1481 FALSE, /* partial_inplace */
1482 0x00000fff, /* src_mask */
1483 0x00000fff, /* dst_mask */
1484 FALSE), /* pcrel_offset */
1485
07d6d2b8 1486 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1487
1488 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1489 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1490 0, /* rightshift */
1491 2, /* size (0 = byte, 1 = short, 2 = long) */
1492 0, /* bitsize */
1493 FALSE, /* pc_relative */
1494 0, /* bitpos */
99059e56 1495 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1496 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1497 "R_ARM_GNU_VTENTRY", /* name */
1498 FALSE, /* partial_inplace */
1499 0, /* src_mask */
1500 0, /* dst_mask */
1501 FALSE), /* pcrel_offset */
c19d1205
ZW		 1502
1503 /* GNU extension to record C++ vtable hierarchy */
1504 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1505 0, /* rightshift */
1506 2, /* size (0 = byte, 1 = short, 2 = long) */
1507 0, /* bitsize */
1508 FALSE, /* pc_relative */
1509 0, /* bitpos */
99059e56 1510 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1511 NULL, /* special_function */
99059e56 1512 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1513 FALSE, /* partial_inplace */
1514 0, /* src_mask */
1515 0, /* dst_mask */
1516 FALSE), /* pcrel_offset */
c19d1205
ZW		 1517
1518 HOWTO (R_ARM_THM_JUMP11, /* type */
1519 1, /* rightshift */
1520 1, /* size (0 = byte, 1 = short, 2 = long) */
1521 11, /* bitsize */
1522 TRUE, /* pc_relative */
1523 0, /* bitpos */
1524 complain_overflow_signed, /* complain_on_overflow */
1525 bfd_elf_generic_reloc, /* special_function */
1526 "R_ARM_THM_JUMP11", /* name */
1527 FALSE, /* partial_inplace */
1528 0x000007ff, /* src_mask */
1529 0x000007ff, /* dst_mask */
1530 TRUE), /* pcrel_offset */
1531
1532 HOWTO (R_ARM_THM_JUMP8, /* type */
1533 1, /* rightshift */
1534 1, /* size (0 = byte, 1 = short, 2 = long) */
1535 8, /* bitsize */
1536 TRUE, /* pc_relative */
1537 0, /* bitpos */
1538 complain_overflow_signed, /* complain_on_overflow */
1539 bfd_elf_generic_reloc, /* special_function */
1540 "R_ARM_THM_JUMP8", /* name */
1541 FALSE, /* partial_inplace */
1542 0x000000ff, /* src_mask */
1543 0x000000ff, /* dst_mask */
1544 TRUE), /* pcrel_offset */
ba93b8ac 1545
c19d1205
ZW		 1546 /* TLS relocations */
1547 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1548 0, /* rightshift */
1549 2, /* size (0 = byte, 1 = short, 2 = long) */
1550 32, /* bitsize */
1551 FALSE, /* pc_relative */
1552 0, /* bitpos */
99059e56
RM		 1553 complain_overflow_bitfield,/* complain_on_overflow */
1554 NULL, /* special_function */
1555 "R_ARM_TLS_GD32", /* name */
1556 TRUE, /* partial_inplace */
1557 0xffffffff, /* src_mask */
1558 0xffffffff, /* dst_mask */
07d6d2b8 1559 FALSE), /* pcrel_offset */
ba93b8ac 1560
ba93b8ac 1561 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1562 0, /* rightshift */
1563 2, /* size (0 = byte, 1 = short, 2 = long) */
1564 32, /* bitsize */
1565 FALSE, /* pc_relative */
1566 0, /* bitpos */
99059e56
RM		 1567 complain_overflow_bitfield,/* complain_on_overflow */
1568 bfd_elf_generic_reloc, /* special_function */
1569 "R_ARM_TLS_LDM32", /* name */
1570 TRUE, /* partial_inplace */
1571 0xffffffff, /* src_mask */
1572 0xffffffff, /* dst_mask */
07d6d2b8 1573 FALSE), /* pcrel_offset */
ba93b8ac 1574
c19d1205 1575 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1576 0, /* rightshift */
1577 2, /* size (0 = byte, 1 = short, 2 = long) */
1578 32, /* bitsize */
1579 FALSE, /* pc_relative */
1580 0, /* bitpos */
99059e56
RM		 1581 complain_overflow_bitfield,/* complain_on_overflow */
1582 bfd_elf_generic_reloc, /* special_function */
1583 "R_ARM_TLS_LDO32", /* name */
1584 TRUE, /* partial_inplace */
1585 0xffffffff, /* src_mask */
1586 0xffffffff, /* dst_mask */
07d6d2b8 1587 FALSE), /* pcrel_offset */
ba93b8ac 1588
ba93b8ac 1589 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1590 0, /* rightshift */
1591 2, /* size (0 = byte, 1 = short, 2 = long) */
1592 32, /* bitsize */
1593 FALSE, /* pc_relative */
1594 0, /* bitpos */
99059e56
RM		 1595 complain_overflow_bitfield,/* complain_on_overflow */
1596 NULL, /* special_function */
1597 "R_ARM_TLS_IE32", /* name */
1598 TRUE, /* partial_inplace */
1599 0xffffffff, /* src_mask */
1600 0xffffffff, /* dst_mask */
07d6d2b8 1601 FALSE), /* pcrel_offset */
7f266840 1602
c19d1205 1603 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1604 0, /* rightshift */
1605 2, /* size (0 = byte, 1 = short, 2 = long) */
1606 32, /* bitsize */
1607 FALSE, /* pc_relative */
1608 0, /* bitpos */
99059e56 1609 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1610 NULL, /* special_function */
99059e56
RM		 1611 "R_ARM_TLS_LE32", /* name */
1612 TRUE, /* partial_inplace */
1613 0xffffffff, /* src_mask */
1614 0xffffffff, /* dst_mask */
07d6d2b8 1615 FALSE), /* pcrel_offset */
7f266840 1616
c19d1205
ZW		 1617 HOWTO (R_ARM_TLS_LDO12, /* type */
1618 0, /* rightshift */
1619 2, /* size (0 = byte, 1 = short, 2 = long) */
1620 12, /* bitsize */
1621 FALSE, /* pc_relative */
7f266840 1622 0, /* bitpos */
c19d1205 1623 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1624 bfd_elf_generic_reloc, /* special_function */
c19d1205 1625 "R_ARM_TLS_LDO12", /* name */
7f266840 1626 FALSE, /* partial_inplace */
c19d1205
ZW		 1627 0x00000fff, /* src_mask */
1628 0x00000fff, /* dst_mask */
1629 FALSE), /* pcrel_offset */
7f266840 1630
c19d1205
ZW		 1631 HOWTO (R_ARM_TLS_LE12, /* type */
1632 0, /* rightshift */
1633 2, /* size (0 = byte, 1 = short, 2 = long) */
1634 12, /* bitsize */
1635 FALSE, /* pc_relative */
7f266840 1636 0, /* bitpos */
c19d1205 1637 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1638 bfd_elf_generic_reloc, /* special_function */
c19d1205 1639 "R_ARM_TLS_LE12", /* name */
7f266840 1640 FALSE, /* partial_inplace */
c19d1205
ZW		 1641 0x00000fff, /* src_mask */
1642 0x00000fff, /* dst_mask */
1643 FALSE), /* pcrel_offset */
7f266840 1644
c19d1205 1645 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1646 0, /* rightshift */
1647 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1648 12, /* bitsize */
1649 FALSE, /* pc_relative */
7f266840 1650 0, /* bitpos */
c19d1205 1651 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1652 bfd_elf_generic_reloc, /* special_function */
c19d1205 1653 "R_ARM_TLS_IE12GP", /* name */
7f266840 1654 FALSE, /* partial_inplace */
c19d1205
ZW		 1655 0x00000fff, /* src_mask */
1656 0x00000fff, /* dst_mask */
1657 FALSE), /* pcrel_offset */
0855e32b 1658
34e77a92 1659 /* 112-127 private relocations. */
0855e32b
NS		 1660 EMPTY_HOWTO (112),
1661 EMPTY_HOWTO (113),
1662 EMPTY_HOWTO (114),
1663 EMPTY_HOWTO (115),
1664 EMPTY_HOWTO (116),
1665 EMPTY_HOWTO (117),
1666 EMPTY_HOWTO (118),
1667 EMPTY_HOWTO (119),
1668 EMPTY_HOWTO (120),
1669 EMPTY_HOWTO (121),
1670 EMPTY_HOWTO (122),
1671 EMPTY_HOWTO (123),
1672 EMPTY_HOWTO (124),
1673 EMPTY_HOWTO (125),
1674 EMPTY_HOWTO (126),
1675 EMPTY_HOWTO (127),
34e77a92
RS		 1676
1677 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1678 EMPTY_HOWTO (128),
1679
1680 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1681 0, /* rightshift */
1682 1, /* size (0 = byte, 1 = short, 2 = long) */
1683 0, /* bitsize */
1684 FALSE, /* pc_relative */
1685 0, /* bitpos */
1686 complain_overflow_bitfield,/* complain_on_overflow */
1687 bfd_elf_generic_reloc, /* special_function */
1688 "R_ARM_THM_TLS_DESCSEQ",/* name */
1689 FALSE, /* partial_inplace */
1690 0x00000000, /* src_mask */
1691 0x00000000, /* dst_mask */
1692 FALSE), /* pcrel_offset */
72d98d16
MG		 1693 EMPTY_HOWTO (130),
1694 EMPTY_HOWTO (131),
1695 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1696 0, /* rightshift. */
1697 1, /* size (0 = byte, 1 = short, 2 = long). */
1698 16, /* bitsize. */
1699 FALSE, /* pc_relative. */
1700 0, /* bitpos. */
1701 complain_overflow_bitfield,/* complain_on_overflow. */
1702 bfd_elf_generic_reloc, /* special_function. */
1703 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1704 FALSE, /* partial_inplace. */
1705 0x00000000, /* src_mask. */
1706 0x00000000, /* dst_mask. */
1707 FALSE), /* pcrel_offset. */
1708 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1709 0, /* rightshift. */
1710 1, /* size (0 = byte, 1 = short, 2 = long). */
1711 16, /* bitsize. */
1712 FALSE, /* pc_relative. */
1713 0, /* bitpos. */
1714 complain_overflow_bitfield,/* complain_on_overflow. */
1715 bfd_elf_generic_reloc, /* special_function. */
1716 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1717 FALSE, /* partial_inplace. */
1718 0x00000000, /* src_mask. */
1719 0x00000000, /* dst_mask. */
1720 FALSE), /* pcrel_offset. */
1721 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1722 0, /* rightshift. */
1723 1, /* size (0 = byte, 1 = short, 2 = long). */
1724 16, /* bitsize. */
1725 FALSE, /* pc_relative. */
1726 0, /* bitpos. */
1727 complain_overflow_bitfield,/* complain_on_overflow. */
1728 bfd_elf_generic_reloc, /* special_function. */
1729 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1730 FALSE, /* partial_inplace. */
1731 0x00000000, /* src_mask. */
1732 0x00000000, /* dst_mask. */
1733 FALSE), /* pcrel_offset. */
1734 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1735 0, /* rightshift. */
1736 1, /* size (0 = byte, 1 = short, 2 = long). */
1737 16, /* bitsize. */
1738 FALSE, /* pc_relative. */
1739 0, /* bitpos. */
1740 complain_overflow_bitfield,/* complain_on_overflow. */
1741 bfd_elf_generic_reloc, /* special_function. */
1742 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1743 FALSE, /* partial_inplace. */
1744 0x00000000, /* src_mask. */
1745 0x00000000, /* dst_mask. */
1746 FALSE), /* pcrel_offset. */
e5d6e09e
AV		 1747 /* Relocations for Armv8.1-M Mainline. */
1748 HOWTO (R_ARM_THM_BF16, /* type. */
1749 0, /* rightshift. */
1750 1, /* size (0 = byte, 1 = short, 2 = long). */
1751 16, /* bitsize. */
1752 TRUE, /* pc_relative. */
1753 0, /* bitpos. */
1754 complain_overflow_dont,/* do not complain_on_overflow. */
1755 bfd_elf_generic_reloc, /* special_function. */
1756 "R_ARM_THM_BF16", /* name. */
1757 FALSE, /* partial_inplace. */
1758 0x001f0ffe, /* src_mask. */
1759 0x001f0ffe, /* dst_mask. */
1760 TRUE), /* pcrel_offset. */
1889da70
AV		 1761 HOWTO (R_ARM_THM_BF12, /* type. */
1762 0, /* rightshift. */
1763 1, /* size (0 = byte, 1 = short, 2 = long). */
1764 12, /* bitsize. */
1765 TRUE, /* pc_relative. */
1766 0, /* bitpos. */
1767 complain_overflow_dont,/* do not complain_on_overflow. */
1768 bfd_elf_generic_reloc, /* special_function. */
1769 "R_ARM_THM_BF12", /* name. */
1770 FALSE, /* partial_inplace. */
1771 0x00010ffe, /* src_mask. */
1772 0x00010ffe, /* dst_mask. */
1773 TRUE), /* pcrel_offset. */
1caf72a5
AV		 1774 HOWTO (R_ARM_THM_BF18, /* type. */
1775 0, /* rightshift. */
1776 1, /* size (0 = byte, 1 = short, 2 = long). */
1777 18, /* bitsize. */
1778 TRUE, /* pc_relative. */
1779 0, /* bitpos. */
1780 complain_overflow_dont,/* do not complain_on_overflow. */
1781 bfd_elf_generic_reloc, /* special_function. */
1782 "R_ARM_THM_BF18", /* name. */
1783 FALSE, /* partial_inplace. */
1784 0x007f0ffe, /* src_mask. */
1785 0x007f0ffe, /* dst_mask. */
1786 TRUE), /* pcrel_offset. */
c19d1205
ZW		 1787};
1788
34e77a92 1789/* 160 onwards: */
5c5a4843 1790static reloc_howto_type elf32_arm_howto_table_2[8] =
34e77a92
RS		 1791{
1792 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1793 0, /* rightshift */
1794 2, /* size (0 = byte, 1 = short, 2 = long) */
1795 32, /* bitsize */
1796 FALSE, /* pc_relative */
1797 0, /* bitpos */
99059e56
RM		 1798 complain_overflow_bitfield,/* complain_on_overflow */
1799 bfd_elf_generic_reloc, /* special_function */
1800 "R_ARM_IRELATIVE", /* name */
1801 TRUE, /* partial_inplace */
1802 0xffffffff, /* src_mask */
1803 0xffffffff, /* dst_mask */
188fd7ae
CL		 1804 FALSE), /* pcrel_offset */
1805 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1806 0, /* rightshift */
1807 2, /* size (0 = byte, 1 = short, 2 = long) */
1808 32, /* bitsize */
1809 FALSE, /* pc_relative */
1810 0, /* bitpos */
1811 complain_overflow_bitfield,/* complain_on_overflow */
1812 bfd_elf_generic_reloc, /* special_function */
1813 "R_ARM_GOTFUNCDESC", /* name */
1814 FALSE, /* partial_inplace */
1815 0, /* src_mask */
1816 0xffffffff, /* dst_mask */
1817 FALSE), /* pcrel_offset */
1818 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1819 0, /* rightshift */
1820 2, /* size (0 = byte, 1 = short, 2 = long) */
1821 32, /* bitsize */
1822 FALSE, /* pc_relative */
1823 0, /* bitpos */
1824 complain_overflow_bitfield,/* complain_on_overflow */
1825 bfd_elf_generic_reloc, /* special_function */
1826 "R_ARM_GOTOFFFUNCDESC",/* name */
1827 FALSE, /* partial_inplace */
1828 0, /* src_mask */
1829 0xffffffff, /* dst_mask */
1830 FALSE), /* pcrel_offset */
1831 HOWTO (R_ARM_FUNCDESC, /* type */
1832 0, /* rightshift */
1833 2, /* size (0 = byte, 1 = short, 2 = long) */
1834 32, /* bitsize */
1835 FALSE, /* pc_relative */
1836 0, /* bitpos */
1837 complain_overflow_bitfield,/* complain_on_overflow */
1838 bfd_elf_generic_reloc, /* special_function */
1839 "R_ARM_FUNCDESC", /* name */
1840 FALSE, /* partial_inplace */
1841 0, /* src_mask */
1842 0xffffffff, /* dst_mask */
1843 FALSE), /* pcrel_offset */
1844 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1845 0, /* rightshift */
1846 2, /* size (0 = byte, 1 = short, 2 = long) */
1847 64, /* bitsize */
1848 FALSE, /* pc_relative */
1849 0, /* bitpos */
1850 complain_overflow_bitfield,/* complain_on_overflow */
1851 bfd_elf_generic_reloc, /* special_function */
1852 "R_ARM_FUNCDESC_VALUE",/* name */
1853 FALSE, /* partial_inplace */
1854 0, /* src_mask */
1855 0xffffffff, /* dst_mask */
1856 FALSE), /* pcrel_offset */
5c5a4843
CL		 1857 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1858 0, /* rightshift */
1859 2, /* size (0 = byte, 1 = short, 2 = long) */
1860 32, /* bitsize */
1861 FALSE, /* pc_relative */
1862 0, /* bitpos */
1863 complain_overflow_bitfield,/* complain_on_overflow */
1864 bfd_elf_generic_reloc, /* special_function */
1865 "R_ARM_TLS_GD32_FDPIC",/* name */
1866 FALSE, /* partial_inplace */
1867 0, /* src_mask */
1868 0xffffffff, /* dst_mask */
1869 FALSE), /* pcrel_offset */
1870 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1871 0, /* rightshift */
1872 2, /* size (0 = byte, 1 = short, 2 = long) */
1873 32, /* bitsize */
1874 FALSE, /* pc_relative */
1875 0, /* bitpos */
1876 complain_overflow_bitfield,/* complain_on_overflow */
1877 bfd_elf_generic_reloc, /* special_function */
1878 "R_ARM_TLS_LDM32_FDPIC",/* name */
1879 FALSE, /* partial_inplace */
1880 0, /* src_mask */
1881 0xffffffff, /* dst_mask */
1882 FALSE), /* pcrel_offset */
1883 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1884 0, /* rightshift */
1885 2, /* size (0 = byte, 1 = short, 2 = long) */
1886 32, /* bitsize */
1887 FALSE, /* pc_relative */
1888 0, /* bitpos */
1889 complain_overflow_bitfield,/* complain_on_overflow */
1890 bfd_elf_generic_reloc, /* special_function */
1891 "R_ARM_TLS_IE32_FDPIC",/* name */
1892 FALSE, /* partial_inplace */
1893 0, /* src_mask */
1894 0xffffffff, /* dst_mask */
1895 FALSE), /* pcrel_offset */
34e77a92 1896};
c19d1205 1897
34e77a92
RS		 1898/* 249-255 extended, currently unused, relocations: */
1899static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1900{
1901 HOWTO (R_ARM_RREL32, /* type */
1902 0, /* rightshift */
1903 0, /* size (0 = byte, 1 = short, 2 = long) */
1904 0, /* bitsize */
1905 FALSE, /* pc_relative */
1906 0, /* bitpos */
1907 complain_overflow_dont,/* complain_on_overflow */
1908 bfd_elf_generic_reloc, /* special_function */
1909 "R_ARM_RREL32", /* name */
1910 FALSE, /* partial_inplace */
1911 0, /* src_mask */
1912 0, /* dst_mask */
1913 FALSE), /* pcrel_offset */
1914
1915 HOWTO (R_ARM_RABS32, /* type */
1916 0, /* rightshift */
1917 0, /* size (0 = byte, 1 = short, 2 = long) */
1918 0, /* bitsize */
1919 FALSE, /* pc_relative */
1920 0, /* bitpos */
1921 complain_overflow_dont,/* complain_on_overflow */
1922 bfd_elf_generic_reloc, /* special_function */
1923 "R_ARM_RABS32", /* name */
1924 FALSE, /* partial_inplace */
1925 0, /* src_mask */
1926 0, /* dst_mask */
1927 FALSE), /* pcrel_offset */
1928
1929 HOWTO (R_ARM_RPC24, /* type */
1930 0, /* rightshift */
1931 0, /* size (0 = byte, 1 = short, 2 = long) */
1932 0, /* bitsize */
1933 FALSE, /* pc_relative */
1934 0, /* bitpos */
1935 complain_overflow_dont,/* complain_on_overflow */
1936 bfd_elf_generic_reloc, /* special_function */
1937 "R_ARM_RPC24", /* name */
1938 FALSE, /* partial_inplace */
1939 0, /* src_mask */
1940 0, /* dst_mask */
1941 FALSE), /* pcrel_offset */
1942
1943 HOWTO (R_ARM_RBASE, /* type */
1944 0, /* rightshift */
1945 0, /* size (0 = byte, 1 = short, 2 = long) */
1946 0, /* bitsize */
1947 FALSE, /* pc_relative */
1948 0, /* bitpos */
1949 complain_overflow_dont,/* complain_on_overflow */
1950 bfd_elf_generic_reloc, /* special_function */
1951 "R_ARM_RBASE", /* name */
1952 FALSE, /* partial_inplace */
1953 0, /* src_mask */
1954 0, /* dst_mask */
1955 FALSE) /* pcrel_offset */
1956};
1957
1958static reloc_howto_type *
1959elf32_arm_howto_from_type (unsigned int r_type)
1960{
906e58ca 1961 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1962 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1963
188fd7ae
CL		 1964 if (r_type >= R_ARM_IRELATIVE
1965 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1966 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1967
c19d1205 1968 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1969 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1970 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1971
c19d1205 1972 return NULL;
7f266840
DJ		 1973}
1974
f3185997
NC		 1975static bfd_boolean
1976elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1977 Elf_Internal_Rela * elf_reloc)
1978{
1979 unsigned int r_type;
1980
1981 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1982 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1983 {
1984 /* xgettext:c-format */
1985 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1986 abfd, r_type);
1987 bfd_set_error (bfd_error_bad_value);
1988 return FALSE;
1989 }
1990 return TRUE;
7f266840
DJ		 1991}
1992
1993struct elf32_arm_reloc_map
1994 {
1995 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1996 unsigned char elf_reloc_val;
7f266840
DJ		 1997 };
1998
1999/* All entries in this list must also be present in elf32_arm_howto_table. */
2000static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
2001 {
07d6d2b8 2002 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 2003 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 2004 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
2005 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 2006 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
2007 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
2008 {BFD_RELOC_32, R_ARM_ABS32},
2009 {BFD_RELOC_32_PCREL, R_ARM_REL32},
2010 {BFD_RELOC_8, R_ARM_ABS8},
2011 {BFD_RELOC_16, R_ARM_ABS16},
2012 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 2013 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 2014 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
2015 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
2016 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
2017 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
2018 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
2019 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 2020 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
2021 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
2022 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
2023 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
2024 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
2025 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
2026 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
2027 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 2028 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
2029 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
2030 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
2031 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 2032 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 2033 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
2034 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
2035 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 2036 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 2037 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 2038 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 2039 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 2040 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
2041 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2042 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2043 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2044 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 2045 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2046 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2047 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2048 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 2049 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2050 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2051 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2052 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
5c5a4843
CL		 2053 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2054 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2055 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
c19d1205
ZW		 2056 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2057 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 2058 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2059 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2060 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2061 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2062 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2063 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2064 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2065 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 2066 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2067 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2068 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2069 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2070 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2071 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2072 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2073 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2074 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2075 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2076 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2077 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2078 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2079 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2080 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2081 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2082 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2083 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2084 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2085 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2086 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2087 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2088 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2089 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2090 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2091 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2092 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2093 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2094 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2095 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2096 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2097 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
e5d6e09e 2098 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
1caf72a5 2099 {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16},
1889da70 2100 {BFD_RELOC_ARM_THUMB_BF13, R_ARM_THM_BF12},
1caf72a5 2101 {BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18}
7f266840
DJ		 2102 };
2103
2104static reloc_howto_type *
f1c71a59
ZW		 2105elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2106 bfd_reloc_code_real_type code)
7f266840
DJ		 2107{
2108 unsigned int i;
8029a119 2109
906e58ca 2110 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2111 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2112 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2113
c19d1205 2114 return NULL;
7f266840
DJ		 2115}
2116
157090f7
AM		 2117static reloc_howto_type *
2118elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2119 const char *r_name)
2120{
2121 unsigned int i;
2122
906e58ca 2123 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2124 if (elf32_arm_howto_table_1[i].name != NULL
2125 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2126 return &elf32_arm_howto_table_1[i];
2127
906e58ca 2128 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2129 if (elf32_arm_howto_table_2[i].name != NULL
2130 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2131 return &elf32_arm_howto_table_2[i];
2132
34e77a92
RS		 2133 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2134 if (elf32_arm_howto_table_3[i].name != NULL
2135 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2136 return &elf32_arm_howto_table_3[i];
2137
157090f7
AM		 2138 return NULL;
2139}
2140
906e58ca
NC		 2141/* Support for core dump NOTE sections. */
2142
7f266840 2143static bfd_boolean
f1c71a59 2144elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2145{
2146 int offset;
2147 size_t size;
2148
2149 switch (note->descsz)
2150 {
2151 default:
2152 return FALSE;
2153
8029a119 2154 case 148: /* Linux/ARM 32-bit. */
7f266840 2155 /* pr_cursig */
228e534f 2156 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2157
2158 /* pr_pid */
228e534f 2159 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2160
2161 /* pr_reg */
2162 offset = 72;
2163 size = 72;
2164
2165 break;
2166 }
2167
2168 /* Make a ".reg/999" section. */
2169 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2170 size, note->descpos + offset);
2171}
2172
2173static bfd_boolean
f1c71a59 2174elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2175{
2176 switch (note->descsz)
2177 {
2178 default:
2179 return FALSE;
2180
8029a119 2181 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2182 elf_tdata (abfd)->core->pid
4395ee08 2183 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2184 elf_tdata (abfd)->core->program
7f266840 2185 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2186 elf_tdata (abfd)->core->command
7f266840
DJ		 2187 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2188 }
2189
2190 /* Note that for some reason, a spurious space is tacked
2191 onto the end of the args in some (at least one anyway)
2192 implementations, so strip it off if it exists. */
7f266840 2193 {
228e534f 2194 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2195 int n = strlen (command);
2196
2197 if (0 < n && command[n - 1] == ' ')
2198 command[n - 1] = '\0';
2199 }
2200
2201 return TRUE;
2202}
2203
1f20dca5
UW		 2204static char *
2205elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2206 int note_type, ...)
2207{
2208 switch (note_type)
2209 {
2210 default:
2211 return NULL;
2212
2213 case NT_PRPSINFO:
2214 {
602f1657 2215 char data[124] ATTRIBUTE_NONSTRING;
1f20dca5
UW		 2216 va_list ap;
2217
2218 va_start (ap, note_type);
2219 memset (data, 0, sizeof (data));
2220 strncpy (data + 28, va_arg (ap, const char *), 16);
be3e27bb 2221#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2222 DIAGNOSTIC_PUSH;
be3e27bb 2223 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
95da9854
L		 2224 -Wstringop-truncation:
2225 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2226 */
95da9854
L		 2227 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2228#endif
1f20dca5 2229 strncpy (data + 44, va_arg (ap, const char *), 80);
be3e27bb 2230#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2231 DIAGNOSTIC_POP;
fe75810f 2232#endif
1f20dca5
UW		 2233 va_end (ap);
2234
2235 return elfcore_write_note (abfd, buf, bufsiz,
2236 "CORE", note_type, data, sizeof (data));
2237 }
2238
2239 case NT_PRSTATUS:
2240 {
2241 char data[148];
2242 va_list ap;
2243 long pid;
2244 int cursig;
2245 const void *greg;
2246
2247 va_start (ap, note_type);
2248 memset (data, 0, sizeof (data));
2249 pid = va_arg (ap, long);
2250 bfd_put_32 (abfd, pid, data + 24);
2251 cursig = va_arg (ap, int);
2252 bfd_put_16 (abfd, cursig, data + 12);
2253 greg = va_arg (ap, const void *);
2254 memcpy (data + 72, greg, 72);
2255 va_end (ap);
2256
2257 return elfcore_write_note (abfd, buf, bufsiz,
2258 "CORE", note_type, data, sizeof (data));
2259 }
2260 }
2261}
2262
07d6d2b8
AM		 2263#define TARGET_LITTLE_SYM arm_elf32_le_vec
2264#define TARGET_LITTLE_NAME "elf32-littlearm"
2265#define TARGET_BIG_SYM arm_elf32_be_vec
2266#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2267
2268#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2269#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2270#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2271
252b5132
RH		 2272typedef unsigned long int insn32;
2273typedef unsigned short int insn16;
2274
3a4a14e9
PB		 2275/* In lieu of proper flags, assume all EABIv4 or later objects are
2276 interworkable. */
57e8b36a 2277#define INTERWORK_FLAG(abfd) \
3a4a14e9 2278 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2279 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2280 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2281
252b5132
RH		 2282/* The linker script knows the section names for placement.
2283 The entry_names are used to do simple name mangling on the stubs.
2284 Given a function name, and its type, the stub can be found. The
9b485d32 2285 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2286#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2287#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2288
2289#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2290#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2291
c7b8f16e
JB		 2292#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2293#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2294
a504d23a
LA		 2295#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2296#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2297
845b51d6
PB		 2298#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2299#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2300
7413f23f
DJ		 2301#define STUB_ENTRY_NAME "__%s_veneer"
2302
4ba2ef8f
TP		 2303#define CMSE_PREFIX "__acle_se_"
2304
4d83e8d9
CL		 2305#define CMSE_STUB_NAME ".gnu.sgstubs"
2306
252b5132
RH		 2307/* The name of the dynamic interpreter. This is put in the .interp
2308 section. */
2309#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2310
cb10292c
CL		 2311/* FDPIC default stack size. */
2312#define DEFAULT_STACK_SIZE 0x8000
2313
0855e32b 2314static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2315{
2316 0xe08e0000, /* add r0, lr, r0 */
2317 0xe5901004, /* ldr r1, [r0,#4] */
2318 0xe12fff11, /* bx r1 */
2319};
0855e32b
NS		 2320
2321static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2322{
2323 0xe52d2004, /* push {r2} */
2324 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2325 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2326 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2327 0xe081100f, /* 2: add r1, pc */
2328 0xe12fff12, /* bx r2 */
2329 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2330 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2331 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2332};
0855e32b 2333
b4e87f2c
TC		 2334/* NOTE: [Thumb nop sequence]
2335 When adding code that transitions from Thumb to Arm the instruction that
2336 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2337 a nop for performance reasons. */
2338
7801f98f
CL		 2339/* ARM FDPIC PLT entry. */
2340/* The last 5 words contain PLT lazy fragment code and data. */
2341static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2342 {
2343 0xe59fc008, /* ldr r12, .L1 */
2344 0xe08cc009, /* add r12, r12, r9 */
2345 0xe59c9004, /* ldr r9, [r12, #4] */
2346 0xe59cf000, /* ldr pc, [r12] */
2347 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2348 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2349 0xe51fc00c, /* ldr r12, [pc, #-12] */
2350 0xe92d1000, /* push {r12} */
2351 0xe599c004, /* ldr r12, [r9, #4] */
2352 0xe599f000, /* ldr pc, [r9] */
2353 };
2354
59029f57
CL		 2355/* Thumb FDPIC PLT entry. */
2356/* The last 5 words contain PLT lazy fragment code and data. */
2357static const bfd_vma elf32_arm_fdpic_thumb_plt_entry [] =
2358 {
2359 0xc00cf8df, /* ldr.w r12, .L1 */
2360 0x0c09eb0c, /* add.w r12, r12, r9 */
2361 0x9004f8dc, /* ldr.w r9, [r12, #4] */
2362 0xf000f8dc, /* ldr.w pc, [r12] */
2363 0x00000000, /* .L1 .word foo(GOTOFFFUNCDESC) */
2364 0x00000000, /* .L2 .word foo(funcdesc_value_reloc_offset) */
2365 0xc008f85f, /* ldr.w r12, .L2 */
2366 0xcd04f84d, /* push {r12} */
2367 0xc004f8d9, /* ldr.w r12, [r9, #4] */
2368 0xf000f8d9, /* ldr.w pc, [r9] */
2369 };
2370
5e681ec4
PB		 2371#ifdef FOUR_WORD_PLT
2372
252b5132
RH		 2373/* The first entry in a procedure linkage table looks like
2374 this. It is set up so that any shared library function that is
59f2c4e7 2375 called before the relocation has been set up calls the dynamic
9b485d32 2376 linker first. */
e5a52504 2377static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2378{
2379 0xe52de004, /* str lr, [sp, #-4]! */
2380 0xe59fe010, /* ldr lr, [pc, #16] */
2381 0xe08fe00e, /* add lr, pc, lr */
2382 0xe5bef008, /* ldr pc, [lr, #8]! */
2383};
5e681ec4
PB		 2384
2385/* Subsequent entries in a procedure linkage table look like
2386 this. */
e5a52504 2387static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2388{
2389 0xe28fc600, /* add ip, pc, #NN */
2390 0xe28cca00, /* add ip, ip, #NN */
2391 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2392 0x00000000, /* unused */
2393};
5e681ec4 2394
eed94f8f 2395#else /* not FOUR_WORD_PLT */
5e681ec4 2396
5e681ec4
PB		 2397/* The first entry in a procedure linkage table looks like
2398 this. It is set up so that any shared library function that is
2399 called before the relocation has been set up calls the dynamic
2400 linker first. */
e5a52504 2401static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2402{
07d6d2b8
AM		 2403 0xe52de004, /* str lr, [sp, #-4]! */
2404 0xe59fe004, /* ldr lr, [pc, #4] */
2405 0xe08fe00e, /* add lr, pc, lr */
2406 0xe5bef008, /* ldr pc, [lr, #8]! */
2407 0x00000000, /* &GOT[0] - . */
b38cadfb 2408};
252b5132 2409
1db37fe6
YG		 2410/* By default subsequent entries in a procedure linkage table look like
2411 this. Offsets that don't fit into 28 bits will cause link error. */
2412static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2413{
2414 0xe28fc600, /* add ip, pc, #0xNN00000 */
2415 0xe28cca00, /* add ip, ip, #0xNN000 */
2416 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2417};
5e681ec4 2418
1db37fe6
YG		 2419/* When explicitly asked, we'll use this "long" entry format
2420 which can cope with arbitrary displacements. */
2421static const bfd_vma elf32_arm_plt_entry_long [] =
2422{
07d6d2b8
AM		 2423 0xe28fc200, /* add ip, pc, #0xN0000000 */
2424 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2425 0xe28cca00, /* add ip, ip, #0xNN000 */
2426 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2427};
2428
2429static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2430
eed94f8f
NC		 2431#endif /* not FOUR_WORD_PLT */
2432
2433/* The first entry in a procedure linkage table looks like this.
2434 It is set up so that any shared library function that is called before the
2435 relocation has been set up calls the dynamic linker first. */
2436static const bfd_vma elf32_thumb2_plt0_entry [] =
2437{
2438 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2439 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2440 0xf8dfb500, /* push {lr} */
2441 0x44fee008, /* ldr.w lr, [pc, #8] */
2442 /* add lr, pc */
eed94f8f 2443 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2444 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2445};
2446
2447/* Subsequent entries in a procedure linkage table for thumb only target
2448 look like this. */
2449static const bfd_vma elf32_thumb2_plt_entry [] =
2450{
2451 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2452 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2453 0x0c00f240, /* movw ip, #0xNNNN */
2454 0x0c00f2c0, /* movt ip, #0xNNNN */
2455 0xf8dc44fc, /* add ip, pc */
15ccbdd7
TC		 2456 0xe7fcf000 /* ldr.w pc, [ip] */
2457 /* b .-4 */
eed94f8f 2458};
252b5132 2459
00a97672
RS		 2460/* The format of the first entry in the procedure linkage table
2461 for a VxWorks executable. */
2462static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2463{
07d6d2b8
AM		 2464 0xe52dc008, /* str ip,[sp,#-8]! */
2465 0xe59fc000, /* ldr ip,[pc] */
2466 0xe59cf008, /* ldr pc,[ip,#8] */
2467 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2468};
00a97672
RS		 2469
2470/* The format of subsequent entries in a VxWorks executable. */
2471static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2472{
07d6d2b8
AM		 2473 0xe59fc000, /* ldr ip,[pc] */
2474 0xe59cf000, /* ldr pc,[ip] */
2475 0x00000000, /* .long @got */
2476 0xe59fc000, /* ldr ip,[pc] */
2477 0xea000000, /* b _PLT */
2478 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2479};
00a97672
RS		 2480
2481/* The format of entries in a VxWorks shared library. */
2482static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2483{
07d6d2b8
AM		 2484 0xe59fc000, /* ldr ip,[pc] */
2485 0xe79cf009, /* ldr pc,[ip,r9] */
2486 0x00000000, /* .long @got */
2487 0xe59fc000, /* ldr ip,[pc] */
2488 0xe599f008, /* ldr pc,[r9,#8] */
2489 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2490};
00a97672 2491
b7693d02
DJ		 2492/* An initial stub used if the PLT entry is referenced from Thumb code. */
2493#define PLT_THUMB_STUB_SIZE 4
2494static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2495{
2496 0x4778, /* bx pc */
b4e87f2c 2497 0xe7fd /* b .-2 */
b38cadfb 2498};
b7693d02 2499
e5a52504
MM		 2500/* The entries in a PLT when using a DLL-based target with multiple
2501 address spaces. */
906e58ca 2502static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2503{
07d6d2b8
AM		 2504 0xe51ff004, /* ldr pc, [pc, #-4] */
2505 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2506};
2507
2508/* The first entry in a procedure linkage table looks like
2509 this. It is set up so that any shared library function that is
2510 called before the relocation has been set up calls the dynamic
2511 linker first. */
2512static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2513{
2514 /* First bundle: */
2515 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2516 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2517 0xe08cc00f, /* add ip, ip, pc */
2518 0xe52dc008, /* str ip, [sp, #-8]! */
2519 /* Second bundle: */
edccdf7c
RM		 2520 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2521 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2522 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2523 0xe12fff1c, /* bx ip */
b38cadfb 2524 /* Third bundle: */
edccdf7c
RM		 2525 0xe320f000, /* nop */
2526 0xe320f000, /* nop */
2527 0xe320f000, /* nop */
b38cadfb
NC		 2528 /* .Lplt_tail: */
2529 0xe50dc004, /* str ip, [sp, #-4] */
2530 /* Fourth bundle: */
edccdf7c
RM		 2531 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2532 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2533 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2534 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2535};
2536#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2537
2538/* Subsequent entries in a procedure linkage table look like this. */
2539static const bfd_vma elf32_arm_nacl_plt_entry [] =
2540{
2541 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2542 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2543 0xe08cc00f, /* add ip, ip, pc */
2544 0xea000000, /* b .Lplt_tail */
2545};
e5a52504 2546
906e58ca
NC		 2547#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2548#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2549#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2550#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2551#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2552#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2553#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2554#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2555
461a49ca 2556enum stub_insn_type
b38cadfb
NC		 2557{
2558 THUMB16_TYPE = 1,
2559 THUMB32_TYPE,
2560 ARM_TYPE,
2561 DATA_TYPE
2562};
461a49ca 2563
48229727
JB		 2564#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2565/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2566 is inserted in arm_build_one_stub(). */
2567#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2568#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2569#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2570#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2571#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2572#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2573#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2574#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2575
2576typedef struct
2577{
07d6d2b8 2578 bfd_vma data;
b38cadfb 2579 enum stub_insn_type type;
07d6d2b8
AM		 2580 unsigned int r_type;
2581 int reloc_addend;
461a49ca
DJ		 2582} insn_sequence;
2583
b4e87f2c
TC		 2584/* See note [Thumb nop sequence] when adding a veneer. */
2585
fea2b4d6
CL		 2586/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2587 to reach the stub if necessary. */
461a49ca 2588static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2589{
07d6d2b8 2590 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2591 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2592};
906e58ca 2593
fea2b4d6
CL		 2594/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2595 available. */
461a49ca 2596static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2597{
07d6d2b8
AM		 2598 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2599 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2600 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2601};
906e58ca 2602
d3626fb0 2603/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2604static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2605{
07d6d2b8
AM		 2606 THUMB16_INSN (0xb401), /* push {r0} */
2607 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2608 THUMB16_INSN (0x4684), /* mov ip, r0 */
2609 THUMB16_INSN (0xbc01), /* pop {r0} */
2610 THUMB16_INSN (0x4760), /* bx ip */
2611 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2612 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2613};
906e58ca 2614
80c135e5
TP		 2615/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2616static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2617{
07d6d2b8 2618 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2619 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2620};
2621
d5a67c02
AV		 2622/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2623 M-profile architectures. */
2624static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2625{
2626 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2627 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2628 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2629};
2630
d3626fb0
CL		 2631/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2632 allowed. */
2633static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2634{
07d6d2b8 2635 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2636 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2637 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2638 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2639 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2640};
d3626fb0 2641
fea2b4d6
CL		 2642/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2643 available. */
461a49ca 2644static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2645{
07d6d2b8 2646 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2647 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8 2648 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2649 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2650};
906e58ca 2651
fea2b4d6
CL		 2652/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2653 one, when the destination is close enough. */
461a49ca 2654static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2655{
07d6d2b8 2656 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2657 THUMB16_INSN (0xe7fd), /* b .-2 */
b38cadfb
NC		 2658 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2659};
c820be07 2660
cf3eccff 2661/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2662 blx to reach the stub if necessary. */
cf3eccff 2663static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2664{
07d6d2b8
AM		 2665 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2666 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2667 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2668};
906e58ca 2669
cf3eccff
DJ		 2670/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2671 blx to reach the stub if necessary. We can not add into pc;
2672 it is not guaranteed to mode switch (different in ARMv6 and
2673 ARMv7). */
2674static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2675{
07d6d2b8
AM		 2676 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2677 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2678 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2679 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2680};
cf3eccff 2681
ebe24dd4
CL		 2682/* V4T ARM -> ARM long branch stub, PIC. */
2683static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2684{
07d6d2b8
AM		 2685 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2686 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2687 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2688 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2689};
ebe24dd4
CL		 2690
2691/* V4T Thumb -> ARM long branch stub, PIC. */
2692static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2693{
07d6d2b8 2694 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2695 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2696 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2697 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2698 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2699};
ebe24dd4 2700
d3626fb0
CL		 2701/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2702 architectures. */
ebe24dd4 2703static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2704{
07d6d2b8
AM		 2705 THUMB16_INSN (0xb401), /* push {r0} */
2706 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2707 THUMB16_INSN (0x46fc), /* mov ip, pc */
2708 THUMB16_INSN (0x4484), /* add ip, r0 */
2709 THUMB16_INSN (0xbc01), /* pop {r0} */
2710 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2711 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2712};
ebe24dd4 2713
d3626fb0
CL		 2714/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2715 allowed. */
2716static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2717{
07d6d2b8 2718 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2719 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2720 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2721 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2722 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2723 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2724};
d3626fb0 2725
0855e32b
NS		 2726/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2727 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2728static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2729{
07d6d2b8
AM		 2730 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2731 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2732 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2733};
2734
2735/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2736 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2737static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2738{
07d6d2b8 2739 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2740 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2741 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2742 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2743 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2744};
2745
7a89b94e
NC		 2746/* NaCl ARM -> ARM long branch stub. */
2747static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2748{
2749 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2750 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2751 ARM_INSN (0xe12fff1c), /* bx ip */
2752 ARM_INSN (0xe320f000), /* nop */
2753 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2754 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2755 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2756 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2757};
2758
2759/* NaCl ARM -> ARM long branch stub, PIC. */
2760static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2761{
2762 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2763 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2764 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2765 ARM_INSN (0xe12fff1c), /* bx ip */
2766 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2767 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2768 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2769 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2770};
2771
4ba2ef8f
TP		 2772/* Stub used for transition to secure state (aka SG veneer). */
2773static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2774{
2775 THUMB32_INSN (0xe97fe97f), /* sg. */
2776 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2777};
2778
7a89b94e 2779
48229727
JB		 2780/* Cortex-A8 erratum-workaround stubs. */
2781
2782/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2783 can't use a conditional branch to reach this stub). */
2784
2785static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2786{
07d6d2b8 2787 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2788 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2789 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2790};
48229727
JB		 2791
2792/* Stub used for b.w and bl.w instructions. */
2793
2794static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2795{
2796 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2797};
48229727
JB		 2798
2799static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2800{
2801 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2802};
48229727
JB		 2803
2804/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2805 instruction (which switches to ARM mode) to point to this stub. Jump to the
2806 real destination using an ARM-mode branch. */
2807
2808static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2809{
2810 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2811};
48229727 2812
9553db3c
NC		 2813/* For each section group there can be a specially created linker section
2814 to hold the stubs for that group. The name of the stub section is based
2815 upon the name of another section within that group with the suffix below
2816 applied.
2817
2818 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2819 create what appeared to be a linker stub section when it actually
2820 contained user code/data. For example, consider this fragment:
b38cadfb 2821
9553db3c
NC		 2822 const char * stubborn_problems[] = { "np" };
2823
2824 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2825 section called:
2826
2827 .data.rel.local.stubborn_problems
2828
2829 This then causes problems in arm32_arm_build_stubs() as it triggers:
2830
2831 // Ignore non-stub sections.
2832 if (!strstr (stub_sec->name, STUB_SUFFIX))
2833 continue;
2834
2835 And so the section would be ignored instead of being processed. Hence
2836 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2837 C identifier. */
2838#define STUB_SUFFIX ".__stub"
906e58ca 2839
738a79f6
CL		 2840/* One entry per long/short branch stub defined above. */
2841#define DEF_STUBS \
2842 DEF_STUB(long_branch_any_any) \
2843 DEF_STUB(long_branch_v4t_arm_thumb) \
2844 DEF_STUB(long_branch_thumb_only) \
2845 DEF_STUB(long_branch_v4t_thumb_thumb) \
2846 DEF_STUB(long_branch_v4t_thumb_arm) \
2847 DEF_STUB(short_branch_v4t_thumb_arm) \
2848 DEF_STUB(long_branch_any_arm_pic) \
2849 DEF_STUB(long_branch_any_thumb_pic) \
2850 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2851 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2852 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2853 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2854 DEF_STUB(long_branch_any_tls_pic) \
2855 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2856 DEF_STUB(long_branch_arm_nacl) \
2857 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2858 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2859 DEF_STUB(a8_veneer_b_cond) \
2860 DEF_STUB(a8_veneer_b) \
2861 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2862 DEF_STUB(a8_veneer_blx) \
2863 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2864 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2865
2866#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2867enum elf32_arm_stub_type
2868{
906e58ca 2869 arm_stub_none,
738a79f6 2870 DEF_STUBS
4f4faa4d 2871 max_stub_type
738a79f6
CL		 2872};
2873#undef DEF_STUB
2874
8d9d9490
TP		 2875/* Note the first a8_veneer type. */
2876const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2877
738a79f6
CL		 2878typedef struct
2879{
d3ce72d0 2880 const insn_sequence* template_sequence;
738a79f6
CL		 2881 int template_size;
2882} stub_def;
2883
2884#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2885static const stub_def stub_definitions[] =
2886{
738a79f6
CL		 2887 {NULL, 0},
2888 DEF_STUBS
906e58ca
NC		 2889};
2890
2891struct elf32_arm_stub_hash_entry
2892{
2893 /* Base hash table entry structure. */
2894 struct bfd_hash_entry root;
2895
2896 /* The stub section. */
2897 asection *stub_sec;
2898
2899 /* Offset within stub_sec of the beginning of this stub. */
2900 bfd_vma stub_offset;
2901
2902 /* Given the symbol's value and its section we can determine its final
2903 value when building the stubs (so the stub knows where to jump). */
2904 bfd_vma target_value;
2905 asection *target_section;
2906
8d9d9490
TP		 2907 /* Same as above but for the source of the branch to the stub. Used for
2908 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2909 such, source section does not need to be recorded since Cortex-A8 erratum
2910 workaround stubs are only generated when both source and target are in the
2911 same section. */
2912 bfd_vma source_value;
48229727
JB		 2913
2914 /* The instruction which caused this stub to be generated (only valid for
2915 Cortex-A8 erratum workaround stubs at present). */
2916 unsigned long orig_insn;
2917
461a49ca 2918 /* The stub type. */
906e58ca 2919 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2920 /* Its encoding size in bytes. */
2921 int stub_size;
2922 /* Its template. */
2923 const insn_sequence *stub_template;
2924 /* The size of the template (number of entries). */
2925 int stub_template_size;
906e58ca
NC		 2926
2927 /* The symbol table entry, if any, that this was derived from. */
2928 struct elf32_arm_link_hash_entry *h;
2929
35fc36a8
RS		 2930 /* Type of branch. */
2931 enum arm_st_branch_type branch_type;
906e58ca
NC		 2932
2933 /* Where this stub is being called from, or, in the case of combined
2934 stub sections, the first input section in the group. */
2935 asection *id_sec;
7413f23f
DJ		 2936
2937 /* The name for the local symbol at the start of this stub. The
2938 stub name in the hash table has to be unique; this does not, so
2939 it can be friendlier. */
2940 char *output_name;
906e58ca
NC		 2941};
2942
e489d0ae
PB		 2943/* Used to build a map of a section. This is required for mixed-endian
2944 code/data. */
2945
2946typedef struct elf32_elf_section_map
2947{
2948 bfd_vma vma;
2949 char type;
2950}
2951elf32_arm_section_map;
2952
c7b8f16e
JB		 2953/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2954
2955typedef enum
2956{
2957 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2958 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2959 VFP11_ERRATUM_ARM_VENEER,
2960 VFP11_ERRATUM_THUMB_VENEER
2961}
2962elf32_vfp11_erratum_type;
2963
2964typedef struct elf32_vfp11_erratum_list
2965{
2966 struct elf32_vfp11_erratum_list *next;
2967 bfd_vma vma;
2968 union
2969 {
2970 struct
2971 {
2972 struct elf32_vfp11_erratum_list *veneer;
2973 unsigned int vfp_insn;
2974 } b;
2975 struct
2976 {
2977 struct elf32_vfp11_erratum_list *branch;
2978 unsigned int id;
2979 } v;
2980 } u;
2981 elf32_vfp11_erratum_type type;
2982}
2983elf32_vfp11_erratum_list;
2984
a504d23a
LA		 2985/* Information about a STM32L4XX erratum veneer, or a branch to such a
2986 veneer. */
2987typedef enum
2988{
2989 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2990 STM32L4XX_ERRATUM_VENEER
2991}
2992elf32_stm32l4xx_erratum_type;
2993
2994typedef struct elf32_stm32l4xx_erratum_list
2995{
2996 struct elf32_stm32l4xx_erratum_list *next;
2997 bfd_vma vma;
2998 union
2999 {
3000 struct
3001 {
3002 struct elf32_stm32l4xx_erratum_list *veneer;
3003 unsigned int insn;
3004 } b;
3005 struct
3006 {
3007 struct elf32_stm32l4xx_erratum_list *branch;
3008 unsigned int id;
3009 } v;
3010 } u;
3011 elf32_stm32l4xx_erratum_type type;
3012}
3013elf32_stm32l4xx_erratum_list;
3014
2468f9c9
PB		 3015typedef enum
3016{
3017 DELETE_EXIDX_ENTRY,
3018 INSERT_EXIDX_CANTUNWIND_AT_END
3019}
3020arm_unwind_edit_type;
3021
3022/* A (sorted) list of edits to apply to an unwind table. */
3023typedef struct arm_unwind_table_edit
3024{
3025 arm_unwind_edit_type type;
3026 /* Note: we sometimes want to insert an unwind entry corresponding to a
3027 section different from the one we're currently writing out, so record the
3028 (text) section this edit relates to here. */
3029 asection *linked_section;
3030 unsigned int index;
3031 struct arm_unwind_table_edit *next;
3032}
3033arm_unwind_table_edit;
3034
8e3de13a 3035typedef struct _arm_elf_section_data
e489d0ae 3036{
2468f9c9 3037 /* Information about mapping symbols. */
e489d0ae 3038 struct bfd_elf_section_data elf;
8e3de13a 3039 unsigned int mapcount;
c7b8f16e 3040 unsigned int mapsize;
e489d0ae 3041 elf32_arm_section_map *map;
2468f9c9 3042 /* Information about CPU errata. */
c7b8f16e
JB		 3043 unsigned int erratumcount;
3044 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 3045 unsigned int stm32l4xx_erratumcount;
3046 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 3047 unsigned int additional_reloc_count;
2468f9c9
PB		 3048 /* Information about unwind tables. */
3049 union
3050 {
3051 /* Unwind info attached to a text section. */
3052 struct
3053 {
3054 asection *arm_exidx_sec;
3055 } text;
3056
3057 /* Unwind info attached to an .ARM.exidx section. */
3058 struct
3059 {
3060 arm_unwind_table_edit *unwind_edit_list;
3061 arm_unwind_table_edit *unwind_edit_tail;
3062 } exidx;
3063 } u;
8e3de13a
NC		 3064}
3065_arm_elf_section_data;
e489d0ae
PB		 3066
3067#define elf32_arm_section_data(sec) \
8e3de13a 3068 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 3069
48229727
JB		 3070/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3071 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3072 so may be created multiple times: we use an array of these entries whilst
3073 relaxing which we can refresh easily, then create stubs for each potentially
3074 erratum-triggering instruction once we've settled on a solution. */
3075
b38cadfb
NC		 3076struct a8_erratum_fix
3077{
48229727
JB		 3078 bfd *input_bfd;
3079 asection *section;
3080 bfd_vma offset;
8d9d9490 3081 bfd_vma target_offset;
48229727
JB		 3082 unsigned long orig_insn;
3083 char *stub_name;
3084 enum elf32_arm_stub_type stub_type;
35fc36a8 3085 enum arm_st_branch_type branch_type;
48229727
JB		 3086};
3087
3088/* A table of relocs applied to branches which might trigger Cortex-A8
3089 erratum. */
3090
b38cadfb
NC		 3091struct a8_erratum_reloc
3092{
48229727
JB		 3093 bfd_vma from;
3094 bfd_vma destination;
92750f34
DJ		 3095 struct elf32_arm_link_hash_entry *hash;
3096 const char *sym_name;
48229727 3097 unsigned int r_type;
35fc36a8 3098 enum arm_st_branch_type branch_type;
48229727
JB		 3099 bfd_boolean non_a8_stub;
3100};
3101
ba93b8ac
DJ		 3102/* The size of the thread control block. */
3103#define TCB_SIZE 8
3104
34e77a92
RS		 3105/* ARM-specific information about a PLT entry, over and above the usual
3106 gotplt_union. */
b38cadfb
NC		 3107struct arm_plt_info
3108{
34e77a92
RS		 3109 /* We reference count Thumb references to a PLT entry separately,
3110 so that we can emit the Thumb trampoline only if needed. */
3111 bfd_signed_vma thumb_refcount;
3112
3113 /* Some references from Thumb code may be eliminated by BL->BLX
3114 conversion, so record them separately. */
3115 bfd_signed_vma maybe_thumb_refcount;
3116
3117 /* How many of the recorded PLT accesses were from non-call relocations.
3118 This information is useful when deciding whether anything takes the
3119 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3120 non-call references to the function should resolve directly to the
3121 real runtime target. */
3122 unsigned int noncall_refcount;
3123
3124 /* Since PLT entries have variable size if the Thumb prologue is
3125 used, we need to record the index into .got.plt instead of
3126 recomputing it from the PLT offset. */
3127 bfd_signed_vma got_offset;
3128};
3129
3130/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 3131struct arm_local_iplt_info
3132{
34e77a92
RS		 3133 /* The information that is usually found in the generic ELF part of
3134 the hash table entry. */
3135 union gotplt_union root;
3136
3137 /* The information that is usually found in the ARM-specific part of
3138 the hash table entry. */
3139 struct arm_plt_info arm;
3140
3141 /* A list of all potential dynamic relocations against this symbol. */
3142 struct elf_dyn_relocs *dyn_relocs;
3143};
3144
e8b09b87
CL		 3145/* Structure to handle FDPIC support for local functions. */
3146struct fdpic_local {
3147 unsigned int funcdesc_cnt;
3148 unsigned int gotofffuncdesc_cnt;
3149 int funcdesc_offset;
3150};
3151
0ffa91dd 3152struct elf_arm_obj_tdata
ba93b8ac
DJ		 3153{
3154 struct elf_obj_tdata root;
3155
3156 /* tls_type for each local got entry. */
3157 char *local_got_tls_type;
ee065d83 3158
0855e32b
NS		 3159 /* GOTPLT entries for TLS descriptors. */
3160 bfd_vma *local_tlsdesc_gotent;
3161
34e77a92
RS		 3162 /* Information for local symbols that need entries in .iplt. */
3163 struct arm_local_iplt_info **local_iplt;
3164
bf21ed78
MS		 3165 /* Zero to warn when linking objects with incompatible enum sizes. */
3166 int no_enum_size_warning;
a9dc9481
JM		 3167
3168 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3169 int no_wchar_size_warning;
e8b09b87
CL		 3170
3171 /* Maintains FDPIC counters and funcdesc info. */
3172 struct fdpic_local *local_fdpic_cnts;
ba93b8ac
DJ		 3173};
3174
0ffa91dd
NC		 3175#define elf_arm_tdata(bfd) \
3176 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3177
0ffa91dd
NC		 3178#define elf32_arm_local_got_tls_type(bfd) \
3179 (elf_arm_tdata (bfd)->local_got_tls_type)
3180
0855e32b
NS		 3181#define elf32_arm_local_tlsdesc_gotent(bfd) \
3182 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3183
34e77a92
RS		 3184#define elf32_arm_local_iplt(bfd) \
3185 (elf_arm_tdata (bfd)->local_iplt)
3186
e8b09b87
CL		 3187#define elf32_arm_local_fdpic_cnts(bfd) \
3188 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3189
0ffa91dd
NC		 3190#define is_arm_elf(bfd) \
3191 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3192 && elf_tdata (bfd) != NULL \
4dfe6ac6 3193 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3194
3195static bfd_boolean
3196elf32_arm_mkobject (bfd *abfd)
3197{
0ffa91dd 3198 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3199 ARM_ELF_DATA);
ba93b8ac
DJ		 3200}
3201
ba93b8ac
DJ		 3202#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3203
e8b09b87
CL		 3204/* Structure to handle FDPIC support for extern functions. */
3205struct fdpic_global {
3206 unsigned int gotofffuncdesc_cnt;
3207 unsigned int gotfuncdesc_cnt;
3208 unsigned int funcdesc_cnt;
3209 int funcdesc_offset;
3210 int gotfuncdesc_offset;
3211};
3212
ba96a88f 3213/* Arm ELF linker hash entry. */
252b5132 3214struct elf32_arm_link_hash_entry
b38cadfb
NC		 3215{
3216 struct elf_link_hash_entry root;
252b5132 3217
b38cadfb
NC		 3218 /* ARM-specific PLT information. */
3219 struct arm_plt_info plt;
ba93b8ac
DJ		 3220
3221#define GOT_UNKNOWN 0
3222#define GOT_NORMAL 1
3223#define GOT_TLS_GD 2
3224#define GOT_TLS_IE 4
0855e32b
NS		 3225#define GOT_TLS_GDESC 8
3226#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3227 unsigned int tls_type : 8;
34e77a92 3228
b38cadfb
NC		 3229 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3230 unsigned int is_iplt : 1;
34e77a92 3231
b38cadfb 3232 unsigned int unused : 23;
a4fd1a8e 3233
b38cadfb
NC		 3234 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3235 starting at the end of the jump table. */
3236 bfd_vma tlsdesc_got;
0855e32b 3237
b38cadfb
NC		 3238 /* The symbol marking the real symbol location for exported thumb
3239 symbols with Arm stubs. */
3240 struct elf_link_hash_entry *export_glue;
906e58ca 3241
b38cadfb 3242 /* A pointer to the most recently used stub hash entry against this
8029a119 3243 symbol. */
b38cadfb 3244 struct elf32_arm_stub_hash_entry *stub_cache;
e8b09b87
CL		 3245
3246 /* Counter for FDPIC relocations against this symbol. */
3247 struct fdpic_global fdpic_cnts;
b38cadfb 3248};
252b5132 3249
252b5132 3250/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3251#define elf32_arm_link_hash_traverse(table, func, info) \
3252 (elf_link_hash_traverse \
3253 (&(table)->root, \
b7693d02 3254 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3255 (info)))
3256
3257/* Get the ARM elf linker hash table from a link_info structure. */
3258#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3259 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3260 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3261
906e58ca
NC		 3262#define arm_stub_hash_lookup(table, string, create, copy) \
3263 ((struct elf32_arm_stub_hash_entry *) \
3264 bfd_hash_lookup ((table), (string), (create), (copy)))
3265
21d799b5
NC		 3266/* Array to keep track of which stub sections have been created, and
3267 information on stub grouping. */
3268struct map_stub
3269{
3270 /* This is the section to which stubs in the group will be
3271 attached. */
3272 asection *link_sec;
3273 /* The stub section. */
3274 asection *stub_sec;
3275};
3276
0855e32b
NS		 3277#define elf32_arm_compute_jump_table_size(htab) \
3278 ((htab)->next_tls_desc_index * 4)
3279
9b485d32 3280/* ARM ELF linker hash table. */
252b5132 3281struct elf32_arm_link_hash_table
906e58ca
NC		 3282{
3283 /* The main hash table. */
3284 struct elf_link_hash_table root;
252b5132 3285
906e58ca
NC		 3286 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3287 bfd_size_type thumb_glue_size;
252b5132 3288
906e58ca
NC		 3289 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3290 bfd_size_type arm_glue_size;
252b5132 3291
906e58ca
NC		 3292 /* The size in bytes of section containing the ARMv4 BX veneers. */
3293 bfd_size_type bx_glue_size;
845b51d6 3294
906e58ca
NC		 3295 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3296 veneer has been populated. */
3297 bfd_vma bx_glue_offset[15];
845b51d6 3298
906e58ca
NC		 3299 /* The size in bytes of the section containing glue for VFP11 erratum
3300 veneers. */
3301 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3302
a504d23a
LA		 3303 /* The size in bytes of the section containing glue for STM32L4XX erratum
3304 veneers. */
3305 bfd_size_type stm32l4xx_erratum_glue_size;
3306
48229727
JB		 3307 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3308 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3309 elf32_arm_write_section(). */
3310 struct a8_erratum_fix *a8_erratum_fixes;
3311 unsigned int num_a8_erratum_fixes;
3312
906e58ca
NC		 3313 /* An arbitrary input BFD chosen to hold the glue sections. */
3314 bfd * bfd_of_glue_owner;
ba96a88f 3315
906e58ca
NC		 3316 /* Nonzero to output a BE8 image. */
3317 int byteswap_code;
e489d0ae 3318
906e58ca
NC		 3319 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3320 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3321 int target1_is_rel;
9c504268 3322
906e58ca
NC		 3323 /* The relocation to use for R_ARM_TARGET2 relocations. */
3324 int target2_reloc;
eb043451 3325
906e58ca
NC		 3326 /* 0 = Ignore R_ARM_V4BX.
3327 1 = Convert BX to MOV PC.
3328 2 = Generate v4 interworing stubs. */
3329 int fix_v4bx;
319850b4 3330
48229727
JB		 3331 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3332 int fix_cortex_a8;
3333
2de70689
MGD		 3334 /* Whether we should fix the ARM1176 BLX immediate issue. */
3335 int fix_arm1176;
3336
906e58ca
NC		 3337 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3338 int use_blx;
33bfe774 3339
906e58ca
NC		 3340 /* What sort of code sequences we should look for which may trigger the
3341 VFP11 denorm erratum. */
3342 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3343
906e58ca
NC		 3344 /* Global counter for the number of fixes we have emitted. */
3345 int num_vfp11_fixes;
c7b8f16e 3346
a504d23a
LA		 3347 /* What sort of code sequences we should look for which may trigger the
3348 STM32L4XX erratum. */
3349 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3350
3351 /* Global counter for the number of fixes we have emitted. */
3352 int num_stm32l4xx_fixes;
3353
906e58ca
NC		 3354 /* Nonzero to force PIC branch veneers. */
3355 int pic_veneer;
27e55c4d 3356
906e58ca
NC		 3357 /* The number of bytes in the initial entry in the PLT. */
3358 bfd_size_type plt_header_size;
e5a52504 3359
906e58ca
NC		 3360 /* The number of bytes in the subsequent PLT etries. */
3361 bfd_size_type plt_entry_size;
e5a52504 3362
906e58ca 3363 /* True if the target uses REL relocations. */
f3185997 3364 bfd_boolean use_rel;
4e7fd91e 3365
54ddd295
TP		 3366 /* Nonzero if import library must be a secure gateway import library
3367 as per ARMv8-M Security Extensions. */
3368 int cmse_implib;
3369
0955507f
TP		 3370 /* The import library whose symbols' address must remain stable in
3371 the import library generated. */
3372 bfd *in_implib_bfd;
3373
0855e32b
NS		 3374 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3375 bfd_vma next_tls_desc_index;
3376
3377 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3378 bfd_vma num_tls_desc;
3379
906e58ca
NC		 3380 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3381 asection *srelplt2;
00a97672 3382
0855e32b
NS		 3383 /* Offset in .plt section of tls_arm_trampoline. */
3384 bfd_vma tls_trampoline;
3385
5c5a4843 3386 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
906e58ca
NC		 3387 union
3388 {
3389 bfd_signed_vma refcount;
3390 bfd_vma offset;
3391 } tls_ldm_got;
b7693d02 3392
906e58ca
NC		 3393 /* For convenience in allocate_dynrelocs. */
3394 bfd * obfd;
3395
0855e32b
NS		 3396 /* The amount of space used by the reserved portion of the sgotplt
3397 section, plus whatever space is used by the jump slots. */
3398 bfd_vma sgotplt_jump_table_size;
3399
906e58ca
NC		 3400 /* The stub hash table. */
3401 struct bfd_hash_table stub_hash_table;
3402
3403 /* Linker stub bfd. */
3404 bfd *stub_bfd;
3405
3406 /* Linker call-backs. */
6bde4c52
TP		 3407 asection * (*add_stub_section) (const char *, asection *, asection *,
3408 unsigned int);
906e58ca
NC		 3409 void (*layout_sections_again) (void);
3410
3411 /* Array to keep track of which stub sections have been created, and
3412 information on stub grouping. */
21d799b5 3413 struct map_stub *stub_group;
906e58ca 3414
4ba2ef8f
TP		 3415 /* Input stub section holding secure gateway veneers. */
3416 asection *cmse_stub_sec;
3417
0955507f
TP		 3418 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3419 start to be allocated. */
3420 bfd_vma new_cmse_stub_offset;
3421
fe33d2fa 3422 /* Number of elements in stub_group. */
7292b3ac 3423 unsigned int top_id;
fe33d2fa 3424
906e58ca
NC		 3425 /* Assorted information used by elf32_arm_size_stubs. */
3426 unsigned int bfd_count;
7292b3ac 3427 unsigned int top_index;
906e58ca 3428 asection **input_list;
617a5ada
CL		 3429
3430 /* True if the target system uses FDPIC. */
3431 int fdpic_p;
e8b09b87
CL		 3432
3433 /* Fixup section. Used for FDPIC. */
3434 asection *srofixup;
906e58ca 3435};
252b5132 3436
e8b09b87
CL		 3437/* Add an FDPIC read-only fixup. */
3438static void
3439arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3440{
3441 bfd_vma fixup_offset;
3442
3443 fixup_offset = srofixup->reloc_count++ * 4;
3444 BFD_ASSERT (fixup_offset < srofixup->size);
3445 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3446}
3447
a504d23a
LA		 3448static inline int
3449ctz (unsigned int mask)
3450{
3451#if GCC_VERSION >= 3004
3452 return __builtin_ctz (mask);
3453#else
3454 unsigned int i;
3455
3456 for (i = 0; i < 8 * sizeof (mask); i++)
3457 {
3458 if (mask & 0x1)
3459 break;
3460 mask = (mask >> 1);
3461 }
3462 return i;
3463#endif
3464}
3465
3466static inline int
b25e998d 3467elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3468{
3469#if GCC_VERSION >= 3004
3470 return __builtin_popcount (mask);
3471#else
b25e998d
CG		 3472 unsigned int i;
3473 int sum = 0;
a504d23a
LA		 3474
3475 for (i = 0; i < 8 * sizeof (mask); i++)
3476 {
3477 if (mask & 0x1)
3478 sum++;
3479 mask = (mask >> 1);
3480 }
3481 return sum;
3482#endif
3483}
3484
e8b09b87
CL		 3485static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3486 asection *sreloc, Elf_Internal_Rela *rel);
3487
3488static void
3489arm_elf_fill_funcdesc(bfd *output_bfd,
3490 struct bfd_link_info *info,
3491 int *funcdesc_offset,
3492 int dynindx,
3493 int offset,
3494 bfd_vma addr,
3495 bfd_vma dynreloc_value,
3496 bfd_vma seg)
3497{
3498 if ((*funcdesc_offset & 1) == 0)
3499 {
3500 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3501 asection *sgot = globals->root.sgot;
3502
3503 if (bfd_link_pic(info))
3504 {
3505 asection *srelgot = globals->root.srelgot;
3506 Elf_Internal_Rela outrel;
3507
3508 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3509 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3510 outrel.r_addend = 0;
3511
3512 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3513 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3514 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3515 }
3516 else
3517 {
3518 struct elf_link_hash_entry *hgot = globals->root.hgot;
3519 bfd_vma got_value = hgot->root.u.def.value
3520 + hgot->root.u.def.section->output_section->vma
3521 + hgot->root.u.def.section->output_offset;
3522
3523 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3524 sgot->output_section->vma + sgot->output_offset
3525 + offset);
3526 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3527 sgot->output_section->vma + sgot->output_offset
3528 + offset + 4);
3529 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3530 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3531 }
3532 *funcdesc_offset |= 1;
3533 }
3534}
3535
780a67af
NC		 3536/* Create an entry in an ARM ELF linker hash table. */
3537
3538static struct bfd_hash_entry *
57e8b36a 3539elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3540 struct bfd_hash_table * table,
3541 const char * string)
780a67af
NC		 3542{
3543 struct elf32_arm_link_hash_entry * ret =
3544 (struct elf32_arm_link_hash_entry *) entry;
3545
3546 /* Allocate the structure if it has not already been allocated by a
3547 subclass. */
906e58ca 3548 if (ret == NULL)
21d799b5 3549 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3550 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3551 if (ret == NULL)
780a67af
NC		 3552 return (struct bfd_hash_entry *) ret;
3553
3554 /* Call the allocation method of the superclass. */
3555 ret = ((struct elf32_arm_link_hash_entry *)
3556 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3557 table, string));
57e8b36a 3558 if (ret != NULL)
b7693d02 3559 {
ba93b8ac 3560 ret->tls_type = GOT_UNKNOWN;
0855e32b 3561 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3562 ret->plt.thumb_refcount = 0;
3563 ret->plt.maybe_thumb_refcount = 0;
3564 ret->plt.noncall_refcount = 0;
3565 ret->plt.got_offset = -1;
3566 ret->is_iplt = FALSE;
a4fd1a8e 3567 ret->export_glue = NULL;
906e58ca
NC		 3568
3569 ret->stub_cache = NULL;
e8b09b87
CL		 3570
3571 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3572 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3573 ret->fdpic_cnts.funcdesc_cnt = 0;
3574 ret->fdpic_cnts.funcdesc_offset = -1;
3575 ret->fdpic_cnts.gotfuncdesc_offset = -1;
b7693d02 3576 }
780a67af
NC		 3577
3578 return (struct bfd_hash_entry *) ret;
3579}
3580
34e77a92
RS		 3581/* Ensure that we have allocated bookkeeping structures for ABFD's local
3582 symbols. */
3583
3584static bfd_boolean
3585elf32_arm_allocate_local_sym_info (bfd *abfd)
3586{
3587 if (elf_local_got_refcounts (abfd) == NULL)
3588 {
3589 bfd_size_type num_syms;
3590 bfd_size_type size;
3591 char *data;
3592
3593 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3594 size = num_syms * (sizeof (bfd_signed_vma)
3595 + sizeof (struct arm_local_iplt_info *)
3596 + sizeof (bfd_vma)
e8b09b87
CL		 3597 + sizeof (char)
3598 + sizeof (struct fdpic_local));
34e77a92
RS		 3599 data = bfd_zalloc (abfd, size);
3600 if (data == NULL)
3601 return FALSE;
3602
e8b09b87
CL		 3603 elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
3604 data += num_syms * sizeof (struct fdpic_local);
3605
34e77a92
RS		 3606 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3607 data += num_syms * sizeof (bfd_signed_vma);
3608
3609 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3610 data += num_syms * sizeof (struct arm_local_iplt_info *);
3611
3612 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3613 data += num_syms * sizeof (bfd_vma);
3614
3615 elf32_arm_local_got_tls_type (abfd) = data;
3616 }
3617 return TRUE;
3618}
3619
3620/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3621 to input bfd ABFD. Create the information if it doesn't already exist.
3622 Return null if an allocation fails. */
3623
3624static struct arm_local_iplt_info *
3625elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3626{
3627 struct arm_local_iplt_info **ptr;
3628
3629 if (!elf32_arm_allocate_local_sym_info (abfd))
3630 return NULL;
3631
3632 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3633 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3634 if (*ptr == NULL)
3635 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3636 return *ptr;
3637}
3638
3639/* Try to obtain PLT information for the symbol with index R_SYMNDX
3640 in ABFD's symbol table. If the symbol is global, H points to its
3641 hash table entry, otherwise H is null.
3642
3643 Return true if the symbol does have PLT information. When returning
3644 true, point *ROOT_PLT at the target-independent reference count/offset
3645 union and *ARM_PLT at the ARM-specific information. */
3646
3647static bfd_boolean
4ba2ef8f
TP		 3648elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3649 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3650 unsigned long r_symndx, union gotplt_union **root_plt,
3651 struct arm_plt_info **arm_plt)
3652{
3653 struct arm_local_iplt_info *local_iplt;
3654
4ba2ef8f
TP		 3655 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3656 return FALSE;
3657
34e77a92
RS		 3658 if (h != NULL)
3659 {
3660 *root_plt = &h->root.plt;
3661 *arm_plt = &h->plt;
3662 return TRUE;
3663 }
3664
3665 if (elf32_arm_local_iplt (abfd) == NULL)
3666 return FALSE;
3667
3668 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3669 if (local_iplt == NULL)
3670 return FALSE;
3671
3672 *root_plt = &local_iplt->root;
3673 *arm_plt = &local_iplt->arm;
3674 return TRUE;
3675}
3676
59029f57
CL		 3677static bfd_boolean using_thumb_only (struct elf32_arm_link_hash_table *globals);
3678
34e77a92
RS		 3679/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3680 before it. */
3681
3682static bfd_boolean
3683elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3684 struct arm_plt_info *arm_plt)
3685{
3686 struct elf32_arm_link_hash_table *htab;
3687
3688 htab = elf32_arm_hash_table (info);
59029f57
CL		 3689
3690 return (!using_thumb_only(htab) && (arm_plt->thumb_refcount != 0
3691 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0)));
34e77a92
RS		 3692}
3693
3694/* Return a pointer to the head of the dynamic reloc list that should
3695 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3696 ABFD's symbol table. Return null if an error occurs. */
3697
3698static struct elf_dyn_relocs **
3699elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3700 Elf_Internal_Sym *isym)
3701{
3702 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3703 {
3704 struct arm_local_iplt_info *local_iplt;
3705
3706 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3707 if (local_iplt == NULL)
3708 return NULL;
3709 return &local_iplt->dyn_relocs;
3710 }
3711 else
3712 {
3713 /* Track dynamic relocs needed for local syms too.
3714 We really need local syms available to do this
3715 easily. Oh well. */
3716 asection *s;
3717 void *vpp;
3718
3719 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3720 if (s == NULL)
3721 abort ();
3722
3723 vpp = &elf_section_data (s)->local_dynrel;
3724 return (struct elf_dyn_relocs **) vpp;
3725 }
3726}
3727
906e58ca
NC		 3728/* Initialize an entry in the stub hash table. */
3729
3730static struct bfd_hash_entry *
3731stub_hash_newfunc (struct bfd_hash_entry *entry,
3732 struct bfd_hash_table *table,
3733 const char *string)
3734{
3735 /* Allocate the structure if it has not already been allocated by a
3736 subclass. */
3737 if (entry == NULL)
3738 {
21d799b5 3739 entry = (struct bfd_hash_entry *)
99059e56 3740 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3741 if (entry == NULL)
3742 return entry;
3743 }
3744
3745 /* Call the allocation method of the superclass. */
3746 entry = bfd_hash_newfunc (entry, table, string);
3747 if (entry != NULL)
3748 {
3749 struct elf32_arm_stub_hash_entry *eh;
3750
3751 /* Initialize the local fields. */
3752 eh = (struct elf32_arm_stub_hash_entry *) entry;
3753 eh->stub_sec = NULL;
0955507f 3754 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3755 eh->source_value = 0;
906e58ca
NC		 3756 eh->target_value = 0;
3757 eh->target_section = NULL;
cedfb179 3758 eh->orig_insn = 0;
906e58ca 3759 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3760 eh->stub_size = 0;
3761 eh->stub_template = NULL;
0955507f 3762 eh->stub_template_size = -1;
906e58ca
NC		 3763 eh->h = NULL;
3764 eh->id_sec = NULL;
d8d2f433 3765 eh->output_name = NULL;
906e58ca
NC		 3766 }
3767
3768 return entry;
3769}
3770
00a97672 3771/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3772 shortcuts to them in our hash table. */
3773
3774static bfd_boolean
57e8b36a 3775create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3776{
3777 struct elf32_arm_link_hash_table *htab;
3778
e5a52504 3779 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3780 if (htab == NULL)
3781 return FALSE;
3782
e5a52504 3783 /* BPABI objects never have a GOT, or associated sections. */
90c14f0c 3784 if (htab->root.target_os == is_symbian)
e5a52504
MM		 3785 return TRUE;
3786
5e681ec4
PB		 3787 if (! _bfd_elf_create_got_section (dynobj, info))
3788 return FALSE;
3789
e8b09b87
CL		 3790 /* Also create .rofixup. */
3791 if (htab->fdpic_p)
3792 {
3793 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3794 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3795 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
fd361982
AM		 3796 if (htab->srofixup == NULL
3797 || !bfd_set_section_alignment (htab->srofixup, 2))
e8b09b87
CL		 3798 return FALSE;
3799 }
3800
5e681ec4
PB		 3801 return TRUE;
3802}
3803
34e77a92
RS		 3804/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3805
3806static bfd_boolean
3807create_ifunc_sections (struct bfd_link_info *info)
3808{
3809 struct elf32_arm_link_hash_table *htab;
3810 const struct elf_backend_data *bed;
3811 bfd *dynobj;
3812 asection *s;
3813 flagword flags;
b38cadfb 3814
34e77a92
RS		 3815 htab = elf32_arm_hash_table (info);
3816 dynobj = htab->root.dynobj;
3817 bed = get_elf_backend_data (dynobj);
3818 flags = bed->dynamic_sec_flags;
3819
3820 if (htab->root.iplt == NULL)
3821 {
3d4d4302
AM		 3822 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3823 flags | SEC_READONLY | SEC_CODE);
34e77a92 3824 if (s == NULL
fd361982 3825 || !bfd_set_section_alignment (s, bed->plt_alignment))
34e77a92
RS		 3826 return FALSE;
3827 htab->root.iplt = s;
3828 }
3829
3830 if (htab->root.irelplt == NULL)
3831 {
3d4d4302
AM		 3832 s = bfd_make_section_anyway_with_flags (dynobj,
3833 RELOC_SECTION (htab, ".iplt"),
3834 flags | SEC_READONLY);
34e77a92 3835 if (s == NULL
fd361982 3836 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3837 return FALSE;
3838 htab->root.irelplt = s;
3839 }
3840
3841 if (htab->root.igotplt == NULL)
3842 {
3d4d4302 3843 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92 3844 if (s == NULL
fd361982 3845 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3846 return FALSE;
3847 htab->root.igotplt = s;
3848 }
3849 return TRUE;
3850}
3851
eed94f8f
NC		 3852/* Determine if we're dealing with a Thumb only architecture. */
3853
3854static bfd_boolean
3855using_thumb_only (struct elf32_arm_link_hash_table *globals)
3856{
2fd158eb
TP		 3857 int arch;
3858 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3859 Tag_CPU_arch_profile);
eed94f8f 3860
2fd158eb
TP		 3861 if (profile)
3862 return profile == 'M';
eed94f8f 3863
2fd158eb 3864 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3865
60a019a0 3866 /* Force return logic to be reviewed for each new architecture. */
031254f2 3867 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0 3868
2fd158eb
TP		 3869 if (arch == TAG_CPU_ARCH_V6_M
3870 || arch == TAG_CPU_ARCH_V6S_M
3871 || arch == TAG_CPU_ARCH_V7E_M
3872 || arch == TAG_CPU_ARCH_V8M_BASE
031254f2
AV		 3873 || arch == TAG_CPU_ARCH_V8M_MAIN
3874 || arch == TAG_CPU_ARCH_V8_1M_MAIN)
2fd158eb 3875 return TRUE;
eed94f8f 3876
2fd158eb 3877 return FALSE;
eed94f8f
NC		 3878}
3879
3880/* Determine if we're dealing with a Thumb-2 object. */
3881
3882static bfd_boolean
3883using_thumb2 (struct elf32_arm_link_hash_table *globals)
3884{
60a019a0
TP		 3885 int arch;
3886 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3887 Tag_THUMB_ISA_use);
3888
3889 if (thumb_isa)
3890 return thumb_isa == 2;
3891
3892 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3893
3894 /* Force return logic to be reviewed for each new architecture. */
031254f2 3895 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 3896
3897 return (arch == TAG_CPU_ARCH_V6T2
3898 || arch == TAG_CPU_ARCH_V7
3899 || arch == TAG_CPU_ARCH_V7E_M
3900 || arch == TAG_CPU_ARCH_V8
bff0500d 3901 || arch == TAG_CPU_ARCH_V8R
031254f2
AV		 3902 || arch == TAG_CPU_ARCH_V8M_MAIN
3903 || arch == TAG_CPU_ARCH_V8_1M_MAIN);
eed94f8f
NC		 3904}
3905
5e866f5a
TP		 3906/* Determine whether Thumb-2 BL instruction is available. */
3907
3908static bfd_boolean
3909using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3910{
3911 int arch =
3912 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3913
3914 /* Force return logic to be reviewed for each new architecture. */
031254f2 3915 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
5e866f5a
TP		 3916
3917 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3918 return (arch == TAG_CPU_ARCH_V6T2
3919 || arch >= TAG_CPU_ARCH_V7);
3920}
3921
00a97672
RS		 3922/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3923 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3924 hash table. */
3925
3926static bfd_boolean
57e8b36a 3927elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3928{
3929 struct elf32_arm_link_hash_table *htab;
3930
3931 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3932 if (htab == NULL)
3933 return FALSE;
3934
362d30a1 3935 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3936 return FALSE;
3937
3938 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3939 return FALSE;
3940
90c14f0c 3941 if (htab->root.target_os == is_vxworks)
00a97672
RS		 3942 {
3943 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3944 return FALSE;
3945
0e1862bb 3946 if (bfd_link_pic (info))
00a97672
RS		 3947 {
3948 htab->plt_header_size = 0;
3949 htab->plt_entry_size
3950 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3951 }
3952 else
3953 {
3954 htab->plt_header_size
3955 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3956 htab->plt_entry_size
3957 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3958 }
aebf9be7
NC		 3959
3960 if (elf_elfheader (dynobj))
3961 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3962 }
eed94f8f
NC		 3963 else
3964 {
3965 /* PR ld/16017
3966 Test for thumb only architectures. Note - we cannot just call
3967 using_thumb_only() as the attributes in the output bfd have not been
3968 initialised at this point, so instead we use the input bfd. */
3969 bfd * saved_obfd = htab->obfd;
3970
3971 htab->obfd = dynobj;
3972 if (using_thumb_only (htab))
3973 {
3974 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3975 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3976 }
3977 htab->obfd = saved_obfd;
3978 }
5e681ec4 3979
7801f98f
CL		 3980 if (htab->fdpic_p) {
3981 htab->plt_header_size = 0;
3982 if (info->flags & DF_BIND_NOW)
3983 htab->plt_entry_size = 4 * (ARRAY_SIZE(elf32_arm_fdpic_plt_entry) - 5);
3984 else
3985 htab->plt_entry_size = 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry);
3986 }
3987
362d30a1
RS		 3988 if (!htab->root.splt
3989 || !htab->root.srelplt
9d19e4fd
AM		 3990 || !htab->root.sdynbss
3991 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 3992 abort ();
3993
3994 return TRUE;
3995}
3996
906e58ca
NC		 3997/* Copy the extra info we tack onto an elf_link_hash_entry. */
3998
3999static void
4000elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
4001 struct elf_link_hash_entry *dir,
4002 struct elf_link_hash_entry *ind)
4003{
4004 struct elf32_arm_link_hash_entry *edir, *eind;
4005
4006 edir = (struct elf32_arm_link_hash_entry *) dir;
4007 eind = (struct elf32_arm_link_hash_entry *) ind;
4008
906e58ca
NC		 4009 if (ind->root.type == bfd_link_hash_indirect)
4010 {
4011 /* Copy over PLT info. */
34e77a92
RS		 4012 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
4013 eind->plt.thumb_refcount = 0;
4014 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
4015 eind->plt.maybe_thumb_refcount = 0;
4016 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
4017 eind->plt.noncall_refcount = 0;
4018
e8b09b87
CL		 4019 /* Copy FDPIC counters. */
4020 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
4021 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
4022 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
4023
34e77a92
RS		 4024 /* We should only allocate a function to .iplt once the final
4025 symbol information is known. */
4026 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 4027
4028 if (dir->got.refcount <= 0)
4029 {
4030 edir->tls_type = eind->tls_type;
4031 eind->tls_type = GOT_UNKNOWN;
4032 }
4033 }
4034
4035 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4036}
4037
68faa637
AM		 4038/* Destroy an ARM elf linker hash table. */
4039
4040static void
d495ab0d 4041elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 4042{
4043 struct elf32_arm_link_hash_table *ret
d495ab0d 4044 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 4045
4046 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 4047 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 4048}
4049
906e58ca
NC		 4050/* Create an ARM elf linker hash table. */
4051
4052static struct bfd_link_hash_table *
4053elf32_arm_link_hash_table_create (bfd *abfd)
4054{
4055 struct elf32_arm_link_hash_table *ret;
986f0783 4056 size_t amt = sizeof (struct elf32_arm_link_hash_table);
906e58ca 4057
7bf52ea2 4058 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 4059 if (ret == NULL)
4060 return NULL;
4061
4062 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4063 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 4064 sizeof (struct elf32_arm_link_hash_entry),
4065 ARM_ELF_DATA))
906e58ca
NC		 4066 {
4067 free (ret);
4068 return NULL;
4069 }
4070
906e58ca 4071 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 4072 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 4073#ifdef FOUR_WORD_PLT
4074 ret->plt_header_size = 16;
4075 ret->plt_entry_size = 16;
4076#else
4077 ret->plt_header_size = 20;
1db37fe6 4078 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 4079#endif
f3185997 4080 ret->use_rel = TRUE;
906e58ca 4081 ret->obfd = abfd;
617a5ada 4082 ret->fdpic_p = 0;
906e58ca
NC		 4083
4084 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4085 sizeof (struct elf32_arm_stub_hash_entry)))
4086 {
d495ab0d 4087 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 4088 return NULL;
4089 }
d495ab0d 4090 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 4091
4092 return &ret->root.root;
4093}
4094
cd1dac3d
DG		 4095/* Determine what kind of NOPs are available. */
4096
4097static bfd_boolean
4098arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4099{
4100 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4101 Tag_CPU_arch);
cd1dac3d 4102
60a019a0 4103 /* Force return logic to be reviewed for each new architecture. */
031254f2 4104 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 4105
4106 return (arch == TAG_CPU_ARCH_V6T2
4107 || arch == TAG_CPU_ARCH_V6K
4108 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 4109 || arch == TAG_CPU_ARCH_V8
4110 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 4111}
4112
f4ac8484
DJ		 4113static bfd_boolean
4114arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4115{
4116 switch (stub_type)
4117 {
fea2b4d6 4118 case arm_stub_long_branch_thumb_only:
80c135e5 4119 case arm_stub_long_branch_thumb2_only:
d5a67c02 4120 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 4121 case arm_stub_long_branch_v4t_thumb_arm:
4122 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 4123 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 4124 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 4125 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 4126 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 4127 return TRUE;
4128 case arm_stub_none:
4129 BFD_FAIL ();
4130 return FALSE;
4131 break;
4132 default:
4133 return FALSE;
4134 }
4135}
4136
906e58ca
NC		 4137/* Determine the type of stub needed, if any, for a call. */
4138
4139static enum elf32_arm_stub_type
4140arm_type_of_stub (struct bfd_link_info *info,
4141 asection *input_sec,
4142 const Elf_Internal_Rela *rel,
34e77a92 4143 unsigned char st_type,
35fc36a8 4144 enum arm_st_branch_type *actual_branch_type,
906e58ca 4145 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 4146 bfd_vma destination,
4147 asection *sym_sec,
4148 bfd *input_bfd,
4149 const char *name)
906e58ca
NC		 4150{
4151 bfd_vma location;
4152 bfd_signed_vma branch_offset;
4153 unsigned int r_type;
4154 struct elf32_arm_link_hash_table * globals;
5e866f5a 4155 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 4156 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 4157 int use_plt = 0;
35fc36a8 4158 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 4159 union gotplt_union *root_plt;
4160 struct arm_plt_info *arm_plt;
d5a67c02
AV		 4161 int arch;
4162 int thumb2_movw;
906e58ca 4163
35fc36a8 4164 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 4165 return stub_type;
4166
906e58ca 4167 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4168 if (globals == NULL)
4169 return stub_type;
906e58ca
NC		 4170
4171 thumb_only = using_thumb_only (globals);
906e58ca 4172 thumb2 = using_thumb2 (globals);
5e866f5a 4173 thumb2_bl = using_thumb2_bl (globals);
906e58ca 4174
d5a67c02
AV		 4175 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4176
4177 /* True for architectures that implement the thumb2 movw instruction. */
4178 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4179
906e58ca
NC		 4180 /* Determine where the call point is. */
4181 location = (input_sec->output_offset
4182 + input_sec->output_section->vma
4183 + rel->r_offset);
4184
906e58ca
NC		 4185 r_type = ELF32_R_TYPE (rel->r_info);
4186
39f21624
NC		 4187 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4188 are considering a function call relocation. */
c5423981 4189 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 4190 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 4191 && branch_type == ST_BRANCH_TO_ARM)
4192 branch_type = ST_BRANCH_TO_THUMB;
4193
34e77a92
RS		 4194 /* For TLS call relocs, it is the caller's responsibility to provide
4195 the address of the appropriate trampoline. */
4196 if (r_type != R_ARM_TLS_CALL
4197 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 4198 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4199 ELF32_R_SYM (rel->r_info), &root_plt,
4200 &arm_plt)
34e77a92 4201 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 4202 {
34e77a92 4203 asection *splt;
fe33d2fa 4204
34e77a92
RS		 4205 if (hash == NULL || hash->is_iplt)
4206 splt = globals->root.iplt;
4207 else
4208 splt = globals->root.splt;
4209 if (splt != NULL)
b38cadfb 4210 {
34e77a92
RS		 4211 use_plt = 1;
4212
4213 /* Note when dealing with PLT entries: the main PLT stub is in
4214 ARM mode, so if the branch is in Thumb mode, another
4215 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4216 PLT stub. If a long branch stub is needed, we'll add a
4217 Thumb->Arm one and branch directly to the ARM PLT entry.
4218 Here, we have to check if a pre-PLT Thumb->ARM stub
4219 is needed and if it will be close enough. */
34e77a92
RS		 4220
4221 destination = (splt->output_section->vma
4222 + splt->output_offset
4223 + root_plt->offset);
4224 st_type = STT_FUNC;
2df2751d
CL		 4225
4226 /* Thumb branch/call to PLT: it can become a branch to ARM
4227 or to Thumb. We must perform the same checks and
4228 corrections as in elf32_arm_final_link_relocate. */
4229 if ((r_type == R_ARM_THM_CALL)
4230 || (r_type == R_ARM_THM_JUMP24))
4231 {
4232 if (globals->use_blx
4233 && r_type == R_ARM_THM_CALL
4234 && !thumb_only)
4235 {
4236 /* If the Thumb BLX instruction is available, convert
4237 the BL to a BLX instruction to call the ARM-mode
4238 PLT entry. */
4239 branch_type = ST_BRANCH_TO_ARM;
4240 }
4241 else
4242 {
4243 if (!thumb_only)
4244 /* Target the Thumb stub before the ARM PLT entry. */
4245 destination -= PLT_THUMB_STUB_SIZE;
4246 branch_type = ST_BRANCH_TO_THUMB;
4247 }
4248 }
4249 else
4250 {
4251 branch_type = ST_BRANCH_TO_ARM;
4252 }
34e77a92 4253 }
5fa9e92f 4254 }
34e77a92
RS		 4255 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4256 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4257
fe33d2fa
CL		 4258 branch_offset = (bfd_signed_vma)(destination - location);
4259
0855e32b 4260 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4261 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4262 {
5fa9e92f
CL		 4263 /* Handle cases where:
4264 - this call goes too far (different Thumb/Thumb2 max
99059e56 4265 distance)
155d87d7 4266 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4267 Thumb->Arm branch (not bl). A stub is needed in this case,
4268 but only if this call is not through a PLT entry. Indeed,
695344c0 4269 PLT stubs handle mode switching already. */
5e866f5a 4270 if ((!thumb2_bl
906e58ca
NC		 4271 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4272 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4273 || (thumb2_bl
906e58ca
NC		 4274 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4275 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4276 || (thumb2
4277 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4278 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4279 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4280 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4281 && (((r_type == R_ARM_THM_CALL
4282 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4283 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4284 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4285 && !use_plt))
906e58ca 4286 {
2df2751d
CL		 4287 /* If we need to insert a Thumb-Thumb long branch stub to a
4288 PLT, use one that branches directly to the ARM PLT
4289 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4290 stub, undo this now. */
695344c0
NC		 4291 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4292 {
4293 branch_type = ST_BRANCH_TO_ARM;
4294 branch_offset += PLT_THUMB_STUB_SIZE;
4295 }
2df2751d 4296
35fc36a8 4297 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4298 {
4299 /* Thumb to thumb. */
4300 if (!thumb_only)
4301 {
d5a67c02 4302 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4303 _bfd_error_handler
871b3ab2 4304 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4305 " section with SHF_ARM_PURECODE section"
4306 " attribute is only supported for M-profile"
90b6238f 4307 " targets that implement the movw instruction"),
10463f39 4308 input_bfd, input_sec);
d5a67c02 4309
0e1862bb 4310 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4311 /* PIC stubs. */
155d87d7 4312 ? ((globals->use_blx
9553db3c 4313 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4314 /* V5T and above. Stub starts with ARM code, so
4315 we must be able to switch mode before
4316 reaching it, which is only possible for 'bl'
4317 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4318 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4319 /* On V4T, use Thumb code only. */
d3626fb0 4320 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4321
4322 /* non-PIC stubs. */
155d87d7 4323 : ((globals->use_blx
9553db3c 4324 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4325 /* V5T and above. */
4326 ? arm_stub_long_branch_any_any
4327 /* V4T. */
d3626fb0 4328 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4329 }
4330 else
4331 {
d5a67c02
AV		 4332 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4333 stub_type = arm_stub_long_branch_thumb2_only_pure;
4334 else
4335 {
4336 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4337 _bfd_error_handler
871b3ab2 4338 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4339 " section with SHF_ARM_PURECODE section"
4340 " attribute is only supported for M-profile"
90b6238f 4341 " targets that implement the movw instruction"),
10463f39 4342 input_bfd, input_sec);
d5a67c02
AV		 4343
4344 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4345 /* PIC stub. */
4346 ? arm_stub_long_branch_thumb_only_pic
4347 /* non-PIC stub. */
4348 : (thumb2 ? arm_stub_long_branch_thumb2_only
4349 : arm_stub_long_branch_thumb_only);
4350 }
906e58ca
NC		 4351 }
4352 }
4353 else
4354 {
d5a67c02 4355 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4356 _bfd_error_handler
871b3ab2 4357 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4358 " section with SHF_ARM_PURECODE section"
4359 " attribute is only supported" " for M-profile"
90b6238f 4360 " targets that implement the movw instruction"),
10463f39 4361 input_bfd, input_sec);
d5a67c02 4362
906e58ca 4363 /* Thumb to arm. */
c820be07
NC		 4364 if (sym_sec != NULL
4365 && sym_sec->owner != NULL
4366 && !INTERWORK_FLAG (sym_sec->owner))
4367 {
4eca0228 4368 _bfd_error_handler
90b6238f
AM		 4369 (_("%pB(%s): warning: interworking not enabled;"
4370 " first occurrence: %pB: %s call to %s"),
4371 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4372 }
4373
0855e32b 4374 stub_type =
0e1862bb 4375 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4376 /* PIC stubs. */
0855e32b 4377 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4378 /* TLS PIC stubs. */
0855e32b
NS		 4379 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4380 : arm_stub_long_branch_v4t_thumb_tls_pic)
4381 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4382 /* V5T PIC and above. */
4383 ? arm_stub_long_branch_any_arm_pic
4384 /* V4T PIC stub. */
4385 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4386
4387 /* non-PIC stubs. */
0855e32b 4388 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4389 /* V5T and above. */
4390 ? arm_stub_long_branch_any_any
4391 /* V4T. */
4392 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4393
4394 /* Handle v4t short branches. */
fea2b4d6 4395 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4396 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4397 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4398 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4399 }
4400 }
4401 }
fe33d2fa
CL		 4402 else if (r_type == R_ARM_CALL
4403 || r_type == R_ARM_JUMP24
0855e32b
NS		 4404 || r_type == R_ARM_PLT32
4405 || r_type == R_ARM_TLS_CALL)
906e58ca 4406 {
d5a67c02 4407 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4408 _bfd_error_handler
871b3ab2 4409 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4410 " section with SHF_ARM_PURECODE section"
4411 " attribute is only supported for M-profile"
90b6238f 4412 " targets that implement the movw instruction"),
10463f39 4413 input_bfd, input_sec);
35fc36a8 4414 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4415 {
4416 /* Arm to thumb. */
c820be07
NC		 4417
4418 if (sym_sec != NULL
4419 && sym_sec->owner != NULL
4420 && !INTERWORK_FLAG (sym_sec->owner))
4421 {
4eca0228 4422 _bfd_error_handler
90b6238f
AM		 4423 (_("%pB(%s): warning: interworking not enabled;"
4424 " first occurrence: %pB: %s call to %s"),
4425 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4426 }
4427
4428 /* We have an extra 2-bytes reach because of
4429 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4430 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4431 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4432 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4433 || (r_type == R_ARM_JUMP24)
4434 || (r_type == R_ARM_PLT32))
906e58ca 4435 {
0e1862bb 4436 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4437 /* PIC stubs. */
ebe24dd4
CL		 4438 ? ((globals->use_blx)
4439 /* V5T and above. */
4440 ? arm_stub_long_branch_any_thumb_pic
4441 /* V4T stub. */
4442 : arm_stub_long_branch_v4t_arm_thumb_pic)
4443
c2b4a39d
CL		 4444 /* non-PIC stubs. */
4445 : ((globals->use_blx)
4446 /* V5T and above. */
4447 ? arm_stub_long_branch_any_any
4448 /* V4T. */
4449 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4450 }
4451 }
4452 else
4453 {
4454 /* Arm to arm. */
4455 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4456 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4457 {
0855e32b 4458 stub_type =
0e1862bb 4459 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4460 /* PIC stubs. */
0855e32b 4461 ? (r_type == R_ARM_TLS_CALL
6a631e86 4462 /* TLS PIC Stub. */
0855e32b 4463 ? arm_stub_long_branch_any_tls_pic
90c14f0c 4464 : (globals->root.target_os == is_nacl
7a89b94e
NC		 4465 ? arm_stub_long_branch_arm_nacl_pic
4466 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4467 /* non-PIC stubs. */
90c14f0c 4468 : (globals->root.target_os == is_nacl
7a89b94e
NC		 4469 ? arm_stub_long_branch_arm_nacl
4470 : arm_stub_long_branch_any_any);
906e58ca
NC		 4471 }
4472 }
4473 }
4474
fe33d2fa
CL		 4475 /* If a stub is needed, record the actual destination type. */
4476 if (stub_type != arm_stub_none)
35fc36a8 4477 *actual_branch_type = branch_type;
fe33d2fa 4478
906e58ca
NC		 4479 return stub_type;
4480}
4481
4482/* Build a name for an entry in the stub hash table. */
4483
4484static char *
4485elf32_arm_stub_name (const asection *input_section,
4486 const asection *sym_sec,
4487 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4488 const Elf_Internal_Rela *rel,
4489 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4490{
4491 char *stub_name;
4492 bfd_size_type len;
4493
4494 if (hash)
4495 {
fe33d2fa 4496 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4497 stub_name = (char *) bfd_malloc (len);
906e58ca 4498 if (stub_name != NULL)
fe33d2fa 4499 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4500 input_section->id & 0xffffffff,
4501 hash->root.root.root.string,
fe33d2fa
CL		 4502 (int) rel->r_addend & 0xffffffff,
4503 (int) stub_type);
906e58ca
NC		 4504 }
4505 else
4506 {
fe33d2fa 4507 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4508 stub_name = (char *) bfd_malloc (len);
906e58ca 4509 if (stub_name != NULL)
fe33d2fa 4510 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4511 input_section->id & 0xffffffff,
4512 sym_sec->id & 0xffffffff,
0855e32b
NS		 4513 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4514 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4515 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4516 (int) rel->r_addend & 0xffffffff,
4517 (int) stub_type);
906e58ca
NC		 4518 }
4519
4520 return stub_name;
4521}
4522
4523/* Look up an entry in the stub hash. Stub entries are cached because
4524 creating the stub name takes a bit of time. */
4525
4526static struct elf32_arm_stub_hash_entry *
4527elf32_arm_get_stub_entry (const asection *input_section,
4528 const asection *sym_sec,
4529 struct elf_link_hash_entry *hash,
4530 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4531 struct elf32_arm_link_hash_table *htab,
4532 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4533{
4534 struct elf32_arm_stub_hash_entry *stub_entry;
4535 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4536 const asection *id_sec;
4537
4538 if ((input_section->flags & SEC_CODE) == 0)
4539 return NULL;
4540
4d83e8d9
CL		 4541 /* If the input section is the CMSE stubs one and it needs a long
4542 branch stub to reach it's final destination, give up with an
4543 error message: this is not supported. See PR ld/24709. */
4544 if (!strncmp (input_section->name, CMSE_STUB_NAME, strlen(CMSE_STUB_NAME)))
4545 {
4546 bfd *output_bfd = htab->obfd;
4547 asection *out_sec = bfd_get_section_by_name (output_bfd, CMSE_STUB_NAME);
4548
4549 _bfd_error_handler (_("ERROR: CMSE stub (%s section) too far "
4550 "(%#" PRIx64 ") from destination (%#" PRIx64 ")"),
4551 CMSE_STUB_NAME,
4552 (uint64_t)out_sec->output_section->vma
4553 + out_sec->output_offset,
4554 (uint64_t)sym_sec->output_section->vma
4555 + sym_sec->output_offset
4556 + h->root.root.u.def.value);
4557 /* Exit, rather than leave incompletely processed
4558 relocations. */
4559 xexit(1);
4560 }
4561
906e58ca
NC		 4562 /* If this input section is part of a group of sections sharing one
4563 stub section, then use the id of the first section in the group.
4564 Stub names need to include a section id, as there may well be
4565 more than one stub used to reach say, printf, and we need to
4566 distinguish between them. */
c2abbbeb 4567 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4568 id_sec = htab->stub_group[input_section->id].link_sec;
4569
4570 if (h != NULL && h->stub_cache != NULL
4571 && h->stub_cache->h == h
fe33d2fa
CL		 4572 && h->stub_cache->id_sec == id_sec
4573 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4574 {
4575 stub_entry = h->stub_cache;
4576 }
4577 else
4578 {
4579 char *stub_name;
4580
fe33d2fa 4581 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4582 if (stub_name == NULL)
4583 return NULL;
4584
4585 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4586 stub_name, FALSE, FALSE);
4587 if (h != NULL)
4588 h->stub_cache = stub_entry;
4589
4590 free (stub_name);
4591 }
4592
4593 return stub_entry;
4594}
4595
daa4adae
TP		 4596/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4597 section. */
4598
4599static bfd_boolean
4600arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4601{
4602 if (stub_type >= max_stub_type)
4603 abort (); /* Should be unreachable. */
4604
4ba2ef8f
TP		 4605 switch (stub_type)
4606 {
4607 case arm_stub_cmse_branch_thumb_only:
4608 return TRUE;
4609
4610 default:
4611 return FALSE;
4612 }
4613
4614 abort (); /* Should be unreachable. */
daa4adae
TP		 4615}
4616
4617/* Required alignment (as a power of 2) for the dedicated section holding
4618 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4619 with input sections. */
4620
4621static int
4622arm_dedicated_stub_output_section_required_alignment
4623 (enum elf32_arm_stub_type stub_type)
4624{
4625 if (stub_type >= max_stub_type)
4626 abort (); /* Should be unreachable. */
4627
4ba2ef8f
TP		 4628 switch (stub_type)
4629 {
4630 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4631 boundary. */
4632 case arm_stub_cmse_branch_thumb_only:
4633 return 5;
4634
4635 default:
4636 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4637 return 0;
4638 }
4639
4640 abort (); /* Should be unreachable. */
daa4adae
TP		 4641}
4642
4643/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4644 NULL if veneers of this type are interspersed with input sections. */
4645
4646static const char *
4647arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4648{
4649 if (stub_type >= max_stub_type)
4650 abort (); /* Should be unreachable. */
4651
4ba2ef8f
TP		 4652 switch (stub_type)
4653 {
4654 case arm_stub_cmse_branch_thumb_only:
4d83e8d9 4655 return CMSE_STUB_NAME;
4ba2ef8f
TP		 4656
4657 default:
4658 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4659 return NULL;
4660 }
4661
4662 abort (); /* Should be unreachable. */
daa4adae
TP		 4663}
4664
4665/* If veneers of type STUB_TYPE should go in a dedicated output section,
4666 returns the address of the hash table field in HTAB holding a pointer to the
4667 corresponding input section. Otherwise, returns NULL. */
4668
4669static asection **
4ba2ef8f
TP		 4670arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4671 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4672{
4673 if (stub_type >= max_stub_type)
4674 abort (); /* Should be unreachable. */
4675
4ba2ef8f
TP		 4676 switch (stub_type)
4677 {
4678 case arm_stub_cmse_branch_thumb_only:
4679 return &htab->cmse_stub_sec;
4680
4681 default:
4682 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4683 return NULL;
4684 }
4685
4686 abort (); /* Should be unreachable. */
daa4adae
TP		 4687}
4688
4689/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4690 is the section that branch into veneer and can be NULL if stub should go in
4691 a dedicated output section. Returns a pointer to the stub section, and the
4692 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4693 LINK_SEC_P may be NULL. */
906e58ca 4694
48229727
JB		 4695static asection *
4696elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4697 struct elf32_arm_link_hash_table *htab,
4698 enum elf32_arm_stub_type stub_type)
906e58ca 4699{
daa4adae
TP		 4700 asection *link_sec, *out_sec, **stub_sec_p;
4701 const char *stub_sec_prefix;
4702 bfd_boolean dedicated_output_section =
4703 arm_dedicated_stub_output_section_required (stub_type);
4704 int align;
906e58ca 4705
daa4adae 4706 if (dedicated_output_section)
906e58ca 4707 {
daa4adae
TP		 4708 bfd *output_bfd = htab->obfd;
4709 const char *out_sec_name =
4710 arm_dedicated_stub_output_section_name (stub_type);
4711 link_sec = NULL;
4712 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4713 stub_sec_prefix = out_sec_name;
4714 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4715 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4716 if (out_sec == NULL)
906e58ca 4717 {
90b6238f 4718 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4719 "section %s"), out_sec_name);
daa4adae 4720 return NULL;
906e58ca 4721 }
daa4adae
TP		 4722 }
4723 else
4724 {
c2abbbeb 4725 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4726 link_sec = htab->stub_group[section->id].link_sec;
4727 BFD_ASSERT (link_sec != NULL);
4728 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4729 if (*stub_sec_p == NULL)
4730 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4731 stub_sec_prefix = link_sec->name;
4732 out_sec = link_sec->output_section;
90c14f0c 4733 align = htab->root.target_os == is_nacl ? 4 : 3;
906e58ca 4734 }
b38cadfb 4735
daa4adae
TP		 4736 if (*stub_sec_p == NULL)
4737 {
4738 size_t namelen;
4739 bfd_size_type len;
4740 char *s_name;
4741
4742 namelen = strlen (stub_sec_prefix);
4743 len = namelen + sizeof (STUB_SUFFIX);
4744 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4745 if (s_name == NULL)
4746 return NULL;
4747
4748 memcpy (s_name, stub_sec_prefix, namelen);
4749 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4750 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4751 align);
4752 if (*stub_sec_p == NULL)
4753 return NULL;
4754
4755 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4756 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4757 | SEC_KEEP;
4758 }
4759
4760 if (!dedicated_output_section)
4761 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4762
48229727
JB		 4763 if (link_sec_p)
4764 *link_sec_p = link_sec;
b38cadfb 4765
daa4adae 4766 return *stub_sec_p;
48229727
JB		 4767}
4768
4769/* Add a new stub entry to the stub hash. Not all fields of the new
4770 stub entry are initialised. */
4771
4772static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4773elf32_arm_add_stub (const char *stub_name, asection *section,
4774 struct elf32_arm_link_hash_table *htab,
4775 enum elf32_arm_stub_type stub_type)
48229727
JB		 4776{
4777 asection *link_sec;
4778 asection *stub_sec;
4779 struct elf32_arm_stub_hash_entry *stub_entry;
4780
daa4adae
TP		 4781 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4782 stub_type);
48229727
JB		 4783 if (stub_sec == NULL)
4784 return NULL;
906e58ca
NC		 4785
4786 /* Enter this entry into the linker stub hash table. */
4787 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4788 TRUE, FALSE);
4789 if (stub_entry == NULL)
4790 {
6bde4c52
TP		 4791 if (section == NULL)
4792 section = stub_sec;
871b3ab2 4793 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4794 section->owner, stub_name);
906e58ca
NC		 4795 return NULL;
4796 }
4797
4798 stub_entry->stub_sec = stub_sec;
0955507f 4799 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4800 stub_entry->id_sec = link_sec;
4801
906e58ca
NC		 4802 return stub_entry;
4803}
4804
4805/* Store an Arm insn into an output section not processed by
4806 elf32_arm_write_section. */
4807
4808static void
8029a119
NC		 4809put_arm_insn (struct elf32_arm_link_hash_table * htab,
4810 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4811{
4812 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4813 bfd_putl32 (val, ptr);
4814 else
4815 bfd_putb32 (val, ptr);
4816}
4817
4818/* Store a 16-bit Thumb insn into an output section not processed by
4819 elf32_arm_write_section. */
4820
4821static void
8029a119
NC		 4822put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4823 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4824{
4825 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4826 bfd_putl16 (val, ptr);
4827 else
4828 bfd_putb16 (val, ptr);
4829}
4830
a504d23a
LA		 4831/* Store a Thumb2 insn into an output section not processed by
4832 elf32_arm_write_section. */
4833
4834static void
4835put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4836 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4837{
4838 /* T2 instructions are 16-bit streamed. */
4839 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4840 {
4841 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4842 bfd_putl16 ((val & 0xffff), ptr + 2);
4843 }
4844 else
4845 {
4846 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4847 bfd_putb16 ((val & 0xffff), ptr + 2);
4848 }
4849}
4850
0855e32b
NS		 4851/* If it's possible to change R_TYPE to a more efficient access
4852 model, return the new reloc type. */
4853
4854static unsigned
b38cadfb 4855elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4856 struct elf_link_hash_entry *h)
4857{
4858 int is_local = (h == NULL);
4859
9cb09e33 4860 if (bfd_link_dll (info)
0e1862bb 4861 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4862 return r_type;
4863
b38cadfb 4864 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4865 switch (r_type)
4866 {
4867 case R_ARM_TLS_GOTDESC:
4868 case R_ARM_TLS_CALL:
4869 case R_ARM_THM_TLS_CALL:
4870 case R_ARM_TLS_DESCSEQ:
4871 case R_ARM_THM_TLS_DESCSEQ:
4872 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4873 }
4874
4875 return r_type;
4876}
4877
48229727
JB		 4878static bfd_reloc_status_type elf32_arm_final_link_relocate
4879 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4880 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4881 const char *, unsigned char, enum arm_st_branch_type,
4882 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4883
4563a860
JB		 4884static unsigned int
4885arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4886{
4887 switch (stub_type)
4888 {
4889 case arm_stub_a8_veneer_b_cond:
4890 case arm_stub_a8_veneer_b:
4891 case arm_stub_a8_veneer_bl:
4892 return 2;
4893
4894 case arm_stub_long_branch_any_any:
4895 case arm_stub_long_branch_v4t_arm_thumb:
4896 case arm_stub_long_branch_thumb_only:
80c135e5 4897 case arm_stub_long_branch_thumb2_only:
d5a67c02 4898 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4899 case arm_stub_long_branch_v4t_thumb_thumb:
4900 case arm_stub_long_branch_v4t_thumb_arm:
4901 case arm_stub_short_branch_v4t_thumb_arm:
4902 case arm_stub_long_branch_any_arm_pic:
4903 case arm_stub_long_branch_any_thumb_pic:
4904 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4905 case arm_stub_long_branch_v4t_arm_thumb_pic:
4906 case arm_stub_long_branch_v4t_thumb_arm_pic:
4907 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4908 case arm_stub_long_branch_any_tls_pic:
4909 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4910 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4911 case arm_stub_a8_veneer_blx:
4912 return 4;
b38cadfb 4913
7a89b94e
NC		 4914 case arm_stub_long_branch_arm_nacl:
4915 case arm_stub_long_branch_arm_nacl_pic:
4916 return 16;
4917
4563a860
JB		 4918 default:
4919 abort (); /* Should be unreachable. */
4920 }
4921}
4922
4f4faa4d
TP		 4923/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4924 veneering (TRUE) or have their own symbol (FALSE). */
4925
4926static bfd_boolean
4927arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4928{
4929 if (stub_type >= max_stub_type)
4930 abort (); /* Should be unreachable. */
4931
4ba2ef8f
TP		 4932 switch (stub_type)
4933 {
4934 case arm_stub_cmse_branch_thumb_only:
4935 return TRUE;
4936
4937 default:
4938 return FALSE;
4939 }
4940
4941 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4942}
4943
d7c5bd02
TP		 4944/* Returns the padding needed for the dedicated section used stubs of type
4945 STUB_TYPE. */
4946
4947static int
4948arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4949{
4950 if (stub_type >= max_stub_type)
4951 abort (); /* Should be unreachable. */
4952
4ba2ef8f
TP		 4953 switch (stub_type)
4954 {
4955 case arm_stub_cmse_branch_thumb_only:
4956 return 32;
4957
4958 default:
4959 return 0;
4960 }
4961
4962 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4963}
4964
0955507f
TP		 4965/* If veneers of type STUB_TYPE should go in a dedicated output section,
4966 returns the address of the hash table field in HTAB holding the offset at
4967 which new veneers should be layed out in the stub section. */
4968
4969static bfd_vma*
4970arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4971 enum elf32_arm_stub_type stub_type)
4972{
4973 switch (stub_type)
4974 {
4975 case arm_stub_cmse_branch_thumb_only:
4976 return &htab->new_cmse_stub_offset;
4977
4978 default:
4979 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4980 return NULL;
4981 }
4982}
4983
906e58ca
NC		 4984static bfd_boolean
4985arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4986 void * in_arg)
4987{
7a89b94e 4988#define MAXRELOCS 3
0955507f 4989 bfd_boolean removed_sg_veneer;
906e58ca 4990 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4991 struct elf32_arm_link_hash_table *globals;
906e58ca 4992 struct bfd_link_info *info;
906e58ca
NC		 4993 asection *stub_sec;
4994 bfd *stub_bfd;
906e58ca
NC		 4995 bfd_byte *loc;
4996 bfd_vma sym_value;
4997 int template_size;
4998 int size;
d3ce72d0 4999 const insn_sequence *template_sequence;
906e58ca 5000 int i;
48229727
JB		 5001 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
5002 int stub_reloc_offset[MAXRELOCS] = {0, 0};
5003 int nrelocs = 0;
0955507f 5004 int just_allocated = 0;
906e58ca
NC		 5005
5006 /* Massage our args to the form they really have. */
5007 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5008 info = (struct bfd_link_info *) in_arg;
5009
abf874aa
CL		 5010 /* Fail if the target section could not be assigned to an output
5011 section. The user should fix his linker script. */
5012 if (stub_entry->target_section->output_section == NULL
5013 && info->non_contiguous_regions)
53215f21
CL		 5014 info->callbacks->einfo (_("%F%P: Could not assign '%pA' to an output section. "
5015 "Retry without --enable-non-contiguous-regions.\n"),
5016 stub_entry->target_section);
abf874aa 5017
906e58ca 5018 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5019 if (globals == NULL)
5020 return FALSE;
906e58ca 5021
906e58ca
NC		 5022 stub_sec = stub_entry->stub_sec;
5023
4dfe6ac6 5024 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 5025 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
5026 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 5027 return TRUE;
fe33d2fa 5028
0955507f
TP		 5029 /* Assign a slot at the end of section if none assigned yet. */
5030 if (stub_entry->stub_offset == (bfd_vma) -1)
5031 {
5032 stub_entry->stub_offset = stub_sec->size;
5033 just_allocated = 1;
5034 }
906e58ca
NC		 5035 loc = stub_sec->contents + stub_entry->stub_offset;
5036
5037 stub_bfd = stub_sec->owner;
5038
906e58ca
NC		 5039 /* This is the address of the stub destination. */
5040 sym_value = (stub_entry->target_value
5041 + stub_entry->target_section->output_offset
5042 + stub_entry->target_section->output_section->vma);
5043
d3ce72d0 5044 template_sequence = stub_entry->stub_template;
461a49ca 5045 template_size = stub_entry->stub_template_size;
906e58ca
NC		 5046
5047 size = 0;
461a49ca 5048 for (i = 0; i < template_size; i++)
906e58ca 5049 {
d3ce72d0 5050 switch (template_sequence[i].type)
461a49ca
DJ		 5051 {
5052 case THUMB16_TYPE:
48229727 5053 {
d3ce72d0
NC		 5054 bfd_vma data = (bfd_vma) template_sequence[i].data;
5055 if (template_sequence[i].reloc_addend != 0)
48229727 5056 {
99059e56
RM		 5057 /* We've borrowed the reloc_addend field to mean we should
5058 insert a condition code into this (Thumb-1 branch)
5059 instruction. See THUMB16_BCOND_INSN. */
5060 BFD_ASSERT ((data & 0xff00) == 0xd000);
5061 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 5062 }
fe33d2fa 5063 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 5064 size += 2;
5065 }
461a49ca 5066 break;
906e58ca 5067
48229727 5068 case THUMB32_TYPE:
fe33d2fa
CL		 5069 bfd_put_16 (stub_bfd,
5070 (template_sequence[i].data >> 16) & 0xffff,
5071 loc + size);
5072 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5073 loc + size + 2);
99059e56
RM		 5074 if (template_sequence[i].r_type != R_ARM_NONE)
5075 {
5076 stub_reloc_idx[nrelocs] = i;
5077 stub_reloc_offset[nrelocs++] = size;
5078 }
5079 size += 4;
5080 break;
48229727 5081
461a49ca 5082 case ARM_TYPE:
fe33d2fa
CL		 5083 bfd_put_32 (stub_bfd, template_sequence[i].data,
5084 loc + size);
461a49ca
DJ		 5085 /* Handle cases where the target is encoded within the
5086 instruction. */
d3ce72d0 5087 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 5088 {
48229727
JB		 5089 stub_reloc_idx[nrelocs] = i;
5090 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5091 }
5092 size += 4;
5093 break;
5094
5095 case DATA_TYPE:
d3ce72d0 5096 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 5097 stub_reloc_idx[nrelocs] = i;
5098 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5099 size += 4;
5100 break;
5101
5102 default:
5103 BFD_FAIL ();
5104 return FALSE;
5105 }
906e58ca 5106 }
461a49ca 5107
0955507f
TP		 5108 if (just_allocated)
5109 stub_sec->size += size;
906e58ca 5110
461a49ca
DJ		 5111 /* Stub size has already been computed in arm_size_one_stub. Check
5112 consistency. */
5113 BFD_ASSERT (size == stub_entry->stub_size);
5114
906e58ca 5115 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 5116 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 5117 sym_value |= 1;
5118
0955507f
TP		 5119 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5120 to relocate in each stub. */
5121 removed_sg_veneer =
5122 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5123 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 5124
48229727 5125 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 5126 {
5127 Elf_Internal_Rela rel;
5128 bfd_boolean unresolved_reloc;
5129 char *error_message;
5130 bfd_vma points_to =
5131 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5132
5133 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5134 rel.r_info = ELF32_R_INFO (0,
5135 template_sequence[stub_reloc_idx[i]].r_type);
5136 rel.r_addend = 0;
5137
5138 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5139 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5140 template should refer back to the instruction after the original
5141 branch. We use target_section as Cortex-A8 erratum workaround stubs
5142 are only generated when both source and target are in the same
5143 section. */
5144 points_to = stub_entry->target_section->output_section->vma
5145 + stub_entry->target_section->output_offset
5146 + stub_entry->source_value;
5147
5148 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5149 (template_sequence[stub_reloc_idx[i]].r_type),
5150 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5151 points_to, info, stub_entry->target_section, "", STT_FUNC,
5152 stub_entry->branch_type,
5153 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5154 &error_message);
5155 }
906e58ca
NC		 5156
5157 return TRUE;
48229727 5158#undef MAXRELOCS
906e58ca
NC		 5159}
5160
48229727
JB		 5161/* Calculate the template, template size and instruction size for a stub.
5162 Return value is the instruction size. */
906e58ca 5163
48229727
JB		 5164static unsigned int
5165find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5166 const insn_sequence **stub_template,
5167 int *stub_template_size)
906e58ca 5168{
d3ce72d0 5169 const insn_sequence *template_sequence = NULL;
48229727
JB		 5170 int template_size = 0, i;
5171 unsigned int size;
906e58ca 5172
d3ce72d0 5173 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 5174 if (stub_template)
5175 *stub_template = template_sequence;
5176
48229727 5177 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 5178 if (stub_template_size)
5179 *stub_template_size = template_size;
906e58ca
NC		 5180
5181 size = 0;
461a49ca
DJ		 5182 for (i = 0; i < template_size; i++)
5183 {
d3ce72d0 5184 switch (template_sequence[i].type)
461a49ca
DJ		 5185 {
5186 case THUMB16_TYPE:
5187 size += 2;
5188 break;
5189
5190 case ARM_TYPE:
48229727 5191 case THUMB32_TYPE:
461a49ca
DJ		 5192 case DATA_TYPE:
5193 size += 4;
5194 break;
5195
5196 default:
5197 BFD_FAIL ();
2a229407 5198 return 0;
461a49ca
DJ		 5199 }
5200 }
5201
48229727
JB		 5202 return size;
5203}
5204
5205/* As above, but don't actually build the stub. Just bump offset so
5206 we know stub section sizes. */
5207
5208static bfd_boolean
5209arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 5210 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 5211{
5212 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 5213 const insn_sequence *template_sequence;
48229727
JB		 5214 int template_size, size;
5215
5216 /* Massage our args to the form they really have. */
5217 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 5218
5219 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
5220 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
5221
d3ce72d0 5222 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 5223 &template_size);
5224
0955507f
TP		 5225 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5226 if (stub_entry->stub_template_size)
5227 {
5228 stub_entry->stub_size = size;
5229 stub_entry->stub_template = template_sequence;
5230 stub_entry->stub_template_size = template_size;
5231 }
5232
5233 /* Already accounted for. */
5234 if (stub_entry->stub_offset != (bfd_vma) -1)
5235 return TRUE;
461a49ca 5236
906e58ca
NC		 5237 size = (size + 7) & ~7;
5238 stub_entry->stub_sec->size += size;
461a49ca 5239
906e58ca
NC		 5240 return TRUE;
5241}
5242
5243/* External entry points for sizing and building linker stubs. */
5244
5245/* Set up various things so that we can make a list of input sections
5246 for each output section included in the link. Returns -1 on error,
5247 0 when no stubs will be needed, and 1 on success. */
5248
5249int
5250elf32_arm_setup_section_lists (bfd *output_bfd,
5251 struct bfd_link_info *info)
5252{
5253 bfd *input_bfd;
5254 unsigned int bfd_count;
7292b3ac 5255 unsigned int top_id, top_index;
906e58ca
NC		 5256 asection *section;
5257 asection **input_list, **list;
986f0783 5258 size_t amt;
906e58ca
NC		 5259 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5260
4dfe6ac6
NC		 5261 if (htab == NULL)
5262 return 0;
906e58ca
NC		 5263 if (! is_elf_hash_table (htab))
5264 return 0;
5265
5266 /* Count the number of input BFDs and find the top input section id. */
5267 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5268 input_bfd != NULL;
c72f2fb2 5269 input_bfd = input_bfd->link.next)
906e58ca
NC		 5270 {
5271 bfd_count += 1;
5272 for (section = input_bfd->sections;
5273 section != NULL;
5274 section = section->next)
5275 {
5276 if (top_id < section->id)
5277 top_id = section->id;
5278 }
5279 }
5280 htab->bfd_count = bfd_count;
5281
5282 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5283 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5284 if (htab->stub_group == NULL)
5285 return -1;
fe33d2fa 5286 htab->top_id = top_id;
906e58ca
NC		 5287
5288 /* We can't use output_bfd->section_count here to find the top output
5289 section index as some sections may have been removed, and
5290 _bfd_strip_section_from_output doesn't renumber the indices. */
5291 for (section = output_bfd->sections, top_index = 0;
5292 section != NULL;
5293 section = section->next)
5294 {
5295 if (top_index < section->index)
5296 top_index = section->index;
5297 }
5298
5299 htab->top_index = top_index;
5300 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5301 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5302 htab->input_list = input_list;
5303 if (input_list == NULL)
5304 return -1;
5305
5306 /* For sections we aren't interested in, mark their entries with a
5307 value we can check later. */
5308 list = input_list + top_index;
5309 do
5310 *list = bfd_abs_section_ptr;
5311 while (list-- != input_list);
5312
5313 for (section = output_bfd->sections;
5314 section != NULL;
5315 section = section->next)
5316 {
5317 if ((section->flags & SEC_CODE) != 0)
5318 input_list[section->index] = NULL;
5319 }
5320
5321 return 1;
5322}
5323
5324/* The linker repeatedly calls this function for each input section,
5325 in the order that input sections are linked into output sections.
5326 Build lists of input sections to determine groupings between which
5327 we may insert linker stubs. */
5328
5329void
5330elf32_arm_next_input_section (struct bfd_link_info *info,
5331 asection *isec)
5332{
5333 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5334
4dfe6ac6
NC		 5335 if (htab == NULL)
5336 return;
5337
906e58ca
NC		 5338 if (isec->output_section->index <= htab->top_index)
5339 {
5340 asection **list = htab->input_list + isec->output_section->index;
5341
a7470592 5342 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5343 {
5344 /* Steal the link_sec pointer for our list. */
5345#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5346 /* This happens to make the list in reverse order,
07d72278 5347 which we reverse later. */
906e58ca
NC		 5348 PREV_SEC (isec) = *list;
5349 *list = isec;
5350 }
5351 }
5352}
5353
5354/* See whether we can group stub sections together. Grouping stub
5355 sections may result in fewer stubs. More importantly, we need to
07d72278 5356 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5357 .fini output sections respectively, because glibc splits the
5358 _init and _fini functions into multiple parts. Putting a stub in
5359 the middle of a function is not a good idea. */
5360
5361static void
5362group_sections (struct elf32_arm_link_hash_table *htab,
5363 bfd_size_type stub_group_size,
07d72278 5364 bfd_boolean stubs_always_after_branch)
906e58ca 5365{
07d72278 5366 asection **list = htab->input_list;
906e58ca
NC		 5367
5368 do
5369 {
5370 asection *tail = *list;
07d72278 5371 asection *head;
906e58ca
NC		 5372
5373 if (tail == bfd_abs_section_ptr)
5374 continue;
5375
07d72278
DJ		 5376 /* Reverse the list: we must avoid placing stubs at the
5377 beginning of the section because the beginning of the text
5378 section may be required for an interrupt vector in bare metal
5379 code. */
5380#define NEXT_SEC PREV_SEC
e780aef2
CL		 5381 head = NULL;
5382 while (tail != NULL)
99059e56
RM		 5383 {
5384 /* Pop from tail. */
5385 asection *item = tail;
5386 tail = PREV_SEC (item);
e780aef2 5387
99059e56
RM		 5388 /* Push on head. */
5389 NEXT_SEC (item) = head;
5390 head = item;
5391 }
07d72278
DJ		 5392
5393 while (head != NULL)
906e58ca
NC		 5394 {
5395 asection *curr;
07d72278 5396 asection *next;
e780aef2
CL		 5397 bfd_vma stub_group_start = head->output_offset;
5398 bfd_vma end_of_next;
906e58ca 5399
07d72278 5400 curr = head;
e780aef2 5401 while (NEXT_SEC (curr) != NULL)
8cd931b7 5402 {
e780aef2
CL		 5403 next = NEXT_SEC (curr);
5404 end_of_next = next->output_offset + next->size;
5405 if (end_of_next - stub_group_start >= stub_group_size)
5406 /* End of NEXT is too far from start, so stop. */
8cd931b7 5407 break;
e780aef2
CL		 5408 /* Add NEXT to the group. */
5409 curr = next;
8cd931b7 5410 }
906e58ca 5411
07d72278 5412 /* OK, the size from the start to the start of CURR is less
906e58ca 5413 than stub_group_size and thus can be handled by one stub
07d72278 5414 section. (Or the head section is itself larger than
906e58ca
NC		 5415 stub_group_size, in which case we may be toast.)
5416 We should really be keeping track of the total size of
5417 stubs added here, as stubs contribute to the final output
7fb9f789 5418 section size. */
906e58ca
NC		 5419 do
5420 {
07d72278 5421 next = NEXT_SEC (head);
906e58ca 5422 /* Set up this stub group. */
07d72278 5423 htab->stub_group[head->id].link_sec = curr;
906e58ca 5424 }
07d72278 5425 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5426
5427 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5428 bytes after the stub section can be handled by it too. */
5429 if (!stubs_always_after_branch)
906e58ca 5430 {
e780aef2
CL		 5431 stub_group_start = curr->output_offset + curr->size;
5432
8cd931b7 5433 while (next != NULL)
906e58ca 5434 {
e780aef2
CL		 5435 end_of_next = next->output_offset + next->size;
5436 if (end_of_next - stub_group_start >= stub_group_size)
5437 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5438 break;
e780aef2 5439 /* Add NEXT to the stub group. */
07d72278
DJ		 5440 head = next;
5441 next = NEXT_SEC (head);
5442 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5443 }
5444 }
07d72278 5445 head = next;
906e58ca
NC		 5446 }
5447 }
07d72278 5448 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5449
5450 free (htab->input_list);
5451#undef PREV_SEC
07d72278 5452#undef NEXT_SEC
906e58ca
NC		 5453}
5454
48229727
JB		 5455/* Comparison function for sorting/searching relocations relating to Cortex-A8
5456 erratum fix. */
5457
5458static int
5459a8_reloc_compare (const void *a, const void *b)
5460{
21d799b5
NC		 5461 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5462 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5463
5464 if (ra->from < rb->from)
5465 return -1;
5466 else if (ra->from > rb->from)
5467 return 1;
5468 else
5469 return 0;
5470}
5471
5472static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5473 const char *, char **);
5474
5475/* Helper function to scan code for sequences which might trigger the Cortex-A8
5476 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5477 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5478 otherwise. */
5479
81694485
NC		 5480static bfd_boolean
5481cortex_a8_erratum_scan (bfd *input_bfd,
5482 struct bfd_link_info *info,
48229727
JB		 5483 struct a8_erratum_fix **a8_fixes_p,
5484 unsigned int *num_a8_fixes_p,
5485 unsigned int *a8_fix_table_size_p,
5486 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5487 unsigned int num_a8_relocs,
5488 unsigned prev_num_a8_fixes,
5489 bfd_boolean *stub_changed_p)
48229727
JB		 5490{
5491 asection *section;
5492 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5493 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5494 unsigned int num_a8_fixes = *num_a8_fixes_p;
5495 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5496
4dfe6ac6
NC		 5497 if (htab == NULL)
5498 return FALSE;
5499
48229727
JB		 5500 for (section = input_bfd->sections;
5501 section != NULL;
5502 section = section->next)
5503 {
5504 bfd_byte *contents = NULL;
5505 struct _arm_elf_section_data *sec_data;
5506 unsigned int span;
5507 bfd_vma base_vma;
5508
5509 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5510 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5511 || (section->flags & SEC_EXCLUDE) != 0
5512 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5513 || (section->output_section == bfd_abs_section_ptr))
5514 continue;
48229727
JB		 5515
5516 base_vma = section->output_section->vma + section->output_offset;
5517
5518 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5519 contents = elf_section_data (section)->this_hdr.contents;
48229727 5520 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5521 return TRUE;
48229727
JB		 5522
5523 sec_data = elf32_arm_section_data (section);
5524
5525 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5526 {
5527 unsigned int span_start = sec_data->map[span].vma;
5528 unsigned int span_end = (span == sec_data->mapcount - 1)
5529 ? section->size : sec_data->map[span + 1].vma;
5530 unsigned int i;
5531 char span_type = sec_data->map[span].type;
5532 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5533
5534 if (span_type != 't')
5535 continue;
5536
5537 /* Span is entirely within a single 4KB region: skip scanning. */
5538 if (((base_vma + span_start) & ~0xfff)
48229727 5539 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5540 continue;
5541
5542 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5543
5544 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5545 * The branch target is in the same 4KB region as the
5546 first half of the branch.
5547 * The instruction before the branch is a 32-bit
5548 length non-branch instruction. */
5549 for (i = span_start; i < span_end;)
5550 {
5551 unsigned int insn = bfd_getl16 (&contents[i]);
5552 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5553 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5554
99059e56
RM		 5555 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5556 insn_32bit = TRUE;
48229727
JB		 5557
5558 if (insn_32bit)
99059e56
RM		 5559 {
5560 /* Load the rest of the insn (in manual-friendly order). */
5561 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5562
5563 /* Encoding T4: B<c>.W. */
5564 is_b = (insn & 0xf800d000) == 0xf0009000;
5565 /* Encoding T1: BL<c>.W. */
5566 is_bl = (insn & 0xf800d000) == 0xf000d000;
5567 /* Encoding T2: BLX<c>.W. */
5568 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5569 /* Encoding T3: B<c>.W (not permitted in IT block). */
5570 is_bcc = (insn & 0xf800d000) == 0xf0008000
5571 && (insn & 0x07f00000) != 0x03800000;
5572 }
5573
5574 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5575
99059e56 5576 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5577 && insn_32bit
5578 && is_32bit_branch
5579 && last_was_32bit
5580 && ! last_was_branch)
99059e56
RM		 5581 {
5582 bfd_signed_vma offset = 0;
5583 bfd_boolean force_target_arm = FALSE;
48229727 5584 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5585 bfd_vma target;
5586 enum elf32_arm_stub_type stub_type = arm_stub_none;
5587 struct a8_erratum_reloc key, *found;
5588 bfd_boolean use_plt = FALSE;
48229727 5589
99059e56
RM		 5590 key.from = base_vma + i;
5591 found = (struct a8_erratum_reloc *)
5592 bsearch (&key, a8_relocs, num_a8_relocs,
5593 sizeof (struct a8_erratum_reloc),
5594 &a8_reloc_compare);
48229727
JB		 5595
5596 if (found)
5597 {
5598 char *error_message = NULL;
5599 struct elf_link_hash_entry *entry;
5600
5601 /* We don't care about the error returned from this
99059e56 5602 function, only if there is glue or not. */
48229727
JB		 5603 entry = find_thumb_glue (info, found->sym_name,
5604 &error_message);
5605
5606 if (entry)
5607 found->non_a8_stub = TRUE;
5608
92750f34 5609 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5610 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5611 && found->hash->root.plt.offset != (bfd_vma) -1)
5612 use_plt = TRUE;
5613
5614 if (found->r_type == R_ARM_THM_CALL)
5615 {
35fc36a8
RS		 5616 if (found->branch_type == ST_BRANCH_TO_ARM
5617 || use_plt)
92750f34
DJ		 5618 force_target_arm = TRUE;
5619 else
5620 force_target_thumb = TRUE;
5621 }
48229727
JB		 5622 }
5623
99059e56 5624 /* Check if we have an offending branch instruction. */
48229727
JB		 5625
5626 if (found && found->non_a8_stub)
5627 /* We've already made a stub for this instruction, e.g.
5628 it's a long branch or a Thumb->ARM stub. Assume that
5629 stub will suffice to work around the A8 erratum (see
5630 setting of always_after_branch above). */
5631 ;
99059e56
RM		 5632 else if (is_bcc)
5633 {
5634 offset = (insn & 0x7ff) << 1;
5635 offset |= (insn & 0x3f0000) >> 4;
5636 offset |= (insn & 0x2000) ? 0x40000 : 0;
5637 offset |= (insn & 0x800) ? 0x80000 : 0;
5638 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5639 if (offset & 0x100000)
5640 offset |= ~ ((bfd_signed_vma) 0xfffff);
5641 stub_type = arm_stub_a8_veneer_b_cond;
5642 }
5643 else if (is_b || is_bl || is_blx)
5644 {
5645 int s = (insn & 0x4000000) != 0;
5646 int j1 = (insn & 0x2000) != 0;
5647 int j2 = (insn & 0x800) != 0;
5648 int i1 = !(j1 ^ s);
5649 int i2 = !(j2 ^ s);
5650
5651 offset = (insn & 0x7ff) << 1;
5652 offset |= (insn & 0x3ff0000) >> 4;
5653 offset |= i2 << 22;
5654 offset |= i1 << 23;
5655 offset |= s << 24;
5656 if (offset & 0x1000000)
5657 offset |= ~ ((bfd_signed_vma) 0xffffff);
5658
5659 if (is_blx)
5660 offset &= ~ ((bfd_signed_vma) 3);
5661
5662 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5663 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5664 }
5665
5666 if (stub_type != arm_stub_none)
5667 {
5668 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5669
5670 /* The original instruction is a BL, but the target is
99059e56 5671 an ARM instruction. If we were not making a stub,
48229727
JB		 5672 the BL would have been converted to a BLX. Use the
5673 BLX stub instead in that case. */
5674 if (htab->use_blx && force_target_arm
5675 && stub_type == arm_stub_a8_veneer_bl)
5676 {
5677 stub_type = arm_stub_a8_veneer_blx;
5678 is_blx = TRUE;
5679 is_bl = FALSE;
5680 }
5681 /* Conversely, if the original instruction was
5682 BLX but the target is Thumb mode, use the BL
5683 stub. */
5684 else if (force_target_thumb
5685 && stub_type == arm_stub_a8_veneer_blx)
5686 {
5687 stub_type = arm_stub_a8_veneer_bl;
5688 is_blx = FALSE;
5689 is_bl = TRUE;
5690 }
5691
99059e56
RM		 5692 if (is_blx)
5693 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5694
99059e56
RM		 5695 /* If we found a relocation, use the proper destination,
5696 not the offset in the (unrelocated) instruction.
48229727
JB		 5697 Note this is always done if we switched the stub type
5698 above. */
99059e56
RM		 5699 if (found)
5700 offset =
81694485 5701 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5702
99059e56
RM		 5703 /* If the stub will use a Thumb-mode branch to a
5704 PLT target, redirect it to the preceding Thumb
5705 entry point. */
5706 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5707 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5708
99059e56 5709 target = pc_for_insn + offset;
48229727 5710
99059e56
RM		 5711 /* The BLX stub is ARM-mode code. Adjust the offset to
5712 take the different PC value (+8 instead of +4) into
48229727 5713 account. */
99059e56
RM		 5714 if (stub_type == arm_stub_a8_veneer_blx)
5715 offset += 4;
5716
5717 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5718 {
5719 char *stub_name = NULL;
5720
5721 if (num_a8_fixes == a8_fix_table_size)
5722 {
5723 a8_fix_table_size *= 2;
5724 a8_fixes = (struct a8_erratum_fix *)
5725 bfd_realloc (a8_fixes,
5726 sizeof (struct a8_erratum_fix)
5727 * a8_fix_table_size);
5728 }
48229727 5729
eb7c4339
NS		 5730 if (num_a8_fixes < prev_num_a8_fixes)
5731 {
5732 /* If we're doing a subsequent scan,
5733 check if we've found the same fix as
5734 before, and try and reuse the stub
5735 name. */
5736 stub_name = a8_fixes[num_a8_fixes].stub_name;
5737 if ((a8_fixes[num_a8_fixes].section != section)
5738 || (a8_fixes[num_a8_fixes].offset != i))
5739 {
5740 free (stub_name);
5741 stub_name = NULL;
5742 *stub_changed_p = TRUE;
5743 }
5744 }
5745
5746 if (!stub_name)
5747 {
21d799b5 5748 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5749 if (stub_name != NULL)
5750 sprintf (stub_name, "%x:%x", section->id, i);
5751 }
48229727 5752
99059e56
RM		 5753 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5754 a8_fixes[num_a8_fixes].section = section;
5755 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5756 a8_fixes[num_a8_fixes].target_offset =
5757 target - base_vma;
99059e56
RM		 5758 a8_fixes[num_a8_fixes].orig_insn = insn;
5759 a8_fixes[num_a8_fixes].stub_name = stub_name;
5760 a8_fixes[num_a8_fixes].stub_type = stub_type;
5761 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5762 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5763
99059e56
RM		 5764 num_a8_fixes++;
5765 }
5766 }
5767 }
48229727 5768
99059e56
RM		 5769 i += insn_32bit ? 4 : 2;
5770 last_was_32bit = insn_32bit;
48229727 5771 last_was_branch = is_32bit_branch;
99059e56
RM		 5772 }
5773 }
48229727
JB		 5774
5775 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5776 free (contents);
48229727 5777 }
fe33d2fa 5778
48229727
JB		 5779 *a8_fixes_p = a8_fixes;
5780 *num_a8_fixes_p = num_a8_fixes;
5781 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5782
81694485 5783 return FALSE;
48229727
JB		 5784}
5785
b715f643
TP		 5786/* Create or update a stub entry depending on whether the stub can already be
5787 found in HTAB. The stub is identified by:
5788 - its type STUB_TYPE
5789 - its source branch (note that several can share the same stub) whose
5790 section and relocation (if any) are given by SECTION and IRELA
5791 respectively
5792 - its target symbol whose input section, hash, name, value and branch type
5793 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5794 respectively
5795
5796 If found, the value of the stub's target symbol is updated from SYM_VALUE
5797 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5798 TRUE and the stub entry is initialized.
5799
0955507f
TP		 5800 Returns the stub that was created or updated, or NULL if an error
5801 occurred. */
b715f643 5802
0955507f 5803static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5804elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5805 enum elf32_arm_stub_type stub_type, asection *section,
5806 Elf_Internal_Rela *irela, asection *sym_sec,
5807 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5808 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5809 bfd_boolean *new_stub)
5810{
5811 const asection *id_sec;
5812 char *stub_name;
5813 struct elf32_arm_stub_hash_entry *stub_entry;
5814 unsigned int r_type;
4f4faa4d 5815 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5816
5817 BFD_ASSERT (stub_type != arm_stub_none);
5818 *new_stub = FALSE;
5819
4f4faa4d
TP		 5820 if (sym_claimed)
5821 stub_name = sym_name;
5822 else
5823 {
5824 BFD_ASSERT (irela);
5825 BFD_ASSERT (section);
c2abbbeb 5826 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5827
4f4faa4d
TP		 5828 /* Support for grouping stub sections. */
5829 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5830
4f4faa4d
TP		 5831 /* Get the name of this stub. */
5832 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5833 stub_type);
5834 if (!stub_name)
0955507f 5835 return NULL;
4f4faa4d 5836 }
b715f643
TP		 5837
5838 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5839 FALSE);
5840 /* The proper stub has already been created, just update its value. */
5841 if (stub_entry != NULL)
5842 {
4f4faa4d
TP		 5843 if (!sym_claimed)
5844 free (stub_name);
b715f643 5845 stub_entry->target_value = sym_value;
0955507f 5846 return stub_entry;
b715f643
TP		 5847 }
5848
daa4adae 5849 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5850 if (stub_entry == NULL)
5851 {
4f4faa4d
TP		 5852 if (!sym_claimed)
5853 free (stub_name);
0955507f 5854 return NULL;
b715f643
TP		 5855 }
5856
5857 stub_entry->target_value = sym_value;
5858 stub_entry->target_section = sym_sec;
5859 stub_entry->stub_type = stub_type;
5860 stub_entry->h = hash;
5861 stub_entry->branch_type = branch_type;
5862
4f4faa4d
TP		 5863 if (sym_claimed)
5864 stub_entry->output_name = sym_name;
5865 else
b715f643 5866 {
4f4faa4d
TP		 5867 if (sym_name == NULL)
5868 sym_name = "unnamed";
5869 stub_entry->output_name = (char *)
5870 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5871 + strlen (sym_name));
5872 if (stub_entry->output_name == NULL)
5873 {
5874 free (stub_name);
0955507f 5875 return NULL;
4f4faa4d 5876 }
b715f643 5877
4f4faa4d
TP		 5878 /* For historical reasons, use the existing names for ARM-to-Thumb and
5879 Thumb-to-ARM stubs. */
5880 r_type = ELF32_R_TYPE (irela->r_info);
5881 if ((r_type == (unsigned int) R_ARM_THM_CALL
5882 || r_type == (unsigned int) R_ARM_THM_JUMP24
5883 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5884 && branch_type == ST_BRANCH_TO_ARM)
5885 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5886 else if ((r_type == (unsigned int) R_ARM_CALL
5887 || r_type == (unsigned int) R_ARM_JUMP24)
5888 && branch_type == ST_BRANCH_TO_THUMB)
5889 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5890 else
5891 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5892 }
b715f643
TP		 5893
5894 *new_stub = TRUE;
0955507f 5895 return stub_entry;
b715f643
TP		 5896}
5897
4ba2ef8f
TP		 5898/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5899 gateway veneer to transition from non secure to secure state and create them
5900 accordingly.
5901
5902 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5903 defines the conditions that govern Secure Gateway veneer creation for a
5904 given symbol <SYM> as follows:
5905 - it has function type
5906 - it has non local binding
5907 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5908 same type, binding and value as <SYM> (called normal symbol).
5909 An entry function can handle secure state transition itself in which case
5910 its special symbol would have a different value from the normal symbol.
5911
5912 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5913 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5914 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5915 created.
4ba2ef8f 5916
0955507f 5917 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5918
5919static bfd_boolean
5920cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5921 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5922 int *cmse_stub_created)
4ba2ef8f
TP		 5923{
5924 const struct elf_backend_data *bed;
5925 Elf_Internal_Shdr *symtab_hdr;
5926 unsigned i, j, sym_count, ext_start;
5927 Elf_Internal_Sym *cmse_sym, *local_syms;
5928 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5929 enum arm_st_branch_type branch_type;
5930 char *sym_name, *lsym_name;
5931 bfd_vma sym_value;
5932 asection *section;
0955507f
TP		 5933 struct elf32_arm_stub_hash_entry *stub_entry;
5934 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5935
5936 bed = get_elf_backend_data (input_bfd);
5937 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5938 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5939 ext_start = symtab_hdr->sh_info;
5940 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5941 && out_attr[Tag_CPU_arch_profile].i == 'M');
5942
5943 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5944 if (local_syms == NULL)
5945 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5946 symtab_hdr->sh_info, 0, NULL, NULL,
5947 NULL);
5948 if (symtab_hdr->sh_info && local_syms == NULL)
5949 return FALSE;
5950
5951 /* Scan symbols. */
5952 for (i = 0; i < sym_count; i++)
5953 {
5954 cmse_invalid = FALSE;
5955
5956 if (i < ext_start)
5957 {
5958 cmse_sym = &local_syms[i];
4ba2ef8f
TP		 5959 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5960 symtab_hdr->sh_link,
5961 cmse_sym->st_name);
baf46cd7
AM		 5962 if (!sym_name || !CONST_STRNEQ (sym_name, CMSE_PREFIX))
5963 continue;
5964
4ba2ef8f
TP		 5965 /* Special symbol with local binding. */
5966 cmse_invalid = TRUE;
5967 }
5968 else
5969 {
5970 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5971 sym_name = (char *) cmse_hash->root.root.root.string;
baf46cd7 5972 if (!CONST_STRNEQ (sym_name, CMSE_PREFIX))
4ba2ef8f
TP		 5973 continue;
5974
5975 /* Special symbol has incorrect binding or type. */
5976 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5977 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5978 || cmse_hash->root.type != STT_FUNC)
5979 cmse_invalid = TRUE;
5980 }
5981
5982 if (!is_v8m)
5983 {
90b6238f
AM		 5984 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
5985 "ARMv8-M architecture or later"),
4eca0228 5986 input_bfd, sym_name);
4ba2ef8f
TP		 5987 is_v8m = TRUE; /* Avoid multiple warning. */
5988 ret = FALSE;
5989 }
5990
5991 if (cmse_invalid)
5992 {
90b6238f
AM		 5993 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
5994 " a global or weak function symbol"),
4eca0228 5995 input_bfd, sym_name);
4ba2ef8f
TP		 5996 ret = FALSE;
5997 if (i < ext_start)
5998 continue;
5999 }
6000
6001 sym_name += strlen (CMSE_PREFIX);
6002 hash = (struct elf32_arm_link_hash_entry *)
6003 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6004
6005 /* No associated normal symbol or it is neither global nor weak. */
6006 if (!hash
6007 || (hash->root.root.type != bfd_link_hash_defined
6008 && hash->root.root.type != bfd_link_hash_defweak)
6009 || hash->root.type != STT_FUNC)
6010 {
6011 /* Initialize here to avoid warning about use of possibly
6012 uninitialized variable. */
6013 j = 0;
6014
6015 if (!hash)
6016 {
6017 /* Searching for a normal symbol with local binding. */
6018 for (; j < ext_start; j++)
6019 {
6020 lsym_name =
6021 bfd_elf_string_from_elf_section (input_bfd,
6022 symtab_hdr->sh_link,
6023 local_syms[j].st_name);
6024 if (!strcmp (sym_name, lsym_name))
6025 break;
6026 }
6027 }
6028
6029 if (hash || j < ext_start)
6030 {
4eca0228 6031 _bfd_error_handler
90b6238f
AM		 6032 (_("%pB: invalid standard symbol `%s'; it must be "
6033 "a global or weak function symbol"),
6034 input_bfd, sym_name);
4ba2ef8f
TP		 6035 }
6036 else
4eca0228 6037 _bfd_error_handler
90b6238f 6038 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 6039 ret = FALSE;
6040 if (!hash)
6041 continue;
6042 }
6043
6044 sym_value = hash->root.root.u.def.value;
6045 section = hash->root.root.u.def.section;
6046
6047 if (cmse_hash->root.root.u.def.section != section)
6048 {
4eca0228 6049 _bfd_error_handler
90b6238f 6050 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 6051 input_bfd, sym_name);
6052 ret = FALSE;
6053 }
6054 if (cmse_hash->root.root.u.def.value != sym_value)
6055 continue; /* Ignore: could be an entry function starting with SG. */
6056
6057 /* If this section is a link-once section that will be discarded, then
6058 don't create any stubs. */
6059 if (section->output_section == NULL)
6060 {
4eca0228 6061 _bfd_error_handler
90b6238f 6062 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 6063 continue;
6064 }
6065
6066 if (hash->root.size == 0)
6067 {
4eca0228 6068 _bfd_error_handler
90b6238f 6069 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 6070 ret = FALSE;
6071 }
6072
6073 if (!ret)
6074 continue;
6075 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 6076 stub_entry
4ba2ef8f
TP		 6077 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6078 NULL, NULL, section, hash, sym_name,
6079 sym_value, branch_type, &new_stub);
6080
0955507f 6081 if (stub_entry == NULL)
4ba2ef8f
TP		 6082 ret = FALSE;
6083 else
6084 {
6085 BFD_ASSERT (new_stub);
0955507f 6086 (*cmse_stub_created)++;
4ba2ef8f
TP		 6087 }
6088 }
6089
6090 if (!symtab_hdr->contents)
6091 free (local_syms);
6092 return ret;
6093}
6094
0955507f
TP		 6095/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6096 code entry function, ie can be called from non secure code without using a
6097 veneer. */
6098
6099static bfd_boolean
6100cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6101{
42484486 6102 bfd_byte contents[4];
0955507f
TP		 6103 uint32_t first_insn;
6104 asection *section;
6105 file_ptr offset;
6106 bfd *abfd;
6107
6108 /* Defined symbol of function type. */
6109 if (hash->root.root.type != bfd_link_hash_defined
6110 && hash->root.root.type != bfd_link_hash_defweak)
6111 return FALSE;
6112 if (hash->root.type != STT_FUNC)
6113 return FALSE;
6114
6115 /* Read first instruction. */
6116 section = hash->root.root.u.def.section;
6117 abfd = section->owner;
6118 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 6119 if (!bfd_get_section_contents (abfd, section, contents, offset,
6120 sizeof (contents)))
0955507f
TP		 6121 return FALSE;
6122
42484486
TP		 6123 first_insn = bfd_get_32 (abfd, contents);
6124
6125 /* Starts by SG instruction. */
0955507f
TP		 6126 return first_insn == 0xe97fe97f;
6127}
6128
6129/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6130 secure gateway veneers (ie. the veneers was not in the input import library)
6131 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6132
6133static bfd_boolean
6134arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6135{
6136 struct elf32_arm_stub_hash_entry *stub_entry;
6137 struct bfd_link_info *info;
6138
6139 /* Massage our args to the form they really have. */
6140 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6141 info = (struct bfd_link_info *) gen_info;
6142
6143 if (info->out_implib_bfd)
6144 return TRUE;
6145
6146 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6147 return TRUE;
6148
6149 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 6150 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 6151
6152 return TRUE;
6153}
6154
6155/* Set offset of each secure gateway veneers so that its address remain
6156 identical to the one in the input import library referred by
6157 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6158 (present in input import library but absent from the executable being
6159 linked) or if new veneers appeared and there is no output import library
6160 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6161 number of secure gateway veneers found in the input import library.
6162
6163 The function returns whether an error occurred. If no error occurred,
6164 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6165 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6166 veneer observed set for new veneers to be layed out after. */
6167
6168static bfd_boolean
6169set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6170 struct elf32_arm_link_hash_table *htab,
6171 int *cmse_stub_created)
6172{
6173 long symsize;
6174 char *sym_name;
6175 flagword flags;
6176 long i, symcount;
6177 bfd *in_implib_bfd;
6178 asection *stub_out_sec;
6179 bfd_boolean ret = TRUE;
6180 Elf_Internal_Sym *intsym;
6181 const char *out_sec_name;
6182 bfd_size_type cmse_stub_size;
6183 asymbol **sympp = NULL, *sym;
6184 struct elf32_arm_link_hash_entry *hash;
6185 const insn_sequence *cmse_stub_template;
6186 struct elf32_arm_stub_hash_entry *stub_entry;
6187 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6188 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6189 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6190
6191 /* No input secure gateway import library. */
6192 if (!htab->in_implib_bfd)
6193 return TRUE;
6194
6195 in_implib_bfd = htab->in_implib_bfd;
6196 if (!htab->cmse_implib)
6197 {
871b3ab2 6198 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 6199 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 6200 return FALSE;
6201 }
6202
6203 /* Get symbol table size. */
6204 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6205 if (symsize < 0)
6206 return FALSE;
6207
6208 /* Read in the input secure gateway import library's symbol table. */
9a733151
AM		 6209 sympp = (asymbol **) bfd_malloc (symsize);
6210 if (sympp == NULL)
6211 return FALSE;
6212
0955507f
TP		 6213 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6214 if (symcount < 0)
6215 {
6216 ret = FALSE;
6217 goto free_sym_buf;
6218 }
6219
6220 htab->new_cmse_stub_offset = 0;
6221 cmse_stub_size =
6222 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6223 &cmse_stub_template,
6224 &cmse_stub_template_size);
6225 out_sec_name =
6226 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6227 stub_out_sec =
6228 bfd_get_section_by_name (htab->obfd, out_sec_name);
6229 if (stub_out_sec != NULL)
6230 cmse_stub_sec_vma = stub_out_sec->vma;
6231
6232 /* Set addresses of veneers mentionned in input secure gateway import
6233 library's symbol table. */
6234 for (i = 0; i < symcount; i++)
6235 {
6236 sym = sympp[i];
6237 flags = sym->flags;
6238 sym_name = (char *) bfd_asymbol_name (sym);
6239 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6240
6241 if (sym->section != bfd_abs_section_ptr
6242 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6243 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6244 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6245 != ST_BRANCH_TO_THUMB))
6246 {
90b6238f
AM		 6247 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6248 "symbol should be absolute, global and "
6249 "refer to Thumb functions"),
4eca0228 6250 in_implib_bfd, sym_name);
0955507f
TP		 6251 ret = FALSE;
6252 continue;
6253 }
6254
6255 veneer_value = bfd_asymbol_value (sym);
6256 stub_offset = veneer_value - cmse_stub_sec_vma;
6257 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6258 FALSE, FALSE);
6259 hash = (struct elf32_arm_link_hash_entry *)
6260 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6261
6262 /* Stub entry should have been created by cmse_scan or the symbol be of
6263 a secure function callable from non secure code. */
6264 if (!stub_entry && !hash)
6265 {
6266 bfd_boolean new_stub;
6267
4eca0228 6268 _bfd_error_handler
90b6238f 6269 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6270 hash = (struct elf32_arm_link_hash_entry *)
6271 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6272 stub_entry
6273 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6274 NULL, NULL, bfd_abs_section_ptr, hash,
6275 sym_name, veneer_value,
6276 ST_BRANCH_TO_THUMB, &new_stub);
6277 if (stub_entry == NULL)
6278 ret = FALSE;
6279 else
6280 {
6281 BFD_ASSERT (new_stub);
6282 new_cmse_stubs_created++;
6283 (*cmse_stub_created)++;
6284 }
6285 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6286 stub_entry->stub_offset = stub_offset;
6287 }
6288 /* Symbol found is not callable from non secure code. */
6289 else if (!stub_entry)
6290 {
6291 if (!cmse_entry_fct_p (hash))
6292 {
90b6238f 6293 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6294 sym_name);
0955507f
TP		 6295 ret = FALSE;
6296 }
6297 continue;
6298 }
6299 else
6300 {
6301 /* Only stubs for SG veneers should have been created. */
6302 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6303
6304 /* Check visibility hasn't changed. */
6305 if (!!(flags & BSF_GLOBAL)
6306 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6307 _bfd_error_handler
90b6238f 6308 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6309 sym_name);
6310
6311 stub_entry->stub_offset = stub_offset;
6312 }
6313
6314 /* Size should match that of a SG veneer. */
6315 if (intsym->st_size != cmse_stub_size)
6316 {
90b6238f 6317 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6318 in_implib_bfd, sym_name);
0955507f
TP		 6319 ret = FALSE;
6320 }
6321
6322 /* Previous veneer address is before current SG veneer section. */
6323 if (veneer_value < cmse_stub_sec_vma)
6324 {
6325 /* Avoid offset underflow. */
6326 if (stub_entry)
6327 stub_entry->stub_offset = 0;
6328 stub_offset = 0;
6329 ret = FALSE;
6330 }
6331
6332 /* Complain if stub offset not a multiple of stub size. */
6333 if (stub_offset % cmse_stub_size)
6334 {
4eca0228 6335 _bfd_error_handler
90b6238f
AM		 6336 (_("offset of veneer for entry function `%s' not a multiple of "
6337 "its size"), sym_name);
0955507f
TP		 6338 ret = FALSE;
6339 }
6340
6341 if (!ret)
6342 continue;
6343
6344 new_cmse_stubs_created--;
6345 if (veneer_value < cmse_stub_array_start)
6346 cmse_stub_array_start = veneer_value;
6347 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6348 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6349 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6350 }
6351
6352 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6353 {
6354 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6355 _bfd_error_handler
0955507f
TP		 6356 (_("new entry function(s) introduced but no output import library "
6357 "specified:"));
6358 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6359 }
6360
6361 if (cmse_stub_array_start != cmse_stub_sec_vma)
6362 {
4eca0228 6363 _bfd_error_handler
90b6238f 6364 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6365 out_sec_name);
6366 ret = FALSE;
6367 }
6368
dc1e8a47 6369 free_sym_buf:
0955507f
TP		 6370 free (sympp);
6371 return ret;
6372}
6373
906e58ca
NC		 6374/* Determine and set the size of the stub section for a final link.
6375
6376 The basic idea here is to examine all the relocations looking for
6377 PC-relative calls to a target that is unreachable with a "bl"
6378 instruction. */
6379
6380bfd_boolean
6381elf32_arm_size_stubs (bfd *output_bfd,
6382 bfd *stub_bfd,
6383 struct bfd_link_info *info,
6384 bfd_signed_vma group_size,
7a89b94e 6385 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6386 asection *,
7a89b94e 6387 unsigned int),
906e58ca
NC		 6388 void (*layout_sections_again) (void))
6389{
0955507f 6390 bfd_boolean ret = TRUE;
4ba2ef8f 6391 obj_attribute *out_attr;
0955507f 6392 int cmse_stub_created = 0;
906e58ca 6393 bfd_size_type stub_group_size;
4ba2ef8f 6394 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6395 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6396 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6397 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6398 struct a8_erratum_reloc *a8_relocs = NULL;
6399 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6400
4dfe6ac6
NC		 6401 if (htab == NULL)
6402 return FALSE;
6403
48229727
JB		 6404 if (htab->fix_cortex_a8)
6405 {
21d799b5 6406 a8_fixes = (struct a8_erratum_fix *)
99059e56 6407 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6408 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6409 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6410 }
906e58ca
NC		 6411
6412 /* Propagate mach to stub bfd, because it may not have been
6413 finalized when we created stub_bfd. */
6414 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6415 bfd_get_mach (output_bfd));
6416
6417 /* Stash our params away. */
6418 htab->stub_bfd = stub_bfd;
6419 htab->add_stub_section = add_stub_section;
6420 htab->layout_sections_again = layout_sections_again;
07d72278 6421 stubs_always_after_branch = group_size < 0;
48229727 6422
4ba2ef8f
TP		 6423 out_attr = elf_known_obj_attributes_proc (output_bfd);
6424 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6425
48229727
JB		 6426 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6427 as the first half of a 32-bit branch straddling two 4K pages. This is a
6428 crude way of enforcing that. */
6429 if (htab->fix_cortex_a8)
6430 stubs_always_after_branch = 1;
6431
906e58ca
NC		 6432 if (group_size < 0)
6433 stub_group_size = -group_size;
6434 else
6435 stub_group_size = group_size;
6436
6437 if (stub_group_size == 1)
6438 {
6439 /* Default values. */
6440 /* Thumb branch range is +-4MB has to be used as the default
6441 maximum size (a given section can contain both ARM and Thumb
6442 code, so the worst case has to be taken into account).
6443
6444 This value is 24K less than that, which allows for 2025
6445 12-byte stubs. If we exceed that, then we will fail to link.
6446 The user will have to relink with an explicit group size
6447 option. */
6448 stub_group_size = 4170000;
6449 }
6450
07d72278 6451 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6452
3ae046cc
NS		 6453 /* If we're applying the cortex A8 fix, we need to determine the
6454 program header size now, because we cannot change it later --
6455 that could alter section placements. Notice the A8 erratum fix
6456 ends up requiring the section addresses to remain unchanged
6457 modulo the page size. That's something we cannot represent
6458 inside BFD, and we don't want to force the section alignment to
6459 be the page size. */
6460 if (htab->fix_cortex_a8)
6461 (*htab->layout_sections_again) ();
6462
906e58ca
NC		 6463 while (1)
6464 {
6465 bfd *input_bfd;
6466 unsigned int bfd_indx;
6467 asection *stub_sec;
d7c5bd02 6468 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6469 bfd_boolean stub_changed = FALSE;
6470 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6471
48229727 6472 num_a8_fixes = 0;
906e58ca
NC		 6473 for (input_bfd = info->input_bfds, bfd_indx = 0;
6474 input_bfd != NULL;
c72f2fb2 6475 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6476 {
6477 Elf_Internal_Shdr *symtab_hdr;
6478 asection *section;
6479 Elf_Internal_Sym *local_syms = NULL;
6480
73d5efd7
AM		 6481 if (!is_arm_elf (input_bfd))
6482 continue;
6483 if ((input_bfd->flags & DYNAMIC) != 0
6484 && (elf_sym_hashes (input_bfd) == NULL
6485 || (elf_dyn_lib_class (input_bfd) & DYN_AS_NEEDED) != 0))
99059e56 6486 continue;
adbcc655 6487
48229727
JB		 6488 num_a8_relocs = 0;
6489
906e58ca
NC		 6490 /* We'll need the symbol table in a second. */
6491 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6492 if (symtab_hdr->sh_info == 0)
6493 continue;
6494
4ba2ef8f
TP		 6495 /* Limit scan of symbols to object file whose profile is
6496 Microcontroller to not hinder performance in the general case. */
6497 if (m_profile && first_veneer_scan)
6498 {
6499 struct elf_link_hash_entry **sym_hashes;
6500
6501 sym_hashes = elf_sym_hashes (input_bfd);
6502 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6503 &cmse_stub_created))
4ba2ef8f 6504 goto error_ret_free_local;
0955507f
TP		 6505
6506 if (cmse_stub_created != 0)
6507 stub_changed = TRUE;
4ba2ef8f
TP		 6508 }
6509
906e58ca
NC		 6510 /* Walk over each section attached to the input bfd. */
6511 for (section = input_bfd->sections;
6512 section != NULL;
6513 section = section->next)
6514 {
6515 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6516
6517 /* If there aren't any relocs, then there's nothing more
6518 to do. */
6519 if ((section->flags & SEC_RELOC) == 0
6520 || section->reloc_count == 0
6521 || (section->flags & SEC_CODE) == 0)
6522 continue;
6523
6524 /* If this section is a link-once section that will be
6525 discarded, then don't create any stubs. */
6526 if (section->output_section == NULL
6527 || section->output_section->owner != output_bfd)
6528 continue;
6529
6530 /* Get the relocs. */
6531 internal_relocs
6532 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6533 NULL, info->keep_memory);
6534 if (internal_relocs == NULL)
6535 goto error_ret_free_local;
6536
6537 /* Now examine each relocation. */
6538 irela = internal_relocs;
6539 irelaend = irela + section->reloc_count;
6540 for (; irela < irelaend; irela++)
6541 {
6542 unsigned int r_type, r_indx;
906e58ca
NC		 6543 asection *sym_sec;
6544 bfd_vma sym_value;
6545 bfd_vma destination;
6546 struct elf32_arm_link_hash_entry *hash;
7413f23f 6547 const char *sym_name;
34e77a92 6548 unsigned char st_type;
35fc36a8 6549 enum arm_st_branch_type branch_type;
48229727 6550 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6551
6552 r_type = ELF32_R_TYPE (irela->r_info);
6553 r_indx = ELF32_R_SYM (irela->r_info);
6554
6555 if (r_type >= (unsigned int) R_ARM_max)
6556 {
6557 bfd_set_error (bfd_error_bad_value);
6558 error_ret_free_internal:
6559 if (elf_section_data (section)->relocs == NULL)
6560 free (internal_relocs);
15dd01b1
TP		 6561 /* Fall through. */
6562 error_ret_free_local:
c9594989 6563 if (symtab_hdr->contents != (unsigned char *) local_syms)
15dd01b1
TP		 6564 free (local_syms);
6565 return FALSE;
906e58ca 6566 }
b38cadfb 6567
0855e32b
NS		 6568 hash = NULL;
6569 if (r_indx >= symtab_hdr->sh_info)
6570 hash = elf32_arm_hash_entry
6571 (elf_sym_hashes (input_bfd)
6572 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6573
0855e32b
NS		 6574 /* Only look for stubs on branch instructions, or
6575 non-relaxed TLSCALL */
906e58ca 6576 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6577 && (r_type != (unsigned int) R_ARM_THM_CALL)
6578 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6579 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6580 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6581 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6582 && (r_type != (unsigned int) R_ARM_PLT32)
6583 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6584 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6585 && r_type == elf32_arm_tls_transition
6586 (info, r_type, &hash->root)
6587 && ((hash ? hash->tls_type
6588 : (elf32_arm_local_got_tls_type
6589 (input_bfd)[r_indx]))
6590 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6591 continue;
6592
6593 /* Now determine the call target, its name, value,
6594 section. */
6595 sym_sec = NULL;
6596 sym_value = 0;
6597 destination = 0;
7413f23f 6598 sym_name = NULL;
b38cadfb 6599
0855e32b
NS		 6600 if (r_type == (unsigned int) R_ARM_TLS_CALL
6601 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6602 {
6603 /* A non-relaxed TLS call. The target is the
6604 plt-resident trampoline and nothing to do
6605 with the symbol. */
6606 BFD_ASSERT (htab->tls_trampoline > 0);
6607 sym_sec = htab->root.splt;
6608 sym_value = htab->tls_trampoline;
6609 hash = 0;
34e77a92 6610 st_type = STT_FUNC;
35fc36a8 6611 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6612 }
6613 else if (!hash)
906e58ca
NC		 6614 {
6615 /* It's a local symbol. */
6616 Elf_Internal_Sym *sym;
906e58ca
NC		 6617
6618 if (local_syms == NULL)
6619 {
6620 local_syms
6621 = (Elf_Internal_Sym *) symtab_hdr->contents;
6622 if (local_syms == NULL)
6623 local_syms
6624 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6625 symtab_hdr->sh_info, 0,
6626 NULL, NULL, NULL);
6627 if (local_syms == NULL)
6628 goto error_ret_free_internal;
6629 }
6630
6631 sym = local_syms + r_indx;
f6d250ce
TS		 6632 if (sym->st_shndx == SHN_UNDEF)
6633 sym_sec = bfd_und_section_ptr;
6634 else if (sym->st_shndx == SHN_ABS)
6635 sym_sec = bfd_abs_section_ptr;
6636 else if (sym->st_shndx == SHN_COMMON)
6637 sym_sec = bfd_com_section_ptr;
6638 else
6639 sym_sec =
6640 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6641
ffcb4889
NS		 6642 if (!sym_sec)
6643 /* This is an undefined symbol. It can never
6a631e86 6644 be resolved. */
ffcb4889 6645 continue;
fe33d2fa 6646
906e58ca
NC		 6647 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6648 sym_value = sym->st_value;
6649 destination = (sym_value + irela->r_addend
6650 + sym_sec->output_offset
6651 + sym_sec->output_section->vma);
34e77a92 6652 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6653 branch_type =
6654 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6655 sym_name
6656 = bfd_elf_string_from_elf_section (input_bfd,
6657 symtab_hdr->sh_link,
6658 sym->st_name);
906e58ca
NC		 6659 }
6660 else
6661 {
6662 /* It's an external symbol. */
906e58ca
NC		 6663 while (hash->root.root.type == bfd_link_hash_indirect
6664 || hash->root.root.type == bfd_link_hash_warning)
6665 hash = ((struct elf32_arm_link_hash_entry *)
6666 hash->root.root.u.i.link);
6667
6668 if (hash->root.root.type == bfd_link_hash_defined
6669 || hash->root.root.type == bfd_link_hash_defweak)
6670 {
6671 sym_sec = hash->root.root.u.def.section;
6672 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6673
6674 struct elf32_arm_link_hash_table *globals =
6675 elf32_arm_hash_table (info);
6676
6677 /* For a destination in a shared library,
6678 use the PLT stub as target address to
6679 decide whether a branch stub is
6680 needed. */
4dfe6ac6 6681 if (globals != NULL
362d30a1 6682 && globals->root.splt != NULL
4dfe6ac6 6683 && hash != NULL
022f8312
CL		 6684 && hash->root.plt.offset != (bfd_vma) -1)
6685 {
362d30a1 6686 sym_sec = globals->root.splt;
022f8312
CL		 6687 sym_value = hash->root.plt.offset;
6688 if (sym_sec->output_section != NULL)
6689 destination = (sym_value
6690 + sym_sec->output_offset
6691 + sym_sec->output_section->vma);
6692 }
6693 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6694 destination = (sym_value + irela->r_addend
6695 + sym_sec->output_offset
6696 + sym_sec->output_section->vma);
6697 }
69c5861e
CL		 6698 else if ((hash->root.root.type == bfd_link_hash_undefined)
6699 || (hash->root.root.type == bfd_link_hash_undefweak))
6700 {
6701 /* For a shared library, use the PLT stub as
6702 target address to decide whether a long
6703 branch stub is needed.
6704 For absolute code, they cannot be handled. */
6705 struct elf32_arm_link_hash_table *globals =
6706 elf32_arm_hash_table (info);
6707
4dfe6ac6 6708 if (globals != NULL
362d30a1 6709 && globals->root.splt != NULL
4dfe6ac6 6710 && hash != NULL
69c5861e
CL		 6711 && hash->root.plt.offset != (bfd_vma) -1)
6712 {
362d30a1 6713 sym_sec = globals->root.splt;
69c5861e
CL		 6714 sym_value = hash->root.plt.offset;
6715 if (sym_sec->output_section != NULL)
6716 destination = (sym_value
6717 + sym_sec->output_offset
6718 + sym_sec->output_section->vma);
6719 }
6720 else
6721 continue;
6722 }
906e58ca
NC		 6723 else
6724 {
6725 bfd_set_error (bfd_error_bad_value);
6726 goto error_ret_free_internal;
6727 }
34e77a92 6728 st_type = hash->root.type;
39d911fc
TP		 6729 branch_type =
6730 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6731 sym_name = hash->root.root.root.string;
906e58ca
NC		 6732 }
6733
48229727 6734 do
7413f23f 6735 {
b715f643 6736 bfd_boolean new_stub;
0955507f 6737 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6738
48229727
JB		 6739 /* Determine what (if any) linker stub is needed. */
6740 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6741 st_type, &branch_type,
6742 hash, destination, sym_sec,
48229727
JB		 6743 input_bfd, sym_name);
6744 if (stub_type == arm_stub_none)
6745 break;
6746
48229727
JB		 6747 /* We've either created a stub for this reloc already,
6748 or we are about to. */
0955507f 6749 stub_entry =
b715f643
TP		 6750 elf32_arm_create_stub (htab, stub_type, section, irela,
6751 sym_sec, hash,
6752 (char *) sym_name, sym_value,
6753 branch_type, &new_stub);
7413f23f 6754
0955507f 6755 created_stub = stub_entry != NULL;
b715f643
TP		 6756 if (!created_stub)
6757 goto error_ret_free_internal;
6758 else if (!new_stub)
6759 break;
99059e56 6760 else
b715f643 6761 stub_changed = TRUE;
99059e56
RM		 6762 }
6763 while (0);
6764
6765 /* Look for relocations which might trigger Cortex-A8
6766 erratum. */
6767 if (htab->fix_cortex_a8
6768 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6769 || r_type == (unsigned int) R_ARM_THM_JUMP19
6770 || r_type == (unsigned int) R_ARM_THM_CALL
6771 || r_type == (unsigned int) R_ARM_THM_XPC22))
6772 {
6773 bfd_vma from = section->output_section->vma
6774 + section->output_offset
6775 + irela->r_offset;
6776
6777 if ((from & 0xfff) == 0xffe)
6778 {
6779 /* Found a candidate. Note we haven't checked the
6780 destination is within 4K here: if we do so (and
6781 don't create an entry in a8_relocs) we can't tell
6782 that a branch should have been relocated when
6783 scanning later. */
6784 if (num_a8_relocs == a8_reloc_table_size)
6785 {
6786 a8_reloc_table_size *= 2;
6787 a8_relocs = (struct a8_erratum_reloc *)
6788 bfd_realloc (a8_relocs,
6789 sizeof (struct a8_erratum_reloc)
6790 * a8_reloc_table_size);
6791 }
6792
6793 a8_relocs[num_a8_relocs].from = from;
6794 a8_relocs[num_a8_relocs].destination = destination;
6795 a8_relocs[num_a8_relocs].r_type = r_type;
6796 a8_relocs[num_a8_relocs].branch_type = branch_type;
6797 a8_relocs[num_a8_relocs].sym_name = sym_name;
6798 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6799 a8_relocs[num_a8_relocs].hash = hash;
6800
6801 num_a8_relocs++;
6802 }
6803 }
906e58ca
NC		 6804 }
6805
99059e56
RM		 6806 /* We're done with the internal relocs, free them. */
6807 if (elf_section_data (section)->relocs == NULL)
6808 free (internal_relocs);
6809 }
48229727 6810
99059e56 6811 if (htab->fix_cortex_a8)
48229727 6812 {
99059e56
RM		 6813 /* Sort relocs which might apply to Cortex-A8 erratum. */
6814 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6815 sizeof (struct a8_erratum_reloc),
99059e56 6816 &a8_reloc_compare);
48229727 6817
99059e56
RM		 6818 /* Scan for branches which might trigger Cortex-A8 erratum. */
6819 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6820 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6821 a8_relocs, num_a8_relocs,
6822 prev_num_a8_fixes, &stub_changed)
6823 != 0)
48229727 6824 goto error_ret_free_local;
5e681ec4 6825 }
7f991970
AM		 6826
6827 if (local_syms != NULL
6828 && symtab_hdr->contents != (unsigned char *) local_syms)
6829 {
6830 if (!info->keep_memory)
6831 free (local_syms);
6832 else
6833 symtab_hdr->contents = (unsigned char *) local_syms;
6834 }
5e681ec4
PB		 6835 }
6836
0955507f
TP		 6837 if (first_veneer_scan
6838 && !set_cmse_veneer_addr_from_implib (info, htab,
6839 &cmse_stub_created))
6840 ret = FALSE;
6841
eb7c4339 6842 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6843 stub_changed = TRUE;
48229727 6844
906e58ca
NC		 6845 if (!stub_changed)
6846 break;
5e681ec4 6847
906e58ca
NC		 6848 /* OK, we've added some stubs. Find out the new size of the
6849 stub sections. */
6850 for (stub_sec = htab->stub_bfd->sections;
6851 stub_sec != NULL;
6852 stub_sec = stub_sec->next)
3e6b1042
DJ		 6853 {
6854 /* Ignore non-stub sections. */
6855 if (!strstr (stub_sec->name, STUB_SUFFIX))
6856 continue;
6857
6858 stub_sec->size = 0;
6859 }
b34b2d70 6860
0955507f
TP		 6861 /* Add new SG veneers after those already in the input import
6862 library. */
6863 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6864 stub_type++)
6865 {
6866 bfd_vma *start_offset_p;
6867 asection **stub_sec_p;
6868
6869 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6870 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6871 if (start_offset_p == NULL)
6872 continue;
6873
6874 BFD_ASSERT (stub_sec_p != NULL);
6875 if (*stub_sec_p != NULL)
6876 (*stub_sec_p)->size = *start_offset_p;
6877 }
6878
d7c5bd02 6879 /* Compute stub section size, considering padding. */
906e58ca 6880 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6881 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6882 stub_type++)
6883 {
6884 int size, padding;
6885 asection **stub_sec_p;
6886
6887 padding = arm_dedicated_stub_section_padding (stub_type);
6888 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6889 /* Skip if no stub input section or no stub section padding
6890 required. */
6891 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6892 continue;
6893 /* Stub section padding required but no dedicated section. */
6894 BFD_ASSERT (stub_sec_p);
6895
6896 size = (*stub_sec_p)->size;
6897 size = (size + padding - 1) & ~(padding - 1);
6898 (*stub_sec_p)->size = size;
6899 }
906e58ca 6900
48229727
JB		 6901 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6902 if (htab->fix_cortex_a8)
99059e56
RM		 6903 for (i = 0; i < num_a8_fixes; i++)
6904 {
48229727 6905 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6906 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6907
6908 if (stub_sec == NULL)
7f991970 6909 return FALSE;
48229727 6910
99059e56
RM		 6911 stub_sec->size
6912 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6913 NULL);
6914 }
48229727
JB		 6915
6916
906e58ca
NC		 6917 /* Ask the linker to do its stuff. */
6918 (*htab->layout_sections_again) ();
4ba2ef8f 6919 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6920 }
6921
48229727
JB		 6922 /* Add stubs for Cortex-A8 erratum fixes now. */
6923 if (htab->fix_cortex_a8)
6924 {
6925 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6926 {
6927 struct elf32_arm_stub_hash_entry *stub_entry;
6928 char *stub_name = a8_fixes[i].stub_name;
6929 asection *section = a8_fixes[i].section;
6930 unsigned int section_id = a8_fixes[i].section->id;
6931 asection *link_sec = htab->stub_group[section_id].link_sec;
6932 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6933 const insn_sequence *template_sequence;
6934 int template_size, size = 0;
6935
6936 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6937 TRUE, FALSE);
6938 if (stub_entry == NULL)
6939 {
871b3ab2 6940 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6941 section->owner, stub_name);
99059e56
RM		 6942 return FALSE;
6943 }
6944
6945 stub_entry->stub_sec = stub_sec;
0955507f 6946 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6947 stub_entry->id_sec = link_sec;
6948 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6949 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6950 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6951 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6952 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6953 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6954
99059e56
RM		 6955 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6956 &template_sequence,
6957 &template_size);
48229727 6958
99059e56
RM		 6959 stub_entry->stub_size = size;
6960 stub_entry->stub_template = template_sequence;
6961 stub_entry->stub_template_size = template_size;
6962 }
48229727
JB		 6963
6964 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6965 elf32_arm_write_section(). */
48229727
JB		 6966 htab->a8_erratum_fixes = a8_fixes;
6967 htab->num_a8_erratum_fixes = num_a8_fixes;
6968 }
6969 else
6970 {
6971 htab->a8_erratum_fixes = NULL;
6972 htab->num_a8_erratum_fixes = 0;
6973 }
0955507f 6974 return ret;
5e681ec4
PB		 6975}
6976
906e58ca
NC		 6977/* Build all the stubs associated with the current output file. The
6978 stubs are kept in a hash table attached to the main linker hash
6979 table. We also set up the .plt entries for statically linked PIC
6980 functions here. This function is called via arm_elf_finish in the
6981 linker. */
252b5132 6982
906e58ca
NC		 6983bfd_boolean
6984elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6985{
906e58ca
NC		 6986 asection *stub_sec;
6987 struct bfd_hash_table *table;
0955507f 6988 enum elf32_arm_stub_type stub_type;
906e58ca 6989 struct elf32_arm_link_hash_table *htab;
252b5132 6990
906e58ca 6991 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6992 if (htab == NULL)
6993 return FALSE;
252b5132 6994
906e58ca
NC		 6995 for (stub_sec = htab->stub_bfd->sections;
6996 stub_sec != NULL;
6997 stub_sec = stub_sec->next)
252b5132 6998 {
906e58ca
NC		 6999 bfd_size_type size;
7000
8029a119 7001 /* Ignore non-stub sections. */
906e58ca
NC		 7002 if (!strstr (stub_sec->name, STUB_SUFFIX))
7003 continue;
7004
d7c5bd02 7005 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 7006 must at least be done for stub section requiring padding and for SG
7007 veneers to ensure that a non secure code branching to a removed SG
7008 veneer causes an error. */
906e58ca 7009 size = stub_sec->size;
21d799b5 7010 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 7011 if (stub_sec->contents == NULL && size != 0)
7012 return FALSE;
0955507f 7013
906e58ca 7014 stub_sec->size = 0;
252b5132
RH		 7015 }
7016
0955507f
TP		 7017 /* Add new SG veneers after those already in the input import library. */
7018 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7019 {
7020 bfd_vma *start_offset_p;
7021 asection **stub_sec_p;
7022
7023 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
7024 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
7025 if (start_offset_p == NULL)
7026 continue;
7027
7028 BFD_ASSERT (stub_sec_p != NULL);
7029 if (*stub_sec_p != NULL)
7030 (*stub_sec_p)->size = *start_offset_p;
7031 }
7032
906e58ca
NC		 7033 /* Build the stubs as directed by the stub hash table. */
7034 table = &htab->stub_hash_table;
7035 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 7036 if (htab->fix_cortex_a8)
7037 {
7038 /* Place the cortex a8 stubs last. */
7039 htab->fix_cortex_a8 = -1;
7040 bfd_hash_traverse (table, arm_build_one_stub, info);
7041 }
252b5132 7042
906e58ca 7043 return TRUE;
252b5132
RH		 7044}
7045
9b485d32
NC		 7046/* Locate the Thumb encoded calling stub for NAME. */
7047
252b5132 7048static struct elf_link_hash_entry *
57e8b36a
NC		 7049find_thumb_glue (struct bfd_link_info *link_info,
7050 const char *name,
f2a9dd69 7051 char **error_message)
252b5132
RH		 7052{
7053 char *tmp_name;
7054 struct elf_link_hash_entry *hash;
7055 struct elf32_arm_link_hash_table *hash_table;
7056
7057 /* We need a pointer to the armelf specific hash table. */
7058 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7059 if (hash_table == NULL)
7060 return NULL;
252b5132 7061
21d799b5 7062 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7063 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7064
7065 BFD_ASSERT (tmp_name);
7066
7067 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7068
7069 hash = elf_link_hash_lookup
b34976b6 7070 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7071
b1657152 7072 if (hash == NULL
90b6238f
AM		 7073 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7074 "Thumb", tmp_name, name) == -1)
b1657152 7075 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7076
7077 free (tmp_name);
7078
7079 return hash;
7080}
7081
9b485d32
NC		 7082/* Locate the ARM encoded calling stub for NAME. */
7083
252b5132 7084static struct elf_link_hash_entry *
57e8b36a
NC		 7085find_arm_glue (struct bfd_link_info *link_info,
7086 const char *name,
f2a9dd69 7087 char **error_message)
252b5132
RH		 7088{
7089 char *tmp_name;
7090 struct elf_link_hash_entry *myh;
7091 struct elf32_arm_link_hash_table *hash_table;
7092
7093 /* We need a pointer to the elfarm specific hash table. */
7094 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7095 if (hash_table == NULL)
7096 return NULL;
252b5132 7097
21d799b5 7098 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7099 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7100 BFD_ASSERT (tmp_name);
7101
7102 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7103
7104 myh = elf_link_hash_lookup
b34976b6 7105 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7106
b1657152 7107 if (myh == NULL
90b6238f
AM		 7108 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7109 "ARM", tmp_name, name) == -1)
b1657152 7110 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7111
7112 free (tmp_name);
7113
7114 return myh;
7115}
7116
8f6277f5 7117/* ARM->Thumb glue (static images):
252b5132
RH		 7118
7119 .arm
7120 __func_from_arm:
7121 ldr r12, __func_addr
7122 bx r12
7123 __func_addr:
906e58ca 7124 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 7125
26079076
PB		 7126 (v5t static images)
7127 .arm
7128 __func_from_arm:
7129 ldr pc, __func_addr
7130 __func_addr:
906e58ca 7131 .word func @ behave as if you saw a ARM_32 reloc.
26079076 7132
8f6277f5
PB		 7133 (relocatable images)
7134 .arm
7135 __func_from_arm:
7136 ldr r12, __func_offset
7137 add r12, r12, pc
7138 bx r12
7139 __func_offset:
8029a119 7140 .word func - . */
8f6277f5
PB		 7141
7142#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 7143static const insn32 a2t1_ldr_insn = 0xe59fc000;
7144static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7145static const insn32 a2t3_func_addr_insn = 0x00000001;
7146
26079076
PB		 7147#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7148static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7149static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7150
8f6277f5
PB		 7151#define ARM2THUMB_PIC_GLUE_SIZE 16
7152static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7153static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7154static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7155
07d6d2b8 7156/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 7157
07d6d2b8
AM		 7158 .thumb .thumb
7159 .align 2 .align 2
7160 __func_from_thumb: __func_from_thumb:
7161 bx pc push {r6, lr}
7162 nop ldr r6, __func_addr
7163 .arm mov lr, pc
7164 b func bx r6
99059e56
RM		 7165 .arm
7166 ;; back_to_thumb
7167 ldmia r13! {r6, lr}
7168 bx lr
7169 __func_addr:
07d6d2b8 7170 .word func */
252b5132
RH		 7171
7172#define THUMB2ARM_GLUE_SIZE 8
7173static const insn16 t2a1_bx_pc_insn = 0x4778;
7174static const insn16 t2a2_noop_insn = 0x46c0;
7175static const insn32 t2a3_b_insn = 0xea000000;
7176
c7b8f16e 7177#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 7178#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7179#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 7180
845b51d6
PB		 7181#define ARM_BX_VENEER_SIZE 12
7182static const insn32 armbx1_tst_insn = 0xe3100001;
7183static const insn32 armbx2_moveq_insn = 0x01a0f000;
7184static const insn32 armbx3_bx_insn = 0xe12fff10;
7185
7e392df6 7186#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 7187static void
7188arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 7189{
7190 asection * s;
8029a119 7191 bfd_byte * contents;
252b5132 7192
8029a119 7193 if (size == 0)
3e6b1042
DJ		 7194 {
7195 /* Do not include empty glue sections in the output. */
7196 if (abfd != NULL)
7197 {
3d4d4302 7198 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 7199 if (s != NULL)
7200 s->flags |= SEC_EXCLUDE;
7201 }
7202 return;
7203 }
252b5132 7204
8029a119 7205 BFD_ASSERT (abfd != NULL);
252b5132 7206
3d4d4302 7207 s = bfd_get_linker_section (abfd, name);
8029a119 7208 BFD_ASSERT (s != NULL);
252b5132 7209
b0f4fbf8 7210 contents = (bfd_byte *) bfd_zalloc (abfd, size);
252b5132 7211
8029a119
NC		 7212 BFD_ASSERT (s->size == size);
7213 s->contents = contents;
7214}
906e58ca 7215
8029a119
NC		 7216bfd_boolean
7217bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7218{
7219 struct elf32_arm_link_hash_table * globals;
906e58ca 7220
8029a119
NC		 7221 globals = elf32_arm_hash_table (info);
7222 BFD_ASSERT (globals != NULL);
906e58ca 7223
8029a119
NC		 7224 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7225 globals->arm_glue_size,
7226 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 7227
8029a119
NC		 7228 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7229 globals->thumb_glue_size,
7230 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 7231
8029a119
NC		 7232 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7233 globals->vfp11_erratum_glue_size,
7234 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 7235
a504d23a
LA		 7236 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7237 globals->stm32l4xx_erratum_glue_size,
7238 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7239
8029a119
NC		 7240 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7241 globals->bx_glue_size,
845b51d6
PB		 7242 ARM_BX_GLUE_SECTION_NAME);
7243
b34976b6 7244 return TRUE;
252b5132
RH		 7245}
7246
a4fd1a8e 7247/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7248 returns the symbol identifying the stub. */
7249
a4fd1a8e 7250static struct elf_link_hash_entry *
57e8b36a
NC		 7251record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7252 struct elf_link_hash_entry * h)
252b5132
RH		 7253{
7254 const char * name = h->root.root.string;
63b0f745 7255 asection * s;
252b5132
RH		 7256 char * tmp_name;
7257 struct elf_link_hash_entry * myh;
14a793b2 7258 struct bfd_link_hash_entry * bh;
252b5132 7259 struct elf32_arm_link_hash_table * globals;
dc810e39 7260 bfd_vma val;
2f475487 7261 bfd_size_type size;
252b5132
RH		 7262
7263 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7264 BFD_ASSERT (globals != NULL);
7265 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7266
3d4d4302 7267 s = bfd_get_linker_section
252b5132
RH		 7268 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7269
252b5132
RH		 7270 BFD_ASSERT (s != NULL);
7271
21d799b5 7272 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7273 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7274 BFD_ASSERT (tmp_name);
7275
7276 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7277
7278 myh = elf_link_hash_lookup
b34976b6 7279 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7280
7281 if (myh != NULL)
7282 {
9b485d32 7283 /* We've already seen this guy. */
252b5132 7284 free (tmp_name);
a4fd1a8e 7285 return myh;
252b5132
RH		 7286 }
7287
57e8b36a
NC		 7288 /* The only trick here is using hash_table->arm_glue_size as the value.
7289 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7290 putting it. The +1 on the value marks that the stub has not been
7291 output yet - not that it is a Thumb function. */
14a793b2 7292 bh = NULL;
dc810e39
AM		 7293 val = globals->arm_glue_size + 1;
7294 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7295 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7296 NULL, TRUE, FALSE, &bh);
252b5132 7297
b7693d02
DJ		 7298 myh = (struct elf_link_hash_entry *) bh;
7299 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7300 myh->forced_local = 1;
7301
252b5132
RH		 7302 free (tmp_name);
7303
0e1862bb
L		 7304 if (bfd_link_pic (link_info)
7305 || globals->root.is_relocatable_executable
27e55c4d 7306 || globals->pic_veneer)
2f475487 7307 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7308 else if (globals->use_blx)
7309 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7310 else
2f475487
AM		 7311 size = ARM2THUMB_STATIC_GLUE_SIZE;
7312
7313 s->size += size;
7314 globals->arm_glue_size += size;
252b5132 7315
a4fd1a8e 7316 return myh;
252b5132
RH		 7317}
7318
845b51d6
PB		 7319/* Allocate space for ARMv4 BX veneers. */
7320
7321static void
7322record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7323{
7324 asection * s;
7325 struct elf32_arm_link_hash_table *globals;
7326 char *tmp_name;
7327 struct elf_link_hash_entry *myh;
7328 struct bfd_link_hash_entry *bh;
7329 bfd_vma val;
7330
7331 /* BX PC does not need a veneer. */
7332 if (reg == 15)
7333 return;
7334
7335 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7336 BFD_ASSERT (globals != NULL);
7337 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7338
7339 /* Check if this veneer has already been allocated. */
7340 if (globals->bx_glue_offset[reg])
7341 return;
7342
3d4d4302 7343 s = bfd_get_linker_section
845b51d6
PB		 7344 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7345
7346 BFD_ASSERT (s != NULL);
7347
7348 /* Add symbol for veneer. */
21d799b5
NC		 7349 tmp_name = (char *)
7350 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
845b51d6 7351 BFD_ASSERT (tmp_name);
906e58ca 7352
845b51d6 7353 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7354
845b51d6
PB		 7355 myh = elf_link_hash_lookup
7356 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7357
845b51d6 7358 BFD_ASSERT (myh == NULL);
906e58ca 7359
845b51d6
PB		 7360 bh = NULL;
7361 val = globals->bx_glue_size;
7362 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7363 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7364 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7365
7366 myh = (struct elf_link_hash_entry *) bh;
7367 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7368 myh->forced_local = 1;
7369
7370 s->size += ARM_BX_VENEER_SIZE;
7371 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7372 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7373}
7374
7375
c7b8f16e
JB		 7376/* Add an entry to the code/data map for section SEC. */
7377
7378static void
7379elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7380{
7381 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7382 unsigned int newidx;
906e58ca 7383
c7b8f16e
JB		 7384 if (sec_data->map == NULL)
7385 {
21d799b5 7386 sec_data->map = (elf32_arm_section_map *)
99059e56 7387 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7388 sec_data->mapcount = 0;
7389 sec_data->mapsize = 1;
7390 }
906e58ca 7391
c7b8f16e 7392 newidx = sec_data->mapcount++;
906e58ca 7393
c7b8f16e
JB		 7394 if (sec_data->mapcount > sec_data->mapsize)
7395 {
7396 sec_data->mapsize *= 2;
21d799b5 7397 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7398 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7399 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7400 }
7401
7402 if (sec_data->map)
7403 {
7404 sec_data->map[newidx].vma = vma;
7405 sec_data->map[newidx].type = type;
c7b8f16e 7406 }
c7b8f16e
JB		 7407}
7408
7409
7410/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7411 veneers are handled for now. */
7412
7413static bfd_vma
7414record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7415 elf32_vfp11_erratum_list *branch,
7416 bfd *branch_bfd,
7417 asection *branch_sec,
7418 unsigned int offset)
c7b8f16e
JB		 7419{
7420 asection *s;
7421 struct elf32_arm_link_hash_table *hash_table;
7422 char *tmp_name;
7423 struct elf_link_hash_entry *myh;
7424 struct bfd_link_hash_entry *bh;
7425 bfd_vma val;
7426 struct _arm_elf_section_data *sec_data;
c7b8f16e 7427 elf32_vfp11_erratum_list *newerr;
906e58ca 7428
c7b8f16e 7429 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7430 BFD_ASSERT (hash_table != NULL);
7431 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7432
3d4d4302 7433 s = bfd_get_linker_section
c7b8f16e 7434 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7435
c7b8f16e 7436 sec_data = elf32_arm_section_data (s);
906e58ca 7437
c7b8f16e 7438 BFD_ASSERT (s != NULL);
906e58ca 7439
21d799b5 7440 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7441 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e 7442 BFD_ASSERT (tmp_name);
906e58ca 7443
c7b8f16e
JB		 7444 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7445 hash_table->num_vfp11_fixes);
906e58ca 7446
c7b8f16e
JB		 7447 myh = elf_link_hash_lookup
7448 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7449
c7b8f16e 7450 BFD_ASSERT (myh == NULL);
906e58ca 7451
c7b8f16e
JB		 7452 bh = NULL;
7453 val = hash_table->vfp11_erratum_glue_size;
7454 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7455 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7456 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7457
7458 myh = (struct elf_link_hash_entry *) bh;
7459 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7460 myh->forced_local = 1;
7461
7462 /* Link veneer back to calling location. */
c7e2358a 7463 sec_data->erratumcount += 1;
21d799b5
NC		 7464 newerr = (elf32_vfp11_erratum_list *)
7465 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7466
c7b8f16e
JB		 7467 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7468 newerr->vma = -1;
7469 newerr->u.v.branch = branch;
7470 newerr->u.v.id = hash_table->num_vfp11_fixes;
7471 branch->u.b.veneer = newerr;
7472
7473 newerr->next = sec_data->erratumlist;
7474 sec_data->erratumlist = newerr;
7475
7476 /* A symbol for the return from the veneer. */
7477 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7478 hash_table->num_vfp11_fixes);
7479
7480 myh = elf_link_hash_lookup
7481 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7482
c7b8f16e
JB		 7483 if (myh != NULL)
7484 abort ();
7485
7486 bh = NULL;
7487 val = offset + 4;
7488 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7489 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7490
c7b8f16e
JB		 7491 myh = (struct elf_link_hash_entry *) bh;
7492 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7493 myh->forced_local = 1;
7494
7495 free (tmp_name);
906e58ca 7496
c7b8f16e
JB		 7497 /* Generate a mapping symbol for the veneer section, and explicitly add an
7498 entry for that symbol to the code/data map for the section. */
7499 if (hash_table->vfp11_erratum_glue_size == 0)
7500 {
7501 bh = NULL;
7502 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7503 ever requires this erratum fix. */
c7b8f16e
JB		 7504 _bfd_generic_link_add_one_symbol (link_info,
7505 hash_table->bfd_of_glue_owner, "$a",
7506 BSF_LOCAL, s, 0, NULL,
99059e56 7507 TRUE, FALSE, &bh);
c7b8f16e
JB		 7508
7509 myh = (struct elf_link_hash_entry *) bh;
7510 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7511 myh->forced_local = 1;
906e58ca 7512
c7b8f16e 7513 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7514 BFDs. We must make a note of this generated mapping symbol
7515 ourselves so that code byteswapping works properly in
7516 elf32_arm_write_section. */
c7b8f16e
JB		 7517 elf32_arm_section_map_add (s, 'a', 0);
7518 }
906e58ca 7519
c7b8f16e
JB		 7520 s->size += VFP11_ERRATUM_VENEER_SIZE;
7521 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7522 hash_table->num_vfp11_fixes++;
906e58ca 7523
c7b8f16e
JB		 7524 /* The offset of the veneer. */
7525 return val;
7526}
7527
a504d23a
LA		 7528/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7529 veneers need to be handled because used only in Cortex-M. */
7530
7531static bfd_vma
7532record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7533 elf32_stm32l4xx_erratum_list *branch,
7534 bfd *branch_bfd,
7535 asection *branch_sec,
7536 unsigned int offset,
7537 bfd_size_type veneer_size)
7538{
7539 asection *s;
7540 struct elf32_arm_link_hash_table *hash_table;
7541 char *tmp_name;
7542 struct elf_link_hash_entry *myh;
7543 struct bfd_link_hash_entry *bh;
7544 bfd_vma val;
7545 struct _arm_elf_section_data *sec_data;
7546 elf32_stm32l4xx_erratum_list *newerr;
7547
7548 hash_table = elf32_arm_hash_table (link_info);
7549 BFD_ASSERT (hash_table != NULL);
7550 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7551
7552 s = bfd_get_linker_section
7553 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7554
7555 BFD_ASSERT (s != NULL);
7556
7557 sec_data = elf32_arm_section_data (s);
7558
7559 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7560 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
a504d23a
LA		 7561 BFD_ASSERT (tmp_name);
7562
7563 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7564 hash_table->num_stm32l4xx_fixes);
7565
7566 myh = elf_link_hash_lookup
7567 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7568
7569 BFD_ASSERT (myh == NULL);
7570
7571 bh = NULL;
7572 val = hash_table->stm32l4xx_erratum_glue_size;
7573 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7574 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7575 NULL, TRUE, FALSE, &bh);
7576
7577 myh = (struct elf_link_hash_entry *) bh;
7578 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7579 myh->forced_local = 1;
7580
7581 /* Link veneer back to calling location. */
7582 sec_data->stm32l4xx_erratumcount += 1;
7583 newerr = (elf32_stm32l4xx_erratum_list *)
7584 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7585
7586 newerr->type = STM32L4XX_ERRATUM_VENEER;
7587 newerr->vma = -1;
7588 newerr->u.v.branch = branch;
7589 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7590 branch->u.b.veneer = newerr;
7591
7592 newerr->next = sec_data->stm32l4xx_erratumlist;
7593 sec_data->stm32l4xx_erratumlist = newerr;
7594
7595 /* A symbol for the return from the veneer. */
7596 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7597 hash_table->num_stm32l4xx_fixes);
7598
7599 myh = elf_link_hash_lookup
7600 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7601
7602 if (myh != NULL)
7603 abort ();
7604
7605 bh = NULL;
7606 val = offset + 4;
7607 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7608 branch_sec, val, NULL, TRUE, FALSE, &bh);
7609
7610 myh = (struct elf_link_hash_entry *) bh;
7611 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7612 myh->forced_local = 1;
7613
7614 free (tmp_name);
7615
7616 /* Generate a mapping symbol for the veneer section, and explicitly add an
7617 entry for that symbol to the code/data map for the section. */
7618 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7619 {
7620 bh = NULL;
7621 /* Creates a THUMB symbol since there is no other choice. */
7622 _bfd_generic_link_add_one_symbol (link_info,
7623 hash_table->bfd_of_glue_owner, "$t",
7624 BSF_LOCAL, s, 0, NULL,
7625 TRUE, FALSE, &bh);
7626
7627 myh = (struct elf_link_hash_entry *) bh;
7628 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7629 myh->forced_local = 1;
7630
7631 /* The elf32_arm_init_maps function only cares about symbols from input
7632 BFDs. We must make a note of this generated mapping symbol
7633 ourselves so that code byteswapping works properly in
7634 elf32_arm_write_section. */
7635 elf32_arm_section_map_add (s, 't', 0);
7636 }
7637
7638 s->size += veneer_size;
7639 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7640 hash_table->num_stm32l4xx_fixes++;
7641
7642 /* The offset of the veneer. */
7643 return val;
7644}
7645
8029a119 7646#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7647 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7648 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7649
7650/* Create a fake section for use by the ARM backend of the linker. */
7651
7652static bfd_boolean
7653arm_make_glue_section (bfd * abfd, const char * name)
7654{
7655 asection * sec;
7656
3d4d4302 7657 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7658 if (sec != NULL)
7659 /* Already made. */
7660 return TRUE;
7661
3d4d4302 7662 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7663
7664 if (sec == NULL
fd361982 7665 || !bfd_set_section_alignment (sec, 2))
8029a119
NC		 7666 return FALSE;
7667
7668 /* Set the gc mark to prevent the section from being removed by garbage
7669 collection, despite the fact that no relocs refer to this section. */
7670 sec->gc_mark = 1;
7671
7672 return TRUE;
7673}
7674
1db37fe6
YG		 7675/* Set size of .plt entries. This function is called from the
7676 linker scripts in ld/emultempl/{armelf}.em. */
7677
7678void
7679bfd_elf32_arm_use_long_plt (void)
7680{
7681 elf32_arm_use_long_plt_entry = TRUE;
7682}
7683
8afb0e02
NC		 7684/* Add the glue sections to ABFD. This function is called from the
7685 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7686
b34976b6 7687bfd_boolean
57e8b36a
NC		 7688bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7689 struct bfd_link_info *info)
252b5132 7690{
a504d23a
LA		 7691 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7692 bfd_boolean dostm32l4xx = globals
7693 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7694 bfd_boolean addglue;
7695
8afb0e02
NC		 7696 /* If we are only performing a partial
7697 link do not bother adding the glue. */
0e1862bb 7698 if (bfd_link_relocatable (info))
b34976b6 7699 return TRUE;
252b5132 7700
a504d23a 7701 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7702 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7703 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7704 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7705
7706 if (!dostm32l4xx)
7707 return addglue;
7708
7709 return addglue
7710 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7711}
7712
daa4adae
TP		 7713/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7714 ensures they are not marked for deletion by
7715 strip_excluded_output_sections () when veneers are going to be created
7716 later. Not doing so would trigger assert on empty section size in
7717 lang_size_sections_1 (). */
7718
7719void
7720bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7721{
7722 enum elf32_arm_stub_type stub_type;
7723
7724 /* If we are only performing a partial
7725 link do not bother adding the glue. */
7726 if (bfd_link_relocatable (info))
7727 return;
7728
7729 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7730 {
7731 asection *out_sec;
7732 const char *out_sec_name;
7733
7734 if (!arm_dedicated_stub_output_section_required (stub_type))
7735 continue;
7736
7737 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7738 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7739 if (out_sec != NULL)
7740 out_sec->flags |= SEC_KEEP;
7741 }
7742}
7743
8afb0e02
NC		 7744/* Select a BFD to be used to hold the sections used by the glue code.
7745 This function is called from the linker scripts in ld/emultempl/
8029a119 7746 {armelf/pe}.em. */
8afb0e02 7747
b34976b6 7748bfd_boolean
57e8b36a 7749bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7750{
7751 struct elf32_arm_link_hash_table *globals;
7752
7753 /* If we are only performing a partial link
7754 do not bother getting a bfd to hold the glue. */
0e1862bb 7755 if (bfd_link_relocatable (info))
b34976b6 7756 return TRUE;
8afb0e02 7757
b7693d02
DJ		 7758 /* Make sure we don't attach the glue sections to a dynamic object. */
7759 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7760
8afb0e02 7761 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7762 BFD_ASSERT (globals != NULL);
7763
7764 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7765 return TRUE;
8afb0e02 7766
252b5132
RH		 7767 /* Save the bfd for later use. */
7768 globals->bfd_of_glue_owner = abfd;
cedb70c5 7769
b34976b6 7770 return TRUE;
252b5132
RH		 7771}
7772
906e58ca
NC		 7773static void
7774check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7775{
2de70689
MGD		 7776 int cpu_arch;
7777
b38cadfb 7778 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7779 Tag_CPU_arch);
7780
7781 if (globals->fix_arm1176)
7782 {
7783 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7784 globals->use_blx = 1;
7785 }
7786 else
7787 {
7788 if (cpu_arch > TAG_CPU_ARCH_V4T)
7789 globals->use_blx = 1;
7790 }
39b41c9c
PB		 7791}
7792
b34976b6 7793bfd_boolean
57e8b36a 7794bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7795 struct bfd_link_info *link_info)
252b5132
RH		 7796{
7797 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7798 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7799 Elf_Internal_Rela *irel, *irelend;
7800 bfd_byte *contents = NULL;
252b5132
RH		 7801
7802 asection *sec;
7803 struct elf32_arm_link_hash_table *globals;
7804
7805 /* If we are only performing a partial link do not bother
7806 to construct any glue. */
0e1862bb 7807 if (bfd_link_relocatable (link_info))
b34976b6 7808 return TRUE;
252b5132 7809
39ce1a6a
NC		 7810 /* Here we have a bfd that is to be included on the link. We have a
7811 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7812 globals = elf32_arm_hash_table (link_info);
252b5132 7813 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7814
7815 check_use_blx (globals);
252b5132 7816
d504ffc8 7817 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7818 {
90b6238f 7819 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7820 abfd);
e489d0ae
PB		 7821 return FALSE;
7822 }
f21f3fe0 7823
39ce1a6a
NC		 7824 /* PR 5398: If we have not decided to include any loadable sections in
7825 the output then we will not have a glue owner bfd. This is OK, it
7826 just means that there is nothing else for us to do here. */
7827 if (globals->bfd_of_glue_owner == NULL)
7828 return TRUE;
7829
252b5132
RH		 7830 /* Rummage around all the relocs and map the glue vectors. */
7831 sec = abfd->sections;
7832
7833 if (sec == NULL)
b34976b6 7834 return TRUE;
252b5132
RH		 7835
7836 for (; sec != NULL; sec = sec->next)
7837 {
7838 if (sec->reloc_count == 0)
7839 continue;
7840
2f475487
AM		 7841 if ((sec->flags & SEC_EXCLUDE) != 0)
7842 continue;
7843
0ffa91dd 7844 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7845
9b485d32 7846 /* Load the relocs. */
6cdc0ccc 7847 internal_relocs
906e58ca 7848 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7849
6cdc0ccc
AM		 7850 if (internal_relocs == NULL)
7851 goto error_return;
252b5132 7852
6cdc0ccc
AM		 7853 irelend = internal_relocs + sec->reloc_count;
7854 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7855 {
7856 long r_type;
7857 unsigned long r_index;
252b5132
RH		 7858
7859 struct elf_link_hash_entry *h;
7860
7861 r_type = ELF32_R_TYPE (irel->r_info);
7862 r_index = ELF32_R_SYM (irel->r_info);
7863
9b485d32 7864 /* These are the only relocation types we care about. */
ba96a88f 7865 if ( r_type != R_ARM_PC24
845b51d6 7866 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7867 continue;
7868
7869 /* Get the section contents if we haven't done so already. */
7870 if (contents == NULL)
7871 {
7872 /* Get cached copy if it exists. */
7873 if (elf_section_data (sec)->this_hdr.contents != NULL)
7874 contents = elf_section_data (sec)->this_hdr.contents;
7875 else
7876 {
7877 /* Go get them off disk. */
57e8b36a 7878 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7879 goto error_return;
7880 }
7881 }
7882
845b51d6
PB		 7883 if (r_type == R_ARM_V4BX)
7884 {
7885 int reg;
7886
7887 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7888 record_arm_bx_glue (link_info, reg);
7889 continue;
7890 }
7891
a7c10850 7892 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7893 h = NULL;
7894
9b485d32 7895 /* We don't care about local symbols. */
252b5132
RH		 7896 if (r_index < symtab_hdr->sh_info)
7897 continue;
7898
9b485d32 7899 /* This is an external symbol. */
252b5132
RH		 7900 r_index -= symtab_hdr->sh_info;
7901 h = (struct elf_link_hash_entry *)
7902 elf_sym_hashes (abfd)[r_index];
7903
7904 /* If the relocation is against a static symbol it must be within
7905 the current section and so cannot be a cross ARM/Thumb relocation. */
7906 if (h == NULL)
7907 continue;
7908
d504ffc8
DJ		 7909 /* If the call will go through a PLT entry then we do not need
7910 glue. */
362d30a1 7911 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7912 continue;
7913
252b5132
RH		 7914 switch (r_type)
7915 {
7916 case R_ARM_PC24:
7917 /* This one is a call from arm code. We need to look up
99059e56
RM		 7918 the target of the call. If it is a thumb target, we
7919 insert glue. */
39d911fc
TP		 7920 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7921 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7922 record_arm_to_thumb_glue (link_info, h);
7923 break;
7924
252b5132 7925 default:
c6596c5e 7926 abort ();
252b5132
RH		 7927 }
7928 }
6cdc0ccc 7929
c9594989 7930 if (elf_section_data (sec)->this_hdr.contents != contents)
6cdc0ccc
AM		 7931 free (contents);
7932 contents = NULL;
7933
c9594989 7934 if (elf_section_data (sec)->relocs != internal_relocs)
6cdc0ccc
AM		 7935 free (internal_relocs);
7936 internal_relocs = NULL;
252b5132
RH		 7937 }
7938
b34976b6 7939 return TRUE;
9a5aca8c 7940
dc1e8a47 7941 error_return:
c9594989 7942 if (elf_section_data (sec)->this_hdr.contents != contents)
6cdc0ccc 7943 free (contents);
c9594989 7944 if (elf_section_data (sec)->relocs != internal_relocs)
6cdc0ccc 7945 free (internal_relocs);
9a5aca8c 7946
b34976b6 7947 return FALSE;
252b5132 7948}
7e392df6 7949#endif
252b5132 7950
eb043451 7951
c7b8f16e
JB		 7952/* Initialise maps of ARM/Thumb/data for input BFDs. */
7953
7954void
7955bfd_elf32_arm_init_maps (bfd *abfd)
7956{
7957 Elf_Internal_Sym *isymbuf;
7958 Elf_Internal_Shdr *hdr;
7959 unsigned int i, localsyms;
7960
af1f4419
NC		 7961 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7962 if (! is_arm_elf (abfd))
7963 return;
7964
c7b8f16e
JB		 7965 if ((abfd->flags & DYNAMIC) != 0)
7966 return;
7967
0ffa91dd 7968 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7969 localsyms = hdr->sh_info;
7970
7971 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7972 should contain the number of local symbols, which should come before any
7973 global symbols. Mapping symbols are always local. */
7974 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7975 NULL);
7976
7977 /* No internal symbols read? Skip this BFD. */
7978 if (isymbuf == NULL)
7979 return;
7980
7981 for (i = 0; i < localsyms; i++)
7982 {
7983 Elf_Internal_Sym *isym = &isymbuf[i];
7984 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7985 const char *name;
906e58ca 7986
c7b8f16e 7987 if (sec != NULL
99059e56
RM		 7988 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7989 {
7990 name = bfd_elf_string_from_elf_section (abfd,
7991 hdr->sh_link, isym->st_name);
906e58ca 7992
99059e56 7993 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7994 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7995 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7996 }
c7b8f16e
JB		 7997 }
7998}
7999
8000
48229727
JB		 8001/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8002 say what they wanted. */
8003
8004void
8005bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
8006{
8007 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8008 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8009
4dfe6ac6
NC		 8010 if (globals == NULL)
8011 return;
8012
48229727
JB		 8013 if (globals->fix_cortex_a8 == -1)
8014 {
8015 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8016 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
8017 && (out_attr[Tag_CPU_arch_profile].i == 'A'
8018 || out_attr[Tag_CPU_arch_profile].i == 0))
8019 globals->fix_cortex_a8 = 1;
8020 else
8021 globals->fix_cortex_a8 = 0;
8022 }
8023}
8024
8025
c7b8f16e
JB		 8026void
8027bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
8028{
8029 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 8030 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 8031
4dfe6ac6
NC		 8032 if (globals == NULL)
8033 return;
c7b8f16e
JB		 8034 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8035 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
8036 {
8037 switch (globals->vfp11_fix)
99059e56
RM		 8038 {
8039 case BFD_ARM_VFP11_FIX_DEFAULT:
8040 case BFD_ARM_VFP11_FIX_NONE:
8041 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8042 break;
8043
8044 default:
8045 /* Give a warning, but do as the user requests anyway. */
871b3ab2 8046 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 8047 "workaround is not necessary for target architecture"), obfd);
8048 }
c7b8f16e
JB		 8049 }
8050 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
8051 /* For earlier architectures, we might need the workaround, but do not
8052 enable it by default. If users is running with broken hardware, they
8053 must enable the erratum fix explicitly. */
8054 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8055}
8056
a504d23a
LA		 8057void
8058bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8059{
8060 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8061 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8062
8063 if (globals == NULL)
8064 return;
8065
8066 /* We assume only Cortex-M4 may require the fix. */
8067 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8068 || out_attr[Tag_CPU_arch_profile].i != 'M')
8069 {
8070 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8071 /* Give a warning, but do as the user requests anyway. */
4eca0228 8072 _bfd_error_handler
871b3ab2 8073 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 8074 "workaround is not necessary for target architecture"), obfd);
8075 }
8076}
c7b8f16e 8077
906e58ca
NC		 8078enum bfd_arm_vfp11_pipe
8079{
c7b8f16e
JB		 8080 VFP11_FMAC,
8081 VFP11_LS,
8082 VFP11_DS,
8083 VFP11_BAD
8084};
8085
8086/* Return a VFP register number. This is encoded as RX:X for single-precision
8087 registers, or X:RX for double-precision registers, where RX is the group of
8088 four bits in the instruction encoding and X is the single extension bit.
8089 RX and X fields are specified using their lowest (starting) bit. The return
8090 value is:
8091
8092 0...31: single-precision registers s0...s31
8093 32...63: double-precision registers d0...d31.
906e58ca 8094
c7b8f16e
JB		 8095 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8096 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 8097
c7b8f16e
JB		 8098static unsigned int
8099bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 8100 unsigned int x)
c7b8f16e
JB		 8101{
8102 if (is_double)
8103 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8104 else
8105 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8106}
8107
8108/* Set bits in *WMASK according to a register number REG as encoded by
8109 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8110
8111static void
8112bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8113{
8114 if (reg < 32)
8115 *wmask |= 1 << reg;
8116 else if (reg < 48)
8117 *wmask |= 3 << ((reg - 32) * 2);
8118}
8119
8120/* Return TRUE if WMASK overwrites anything in REGS. */
8121
8122static bfd_boolean
8123bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8124{
8125 int i;
906e58ca 8126
c7b8f16e
JB		 8127 for (i = 0; i < numregs; i++)
8128 {
8129 unsigned int reg = regs[i];
8130
8131 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 8132 return TRUE;
906e58ca 8133
c7b8f16e
JB		 8134 reg -= 32;
8135
8136 if (reg >= 16)
99059e56 8137 continue;
906e58ca 8138
c7b8f16e 8139 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 8140 return TRUE;
c7b8f16e 8141 }
906e58ca 8142
c7b8f16e
JB		 8143 return FALSE;
8144}
8145
8146/* In this function, we're interested in two things: finding input registers
8147 for VFP data-processing instructions, and finding the set of registers which
8148 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8149 hold the written set, so FLDM etc. are easy to deal with (we're only
8150 interested in 32 SP registers or 16 dp registers, due to the VFP version
8151 implemented by the chip in question). DP registers are marked by setting
8152 both SP registers in the write mask). */
8153
8154static enum bfd_arm_vfp11_pipe
8155bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 8156 int *numregs)
c7b8f16e 8157{
91d6fa6a 8158 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 8159 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8160
8161 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8162 {
8163 unsigned int pqrs;
8164 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8165 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8166
8167 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 8168 | ((insn & 0x00300000) >> 19)
8169 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 8170
8171 switch (pqrs)
99059e56
RM		 8172 {
8173 case 0: /* fmac[sd]. */
8174 case 1: /* fnmac[sd]. */
8175 case 2: /* fmsc[sd]. */
8176 case 3: /* fnmsc[sd]. */
8177 vpipe = VFP11_FMAC;
8178 bfd_arm_vfp11_write_mask (destmask, fd);
8179 regs[0] = fd;
8180 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8181 regs[2] = fm;
8182 *numregs = 3;
8183 break;
8184
8185 case 4: /* fmul[sd]. */
8186 case 5: /* fnmul[sd]. */
8187 case 6: /* fadd[sd]. */
8188 case 7: /* fsub[sd]. */
8189 vpipe = VFP11_FMAC;
8190 goto vfp_binop;
8191
8192 case 8: /* fdiv[sd]. */
8193 vpipe = VFP11_DS;
8194 vfp_binop:
8195 bfd_arm_vfp11_write_mask (destmask, fd);
8196 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8197 regs[1] = fm;
8198 *numregs = 2;
8199 break;
8200
8201 case 15: /* extended opcode. */
8202 {
8203 unsigned int extn = ((insn >> 15) & 0x1e)
8204 | ((insn >> 7) & 1);
8205
8206 switch (extn)
8207 {
8208 case 0: /* fcpy[sd]. */
8209 case 1: /* fabs[sd]. */
8210 case 2: /* fneg[sd]. */
8211 case 8: /* fcmp[sd]. */
8212 case 9: /* fcmpe[sd]. */
8213 case 10: /* fcmpz[sd]. */
8214 case 11: /* fcmpez[sd]. */
8215 case 16: /* fuito[sd]. */
8216 case 17: /* fsito[sd]. */
8217 case 24: /* ftoui[sd]. */
8218 case 25: /* ftouiz[sd]. */
8219 case 26: /* ftosi[sd]. */
8220 case 27: /* ftosiz[sd]. */
8221 /* These instructions will not bounce due to underflow. */
8222 *numregs = 0;
8223 vpipe = VFP11_FMAC;
8224 break;
8225
8226 case 3: /* fsqrt[sd]. */
8227 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8228 registers to cause the erratum in previous instructions. */
8229 bfd_arm_vfp11_write_mask (destmask, fd);
8230 vpipe = VFP11_DS;
8231 break;
8232
8233 case 15: /* fcvt{ds,sd}. */
8234 {
8235 int rnum = 0;
8236
8237 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8238
8239 /* Only FCVTSD can underflow. */
99059e56
RM		 8240 if ((insn & 0x100) != 0)
8241 regs[rnum++] = fm;
c7b8f16e 8242
99059e56 8243 *numregs = rnum;
c7b8f16e 8244
99059e56
RM		 8245 vpipe = VFP11_FMAC;
8246 }
8247 break;
c7b8f16e 8248
99059e56
RM		 8249 default:
8250 return VFP11_BAD;
8251 }
8252 }
8253 break;
c7b8f16e 8254
99059e56
RM		 8255 default:
8256 return VFP11_BAD;
8257 }
c7b8f16e
JB		 8258 }
8259 /* Two-register transfer. */
8260 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8261 {
8262 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8263
c7b8f16e
JB		 8264 if ((insn & 0x100000) == 0)
8265 {
99059e56
RM		 8266 if (is_double)
8267 bfd_arm_vfp11_write_mask (destmask, fm);
8268 else
8269 {
8270 bfd_arm_vfp11_write_mask (destmask, fm);
8271 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8272 }
c7b8f16e
JB		 8273 }
8274
91d6fa6a 8275 vpipe = VFP11_LS;
c7b8f16e
JB		 8276 }
8277 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8278 {
8279 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8280 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8281
c7b8f16e 8282 switch (puw)
99059e56
RM		 8283 {
8284 case 0: /* Two-reg transfer. We should catch these above. */
8285 abort ();
906e58ca 8286
99059e56
RM		 8287 case 2: /* fldm[sdx]. */
8288 case 3:
8289 case 5:
8290 {
8291 unsigned int i, offset = insn & 0xff;
c7b8f16e 8292
99059e56
RM		 8293 if (is_double)
8294 offset >>= 1;
c7b8f16e 8295
99059e56
RM		 8296 for (i = fd; i < fd + offset; i++)
8297 bfd_arm_vfp11_write_mask (destmask, i);
8298 }
8299 break;
906e58ca 8300
99059e56
RM		 8301 case 4: /* fld[sd]. */
8302 case 6:
8303 bfd_arm_vfp11_write_mask (destmask, fd);
8304 break;
906e58ca 8305
99059e56
RM		 8306 default:
8307 return VFP11_BAD;
8308 }
c7b8f16e 8309
91d6fa6a 8310 vpipe = VFP11_LS;
c7b8f16e
JB		 8311 }
8312 /* Single-register transfer. Note L==0. */
8313 else if ((insn & 0x0f100e10) == 0x0e000a10)
8314 {
8315 unsigned int opcode = (insn >> 21) & 7;
8316 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8317
8318 switch (opcode)
99059e56
RM		 8319 {
8320 case 0: /* fmsr/fmdlr. */
8321 case 1: /* fmdhr. */
8322 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8323 destination register. I don't know if this is exactly right,
8324 but it is the conservative choice. */
8325 bfd_arm_vfp11_write_mask (destmask, fn);
8326 break;
8327
8328 case 7: /* fmxr. */
8329 break;
8330 }
c7b8f16e 8331
91d6fa6a 8332 vpipe = VFP11_LS;
c7b8f16e
JB		 8333 }
8334
91d6fa6a 8335 return vpipe;
c7b8f16e
JB		 8336}
8337
8338
8339static int elf32_arm_compare_mapping (const void * a, const void * b);
8340
8341
8342/* Look for potentially-troublesome code sequences which might trigger the
8343 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8344 (available from ARM) for details of the erratum. A short version is
8345 described in ld.texinfo. */
8346
8347bfd_boolean
8348bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8349{
8350 asection *sec;
8351 bfd_byte *contents = NULL;
8352 int state = 0;
8353 int regs[3], numregs = 0;
8354 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8355 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8356
4dfe6ac6
NC		 8357 if (globals == NULL)
8358 return FALSE;
8359
c7b8f16e
JB		 8360 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8361 The states transition as follows:
906e58ca 8362
c7b8f16e 8363 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8364 A VFP FMAC-pipeline instruction has been seen. Fill
8365 regs[0]..regs[numregs-1] with its input operands. Remember this
8366 instruction in 'first_fmac'.
c7b8f16e
JB		 8367
8368 1 -> 2
99059e56
RM		 8369 Any instruction, except for a VFP instruction which overwrites
8370 regs[*].
906e58ca 8371
c7b8f16e
JB		 8372 1 -> 3 [ -> 0 ] or
8373 2 -> 3 [ -> 0 ]
99059e56
RM		 8374 A VFP instruction has been seen which overwrites any of regs[*].
8375 We must make a veneer! Reset state to 0 before examining next
8376 instruction.
906e58ca 8377
c7b8f16e 8378 2 -> 0
99059e56
RM		 8379 If we fail to match anything in state 2, reset to state 0 and reset
8380 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8381
8382 If the VFP11 vector mode is in use, there must be at least two unrelated
8383 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8384 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8385
8386 /* If we are only performing a partial link do not bother
8387 to construct any glue. */
0e1862bb 8388 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8389 return TRUE;
8390
0ffa91dd
NC		 8391 /* Skip if this bfd does not correspond to an ELF image. */
8392 if (! is_arm_elf (abfd))
8393 return TRUE;
906e58ca 8394
c7b8f16e
JB		 8395 /* We should have chosen a fix type by the time we get here. */
8396 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8397
8398 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8399 return TRUE;
2e6030b9 8400
33a7ffc2
JM		 8401 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8402 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8403 return TRUE;
8404
c7b8f16e
JB		 8405 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8406 {
8407 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8408 struct _arm_elf_section_data *sec_data;
8409
8410 /* If we don't have executable progbits, we're not interested in this
99059e56 8411 section. Also skip if section is to be excluded. */
c7b8f16e 8412 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8413 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8414 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8415 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8416 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8417 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8418 continue;
c7b8f16e
JB		 8419
8420 sec_data = elf32_arm_section_data (sec);
906e58ca 8421
c7b8f16e 8422 if (sec_data->mapcount == 0)
99059e56 8423 continue;
906e58ca 8424
c7b8f16e
JB		 8425 if (elf_section_data (sec)->this_hdr.contents != NULL)
8426 contents = elf_section_data (sec)->this_hdr.contents;
8427 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8428 goto error_return;
8429
8430 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8431 elf32_arm_compare_mapping);
8432
8433 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8434 {
8435 unsigned int span_start = sec_data->map[span].vma;
8436 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8437 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8438 char span_type = sec_data->map[span].type;
8439
8440 /* FIXME: Only ARM mode is supported at present. We may need to
8441 support Thumb-2 mode also at some point. */
8442 if (span_type != 'a')
8443 continue;
8444
8445 for (i = span_start; i < span_end;)
8446 {
8447 unsigned int next_i = i + 4;
8448 unsigned int insn = bfd_big_endian (abfd)
13c9c485
AM		 8449 ? (((unsigned) contents[i] << 24)
8450 | (contents[i + 1] << 16)
8451 | (contents[i + 2] << 8)
8452 | contents[i + 3])
8453 : (((unsigned) contents[i + 3] << 24)
8454 | (contents[i + 2] << 16)
8455 | (contents[i + 1] << 8)
8456 | contents[i]);
99059e56
RM		 8457 unsigned int writemask = 0;
8458 enum bfd_arm_vfp11_pipe vpipe;
8459
8460 switch (state)
8461 {
8462 case 0:
8463 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8464 &numregs);
8465 /* I'm assuming the VFP11 erratum can trigger with denorm
8466 operands on either the FMAC or the DS pipeline. This might
8467 lead to slightly overenthusiastic veneer insertion. */
8468 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8469 {
8470 state = use_vector ? 1 : 2;
8471 first_fmac = i;
8472 veneer_of_insn = insn;
8473 }
8474 break;
8475
8476 case 1:
8477 {
8478 int other_regs[3], other_numregs;
8479 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8480 other_regs,
99059e56
RM		 8481 &other_numregs);
8482 if (vpipe != VFP11_BAD
8483 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8484 numregs))
99059e56
RM		 8485 state = 3;
8486 else
8487 state = 2;
8488 }
8489 break;
8490
8491 case 2:
8492 {
8493 int other_regs[3], other_numregs;
8494 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8495 other_regs,
99059e56
RM		 8496 &other_numregs);
8497 if (vpipe != VFP11_BAD
8498 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8499 numregs))
99059e56
RM		 8500 state = 3;
8501 else
8502 {
8503 state = 0;
8504 next_i = first_fmac + 4;
8505 }
8506 }
8507 break;
8508
8509 case 3:
8510 abort (); /* Should be unreachable. */
8511 }
8512
8513 if (state == 3)
8514 {
8515 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8516 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8517
8518 elf32_arm_section_data (sec)->erratumcount += 1;
8519
8520 newerr->u.b.vfp_insn = veneer_of_insn;
8521
8522 switch (span_type)
8523 {
8524 case 'a':
8525 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8526 break;
8527
8528 default:
8529 abort ();
8530 }
8531
8532 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8533 first_fmac);
8534
99059e56 8535 newerr->vma = -1;
c7b8f16e 8536
99059e56
RM		 8537 newerr->next = sec_data->erratumlist;
8538 sec_data->erratumlist = newerr;
c7b8f16e 8539
99059e56
RM		 8540 state = 0;
8541 }
c7b8f16e 8542
99059e56
RM		 8543 i = next_i;
8544 }
8545 }
906e58ca 8546
c9594989 8547 if (elf_section_data (sec)->this_hdr.contents != contents)
99059e56 8548 free (contents);
c7b8f16e
JB		 8549 contents = NULL;
8550 }
8551
8552 return TRUE;
8553
dc1e8a47 8554 error_return:
c9594989 8555 if (elf_section_data (sec)->this_hdr.contents != contents)
c7b8f16e 8556 free (contents);
906e58ca 8557
c7b8f16e
JB		 8558 return FALSE;
8559}
8560
8561/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8562 after sections have been laid out, using specially-named symbols. */
8563
8564void
8565bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8566 struct bfd_link_info *link_info)
8567{
8568 asection *sec;
8569 struct elf32_arm_link_hash_table *globals;
8570 char *tmp_name;
906e58ca 8571
0e1862bb 8572 if (bfd_link_relocatable (link_info))
c7b8f16e 8573 return;
2e6030b9
MS		 8574
8575 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8576 if (! is_arm_elf (abfd))
2e6030b9
MS		 8577 return;
8578
c7b8f16e 8579 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8580 if (globals == NULL)
8581 return;
906e58ca 8582
21d799b5 8583 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8584 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
7a0fb7be 8585 BFD_ASSERT (tmp_name);
c7b8f16e
JB		 8586
8587 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8588 {
8589 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8590 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8591
c7b8f16e 8592 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8593 {
8594 struct elf_link_hash_entry *myh;
8595 bfd_vma vma;
8596
8597 switch (errnode->type)
8598 {
8599 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8600 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8601 /* Find veneer symbol. */
8602 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8603 errnode->u.b.veneer->u.v.id);
8604
99059e56
RM		 8605 myh = elf_link_hash_lookup
8606 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8607
a504d23a 8608 if (myh == NULL)
90b6238f
AM		 8609 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8610 abfd, "VFP11", tmp_name);
a504d23a
LA		 8611
8612 vma = myh->root.u.def.section->output_section->vma
8613 + myh->root.u.def.section->output_offset
8614 + myh->root.u.def.value;
8615
8616 errnode->u.b.veneer->vma = vma;
8617 break;
8618
8619 case VFP11_ERRATUM_ARM_VENEER:
8620 case VFP11_ERRATUM_THUMB_VENEER:
8621 /* Find return location. */
8622 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8623 errnode->u.v.id);
8624
8625 myh = elf_link_hash_lookup
8626 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8627
8628 if (myh == NULL)
90b6238f
AM		 8629 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8630 abfd, "VFP11", tmp_name);
a504d23a
LA		 8631
8632 vma = myh->root.u.def.section->output_section->vma
8633 + myh->root.u.def.section->output_offset
8634 + myh->root.u.def.value;
8635
8636 errnode->u.v.branch->vma = vma;
8637 break;
8638
8639 default:
8640 abort ();
8641 }
8642 }
8643 }
8644
8645 free (tmp_name);
8646}
8647
8648/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8649 return locations after sections have been laid out, using
8650 specially-named symbols. */
8651
8652void
8653bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8654 struct bfd_link_info *link_info)
8655{
8656 asection *sec;
8657 struct elf32_arm_link_hash_table *globals;
8658 char *tmp_name;
8659
8660 if (bfd_link_relocatable (link_info))
8661 return;
8662
8663 /* Skip if this bfd does not correspond to an ELF image. */
8664 if (! is_arm_elf (abfd))
8665 return;
8666
8667 globals = elf32_arm_hash_table (link_info);
8668 if (globals == NULL)
8669 return;
8670
8671 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8672 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7a0fb7be 8673 BFD_ASSERT (tmp_name);
a504d23a
LA		 8674
8675 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8676 {
8677 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8678 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8679
8680 for (; errnode != NULL; errnode = errnode->next)
8681 {
8682 struct elf_link_hash_entry *myh;
8683 bfd_vma vma;
8684
8685 switch (errnode->type)
8686 {
8687 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8688 /* Find veneer symbol. */
8689 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8690 errnode->u.b.veneer->u.v.id);
8691
8692 myh = elf_link_hash_lookup
8693 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8694
8695 if (myh == NULL)
90b6238f
AM		 8696 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8697 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8698
8699 vma = myh->root.u.def.section->output_section->vma
8700 + myh->root.u.def.section->output_offset
8701 + myh->root.u.def.value;
8702
8703 errnode->u.b.veneer->vma = vma;
8704 break;
8705
8706 case STM32L4XX_ERRATUM_VENEER:
8707 /* Find return location. */
8708 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8709 errnode->u.v.id);
8710
8711 myh = elf_link_hash_lookup
8712 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8713
8714 if (myh == NULL)
90b6238f
AM		 8715 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8716 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8717
8718 vma = myh->root.u.def.section->output_section->vma
8719 + myh->root.u.def.section->output_offset
8720 + myh->root.u.def.value;
8721
8722 errnode->u.v.branch->vma = vma;
8723 break;
8724
8725 default:
8726 abort ();
8727 }
8728 }
8729 }
8730
8731 free (tmp_name);
8732}
8733
8734static inline bfd_boolean
8735is_thumb2_ldmia (const insn32 insn)
8736{
8737 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8738 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8739 return (insn & 0xffd02000) == 0xe8900000;
8740}
8741
8742static inline bfd_boolean
8743is_thumb2_ldmdb (const insn32 insn)
8744{
8745 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8746 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8747 return (insn & 0xffd02000) == 0xe9100000;
8748}
8749
8750static inline bfd_boolean
8751is_thumb2_vldm (const insn32 insn)
8752{
8753 /* A6.5 Extension register load or store instruction
8754 A7.7.229
9239bbd3
CM		 8755 We look for SP 32-bit and DP 64-bit registers.
8756 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8757 <list> is consecutive 64-bit registers
8758 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8759 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8760 <list> is consecutive 32-bit registers
8761 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8762 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8763 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8764 return
9239bbd3
CM		 8765 (((insn & 0xfe100f00) == 0xec100b00) ||
8766 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8767 && /* (IA without !). */
8768 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8769 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8770 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8771 /* (DB with !). */
8772 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8773}
8774
8775/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8776 VLDM opcode and:
8777 - computes the number and the mode of memory accesses
8778 - decides if the replacement should be done:
8779 . replaces only if > 8-word accesses
8780 . or (testing purposes only) replaces all accesses. */
8781
8782static bfd_boolean
8783stm32l4xx_need_create_replacing_stub (const insn32 insn,
8784 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8785{
9239bbd3 8786 int nb_words = 0;
a504d23a
LA		 8787
8788 /* The field encoding the register list is the same for both LDMIA
8789 and LDMDB encodings. */
8790 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8791 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8792 else if (is_thumb2_vldm (insn))
9239bbd3 8793 nb_words = (insn & 0xff);
a504d23a
LA		 8794
8795 /* DEFAULT mode accounts for the real bug condition situation,
8796 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8797 return
9239bbd3 8798 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8799 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8800}
8801
8802/* Look for potentially-troublesome code sequences which might trigger
8803 the STM STM32L4XX erratum. */
8804
8805bfd_boolean
8806bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8807 struct bfd_link_info *link_info)
8808{
8809 asection *sec;
8810 bfd_byte *contents = NULL;
8811 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8812
8813 if (globals == NULL)
8814 return FALSE;
8815
8816 /* If we are only performing a partial link do not bother
8817 to construct any glue. */
8818 if (bfd_link_relocatable (link_info))
8819 return TRUE;
8820
8821 /* Skip if this bfd does not correspond to an ELF image. */
8822 if (! is_arm_elf (abfd))
8823 return TRUE;
8824
8825 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8826 return TRUE;
8827
8828 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8829 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8830 return TRUE;
8831
8832 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8833 {
8834 unsigned int i, span;
8835 struct _arm_elf_section_data *sec_data;
8836
8837 /* If we don't have executable progbits, we're not interested in this
8838 section. Also skip if section is to be excluded. */
8839 if (elf_section_type (sec) != SHT_PROGBITS
8840 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8841 || (sec->flags & SEC_EXCLUDE) != 0
8842 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8843 || sec->output_section == bfd_abs_section_ptr
8844 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8845 continue;
8846
8847 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8848
a504d23a
LA		 8849 if (sec_data->mapcount == 0)
8850 continue;
c7b8f16e 8851
a504d23a
LA		 8852 if (elf_section_data (sec)->this_hdr.contents != NULL)
8853 contents = elf_section_data (sec)->this_hdr.contents;
8854 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8855 goto error_return;
c7b8f16e 8856
a504d23a
LA		 8857 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8858 elf32_arm_compare_mapping);
c7b8f16e 8859
a504d23a
LA		 8860 for (span = 0; span < sec_data->mapcount; span++)
8861 {
8862 unsigned int span_start = sec_data->map[span].vma;
8863 unsigned int span_end = (span == sec_data->mapcount - 1)
8864 ? sec->size : sec_data->map[span + 1].vma;
8865 char span_type = sec_data->map[span].type;
8866 int itblock_current_pos = 0;
c7b8f16e 8867
a504d23a
LA		 8868 /* Only Thumb2 mode need be supported with this CM4 specific
8869 code, we should not encounter any arm mode eg span_type
8870 != 'a'. */
8871 if (span_type != 't')
8872 continue;
c7b8f16e 8873
a504d23a
LA		 8874 for (i = span_start; i < span_end;)
8875 {
8876 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8877 bfd_boolean insn_32bit = FALSE;
8878 bfd_boolean is_ldm = FALSE;
8879 bfd_boolean is_vldm = FALSE;
8880 bfd_boolean is_not_last_in_it_block = FALSE;
8881
8882 /* The first 16-bits of all 32-bit thumb2 instructions start
8883 with opcode[15..13]=0b111 and the encoded op1 can be anything
8884 except opcode[12..11]!=0b00.
8885 See 32-bit Thumb instruction encoding. */
8886 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8887 insn_32bit = TRUE;
c7b8f16e 8888
a504d23a
LA		 8889 /* Compute the predicate that tells if the instruction
8890 is concerned by the IT block
8891 - Creates an error if there is a ldm that is not
8892 last in the IT block thus cannot be replaced
8893 - Otherwise we can create a branch at the end of the
8894 IT block, it will be controlled naturally by IT
8895 with the proper pseudo-predicate
8896 - So the only interesting predicate is the one that
8897 tells that we are not on the last item of an IT
8898 block. */
8899 if (itblock_current_pos != 0)
8900 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8901
a504d23a
LA		 8902 if (insn_32bit)
8903 {
8904 /* Load the rest of the insn (in manual-friendly order). */
8905 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8906 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8907 is_vldm = is_thumb2_vldm (insn);
8908
8909 /* Veneers are created for (v)ldm depending on
8910 option flags and memory accesses conditions; but
8911 if the instruction is not the last instruction of
8912 an IT block, we cannot create a jump there, so we
8913 bail out. */
5025eb7c
AO		 8914 if ((is_ldm || is_vldm)
8915 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8916 (insn, globals->stm32l4xx_fix))
8917 {
8918 if (is_not_last_in_it_block)
8919 {
4eca0228 8920 _bfd_error_handler
695344c0 8921 /* xgettext:c-format */
871b3ab2 8922 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8923 " in non-last IT block instruction:"
8924 " STM32L4XX veneer cannot be generated; "
8925 "use gcc option -mrestrict-it to generate"
8926 " only one instruction per IT block"),
d42c267e 8927 abfd, sec, i);
a504d23a
LA		 8928 }
8929 else
8930 {
8931 elf32_stm32l4xx_erratum_list *newerr =
8932 (elf32_stm32l4xx_erratum_list *)
8933 bfd_zmalloc
8934 (sizeof (elf32_stm32l4xx_erratum_list));
8935
8936 elf32_arm_section_data (sec)
8937 ->stm32l4xx_erratumcount += 1;
8938 newerr->u.b.insn = insn;
8939 /* We create only thumb branches. */
8940 newerr->type =
8941 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8942 record_stm32l4xx_erratum_veneer
8943 (link_info, newerr, abfd, sec,
8944 i,
8945 is_ldm ?
8946 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8947 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8948 newerr->vma = -1;
8949 newerr->next = sec_data->stm32l4xx_erratumlist;
8950 sec_data->stm32l4xx_erratumlist = newerr;
8951 }
8952 }
8953 }
8954 else
8955 {
8956 /* A7.7.37 IT p208
8957 IT blocks are only encoded in T1
8958 Encoding T1: IT{x{y{z}}} <firstcond>
8959 1 0 1 1 - 1 1 1 1 - firstcond - mask
8960 if mask = '0000' then see 'related encodings'
8961 We don't deal with UNPREDICTABLE, just ignore these.
8962 There can be no nested IT blocks so an IT block
8963 is naturally a new one for which it is worth
8964 computing its size. */
5025eb7c
AO		 8965 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8966 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8967 /* If we have a new IT block we compute its size. */
8968 if (is_newitblock)
8969 {
8970 /* Compute the number of instructions controlled
8971 by the IT block, it will be used to decide
8972 whether we are inside an IT block or not. */
8973 unsigned int mask = insn & 0x000f;
8974 itblock_current_pos = 4 - ctz (mask);
8975 }
8976 }
8977
8978 i += insn_32bit ? 4 : 2;
99059e56
RM		 8979 }
8980 }
a504d23a 8981
c9594989 8982 if (elf_section_data (sec)->this_hdr.contents != contents)
a504d23a
LA		 8983 free (contents);
8984 contents = NULL;
c7b8f16e 8985 }
906e58ca 8986
a504d23a
LA		 8987 return TRUE;
8988
dc1e8a47 8989 error_return:
c9594989 8990 if (elf_section_data (sec)->this_hdr.contents != contents)
a504d23a 8991 free (contents);
c7b8f16e 8992
a504d23a
LA		 8993 return FALSE;
8994}
c7b8f16e 8995
eb043451
PB		 8996/* Set target relocation values needed during linking. */
8997
8998void
68c39892 8999bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 9000 struct bfd_link_info *link_info,
68c39892 9001 struct elf32_arm_params *params)
eb043451
PB		 9002{
9003 struct elf32_arm_link_hash_table *globals;
9004
9005 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9006 if (globals == NULL)
9007 return;
eb043451 9008
68c39892 9009 globals->target1_is_rel = params->target1_is_rel;
29e9b073
CL		 9010 if (globals->fdpic_p)
9011 globals->target2_reloc = R_ARM_GOT32;
9012 else if (strcmp (params->target2_type, "rel") == 0)
eb043451 9013 globals->target2_reloc = R_ARM_REL32;
68c39892 9014 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 9015 globals->target2_reloc = R_ARM_ABS32;
68c39892 9016 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 9017 globals->target2_reloc = R_ARM_GOT_PREL;
9018 else
9019 {
90b6238f 9020 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 9021 params->target2_type);
eb043451 9022 }
68c39892
TP		 9023 globals->fix_v4bx = params->fix_v4bx;
9024 globals->use_blx |= params->use_blx;
9025 globals->vfp11_fix = params->vfp11_denorm_fix;
9026 globals->stm32l4xx_fix = params->stm32l4xx_fix;
e8b09b87
CL		 9027 if (globals->fdpic_p)
9028 globals->pic_veneer = 1;
9029 else
9030 globals->pic_veneer = params->pic_veneer;
68c39892
TP		 9031 globals->fix_cortex_a8 = params->fix_cortex_a8;
9032 globals->fix_arm1176 = params->fix_arm1176;
9033 globals->cmse_implib = params->cmse_implib;
9034 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 9035
0ffa91dd 9036 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 9037 elf_arm_tdata (output_bfd)->no_enum_size_warning
9038 = params->no_enum_size_warning;
9039 elf_arm_tdata (output_bfd)->no_wchar_size_warning
9040 = params->no_wchar_size_warning;
eb043451 9041}
eb043451 9042
12a0a0fd 9043/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 9044
12a0a0fd
PB		 9045static void
9046insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
9047{
9048 bfd_vma upper;
9049 bfd_vma lower;
9050 int reloc_sign;
9051
9052 BFD_ASSERT ((offset & 1) == 0);
9053
9054 upper = bfd_get_16 (abfd, insn);
9055 lower = bfd_get_16 (abfd, insn + 2);
9056 reloc_sign = (offset < 0) ? 1 : 0;
9057 upper = (upper & ~(bfd_vma) 0x7ff)
9058 | ((offset >> 12) & 0x3ff)
9059 | (reloc_sign << 10);
906e58ca 9060 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 9061 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9062 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9063 | ((offset >> 1) & 0x7ff);
9064 bfd_put_16 (abfd, upper, insn);
9065 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 9066}
9067
9b485d32
NC		 9068/* Thumb code calling an ARM function. */
9069
252b5132 9070static int
57e8b36a 9071elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9072 const char * name,
9073 bfd * input_bfd,
9074 bfd * output_bfd,
9075 asection * input_section,
9076 bfd_byte * hit_data,
9077 asection * sym_sec,
9078 bfd_vma offset,
9079 bfd_signed_vma addend,
9080 bfd_vma val,
f2a9dd69 9081 char **error_message)
252b5132 9082{
bcbdc74c 9083 asection * s = 0;
dc810e39 9084 bfd_vma my_offset;
252b5132 9085 long int ret_offset;
bcbdc74c
NC		 9086 struct elf_link_hash_entry * myh;
9087 struct elf32_arm_link_hash_table * globals;
252b5132 9088
f2a9dd69 9089 myh = find_thumb_glue (info, name, error_message);
252b5132 9090 if (myh == NULL)
b34976b6 9091 return FALSE;
252b5132
RH		 9092
9093 globals = elf32_arm_hash_table (info);
252b5132
RH		 9094 BFD_ASSERT (globals != NULL);
9095 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9096
9097 my_offset = myh->root.u.def.value;
9098
3d4d4302
AM		 9099 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9100 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 9101
9102 BFD_ASSERT (s != NULL);
9103 BFD_ASSERT (s->contents != NULL);
9104 BFD_ASSERT (s->output_section != NULL);
9105
9106 if ((my_offset & 0x01) == 0x01)
9107 {
9108 if (sym_sec != NULL
9109 && sym_sec->owner != NULL
9110 && !INTERWORK_FLAG (sym_sec->owner))
9111 {
4eca0228 9112 _bfd_error_handler
90b6238f
AM		 9113 (_("%pB(%s): warning: interworking not enabled;"
9114 " first occurrence: %pB: %s call to %s"),
9115 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 9116
b34976b6 9117 return FALSE;
252b5132
RH		 9118 }
9119
9120 --my_offset;
9121 myh->root.u.def.value = my_offset;
9122
52ab56c2
PB		 9123 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9124 s->contents + my_offset);
252b5132 9125
52ab56c2
PB		 9126 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9127 s->contents + my_offset + 2);
252b5132
RH		 9128
9129 ret_offset =
9b485d32
NC		 9130 /* Address of destination of the stub. */
9131 ((bfd_signed_vma) val)
252b5132 9132 - ((bfd_signed_vma)
57e8b36a
NC		 9133 /* Offset from the start of the current section
9134 to the start of the stubs. */
9b485d32
NC		 9135 (s->output_offset
9136 /* Offset of the start of this stub from the start of the stubs. */
9137 + my_offset
9138 /* Address of the start of the current section. */
9139 + s->output_section->vma)
9140 /* The branch instruction is 4 bytes into the stub. */
9141 + 4
9142 /* ARM branches work from the pc of the instruction + 8. */
9143 + 8);
252b5132 9144
52ab56c2
PB		 9145 put_arm_insn (globals, output_bfd,
9146 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9147 s->contents + my_offset + 4);
252b5132
RH		 9148 }
9149
9150 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9151
427bfd90
NC		 9152 /* Now go back and fix up the original BL insn to point to here. */
9153 ret_offset =
9154 /* Address of where the stub is located. */
9155 (s->output_section->vma + s->output_offset + my_offset)
9156 /* Address of where the BL is located. */
57e8b36a
NC		 9157 - (input_section->output_section->vma + input_section->output_offset
9158 + offset)
427bfd90
NC		 9159 /* Addend in the relocation. */
9160 - addend
9161 /* Biassing for PC-relative addressing. */
9162 - 8;
252b5132 9163
12a0a0fd 9164 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 9165
b34976b6 9166 return TRUE;
252b5132
RH		 9167}
9168
a4fd1a8e 9169/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 9170
a4fd1a8e
PB		 9171static struct elf_link_hash_entry *
9172elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9173 const char * name,
9174 bfd * input_bfd,
9175 bfd * output_bfd,
9176 asection * sym_sec,
9177 bfd_vma val,
9178 asection * s,
9179 char ** error_message)
252b5132 9180{
dc810e39 9181 bfd_vma my_offset;
252b5132 9182 long int ret_offset;
bcbdc74c
NC		 9183 struct elf_link_hash_entry * myh;
9184 struct elf32_arm_link_hash_table * globals;
252b5132 9185
f2a9dd69 9186 myh = find_arm_glue (info, name, error_message);
252b5132 9187 if (myh == NULL)
a4fd1a8e 9188 return NULL;
252b5132
RH		 9189
9190 globals = elf32_arm_hash_table (info);
252b5132
RH		 9191 BFD_ASSERT (globals != NULL);
9192 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9193
9194 my_offset = myh->root.u.def.value;
252b5132
RH		 9195
9196 if ((my_offset & 0x01) == 0x01)
9197 {
9198 if (sym_sec != NULL
9199 && sym_sec->owner != NULL
9200 && !INTERWORK_FLAG (sym_sec->owner))
9201 {
4eca0228 9202 _bfd_error_handler
90b6238f
AM		 9203 (_("%pB(%s): warning: interworking not enabled;"
9204 " first occurrence: %pB: %s call to %s"),
9205 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 9206 }
9b485d32 9207
252b5132
RH		 9208 --my_offset;
9209 myh->root.u.def.value = my_offset;
9210
0e1862bb
L		 9211 if (bfd_link_pic (info)
9212 || globals->root.is_relocatable_executable
27e55c4d 9213 || globals->pic_veneer)
8f6277f5
PB		 9214 {
9215 /* For relocatable objects we can't use absolute addresses,
9216 so construct the address from a relative offset. */
9217 /* TODO: If the offset is small it's probably worth
9218 constructing the address with adds. */
52ab56c2
PB		 9219 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9220 s->contents + my_offset);
9221 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9222 s->contents + my_offset + 4);
9223 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9224 s->contents + my_offset + 8);
8f6277f5
PB		 9225 /* Adjust the offset by 4 for the position of the add,
9226 and 8 for the pipeline offset. */
9227 ret_offset = (val - (s->output_offset
9228 + s->output_section->vma
9229 + my_offset + 12))
9230 | 1;
9231 bfd_put_32 (output_bfd, ret_offset,
9232 s->contents + my_offset + 12);
9233 }
26079076
PB		 9234 else if (globals->use_blx)
9235 {
9236 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9237 s->contents + my_offset);
9238
9239 /* It's a thumb address. Add the low order bit. */
9240 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9241 s->contents + my_offset + 4);
9242 }
8f6277f5
PB		 9243 else
9244 {
52ab56c2
PB		 9245 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9246 s->contents + my_offset);
252b5132 9247
52ab56c2
PB		 9248 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9249 s->contents + my_offset + 4);
252b5132 9250
8f6277f5
PB		 9251 /* It's a thumb address. Add the low order bit. */
9252 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9253 s->contents + my_offset + 8);
8029a119
NC		 9254
9255 my_offset += 12;
8f6277f5 9256 }
252b5132
RH		 9257 }
9258
9259 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9260
a4fd1a8e
PB		 9261 return myh;
9262}
9263
9264/* Arm code calling a Thumb function. */
9265
9266static int
9267elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9268 const char * name,
9269 bfd * input_bfd,
9270 bfd * output_bfd,
9271 asection * input_section,
9272 bfd_byte * hit_data,
9273 asection * sym_sec,
9274 bfd_vma offset,
9275 bfd_signed_vma addend,
9276 bfd_vma val,
f2a9dd69 9277 char **error_message)
a4fd1a8e
PB		 9278{
9279 unsigned long int tmp;
9280 bfd_vma my_offset;
9281 asection * s;
9282 long int ret_offset;
9283 struct elf_link_hash_entry * myh;
9284 struct elf32_arm_link_hash_table * globals;
9285
9286 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9287 BFD_ASSERT (globals != NULL);
9288 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9289
3d4d4302
AM		 9290 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9291 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9292 BFD_ASSERT (s != NULL);
9293 BFD_ASSERT (s->contents != NULL);
9294 BFD_ASSERT (s->output_section != NULL);
9295
9296 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9297 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9298 if (!myh)
9299 return FALSE;
9300
9301 my_offset = myh->root.u.def.value;
252b5132
RH		 9302 tmp = bfd_get_32 (input_bfd, hit_data);
9303 tmp = tmp & 0xFF000000;
9304
9b485d32 9305 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9306 ret_offset = (s->output_offset
9307 + my_offset
9308 + s->output_section->vma
9309 - (input_section->output_offset
9310 + input_section->output_section->vma
9311 + offset + addend)
9312 - 8);
9a5aca8c 9313
252b5132
RH		 9314 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9315
dc810e39 9316 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9317
b34976b6 9318 return TRUE;
252b5132
RH		 9319}
9320
a4fd1a8e
PB		 9321/* Populate Arm stub for an exported Thumb function. */
9322
9323static bfd_boolean
9324elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9325{
9326 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9327 asection * s;
9328 struct elf_link_hash_entry * myh;
9329 struct elf32_arm_link_hash_entry *eh;
9330 struct elf32_arm_link_hash_table * globals;
9331 asection *sec;
9332 bfd_vma val;
f2a9dd69 9333 char *error_message;
a4fd1a8e 9334
906e58ca 9335 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9336 /* Allocate stubs for exported Thumb functions on v4t. */
9337 if (eh->export_glue == NULL)
9338 return TRUE;
9339
9340 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9341 BFD_ASSERT (globals != NULL);
9342 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9343
3d4d4302
AM		 9344 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9345 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9346 BFD_ASSERT (s != NULL);
9347 BFD_ASSERT (s->contents != NULL);
9348 BFD_ASSERT (s->output_section != NULL);
9349
9350 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9351
9352 BFD_ASSERT (sec->output_section != NULL);
9353
a4fd1a8e
PB		 9354 val = eh->export_glue->root.u.def.value + sec->output_offset
9355 + sec->output_section->vma;
8029a119 9356
a4fd1a8e
PB		 9357 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9358 h->root.u.def.section->owner,
f2a9dd69
DJ		 9359 globals->obfd, sec, val, s,
9360 &error_message);
a4fd1a8e
PB		 9361 BFD_ASSERT (myh);
9362 return TRUE;
9363}
9364
845b51d6
PB		 9365/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9366
9367static bfd_vma
9368elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9369{
9370 bfd_byte *p;
9371 bfd_vma glue_addr;
9372 asection *s;
9373 struct elf32_arm_link_hash_table *globals;
9374
9375 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9376 BFD_ASSERT (globals != NULL);
9377 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9378
3d4d4302
AM		 9379 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9380 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9381 BFD_ASSERT (s != NULL);
9382 BFD_ASSERT (s->contents != NULL);
9383 BFD_ASSERT (s->output_section != NULL);
9384
9385 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9386
9387 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9388
9389 if ((globals->bx_glue_offset[reg] & 1) == 0)
9390 {
9391 p = s->contents + glue_addr;
9392 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9393 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9394 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9395 globals->bx_glue_offset[reg] |= 1;
9396 }
9397
9398 return glue_addr + s->output_section->vma + s->output_offset;
9399}
9400
a4fd1a8e
PB		 9401/* Generate Arm stubs for exported Thumb symbols. */
9402static void
906e58ca 9403elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9404 struct bfd_link_info *link_info)
9405{
9406 struct elf32_arm_link_hash_table * globals;
9407
8029a119
NC		 9408 if (link_info == NULL)
9409 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9410 return;
9411
9412 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9413 if (globals == NULL)
9414 return;
9415
84c08195
PB		 9416 /* If blx is available then exported Thumb symbols are OK and there is
9417 nothing to do. */
a4fd1a8e
PB		 9418 if (globals->use_blx)
9419 return;
9420
9421 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9422 link_info);
9423}
9424
47beaa6a
RS		 9425/* Reserve space for COUNT dynamic relocations in relocation selection
9426 SRELOC. */
9427
9428static void
9429elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9430 bfd_size_type count)
9431{
9432 struct elf32_arm_link_hash_table *htab;
9433
9434 htab = elf32_arm_hash_table (info);
9435 BFD_ASSERT (htab->root.dynamic_sections_created);
9436 if (sreloc == NULL)
9437 abort ();
9438 sreloc->size += RELOC_SIZE (htab) * count;
9439}
9440
34e77a92
RS		 9441/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9442 dynamic, the relocations should go in SRELOC, otherwise they should
9443 go in the special .rel.iplt section. */
9444
9445static void
9446elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9447 bfd_size_type count)
9448{
9449 struct elf32_arm_link_hash_table *htab;
9450
9451 htab = elf32_arm_hash_table (info);
9452 if (!htab->root.dynamic_sections_created)
9453 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9454 else
9455 {
9456 BFD_ASSERT (sreloc != NULL);
9457 sreloc->size += RELOC_SIZE (htab) * count;
9458 }
9459}
9460
47beaa6a
RS		 9461/* Add relocation REL to the end of relocation section SRELOC. */
9462
9463static void
9464elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9465 asection *sreloc, Elf_Internal_Rela *rel)
9466{
9467 bfd_byte *loc;
9468 struct elf32_arm_link_hash_table *htab;
9469
9470 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9471 if (!htab->root.dynamic_sections_created
9472 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9473 sreloc = htab->root.irelplt;
47beaa6a
RS		 9474 if (sreloc == NULL)
9475 abort ();
9476 loc = sreloc->contents;
9477 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9478 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9479 abort ();
9480 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9481}
9482
34e77a92
RS		 9483/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9484 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9485 to .plt. */
9486
9487static void
9488elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9489 bfd_boolean is_iplt_entry,
9490 union gotplt_union *root_plt,
9491 struct arm_plt_info *arm_plt)
9492{
9493 struct elf32_arm_link_hash_table *htab;
9494 asection *splt;
9495 asection *sgotplt;
9496
9497 htab = elf32_arm_hash_table (info);
9498
9499 if (is_iplt_entry)
9500 {
9501 splt = htab->root.iplt;
9502 sgotplt = htab->root.igotplt;
9503
99059e56 9504 /* NaCl uses a special first entry in .iplt too. */
90c14f0c 9505 if (htab->root.target_os == is_nacl && splt->size == 0)
99059e56
RM		 9506 splt->size += htab->plt_header_size;
9507
34e77a92
RS		 9508 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9509 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9510 }
9511 else
9512 {
9513 splt = htab->root.splt;
9514 sgotplt = htab->root.sgotplt;
9515
7801f98f
CL		 9516 if (htab->fdpic_p)
9517 {
9518 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9519 /* For lazy binding, relocations will be put into .rel.plt, in
9520 .rel.got otherwise. */
9521 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9522 if (info->flags & DF_BIND_NOW)
9523 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9524 else
9525 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9526 }
9527 else
9528 {
9529 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9530 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9531 }
34e77a92
RS		 9532
9533 /* If this is the first .plt entry, make room for the special
9534 first entry. */
9535 if (splt->size == 0)
9536 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9537
9538 htab->next_tls_desc_index++;
34e77a92
RS		 9539 }
9540
9541 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9542 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9543 splt->size += PLT_THUMB_STUB_SIZE;
9544 root_plt->offset = splt->size;
9545 splt->size += htab->plt_entry_size;
9546
90c14f0c 9547 if (htab->root.target_os != is_symbian)
34e77a92
RS		 9548 {
9549 /* We also need to make an entry in the .got.plt section, which
9550 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9551 if (is_iplt_entry)
9552 arm_plt->got_offset = sgotplt->size;
9553 else
9554 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
7801f98f
CL		 9555 if (htab->fdpic_p)
9556 /* Function descriptor takes 64 bits in GOT. */
4b24dd1a 9557 sgotplt->size += 8;
7801f98f
CL		 9558 else
9559 sgotplt->size += 4;
34e77a92
RS		 9560 }
9561}
9562
b38cadfb
NC		 9563static bfd_vma
9564arm_movw_immediate (bfd_vma value)
9565{
9566 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9567}
9568
9569static bfd_vma
9570arm_movt_immediate (bfd_vma value)
9571{
9572 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9573}
9574
34e77a92
RS		 9575/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9576 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9577 Otherwise, DYNINDX is the index of the symbol in the dynamic
9578 symbol table and SYM_VALUE is undefined.
9579
9580 ROOT_PLT points to the offset of the PLT entry from the start of its
9581 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9582 bookkeeping information.
34e77a92 9583
57460bcf
NC		 9584 Returns FALSE if there was a problem. */
9585
9586static bfd_boolean
34e77a92
RS		 9587elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9588 union gotplt_union *root_plt,
9589 struct arm_plt_info *arm_plt,
9590 int dynindx, bfd_vma sym_value)
9591{
9592 struct elf32_arm_link_hash_table *htab;
9593 asection *sgot;
9594 asection *splt;
9595 asection *srel;
9596 bfd_byte *loc;
9597 bfd_vma plt_index;
9598 Elf_Internal_Rela rel;
9599 bfd_vma plt_header_size;
9600 bfd_vma got_header_size;
9601
9602 htab = elf32_arm_hash_table (info);
9603
9604 /* Pick the appropriate sections and sizes. */
9605 if (dynindx == -1)
9606 {
9607 splt = htab->root.iplt;
9608 sgot = htab->root.igotplt;
9609 srel = htab->root.irelplt;
9610
9611 /* There are no reserved entries in .igot.plt, and no special
9612 first entry in .iplt. */
9613 got_header_size = 0;
9614 plt_header_size = 0;
9615 }
9616 else
9617 {
9618 splt = htab->root.splt;
9619 sgot = htab->root.sgotplt;
9620 srel = htab->root.srelplt;
9621
9622 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9623 plt_header_size = htab->plt_header_size;
9624 }
9625 BFD_ASSERT (splt != NULL && srel != NULL);
9626
9627 /* Fill in the entry in the procedure linkage table. */
90c14f0c 9628 if (htab->root.target_os == is_symbian)
34e77a92
RS		 9629 {
9630 BFD_ASSERT (dynindx >= 0);
9631 put_arm_insn (htab, output_bfd,
9632 elf32_arm_symbian_plt_entry[0],
9633 splt->contents + root_plt->offset);
9634 bfd_put_32 (output_bfd,
9635 elf32_arm_symbian_plt_entry[1],
9636 splt->contents + root_plt->offset + 4);
9637
9638 /* Fill in the entry in the .rel.plt section. */
9639 rel.r_offset = (splt->output_section->vma
9640 + splt->output_offset
9641 + root_plt->offset + 4);
9642 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9643
9644 /* Get the index in the procedure linkage table which
9645 corresponds to this symbol. This is the index of this symbol
9646 in all the symbols for which we are making plt entries. The
9647 first entry in the procedure linkage table is reserved. */
9648 plt_index = ((root_plt->offset - plt_header_size)
9649 / htab->plt_entry_size);
9650 }
9651 else
9652 {
9653 bfd_vma got_offset, got_address, plt_address;
9654 bfd_vma got_displacement, initial_got_entry;
9655 bfd_byte * ptr;
9656
9657 BFD_ASSERT (sgot != NULL);
9658
9659 /* Get the offset into the .(i)got.plt table of the entry that
9660 corresponds to this function. */
9661 got_offset = (arm_plt->got_offset & -2);
9662
9663 /* Get the index in the procedure linkage table which
9664 corresponds to this symbol. This is the index of this symbol
9665 in all the symbols for which we are making plt entries.
9666 After the reserved .got.plt entries, all symbols appear in
9667 the same order as in .plt. */
7801f98f 9668 if (htab->fdpic_p)
4b24dd1a
AM		 9669 /* Function descriptor takes 8 bytes. */
9670 plt_index = (got_offset - got_header_size) / 8;
7801f98f 9671 else
4b24dd1a 9672 plt_index = (got_offset - got_header_size) / 4;
34e77a92
RS		 9673
9674 /* Calculate the address of the GOT entry. */
9675 got_address = (sgot->output_section->vma
9676 + sgot->output_offset
9677 + got_offset);
9678
9679 /* ...and the address of the PLT entry. */
9680 plt_address = (splt->output_section->vma
9681 + splt->output_offset
9682 + root_plt->offset);
9683
9684 ptr = splt->contents + root_plt->offset;
90c14f0c 9685 if (htab->root.target_os == is_vxworks && bfd_link_pic (info))
34e77a92
RS		 9686 {
9687 unsigned int i;
9688 bfd_vma val;
9689
9690 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9691 {
9692 val = elf32_arm_vxworks_shared_plt_entry[i];
9693 if (i == 2)
9694 val |= got_address - sgot->output_section->vma;
9695 if (i == 5)
9696 val |= plt_index * RELOC_SIZE (htab);
9697 if (i == 2 || i == 5)
9698 bfd_put_32 (output_bfd, val, ptr);
9699 else
9700 put_arm_insn (htab, output_bfd, val, ptr);
9701 }
9702 }
90c14f0c 9703 else if (htab->root.target_os == is_vxworks)
34e77a92
RS		 9704 {
9705 unsigned int i;
9706 bfd_vma val;
9707
9708 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9709 {
9710 val = elf32_arm_vxworks_exec_plt_entry[i];
9711 if (i == 2)
9712 val |= got_address;
9713 if (i == 4)
9714 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9715 if (i == 5)
9716 val |= plt_index * RELOC_SIZE (htab);
9717 if (i == 2 || i == 5)
9718 bfd_put_32 (output_bfd, val, ptr);
9719 else
9720 put_arm_insn (htab, output_bfd, val, ptr);
9721 }
9722
9723 loc = (htab->srelplt2->contents
9724 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9725
9726 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9727 referencing the GOT for this PLT entry. */
9728 rel.r_offset = plt_address + 8;
9729 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9730 rel.r_addend = got_offset;
9731 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9732 loc += RELOC_SIZE (htab);
9733
9734 /* Create the R_ARM_ABS32 relocation referencing the
9735 beginning of the PLT for this GOT entry. */
9736 rel.r_offset = got_address;
9737 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9738 rel.r_addend = 0;
9739 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9740 }
90c14f0c 9741 else if (htab->root.target_os == is_nacl)
b38cadfb
NC		 9742 {
9743 /* Calculate the displacement between the PLT slot and the
9744 common tail that's part of the special initial PLT slot. */
6034aab8 9745 int32_t tail_displacement
b38cadfb
NC		 9746 = ((splt->output_section->vma + splt->output_offset
9747 + ARM_NACL_PLT_TAIL_OFFSET)
9748 - (plt_address + htab->plt_entry_size + 4));
9749 BFD_ASSERT ((tail_displacement & 3) == 0);
9750 tail_displacement >>= 2;
9751
9752 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9753 || (-tail_displacement & 0xff000000) == 0);
9754
9755 /* Calculate the displacement between the PLT slot and the entry
9756 in the GOT. The offset accounts for the value produced by
9757 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9758 got_displacement = (got_address
99059e56 9759 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9760
9761 /* NaCl does not support interworking at all. */
9762 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9763
9764 put_arm_insn (htab, output_bfd,
9765 elf32_arm_nacl_plt_entry[0]
9766 | arm_movw_immediate (got_displacement),
9767 ptr + 0);
9768 put_arm_insn (htab, output_bfd,
9769 elf32_arm_nacl_plt_entry[1]
9770 | arm_movt_immediate (got_displacement),
9771 ptr + 4);
9772 put_arm_insn (htab, output_bfd,
9773 elf32_arm_nacl_plt_entry[2],
9774 ptr + 8);
9775 put_arm_insn (htab, output_bfd,
9776 elf32_arm_nacl_plt_entry[3]
9777 | (tail_displacement & 0x00ffffff),
9778 ptr + 12);
9779 }
7801f98f
CL		 9780 else if (htab->fdpic_p)
9781 {
59029f57
CL		 9782 const bfd_vma *plt_entry = using_thumb_only(htab)
9783 ? elf32_arm_fdpic_thumb_plt_entry
9784 : elf32_arm_fdpic_plt_entry;
9785
7801f98f
CL		 9786 /* Fill-up Thumb stub if needed. */
9787 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9788 {
9789 put_thumb_insn (htab, output_bfd,
9790 elf32_arm_plt_thumb_stub[0], ptr - 4);
9791 put_thumb_insn (htab, output_bfd,
9792 elf32_arm_plt_thumb_stub[1], ptr - 2);
9793 }
59029f57
CL		 9794 /* As we are using 32 bit instructions even for the Thumb
9795 version, we have to use 'put_arm_insn' instead of
9796 'put_thumb_insn'. */
9797 put_arm_insn(htab, output_bfd, plt_entry[0], ptr + 0);
9798 put_arm_insn(htab, output_bfd, plt_entry[1], ptr + 4);
9799 put_arm_insn(htab, output_bfd, plt_entry[2], ptr + 8);
9800 put_arm_insn(htab, output_bfd, plt_entry[3], ptr + 12);
7801f98f
CL		 9801 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9802
9803 if (!(info->flags & DF_BIND_NOW))
9804 {
9805 /* funcdesc_value_reloc_offset. */
9806 bfd_put_32 (output_bfd,
9807 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9808 ptr + 20);
59029f57
CL		 9809 put_arm_insn(htab, output_bfd, plt_entry[6], ptr + 24);
9810 put_arm_insn(htab, output_bfd, plt_entry[7], ptr + 28);
9811 put_arm_insn(htab, output_bfd, plt_entry[8], ptr + 32);
9812 put_arm_insn(htab, output_bfd, plt_entry[9], ptr + 36);
7801f98f
CL		 9813 }
9814 }
57460bcf
NC		 9815 else if (using_thumb_only (htab))
9816 {
eed94f8f 9817 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9818 if (!using_thumb2 (htab))
eed94f8f
NC		 9819 {
9820 /* FIXME: We ought to be able to generate thumb-1 PLT
9821 instructions... */
90b6238f 9822 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9823 output_bfd);
9824 return FALSE;
9825 }
57460bcf 9826
eed94f8f
NC		 9827 /* Calculate the displacement between the PLT slot and the entry in
9828 the GOT. The 12-byte offset accounts for the value produced by
9829 adding to pc in the 3rd instruction of the PLT stub. */
9830 got_displacement = got_address - (plt_address + 12);
9831
9832 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9833 instead of 'put_thumb_insn'. */
9834 put_arm_insn (htab, output_bfd,
9835 elf32_thumb2_plt_entry[0]
9836 | ((got_displacement & 0x000000ff) << 16)
9837 | ((got_displacement & 0x00000700) << 20)
9838 | ((got_displacement & 0x00000800) >> 1)
9839 | ((got_displacement & 0x0000f000) >> 12),
9840 ptr + 0);
9841 put_arm_insn (htab, output_bfd,
9842 elf32_thumb2_plt_entry[1]
9843 | ((got_displacement & 0x00ff0000) )
9844 | ((got_displacement & 0x07000000) << 4)
9845 | ((got_displacement & 0x08000000) >> 17)
9846 | ((got_displacement & 0xf0000000) >> 28),
9847 ptr + 4);
9848 put_arm_insn (htab, output_bfd,
9849 elf32_thumb2_plt_entry[2],
9850 ptr + 8);
9851 put_arm_insn (htab, output_bfd,
9852 elf32_thumb2_plt_entry[3],
9853 ptr + 12);
57460bcf 9854 }
34e77a92
RS		 9855 else
9856 {
9857 /* Calculate the displacement between the PLT slot and the
9858 entry in the GOT. The eight-byte offset accounts for the
9859 value produced by adding to pc in the first instruction
9860 of the PLT stub. */
9861 got_displacement = got_address - (plt_address + 8);
9862
34e77a92
RS		 9863 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9864 {
9865 put_thumb_insn (htab, output_bfd,
9866 elf32_arm_plt_thumb_stub[0], ptr - 4);
9867 put_thumb_insn (htab, output_bfd,
9868 elf32_arm_plt_thumb_stub[1], ptr - 2);
9869 }
9870
1db37fe6
YG		 9871 if (!elf32_arm_use_long_plt_entry)
9872 {
9873 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9874
9875 put_arm_insn (htab, output_bfd,
9876 elf32_arm_plt_entry_short[0]
9877 | ((got_displacement & 0x0ff00000) >> 20),
9878 ptr + 0);
9879 put_arm_insn (htab, output_bfd,
9880 elf32_arm_plt_entry_short[1]
9881 | ((got_displacement & 0x000ff000) >> 12),
9882 ptr+ 4);
9883 put_arm_insn (htab, output_bfd,
9884 elf32_arm_plt_entry_short[2]
9885 | (got_displacement & 0x00000fff),
9886 ptr + 8);
34e77a92 9887#ifdef FOUR_WORD_PLT
1db37fe6 9888 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9889#endif
1db37fe6
YG		 9890 }
9891 else
9892 {
9893 put_arm_insn (htab, output_bfd,
9894 elf32_arm_plt_entry_long[0]
9895 | ((got_displacement & 0xf0000000) >> 28),
9896 ptr + 0);
9897 put_arm_insn (htab, output_bfd,
9898 elf32_arm_plt_entry_long[1]
9899 | ((got_displacement & 0x0ff00000) >> 20),
9900 ptr + 4);
9901 put_arm_insn (htab, output_bfd,
9902 elf32_arm_plt_entry_long[2]
9903 | ((got_displacement & 0x000ff000) >> 12),
9904 ptr+ 8);
9905 put_arm_insn (htab, output_bfd,
9906 elf32_arm_plt_entry_long[3]
9907 | (got_displacement & 0x00000fff),
9908 ptr + 12);
9909 }
34e77a92
RS		 9910 }
9911
9912 /* Fill in the entry in the .rel(a).(i)plt section. */
9913 rel.r_offset = got_address;
9914 rel.r_addend = 0;
9915 if (dynindx == -1)
9916 {
9917 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9918 The dynamic linker or static executable then calls SYM_VALUE
9919 to determine the correct run-time value of the .igot.plt entry. */
9920 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9921 initial_got_entry = sym_value;
9922 }
9923 else
9924 {
7801f98f
CL		 9925 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9926 used by PLT entry. */
9927 if (htab->fdpic_p)
9928 {
9929 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
9930 initial_got_entry = 0;
9931 }
9932 else
9933 {
9934 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9935 initial_got_entry = (splt->output_section->vma
9936 + splt->output_offset);
a7618269
TC		 9937
9938 /* PR ld/16017
9939 When thumb only we need to set the LSB for any address that
9940 will be used with an interworking branch instruction. */
9941 if (using_thumb_only (htab))
9942 initial_got_entry |= 1;
7801f98f 9943 }
34e77a92
RS		 9944 }
9945
9946 /* Fill in the entry in the global offset table. */
9947 bfd_put_32 (output_bfd, initial_got_entry,
9948 sgot->contents + got_offset);
7801f98f
CL		 9949
9950 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
9951 {
9952 /* Setup initial funcdesc value. */
9953 /* FIXME: we don't support lazy binding because there is a
9954 race condition between both words getting written and
9955 some other thread attempting to read them. The ARM
9956 architecture does not have an atomic 64 bit load/store
9957 instruction that could be used to prevent it; it is
9958 recommended that threaded FDPIC applications run with the
9959 LD_BIND_NOW environment variable set. */
9960 bfd_put_32(output_bfd, plt_address + 0x18,
9961 sgot->contents + got_offset);
9962 bfd_put_32(output_bfd, -1 /*TODO*/,
9963 sgot->contents + got_offset + 4);
9964 }
34e77a92
RS		 9965 }
9966
aba8c3de
WN		 9967 if (dynindx == -1)
9968 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9969 else
9970 {
7801f98f
CL		 9971 if (htab->fdpic_p)
9972 {
9973 /* For FDPIC we put PLT relocationss into .rel.got when not
9974 lazy binding otherwise we put them in .rel.plt. For now,
9975 we don't support lazy binding so put it in .rel.got. */
9976 if (info->flags & DF_BIND_NOW)
9977 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelgot, &rel);
9978 else
9979 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelplt, &rel);
9980 }
9981 else
9982 {
9983 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9984 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9985 }
aba8c3de 9986 }
57460bcf
NC		 9987
9988 return TRUE;
34e77a92
RS		 9989}
9990
eb043451
PB		 9991/* Some relocations map to different relocations depending on the
9992 target. Return the real relocation. */
8029a119 9993
eb043451
PB		 9994static int
9995arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9996 int r_type)
9997{
9998 switch (r_type)
9999 {
10000 case R_ARM_TARGET1:
10001 if (globals->target1_is_rel)
10002 return R_ARM_REL32;
10003 else
10004 return R_ARM_ABS32;
10005
10006 case R_ARM_TARGET2:
10007 return globals->target2_reloc;
10008
10009 default:
10010 return r_type;
10011 }
10012}
eb043451 10013
ba93b8ac
DJ		 10014/* Return the base VMA address which should be subtracted from real addresses
10015 when resolving @dtpoff relocation.
10016 This is PT_TLS segment p_vaddr. */
10017
10018static bfd_vma
10019dtpoff_base (struct bfd_link_info *info)
10020{
10021 /* If tls_sec is NULL, we should have signalled an error already. */
10022 if (elf_hash_table (info)->tls_sec == NULL)
10023 return 0;
10024 return elf_hash_table (info)->tls_sec->vma;
10025}
10026
10027/* Return the relocation value for @tpoff relocation
10028 if STT_TLS virtual address is ADDRESS. */
10029
10030static bfd_vma
10031tpoff (struct bfd_link_info *info, bfd_vma address)
10032{
10033 struct elf_link_hash_table *htab = elf_hash_table (info);
10034 bfd_vma base;
10035
10036 /* If tls_sec is NULL, we should have signalled an error already. */
10037 if (htab->tls_sec == NULL)
10038 return 0;
10039 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
10040 return address - htab->tls_sec->vma + base;
10041}
10042
00a97672
RS		 10043/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10044 VALUE is the relocation value. */
10045
10046static bfd_reloc_status_type
10047elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
10048{
10049 if (value > 0xfff)
10050 return bfd_reloc_overflow;
10051
10052 value |= bfd_get_32 (abfd, data) & 0xfffff000;
10053 bfd_put_32 (abfd, value, data);
10054 return bfd_reloc_ok;
10055}
10056
0855e32b
NS		 10057/* Handle TLS relaxations. Relaxing is possible for symbols that use
10058 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10059 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10060
10061 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10062 is to then call final_link_relocate. Return other values in the
62672b10
NS		 10063 case of error.
10064
10065 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10066 the pre-relaxed code. It would be nice if the relocs were updated
10067 to match the optimization. */
0855e32b 10068
b38cadfb 10069static bfd_reloc_status_type
0855e32b 10070elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 10071 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 10072 Elf_Internal_Rela *rel, unsigned long is_local)
10073{
10074 unsigned long insn;
b38cadfb 10075
0855e32b
NS		 10076 switch (ELF32_R_TYPE (rel->r_info))
10077 {
10078 default:
10079 return bfd_reloc_notsupported;
b38cadfb 10080
0855e32b
NS		 10081 case R_ARM_TLS_GOTDESC:
10082 if (is_local)
10083 insn = 0;
10084 else
10085 {
10086 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10087 if (insn & 1)
10088 insn -= 5; /* THUMB */
10089 else
10090 insn -= 8; /* ARM */
10091 }
10092 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10093 return bfd_reloc_continue;
10094
10095 case R_ARM_THM_TLS_DESCSEQ:
10096 /* Thumb insn. */
10097 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10098 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10099 {
10100 if (is_local)
10101 /* nop */
10102 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10103 }
10104 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10105 {
10106 if (is_local)
10107 /* nop */
10108 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10109 else
10110 /* ldr rx,[ry] */
10111 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10112 }
10113 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10114 {
10115 if (is_local)
10116 /* nop */
10117 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10118 else
10119 /* mov r0, rx */
10120 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10121 contents + rel->r_offset);
10122 }
10123 else
10124 {
10125 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10126 /* It's a 32 bit instruction, fetch the rest of it for
10127 error generation. */
10128 insn = (insn << 16)
10129 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 10130 _bfd_error_handler
695344c0 10131 /* xgettext:c-format */
2dcf00ce 10132 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10133 "unexpected %s instruction '%#lx' in TLS trampoline"),
10134 input_bfd, input_sec, (uint64_t) rel->r_offset,
10135 "Thumb", insn);
0855e32b
NS		 10136 return bfd_reloc_notsupported;
10137 }
10138 break;
b38cadfb 10139
0855e32b
NS		 10140 case R_ARM_TLS_DESCSEQ:
10141 /* arm insn. */
10142 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10143 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10144 {
10145 if (is_local)
10146 /* mov rx, ry */
10147 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10148 contents + rel->r_offset);
10149 }
10150 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10151 {
10152 if (is_local)
10153 /* nop */
10154 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10155 else
10156 /* ldr rx,[ry] */
10157 bfd_put_32 (input_bfd, insn & 0xfffff000,
10158 contents + rel->r_offset);
10159 }
10160 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10161 {
10162 if (is_local)
10163 /* nop */
10164 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10165 else
10166 /* mov r0, rx */
10167 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10168 contents + rel->r_offset);
10169 }
10170 else
10171 {
4eca0228 10172 _bfd_error_handler
695344c0 10173 /* xgettext:c-format */
2dcf00ce 10174 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10175 "unexpected %s instruction '%#lx' in TLS trampoline"),
10176 input_bfd, input_sec, (uint64_t) rel->r_offset,
10177 "ARM", insn);
0855e32b
NS		 10178 return bfd_reloc_notsupported;
10179 }
10180 break;
10181
10182 case R_ARM_TLS_CALL:
10183 /* GD->IE relaxation, turn the instruction into 'nop' or
10184 'ldr r0, [pc,r0]' */
10185 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10186 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10187 break;
b38cadfb 10188
0855e32b 10189 case R_ARM_THM_TLS_CALL:
6a631e86 10190 /* GD->IE relaxation. */
0855e32b
NS		 10191 if (!is_local)
10192 /* add r0,pc; ldr r0, [r0] */
10193 insn = 0x44786800;
60a019a0 10194 else if (using_thumb2 (globals))
0855e32b
NS		 10195 /* nop.w */
10196 insn = 0xf3af8000;
10197 else
10198 /* nop; nop */
10199 insn = 0xbf00bf00;
b38cadfb 10200
0855e32b
NS		 10201 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10202 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10203 break;
10204 }
10205 return bfd_reloc_ok;
10206}
10207
4962c51a
MS		 10208/* For a given value of n, calculate the value of G_n as required to
10209 deal with group relocations. We return it in the form of an
10210 encoded constant-and-rotation, together with the final residual. If n is
10211 specified as less than zero, then final_residual is filled with the
10212 input value and no further action is performed. */
10213
10214static bfd_vma
10215calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10216{
10217 int current_n;
10218 bfd_vma g_n;
10219 bfd_vma encoded_g_n = 0;
10220 bfd_vma residual = value; /* Also known as Y_n. */
10221
10222 for (current_n = 0; current_n <= n; current_n++)
10223 {
10224 int shift;
10225
10226 /* Calculate which part of the value to mask. */
10227 if (residual == 0)
99059e56 10228 shift = 0;
4962c51a 10229 else
99059e56
RM		 10230 {
10231 int msb;
10232
10233 /* Determine the most significant bit in the residual and
10234 align the resulting value to a 2-bit boundary. */
10235 for (msb = 30; msb >= 0; msb -= 2)
10236 if (residual & (3 << msb))
10237 break;
10238
10239 /* The desired shift is now (msb - 6), or zero, whichever
10240 is the greater. */
10241 shift = msb - 6;
10242 if (shift < 0)
10243 shift = 0;
10244 }
4962c51a
MS		 10245
10246 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10247 g_n = residual & (0xff << shift);
10248 encoded_g_n = (g_n >> shift)
99059e56 10249 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 10250
10251 /* Calculate the residual for the next time around. */
10252 residual &= ~g_n;
10253 }
10254
10255 *final_residual = residual;
10256
10257 return encoded_g_n;
10258}
10259
10260/* Given an ARM instruction, determine whether it is an ADD or a SUB.
10261 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 10262
4962c51a 10263static int
906e58ca 10264identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 10265{
10266 int opcode = insn & 0x1e00000;
10267
10268 if (opcode == 1 << 23) /* ADD */
10269 return 1;
10270
10271 if (opcode == 1 << 22) /* SUB */
10272 return -1;
10273
10274 return 0;
10275}
10276
252b5132 10277/* Perform a relocation as part of a final link. */
9b485d32 10278
252b5132 10279static bfd_reloc_status_type
07d6d2b8
AM		 10280elf32_arm_final_link_relocate (reloc_howto_type * howto,
10281 bfd * input_bfd,
10282 bfd * output_bfd,
10283 asection * input_section,
10284 bfd_byte * contents,
10285 Elf_Internal_Rela * rel,
10286 bfd_vma value,
10287 struct bfd_link_info * info,
10288 asection * sym_sec,
10289 const char * sym_name,
10290 unsigned char st_type,
10291 enum arm_st_branch_type branch_type,
0945cdfd 10292 struct elf_link_hash_entry * h,
07d6d2b8
AM		 10293 bfd_boolean * unresolved_reloc_p,
10294 char ** error_message)
10295{
10296 unsigned long r_type = howto->type;
10297 unsigned long r_symndx;
10298 bfd_byte * hit_data = contents + rel->r_offset;
10299 bfd_vma * local_got_offsets;
10300 bfd_vma * local_tlsdesc_gotents;
10301 asection * sgot;
10302 asection * splt;
10303 asection * sreloc = NULL;
10304 asection * srelgot;
10305 bfd_vma addend;
10306 bfd_signed_vma signed_addend;
10307 unsigned char dynreloc_st_type;
10308 bfd_vma dynreloc_value;
ba96a88f 10309 struct elf32_arm_link_hash_table * globals;
34e77a92 10310 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 10311 union gotplt_union *root_plt;
10312 struct arm_plt_info *arm_plt;
10313 bfd_vma plt_offset;
10314 bfd_vma gotplt_offset;
10315 bfd_boolean has_iplt_entry;
10316 bfd_boolean resolved_to_zero;
f21f3fe0 10317
9c504268 10318 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 10319 if (globals == NULL)
10320 return bfd_reloc_notsupported;
9c504268 10321
0ffa91dd 10322 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 10323 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 10324
10325 /* Some relocation types map to different relocations depending on the
9c504268 10326 target. We pick the right one here. */
eb043451 10327 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 10328
10329 /* It is possible to have linker relaxations on some TLS access
10330 models. Update our information here. */
10331 r_type = elf32_arm_tls_transition (info, r_type, h);
10332
eb043451
PB		 10333 if (r_type != howto->type)
10334 howto = elf32_arm_howto_from_type (r_type);
9c504268 10335
34e77a92 10336 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 10337 sgot = globals->root.sgot;
252b5132 10338 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 10339 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10340
34e77a92
RS		 10341 if (globals->root.dynamic_sections_created)
10342 srelgot = globals->root.srelgot;
10343 else
10344 srelgot = NULL;
10345
252b5132
RH		 10346 r_symndx = ELF32_R_SYM (rel->r_info);
10347
4e7fd91e 10348 if (globals->use_rel)
ba96a88f 10349 {
4e7fd91e
PB		 10350 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
10351
10352 if (addend & ((howto->src_mask + 1) >> 1))
10353 {
10354 signed_addend = -1;
10355 signed_addend &= ~ howto->src_mask;
10356 signed_addend |= addend;
10357 }
10358 else
10359 signed_addend = addend;
ba96a88f
NC		 10360 }
10361 else
4e7fd91e 10362 addend = signed_addend = rel->r_addend;
f21f3fe0 10363
39f21624
NC		 10364 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10365 are resolving a function call relocation. */
10366 if (using_thumb_only (globals)
10367 && (r_type == R_ARM_THM_CALL
10368 || r_type == R_ARM_THM_JUMP24)
10369 && branch_type == ST_BRANCH_TO_ARM)
10370 branch_type = ST_BRANCH_TO_THUMB;
10371
34e77a92
RS		 10372 /* Record the symbol information that should be used in dynamic
10373 relocations. */
10374 dynreloc_st_type = st_type;
10375 dynreloc_value = value;
10376 if (branch_type == ST_BRANCH_TO_THUMB)
10377 dynreloc_value |= 1;
10378
10379 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10380 VALUE appropriately for relocations that we resolve at link time. */
10381 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10382 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10383 &arm_plt)
34e77a92
RS		 10384 && root_plt->offset != (bfd_vma) -1)
10385 {
10386 plt_offset = root_plt->offset;
10387 gotplt_offset = arm_plt->got_offset;
10388
10389 if (h == NULL || eh->is_iplt)
10390 {
10391 has_iplt_entry = TRUE;
10392 splt = globals->root.iplt;
10393
10394 /* Populate .iplt entries here, because not all of them will
10395 be seen by finish_dynamic_symbol. The lower bit is set if
10396 we have already populated the entry. */
10397 if (plt_offset & 1)
10398 plt_offset--;
10399 else
10400 {
57460bcf
NC		 10401 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10402 -1, dynreloc_value))
10403 root_plt->offset |= 1;
10404 else
10405 return bfd_reloc_notsupported;
34e77a92
RS		 10406 }
10407
10408 /* Static relocations always resolve to the .iplt entry. */
10409 st_type = STT_FUNC;
10410 value = (splt->output_section->vma
10411 + splt->output_offset
10412 + plt_offset);
10413 branch_type = ST_BRANCH_TO_ARM;
10414
10415 /* If there are non-call relocations that resolve to the .iplt
10416 entry, then all dynamic ones must too. */
10417 if (arm_plt->noncall_refcount != 0)
10418 {
10419 dynreloc_st_type = st_type;
10420 dynreloc_value = value;
10421 }
10422 }
10423 else
10424 /* We populate the .plt entry in finish_dynamic_symbol. */
10425 splt = globals->root.splt;
10426 }
10427 else
10428 {
10429 splt = NULL;
10430 plt_offset = (bfd_vma) -1;
10431 gotplt_offset = (bfd_vma) -1;
10432 }
10433
95b03e4a
L		 10434 resolved_to_zero = (h != NULL
10435 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10436
252b5132
RH		 10437 switch (r_type)
10438 {
10439 case R_ARM_NONE:
28a094c2
DJ		 10440 /* We don't need to find a value for this symbol. It's just a
10441 marker. */
10442 *unresolved_reloc_p = FALSE;
252b5132
RH		 10443 return bfd_reloc_ok;
10444
00a97672 10445 case R_ARM_ABS12:
90c14f0c 10446 if (globals->root.target_os != is_vxworks)
00a97672 10447 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10448 /* Fall through. */
00a97672 10449
252b5132
RH		 10450 case R_ARM_PC24:
10451 case R_ARM_ABS32:
bb224fc3 10452 case R_ARM_ABS32_NOI:
252b5132 10453 case R_ARM_REL32:
bb224fc3 10454 case R_ARM_REL32_NOI:
5b5bb741
PB		 10455 case R_ARM_CALL:
10456 case R_ARM_JUMP24:
dfc5f959 10457 case R_ARM_XPC25:
eb043451 10458 case R_ARM_PREL31:
7359ea65 10459 case R_ARM_PLT32:
7359ea65
DJ		 10460 /* Handle relocations which should use the PLT entry. ABS32/REL32
10461 will use the symbol's value, which may point to a PLT entry, but we
10462 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10463 branches in this object should go to it, except if the PLT is too
10464 far away, in which case a long branch stub should be inserted. */
bb224fc3 10465 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10466 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10467 && r_type != R_ARM_CALL
10468 && r_type != R_ARM_JUMP24
10469 && r_type != R_ARM_PLT32)
34e77a92 10470 && plt_offset != (bfd_vma) -1)
7359ea65 10471 {
34e77a92
RS		 10472 /* If we've created a .plt section, and assigned a PLT entry
10473 to this function, it must either be a STT_GNU_IFUNC reference
10474 or not be known to bind locally. In other cases, we should
10475 have cleared the PLT entry by now. */
10476 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10477
10478 value = (splt->output_section->vma
10479 + splt->output_offset
34e77a92 10480 + plt_offset);
0945cdfd 10481 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10482 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10483 contents, rel->r_offset, value,
00a97672 10484 rel->r_addend);
7359ea65
DJ		 10485 }
10486
67687978
PB		 10487 /* When generating a shared object or relocatable executable, these
10488 relocations are copied into the output file to be resolved at
10489 run time. */
0e1862bb 10490 if ((bfd_link_pic (info)
e8b09b87
CL		 10491 || globals->root.is_relocatable_executable
10492 || globals->fdpic_p)
7359ea65 10493 && (input_section->flags & SEC_ALLOC)
90c14f0c 10494 && !(globals->root.target_os == is_vxworks
3348747a
NS		 10495 && strcmp (input_section->output_section->name,
10496 ".tls_vars") == 0)
bb224fc3 10497 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10498 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10499 && !(input_bfd == globals->stub_bfd
10500 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10501 && (h == NULL
95b03e4a
L		 10502 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10503 && !resolved_to_zero)
7359ea65
DJ		 10504 || h->root.type != bfd_link_hash_undefweak)
10505 && r_type != R_ARM_PC24
5b5bb741
PB		 10506 && r_type != R_ARM_CALL
10507 && r_type != R_ARM_JUMP24
ee06dc07 10508 && r_type != R_ARM_PREL31
7359ea65 10509 && r_type != R_ARM_PLT32)
252b5132 10510 {
947216bf 10511 Elf_Internal_Rela outrel;
b34976b6 10512 bfd_boolean skip, relocate;
e8b09b87 10513 int isrofixup = 0;
f21f3fe0 10514
52db4ec2
JW		 10515 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10516 && !h->def_regular)
10517 {
10518 char *v = _("shared object");
10519
0e1862bb 10520 if (bfd_link_executable (info))
52db4ec2
JW		 10521 v = _("PIE executable");
10522
4eca0228 10523 _bfd_error_handler
871b3ab2 10524 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10525 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10526 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10527 return bfd_reloc_notsupported;
10528 }
10529
0945cdfd
DJ		 10530 *unresolved_reloc_p = FALSE;
10531
34e77a92 10532 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10533 {
83bac4b0
NC		 10534 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10535 ! globals->use_rel);
f21f3fe0 10536
83bac4b0 10537 if (sreloc == NULL)
252b5132 10538 return bfd_reloc_notsupported;
252b5132 10539 }
f21f3fe0 10540
b34976b6
AM		 10541 skip = FALSE;
10542 relocate = FALSE;
f21f3fe0 10543
00a97672 10544 outrel.r_addend = addend;
c629eae0
JJ		 10545 outrel.r_offset =
10546 _bfd_elf_section_offset (output_bfd, info, input_section,
10547 rel->r_offset);
10548 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10549 skip = TRUE;
0bb2d96a 10550 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10551 skip = TRUE, relocate = TRUE;
252b5132
RH		 10552 outrel.r_offset += (input_section->output_section->vma
10553 + input_section->output_offset);
f21f3fe0 10554
252b5132 10555 if (skip)
0bb2d96a 10556 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10557 else if (h != NULL
10558 && h->dynindx != -1
0e1862bb 10559 && (!bfd_link_pic (info)
1dcb9720
JW		 10560 || !(bfd_link_pie (info)
10561 || SYMBOLIC_BIND (info, h))
f5385ebf 10562 || !h->def_regular))
5e681ec4 10563 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10564 else
10565 {
a16385dc
MM		 10566 int symbol;
10567
5e681ec4 10568 /* This symbol is local, or marked to become local. */
e8b09b87
CL		 10569 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10570 || (globals->fdpic_p && !bfd_link_pic(info)));
90c14f0c 10571 if (globals->root.target_os == is_symbian)
6366ff1e 10572 {
74541ad4
AM		 10573 asection *osec;
10574
6366ff1e
MM		 10575 /* On Symbian OS, the data segment and text segement
10576 can be relocated independently. Therefore, we
10577 must indicate the segment to which this
10578 relocation is relative. The BPABI allows us to
10579 use any symbol in the right segment; we just use
10580 the section symbol as it is convenient. (We
10581 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10582 will not appear in the dynamic symbol table.)
10583
10584 Note that the dynamic linker ignores the section
10585 symbol value, so we don't subtract osec->vma
10586 from the emitted reloc addend. */
10dbd1f3 10587 if (sym_sec)
74541ad4 10588 osec = sym_sec->output_section;
10dbd1f3 10589 else
74541ad4
AM		 10590 osec = input_section->output_section;
10591 symbol = elf_section_data (osec)->dynindx;
10592 if (symbol == 0)
10593 {
10594 struct elf_link_hash_table *htab = elf_hash_table (info);
10595
10596 if ((osec->flags & SEC_READONLY) == 0
10597 && htab->data_index_section != NULL)
10598 osec = htab->data_index_section;
10599 else
10600 osec = htab->text_index_section;
10601 symbol = elf_section_data (osec)->dynindx;
10602 }
6366ff1e
MM		 10603 BFD_ASSERT (symbol != 0);
10604 }
a16385dc
MM		 10605 else
10606 /* On SVR4-ish systems, the dynamic loader cannot
10607 relocate the text and data segments independently,
10608 so the symbol does not matter. */
10609 symbol = 0;
34e77a92
RS		 10610 if (dynreloc_st_type == STT_GNU_IFUNC)
10611 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10612 to the .iplt entry. Instead, every non-call reference
10613 must use an R_ARM_IRELATIVE relocation to obtain the
10614 correct run-time address. */
10615 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
e8b09b87
CL		 10616 else if (globals->fdpic_p && !bfd_link_pic(info))
10617 isrofixup = 1;
34e77a92
RS		 10618 else
10619 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10620 if (globals->use_rel)
10621 relocate = TRUE;
10622 else
34e77a92 10623 outrel.r_addend += dynreloc_value;
252b5132 10624 }
f21f3fe0 10625
e8b09b87
CL		 10626 if (isrofixup)
10627 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
10628 else
10629 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10630
f21f3fe0 10631 /* If this reloc is against an external symbol, we do not want to
252b5132 10632 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10633 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10634 if (! relocate)
10635 return bfd_reloc_ok;
9a5aca8c 10636
f21f3fe0 10637 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10638 contents, rel->r_offset,
10639 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10640 }
10641 else switch (r_type)
10642 {
00a97672
RS		 10643 case R_ARM_ABS12:
10644 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10645
dfc5f959 10646 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10647 case R_ARM_CALL:
10648 case R_ARM_JUMP24:
8029a119 10649 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10650 case R_ARM_PLT32:
906e58ca 10651 {
906e58ca
NC		 10652 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10653
dfc5f959 10654 if (r_type == R_ARM_XPC25)
252b5132 10655 {
dfc5f959
NC		 10656 /* Check for Arm calling Arm function. */
10657 /* FIXME: Should we translate the instruction into a BL
10658 instruction instead ? */
35fc36a8 10659 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10660 _bfd_error_handler
90b6238f
AM		 10661 (_("\%pB: warning: %s BLX instruction targets"
10662 " %s function '%s'"),
10663 input_bfd, "ARM",
10664 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10665 }
155d87d7 10666 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10667 {
10668 /* Check for Arm calling Thumb function. */
35fc36a8 10669 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10670 {
f2a9dd69
DJ		 10671 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10672 output_bfd, input_section,
10673 hit_data, sym_sec, rel->r_offset,
10674 signed_addend, value,
10675 error_message))
10676 return bfd_reloc_ok;
10677 else
10678 return bfd_reloc_dangerous;
dfc5f959 10679 }
252b5132 10680 }
ba96a88f 10681
906e58ca 10682 /* Check if a stub has to be inserted because the
8029a119 10683 destination is too far or we are changing mode. */
155d87d7
CL		 10684 if ( r_type == R_ARM_CALL
10685 || r_type == R_ARM_JUMP24
10686 || r_type == R_ARM_PLT32)
906e58ca 10687 {
fe33d2fa
CL		 10688 enum elf32_arm_stub_type stub_type = arm_stub_none;
10689 struct elf32_arm_link_hash_entry *hash;
10690
10691 hash = (struct elf32_arm_link_hash_entry *) h;
10692 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10693 st_type, &branch_type,
10694 hash, value, sym_sec,
fe33d2fa 10695 input_bfd, sym_name);
5fa9e92f 10696
fe33d2fa 10697 if (stub_type != arm_stub_none)
906e58ca
NC		 10698 {
10699 /* The target is out of reach, so redirect the
10700 branch to the local stub for this function. */
906e58ca
NC		 10701 stub_entry = elf32_arm_get_stub_entry (input_section,
10702 sym_sec, h,
fe33d2fa
CL		 10703 rel, globals,
10704 stub_type);
9cd3e4e5
NC		 10705 {
10706 if (stub_entry != NULL)
10707 value = (stub_entry->stub_offset
10708 + stub_entry->stub_sec->output_offset
10709 + stub_entry->stub_sec->output_section->vma);
10710
10711 if (plt_offset != (bfd_vma) -1)
10712 *unresolved_reloc_p = FALSE;
10713 }
906e58ca 10714 }
fe33d2fa
CL		 10715 else
10716 {
10717 /* If the call goes through a PLT entry, make sure to
10718 check distance to the right destination address. */
34e77a92 10719 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10720 {
10721 value = (splt->output_section->vma
10722 + splt->output_offset
34e77a92 10723 + plt_offset);
fe33d2fa
CL		 10724 *unresolved_reloc_p = FALSE;
10725 /* The PLT entry is in ARM mode, regardless of the
10726 target function. */
35fc36a8 10727 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10728 }
10729 }
906e58ca
NC		 10730 }
10731
dea514f5
PB		 10732 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10733 where:
10734 S is the address of the symbol in the relocation.
10735 P is address of the instruction being relocated.
10736 A is the addend (extracted from the instruction) in bytes.
10737
10738 S is held in 'value'.
10739 P is the base address of the section containing the
10740 instruction plus the offset of the reloc into that
10741 section, ie:
10742 (input_section->output_section->vma +
10743 input_section->output_offset +
10744 rel->r_offset).
10745 A is the addend, converted into bytes, ie:
10746 (signed_addend * 4)
10747
10748 Note: None of these operations have knowledge of the pipeline
10749 size of the processor, thus it is up to the assembler to
10750 encode this information into the addend. */
10751 value -= (input_section->output_section->vma
10752 + input_section->output_offset);
10753 value -= rel->r_offset;
4e7fd91e
PB		 10754 if (globals->use_rel)
10755 value += (signed_addend << howto->size);
10756 else
10757 /* RELA addends do not have to be adjusted by howto->size. */
10758 value += signed_addend;
23080146 10759
dcb5e6e6
NC		 10760 signed_addend = value;
10761 signed_addend >>= howto->rightshift;
9a5aca8c 10762
5ab79981 10763 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10764 the next instruction unless a PLT entry will be created.
77b4f08f 10765 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10766 The jump to the next instruction is optimized as a NOP depending
10767 on the architecture. */
ffcb4889 10768 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10769 && plt_offset == (bfd_vma) -1)
77b4f08f 10770 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10771 {
cd1dac3d
DG		 10772 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10773
10774 if (arch_has_arm_nop (globals))
10775 value |= 0x0320f000;
10776 else
10777 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10778 }
10779 else
59f2c4e7 10780 {
9b485d32 10781 /* Perform a signed range check. */
dcb5e6e6 10782 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10783 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10784 return bfd_reloc_overflow;
9a5aca8c 10785
5ab79981 10786 addend = (value & 2);
39b41c9c 10787
5ab79981
PB		 10788 value = (signed_addend & howto->dst_mask)
10789 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10790
5ab79981
PB		 10791 if (r_type == R_ARM_CALL)
10792 {
155d87d7 10793 /* Set the H bit in the BLX instruction. */
35fc36a8 10794 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10795 {
10796 if (addend)
10797 value |= (1 << 24);
10798 else
10799 value &= ~(bfd_vma)(1 << 24);
10800 }
10801
5ab79981 10802 /* Select the correct instruction (BL or BLX). */
906e58ca 10803 /* Only if we are not handling a BL to a stub. In this
8029a119 10804 case, mode switching is performed by the stub. */
35fc36a8 10805 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10806 value |= (1 << 28);
63e1a0fc 10807 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10808 {
10809 value &= ~(bfd_vma)(1 << 28);
10810 value |= (1 << 24);
10811 }
39b41c9c
PB		 10812 }
10813 }
906e58ca 10814 }
252b5132 10815 break;
f21f3fe0 10816
252b5132
RH		 10817 case R_ARM_ABS32:
10818 value += addend;
35fc36a8 10819 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10820 value |= 1;
10821 break;
f21f3fe0 10822
bb224fc3
MS		 10823 case R_ARM_ABS32_NOI:
10824 value += addend;
10825 break;
10826
252b5132 10827 case R_ARM_REL32:
a8bc6c78 10828 value += addend;
35fc36a8 10829 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10830 value |= 1;
252b5132 10831 value -= (input_section->output_section->vma
62efb346 10832 + input_section->output_offset + rel->r_offset);
252b5132 10833 break;
eb043451 10834
bb224fc3
MS		 10835 case R_ARM_REL32_NOI:
10836 value += addend;
10837 value -= (input_section->output_section->vma
10838 + input_section->output_offset + rel->r_offset);
10839 break;
10840
eb043451
PB		 10841 case R_ARM_PREL31:
10842 value -= (input_section->output_section->vma
10843 + input_section->output_offset + rel->r_offset);
10844 value += signed_addend;
10845 if (! h || h->root.type != bfd_link_hash_undefweak)
10846 {
8029a119 10847 /* Check for overflow. */
eb043451
PB		 10848 if ((value ^ (value >> 1)) & (1 << 30))
10849 return bfd_reloc_overflow;
10850 }
10851 value &= 0x7fffffff;
10852 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10853 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10854 value |= 1;
10855 break;
252b5132 10856 }
f21f3fe0 10857
252b5132
RH		 10858 bfd_put_32 (input_bfd, value, hit_data);
10859 return bfd_reloc_ok;
10860
10861 case R_ARM_ABS8:
fd0fd00c
MJ		 10862 /* PR 16202: Refectch the addend using the correct size. */
10863 if (globals->use_rel)
10864 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10865 value += addend;
4e67d4ca
DG		 10866
10867 /* There is no way to tell whether the user intended to use a signed or
10868 unsigned addend. When checking for overflow we accept either,
10869 as specified by the AAELF. */
10870 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10871 return bfd_reloc_overflow;
10872
10873 bfd_put_8 (input_bfd, value, hit_data);
10874 return bfd_reloc_ok;
10875
10876 case R_ARM_ABS16:
fd0fd00c
MJ		 10877 /* PR 16202: Refectch the addend using the correct size. */
10878 if (globals->use_rel)
10879 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10880 value += addend;
10881
4e67d4ca
DG		 10882 /* See comment for R_ARM_ABS8. */
10883 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10884 return bfd_reloc_overflow;
10885
10886 bfd_put_16 (input_bfd, value, hit_data);
10887 return bfd_reloc_ok;
10888
252b5132 10889 case R_ARM_THM_ABS5:
9b485d32 10890 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10891 if (globals->use_rel)
10892 {
10893 /* Need to refetch addend. */
10894 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10895 /* ??? Need to determine shift amount from operand size. */
10896 addend >>= howto->rightshift;
10897 }
252b5132
RH		 10898 value += addend;
10899
10900 /* ??? Isn't value unsigned? */
10901 if ((long) value > 0x1f || (long) value < -0x10)
10902 return bfd_reloc_overflow;
10903
10904 /* ??? Value needs to be properly shifted into place first. */
10905 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10906 bfd_put_16 (input_bfd, value, hit_data);
10907 return bfd_reloc_ok;
10908
2cab6cc3
MS		 10909 case R_ARM_THM_ALU_PREL_11_0:
10910 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10911 {
10912 bfd_vma insn;
10913 bfd_signed_vma relocation;
10914
10915 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10916 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10917
99059e56
RM		 10918 if (globals->use_rel)
10919 {
10920 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10921 | ((insn & (1 << 26)) >> 15);
10922 if (insn & 0xf00000)
10923 signed_addend = -signed_addend;
10924 }
2cab6cc3
MS		 10925
10926 relocation = value + signed_addend;
79f08007 10927 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10928 + input_section->output_offset
10929 + rel->r_offset);
2cab6cc3 10930
8c65b54f
CS		 10931 /* PR 21523: Use an absolute value. The user of this reloc will
10932 have already selected an ADD or SUB insn appropriately. */
453f8e1e 10933 value = llabs (relocation);
2cab6cc3 10934
99059e56
RM		 10935 if (value >= 0x1000)
10936 return bfd_reloc_overflow;
2cab6cc3 10937
e645cf40
AG		 10938 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10939 if (branch_type == ST_BRANCH_TO_THUMB)
10940 value |= 1;
10941
2cab6cc3 10942 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10943 | ((value & 0x700) << 4)
10944 | ((value & 0x800) << 15);
10945 if (relocation < 0)
10946 insn |= 0xa00000;
2cab6cc3
MS		 10947
10948 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10949 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10950
99059e56 10951 return bfd_reloc_ok;
2cab6cc3
MS		 10952 }
10953
e1ec24c6
NC		 10954 case R_ARM_THM_PC8:
10955 /* PR 10073: This reloc is not generated by the GNU toolchain,
10956 but it is supported for compatibility with third party libraries
10957 generated by other compilers, specifically the ARM/IAR. */
10958 {
10959 bfd_vma insn;
10960 bfd_signed_vma relocation;
10961
10962 insn = bfd_get_16 (input_bfd, hit_data);
10963
99059e56 10964 if (globals->use_rel)
79f08007 10965 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10966
10967 relocation = value + addend;
79f08007 10968 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10969 + input_section->output_offset
10970 + rel->r_offset);
e1ec24c6 10971
b6518b38 10972 value = relocation;
e1ec24c6
NC		 10973
10974 /* We do not check for overflow of this reloc. Although strictly
10975 speaking this is incorrect, it appears to be necessary in order
10976 to work with IAR generated relocs. Since GCC and GAS do not
10977 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10978 a problem for them. */
10979 value &= 0x3fc;
10980
10981 insn = (insn & 0xff00) | (value >> 2);
10982
10983 bfd_put_16 (input_bfd, insn, hit_data);
10984
99059e56 10985 return bfd_reloc_ok;
e1ec24c6
NC		 10986 }
10987
2cab6cc3
MS		 10988 case R_ARM_THM_PC12:
10989 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10990 {
10991 bfd_vma insn;
10992 bfd_signed_vma relocation;
10993
10994 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10995 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10996
99059e56
RM		 10997 if (globals->use_rel)
10998 {
10999 signed_addend = insn & 0xfff;
11000 if (!(insn & (1 << 23)))
11001 signed_addend = -signed_addend;
11002 }
2cab6cc3
MS		 11003
11004 relocation = value + signed_addend;
79f08007 11005 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11006 + input_section->output_offset
11007 + rel->r_offset);
2cab6cc3 11008
b6518b38 11009 value = relocation;
2cab6cc3 11010
99059e56
RM		 11011 if (value >= 0x1000)
11012 return bfd_reloc_overflow;
2cab6cc3
MS		 11013
11014 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 11015 if (relocation >= 0)
11016 insn |= (1 << 23);
2cab6cc3
MS		 11017
11018 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11019 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11020
99059e56 11021 return bfd_reloc_ok;
2cab6cc3
MS		 11022 }
11023
dfc5f959 11024 case R_ARM_THM_XPC22:
c19d1205 11025 case R_ARM_THM_CALL:
bd97cb95 11026 case R_ARM_THM_JUMP24:
dfc5f959 11027 /* Thumb BL (branch long instruction). */
252b5132 11028 {
b34976b6 11029 bfd_vma relocation;
99059e56 11030 bfd_vma reloc_sign;
b34976b6
AM		 11031 bfd_boolean overflow = FALSE;
11032 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11033 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 11034 bfd_signed_vma reloc_signed_max;
11035 bfd_signed_vma reloc_signed_min;
b34976b6 11036 bfd_vma check;
252b5132 11037 bfd_signed_vma signed_check;
e95de063 11038 int bitsize;
cd1dac3d 11039 const int thumb2 = using_thumb2 (globals);
5e866f5a 11040 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 11041
5ab79981 11042 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 11043 the next instruction unless a PLT entry will be created.
11044 The jump to the next instruction is optimized as a NOP.W for
11045 Thumb-2 enabled architectures. */
19540007 11046 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 11047 && plt_offset == (bfd_vma) -1)
5ab79981 11048 {
60a019a0 11049 if (thumb2)
cd1dac3d
DG		 11050 {
11051 bfd_put_16 (input_bfd, 0xf3af, hit_data);
11052 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
11053 }
11054 else
11055 {
11056 bfd_put_16 (input_bfd, 0xe000, hit_data);
11057 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11058 }
5ab79981
PB		 11059 return bfd_reloc_ok;
11060 }
11061
e95de063 11062 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 11063 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 11064 if (globals->use_rel)
11065 {
99059e56
RM		 11066 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11067 bfd_vma upper = upper_insn & 0x3ff;
11068 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 11069 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11070 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 11071 bfd_vma i1 = j1 ^ s ? 0 : 1;
11072 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 11073
99059e56
RM		 11074 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11075 /* Sign extend. */
11076 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 11077
4e7fd91e
PB		 11078 signed_addend = addend;
11079 }
cb1afa5c 11080
dfc5f959
NC		 11081 if (r_type == R_ARM_THM_XPC22)
11082 {
11083 /* Check for Thumb to Thumb call. */
11084 /* FIXME: Should we translate the instruction into a BL
11085 instruction instead ? */
35fc36a8 11086 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 11087 _bfd_error_handler
90b6238f
AM		 11088 (_("%pB: warning: %s BLX instruction targets"
11089 " %s function '%s'"),
11090 input_bfd, "Thumb",
11091 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 11092 }
11093 else
252b5132 11094 {
dfc5f959
NC		 11095 /* If it is not a call to Thumb, assume call to Arm.
11096 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 11097 function call at all, but rather a long jump. Calls through
11098 the PLT do not require stubs. */
34e77a92 11099 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 11100 {
bd97cb95 11101 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11102 {
11103 /* Convert BL to BLX. */
11104 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11105 }
155d87d7
CL		 11106 else if (( r_type != R_ARM_THM_CALL)
11107 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 11108 {
11109 if (elf32_thumb_to_arm_stub
11110 (info, sym_name, input_bfd, output_bfd, input_section,
11111 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11112 error_message))
11113 return bfd_reloc_ok;
11114 else
11115 return bfd_reloc_dangerous;
11116 }
da5938a2 11117 }
35fc36a8
RS		 11118 else if (branch_type == ST_BRANCH_TO_THUMB
11119 && globals->use_blx
bd97cb95 11120 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11121 {
11122 /* Make sure this is a BL. */
11123 lower_insn |= 0x1800;
11124 }
252b5132 11125 }
f21f3fe0 11126
fe33d2fa 11127 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 11128 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 11129 {
11130 /* Check if a stub has to be inserted because the destination
8029a119 11131 is too far. */
fe33d2fa
CL		 11132 struct elf32_arm_stub_hash_entry *stub_entry;
11133 struct elf32_arm_link_hash_entry *hash;
11134
11135 hash = (struct elf32_arm_link_hash_entry *) h;
11136
11137 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 11138 st_type, &branch_type,
11139 hash, value, sym_sec,
fe33d2fa
CL		 11140 input_bfd, sym_name);
11141
11142 if (stub_type != arm_stub_none)
906e58ca
NC		 11143 {
11144 /* The target is out of reach or we are changing modes, so
11145 redirect the branch to the local stub for this
11146 function. */
11147 stub_entry = elf32_arm_get_stub_entry (input_section,
11148 sym_sec, h,
fe33d2fa
CL		 11149 rel, globals,
11150 stub_type);
906e58ca 11151 if (stub_entry != NULL)
9cd3e4e5
NC		 11152 {
11153 value = (stub_entry->stub_offset
11154 + stub_entry->stub_sec->output_offset
11155 + stub_entry->stub_sec->output_section->vma);
11156
11157 if (plt_offset != (bfd_vma) -1)
11158 *unresolved_reloc_p = FALSE;
11159 }
906e58ca 11160
f4ac8484 11161 /* If this call becomes a call to Arm, force BLX. */
155d87d7 11162 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 11163 {
11164 if ((stub_entry
11165 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 11166 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 11167 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11168 }
906e58ca
NC		 11169 }
11170 }
11171
fe33d2fa 11172 /* Handle calls via the PLT. */
34e77a92 11173 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 11174 {
11175 value = (splt->output_section->vma
11176 + splt->output_offset
34e77a92 11177 + plt_offset);
fe33d2fa 11178
eed94f8f
NC		 11179 if (globals->use_blx
11180 && r_type == R_ARM_THM_CALL
11181 && ! using_thumb_only (globals))
fe33d2fa
CL		 11182 {
11183 /* If the Thumb BLX instruction is available, convert
11184 the BL to a BLX instruction to call the ARM-mode
11185 PLT entry. */
11186 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 11187 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 11188 }
11189 else
11190 {
eed94f8f
NC		 11191 if (! using_thumb_only (globals))
11192 /* Target the Thumb stub before the ARM PLT entry. */
11193 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 11194 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 11195 }
11196 *unresolved_reloc_p = FALSE;
11197 }
11198
ba96a88f 11199 relocation = value + signed_addend;
f21f3fe0 11200
252b5132 11201 relocation -= (input_section->output_section->vma
ba96a88f
NC		 11202 + input_section->output_offset
11203 + rel->r_offset);
9a5aca8c 11204
252b5132
RH		 11205 check = relocation >> howto->rightshift;
11206
11207 /* If this is a signed value, the rightshift just dropped
11208 leading 1 bits (assuming twos complement). */
11209 if ((bfd_signed_vma) relocation >= 0)
11210 signed_check = check;
11211 else
11212 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11213
e95de063
MS		 11214 /* Calculate the permissable maximum and minimum values for
11215 this relocation according to whether we're relocating for
11216 Thumb-2 or not. */
11217 bitsize = howto->bitsize;
5e866f5a 11218 if (!thumb2_bl)
e95de063 11219 bitsize -= 2;
f6ebfac0 11220 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 11221 reloc_signed_min = ~reloc_signed_max;
11222
252b5132 11223 /* Assumes two's complement. */
ba96a88f 11224 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 11225 overflow = TRUE;
252b5132 11226
bd97cb95 11227 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 11228 /* For a BLX instruction, make sure that the relocation is rounded up
11229 to a word boundary. This follows the semantics of the instruction
11230 which specifies that bit 1 of the target address will come from bit
11231 1 of the base address. */
11232 relocation = (relocation + 2) & ~ 3;
cb1afa5c 11233
e95de063
MS		 11234 /* Put RELOCATION back into the insn. Assumes two's complement.
11235 We use the Thumb-2 encoding, which is safe even if dealing with
11236 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 11237 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 11238 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 11239 | ((relocation >> 12) & 0x3ff)
11240 | (reloc_sign << 10);
906e58ca 11241 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 11242 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11243 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11244 | ((relocation >> 1) & 0x7ff);
c62e1cc3 11245
252b5132
RH		 11246 /* Put the relocated value back in the object file: */
11247 bfd_put_16 (input_bfd, upper_insn, hit_data);
11248 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11249
11250 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11251 }
11252 break;
11253
c19d1205
ZW		 11254 case R_ARM_THM_JUMP19:
11255 /* Thumb32 conditional branch instruction. */
11256 {
11257 bfd_vma relocation;
11258 bfd_boolean overflow = FALSE;
11259 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11260 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 11261 bfd_signed_vma reloc_signed_max = 0xffffe;
11262 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 11263 bfd_signed_vma signed_check;
07d6d2b8 11264 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 11265 struct elf32_arm_stub_hash_entry *stub_entry;
11266 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 11267
11268 /* Need to refetch the addend, reconstruct the top three bits,
11269 and squish the two 11 bit pieces together. */
11270 if (globals->use_rel)
11271 {
11272 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 11273 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 11274 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11275 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11276 bfd_vma lower = (lower_insn & 0x07ff);
11277
a00a1f35
MS		 11278 upper |= J1 << 6;
11279 upper |= J2 << 7;
11280 upper |= (!S) << 8;
c19d1205
ZW		 11281 upper -= 0x0100; /* Sign extend. */
11282
11283 addend = (upper << 12) | (lower << 1);
11284 signed_addend = addend;
11285 }
11286
bd97cb95 11287 /* Handle calls via the PLT. */
34e77a92 11288 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 11289 {
11290 value = (splt->output_section->vma
11291 + splt->output_offset
34e77a92 11292 + plt_offset);
bd97cb95
DJ		 11293 /* Target the Thumb stub before the ARM PLT entry. */
11294 value -= PLT_THUMB_STUB_SIZE;
11295 *unresolved_reloc_p = FALSE;
11296 }
11297
c5423981
TG		 11298 hash = (struct elf32_arm_link_hash_entry *)h;
11299
11300 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 11301 st_type, &branch_type,
11302 hash, value, sym_sec,
11303 input_bfd, sym_name);
c5423981
TG		 11304 if (stub_type != arm_stub_none)
11305 {
11306 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 11307 sym_sec, h,
11308 rel, globals,
11309 stub_type);
c5423981
TG		 11310 if (stub_entry != NULL)
11311 {
07d6d2b8
AM		 11312 value = (stub_entry->stub_offset
11313 + stub_entry->stub_sec->output_offset
11314 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 11315 }
11316 }
c19d1205 11317
99059e56 11318 relocation = value + signed_addend;
c19d1205
ZW		 11319 relocation -= (input_section->output_section->vma
11320 + input_section->output_offset
11321 + rel->r_offset);
a00a1f35 11322 signed_check = (bfd_signed_vma) relocation;
c19d1205 11323
c19d1205
ZW		 11324 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11325 overflow = TRUE;
11326
11327 /* Put RELOCATION back into the insn. */
11328 {
11329 bfd_vma S = (relocation & 0x00100000) >> 20;
11330 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11331 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11332 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11333 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11334
a00a1f35 11335 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 11336 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11337 }
11338
11339 /* Put the relocated value back in the object file: */
11340 bfd_put_16 (input_bfd, upper_insn, hit_data);
11341 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11342
11343 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11344 }
11345
11346 case R_ARM_THM_JUMP11:
11347 case R_ARM_THM_JUMP8:
11348 case R_ARM_THM_JUMP6:
51c5503b
NC		 11349 /* Thumb B (branch) instruction). */
11350 {
6cf9e9fe 11351 bfd_signed_vma relocation;
51c5503b
NC		 11352 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11353 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11354 bfd_signed_vma signed_check;
11355
c19d1205
ZW		 11356 /* CZB cannot jump backward. */
11357 if (r_type == R_ARM_THM_JUMP6)
11358 reloc_signed_min = 0;
11359
4e7fd91e 11360 if (globals->use_rel)
6cf9e9fe 11361 {
4e7fd91e
PB		 11362 /* Need to refetch addend. */
11363 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
11364 if (addend & ((howto->src_mask + 1) >> 1))
11365 {
11366 signed_addend = -1;
11367 signed_addend &= ~ howto->src_mask;
11368 signed_addend |= addend;
11369 }
11370 else
11371 signed_addend = addend;
11372 /* The value in the insn has been right shifted. We need to
11373 undo this, so that we can perform the address calculation
11374 in terms of bytes. */
11375 signed_addend <<= howto->rightshift;
6cf9e9fe 11376 }
6cf9e9fe 11377 relocation = value + signed_addend;
51c5503b
NC		 11378
11379 relocation -= (input_section->output_section->vma
11380 + input_section->output_offset
11381 + rel->r_offset);
11382
6cf9e9fe
NC		 11383 relocation >>= howto->rightshift;
11384 signed_check = relocation;
c19d1205
ZW		 11385
11386 if (r_type == R_ARM_THM_JUMP6)
11387 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11388 else
11389 relocation &= howto->dst_mask;
51c5503b 11390 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11391
51c5503b
NC		 11392 bfd_put_16 (input_bfd, relocation, hit_data);
11393
11394 /* Assumes two's complement. */
11395 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11396 return bfd_reloc_overflow;
11397
11398 return bfd_reloc_ok;
11399 }
cedb70c5 11400
8375c36b
PB		 11401 case R_ARM_ALU_PCREL7_0:
11402 case R_ARM_ALU_PCREL15_8:
11403 case R_ARM_ALU_PCREL23_15:
11404 {
11405 bfd_vma insn;
11406 bfd_vma relocation;
11407
11408 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11409 if (globals->use_rel)
11410 {
11411 /* Extract the addend. */
11412 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11413 signed_addend = addend;
11414 }
8375c36b
PB		 11415 relocation = value + signed_addend;
11416
11417 relocation -= (input_section->output_section->vma
11418 + input_section->output_offset
11419 + rel->r_offset);
11420 insn = (insn & ~0xfff)
11421 | ((howto->bitpos << 7) & 0xf00)
11422 | ((relocation >> howto->bitpos) & 0xff);
11423 bfd_put_32 (input_bfd, value, hit_data);
11424 }
11425 return bfd_reloc_ok;
11426
252b5132
RH		 11427 case R_ARM_GNU_VTINHERIT:
11428 case R_ARM_GNU_VTENTRY:
11429 return bfd_reloc_ok;
11430
c19d1205 11431 case R_ARM_GOTOFF32:
252b5132 11432 /* Relocation is relative to the start of the
99059e56 11433 global offset table. */
252b5132
RH		 11434
11435 BFD_ASSERT (sgot != NULL);
11436 if (sgot == NULL)
99059e56 11437 return bfd_reloc_notsupported;
9a5aca8c 11438
cedb70c5 11439 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11440 address by one, so that attempts to call the function pointer will
11441 correctly interpret it as Thumb code. */
35fc36a8 11442 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11443 value += 1;
11444
252b5132 11445 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11446 calculation. We always want the start of .got. If we
11447 define _GLOBAL_OFFSET_TABLE in a different way, as is
11448 permitted by the ABI, we might have to change this
11449 calculation. */
252b5132 11450 value -= sgot->output_section->vma;
f21f3fe0 11451 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11452 contents, rel->r_offset, value,
00a97672 11453 rel->r_addend);
252b5132
RH		 11454
11455 case R_ARM_GOTPC:
a7c10850 11456 /* Use global offset table as symbol value. */
252b5132 11457 BFD_ASSERT (sgot != NULL);
f21f3fe0 11458
252b5132 11459 if (sgot == NULL)
99059e56 11460 return bfd_reloc_notsupported;
252b5132 11461
0945cdfd 11462 *unresolved_reloc_p = FALSE;
252b5132 11463 value = sgot->output_section->vma;
f21f3fe0 11464 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11465 contents, rel->r_offset, value,
00a97672 11466 rel->r_addend);
f21f3fe0 11467
252b5132 11468 case R_ARM_GOT32:
eb043451 11469 case R_ARM_GOT_PREL:
252b5132 11470 /* Relocation is to the entry for this symbol in the
99059e56 11471 global offset table. */
252b5132
RH		 11472 if (sgot == NULL)
11473 return bfd_reloc_notsupported;
f21f3fe0 11474
34e77a92
RS		 11475 if (dynreloc_st_type == STT_GNU_IFUNC
11476 && plt_offset != (bfd_vma) -1
11477 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11478 {
11479 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11480 symbol, and the relocation resolves directly to the runtime
11481 target rather than to the .iplt entry. This means that any
11482 .got entry would be the same value as the .igot.plt entry,
11483 so there's no point creating both. */
11484 sgot = globals->root.igotplt;
11485 value = sgot->output_offset + gotplt_offset;
11486 }
11487 else if (h != NULL)
252b5132
RH		 11488 {
11489 bfd_vma off;
f21f3fe0 11490
252b5132
RH		 11491 off = h->got.offset;
11492 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11493 if ((off & 1) != 0)
252b5132 11494 {
b436d854
RS		 11495 /* We have already processsed one GOT relocation against
11496 this symbol. */
11497 off &= ~1;
11498 if (globals->root.dynamic_sections_created
11499 && !SYMBOL_REFERENCES_LOCAL (info, h))
11500 *unresolved_reloc_p = FALSE;
11501 }
11502 else
11503 {
11504 Elf_Internal_Rela outrel;
e8b09b87 11505 int isrofixup = 0;
b436d854 11506
e8b09b87
CL		 11507 if (((h->dynindx != -1) || globals->fdpic_p)
11508 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11509 {
11510 /* If the symbol doesn't resolve locally in a static
11511 object, we have an undefined reference. If the
11512 symbol doesn't resolve locally in a dynamic object,
11513 it should be resolved by the dynamic linker. */
11514 if (globals->root.dynamic_sections_created)
11515 {
11516 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11517 *unresolved_reloc_p = FALSE;
11518 }
11519 else
11520 outrel.r_info = 0;
11521 outrel.r_addend = 0;
11522 }
252b5132
RH		 11523 else
11524 {
34e77a92 11525 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11526 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c 11527 else if (bfd_link_pic (info)
7f026732 11528 && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
99059e56
RM		 11529 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11530 else
2376f038
EB		 11531 {
11532 outrel.r_info = 0;
11533 if (globals->fdpic_p)
11534 isrofixup = 1;
11535 }
34e77a92 11536 outrel.r_addend = dynreloc_value;
b436d854 11537 }
ee29b9fb 11538
b436d854
RS		 11539 /* The GOT entry is initialized to zero by default.
11540 See if we should install a different value. */
11541 if (outrel.r_addend != 0
2376f038 11542 && (globals->use_rel || outrel.r_info == 0))
b436d854
RS		 11543 {
11544 bfd_put_32 (output_bfd, outrel.r_addend,
11545 sgot->contents + off);
11546 outrel.r_addend = 0;
252b5132 11547 }
f21f3fe0 11548
2376f038
EB		 11549 if (isrofixup)
11550 arm_elf_add_rofixup (output_bfd,
11551 elf32_arm_hash_table(info)->srofixup,
11552 sgot->output_section->vma
11553 + sgot->output_offset + off);
11554
11555 else if (outrel.r_info != 0)
b436d854
RS		 11556 {
11557 outrel.r_offset = (sgot->output_section->vma
11558 + sgot->output_offset
11559 + off);
11560 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11561 }
2376f038 11562
b436d854
RS		 11563 h->got.offset |= 1;
11564 }
252b5132
RH		 11565 value = sgot->output_offset + off;
11566 }
11567 else
11568 {
11569 bfd_vma off;
f21f3fe0 11570
5025eb7c
AO		 11571 BFD_ASSERT (local_got_offsets != NULL
11572 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11573
252b5132 11574 off = local_got_offsets[r_symndx];
f21f3fe0 11575
252b5132
RH		 11576 /* The offset must always be a multiple of 4. We use the
11577 least significant bit to record whether we have already
9b485d32 11578 generated the necessary reloc. */
252b5132
RH		 11579 if ((off & 1) != 0)
11580 off &= ~1;
11581 else
11582 {
2376f038
EB		 11583 Elf_Internal_Rela outrel;
11584 int isrofixup = 0;
f21f3fe0 11585
2376f038
EB		 11586 if (dynreloc_st_type == STT_GNU_IFUNC)
11587 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11588 else if (bfd_link_pic (info))
11589 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11590 else
252b5132 11591 {
2376f038
EB		 11592 outrel.r_info = 0;
11593 if (globals->fdpic_p)
11594 isrofixup = 1;
11595 }
11596
11597 /* The GOT entry is initialized to zero by default.
11598 See if we should install a different value. */
11599 if (globals->use_rel || outrel.r_info == 0)
11600 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
11601
11602 if (isrofixup)
11603 arm_elf_add_rofixup (output_bfd,
11604 globals->srofixup,
11605 sgot->output_section->vma
11606 + sgot->output_offset + off);
f21f3fe0 11607
2376f038
EB		 11608 else if (outrel.r_info != 0)
11609 {
34e77a92 11610 outrel.r_addend = addend + dynreloc_value;
252b5132 11611 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11612 + sgot->output_offset
252b5132 11613 + off);
47beaa6a 11614 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11615 }
f21f3fe0 11616
252b5132
RH		 11617 local_got_offsets[r_symndx] |= 1;
11618 }
f21f3fe0 11619
252b5132
RH		 11620 value = sgot->output_offset + off;
11621 }
eb043451
PB		 11622 if (r_type != R_ARM_GOT32)
11623 value += sgot->output_section->vma;
9a5aca8c 11624
f21f3fe0 11625 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11626 contents, rel->r_offset, value,
00a97672 11627 rel->r_addend);
f21f3fe0 11628
ba93b8ac
DJ		 11629 case R_ARM_TLS_LDO32:
11630 value = value - dtpoff_base (info);
11631
11632 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11633 contents, rel->r_offset, value,
11634 rel->r_addend);
ba93b8ac
DJ		 11635
11636 case R_ARM_TLS_LDM32:
5c5a4843 11637 case R_ARM_TLS_LDM32_FDPIC:
ba93b8ac
DJ		 11638 {
11639 bfd_vma off;
11640
362d30a1 11641 if (sgot == NULL)
ba93b8ac
DJ		 11642 abort ();
11643
11644 off = globals->tls_ldm_got.offset;
11645
11646 if ((off & 1) != 0)
11647 off &= ~1;
11648 else
11649 {
11650 /* If we don't know the module number, create a relocation
11651 for it. */
9cb09e33 11652 if (bfd_link_dll (info))
ba93b8ac
DJ		 11653 {
11654 Elf_Internal_Rela outrel;
ba93b8ac 11655
362d30a1 11656 if (srelgot == NULL)
ba93b8ac
DJ		 11657 abort ();
11658
00a97672 11659 outrel.r_addend = 0;
362d30a1
RS		 11660 outrel.r_offset = (sgot->output_section->vma
11661 + sgot->output_offset + off);
ba93b8ac
DJ		 11662 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11663
00a97672
RS		 11664 if (globals->use_rel)
11665 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11666 sgot->contents + off);
ba93b8ac 11667
47beaa6a 11668 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11669 }
11670 else
362d30a1 11671 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11672
11673 globals->tls_ldm_got.offset |= 1;
11674 }
11675
5c5a4843 11676 if (r_type == R_ARM_TLS_LDM32_FDPIC)
e8b09b87
CL		 11677 {
11678 bfd_put_32(output_bfd,
11679 globals->root.sgot->output_offset + off,
11680 contents + rel->r_offset);
11681
11682 return bfd_reloc_ok;
11683 }
11684 else
11685 {
11686 value = sgot->output_section->vma + sgot->output_offset + off
11687 - (input_section->output_section->vma
11688 + input_section->output_offset + rel->r_offset);
ba93b8ac 11689
e8b09b87
CL		 11690 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11691 contents, rel->r_offset, value,
11692 rel->r_addend);
11693 }
ba93b8ac
DJ		 11694 }
11695
0855e32b
NS		 11696 case R_ARM_TLS_CALL:
11697 case R_ARM_THM_TLS_CALL:
ba93b8ac 11698 case R_ARM_TLS_GD32:
5c5a4843 11699 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 11700 case R_ARM_TLS_IE32:
5c5a4843 11701 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 11702 case R_ARM_TLS_GOTDESC:
11703 case R_ARM_TLS_DESCSEQ:
11704 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11705 {
0855e32b
NS		 11706 bfd_vma off, offplt;
11707 int indx = 0;
ba93b8ac
DJ		 11708 char tls_type;
11709
0855e32b 11710 BFD_ASSERT (sgot != NULL);
ba93b8ac 11711
ba93b8ac
DJ		 11712 if (h != NULL)
11713 {
11714 bfd_boolean dyn;
11715 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11716 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11717 bfd_link_pic (info),
11718 h)
11719 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11720 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11721 {
11722 *unresolved_reloc_p = FALSE;
11723 indx = h->dynindx;
11724 }
11725 off = h->got.offset;
0855e32b 11726 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11727 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11728 }
11729 else
11730 {
0855e32b 11731 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11732 off = local_got_offsets[r_symndx];
0855e32b 11733 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11734 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11735 }
11736
0855e32b 11737 /* Linker relaxations happens from one of the
b38cadfb 11738 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11739 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11740 tls_type = GOT_TLS_IE;
0855e32b
NS		 11741
11742 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11743
11744 if ((off & 1) != 0)
11745 off &= ~1;
11746 else
11747 {
11748 bfd_boolean need_relocs = FALSE;
11749 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11750 int cur_off = off;
11751
11752 /* The GOT entries have not been initialized yet. Do it
11753 now, and emit any relocations. If both an IE GOT and a
11754 GD GOT are necessary, we emit the GD first. */
11755
9cb09e33 11756 if ((bfd_link_dll (info) || indx != 0)
ba93b8ac 11757 && (h == NULL
95b03e4a
L		 11758 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11759 && !resolved_to_zero)
ba93b8ac
DJ		 11760 || h->root.type != bfd_link_hash_undefweak))
11761 {
11762 need_relocs = TRUE;
0855e32b 11763 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11764 }
11765
0855e32b
NS		 11766 if (tls_type & GOT_TLS_GDESC)
11767 {
47beaa6a
RS		 11768 bfd_byte *loc;
11769
0855e32b
NS		 11770 /* We should have relaxed, unless this is an undefined
11771 weak symbol. */
11772 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
9cb09e33 11773 || bfd_link_dll (info));
0855e32b 11774 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11775 <= globals->root.sgotplt->size);
0855e32b
NS		 11776
11777 outrel.r_addend = 0;
11778 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11779 + globals->root.sgotplt->output_offset
11780 + offplt
11781 + globals->sgotplt_jump_table_size);
b38cadfb 11782
0855e32b
NS		 11783 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11784 sreloc = globals->root.srelplt;
11785 loc = sreloc->contents;
11786 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11787 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11788 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11789
11790 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11791
11792 /* For globals, the first word in the relocation gets
11793 the relocation index and the top bit set, or zero,
11794 if we're binding now. For locals, it gets the
11795 symbol's offset in the tls section. */
99059e56 11796 bfd_put_32 (output_bfd,
0855e32b
NS		 11797 !h ? value - elf_hash_table (info)->tls_sec->vma
11798 : info->flags & DF_BIND_NOW ? 0
11799 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11800 globals->root.sgotplt->contents + offplt
11801 + globals->sgotplt_jump_table_size);
11802
0855e32b 11803 /* Second word in the relocation is always zero. */
99059e56 11804 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11805 globals->root.sgotplt->contents + offplt
11806 + globals->sgotplt_jump_table_size + 4);
0855e32b 11807 }
ba93b8ac
DJ		 11808 if (tls_type & GOT_TLS_GD)
11809 {
11810 if (need_relocs)
11811 {
00a97672 11812 outrel.r_addend = 0;
362d30a1
RS		 11813 outrel.r_offset = (sgot->output_section->vma
11814 + sgot->output_offset
00a97672 11815 + cur_off);
ba93b8ac 11816 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11817
00a97672
RS		 11818 if (globals->use_rel)
11819 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11820 sgot->contents + cur_off);
00a97672 11821
47beaa6a 11822 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11823
11824 if (indx == 0)
11825 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11826 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11827 else
11828 {
00a97672 11829 outrel.r_addend = 0;
ba93b8ac
DJ		 11830 outrel.r_info = ELF32_R_INFO (indx,
11831 R_ARM_TLS_DTPOFF32);
11832 outrel.r_offset += 4;
00a97672
RS		 11833
11834 if (globals->use_rel)
11835 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11836 sgot->contents + cur_off + 4);
00a97672 11837
47beaa6a
RS		 11838 elf32_arm_add_dynreloc (output_bfd, info,
11839 srelgot, &outrel);
ba93b8ac
DJ		 11840 }
11841 }
11842 else
11843 {
11844 /* If we are not emitting relocations for a
11845 general dynamic reference, then we must be in a
11846 static link or an executable link with the
11847 symbol binding locally. Mark it as belonging
11848 to module 1, the executable. */
11849 bfd_put_32 (output_bfd, 1,
362d30a1 11850 sgot->contents + cur_off);
ba93b8ac 11851 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11852 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11853 }
11854
11855 cur_off += 8;
11856 }
11857
11858 if (tls_type & GOT_TLS_IE)
11859 {
11860 if (need_relocs)
11861 {
00a97672
RS		 11862 if (indx == 0)
11863 outrel.r_addend = value - dtpoff_base (info);
11864 else
11865 outrel.r_addend = 0;
362d30a1
RS		 11866 outrel.r_offset = (sgot->output_section->vma
11867 + sgot->output_offset
ba93b8ac
DJ		 11868 + cur_off);
11869 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11870
00a97672
RS		 11871 if (globals->use_rel)
11872 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11873 sgot->contents + cur_off);
ba93b8ac 11874
47beaa6a 11875 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11876 }
11877 else
11878 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11879 sgot->contents + cur_off);
ba93b8ac
DJ		 11880 cur_off += 4;
11881 }
11882
11883 if (h != NULL)
11884 h->got.offset |= 1;
11885 else
11886 local_got_offsets[r_symndx] |= 1;
11887 }
11888
5c5a4843 11889 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
ba93b8ac 11890 off += 8;
0855e32b
NS		 11891 else if (tls_type & GOT_TLS_GDESC)
11892 off = offplt;
11893
11894 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11895 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11896 {
11897 bfd_signed_vma offset;
12352d3f
PB		 11898 /* TLS stubs are arm mode. The original symbol is a
11899 data object, so branch_type is bogus. */
11900 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11901 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11902 = arm_type_of_stub (info, input_section, rel,
11903 st_type, &branch_type,
0855e32b
NS		 11904 (struct elf32_arm_link_hash_entry *)h,
11905 globals->tls_trampoline, globals->root.splt,
11906 input_bfd, sym_name);
11907
11908 if (stub_type != arm_stub_none)
11909 {
11910 struct elf32_arm_stub_hash_entry *stub_entry
11911 = elf32_arm_get_stub_entry
11912 (input_section, globals->root.splt, 0, rel,
11913 globals, stub_type);
11914 offset = (stub_entry->stub_offset
11915 + stub_entry->stub_sec->output_offset
11916 + stub_entry->stub_sec->output_section->vma);
11917 }
11918 else
11919 offset = (globals->root.splt->output_section->vma
11920 + globals->root.splt->output_offset
11921 + globals->tls_trampoline);
11922
11923 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11924 {
11925 unsigned long inst;
b38cadfb
NC		 11926
11927 offset -= (input_section->output_section->vma
11928 + input_section->output_offset
11929 + rel->r_offset + 8);
0855e32b
NS		 11930
11931 inst = offset >> 2;
11932 inst &= 0x00ffffff;
11933 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11934 }
11935 else
11936 {
11937 /* Thumb blx encodes the offset in a complicated
11938 fashion. */
11939 unsigned upper_insn, lower_insn;
11940 unsigned neg;
11941
b38cadfb
NC		 11942 offset -= (input_section->output_section->vma
11943 + input_section->output_offset
0855e32b 11944 + rel->r_offset + 4);
b38cadfb 11945
12352d3f
PB		 11946 if (stub_type != arm_stub_none
11947 && arm_stub_is_thumb (stub_type))
11948 {
11949 lower_insn = 0xd000;
11950 }
11951 else
11952 {
11953 lower_insn = 0xc000;
6a631e86 11954 /* Round up the offset to a word boundary. */
12352d3f
PB		 11955 offset = (offset + 2) & ~2;
11956 }
11957
0855e32b
NS		 11958 neg = offset < 0;
11959 upper_insn = (0xf000
11960 | ((offset >> 12) & 0x3ff)
11961 | (neg << 10));
12352d3f 11962 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11963 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11964 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11965 bfd_put_16 (input_bfd, upper_insn, hit_data);
11966 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11967 return bfd_reloc_ok;
11968 }
11969 }
11970 /* These relocations needs special care, as besides the fact
11971 they point somewhere in .gotplt, the addend must be
11972 adjusted accordingly depending on the type of instruction
6a631e86 11973 we refer to. */
0855e32b
NS		 11974 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11975 {
11976 unsigned long data, insn;
11977 unsigned thumb;
b38cadfb 11978
b627f562 11979 data = bfd_get_signed_32 (input_bfd, hit_data);
0855e32b 11980 thumb = data & 1;
b627f562 11981 data &= ~1ul;
b38cadfb 11982
0855e32b
NS		 11983 if (thumb)
11984 {
11985 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11986 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11987 insn = (insn << 16)
11988 | bfd_get_16 (input_bfd,
11989 contents + rel->r_offset - data + 2);
11990 if ((insn & 0xf800c000) == 0xf000c000)
11991 /* bl/blx */
11992 value = -6;
11993 else if ((insn & 0xffffff00) == 0x4400)
11994 /* add */
11995 value = -5;
11996 else
11997 {
4eca0228 11998 _bfd_error_handler
695344c0 11999 /* xgettext:c-format */
2dcf00ce 12000 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12001 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12002 "referenced by TLS_GOTDESC"),
12003 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12004 "Thumb", insn);
0855e32b
NS		 12005 return bfd_reloc_notsupported;
12006 }
12007 }
12008 else
12009 {
12010 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
12011
12012 switch (insn >> 24)
12013 {
12014 case 0xeb: /* bl */
12015 case 0xfa: /* blx */
12016 value = -4;
12017 break;
12018
12019 case 0xe0: /* add */
12020 value = -8;
12021 break;
b38cadfb 12022
0855e32b 12023 default:
4eca0228 12024 _bfd_error_handler
695344c0 12025 /* xgettext:c-format */
2dcf00ce 12026 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12027 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12028 "referenced by TLS_GOTDESC"),
12029 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12030 "ARM", insn);
0855e32b
NS		 12031 return bfd_reloc_notsupported;
12032 }
12033 }
b38cadfb 12034
0855e32b
NS		 12035 value += ((globals->root.sgotplt->output_section->vma
12036 + globals->root.sgotplt->output_offset + off)
12037 - (input_section->output_section->vma
12038 + input_section->output_offset
12039 + rel->r_offset)
12040 + globals->sgotplt_jump_table_size);
12041 }
12042 else
12043 value = ((globals->root.sgot->output_section->vma
12044 + globals->root.sgot->output_offset + off)
12045 - (input_section->output_section->vma
12046 + input_section->output_offset + rel->r_offset));
ba93b8ac 12047
5c5a4843
CL		 12048 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
12049 r_type == R_ARM_TLS_IE32_FDPIC))
e8b09b87
CL		 12050 {
12051 /* For FDPIC relocations, resolve to the offset of the GOT
12052 entry from the start of GOT. */
12053 bfd_put_32(output_bfd,
12054 globals->root.sgot->output_offset + off,
12055 contents + rel->r_offset);
12056
12057 return bfd_reloc_ok;
12058 }
12059 else
12060 {
12061 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12062 contents, rel->r_offset, value,
12063 rel->r_addend);
12064 }
ba93b8ac
DJ		 12065 }
12066
12067 case R_ARM_TLS_LE32:
3cbc1e5e 12068 if (bfd_link_dll (info))
ba93b8ac 12069 {
4eca0228 12070 _bfd_error_handler
695344c0 12071 /* xgettext:c-format */
2dcf00ce
AM		 12072 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12073 "in shared object"),
12074 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 12075 return bfd_reloc_notsupported;
ba93b8ac
DJ		 12076 }
12077 else
12078 value = tpoff (info, value);
906e58ca 12079
ba93b8ac 12080 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 12081 contents, rel->r_offset, value,
12082 rel->r_addend);
ba93b8ac 12083
319850b4
JB		 12084 case R_ARM_V4BX:
12085 if (globals->fix_v4bx)
845b51d6
PB		 12086 {
12087 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 12088
845b51d6
PB		 12089 /* Ensure that we have a BX instruction. */
12090 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 12091
845b51d6
PB		 12092 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12093 {
12094 /* Branch to veneer. */
12095 bfd_vma glue_addr;
12096 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12097 glue_addr -= input_section->output_section->vma
12098 + input_section->output_offset
12099 + rel->r_offset + 8;
12100 insn = (insn & 0xf0000000) | 0x0a000000
12101 | ((glue_addr >> 2) & 0x00ffffff);
12102 }
12103 else
12104 {
12105 /* Preserve Rm (lowest four bits) and the condition code
12106 (highest four bits). Other bits encode MOV PC,Rm. */
12107 insn = (insn & 0xf000000f) | 0x01a0f000;
12108 }
319850b4 12109
845b51d6
PB		 12110 bfd_put_32 (input_bfd, insn, hit_data);
12111 }
319850b4
JB		 12112 return bfd_reloc_ok;
12113
b6895b4f
PB		 12114 case R_ARM_MOVW_ABS_NC:
12115 case R_ARM_MOVT_ABS:
12116 case R_ARM_MOVW_PREL_NC:
12117 case R_ARM_MOVT_PREL:
92f5d02b
MS		 12118 /* Until we properly support segment-base-relative addressing then
12119 we assume the segment base to be zero, as for the group relocations.
12120 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12121 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12122 case R_ARM_MOVW_BREL_NC:
12123 case R_ARM_MOVW_BREL:
12124 case R_ARM_MOVT_BREL:
b6895b4f
PB		 12125 {
12126 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12127
12128 if (globals->use_rel)
12129 {
12130 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 12131 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12132 }
92f5d02b 12133
b6895b4f 12134 value += signed_addend;
b6895b4f
PB		 12135
12136 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12137 value -= (input_section->output_section->vma
12138 + input_section->output_offset + rel->r_offset);
12139
92f5d02b 12140 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 12141 return bfd_reloc_overflow;
92f5d02b 12142
35fc36a8 12143 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12144 value |= 1;
12145
12146 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 12147 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 12148 value >>= 16;
12149
12150 insn &= 0xfff0f000;
12151 insn |= value & 0xfff;
12152 insn |= (value & 0xf000) << 4;
12153 bfd_put_32 (input_bfd, insn, hit_data);
12154 }
12155 return bfd_reloc_ok;
12156
12157 case R_ARM_THM_MOVW_ABS_NC:
12158 case R_ARM_THM_MOVT_ABS:
12159 case R_ARM_THM_MOVW_PREL_NC:
12160 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 12161 /* Until we properly support segment-base-relative addressing then
12162 we assume the segment base to be zero, as for the above relocations.
12163 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12164 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12165 as R_ARM_THM_MOVT_ABS. */
12166 case R_ARM_THM_MOVW_BREL_NC:
12167 case R_ARM_THM_MOVW_BREL:
12168 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 12169 {
12170 bfd_vma insn;
906e58ca 12171
b6895b4f
PB		 12172 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12173 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12174
12175 if (globals->use_rel)
12176 {
12177 addend = ((insn >> 4) & 0xf000)
12178 | ((insn >> 15) & 0x0800)
12179 | ((insn >> 4) & 0x0700)
07d6d2b8 12180 | (insn & 0x00ff);
39623e12 12181 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12182 }
92f5d02b 12183
b6895b4f 12184 value += signed_addend;
b6895b4f
PB		 12185
12186 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12187 value -= (input_section->output_section->vma
12188 + input_section->output_offset + rel->r_offset);
12189
92f5d02b 12190 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 12191 return bfd_reloc_overflow;
92f5d02b 12192
35fc36a8 12193 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12194 value |= 1;
12195
12196 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 12197 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 12198 value >>= 16;
12199
12200 insn &= 0xfbf08f00;
12201 insn |= (value & 0xf000) << 4;
12202 insn |= (value & 0x0800) << 15;
12203 insn |= (value & 0x0700) << 4;
12204 insn |= (value & 0x00ff);
12205
12206 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12207 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12208 }
12209 return bfd_reloc_ok;
12210
4962c51a
MS		 12211 case R_ARM_ALU_PC_G0_NC:
12212 case R_ARM_ALU_PC_G1_NC:
12213 case R_ARM_ALU_PC_G0:
12214 case R_ARM_ALU_PC_G1:
12215 case R_ARM_ALU_PC_G2:
12216 case R_ARM_ALU_SB_G0_NC:
12217 case R_ARM_ALU_SB_G1_NC:
12218 case R_ARM_ALU_SB_G0:
12219 case R_ARM_ALU_SB_G1:
12220 case R_ARM_ALU_SB_G2:
12221 {
12222 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12223 bfd_vma pc = input_section->output_section->vma
4962c51a 12224 + input_section->output_offset + rel->r_offset;
31a91d61 12225 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12226 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 12227 bfd_vma residual;
12228 bfd_vma g_n;
4962c51a 12229 bfd_signed_vma signed_value;
99059e56
RM		 12230 int group = 0;
12231
12232 /* Determine which group of bits to select. */
12233 switch (r_type)
12234 {
12235 case R_ARM_ALU_PC_G0_NC:
12236 case R_ARM_ALU_PC_G0:
12237 case R_ARM_ALU_SB_G0_NC:
12238 case R_ARM_ALU_SB_G0:
12239 group = 0;
12240 break;
12241
12242 case R_ARM_ALU_PC_G1_NC:
12243 case R_ARM_ALU_PC_G1:
12244 case R_ARM_ALU_SB_G1_NC:
12245 case R_ARM_ALU_SB_G1:
12246 group = 1;
12247 break;
12248
12249 case R_ARM_ALU_PC_G2:
12250 case R_ARM_ALU_SB_G2:
12251 group = 2;
12252 break;
12253
12254 default:
12255 abort ();
12256 }
12257
12258 /* If REL, extract the addend from the insn. If RELA, it will
12259 have already been fetched for us. */
4962c51a 12260 if (globals->use_rel)
99059e56
RM		 12261 {
12262 int negative;
12263 bfd_vma constant = insn & 0xff;
12264 bfd_vma rotation = (insn & 0xf00) >> 8;
12265
12266 if (rotation == 0)
12267 signed_addend = constant;
12268 else
12269 {
12270 /* Compensate for the fact that in the instruction, the
12271 rotation is stored in multiples of 2 bits. */
12272 rotation *= 2;
12273
12274 /* Rotate "constant" right by "rotation" bits. */
12275 signed_addend = (constant >> rotation) |
12276 (constant << (8 * sizeof (bfd_vma) - rotation));
12277 }
12278
12279 /* Determine if the instruction is an ADD or a SUB.
12280 (For REL, this determines the sign of the addend.) */
12281 negative = identify_add_or_sub (insn);
12282 if (negative == 0)
12283 {
4eca0228 12284 _bfd_error_handler
695344c0 12285 /* xgettext:c-format */
90b6238f 12286 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 12287 "are allowed for ALU group relocations"),
12288 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 12289 return bfd_reloc_overflow;
12290 }
12291
12292 signed_addend *= negative;
12293 }
4962c51a
MS		 12294
12295 /* Compute the value (X) to go in the place. */
99059e56
RM		 12296 if (r_type == R_ARM_ALU_PC_G0_NC
12297 || r_type == R_ARM_ALU_PC_G1_NC
12298 || r_type == R_ARM_ALU_PC_G0
12299 || r_type == R_ARM_ALU_PC_G1
12300 || r_type == R_ARM_ALU_PC_G2)
12301 /* PC relative. */
12302 signed_value = value - pc + signed_addend;
12303 else
12304 /* Section base relative. */
12305 signed_value = value - sb + signed_addend;
12306
12307 /* If the target symbol is a Thumb function, then set the
12308 Thumb bit in the address. */
35fc36a8 12309 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 12310 signed_value |= 1;
12311
99059e56
RM		 12312 /* Calculate the value of the relevant G_n, in encoded
12313 constant-with-rotation format. */
b6518b38
NC		 12314 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12315 group, &residual);
99059e56
RM		 12316
12317 /* Check for overflow if required. */
12318 if ((r_type == R_ARM_ALU_PC_G0
12319 || r_type == R_ARM_ALU_PC_G1
12320 || r_type == R_ARM_ALU_PC_G2
12321 || r_type == R_ARM_ALU_SB_G0
12322 || r_type == R_ARM_ALU_SB_G1
12323 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12324 {
4eca0228 12325 _bfd_error_handler
695344c0 12326 /* xgettext:c-format */
90b6238f 12327 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12328 "splitting %#" PRIx64 " for group relocation %s"),
12329 input_bfd, input_section, (uint64_t) rel->r_offset,
12330 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12331 howto->name);
99059e56
RM		 12332 return bfd_reloc_overflow;
12333 }
12334
12335 /* Mask out the value and the ADD/SUB part of the opcode; take care
12336 not to destroy the S bit. */
12337 insn &= 0xff1ff000;
12338
12339 /* Set the opcode according to whether the value to go in the
12340 place is negative. */
12341 if (signed_value < 0)
12342 insn |= 1 << 22;
12343 else
12344 insn |= 1 << 23;
12345
12346 /* Encode the offset. */
12347 insn |= g_n;
4962c51a
MS		 12348
12349 bfd_put_32 (input_bfd, insn, hit_data);
12350 }
12351 return bfd_reloc_ok;
12352
12353 case R_ARM_LDR_PC_G0:
12354 case R_ARM_LDR_PC_G1:
12355 case R_ARM_LDR_PC_G2:
12356 case R_ARM_LDR_SB_G0:
12357 case R_ARM_LDR_SB_G1:
12358 case R_ARM_LDR_SB_G2:
12359 {
12360 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12361 bfd_vma pc = input_section->output_section->vma
4962c51a 12362 + input_section->output_offset + rel->r_offset;
31a91d61 12363 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12364 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12365 bfd_vma residual;
4962c51a 12366 bfd_signed_vma signed_value;
99059e56
RM		 12367 int group = 0;
12368
12369 /* Determine which groups of bits to calculate. */
12370 switch (r_type)
12371 {
12372 case R_ARM_LDR_PC_G0:
12373 case R_ARM_LDR_SB_G0:
12374 group = 0;
12375 break;
12376
12377 case R_ARM_LDR_PC_G1:
12378 case R_ARM_LDR_SB_G1:
12379 group = 1;
12380 break;
12381
12382 case R_ARM_LDR_PC_G2:
12383 case R_ARM_LDR_SB_G2:
12384 group = 2;
12385 break;
12386
12387 default:
12388 abort ();
12389 }
12390
12391 /* If REL, extract the addend from the insn. If RELA, it will
12392 have already been fetched for us. */
4962c51a 12393 if (globals->use_rel)
99059e56
RM		 12394 {
12395 int negative = (insn & (1 << 23)) ? 1 : -1;
12396 signed_addend = negative * (insn & 0xfff);
12397 }
4962c51a
MS		 12398
12399 /* Compute the value (X) to go in the place. */
99059e56
RM		 12400 if (r_type == R_ARM_LDR_PC_G0
12401 || r_type == R_ARM_LDR_PC_G1
12402 || r_type == R_ARM_LDR_PC_G2)
12403 /* PC relative. */
12404 signed_value = value - pc + signed_addend;
12405 else
12406 /* Section base relative. */
12407 signed_value = value - sb + signed_addend;
12408
12409 /* Calculate the value of the relevant G_{n-1} to obtain
12410 the residual at that stage. */
b6518b38
NC		 12411 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12412 group - 1, &residual);
99059e56
RM		 12413
12414 /* Check for overflow. */
12415 if (residual >= 0x1000)
12416 {
4eca0228 12417 _bfd_error_handler
695344c0 12418 /* xgettext:c-format */
90b6238f 12419 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12420 "splitting %#" PRIx64 " for group relocation %s"),
12421 input_bfd, input_section, (uint64_t) rel->r_offset,
12422 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12423 howto->name);
99059e56
RM		 12424 return bfd_reloc_overflow;
12425 }
12426
12427 /* Mask out the value and U bit. */
12428 insn &= 0xff7ff000;
12429
12430 /* Set the U bit if the value to go in the place is non-negative. */
12431 if (signed_value >= 0)
12432 insn |= 1 << 23;
12433
12434 /* Encode the offset. */
12435 insn |= residual;
4962c51a
MS		 12436
12437 bfd_put_32 (input_bfd, insn, hit_data);
12438 }
12439 return bfd_reloc_ok;
12440
12441 case R_ARM_LDRS_PC_G0:
12442 case R_ARM_LDRS_PC_G1:
12443 case R_ARM_LDRS_PC_G2:
12444 case R_ARM_LDRS_SB_G0:
12445 case R_ARM_LDRS_SB_G1:
12446 case R_ARM_LDRS_SB_G2:
12447 {
12448 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12449 bfd_vma pc = input_section->output_section->vma
4962c51a 12450 + input_section->output_offset + rel->r_offset;
31a91d61 12451 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12452 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12453 bfd_vma residual;
4962c51a 12454 bfd_signed_vma signed_value;
99059e56
RM		 12455 int group = 0;
12456
12457 /* Determine which groups of bits to calculate. */
12458 switch (r_type)
12459 {
12460 case R_ARM_LDRS_PC_G0:
12461 case R_ARM_LDRS_SB_G0:
12462 group = 0;
12463 break;
12464
12465 case R_ARM_LDRS_PC_G1:
12466 case R_ARM_LDRS_SB_G1:
12467 group = 1;
12468 break;
12469
12470 case R_ARM_LDRS_PC_G2:
12471 case R_ARM_LDRS_SB_G2:
12472 group = 2;
12473 break;
12474
12475 default:
12476 abort ();
12477 }
12478
12479 /* If REL, extract the addend from the insn. If RELA, it will
12480 have already been fetched for us. */
4962c51a 12481 if (globals->use_rel)
99059e56
RM		 12482 {
12483 int negative = (insn & (1 << 23)) ? 1 : -1;
12484 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12485 }
4962c51a
MS		 12486
12487 /* Compute the value (X) to go in the place. */
99059e56
RM		 12488 if (r_type == R_ARM_LDRS_PC_G0
12489 || r_type == R_ARM_LDRS_PC_G1
12490 || r_type == R_ARM_LDRS_PC_G2)
12491 /* PC relative. */
12492 signed_value = value - pc + signed_addend;
12493 else
12494 /* Section base relative. */
12495 signed_value = value - sb + signed_addend;
12496
12497 /* Calculate the value of the relevant G_{n-1} to obtain
12498 the residual at that stage. */
b6518b38
NC		 12499 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12500 group - 1, &residual);
99059e56
RM		 12501
12502 /* Check for overflow. */
12503 if (residual >= 0x100)
12504 {
4eca0228 12505 _bfd_error_handler
695344c0 12506 /* xgettext:c-format */
90b6238f 12507 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12508 "splitting %#" PRIx64 " for group relocation %s"),
12509 input_bfd, input_section, (uint64_t) rel->r_offset,
12510 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12511 howto->name);
99059e56
RM		 12512 return bfd_reloc_overflow;
12513 }
12514
12515 /* Mask out the value and U bit. */
12516 insn &= 0xff7ff0f0;
12517
12518 /* Set the U bit if the value to go in the place is non-negative. */
12519 if (signed_value >= 0)
12520 insn |= 1 << 23;
12521
12522 /* Encode the offset. */
12523 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12524
12525 bfd_put_32 (input_bfd, insn, hit_data);
12526 }
12527 return bfd_reloc_ok;
12528
12529 case R_ARM_LDC_PC_G0:
12530 case R_ARM_LDC_PC_G1:
12531 case R_ARM_LDC_PC_G2:
12532 case R_ARM_LDC_SB_G0:
12533 case R_ARM_LDC_SB_G1:
12534 case R_ARM_LDC_SB_G2:
12535 {
12536 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12537 bfd_vma pc = input_section->output_section->vma
4962c51a 12538 + input_section->output_offset + rel->r_offset;
31a91d61 12539 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12540 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12541 bfd_vma residual;
4962c51a 12542 bfd_signed_vma signed_value;
99059e56
RM		 12543 int group = 0;
12544
12545 /* Determine which groups of bits to calculate. */
12546 switch (r_type)
12547 {
12548 case R_ARM_LDC_PC_G0:
12549 case R_ARM_LDC_SB_G0:
12550 group = 0;
12551 break;
12552
12553 case R_ARM_LDC_PC_G1:
12554 case R_ARM_LDC_SB_G1:
12555 group = 1;
12556 break;
12557
12558 case R_ARM_LDC_PC_G2:
12559 case R_ARM_LDC_SB_G2:
12560 group = 2;
12561 break;
12562
12563 default:
12564 abort ();
12565 }
12566
12567 /* If REL, extract the addend from the insn. If RELA, it will
12568 have already been fetched for us. */
4962c51a 12569 if (globals->use_rel)
99059e56
RM		 12570 {
12571 int negative = (insn & (1 << 23)) ? 1 : -1;
12572 signed_addend = negative * ((insn & 0xff) << 2);
12573 }
4962c51a
MS		 12574
12575 /* Compute the value (X) to go in the place. */
99059e56
RM		 12576 if (r_type == R_ARM_LDC_PC_G0
12577 || r_type == R_ARM_LDC_PC_G1
12578 || r_type == R_ARM_LDC_PC_G2)
12579 /* PC relative. */
12580 signed_value = value - pc + signed_addend;
12581 else
12582 /* Section base relative. */
12583 signed_value = value - sb + signed_addend;
12584
12585 /* Calculate the value of the relevant G_{n-1} to obtain
12586 the residual at that stage. */
b6518b38
NC		 12587 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12588 group - 1, &residual);
99059e56
RM		 12589
12590 /* Check for overflow. (The absolute value to go in the place must be
12591 divisible by four and, after having been divided by four, must
12592 fit in eight bits.) */
12593 if ((residual & 0x3) != 0 || residual >= 0x400)
12594 {
4eca0228 12595 _bfd_error_handler
695344c0 12596 /* xgettext:c-format */
90b6238f 12597 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12598 "splitting %#" PRIx64 " for group relocation %s"),
12599 input_bfd, input_section, (uint64_t) rel->r_offset,
12600 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12601 howto->name);
99059e56
RM		 12602 return bfd_reloc_overflow;
12603 }
12604
12605 /* Mask out the value and U bit. */
12606 insn &= 0xff7fff00;
12607
12608 /* Set the U bit if the value to go in the place is non-negative. */
12609 if (signed_value >= 0)
12610 insn |= 1 << 23;
12611
12612 /* Encode the offset. */
12613 insn |= residual >> 2;
4962c51a
MS		 12614
12615 bfd_put_32 (input_bfd, insn, hit_data);
12616 }
12617 return bfd_reloc_ok;
12618
72d98d16
MG		 12619 case R_ARM_THM_ALU_ABS_G0_NC:
12620 case R_ARM_THM_ALU_ABS_G1_NC:
12621 case R_ARM_THM_ALU_ABS_G2_NC:
12622 case R_ARM_THM_ALU_ABS_G3_NC:
12623 {
12624 const int shift_array[4] = {0, 8, 16, 24};
12625 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12626 bfd_vma addr = value;
12627 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12628
12629 /* Compute address. */
12630 if (globals->use_rel)
12631 signed_addend = insn & 0xff;
12632 addr += signed_addend;
12633 if (branch_type == ST_BRANCH_TO_THUMB)
12634 addr |= 1;
12635 /* Clean imm8 insn. */
12636 insn &= 0xff00;
12637 /* And update with correct part of address. */
12638 insn |= (addr >> shift) & 0xff;
12639 /* Update insn. */
12640 bfd_put_16 (input_bfd, insn, hit_data);
12641 }
12642
12643 *unresolved_reloc_p = FALSE;
12644 return bfd_reloc_ok;
12645
e8b09b87
CL		 12646 case R_ARM_GOTOFFFUNCDESC:
12647 {
4b24dd1a 12648 if (h == NULL)
e8b09b87
CL		 12649 {
12650 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12651 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12652 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12653 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12654 bfd_vma seg = -1;
12655
12656 if (bfd_link_pic(info) && dynindx == 0)
12657 abort();
12658
12659 /* Resolve relocation. */
12660 bfd_put_32(output_bfd, (offset + sgot->output_offset)
12661 , contents + rel->r_offset);
12662 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12663 not done yet. */
12664 arm_elf_fill_funcdesc(output_bfd, info,
12665 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12666 dynindx, offset, addr, dynreloc_value, seg);
12667 }
12668 else
12669 {
12670 int dynindx;
12671 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12672 bfd_vma addr;
12673 bfd_vma seg = -1;
12674
12675 /* For static binaries, sym_sec can be null. */
12676 if (sym_sec)
12677 {
12678 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12679 addr = dynreloc_value - sym_sec->output_section->vma;
12680 }
12681 else
12682 {
12683 dynindx = 0;
12684 addr = 0;
12685 }
12686
12687 if (bfd_link_pic(info) && dynindx == 0)
12688 abort();
12689
12690 /* This case cannot occur since funcdesc is allocated by
12691 the dynamic loader so we cannot resolve the relocation. */
12692 if (h->dynindx != -1)
12693 abort();
12694
12695 /* Resolve relocation. */
12696 bfd_put_32(output_bfd, (offset + sgot->output_offset),
12697 contents + rel->r_offset);
12698 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12699 arm_elf_fill_funcdesc(output_bfd, info,
12700 &eh->fdpic_cnts.funcdesc_offset,
12701 dynindx, offset, addr, dynreloc_value, seg);
12702 }
12703 }
12704 *unresolved_reloc_p = FALSE;
12705 return bfd_reloc_ok;
12706
12707 case R_ARM_GOTFUNCDESC:
12708 {
4b24dd1a 12709 if (h != NULL)
e8b09b87
CL		 12710 {
12711 Elf_Internal_Rela outrel;
12712
12713 /* Resolve relocation. */
12714 bfd_put_32(output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12715 + sgot->output_offset),
12716 contents + rel->r_offset);
12717 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12718 if(h->dynindx == -1)
12719 {
12720 int dynindx;
12721 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12722 bfd_vma addr;
12723 bfd_vma seg = -1;
12724
12725 /* For static binaries sym_sec can be null. */
12726 if (sym_sec)
12727 {
12728 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12729 addr = dynreloc_value - sym_sec->output_section->vma;
12730 }
12731 else
12732 {
12733 dynindx = 0;
12734 addr = 0;
12735 }
12736
12737 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12738 arm_elf_fill_funcdesc(output_bfd, info,
12739 &eh->fdpic_cnts.funcdesc_offset,
12740 dynindx, offset, addr, dynreloc_value, seg);
12741 }
12742
12743 /* Add a dynamic relocation on GOT entry if not already done. */
12744 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12745 {
12746 if (h->dynindx == -1)
12747 {
12748 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12749 if (h->root.type == bfd_link_hash_undefweak)
12750 bfd_put_32(output_bfd, 0, sgot->contents
12751 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12752 else
12753 bfd_put_32(output_bfd, sgot->output_section->vma
12754 + sgot->output_offset
12755 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12756 sgot->contents
12757 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12758 }
12759 else
12760 {
12761 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12762 }
12763 outrel.r_offset = sgot->output_section->vma
12764 + sgot->output_offset
12765 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12766 outrel.r_addend = 0;
12767 if (h->dynindx == -1 && !bfd_link_pic(info))
12768 if (h->root.type == bfd_link_hash_undefweak)
4b24dd1a 12769 arm_elf_add_rofixup(output_bfd, globals->srofixup, -1);
e8b09b87 12770 else
4b24dd1a
AM		 12771 arm_elf_add_rofixup(output_bfd, globals->srofixup,
12772 outrel.r_offset);
e8b09b87
CL		 12773 else
12774 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12775 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12776 }
12777 }
12778 else
12779 {
12780 /* Such relocation on static function should not have been
12781 emitted by the compiler. */
12782 abort();
12783 }
12784 }
12785 *unresolved_reloc_p = FALSE;
12786 return bfd_reloc_ok;
12787
12788 case R_ARM_FUNCDESC:
12789 {
4b24dd1a 12790 if (h == NULL)
e8b09b87
CL		 12791 {
12792 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12793 Elf_Internal_Rela outrel;
12794 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12795 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12796 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12797 bfd_vma seg = -1;
12798
12799 if (bfd_link_pic(info) && dynindx == 0)
12800 abort();
12801
12802 /* Replace static FUNCDESC relocation with a
12803 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12804 executable. */
12805 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12806 outrel.r_offset = input_section->output_section->vma
12807 + input_section->output_offset + rel->r_offset;
12808 outrel.r_addend = 0;
12809 if (bfd_link_pic(info))
12810 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12811 else
12812 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12813
12814 bfd_put_32 (input_bfd, sgot->output_section->vma
12815 + sgot->output_offset + offset, hit_data);
12816
12817 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12818 arm_elf_fill_funcdesc(output_bfd, info,
12819 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12820 dynindx, offset, addr, dynreloc_value, seg);
12821 }
12822 else
12823 {
12824 if (h->dynindx == -1)
12825 {
12826 int dynindx;
12827 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12828 bfd_vma addr;
12829 bfd_vma seg = -1;
12830 Elf_Internal_Rela outrel;
12831
12832 /* For static binaries sym_sec can be null. */
12833 if (sym_sec)
12834 {
12835 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12836 addr = dynreloc_value - sym_sec->output_section->vma;
12837 }
12838 else
12839 {
12840 dynindx = 0;
12841 addr = 0;
12842 }
12843
12844 if (bfd_link_pic(info) && dynindx == 0)
12845 abort();
12846
12847 /* Replace static FUNCDESC relocation with a
12848 R_ARM_RELATIVE dynamic relocation. */
12849 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12850 outrel.r_offset = input_section->output_section->vma
12851 + input_section->output_offset + rel->r_offset;
12852 outrel.r_addend = 0;
12853 if (bfd_link_pic(info))
12854 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12855 else
12856 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12857
12858 bfd_put_32 (input_bfd, sgot->output_section->vma
12859 + sgot->output_offset + offset, hit_data);
12860
12861 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12862 arm_elf_fill_funcdesc(output_bfd, info,
12863 &eh->fdpic_cnts.funcdesc_offset,
12864 dynindx, offset, addr, dynreloc_value, seg);
12865 }
12866 else
12867 {
12868 Elf_Internal_Rela outrel;
12869
12870 /* Add a dynamic relocation. */
12871 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12872 outrel.r_offset = input_section->output_section->vma
12873 + input_section->output_offset + rel->r_offset;
12874 outrel.r_addend = 0;
12875 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12876 }
12877 }
12878 }
12879 *unresolved_reloc_p = FALSE;
12880 return bfd_reloc_ok;
12881
e5d6e09e
AV		 12882 case R_ARM_THM_BF16:
12883 {
12884 bfd_vma relocation;
12885 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12886 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12887
12888 if (globals->use_rel)
12889 {
12890 bfd_vma immA = (upper_insn & 0x001f);
12891 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12892 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12893 addend = (immA << 12);
12894 addend |= (immB << 2);
12895 addend |= (immC << 1);
12896 addend |= 1;
12897 /* Sign extend. */
e6f65e75 12898 signed_addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
e5d6e09e
AV		 12899 }
12900
e6f65e75 12901 relocation = value + signed_addend;
e5d6e09e
AV		 12902 relocation -= (input_section->output_section->vma
12903 + input_section->output_offset
12904 + rel->r_offset);
12905
12906 /* Put RELOCATION back into the insn. */
12907 {
12908 bfd_vma immA = (relocation & 0x0001f000) >> 12;
12909 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12910 bfd_vma immC = (relocation & 0x00000002) >> 1;
12911
12912 upper_insn = (upper_insn & 0xffe0) | immA;
12913 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12914 }
12915
12916 /* Put the relocated value back in the object file: */
12917 bfd_put_16 (input_bfd, upper_insn, hit_data);
12918 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12919
12920 return bfd_reloc_ok;
12921 }
12922
1889da70
AV		 12923 case R_ARM_THM_BF12:
12924 {
12925 bfd_vma relocation;
12926 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12927 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12928
12929 if (globals->use_rel)
12930 {
12931 bfd_vma immA = (upper_insn & 0x0001);
12932 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12933 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12934 addend = (immA << 12);
12935 addend |= (immB << 2);
12936 addend |= (immC << 1);
12937 addend |= 1;
12938 /* Sign extend. */
12939 addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
e6f65e75 12940 signed_addend = addend;
1889da70
AV		 12941 }
12942
e6f65e75 12943 relocation = value + signed_addend;
1889da70
AV		 12944 relocation -= (input_section->output_section->vma
12945 + input_section->output_offset
12946 + rel->r_offset);
12947
12948 /* Put RELOCATION back into the insn. */
12949 {
12950 bfd_vma immA = (relocation & 0x00001000) >> 12;
12951 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12952 bfd_vma immC = (relocation & 0x00000002) >> 1;
12953
12954 upper_insn = (upper_insn & 0xfffe) | immA;
12955 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12956 }
12957
12958 /* Put the relocated value back in the object file: */
12959 bfd_put_16 (input_bfd, upper_insn, hit_data);
12960 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12961
12962 return bfd_reloc_ok;
12963 }
12964
1caf72a5
AV		 12965 case R_ARM_THM_BF18:
12966 {
12967 bfd_vma relocation;
12968 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12969 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12970
12971 if (globals->use_rel)
12972 {
12973 bfd_vma immA = (upper_insn & 0x007f);
12974 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12975 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12976 addend = (immA << 12);
12977 addend |= (immB << 2);
12978 addend |= (immC << 1);
12979 addend |= 1;
12980 /* Sign extend. */
12981 addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
e6f65e75 12982 signed_addend = addend;
1caf72a5
AV		 12983 }
12984
e6f65e75 12985 relocation = value + signed_addend;
1caf72a5
AV		 12986 relocation -= (input_section->output_section->vma
12987 + input_section->output_offset
12988 + rel->r_offset);
12989
12990 /* Put RELOCATION back into the insn. */
12991 {
12992 bfd_vma immA = (relocation & 0x0007f000) >> 12;
12993 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12994 bfd_vma immC = (relocation & 0x00000002) >> 1;
12995
12996 upper_insn = (upper_insn & 0xff80) | immA;
12997 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12998 }
12999
13000 /* Put the relocated value back in the object file: */
13001 bfd_put_16 (input_bfd, upper_insn, hit_data);
13002 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13003
13004 return bfd_reloc_ok;
13005 }
13006
252b5132
RH		 13007 default:
13008 return bfd_reloc_notsupported;
13009 }
13010}
13011
98c1d4aa
NC		 13012/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13013static void
07d6d2b8
AM		 13014arm_add_to_rel (bfd * abfd,
13015 bfd_byte * address,
57e8b36a 13016 reloc_howto_type * howto,
07d6d2b8 13017 bfd_signed_vma increment)
98c1d4aa 13018{
98c1d4aa
NC		 13019 bfd_signed_vma addend;
13020
bd97cb95
DJ		 13021 if (howto->type == R_ARM_THM_CALL
13022 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 13023 {
9a5aca8c
AM		 13024 int upper_insn, lower_insn;
13025 int upper, lower;
98c1d4aa 13026
9a5aca8c
AM		 13027 upper_insn = bfd_get_16 (abfd, address);
13028 lower_insn = bfd_get_16 (abfd, address + 2);
13029 upper = upper_insn & 0x7ff;
13030 lower = lower_insn & 0x7ff;
13031
13032 addend = (upper << 12) | (lower << 1);
ddda4409 13033 addend += increment;
9a5aca8c 13034 addend >>= 1;
98c1d4aa 13035
9a5aca8c
AM		 13036 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
13037 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
13038
dc810e39
AM		 13039 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
13040 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 13041 }
13042 else
13043 {
07d6d2b8 13044 bfd_vma contents;
9a5aca8c
AM		 13045
13046 contents = bfd_get_32 (abfd, address);
13047
13048 /* Get the (signed) value from the instruction. */
13049 addend = contents & howto->src_mask;
13050 if (addend & ((howto->src_mask + 1) >> 1))
13051 {
13052 bfd_signed_vma mask;
13053
13054 mask = -1;
13055 mask &= ~ howto->src_mask;
13056 addend |= mask;
13057 }
13058
13059 /* Add in the increment, (which is a byte value). */
13060 switch (howto->type)
13061 {
13062 default:
13063 addend += increment;
13064 break;
13065
13066 case R_ARM_PC24:
c6596c5e 13067 case R_ARM_PLT32:
5b5bb741
PB		 13068 case R_ARM_CALL:
13069 case R_ARM_JUMP24:
9a5aca8c 13070 addend <<= howto->size;
dc810e39 13071 addend += increment;
9a5aca8c
AM		 13072
13073 /* Should we check for overflow here ? */
13074
13075 /* Drop any undesired bits. */
13076 addend >>= howto->rightshift;
13077 break;
13078 }
13079
13080 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
13081
13082 bfd_put_32 (abfd, contents, address);
ddda4409 13083 }
98c1d4aa 13084}
252b5132 13085
ba93b8ac
DJ		 13086#define IS_ARM_TLS_RELOC(R_TYPE) \
13087 ((R_TYPE) == R_ARM_TLS_GD32 \
5c5a4843 13088 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
ba93b8ac
DJ		 13089 || (R_TYPE) == R_ARM_TLS_LDO32 \
13090 || (R_TYPE) == R_ARM_TLS_LDM32 \
5c5a4843 13091 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
ba93b8ac
DJ		 13092 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13093 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13094 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13095 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b 13096 || (R_TYPE) == R_ARM_TLS_IE32 \
5c5a4843 13097 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
0855e32b
NS		 13098 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13099
13100/* Specific set of relocations for the gnu tls dialect. */
13101#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13102 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13103 || (R_TYPE) == R_ARM_TLS_CALL \
13104 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13105 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13106 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 13107
252b5132 13108/* Relocate an ARM ELF section. */
906e58ca 13109
b34976b6 13110static bfd_boolean
07d6d2b8 13111elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 13112 struct bfd_link_info * info,
07d6d2b8
AM		 13113 bfd * input_bfd,
13114 asection * input_section,
13115 bfd_byte * contents,
13116 Elf_Internal_Rela * relocs,
13117 Elf_Internal_Sym * local_syms,
13118 asection ** local_sections)
252b5132 13119{
b34976b6
AM		 13120 Elf_Internal_Shdr *symtab_hdr;
13121 struct elf_link_hash_entry **sym_hashes;
13122 Elf_Internal_Rela *rel;
13123 Elf_Internal_Rela *relend;
13124 const char *name;
b32d3aa2 13125 struct elf32_arm_link_hash_table * globals;
252b5132 13126
4e7fd91e 13127 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13128 if (globals == NULL)
13129 return FALSE;
b491616a 13130
0ffa91dd 13131 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 13132 sym_hashes = elf_sym_hashes (input_bfd);
13133
13134 rel = relocs;
13135 relend = relocs + input_section->reloc_count;
13136 for (; rel < relend; rel++)
13137 {
07d6d2b8
AM		 13138 int r_type;
13139 reloc_howto_type * howto;
13140 unsigned long r_symndx;
13141 Elf_Internal_Sym * sym;
13142 asection * sec;
252b5132 13143 struct elf_link_hash_entry * h;
07d6d2b8
AM		 13144 bfd_vma relocation;
13145 bfd_reloc_status_type r;
13146 arelent bfd_reloc;
13147 char sym_type;
13148 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 13149 char *error_message = NULL;
f21f3fe0 13150
252b5132 13151 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 13152 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 13153 r_type = arm_real_reloc_type (globals, r_type);
252b5132 13154
ba96a88f 13155 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 13156 || r_type == R_ARM_GNU_VTINHERIT)
13157 continue;
252b5132 13158
47aeb64c
NC		 13159 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
13160
13161 if (howto == NULL)
13162 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 13163
252b5132
RH		 13164 h = NULL;
13165 sym = NULL;
13166 sec = NULL;
9b485d32 13167
252b5132
RH		 13168 if (r_symndx < symtab_hdr->sh_info)
13169 {
13170 sym = local_syms + r_symndx;
ba93b8ac 13171 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 13172 sec = local_sections[r_symndx];
ffcb4889
NS		 13173
13174 /* An object file might have a reference to a local
13175 undefined symbol. This is a daft object file, but we
13176 should at least do something about it. V4BX & NONE
13177 relocations do not use the symbol and are explicitly
77b4f08f
TS		 13178 allowed to use the undefined symbol, so allow those.
13179 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 13180 if (r_type != R_ARM_V4BX
13181 && r_type != R_ARM_NONE
77b4f08f 13182 && r_symndx != STN_UNDEF
ffcb4889
NS		 13183 && bfd_is_und_section (sec)
13184 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 13185 (*info->callbacks->undefined_symbol)
13186 (info, bfd_elf_string_from_elf_section
13187 (input_bfd, symtab_hdr->sh_link, sym->st_name),
13188 input_bfd, input_section,
13189 rel->r_offset, TRUE);
b38cadfb 13190
4e7fd91e 13191 if (globals->use_rel)
f8df10f4 13192 {
4e7fd91e
PB		 13193 relocation = (sec->output_section->vma
13194 + sec->output_offset
13195 + sym->st_value);
0e1862bb 13196 if (!bfd_link_relocatable (info)
ab96bf03
AM		 13197 && (sec->flags & SEC_MERGE)
13198 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 13199 {
4e7fd91e
PB		 13200 asection *msec;
13201 bfd_vma addend, value;
13202
39623e12 13203 switch (r_type)
4e7fd91e 13204 {
39623e12
PB		 13205 case R_ARM_MOVW_ABS_NC:
13206 case R_ARM_MOVT_ABS:
13207 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13208 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13209 addend = (addend ^ 0x8000) - 0x8000;
13210 break;
f8df10f4 13211
39623e12
PB		 13212 case R_ARM_THM_MOVW_ABS_NC:
13213 case R_ARM_THM_MOVT_ABS:
13214 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13215 << 16;
13216 value |= bfd_get_16 (input_bfd,
13217 contents + rel->r_offset + 2);
13218 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13219 | ((value & 0x04000000) >> 15);
13220 addend = (addend ^ 0x8000) - 0x8000;
13221 break;
f8df10f4 13222
39623e12
PB		 13223 default:
13224 if (howto->rightshift
13225 || (howto->src_mask & (howto->src_mask + 1)))
13226 {
4eca0228 13227 _bfd_error_handler
695344c0 13228 /* xgettext:c-format */
2dcf00ce
AM		 13229 (_("%pB(%pA+%#" PRIx64 "): "
13230 "%s relocation against SEC_MERGE section"),
39623e12 13231 input_bfd, input_section,
2dcf00ce 13232 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 13233 return FALSE;
13234 }
13235
13236 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13237
13238 /* Get the (signed) value from the instruction. */
13239 addend = value & howto->src_mask;
13240 if (addend & ((howto->src_mask + 1) >> 1))
13241 {
13242 bfd_signed_vma mask;
13243
13244 mask = -1;
13245 mask &= ~ howto->src_mask;
13246 addend |= mask;
13247 }
13248 break;
4e7fd91e 13249 }
39623e12 13250
4e7fd91e
PB		 13251 msec = sec;
13252 addend =
13253 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13254 - relocation;
13255 addend += msec->output_section->vma + msec->output_offset;
39623e12 13256
cc643b88 13257 /* Cases here must match those in the preceding
39623e12
PB		 13258 switch statement. */
13259 switch (r_type)
13260 {
13261 case R_ARM_MOVW_ABS_NC:
13262 case R_ARM_MOVT_ABS:
13263 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13264 | (addend & 0xfff);
13265 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13266 break;
13267
13268 case R_ARM_THM_MOVW_ABS_NC:
13269 case R_ARM_THM_MOVT_ABS:
13270 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13271 | (addend & 0xff) | ((addend & 0x0800) << 15);
13272 bfd_put_16 (input_bfd, value >> 16,
13273 contents + rel->r_offset);
13274 bfd_put_16 (input_bfd, value,
13275 contents + rel->r_offset + 2);
13276 break;
13277
13278 default:
13279 value = (value & ~ howto->dst_mask)
13280 | (addend & howto->dst_mask);
13281 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13282 break;
13283 }
f8df10f4 13284 }
f8df10f4 13285 }
4e7fd91e
PB		 13286 else
13287 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 13288 }
13289 else
13290 {
62d887d4 13291 bfd_boolean warned, ignored;
560e09e9 13292
b2a8e766
AM		 13293 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13294 r_symndx, symtab_hdr, sym_hashes,
13295 h, sec, relocation,
62d887d4 13296 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 13297
13298 sym_type = h->type;
252b5132
RH		 13299 }
13300
dbaa2011 13301 if (sec != NULL && discarded_section (sec))
e4067dbb 13302 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 13303 rel, 1, relend, howto, 0, contents);
ab96bf03 13304
0e1862bb 13305 if (bfd_link_relocatable (info))
ab96bf03
AM		 13306 {
13307 /* This is a relocatable link. We don't have to change
13308 anything, unless the reloc is against a section symbol,
13309 in which case we have to adjust according to where the
13310 section symbol winds up in the output section. */
13311 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13312 {
13313 if (globals->use_rel)
13314 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13315 howto, (bfd_signed_vma) sec->output_offset);
13316 else
13317 rel->r_addend += sec->output_offset;
13318 }
13319 continue;
13320 }
13321
252b5132
RH		 13322 if (h != NULL)
13323 name = h->root.root.string;
13324 else
13325 {
13326 name = (bfd_elf_string_from_elf_section
13327 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13328 if (name == NULL || *name == '\0')
fd361982 13329 name = bfd_section_name (sec);
252b5132 13330 }
f21f3fe0 13331
cf35638d 13332 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 13333 && r_type != R_ARM_NONE
13334 && (h == NULL
13335 || h->root.type == bfd_link_hash_defined
13336 || h->root.type == bfd_link_hash_defweak)
13337 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13338 {
4eca0228 13339 _bfd_error_handler
ba93b8ac 13340 ((sym_type == STT_TLS
695344c0 13341 /* xgettext:c-format */
2dcf00ce 13342 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 13343 /* xgettext:c-format */
2dcf00ce 13344 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 13345 input_bfd,
13346 input_section,
2dcf00ce 13347 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 13348 howto->name,
13349 name);
13350 }
13351
0855e32b 13352 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 13353 done, i.e., the relaxation produced the final output we want,
13354 and we won't let anybody mess with it. Also, we have to do
13355 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 13356 both in relaxed and non-relaxed cases. */
39d911fc
TP		 13357 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13358 || (IS_ARM_TLS_GNU_RELOC (r_type)
13359 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13360 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13361 & GOT_TLS_GDESC)))
13362 {
13363 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13364 contents, rel, h == NULL);
13365 /* This may have been marked unresolved because it came from
13366 a shared library. But we've just dealt with that. */
13367 unresolved_reloc = 0;
13368 }
13369 else
13370 r = bfd_reloc_continue;
b38cadfb 13371
39d911fc
TP		 13372 if (r == bfd_reloc_continue)
13373 {
13374 unsigned char branch_type =
13375 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13376 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13377
13378 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13379 input_section, contents, rel,
13380 relocation, info, sec, name,
13381 sym_type, branch_type, h,
13382 &unresolved_reloc,
13383 &error_message);
13384 }
0945cdfd
DJ		 13385
13386 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13387 because such sections are not SEC_ALLOC and thus ld.so will
13388 not process them. */
13389 if (unresolved_reloc
99059e56
RM		 13390 && !((input_section->flags & SEC_DEBUGGING) != 0
13391 && h->def_dynamic)
1d5316ab
AM		 13392 && _bfd_elf_section_offset (output_bfd, info, input_section,
13393 rel->r_offset) != (bfd_vma) -1)
0945cdfd 13394 {
4eca0228 13395 _bfd_error_handler
695344c0 13396 /* xgettext:c-format */
2dcf00ce
AM		 13397 (_("%pB(%pA+%#" PRIx64 "): "
13398 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 13399 input_bfd,
13400 input_section,
2dcf00ce 13401 (uint64_t) rel->r_offset,
843fe662
L		 13402 howto->name,
13403 h->root.root.string);
0945cdfd
DJ		 13404 return FALSE;
13405 }
252b5132
RH		 13406
13407 if (r != bfd_reloc_ok)
13408 {
252b5132
RH		 13409 switch (r)
13410 {
13411 case bfd_reloc_overflow:
cf919dfd
PB		 13412 /* If the overflowing reloc was to an undefined symbol,
13413 we have already printed one error message and there
13414 is no point complaining again. */
1a72702b
AM		 13415 if (!h || h->root.type != bfd_link_hash_undefined)
13416 (*info->callbacks->reloc_overflow)
13417 (info, (h ? &h->root : NULL), name, howto->name,
13418 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13419 break;
13420
13421 case bfd_reloc_undefined:
1a72702b
AM		 13422 (*info->callbacks->undefined_symbol)
13423 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 13424 break;
13425
13426 case bfd_reloc_outofrange:
f2a9dd69 13427 error_message = _("out of range");
252b5132
RH		 13428 goto common_error;
13429
13430 case bfd_reloc_notsupported:
f2a9dd69 13431 error_message = _("unsupported relocation");
252b5132
RH		 13432 goto common_error;
13433
13434 case bfd_reloc_dangerous:
f2a9dd69 13435 /* error_message should already be set. */
252b5132
RH		 13436 goto common_error;
13437
13438 default:
f2a9dd69 13439 error_message = _("unknown error");
8029a119 13440 /* Fall through. */
252b5132
RH		 13441
13442 common_error:
f2a9dd69 13443 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 13444 (*info->callbacks->reloc_dangerous)
13445 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13446 break;
13447 }
13448 }
13449 }
13450
b34976b6 13451 return TRUE;
252b5132
RH		 13452}
13453
91d6fa6a 13454/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 13455 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 13456 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 13457 maintaining that condition). */
13458
13459static void
13460add_unwind_table_edit (arm_unwind_table_edit **head,
13461 arm_unwind_table_edit **tail,
13462 arm_unwind_edit_type type,
13463 asection *linked_section,
91d6fa6a 13464 unsigned int tindex)
2468f9c9 13465{
21d799b5
NC		 13466 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13467 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 13468
2468f9c9
PB		 13469 new_edit->type = type;
13470 new_edit->linked_section = linked_section;
91d6fa6a 13471 new_edit->index = tindex;
b38cadfb 13472
91d6fa6a 13473 if (tindex > 0)
2468f9c9
PB		 13474 {
13475 new_edit->next = NULL;
13476
13477 if (*tail)
13478 (*tail)->next = new_edit;
13479
13480 (*tail) = new_edit;
13481
13482 if (!*head)
13483 (*head) = new_edit;
13484 }
13485 else
13486 {
13487 new_edit->next = *head;
13488
13489 if (!*tail)
13490 *tail = new_edit;
13491
13492 *head = new_edit;
13493 }
13494}
13495
13496static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13497
13498/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13499static void
13500adjust_exidx_size(asection *exidx_sec, int adjust)
13501{
13502 asection *out_sec;
13503
13504 if (!exidx_sec->rawsize)
13505 exidx_sec->rawsize = exidx_sec->size;
13506
fd361982 13507 bfd_set_section_size (exidx_sec, exidx_sec->size + adjust);
2468f9c9
PB		 13508 out_sec = exidx_sec->output_section;
13509 /* Adjust size of output section. */
fd361982 13510 bfd_set_section_size (out_sec, out_sec->size +adjust);
2468f9c9
PB		 13511}
13512
13513/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13514static void
13515insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
13516{
13517 struct _arm_elf_section_data *exidx_arm_data;
13518
13519 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13520 add_unwind_table_edit (
13521 &exidx_arm_data->u.exidx.unwind_edit_list,
13522 &exidx_arm_data->u.exidx.unwind_edit_tail,
13523 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13524
491d01d3
YU		 13525 exidx_arm_data->additional_reloc_count++;
13526
2468f9c9
PB		 13527 adjust_exidx_size(exidx_sec, 8);
13528}
13529
13530/* Scan .ARM.exidx tables, and create a list describing edits which should be
13531 made to those tables, such that:
b38cadfb 13532
2468f9c9
PB		 13533 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13534 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 13535 codes which have been inlined into the index).
2468f9c9 13536
85fdf906
AH		 13537 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13538
2468f9c9 13539 The edits are applied when the tables are written
b38cadfb 13540 (in elf32_arm_write_section). */
2468f9c9
PB		 13541
13542bfd_boolean
13543elf32_arm_fix_exidx_coverage (asection **text_section_order,
13544 unsigned int num_text_sections,
85fdf906
AH		 13545 struct bfd_link_info *info,
13546 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 13547{
13548 bfd *inp;
13549 unsigned int last_second_word = 0, i;
13550 asection *last_exidx_sec = NULL;
13551 asection *last_text_sec = NULL;
13552 int last_unwind_type = -1;
13553
13554 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13555 text sections. */
c72f2fb2 13556 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 13557 {
13558 asection *sec;
b38cadfb 13559
2468f9c9 13560 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 13561 {
2468f9c9
PB		 13562 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13563 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 13564
dec9d5df 13565 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 13566 continue;
b38cadfb 13567
2468f9c9
PB		 13568 if (elf_sec->linked_to)
13569 {
13570 Elf_Internal_Shdr *linked_hdr
99059e56 13571 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 13572 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 13573 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 13574
13575 if (linked_sec_arm_data == NULL)
99059e56 13576 continue;
2468f9c9
PB		 13577
13578 /* Link this .ARM.exidx section back from the text section it
99059e56 13579 describes. */
2468f9c9
PB		 13580 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13581 }
13582 }
13583 }
13584
13585 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13586 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 13587 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 13588
13589 for (i = 0; i < num_text_sections; i++)
13590 {
13591 asection *sec = text_section_order[i];
13592 asection *exidx_sec;
13593 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13594 struct _arm_elf_section_data *exidx_arm_data;
13595 bfd_byte *contents = NULL;
13596 int deleted_exidx_bytes = 0;
13597 bfd_vma j;
13598 arm_unwind_table_edit *unwind_edit_head = NULL;
13599 arm_unwind_table_edit *unwind_edit_tail = NULL;
13600 Elf_Internal_Shdr *hdr;
13601 bfd *ibfd;
13602
13603 if (arm_data == NULL)
99059e56 13604 continue;
2468f9c9
PB		 13605
13606 exidx_sec = arm_data->u.text.arm_exidx_sec;
13607 if (exidx_sec == NULL)
13608 {
13609 /* Section has no unwind data. */
13610 if (last_unwind_type == 0 || !last_exidx_sec)
13611 continue;
13612
13613 /* Ignore zero sized sections. */
13614 if (sec->size == 0)
13615 continue;
13616
13617 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13618 last_unwind_type = 0;
13619 continue;
13620 }
13621
22a8f80e
PB		 13622 /* Skip /DISCARD/ sections. */
13623 if (bfd_is_abs_section (exidx_sec->output_section))
13624 continue;
13625
2468f9c9
PB		 13626 hdr = &elf_section_data (exidx_sec)->this_hdr;
13627 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 13628 continue;
b38cadfb 13629
2468f9c9
PB		 13630 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13631 if (exidx_arm_data == NULL)
99059e56 13632 continue;
b38cadfb 13633
2468f9c9 13634 ibfd = exidx_sec->owner;
b38cadfb 13635
2468f9c9
PB		 13636 if (hdr->contents != NULL)
13637 contents = hdr->contents;
13638 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13639 /* An error? */
13640 continue;
13641
ac06903d
YU		 13642 if (last_unwind_type > 0)
13643 {
13644 unsigned int first_word = bfd_get_32 (ibfd, contents);
13645 /* Add cantunwind if first unwind item does not match section
13646 start. */
13647 if (first_word != sec->vma)
13648 {
13649 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13650 last_unwind_type = 0;
13651 }
13652 }
13653
2468f9c9
PB		 13654 for (j = 0; j < hdr->sh_size; j += 8)
13655 {
13656 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13657 int unwind_type;
13658 int elide = 0;
13659
13660 /* An EXIDX_CANTUNWIND entry. */
13661 if (second_word == 1)
13662 {
13663 if (last_unwind_type == 0)
13664 elide = 1;
13665 unwind_type = 0;
13666 }
13667 /* Inlined unwinding data. Merge if equal to previous. */
13668 else if ((second_word & 0x80000000) != 0)
13669 {
85fdf906
AH		 13670 if (merge_exidx_entries
13671 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 13672 elide = 1;
13673 unwind_type = 1;
13674 last_second_word = second_word;
13675 }
13676 /* Normal table entry. In theory we could merge these too,
13677 but duplicate entries are likely to be much less common. */
13678 else
13679 unwind_type = 2;
13680
491d01d3 13681 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 13682 {
13683 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13684 DELETE_EXIDX_ENTRY, NULL, j / 8);
13685
13686 deleted_exidx_bytes += 8;
13687 }
13688
13689 last_unwind_type = unwind_type;
13690 }
13691
13692 /* Free contents if we allocated it ourselves. */
13693 if (contents != hdr->contents)
99059e56 13694 free (contents);
2468f9c9
PB		 13695
13696 /* Record edits to be applied later (in elf32_arm_write_section). */
13697 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13698 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 13699
2468f9c9
PB		 13700 if (deleted_exidx_bytes > 0)
13701 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
13702
13703 last_exidx_sec = exidx_sec;
13704 last_text_sec = sec;
13705 }
13706
13707 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 13708 if (!bfd_link_relocatable (info) && last_exidx_sec
13709 && last_unwind_type != 0)
2468f9c9
PB		 13710 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13711
13712 return TRUE;
13713}
13714
3e6b1042
DJ		 13715static bfd_boolean
13716elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13717 bfd *ibfd, const char *name)
13718{
13719 asection *sec, *osec;
13720
3d4d4302 13721 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 13722 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13723 return TRUE;
13724
13725 osec = sec->output_section;
13726 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13727 return TRUE;
13728
13729 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13730 sec->output_offset, sec->size))
13731 return FALSE;
13732
13733 return TRUE;
13734}
13735
13736static bfd_boolean
13737elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13738{
13739 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 13740 asection *sec, *osec;
3e6b1042 13741
4dfe6ac6
NC		 13742 if (globals == NULL)
13743 return FALSE;
13744
3e6b1042
DJ		 13745 /* Invoke the regular ELF backend linker to do all the work. */
13746 if (!bfd_elf_final_link (abfd, info))
13747 return FALSE;
13748
fe33d2fa
CL		 13749 /* Process stub sections (eg BE8 encoding, ...). */
13750 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 13751 unsigned int i;
cdb21a0a
NS		 13752 for (i=0; i<htab->top_id; i++)
13753 {
13754 sec = htab->stub_group[i].stub_sec;
13755 /* Only process it once, in its link_sec slot. */
13756 if (sec && i == htab->stub_group[i].link_sec->id)
13757 {
13758 osec = sec->output_section;
13759 elf32_arm_write_section (abfd, info, sec, sec->contents);
13760 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13761 sec->output_offset, sec->size))
13762 return FALSE;
13763 }
fe33d2fa 13764 }
fe33d2fa 13765
3e6b1042
DJ		 13766 /* Write out any glue sections now that we have created all the
13767 stubs. */
13768 if (globals->bfd_of_glue_owner != NULL)
13769 {
13770 if (! elf32_arm_output_glue_section (info, abfd,
13771 globals->bfd_of_glue_owner,
13772 ARM2THUMB_GLUE_SECTION_NAME))
13773 return FALSE;
13774
13775 if (! elf32_arm_output_glue_section (info, abfd,
13776 globals->bfd_of_glue_owner,
13777 THUMB2ARM_GLUE_SECTION_NAME))
13778 return FALSE;
13779
13780 if (! elf32_arm_output_glue_section (info, abfd,
13781 globals->bfd_of_glue_owner,
13782 VFP11_ERRATUM_VENEER_SECTION_NAME))
13783 return FALSE;
13784
a504d23a
LA		 13785 if (! elf32_arm_output_glue_section (info, abfd,
13786 globals->bfd_of_glue_owner,
13787 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13788 return FALSE;
13789
3e6b1042
DJ		 13790 if (! elf32_arm_output_glue_section (info, abfd,
13791 globals->bfd_of_glue_owner,
13792 ARM_BX_GLUE_SECTION_NAME))
13793 return FALSE;
13794 }
13795
13796 return TRUE;
13797}
13798
5968a7b8
NC		 13799/* Return a best guess for the machine number based on the attributes. */
13800
13801static unsigned int
13802bfd_arm_get_mach_from_attributes (bfd * abfd)
13803{
13804 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13805
13806 switch (arch)
13807 {
c0c468d5 13808 case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
5968a7b8
NC		 13809 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13810 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13811 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13812
13813 case TAG_CPU_ARCH_V5TE:
13814 {
13815 char * name;
13816
13817 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13818 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13819
13820 if (name)
13821 {
13822 if (strcmp (name, "IWMMXT2") == 0)
13823 return bfd_mach_arm_iWMMXt2;
13824
13825 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13826 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13827
13828 if (strcmp (name, "XSCALE") == 0)
13829 {
13830 int wmmx;
13831
13832 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13833 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13834 switch (wmmx)
13835 {
13836 case 1: return bfd_mach_arm_iWMMXt;
13837 case 2: return bfd_mach_arm_iWMMXt2;
13838 default: return bfd_mach_arm_XScale;
13839 }
13840 }
5968a7b8
NC		 13841 }
13842
13843 return bfd_mach_arm_5TE;
13844 }
13845
c0c468d5
TP		 13846 case TAG_CPU_ARCH_V5TEJ:
13847 return bfd_mach_arm_5TEJ;
13848 case TAG_CPU_ARCH_V6:
13849 return bfd_mach_arm_6;
13850 case TAG_CPU_ARCH_V6KZ:
13851 return bfd_mach_arm_6KZ;
13852 case TAG_CPU_ARCH_V6T2:
13853 return bfd_mach_arm_6T2;
13854 case TAG_CPU_ARCH_V6K:
13855 return bfd_mach_arm_6K;
13856 case TAG_CPU_ARCH_V7:
13857 return bfd_mach_arm_7;
13858 case TAG_CPU_ARCH_V6_M:
13859 return bfd_mach_arm_6M;
13860 case TAG_CPU_ARCH_V6S_M:
13861 return bfd_mach_arm_6SM;
13862 case TAG_CPU_ARCH_V7E_M:
13863 return bfd_mach_arm_7EM;
13864 case TAG_CPU_ARCH_V8:
13865 return bfd_mach_arm_8;
13866 case TAG_CPU_ARCH_V8R:
13867 return bfd_mach_arm_8R;
13868 case TAG_CPU_ARCH_V8M_BASE:
13869 return bfd_mach_arm_8M_BASE;
13870 case TAG_CPU_ARCH_V8M_MAIN:
13871 return bfd_mach_arm_8M_MAIN;
031254f2
AV		 13872 case TAG_CPU_ARCH_V8_1M_MAIN:
13873 return bfd_mach_arm_8_1M_MAIN;
c0c468d5 13874
5968a7b8 13875 default:
c0c468d5
TP		 13876 /* Force entry to be added for any new known Tag_CPU_arch value. */
13877 BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
13878
13879 /* Unknown Tag_CPU_arch value. */
5968a7b8
NC		 13880 return bfd_mach_arm_unknown;
13881 }
13882}
13883
c178919b
NC		 13884/* Set the right machine number. */
13885
13886static bfd_boolean
57e8b36a 13887elf32_arm_object_p (bfd *abfd)
c178919b 13888{
5a6c6817 13889 unsigned int mach;
57e8b36a 13890
5a6c6817 13891 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13892
5968a7b8
NC		 13893 if (mach == bfd_mach_arm_unknown)
13894 {
13895 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13896 mach = bfd_mach_arm_ep9312;
13897 else
13898 mach = bfd_arm_get_mach_from_attributes (abfd);
13899 }
c178919b 13900
5968a7b8 13901 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13902 return TRUE;
13903}
13904
fc830a83 13905/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13906
b34976b6 13907static bfd_boolean
57e8b36a 13908elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13909{
13910 if (elf_flags_init (abfd)
13911 && elf_elfheader (abfd)->e_flags != flags)
13912 {
fc830a83
NC		 13913 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13914 {
fd2ec330 13915 if (flags & EF_ARM_INTERWORK)
4eca0228 13916 _bfd_error_handler
90b6238f 13917 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13918 abfd);
fc830a83 13919 else
d003868e 13920 _bfd_error_handler
90b6238f 13921 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13922 abfd);
fc830a83 13923 }
252b5132
RH		 13924 }
13925 else
13926 {
13927 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13928 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13929 }
13930
b34976b6 13931 return TRUE;
252b5132
RH		 13932}
13933
fc830a83 13934/* Copy backend specific data from one object module to another. */
9b485d32 13935
b34976b6 13936static bfd_boolean
57e8b36a 13937elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13938{
13939 flagword in_flags;
13940 flagword out_flags;
13941
0ffa91dd 13942 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13943 return TRUE;
252b5132 13944
fc830a83 13945 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13946 out_flags = elf_elfheader (obfd)->e_flags;
13947
fc830a83
NC		 13948 if (elf_flags_init (obfd)
13949 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13950 && in_flags != out_flags)
252b5132 13951 {
252b5132 13952 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13953 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13954 return FALSE;
252b5132
RH		 13955
13956 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13957 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13958 return FALSE;
252b5132
RH		 13959
13960 /* If the src and dest have different interworking flags
99059e56 13961 then turn off the interworking bit. */
fd2ec330 13962 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13963 {
fd2ec330 13964 if (out_flags & EF_ARM_INTERWORK)
d003868e 13965 _bfd_error_handler
90b6238f 13966 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 13967 obfd, ibfd);
252b5132 13968
fd2ec330 13969 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13970 }
1006ba19
PB		 13971
13972 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13973 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13974 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13975 }
13976
13977 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13978 elf_flags_init (obfd) = TRUE;
252b5132 13979
e2349352 13980 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13981}
13982
13983/* Values for Tag_ABI_PCS_R9_use. */
13984enum
13985{
13986 AEABI_R9_V6,
13987 AEABI_R9_SB,
13988 AEABI_R9_TLS,
13989 AEABI_R9_unused
13990};
13991
13992/* Values for Tag_ABI_PCS_RW_data. */
13993enum
13994{
13995 AEABI_PCS_RW_data_absolute,
13996 AEABI_PCS_RW_data_PCrel,
13997 AEABI_PCS_RW_data_SBrel,
13998 AEABI_PCS_RW_data_unused
13999};
14000
14001/* Values for Tag_ABI_enum_size. */
14002enum
14003{
14004 AEABI_enum_unused,
14005 AEABI_enum_short,
14006 AEABI_enum_wide,
14007 AEABI_enum_forced_wide
14008};
14009
104d59d1
JM		 14010/* Determine whether an object attribute tag takes an integer, a
14011 string or both. */
906e58ca 14012
104d59d1
JM		 14013static int
14014elf32_arm_obj_attrs_arg_type (int tag)
14015{
14016 if (tag == Tag_compatibility)
3483fe2e 14017 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 14018 else if (tag == Tag_nodefaults)
3483fe2e
AS		 14019 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
14020 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
14021 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 14022 else if (tag < 32)
3483fe2e 14023 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 14024 else
3483fe2e 14025 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 14026}
14027
5aa6ff7c
AS		 14028/* The ABI defines that Tag_conformance should be emitted first, and that
14029 Tag_nodefaults should be second (if either is defined). This sets those
14030 two positions, and bumps up the position of all the remaining tags to
14031 compensate. */
14032static int
14033elf32_arm_obj_attrs_order (int num)
14034{
3de4a297 14035 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 14036 return Tag_conformance;
3de4a297 14037 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 14038 return Tag_nodefaults;
14039 if ((num - 2) < Tag_nodefaults)
14040 return num - 2;
14041 if ((num - 1) < Tag_conformance)
14042 return num - 1;
14043 return num;
14044}
14045
e8b36cd1
JM		 14046/* Attribute numbers >=64 (mod 128) can be safely ignored. */
14047static bfd_boolean
14048elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
14049{
14050 if ((tag & 127) < 64)
14051 {
14052 _bfd_error_handler
90b6238f 14053 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 14054 abfd, tag);
14055 bfd_set_error (bfd_error_bad_value);
14056 return FALSE;
14057 }
14058 else
14059 {
14060 _bfd_error_handler
90b6238f 14061 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 14062 abfd, tag);
14063 return TRUE;
14064 }
14065}
14066
91e22acd
AS		 14067/* Read the architecture from the Tag_also_compatible_with attribute, if any.
14068 Returns -1 if no architecture could be read. */
14069
14070static int
14071get_secondary_compatible_arch (bfd *abfd)
14072{
14073 obj_attribute *attr =
14074 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
14075
14076 /* Note: the tag and its argument below are uleb128 values, though
14077 currently-defined values fit in one byte for each. */
14078 if (attr->s
14079 && attr->s[0] == Tag_CPU_arch
14080 && (attr->s[1] & 128) != 128
14081 && attr->s[2] == 0)
14082 return attr->s[1];
14083
14084 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14085 return -1;
14086}
14087
14088/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14089 The tag is removed if ARCH is -1. */
14090
8e79c3df 14091static void
91e22acd 14092set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 14093{
91e22acd
AS		 14094 obj_attribute *attr =
14095 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 14096
91e22acd
AS		 14097 if (arch == -1)
14098 {
14099 attr->s = NULL;
14100 return;
8e79c3df 14101 }
91e22acd
AS		 14102
14103 /* Note: the tag and its argument below are uleb128 values, though
14104 currently-defined values fit in one byte for each. */
14105 if (!attr->s)
21d799b5 14106 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 14107 attr->s[0] = Tag_CPU_arch;
14108 attr->s[1] = arch;
14109 attr->s[2] = '\0';
8e79c3df
CM		 14110}
14111
91e22acd
AS		 14112/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14113 into account. */
14114
14115static int
14116tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
14117 int newtag, int secondary_compat)
8e79c3df 14118{
91e22acd
AS		 14119#define T(X) TAG_CPU_ARCH_##X
14120 int tagl, tagh, result;
14121 const int v6t2[] =
14122 {
14123 T(V6T2), /* PRE_V4. */
14124 T(V6T2), /* V4. */
14125 T(V6T2), /* V4T. */
14126 T(V6T2), /* V5T. */
14127 T(V6T2), /* V5TE. */
14128 T(V6T2), /* V5TEJ. */
14129 T(V6T2), /* V6. */
14130 T(V7), /* V6KZ. */
14131 T(V6T2) /* V6T2. */
14132 };
14133 const int v6k[] =
14134 {
14135 T(V6K), /* PRE_V4. */
14136 T(V6K), /* V4. */
14137 T(V6K), /* V4T. */
14138 T(V6K), /* V5T. */
14139 T(V6K), /* V5TE. */
14140 T(V6K), /* V5TEJ. */
14141 T(V6K), /* V6. */
14142 T(V6KZ), /* V6KZ. */
14143 T(V7), /* V6T2. */
14144 T(V6K) /* V6K. */
14145 };
14146 const int v7[] =
14147 {
14148 T(V7), /* PRE_V4. */
14149 T(V7), /* V4. */
14150 T(V7), /* V4T. */
14151 T(V7), /* V5T. */
14152 T(V7), /* V5TE. */
14153 T(V7), /* V5TEJ. */
14154 T(V7), /* V6. */
14155 T(V7), /* V6KZ. */
14156 T(V7), /* V6T2. */
14157 T(V7), /* V6K. */
14158 T(V7) /* V7. */
14159 };
14160 const int v6_m[] =
14161 {
07d6d2b8
AM		 14162 -1, /* PRE_V4. */
14163 -1, /* V4. */
91e22acd
AS		 14164 T(V6K), /* V4T. */
14165 T(V6K), /* V5T. */
14166 T(V6K), /* V5TE. */
14167 T(V6K), /* V5TEJ. */
14168 T(V6K), /* V6. */
14169 T(V6KZ), /* V6KZ. */
14170 T(V7), /* V6T2. */
14171 T(V6K), /* V6K. */
14172 T(V7), /* V7. */
14173 T(V6_M) /* V6_M. */
14174 };
14175 const int v6s_m[] =
14176 {
07d6d2b8
AM		 14177 -1, /* PRE_V4. */
14178 -1, /* V4. */
91e22acd
AS		 14179 T(V6K), /* V4T. */
14180 T(V6K), /* V5T. */
14181 T(V6K), /* V5TE. */
14182 T(V6K), /* V5TEJ. */
14183 T(V6K), /* V6. */
14184 T(V6KZ), /* V6KZ. */
14185 T(V7), /* V6T2. */
14186 T(V6K), /* V6K. */
14187 T(V7), /* V7. */
14188 T(V6S_M), /* V6_M. */
14189 T(V6S_M) /* V6S_M. */
14190 };
9e3c6df6
PB		 14191 const int v7e_m[] =
14192 {
07d6d2b8
AM		 14193 -1, /* PRE_V4. */
14194 -1, /* V4. */
9e3c6df6
PB		 14195 T(V7E_M), /* V4T. */
14196 T(V7E_M), /* V5T. */
14197 T(V7E_M), /* V5TE. */
14198 T(V7E_M), /* V5TEJ. */
14199 T(V7E_M), /* V6. */
14200 T(V7E_M), /* V6KZ. */
14201 T(V7E_M), /* V6T2. */
14202 T(V7E_M), /* V6K. */
14203 T(V7E_M), /* V7. */
14204 T(V7E_M), /* V6_M. */
14205 T(V7E_M), /* V6S_M. */
14206 T(V7E_M) /* V7E_M. */
14207 };
bca38921
MGD		 14208 const int v8[] =
14209 {
14210 T(V8), /* PRE_V4. */
14211 T(V8), /* V4. */
14212 T(V8), /* V4T. */
14213 T(V8), /* V5T. */
14214 T(V8), /* V5TE. */
14215 T(V8), /* V5TEJ. */
14216 T(V8), /* V6. */
14217 T(V8), /* V6KZ. */
14218 T(V8), /* V6T2. */
14219 T(V8), /* V6K. */
14220 T(V8), /* V7. */
14221 T(V8), /* V6_M. */
14222 T(V8), /* V6S_M. */
14223 T(V8), /* V7E_M. */
14224 T(V8) /* V8. */
14225 };
bff0500d
TP		 14226 const int v8r[] =
14227 {
14228 T(V8R), /* PRE_V4. */
14229 T(V8R), /* V4. */
14230 T(V8R), /* V4T. */
14231 T(V8R), /* V5T. */
14232 T(V8R), /* V5TE. */
14233 T(V8R), /* V5TEJ. */
14234 T(V8R), /* V6. */
14235 T(V8R), /* V6KZ. */
14236 T(V8R), /* V6T2. */
14237 T(V8R), /* V6K. */
14238 T(V8R), /* V7. */
14239 T(V8R), /* V6_M. */
14240 T(V8R), /* V6S_M. */
14241 T(V8R), /* V7E_M. */
14242 T(V8), /* V8. */
14243 T(V8R), /* V8R. */
14244 };
2fd158eb
TP		 14245 const int v8m_baseline[] =
14246 {
14247 -1, /* PRE_V4. */
14248 -1, /* V4. */
14249 -1, /* V4T. */
14250 -1, /* V5T. */
14251 -1, /* V5TE. */
14252 -1, /* V5TEJ. */
14253 -1, /* V6. */
14254 -1, /* V6KZ. */
14255 -1, /* V6T2. */
14256 -1, /* V6K. */
14257 -1, /* V7. */
14258 T(V8M_BASE), /* V6_M. */
14259 T(V8M_BASE), /* V6S_M. */
14260 -1, /* V7E_M. */
14261 -1, /* V8. */
bff0500d 14262 -1, /* V8R. */
2fd158eb
TP		 14263 T(V8M_BASE) /* V8-M BASELINE. */
14264 };
14265 const int v8m_mainline[] =
14266 {
14267 -1, /* PRE_V4. */
14268 -1, /* V4. */
14269 -1, /* V4T. */
14270 -1, /* V5T. */
14271 -1, /* V5TE. */
14272 -1, /* V5TEJ. */
14273 -1, /* V6. */
14274 -1, /* V6KZ. */
14275 -1, /* V6T2. */
14276 -1, /* V6K. */
14277 T(V8M_MAIN), /* V7. */
14278 T(V8M_MAIN), /* V6_M. */
14279 T(V8M_MAIN), /* V6S_M. */
14280 T(V8M_MAIN), /* V7E_M. */
14281 -1, /* V8. */
bff0500d 14282 -1, /* V8R. */
2fd158eb
TP		 14283 T(V8M_MAIN), /* V8-M BASELINE. */
14284 T(V8M_MAIN) /* V8-M MAINLINE. */
14285 };
031254f2
AV		 14286 const int v8_1m_mainline[] =
14287 {
14288 -1, /* PRE_V4. */
14289 -1, /* V4. */
14290 -1, /* V4T. */
14291 -1, /* V5T. */
14292 -1, /* V5TE. */
14293 -1, /* V5TEJ. */
14294 -1, /* V6. */
14295 -1, /* V6KZ. */
14296 -1, /* V6T2. */
14297 -1, /* V6K. */
14298 T(V8_1M_MAIN), /* V7. */
14299 T(V8_1M_MAIN), /* V6_M. */
14300 T(V8_1M_MAIN), /* V6S_M. */
14301 T(V8_1M_MAIN), /* V7E_M. */
14302 -1, /* V8. */
14303 -1, /* V8R. */
14304 T(V8_1M_MAIN), /* V8-M BASELINE. */
14305 T(V8_1M_MAIN), /* V8-M MAINLINE. */
14306 -1, /* Unused (18). */
14307 -1, /* Unused (19). */
14308 -1, /* Unused (20). */
14309 T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
14310 };
91e22acd
AS		 14311 const int v4t_plus_v6_m[] =
14312 {
14313 -1, /* PRE_V4. */
14314 -1, /* V4. */
14315 T(V4T), /* V4T. */
14316 T(V5T), /* V5T. */
14317 T(V5TE), /* V5TE. */
14318 T(V5TEJ), /* V5TEJ. */
14319 T(V6), /* V6. */
14320 T(V6KZ), /* V6KZ. */
14321 T(V6T2), /* V6T2. */
14322 T(V6K), /* V6K. */
14323 T(V7), /* V7. */
14324 T(V6_M), /* V6_M. */
14325 T(V6S_M), /* V6S_M. */
9e3c6df6 14326 T(V7E_M), /* V7E_M. */
bca38921 14327 T(V8), /* V8. */
bff0500d 14328 -1, /* V8R. */
2fd158eb
TP		 14329 T(V8M_BASE), /* V8-M BASELINE. */
14330 T(V8M_MAIN), /* V8-M MAINLINE. */
031254f2
AV		 14331 -1, /* Unused (18). */
14332 -1, /* Unused (19). */
14333 -1, /* Unused (20). */
14334 T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
91e22acd
AS		 14335 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14336 };
14337 const int *comb[] =
14338 {
14339 v6t2,
14340 v6k,
14341 v7,
14342 v6_m,
14343 v6s_m,
9e3c6df6 14344 v7e_m,
bca38921 14345 v8,
bff0500d 14346 v8r,
2fd158eb
TP		 14347 v8m_baseline,
14348 v8m_mainline,
031254f2
AV		 14349 NULL,
14350 NULL,
14351 NULL,
14352 v8_1m_mainline,
91e22acd
AS		 14353 /* Pseudo-architecture. */
14354 v4t_plus_v6_m
14355 };
14356
14357 /* Check we've not got a higher architecture than we know about. */
14358
9e3c6df6 14359 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 14360 {
90b6238f 14361 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 14362 return -1;
14363 }
14364
14365 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14366
14367 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14368 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14369 oldtag = T(V4T_PLUS_V6_M);
14370
14371 /* And override the new tag if we have a Tag_also_compatible_with on the
14372 input. */
14373
14374 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14375 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14376 newtag = T(V4T_PLUS_V6_M);
14377
14378 tagl = (oldtag < newtag) ? oldtag : newtag;
14379 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14380
14381 /* Architectures before V6KZ add features monotonically. */
14382 if (tagh <= TAG_CPU_ARCH_V6KZ)
14383 return result;
14384
4ed7ed8d 14385 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 14386
14387 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14388 as the canonical version. */
14389 if (result == T(V4T_PLUS_V6_M))
14390 {
14391 result = T(V4T);
14392 *secondary_compat_out = T(V6_M);
14393 }
14394 else
14395 *secondary_compat_out = -1;
14396
14397 if (result == -1)
14398 {
90b6238f 14399 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 14400 ibfd, oldtag, newtag);
14401 return -1;
14402 }
14403
14404 return result;
14405#undef T
8e79c3df
CM		 14406}
14407
ac56ee8f
MGD		 14408/* Query attributes object to see if integer divide instructions may be
14409 present in an object. */
14410static bfd_boolean
14411elf32_arm_attributes_accept_div (const obj_attribute *attr)
14412{
14413 int arch = attr[Tag_CPU_arch].i;
14414 int profile = attr[Tag_CPU_arch_profile].i;
14415
14416 switch (attr[Tag_DIV_use].i)
14417 {
14418 case 0:
14419 /* Integer divide allowed if instruction contained in archetecture. */
14420 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14421 return TRUE;
14422 else if (arch >= TAG_CPU_ARCH_V7E_M)
14423 return TRUE;
14424 else
14425 return FALSE;
14426
14427 case 1:
14428 /* Integer divide explicitly prohibited. */
14429 return FALSE;
14430
14431 default:
14432 /* Unrecognised case - treat as allowing divide everywhere. */
14433 case 2:
14434 /* Integer divide allowed in ARM state. */
14435 return TRUE;
14436 }
14437}
14438
14439/* Query attributes object to see if integer divide instructions are
14440 forbidden to be in the object. This is not the inverse of
14441 elf32_arm_attributes_accept_div. */
14442static bfd_boolean
14443elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14444{
14445 return attr[Tag_DIV_use].i == 1;
14446}
14447
ee065d83
PB		 14448/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14449 are conflicting attributes. */
906e58ca 14450
ee065d83 14451static bfd_boolean
50e03d47 14452elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 14453{
50e03d47 14454 bfd *obfd = info->output_bfd;
104d59d1
JM		 14455 obj_attribute *in_attr;
14456 obj_attribute *out_attr;
ee065d83
PB		 14457 /* Some tags have 0 = don't care, 1 = strong requirement,
14458 2 = weak requirement. */
91e22acd 14459 static const int order_021[3] = {0, 2, 1};
ee065d83 14460 int i;
91e22acd 14461 bfd_boolean result = TRUE;
9274e9de 14462 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 14463
3e6b1042
DJ		 14464 /* Skip the linker stubs file. This preserves previous behavior
14465 of accepting unknown attributes in the first input file - but
14466 is that a bug? */
14467 if (ibfd->flags & BFD_LINKER_CREATED)
14468 return TRUE;
14469
9274e9de
TG		 14470 /* Skip any input that hasn't attribute section.
14471 This enables to link object files without attribute section with
14472 any others. */
14473 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14474 return TRUE;
14475
104d59d1 14476 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 14477 {
14478 /* This is the first object. Copy the attributes. */
104d59d1 14479 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 14480
cd21e546
MGD		 14481 out_attr = elf_known_obj_attributes_proc (obfd);
14482
004ae526
PB		 14483 /* Use the Tag_null value to indicate the attributes have been
14484 initialized. */
cd21e546 14485 out_attr[0].i = 1;
004ae526 14486
cd21e546
MGD		 14487 /* We do not output objects with Tag_MPextension_use_legacy - we move
14488 the attribute's value to Tag_MPextension_use. */
14489 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14490 {
14491 if (out_attr[Tag_MPextension_use].i != 0
14492 && out_attr[Tag_MPextension_use_legacy].i
99059e56 14493 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 14494 {
14495 _bfd_error_handler
871b3ab2 14496 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 14497 "Tag_MPextension_use attributes"), ibfd);
14498 result = FALSE;
14499 }
14500
14501 out_attr[Tag_MPextension_use] =
14502 out_attr[Tag_MPextension_use_legacy];
14503 out_attr[Tag_MPextension_use_legacy].type = 0;
14504 out_attr[Tag_MPextension_use_legacy].i = 0;
14505 }
14506
14507 return result;
ee065d83
PB		 14508 }
14509
104d59d1
JM		 14510 in_attr = elf_known_obj_attributes_proc (ibfd);
14511 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 14512 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14513 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14514 {
5c294fee
TG		 14515 /* Ignore mismatches if the object doesn't use floating point or is
14516 floating point ABI independent. */
14517 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14518 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14519 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 14520 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 14521 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14522 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 14523 {
14524 _bfd_error_handler
871b3ab2 14525 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 14526 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14527 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 14528 result = FALSE;
ee065d83
PB		 14529 }
14530 }
14531
3de4a297 14532 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 14533 {
14534 /* Merge this attribute with existing attributes. */
14535 switch (i)
14536 {
14537 case Tag_CPU_raw_name:
14538 case Tag_CPU_name:
6a631e86 14539 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 14540 break;
14541
14542 case Tag_ABI_optimization_goals:
14543 case Tag_ABI_FP_optimization_goals:
14544 /* Use the first value seen. */
14545 break;
14546
14547 case Tag_CPU_arch:
91e22acd
AS		 14548 {
14549 int secondary_compat = -1, secondary_compat_out = -1;
14550 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 14551 int arch_attr;
14552 static const char *name_table[] =
14553 {
91e22acd
AS		 14554 /* These aren't real CPU names, but we can't guess
14555 that from the architecture version alone. */
14556 "Pre v4",
14557 "ARM v4",
14558 "ARM v4T",
14559 "ARM v5T",
14560 "ARM v5TE",
14561 "ARM v5TEJ",
14562 "ARM v6",
14563 "ARM v6KZ",
14564 "ARM v6T2",
14565 "ARM v6K",
14566 "ARM v7",
14567 "ARM v6-M",
bca38921 14568 "ARM v6S-M",
2fd158eb
TP		 14569 "ARM v8",
14570 "",
14571 "ARM v8-M.baseline",
14572 "ARM v8-M.mainline",
91e22acd
AS		 14573 };
14574
14575 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14576 secondary_compat = get_secondary_compatible_arch (ibfd);
14577 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 14578 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14579 &secondary_compat_out,
14580 in_attr[i].i,
14581 secondary_compat);
14582
14583 /* Return with error if failed to merge. */
14584 if (arch_attr == -1)
14585 return FALSE;
14586
14587 out_attr[i].i = arch_attr;
14588
91e22acd
AS		 14589 set_secondary_compatible_arch (obfd, secondary_compat_out);
14590
14591 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14592 if (out_attr[i].i == saved_out_attr)
14593 ; /* Leave the names alone. */
14594 else if (out_attr[i].i == in_attr[i].i)
14595 {
14596 /* The output architecture has been changed to match the
14597 input architecture. Use the input names. */
14598 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14599 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14600 : NULL;
14601 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14602 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14603 : NULL;
14604 }
14605 else
14606 {
14607 out_attr[Tag_CPU_name].s = NULL;
14608 out_attr[Tag_CPU_raw_name].s = NULL;
14609 }
14610
14611 /* If we still don't have a value for Tag_CPU_name,
14612 make one up now. Tag_CPU_raw_name remains blank. */
14613 if (out_attr[Tag_CPU_name].s == NULL
14614 && out_attr[i].i < ARRAY_SIZE (name_table))
14615 out_attr[Tag_CPU_name].s =
14616 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14617 }
14618 break;
14619
ee065d83
PB		 14620 case Tag_ARM_ISA_use:
14621 case Tag_THUMB_ISA_use:
ee065d83 14622 case Tag_WMMX_arch:
91e22acd
AS		 14623 case Tag_Advanced_SIMD_arch:
14624 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 14625 case Tag_ABI_FP_rounding:
ee065d83
PB		 14626 case Tag_ABI_FP_exceptions:
14627 case Tag_ABI_FP_user_exceptions:
14628 case Tag_ABI_FP_number_model:
75375b3e 14629 case Tag_FP_HP_extension:
91e22acd
AS		 14630 case Tag_CPU_unaligned_access:
14631 case Tag_T2EE_use:
91e22acd 14632 case Tag_MPextension_use:
a7ad558c 14633 case Tag_MVE_arch:
ee065d83
PB		 14634 /* Use the largest value specified. */
14635 if (in_attr[i].i > out_attr[i].i)
14636 out_attr[i].i = in_attr[i].i;
14637 break;
14638
75375b3e 14639 case Tag_ABI_align_preserved:
91e22acd
AS		 14640 case Tag_ABI_PCS_RO_data:
14641 /* Use the smallest value specified. */
14642 if (in_attr[i].i < out_attr[i].i)
14643 out_attr[i].i = in_attr[i].i;
14644 break;
14645
75375b3e 14646 case Tag_ABI_align_needed:
91e22acd 14647 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 14648 && (in_attr[Tag_ABI_align_preserved].i == 0
14649 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 14650 {
91e22acd
AS		 14651 /* This error message should be enabled once all non-conformant
14652 binaries in the toolchain have had the attributes set
14653 properly.
ee065d83 14654 _bfd_error_handler
871b3ab2 14655 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 14656 obfd, ibfd);
14657 result = FALSE; */
ee065d83 14658 }
91e22acd
AS		 14659 /* Fall through. */
14660 case Tag_ABI_FP_denormal:
14661 case Tag_ABI_PCS_GOT_use:
14662 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14663 value if greater than 2 (for future-proofing). */
14664 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14665 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14666 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 14667 out_attr[i].i = in_attr[i].i;
14668 break;
91e22acd 14669
75375b3e
MGD		 14670 case Tag_Virtualization_use:
14671 /* The virtualization tag effectively stores two bits of
14672 information: the intended use of TrustZone (in bit 0), and the
14673 intended use of Virtualization (in bit 1). */
14674 if (out_attr[i].i == 0)
14675 out_attr[i].i = in_attr[i].i;
14676 else if (in_attr[i].i != 0
14677 && in_attr[i].i != out_attr[i].i)
14678 {
14679 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14680 out_attr[i].i = 3;
14681 else
14682 {
14683 _bfd_error_handler
871b3ab2
AM		 14684 (_("error: %pB: unable to merge virtualization attributes "
14685 "with %pB"),
75375b3e
MGD		 14686 obfd, ibfd);
14687 result = FALSE;
14688 }
14689 }
14690 break;
91e22acd
AS		 14691
14692 case Tag_CPU_arch_profile:
14693 if (out_attr[i].i != in_attr[i].i)
14694 {
14695 /* 0 will merge with anything.
14696 'A' and 'S' merge to 'A'.
14697 'R' and 'S' merge to 'R'.
99059e56 14698 'M' and 'A|R|S' is an error. */
91e22acd
AS		 14699 if (out_attr[i].i == 0
14700 || (out_attr[i].i == 'S'
14701 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14702 out_attr[i].i = in_attr[i].i;
14703 else if (in_attr[i].i == 0
14704 || (in_attr[i].i == 'S'
14705 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 14706 ; /* Do nothing. */
91e22acd
AS		 14707 else
14708 {
14709 _bfd_error_handler
90b6238f 14710 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 14711 ibfd,
14712 in_attr[i].i ? in_attr[i].i : '0',
14713 out_attr[i].i ? out_attr[i].i : '0');
14714 result = FALSE;
14715 }
14716 }
14717 break;
15afaa63
TP		 14718
14719 case Tag_DSP_extension:
14720 /* No need to change output value if any of:
14721 - pre (<=) ARMv5T input architecture (do not have DSP)
14722 - M input profile not ARMv7E-M and do not have DSP. */
14723 if (in_attr[Tag_CPU_arch].i <= 3
14724 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14725 && in_attr[Tag_CPU_arch].i != 13
14726 && in_attr[i].i == 0))
14727 ; /* Do nothing. */
14728 /* Output value should be 0 if DSP part of architecture, ie.
14729 - post (>=) ARMv5te architecture output
14730 - A, R or S profile output or ARMv7E-M output architecture. */
14731 else if (out_attr[Tag_CPU_arch].i >= 4
14732 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14733 || out_attr[Tag_CPU_arch_profile].i == 'R'
14734 || out_attr[Tag_CPU_arch_profile].i == 'S'
14735 || out_attr[Tag_CPU_arch].i == 13))
14736 out_attr[i].i = 0;
14737 /* Otherwise, DSP instructions are added and not part of output
14738 architecture. */
14739 else
14740 out_attr[i].i = 1;
14741 break;
14742
75375b3e 14743 case Tag_FP_arch:
62f3b8c8 14744 {
4547cb56
NC		 14745 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14746 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14747 when it's 0. It might mean absence of FP hardware if
99654aaf 14748 Tag_FP_arch is zero. */
4547cb56 14749
a715796b 14750#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 14751 static const struct
14752 {
14753 int ver;
14754 int regs;
bca38921 14755 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 14756 {
14757 {0, 0},
14758 {1, 16},
14759 {2, 16},
14760 {3, 32},
14761 {3, 16},
14762 {4, 32},
bca38921 14763 {4, 16},
a715796b
TG		 14764 {8, 32},
14765 {8, 16}
62f3b8c8
PB		 14766 };
14767 int ver;
14768 int regs;
14769 int newval;
14770
4547cb56
NC		 14771 /* If the output has no requirement about FP hardware,
14772 follow the requirement of the input. */
14773 if (out_attr[i].i == 0)
14774 {
4ec192e6
RE		 14775 /* This assert is still reasonable, we shouldn't
14776 produce the suspicious build attribute
14777 combination (See below for in_attr). */
4547cb56
NC		 14778 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14779 out_attr[i].i = in_attr[i].i;
14780 out_attr[Tag_ABI_HardFP_use].i
14781 = in_attr[Tag_ABI_HardFP_use].i;
14782 break;
14783 }
14784 /* If the input has no requirement about FP hardware, do
14785 nothing. */
14786 else if (in_attr[i].i == 0)
14787 {
4ec192e6
RE		 14788 /* We used to assert that Tag_ABI_HardFP_use was
14789 zero here, but we should never assert when
14790 consuming an object file that has suspicious
14791 build attributes. The single precision variant
14792 of 'no FP architecture' is still 'no FP
14793 architecture', so we just ignore the tag in this
14794 case. */
4547cb56
NC		 14795 break;
14796 }
14797
14798 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 14799 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 14800
14801 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14802 do nothing. */
14803 if (in_attr[Tag_ABI_HardFP_use].i == 0
14804 && out_attr[Tag_ABI_HardFP_use].i == 0)
14805 ;
14806 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 14807 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 14808 else if (in_attr[Tag_ABI_HardFP_use].i
14809 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 14810 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 14811
14812 /* Now we can handle Tag_FP_arch. */
14813
bca38921
MGD		 14814 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14815 pick the biggest. */
14816 if (in_attr[i].i >= VFP_VERSION_COUNT
14817 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 14818 {
14819 out_attr[i] = in_attr[i];
14820 break;
14821 }
14822 /* The output uses the superset of input features
14823 (ISA version) and registers. */
14824 ver = vfp_versions[in_attr[i].i].ver;
14825 if (ver < vfp_versions[out_attr[i].i].ver)
14826 ver = vfp_versions[out_attr[i].i].ver;
14827 regs = vfp_versions[in_attr[i].i].regs;
14828 if (regs < vfp_versions[out_attr[i].i].regs)
14829 regs = vfp_versions[out_attr[i].i].regs;
14830 /* This assumes all possible supersets are also a valid
99059e56 14831 options. */
bca38921 14832 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 14833 {
14834 if (regs == vfp_versions[newval].regs
14835 && ver == vfp_versions[newval].ver)
14836 break;
14837 }
14838 out_attr[i].i = newval;
14839 }
b1cc4aeb 14840 break;
ee065d83
PB		 14841 case Tag_PCS_config:
14842 if (out_attr[i].i == 0)
14843 out_attr[i].i = in_attr[i].i;
b6009aca 14844 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14845 {
14846 /* It's sometimes ok to mix different configs, so this is only
99059e56 14847 a warning. */
ee065d83 14848 _bfd_error_handler
90b6238f 14849 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14850 }
14851 break;
14852 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14853 if (in_attr[i].i != out_attr[i].i
14854 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14855 && in_attr[i].i != AEABI_R9_unused)
14856 {
14857 _bfd_error_handler
90b6238f 14858 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14859 result = FALSE;
ee065d83
PB		 14860 }
14861 if (out_attr[i].i == AEABI_R9_unused)
14862 out_attr[i].i = in_attr[i].i;
14863 break;
14864 case Tag_ABI_PCS_RW_data:
14865 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14866 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14867 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14868 {
14869 _bfd_error_handler
871b3ab2 14870 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14871 ibfd);
91e22acd 14872 result = FALSE;
ee065d83
PB		 14873 }
14874 /* Use the smallest value specified. */
14875 if (in_attr[i].i < out_attr[i].i)
14876 out_attr[i].i = in_attr[i].i;
14877 break;
ee065d83 14878 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14879 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14880 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14881 {
14882 _bfd_error_handler
871b3ab2 14883 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14884 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14885 }
a9dc9481 14886 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14887 out_attr[i].i = in_attr[i].i;
14888 break;
ee065d83
PB		 14889 case Tag_ABI_enum_size:
14890 if (in_attr[i].i != AEABI_enum_unused)
14891 {
14892 if (out_attr[i].i == AEABI_enum_unused
14893 || out_attr[i].i == AEABI_enum_forced_wide)
14894 {
14895 /* The existing object is compatible with anything.
14896 Use whatever requirements the new object has. */
14897 out_attr[i].i = in_attr[i].i;
14898 }
14899 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14900 && out_attr[i].i != in_attr[i].i
0ffa91dd 14901 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14902 {
91e22acd 14903 static const char *aeabi_enum_names[] =
bf21ed78 14904 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14905 const char *in_name =
14906 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14907 ? aeabi_enum_names[in_attr[i].i]
14908 : "<unknown>";
14909 const char *out_name =
14910 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14911 ? aeabi_enum_names[out_attr[i].i]
14912 : "<unknown>";
ee065d83 14913 _bfd_error_handler
871b3ab2 14914 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14915 ibfd, in_name, out_name);
ee065d83
PB		 14916 }
14917 }
14918 break;
14919 case Tag_ABI_VFP_args:
14920 /* Aready done. */
14921 break;
14922 case Tag_ABI_WMMX_args:
14923 if (in_attr[i].i != out_attr[i].i)
14924 {
14925 _bfd_error_handler
871b3ab2 14926 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14927 ibfd, obfd);
91e22acd 14928 result = FALSE;
ee065d83
PB		 14929 }
14930 break;
7b86a9fa
AS		 14931 case Tag_compatibility:
14932 /* Merged in target-independent code. */
14933 break;
91e22acd 14934 case Tag_ABI_HardFP_use:
4547cb56 14935 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14936 break;
14937 case Tag_ABI_FP_16bit_format:
14938 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14939 {
14940 if (in_attr[i].i != out_attr[i].i)
14941 {
14942 _bfd_error_handler
871b3ab2 14943 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 14944 ibfd, obfd);
14945 result = FALSE;
14946 }
14947 }
14948 if (in_attr[i].i != 0)
14949 out_attr[i].i = in_attr[i].i;
14950 break;
7b86a9fa 14951
cd21e546 14952 case Tag_DIV_use:
ac56ee8f
MGD		 14953 /* A value of zero on input means that the divide instruction may
14954 be used if available in the base architecture as specified via
14955 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14956 the user did not want divide instructions. A value of 2
14957 explicitly means that divide instructions were allowed in ARM
14958 and Thumb state. */
14959 if (in_attr[i].i == out_attr[i].i)
14960 /* Do nothing. */ ;
14961 else if (elf32_arm_attributes_forbid_div (in_attr)
14962 && !elf32_arm_attributes_accept_div (out_attr))
14963 out_attr[i].i = 1;
14964 else if (elf32_arm_attributes_forbid_div (out_attr)
14965 && elf32_arm_attributes_accept_div (in_attr))
14966 out_attr[i].i = in_attr[i].i;
14967 else if (in_attr[i].i == 2)
14968 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14969 break;
14970
14971 case Tag_MPextension_use_legacy:
14972 /* We don't output objects with Tag_MPextension_use_legacy - we
14973 move the value to Tag_MPextension_use. */
14974 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14975 {
14976 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14977 {
14978 _bfd_error_handler
871b3ab2 14979 (_("%pB has both the current and legacy "
b38cadfb 14980 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14981 ibfd);
14982 result = FALSE;
14983 }
14984 }
14985
14986 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14987 out_attr[Tag_MPextension_use] = in_attr[i];
14988
14989 break;
14990
91e22acd 14991 case Tag_nodefaults:
2d0bb761
AS		 14992 /* This tag is set if it exists, but the value is unused (and is
14993 typically zero). We don't actually need to do anything here -
14994 the merge happens automatically when the type flags are merged
14995 below. */
91e22acd
AS		 14996 break;
14997 case Tag_also_compatible_with:
14998 /* Already done in Tag_CPU_arch. */
14999 break;
15000 case Tag_conformance:
15001 /* Keep the attribute if it matches. Throw it away otherwise.
15002 No attribute means no claim to conform. */
15003 if (!in_attr[i].s || !out_attr[i].s
15004 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
15005 out_attr[i].s = NULL;
15006 break;
3cfad14c 15007
91e22acd 15008 default:
e8b36cd1
JM		 15009 result
15010 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 15011 }
15012
15013 /* If out_attr was copied from in_attr then it won't have a type yet. */
15014 if (in_attr[i].type && !out_attr[i].type)
15015 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 15016 }
15017
104d59d1 15018 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 15019 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 15020 return FALSE;
ee065d83 15021
104d59d1 15022 /* Check for any attributes not known on ARM. */
e8b36cd1 15023 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 15024
91e22acd 15025 return result;
252b5132
RH		 15026}
15027
3a4a14e9
PB		 15028
15029/* Return TRUE if the two EABI versions are incompatible. */
15030
15031static bfd_boolean
15032elf32_arm_versions_compatible (unsigned iver, unsigned over)
15033{
15034 /* v4 and v5 are the same spec before and after it was released,
15035 so allow mixing them. */
15036 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
15037 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
15038 return TRUE;
15039
15040 return (iver == over);
15041}
15042
252b5132
RH		 15043/* Merge backend specific data from an object file to the output
15044 object file when linking. */
9b485d32 15045
b34976b6 15046static bfd_boolean
50e03d47 15047elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 15048
9b485d32
NC		 15049/* Display the flags field. */
15050
b34976b6 15051static bfd_boolean
57e8b36a 15052elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 15053{
fc830a83
NC		 15054 FILE * file = (FILE *) ptr;
15055 unsigned long flags;
252b5132
RH		 15056
15057 BFD_ASSERT (abfd != NULL && ptr != NULL);
15058
15059 /* Print normal ELF private data. */
15060 _bfd_elf_print_private_bfd_data (abfd, ptr);
15061
fc830a83 15062 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 15063 /* Ignore init flag - it may not be set, despite the flags field
15064 containing valid data. */
252b5132 15065
9b485d32 15066 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 15067
fc830a83
NC		 15068 switch (EF_ARM_EABI_VERSION (flags))
15069 {
15070 case EF_ARM_EABI_UNKNOWN:
4cc11e76 15071 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 15072 official ARM ELF extended ABI. Hence they are only decoded if
15073 the EABI version is not set. */
fd2ec330 15074 if (flags & EF_ARM_INTERWORK)
9b485d32 15075 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 15076
fd2ec330 15077 if (flags & EF_ARM_APCS_26)
6c571f00 15078 fprintf (file, " [APCS-26]");
fc830a83 15079 else
6c571f00 15080 fprintf (file, " [APCS-32]");
9a5aca8c 15081
96a846ea
RE		 15082 if (flags & EF_ARM_VFP_FLOAT)
15083 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 15084 else if (flags & EF_ARM_MAVERICK_FLOAT)
15085 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 15086 else
15087 fprintf (file, _(" [FPA float format]"));
15088
fd2ec330 15089 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 15090 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 15091
fd2ec330 15092 if (flags & EF_ARM_PIC)
9b485d32 15093 fprintf (file, _(" [position independent]"));
fc830a83 15094
fd2ec330 15095 if (flags & EF_ARM_NEW_ABI)
9b485d32 15096 fprintf (file, _(" [new ABI]"));
9a5aca8c 15097
fd2ec330 15098 if (flags & EF_ARM_OLD_ABI)
9b485d32 15099 fprintf (file, _(" [old ABI]"));
9a5aca8c 15100
fd2ec330 15101 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 15102 fprintf (file, _(" [software FP]"));
9a5aca8c 15103
96a846ea
RE		 15104 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
15105 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 15106 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
15107 | EF_ARM_MAVERICK_FLOAT);
fc830a83 15108 break;
9a5aca8c 15109
fc830a83 15110 case EF_ARM_EABI_VER1:
9b485d32 15111 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 15112
fc830a83 15113 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 15114 fprintf (file, _(" [sorted symbol table]"));
fc830a83 15115 else
9b485d32 15116 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 15117
fc830a83
NC		 15118 flags &= ~ EF_ARM_SYMSARESORTED;
15119 break;
9a5aca8c 15120
fd2ec330
PB		 15121 case EF_ARM_EABI_VER2:
15122 fprintf (file, _(" [Version2 EABI]"));
15123
15124 if (flags & EF_ARM_SYMSARESORTED)
15125 fprintf (file, _(" [sorted symbol table]"));
15126 else
15127 fprintf (file, _(" [unsorted symbol table]"));
15128
15129 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
15130 fprintf (file, _(" [dynamic symbols use segment index]"));
15131
15132 if (flags & EF_ARM_MAPSYMSFIRST)
15133 fprintf (file, _(" [mapping symbols precede others]"));
15134
99e4ae17 15135 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 15136 | EF_ARM_MAPSYMSFIRST);
15137 break;
15138
d507cf36
PB		 15139 case EF_ARM_EABI_VER3:
15140 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 15141 break;
15142
15143 case EF_ARM_EABI_VER4:
15144 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 15145 goto eabi;
d507cf36 15146
3a4a14e9
PB		 15147 case EF_ARM_EABI_VER5:
15148 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 15149
15150 if (flags & EF_ARM_ABI_FLOAT_SOFT)
15151 fprintf (file, _(" [soft-float ABI]"));
15152
15153 if (flags & EF_ARM_ABI_FLOAT_HARD)
15154 fprintf (file, _(" [hard-float ABI]"));
15155
15156 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
15157
3a4a14e9 15158 eabi:
d507cf36
PB		 15159 if (flags & EF_ARM_BE8)
15160 fprintf (file, _(" [BE8]"));
15161
15162 if (flags & EF_ARM_LE8)
15163 fprintf (file, _(" [LE8]"));
15164
15165 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
15166 break;
15167
fc830a83 15168 default:
9b485d32 15169 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 15170 break;
15171 }
252b5132 15172
fc830a83 15173 flags &= ~ EF_ARM_EABIMASK;
252b5132 15174
fc830a83 15175 if (flags & EF_ARM_RELEXEC)
9b485d32 15176 fprintf (file, _(" [relocatable executable]"));
252b5132 15177
18a20338
CL		 15178 if (flags & EF_ARM_PIC)
15179 fprintf (file, _(" [position independent]"));
15180
15181 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
15182 fprintf (file, _(" [FDPIC ABI supplement]"));
15183
15184 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 15185
15186 if (flags)
9b485d32 15187 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 15188
252b5132
RH		 15189 fputc ('\n', file);
15190
b34976b6 15191 return TRUE;
252b5132
RH		 15192}
15193
15194static int
57e8b36a 15195elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 15196{
2f0ca46a
NC		 15197 switch (ELF_ST_TYPE (elf_sym->st_info))
15198 {
15199 case STT_ARM_TFUNC:
15200 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 15201
2f0ca46a
NC		 15202 case STT_ARM_16BIT:
15203 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15204 This allows us to distinguish between data used by Thumb instructions
15205 and non-data (which is probably code) inside Thumb regions of an
15206 executable. */
1a0eb693 15207 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 15208 return ELF_ST_TYPE (elf_sym->st_info);
15209 break;
9a5aca8c 15210
ce855c42
NC		 15211 default:
15212 break;
2f0ca46a
NC		 15213 }
15214
15215 return type;
252b5132 15216}
f21f3fe0 15217
252b5132 15218static asection *
07adf181
AM		 15219elf32_arm_gc_mark_hook (asection *sec,
15220 struct bfd_link_info *info,
15221 Elf_Internal_Rela *rel,
15222 struct elf_link_hash_entry *h,
15223 Elf_Internal_Sym *sym)
252b5132
RH		 15224{
15225 if (h != NULL)
07adf181 15226 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 15227 {
15228 case R_ARM_GNU_VTINHERIT:
15229 case R_ARM_GNU_VTENTRY:
07adf181
AM		 15230 return NULL;
15231 }
9ad5cbcf 15232
07adf181 15233 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 15234}
15235
780a67af
NC		 15236/* Look through the relocs for a section during the first phase. */
15237
b34976b6 15238static bfd_boolean
57e8b36a
NC		 15239elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
15240 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 15241{
b34976b6
AM		 15242 Elf_Internal_Shdr *symtab_hdr;
15243 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 15244 const Elf_Internal_Rela *rel;
15245 const Elf_Internal_Rela *rel_end;
15246 bfd *dynobj;
5e681ec4 15247 asection *sreloc;
5e681ec4 15248 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 15249 bfd_boolean call_reloc_p;
15250 bfd_boolean may_become_dynamic_p;
15251 bfd_boolean may_need_local_target_p;
ce98a316 15252 unsigned long nsyms;
9a5aca8c 15253
0e1862bb 15254 if (bfd_link_relocatable (info))
b34976b6 15255 return TRUE;
9a5aca8c 15256
0ffa91dd
NC		 15257 BFD_ASSERT (is_arm_elf (abfd));
15258
5e681ec4 15259 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15260 if (htab == NULL)
15261 return FALSE;
15262
5e681ec4 15263 sreloc = NULL;
9a5aca8c 15264
67687978
PB		 15265 /* Create dynamic sections for relocatable executables so that we can
15266 copy relocations. */
15267 if (htab->root.is_relocatable_executable
15268 && ! htab->root.dynamic_sections_created)
15269 {
15270 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15271 return FALSE;
15272 }
15273
cbc704f3
RS		 15274 if (htab->root.dynobj == NULL)
15275 htab->root.dynobj = abfd;
34e77a92
RS		 15276 if (!create_ifunc_sections (info))
15277 return FALSE;
cbc704f3
RS		 15278
15279 dynobj = htab->root.dynobj;
15280
0ffa91dd 15281 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 15282 sym_hashes = elf_sym_hashes (abfd);
ce98a316 15283 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 15284
252b5132
RH		 15285 rel_end = relocs + sec->reloc_count;
15286 for (rel = relocs; rel < rel_end; rel++)
15287 {
34e77a92 15288 Elf_Internal_Sym *isym;
252b5132 15289 struct elf_link_hash_entry *h;
b7693d02 15290 struct elf32_arm_link_hash_entry *eh;
d42c267e 15291 unsigned int r_symndx;
eb043451 15292 int r_type;
9a5aca8c 15293
252b5132 15294 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 15295 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 15296 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 15297
ce98a316
NC		 15298 if (r_symndx >= nsyms
15299 /* PR 9934: It is possible to have relocations that do not
15300 refer to symbols, thus it is also possible to have an
15301 object file containing relocations but no symbol table. */
cf35638d 15302 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 15303 {
871b3ab2 15304 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 15305 r_symndx);
ba93b8ac
DJ		 15306 return FALSE;
15307 }
15308
34e77a92
RS		 15309 h = NULL;
15310 isym = NULL;
15311 if (nsyms > 0)
973a3492 15312 {
34e77a92
RS		 15313 if (r_symndx < symtab_hdr->sh_info)
15314 {
15315 /* A local symbol. */
f1dfbfdb 15316 isym = bfd_sym_from_r_symndx (&htab->root.sym_cache,
34e77a92
RS		 15317 abfd, r_symndx);
15318 if (isym == NULL)
15319 return FALSE;
15320 }
15321 else
15322 {
15323 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15324 while (h->root.type == bfd_link_hash_indirect
15325 || h->root.type == bfd_link_hash_warning)
15326 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15327 }
973a3492 15328 }
9a5aca8c 15329
b7693d02
DJ		 15330 eh = (struct elf32_arm_link_hash_entry *) h;
15331
f6e32f6d
RS		 15332 call_reloc_p = FALSE;
15333 may_become_dynamic_p = FALSE;
15334 may_need_local_target_p = FALSE;
15335
0855e32b
NS		 15336 /* Could be done earlier, if h were already available. */
15337 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 15338 switch (r_type)
99059e56 15339 {
e8b09b87
CL		 15340 case R_ARM_GOTOFFFUNCDESC:
15341 {
15342 if (h == NULL)
15343 {
15344 if (!elf32_arm_allocate_local_sym_info (abfd))
15345 return FALSE;
15346 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].gotofffuncdesc_cnt += 1;
15347 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15348 }
15349 else
15350 {
15351 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15352 }
15353 }
15354 break;
15355
15356 case R_ARM_GOTFUNCDESC:
15357 {
15358 if (h == NULL)
15359 {
15360 /* Such a relocation is not supposed to be generated
15361 by gcc on a static function. */
15362 /* Anyway if needed it could be handled. */
15363 abort();
15364 }
15365 else
15366 {
15367 eh->fdpic_cnts.gotfuncdesc_cnt++;
15368 }
15369 }
15370 break;
15371
15372 case R_ARM_FUNCDESC:
15373 {
15374 if (h == NULL)
15375 {
15376 if (!elf32_arm_allocate_local_sym_info (abfd))
15377 return FALSE;
15378 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_cnt += 1;
15379 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15380 }
15381 else
15382 {
15383 eh->fdpic_cnts.funcdesc_cnt++;
15384 }
15385 }
15386 break;
15387
5e681ec4 15388 case R_ARM_GOT32:
eb043451 15389 case R_ARM_GOT_PREL:
ba93b8ac 15390 case R_ARM_TLS_GD32:
5c5a4843 15391 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 15392 case R_ARM_TLS_IE32:
5c5a4843 15393 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 15394 case R_ARM_TLS_GOTDESC:
15395 case R_ARM_TLS_DESCSEQ:
15396 case R_ARM_THM_TLS_DESCSEQ:
15397 case R_ARM_TLS_CALL:
15398 case R_ARM_THM_TLS_CALL:
5e681ec4 15399 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 15400 {
15401 int tls_type, old_tls_type;
5e681ec4 15402
ba93b8ac
DJ		 15403 switch (r_type)
15404 {
15405 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
5c5a4843 15406 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
b38cadfb 15407
ba93b8ac 15408 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
5c5a4843 15409 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
b38cadfb 15410
0855e32b
NS		 15411 case R_ARM_TLS_GOTDESC:
15412 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15413 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15414 tls_type = GOT_TLS_GDESC; break;
b38cadfb 15415
ba93b8ac
DJ		 15416 default: tls_type = GOT_NORMAL; break;
15417 }
252b5132 15418
0e1862bb 15419 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 15420 info->flags |= DF_STATIC_TLS;
15421
ba93b8ac
DJ		 15422 if (h != NULL)
15423 {
15424 h->got.refcount++;
15425 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15426 }
15427 else
15428 {
ba93b8ac 15429 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 15430 if (!elf32_arm_allocate_local_sym_info (abfd))
15431 return FALSE;
15432 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 15433 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15434 }
15435
0855e32b 15436 /* If a variable is accessed with both tls methods, two
99059e56 15437 slots may be created. */
0855e32b
NS		 15438 if (GOT_TLS_GD_ANY_P (old_tls_type)
15439 && GOT_TLS_GD_ANY_P (tls_type))
15440 tls_type |= old_tls_type;
15441
15442 /* We will already have issued an error message if there
15443 is a TLS/non-TLS mismatch, based on the symbol
15444 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 15445 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15446 && tls_type != GOT_NORMAL)
15447 tls_type |= old_tls_type;
15448
0855e32b 15449 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 15450 method, we're able to relax. Turn off the GDESC flag,
15451 without messing up with any other kind of tls types
6a631e86 15452 that may be involved. */
0855e32b
NS		 15453 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15454 tls_type &= ~GOT_TLS_GDESC;
15455
ba93b8ac
DJ		 15456 if (old_tls_type != tls_type)
15457 {
15458 if (h != NULL)
15459 elf32_arm_hash_entry (h)->tls_type = tls_type;
15460 else
15461 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15462 }
15463 }
8029a119 15464 /* Fall through. */
ba93b8ac
DJ		 15465
15466 case R_ARM_TLS_LDM32:
5c5a4843
CL		 15467 case R_ARM_TLS_LDM32_FDPIC:
15468 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
ba93b8ac 15469 htab->tls_ldm_got.refcount++;
8029a119 15470 /* Fall through. */
252b5132 15471
c19d1205 15472 case R_ARM_GOTOFF32:
5e681ec4 15473 case R_ARM_GOTPC:
cbc704f3
RS		 15474 if (htab->root.sgot == NULL
15475 && !create_got_section (htab->root.dynobj, info))
15476 return FALSE;
252b5132
RH		 15477 break;
15478
252b5132 15479 case R_ARM_PC24:
7359ea65 15480 case R_ARM_PLT32:
5b5bb741
PB		 15481 case R_ARM_CALL:
15482 case R_ARM_JUMP24:
eb043451 15483 case R_ARM_PREL31:
c19d1205 15484 case R_ARM_THM_CALL:
bd97cb95
DJ		 15485 case R_ARM_THM_JUMP24:
15486 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 15487 call_reloc_p = TRUE;
15488 may_need_local_target_p = TRUE;
15489 break;
15490
15491 case R_ARM_ABS12:
15492 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15493 ldr __GOTT_INDEX__ offsets. */
90c14f0c 15494 if (htab->root.target_os != is_vxworks)
f6e32f6d
RS		 15495 {
15496 may_need_local_target_p = TRUE;
15497 break;
15498 }
aebf9be7 15499 else goto jump_over;
9eaff861 15500
f6e32f6d 15501 /* Fall through. */
39623e12 15502
96c23d59
JM		 15503 case R_ARM_MOVW_ABS_NC:
15504 case R_ARM_MOVT_ABS:
15505 case R_ARM_THM_MOVW_ABS_NC:
15506 case R_ARM_THM_MOVT_ABS:
0e1862bb 15507 if (bfd_link_pic (info))
96c23d59 15508 {
4eca0228 15509 _bfd_error_handler
871b3ab2 15510 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 15511 abfd, elf32_arm_howto_table_1[r_type].name,
15512 (h) ? h->root.root.string : "a local symbol");
15513 bfd_set_error (bfd_error_bad_value);
15514 return FALSE;
15515 }
15516
15517 /* Fall through. */
39623e12
PB		 15518 case R_ARM_ABS32:
15519 case R_ARM_ABS32_NOI:
aebf9be7 15520 jump_over:
0e1862bb 15521 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 15522 {
15523 h->pointer_equality_needed = 1;
15524 }
15525 /* Fall through. */
39623e12
PB		 15526 case R_ARM_REL32:
15527 case R_ARM_REL32_NOI:
b6895b4f
PB		 15528 case R_ARM_MOVW_PREL_NC:
15529 case R_ARM_MOVT_PREL:
b6895b4f
PB		 15530 case R_ARM_THM_MOVW_PREL_NC:
15531 case R_ARM_THM_MOVT_PREL:
39623e12 15532
b7693d02 15533 /* Should the interworking branches be listed here? */
e8b09b87
CL		 15534 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15535 || htab->fdpic_p)
34e77a92
RS		 15536 && (sec->flags & SEC_ALLOC) != 0)
15537 {
15538 if (h == NULL
469a3493 15539 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 15540 {
15541 /* In shared libraries and relocatable executables,
15542 we treat local relative references as calls;
15543 see the related SYMBOL_CALLS_LOCAL code in
15544 allocate_dynrelocs. */
15545 call_reloc_p = TRUE;
15546 may_need_local_target_p = TRUE;
15547 }
15548 else
15549 /* We are creating a shared library or relocatable
15550 executable, and this is a reloc against a global symbol,
15551 or a non-PC-relative reloc against a local symbol.
15552 We may need to copy the reloc into the output. */
15553 may_become_dynamic_p = TRUE;
15554 }
f6e32f6d
RS		 15555 else
15556 may_need_local_target_p = TRUE;
252b5132
RH		 15557 break;
15558
99059e56
RM		 15559 /* This relocation describes the C++ object vtable hierarchy.
15560 Reconstruct it for later use during GC. */
15561 case R_ARM_GNU_VTINHERIT:
15562 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15563 return FALSE;
15564 break;
15565
15566 /* This relocation describes which C++ vtable entries are actually
15567 used. Record for later use during GC. */
15568 case R_ARM_GNU_VTENTRY:
a0ea3a14 15569 if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
99059e56
RM		 15570 return FALSE;
15571 break;
15572 }
f6e32f6d
RS		 15573
15574 if (h != NULL)
15575 {
15576 if (call_reloc_p)
15577 /* We may need a .plt entry if the function this reloc
15578 refers to is in a different object, regardless of the
15579 symbol's type. We can't tell for sure yet, because
15580 something later might force the symbol local. */
15581 h->needs_plt = 1;
15582 else if (may_need_local_target_p)
15583 /* If this reloc is in a read-only section, we might
15584 need a copy reloc. We can't check reliably at this
15585 stage whether the section is read-only, as input
15586 sections have not yet been mapped to output sections.
15587 Tentatively set the flag for now, and correct in
15588 adjust_dynamic_symbol. */
15589 h->non_got_ref = 1;
15590 }
15591
34e77a92
RS		 15592 if (may_need_local_target_p
15593 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 15594 {
34e77a92
RS		 15595 union gotplt_union *root_plt;
15596 struct arm_plt_info *arm_plt;
15597 struct arm_local_iplt_info *local_iplt;
15598
15599 if (h != NULL)
15600 {
15601 root_plt = &h->plt;
15602 arm_plt = &eh->plt;
15603 }
15604 else
15605 {
15606 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15607 if (local_iplt == NULL)
15608 return FALSE;
15609 root_plt = &local_iplt->root;
15610 arm_plt = &local_iplt->arm;
15611 }
15612
f6e32f6d
RS		 15613 /* If the symbol is a function that doesn't bind locally,
15614 this relocation will need a PLT entry. */
a8c887dd
NC		 15615 if (root_plt->refcount != -1)
15616 root_plt->refcount += 1;
34e77a92
RS		 15617
15618 if (!call_reloc_p)
15619 arm_plt->noncall_refcount++;
f6e32f6d
RS		 15620
15621 /* It's too early to use htab->use_blx here, so we have to
15622 record possible blx references separately from
15623 relocs that definitely need a thumb stub. */
15624
15625 if (r_type == R_ARM_THM_CALL)
34e77a92 15626 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 15627
15628 if (r_type == R_ARM_THM_JUMP24
15629 || r_type == R_ARM_THM_JUMP19)
34e77a92 15630 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 15631 }
15632
15633 if (may_become_dynamic_p)
15634 {
15635 struct elf_dyn_relocs *p, **head;
15636
15637 /* Create a reloc section in dynobj. */
15638 if (sreloc == NULL)
15639 {
15640 sreloc = _bfd_elf_make_dynamic_reloc_section
15641 (sec, dynobj, 2, abfd, ! htab->use_rel);
15642
15643 if (sreloc == NULL)
15644 return FALSE;
15645
15646 /* BPABI objects never have dynamic relocations mapped. */
90c14f0c 15647 if (htab->root.target_os == is_symbian)
f6e32f6d
RS		 15648 {
15649 flagword flags;
15650
fd361982 15651 flags = bfd_section_flags (sreloc);
f6e32f6d 15652 flags &= ~(SEC_LOAD | SEC_ALLOC);
fd361982 15653 bfd_set_section_flags (sreloc, flags);
f6e32f6d
RS		 15654 }
15655 }
15656
15657 /* If this is a global symbol, count the number of
15658 relocations we need for this symbol. */
15659 if (h != NULL)
190eb1dd 15660 head = &h->dyn_relocs;
f6e32f6d
RS		 15661 else
15662 {
34e77a92
RS		 15663 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15664 if (head == NULL)
f6e32f6d 15665 return FALSE;
f6e32f6d
RS		 15666 }
15667
15668 p = *head;
15669 if (p == NULL || p->sec != sec)
15670 {
986f0783 15671 size_t amt = sizeof *p;
f6e32f6d
RS		 15672
15673 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15674 if (p == NULL)
15675 return FALSE;
15676 p->next = *head;
15677 *head = p;
15678 p->sec = sec;
15679 p->count = 0;
15680 p->pc_count = 0;
15681 }
15682
469a3493 15683 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 15684 p->pc_count += 1;
15685 p->count += 1;
e8b09b87
CL		 15686 if (h == NULL && htab->fdpic_p && !bfd_link_pic(info)
15687 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI) {
15688 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15689 that will become rofixup. */
15690 /* This is due to the fact that we suppose all will become rofixup. */
15691 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15692 _bfd_error_handler
15693 (_("FDPIC does not yet support %s relocation"
15694 " to become dynamic for executable"),
15695 elf32_arm_howto_table_1[r_type].name);
15696 abort();
15697 }
f6e32f6d 15698 }
252b5132 15699 }
f21f3fe0 15700
b34976b6 15701 return TRUE;
252b5132
RH		 15702}
15703
9eaff861
AO		 15704static void
15705elf32_arm_update_relocs (asection *o,
15706 struct bfd_elf_section_reloc_data *reldata)
15707{
15708 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15709 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15710 const struct elf_backend_data *bed;
15711 _arm_elf_section_data *eado;
15712 struct bfd_link_order *p;
15713 bfd_byte *erela_head, *erela;
15714 Elf_Internal_Rela *irela_head, *irela;
15715 Elf_Internal_Shdr *rel_hdr;
15716 bfd *abfd;
15717 unsigned int count;
15718
15719 eado = get_arm_elf_section_data (o);
15720
15721 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15722 return;
15723
15724 abfd = o->owner;
15725 bed = get_elf_backend_data (abfd);
15726 rel_hdr = reldata->hdr;
15727
15728 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15729 {
15730 swap_in = bed->s->swap_reloc_in;
15731 swap_out = bed->s->swap_reloc_out;
15732 }
15733 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15734 {
15735 swap_in = bed->s->swap_reloca_in;
15736 swap_out = bed->s->swap_reloca_out;
15737 }
15738 else
15739 abort ();
15740
15741 erela_head = rel_hdr->contents;
15742 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15743 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15744
15745 erela = erela_head;
15746 irela = irela_head;
15747 count = 0;
15748
15749 for (p = o->map_head.link_order; p; p = p->next)
15750 {
15751 if (p->type == bfd_section_reloc_link_order
15752 || p->type == bfd_symbol_reloc_link_order)
15753 {
15754 (*swap_in) (abfd, erela, irela);
15755 erela += rel_hdr->sh_entsize;
15756 irela++;
15757 count++;
15758 }
15759 else if (p->type == bfd_indirect_link_order)
15760 {
15761 struct bfd_elf_section_reloc_data *input_reldata;
15762 arm_unwind_table_edit *edit_list, *edit_tail;
15763 _arm_elf_section_data *eadi;
15764 bfd_size_type j;
15765 bfd_vma offset;
15766 asection *i;
15767
15768 i = p->u.indirect.section;
15769
15770 eadi = get_arm_elf_section_data (i);
15771 edit_list = eadi->u.exidx.unwind_edit_list;
15772 edit_tail = eadi->u.exidx.unwind_edit_tail;
539300fb 15773 offset = i->output_offset;
9eaff861
AO		 15774
15775 if (eadi->elf.rel.hdr &&
15776 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15777 input_reldata = &eadi->elf.rel;
15778 else if (eadi->elf.rela.hdr &&
15779 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15780 input_reldata = &eadi->elf.rela;
15781 else
15782 abort ();
15783
15784 if (edit_list)
15785 {
15786 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15787 {
15788 arm_unwind_table_edit *edit_node, *edit_next;
15789 bfd_vma bias;
c48182bf 15790 bfd_vma reloc_index;
9eaff861
AO		 15791
15792 (*swap_in) (abfd, erela, irela);
c48182bf 15793 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 15794
15795 bias = 0;
15796 edit_node = edit_list;
15797 for (edit_next = edit_list;
c48182bf 15798 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 15799 edit_next = edit_node->next)
15800 {
15801 bias++;
15802 edit_node = edit_next;
15803 }
15804
15805 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 15806 || edit_node->index != reloc_index)
9eaff861
AO		 15807 {
15808 irela->r_offset -= bias * 8;
15809 irela++;
15810 count++;
15811 }
15812
15813 erela += rel_hdr->sh_entsize;
15814 }
15815
15816 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15817 {
15818 /* New relocation entity. */
15819 asection *text_sec = edit_tail->linked_section;
15820 asection *text_out = text_sec->output_section;
15821 bfd_vma exidx_offset = offset + i->size - 8;
15822
15823 irela->r_addend = 0;
15824 irela->r_offset = exidx_offset;
15825 irela->r_info = ELF32_R_INFO
15826 (text_out->target_index, R_ARM_PREL31);
15827 irela++;
15828 count++;
15829 }
15830 }
15831 else
15832 {
15833 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15834 {
15835 (*swap_in) (abfd, erela, irela);
15836 erela += rel_hdr->sh_entsize;
15837 irela++;
15838 }
15839
15840 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15841 }
15842 }
15843 }
15844
15845 reldata->count = count;
15846 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15847
15848 erela = erela_head;
15849 irela = irela_head;
15850 while (count > 0)
15851 {
15852 (*swap_out) (abfd, irela, erela);
15853 erela += rel_hdr->sh_entsize;
15854 irela++;
15855 count--;
15856 }
15857
15858 free (irela_head);
15859
15860 /* Hashes are no longer valid. */
15861 free (reldata->hashes);
15862 reldata->hashes = NULL;
15863}
15864
6a5bb875 15865/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15866 required if the corresponding code section is marked. Similarly, ARMv8-M
15867 secure entry functions can only be referenced by SG veneers which are
15868 created after the GC process. They need to be marked in case they reside in
15869 their own section (as would be the case if code was compiled with
15870 -ffunction-sections). */
6a5bb875
PB		 15871
15872static bfd_boolean
906e58ca
NC		 15873elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15874 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15875{
15876 bfd *sub;
15877 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15878 asection *cmse_sec;
15879 obj_attribute *out_attr;
15880 Elf_Internal_Shdr *symtab_hdr;
15881 unsigned i, sym_count, ext_start;
15882 const struct elf_backend_data *bed;
15883 struct elf_link_hash_entry **sym_hashes;
15884 struct elf32_arm_link_hash_entry *cmse_hash;
15885 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
bb32413f
SP		 15886 bfd_boolean debug_sec_need_to_be_marked = FALSE;
15887 asection *isec;
6a5bb875 15888
7f6ab9f8
AM		 15889 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15890
4ba2ef8f
TP		 15891 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15892 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15893 && out_attr[Tag_CPU_arch_profile].i == 'M';
15894
6a5bb875
PB		 15895 /* Marking EH data may cause additional code sections to be marked,
15896 requiring multiple passes. */
15897 again = TRUE;
15898 while (again)
15899 {
15900 again = FALSE;
c72f2fb2 15901 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15902 {
15903 asection *o;
15904
0ffa91dd 15905 if (! is_arm_elf (sub))
6a5bb875
PB		 15906 continue;
15907
15908 elf_shdrp = elf_elfsections (sub);
15909 for (o = sub->sections; o != NULL; o = o->next)
15910 {
15911 Elf_Internal_Shdr *hdr;
0ffa91dd 15912
6a5bb875 15913 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15914 if (hdr->sh_type == SHT_ARM_EXIDX
15915 && hdr->sh_link
15916 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15917 && !o->gc_mark
15918 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15919 {
15920 again = TRUE;
15921 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15922 return FALSE;
15923 }
15924 }
4ba2ef8f
TP		 15925
15926 /* Mark section holding ARMv8-M secure entry functions. We mark all
15927 of them so no need for a second browsing. */
15928 if (is_v8m && first_bfd_browse)
15929 {
15930 sym_hashes = elf_sym_hashes (sub);
15931 bed = get_elf_backend_data (sub);
15932 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15933 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15934 ext_start = symtab_hdr->sh_info;
15935
15936 /* Scan symbols. */
15937 for (i = ext_start; i < sym_count; i++)
15938 {
15939 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15940
15941 /* Assume it is a special symbol. If not, cmse_scan will
15942 warn about it and user can do something about it. */
baf46cd7
AM		 15943 if (CONST_STRNEQ (cmse_hash->root.root.root.string,
15944 CMSE_PREFIX))
4ba2ef8f
TP		 15945 {
15946 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15947 if (!cmse_sec->gc_mark
15948 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f 15949 return FALSE;
bb32413f
SP		 15950 /* The debug sections related to these secure entry
15951 functions are marked on enabling below flag. */
15952 debug_sec_need_to_be_marked = TRUE;
4ba2ef8f
TP		 15953 }
15954 }
bb32413f
SP		 15955
15956 if (debug_sec_need_to_be_marked)
15957 {
15958 /* Looping over all the sections of the object file containing
15959 Armv8-M secure entry functions and marking all the debug
15960 sections. */
15961 for (isec = sub->sections; isec != NULL; isec = isec->next)
15962 {
15963 /* If not a debug sections, skip it. */
15964 if (!isec->gc_mark && (isec->flags & SEC_DEBUGGING))
15965 isec->gc_mark = 1 ;
15966 }
15967 debug_sec_need_to_be_marked = FALSE;
15968 }
4ba2ef8f 15969 }
6a5bb875 15970 }
4ba2ef8f 15971 first_bfd_browse = FALSE;
6a5bb875
PB		 15972 }
15973
15974 return TRUE;
15975}
15976
3c9458e9
NC		 15977/* Treat mapping symbols as special target symbols. */
15978
15979static bfd_boolean
15980elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
15981{
b0796911
PB		 15982 return bfd_is_arm_special_symbol_name (sym->name,
15983 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 15984}
15985
e7679060
AM		 15986/* If the ELF symbol SYM might be a function in SEC, return the
15987 function size and set *CODE_OFF to the function's entry point,
15988 otherwise return zero. */
252b5132 15989
e7679060
AM		 15990static bfd_size_type
15991elf32_arm_maybe_function_sym (const asymbol *sym, asection *sec,
15992 bfd_vma *code_off)
15993{
15994 bfd_size_type size;
252b5132 15995
e7679060
AM		 15996 if ((sym->flags & (BSF_SECTION_SYM | BSF_FILE | BSF_OBJECT
15997 | BSF_THREAD_LOCAL | BSF_RELC | BSF_SRELC)) != 0
15998 || sym->section != sec)
15999 return 0;
252b5132 16000
e7679060
AM		 16001 if (!(sym->flags & BSF_SYNTHETIC))
16002 switch (ELF_ST_TYPE (((elf_symbol_type *) sym)->internal_elf_sym.st_info))
16003 {
252b5132
RH		 16004 case STT_FUNC:
16005 case STT_ARM_TFUNC:
9d2da7ca 16006 case STT_NOTYPE:
252b5132 16007 break;
e7679060
AM		 16008 default:
16009 return 0;
16010 }
0367ecfb 16011
e7679060
AM		 16012 if ((sym->flags & BSF_LOCAL)
16013 && bfd_is_arm_special_symbol_name (sym->name,
16014 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
16015 return 0;
0367ecfb 16016
e7679060
AM		 16017 *code_off = sym->value;
16018 size = 0;
16019 if (!(sym->flags & BSF_SYNTHETIC))
16020 size = ((elf_symbol_type *) sym)->internal_elf_sym.st_size;
16021 if (size == 0)
16022 size = 1;
16023 return size;
252b5132
RH		 16024}
16025
4ab527b0 16026static bfd_boolean
07d6d2b8 16027elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 16028 const char ** filename_ptr,
16029 const char ** functionname_ptr,
16030 unsigned int * line_ptr)
16031{
16032 bfd_boolean found;
16033 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
16034 functionname_ptr, line_ptr,
16035 & elf_tdata (abfd)->dwarf2_find_line_info);
16036 return found;
16037}
16038
252b5132
RH		 16039/* Adjust a symbol defined by a dynamic object and referenced by a
16040 regular object. The current definition is in some section of the
16041 dynamic object, but we're not including those sections. We have to
16042 change the definition to something the rest of the link can
16043 understand. */
16044
b34976b6 16045static bfd_boolean
57e8b36a
NC		 16046elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
16047 struct elf_link_hash_entry * h)
252b5132
RH		 16048{
16049 bfd * dynobj;
5474d94f 16050 asection *s, *srel;
b7693d02 16051 struct elf32_arm_link_hash_entry * eh;
67687978 16052 struct elf32_arm_link_hash_table *globals;
252b5132 16053
67687978 16054 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16055 if (globals == NULL)
16056 return FALSE;
16057
252b5132
RH		 16058 dynobj = elf_hash_table (info)->dynobj;
16059
16060 /* Make sure we know what is going on here. */
16061 BFD_ASSERT (dynobj != NULL
f5385ebf 16062 && (h->needs_plt
34e77a92 16063 || h->type == STT_GNU_IFUNC
60d67dc8 16064 || h->is_weakalias
f5385ebf
AM		 16065 || (h->def_dynamic
16066 && h->ref_regular
16067 && !h->def_regular)));
252b5132 16068
b7693d02
DJ		 16069 eh = (struct elf32_arm_link_hash_entry *) h;
16070
252b5132
RH		 16071 /* If this is a function, put it in the procedure linkage table. We
16072 will fill in the contents of the procedure linkage table later,
16073 when we know the address of the .got section. */
34e77a92 16074 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 16075 {
34e77a92
RS		 16076 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16077 symbol binds locally. */
5e681ec4 16078 if (h->plt.refcount <= 0
34e77a92
RS		 16079 || (h->type != STT_GNU_IFUNC
16080 && (SYMBOL_CALLS_LOCAL (info, h)
16081 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16082 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 16083 {
16084 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 16085 file, but the symbol was never referred to by a dynamic
16086 object, or if all references were garbage collected. In
16087 such a case, we don't actually need to build a procedure
16088 linkage table, and we can just do a PC24 reloc instead. */
16089 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16090 eh->plt.thumb_refcount = 0;
16091 eh->plt.maybe_thumb_refcount = 0;
16092 eh->plt.noncall_refcount = 0;
f5385ebf 16093 h->needs_plt = 0;
252b5132
RH		 16094 }
16095
b34976b6 16096 return TRUE;
252b5132 16097 }
5e681ec4 16098 else
b7693d02
DJ		 16099 {
16100 /* It's possible that we incorrectly decided a .plt reloc was
16101 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16102 in check_relocs. We can't decide accurately between function
16103 and non-function syms in check-relocs; Objects loaded later in
16104 the link may change h->type. So fix it now. */
16105 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16106 eh->plt.thumb_refcount = 0;
16107 eh->plt.maybe_thumb_refcount = 0;
16108 eh->plt.noncall_refcount = 0;
b7693d02 16109 }
252b5132
RH		 16110
16111 /* If this is a weak symbol, and there is a real definition, the
16112 processor independent code will have arranged for us to see the
16113 real definition first, and we can just use the same value. */
60d67dc8 16114 if (h->is_weakalias)
252b5132 16115 {
60d67dc8
AM		 16116 struct elf_link_hash_entry *def = weakdef (h);
16117 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
16118 h->root.u.def.section = def->root.u.def.section;
16119 h->root.u.def.value = def->root.u.def.value;
b34976b6 16120 return TRUE;
252b5132
RH		 16121 }
16122
ba93b8ac
DJ		 16123 /* If there are no non-GOT references, we do not need a copy
16124 relocation. */
16125 if (!h->non_got_ref)
16126 return TRUE;
16127
252b5132
RH		 16128 /* This is a reference to a symbol defined by a dynamic object which
16129 is not a function. */
16130
16131 /* If we are creating a shared library, we must presume that the
16132 only references to the symbol are via the global offset table.
16133 For such cases we need not do anything here; the relocations will
67687978
PB		 16134 be handled correctly by relocate_section. Relocatable executables
16135 can reference data in shared objects directly, so we don't need to
16136 do anything here. */
0e1862bb 16137 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 16138 return TRUE;
252b5132
RH		 16139
16140 /* We must allocate the symbol in our .dynbss section, which will
16141 become part of the .bss section of the executable. There will be
16142 an entry for this symbol in the .dynsym section. The dynamic
16143 object will contain position independent code, so all references
16144 from the dynamic object to this symbol will go through the global
16145 offset table. The dynamic linker will use the .dynsym entry to
16146 determine the address it must put in the global offset table, so
16147 both the dynamic object and the regular object will refer to the
16148 same memory location for the variable. */
5522f910
NC		 16149 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16150 linker to copy the initial value out of the dynamic object and into
16151 the runtime process image. We need to remember the offset into the
00a97672 16152 .rel(a).bss section we are going to use. */
5474d94f
AM		 16153 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
16154 {
16155 s = globals->root.sdynrelro;
16156 srel = globals->root.sreldynrelro;
16157 }
16158 else
16159 {
16160 s = globals->root.sdynbss;
16161 srel = globals->root.srelbss;
16162 }
5522f910
NC		 16163 if (info->nocopyreloc == 0
16164 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 16165 && h->size != 0)
252b5132 16166 {
47beaa6a 16167 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 16168 h->needs_copy = 1;
252b5132
RH		 16169 }
16170
6cabe1ea 16171 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 16172}
16173
5e681ec4
PB		 16174/* Allocate space in .plt, .got and associated reloc sections for
16175 dynamic relocs. */
16176
16177static bfd_boolean
47beaa6a 16178allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 16179{
16180 struct bfd_link_info *info;
16181 struct elf32_arm_link_hash_table *htab;
16182 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 16183 struct elf_dyn_relocs *p;
5e681ec4
PB		 16184
16185 if (h->root.type == bfd_link_hash_indirect)
16186 return TRUE;
16187
e6a6bb22
AM		 16188 eh = (struct elf32_arm_link_hash_entry *) h;
16189
5e681ec4
PB		 16190 info = (struct bfd_link_info *) inf;
16191 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16192 if (htab == NULL)
16193 return FALSE;
5e681ec4 16194
34e77a92 16195 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 16196 && h->plt.refcount > 0)
16197 {
16198 /* Make sure this symbol is output as a dynamic symbol.
16199 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16200 if (h->dynindx == -1 && !h->forced_local
16201 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16202 {
c152c796 16203 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16204 return FALSE;
16205 }
16206
34e77a92
RS		 16207 /* If the call in the PLT entry binds locally, the associated
16208 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16209 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16210 than the .plt section. */
16211 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16212 {
16213 eh->is_iplt = 1;
16214 if (eh->plt.noncall_refcount == 0
16215 && SYMBOL_REFERENCES_LOCAL (info, h))
16216 /* All non-call references can be resolved directly.
16217 This means that they can (and in some cases, must)
16218 resolve directly to the run-time target, rather than
16219 to the PLT. That in turns means that any .got entry
16220 would be equal to the .igot.plt entry, so there's
16221 no point having both. */
16222 h->got.refcount = 0;
16223 }
16224
0e1862bb 16225 if (bfd_link_pic (info)
34e77a92 16226 || eh->is_iplt
7359ea65 16227 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 16228 {
34e77a92 16229 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 16230
5e681ec4
PB		 16231 /* If this symbol is not defined in a regular file, and we are
16232 not generating a shared library, then set the symbol to this
16233 location in the .plt. This is required to make function
16234 pointers compare as equal between the normal executable and
16235 the shared library. */
0e1862bb 16236 if (! bfd_link_pic (info)
f5385ebf 16237 && !h->def_regular)
5e681ec4 16238 {
34e77a92 16239 h->root.u.def.section = htab->root.splt;
5e681ec4 16240 h->root.u.def.value = h->plt.offset;
5e681ec4 16241
67d74e43
DJ		 16242 /* Make sure the function is not marked as Thumb, in case
16243 it is the target of an ABS32 relocation, which will
16244 point to the PLT entry. */
39d911fc 16245 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 16246 }
022f8312 16247
00a97672
RS		 16248 /* VxWorks executables have a second set of relocations for
16249 each PLT entry. They go in a separate relocation section,
16250 which is processed by the kernel loader. */
90c14f0c 16251 if (htab->root.target_os == is_vxworks && !bfd_link_pic (info))
00a97672
RS		 16252 {
16253 /* There is a relocation for the initial PLT entry:
16254 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16255 if (h->plt.offset == htab->plt_header_size)
47beaa6a 16256 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 16257
16258 /* There are two extra relocations for each subsequent
16259 PLT entry: an R_ARM_32 relocation for the GOT entry,
16260 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 16261 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 16262 }
5e681ec4
PB		 16263 }
16264 else
16265 {
16266 h->plt.offset = (bfd_vma) -1;
f5385ebf 16267 h->needs_plt = 0;
5e681ec4
PB		 16268 }
16269 }
16270 else
16271 {
16272 h->plt.offset = (bfd_vma) -1;
f5385ebf 16273 h->needs_plt = 0;
5e681ec4
PB		 16274 }
16275
0855e32b
NS		 16276 eh = (struct elf32_arm_link_hash_entry *) h;
16277 eh->tlsdesc_got = (bfd_vma) -1;
16278
5e681ec4
PB		 16279 if (h->got.refcount > 0)
16280 {
16281 asection *s;
16282 bfd_boolean dyn;
ba93b8ac
DJ		 16283 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16284 int indx;
5e681ec4
PB		 16285
16286 /* Make sure this symbol is output as a dynamic symbol.
16287 Undefined weak syms won't yet be marked as dynamic. */
e8b09b87 16288 if (htab->root.dynamic_sections_created && h->dynindx == -1 && !h->forced_local
6c699715 16289 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16290 {
c152c796 16291 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16292 return FALSE;
16293 }
16294
90c14f0c 16295 if (htab->root.target_os != is_symbian)
e5a52504 16296 {
362d30a1 16297 s = htab->root.sgot;
e5a52504 16298 h->got.offset = s->size;
ba93b8ac
DJ		 16299
16300 if (tls_type == GOT_UNKNOWN)
16301 abort ();
16302
16303 if (tls_type == GOT_NORMAL)
16304 /* Non-TLS symbols need one GOT slot. */
16305 s->size += 4;
16306 else
16307 {
99059e56
RM		 16308 if (tls_type & GOT_TLS_GDESC)
16309 {
0855e32b 16310 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 16311 eh->tlsdesc_got
0855e32b
NS		 16312 = (htab->root.sgotplt->size
16313 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 16314 htab->root.sgotplt->size += 8;
16315 h->got.offset = (bfd_vma) -2;
34e77a92 16316 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16317 reloc in the middle of .got.plt. */
99059e56
RM		 16318 htab->num_tls_desc++;
16319 }
0855e32b 16320
ba93b8ac 16321 if (tls_type & GOT_TLS_GD)
0855e32b 16322 {
5c5a4843
CL		 16323 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16324 consecutive GOT slots. If the symbol is both GD
16325 and GDESC, got.offset may have been
16326 overwritten. */
0855e32b
NS		 16327 h->got.offset = s->size;
16328 s->size += 8;
16329 }
16330
ba93b8ac 16331 if (tls_type & GOT_TLS_IE)
5c5a4843
CL		 16332 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16333 slot. */
ba93b8ac
DJ		 16334 s->size += 4;
16335 }
16336
e5a52504 16337 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 16338
16339 indx = 0;
0e1862bb
L		 16340 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
16341 bfd_link_pic (info),
16342 h)
16343 && (!bfd_link_pic (info)
ba93b8ac
DJ		 16344 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16345 indx = h->dynindx;
16346
16347 if (tls_type != GOT_NORMAL
9cb09e33 16348 && (bfd_link_dll (info) || indx != 0)
ba93b8ac
DJ		 16349 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16350 || h->root.type != bfd_link_hash_undefweak))
16351 {
16352 if (tls_type & GOT_TLS_IE)
47beaa6a 16353 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16354
16355 if (tls_type & GOT_TLS_GD)
47beaa6a 16356 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16357
b38cadfb 16358 if (tls_type & GOT_TLS_GDESC)
0855e32b 16359 {
47beaa6a 16360 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 16361 /* GDESC needs a trampoline to jump to. */
16362 htab->tls_trampoline = -1;
16363 }
16364
16365 /* Only GD needs it. GDESC just emits one relocation per
16366 2 entries. */
b38cadfb 16367 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 16368 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16369 }
e8b09b87
CL		 16370 else if (((indx != -1) || htab->fdpic_p)
16371 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 16372 {
16373 if (htab->root.dynamic_sections_created)
16374 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16375 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16376 }
34e77a92
RS		 16377 else if (h->type == STT_GNU_IFUNC
16378 && eh->plt.noncall_refcount == 0)
16379 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16380 they all resolve dynamically instead. Reserve room for the
16381 GOT entry's R_ARM_IRELATIVE relocation. */
16382 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb 16383 else if (bfd_link_pic (info)
7f026732 16384 && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
b436d854 16385 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 16386 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16387 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16388 /* Reserve room for rofixup for FDPIC executable. */
16389 /* TLS relocs do not need space since they are completely
16390 resolved. */
16391 htab->srofixup->size += 4;
e5a52504 16392 }
5e681ec4
PB		 16393 }
16394 else
16395 h->got.offset = (bfd_vma) -1;
16396
e8b09b87
CL		 16397 /* FDPIC support. */
16398 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16399 {
16400 /* Symbol musn't be exported. */
16401 if (h->dynindx != -1)
16402 abort();
16403
16404 /* We only allocate one function descriptor with its associated relocation. */
16405 if (eh->fdpic_cnts.funcdesc_offset == -1)
16406 {
16407 asection *s = htab->root.sgot;
16408
16409 eh->fdpic_cnts.funcdesc_offset = s->size;
16410 s->size += 8;
16411 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16412 if (bfd_link_pic(info))
16413 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16414 else
16415 htab->srofixup->size += 8;
16416 }
16417 }
16418
16419 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16420 {
16421 asection *s = htab->root.sgot;
16422
16423 if (htab->root.dynamic_sections_created && h->dynindx == -1
16424 && !h->forced_local)
16425 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16426 return FALSE;
16427
16428 if (h->dynindx == -1)
16429 {
16430 /* We only allocate one function descriptor with its associated relocation. q */
16431 if (eh->fdpic_cnts.funcdesc_offset == -1)
16432 {
16433
16434 eh->fdpic_cnts.funcdesc_offset = s->size;
16435 s->size += 8;
16436 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16437 if (bfd_link_pic(info))
16438 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16439 else
16440 htab->srofixup->size += 8;
16441 }
16442 }
16443
16444 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16445 R_ARM_RELATIVE/rofixup relocation on it. */
16446 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16447 s->size += 4;
16448 if (h->dynindx == -1 && !bfd_link_pic(info))
4b24dd1a 16449 htab->srofixup->size += 4;
e8b09b87 16450 else
4b24dd1a 16451 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16452 }
16453
16454 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16455 {
16456 if (htab->root.dynamic_sections_created && h->dynindx == -1
16457 && !h->forced_local)
16458 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16459 return FALSE;
16460
16461 if (h->dynindx == -1)
16462 {
16463 /* We only allocate one function descriptor with its associated relocation. */
16464 if (eh->fdpic_cnts.funcdesc_offset == -1)
16465 {
16466 asection *s = htab->root.sgot;
16467
16468 eh->fdpic_cnts.funcdesc_offset = s->size;
16469 s->size += 8;
16470 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16471 if (bfd_link_pic(info))
16472 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16473 else
16474 htab->srofixup->size += 8;
16475 }
16476 }
16477 if (h->dynindx == -1 && !bfd_link_pic(info))
16478 {
16479 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16480 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16481 }
16482 else
16483 {
16484 /* Will need one dynamic reloc per reference. will be either
16485 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16486 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16487 eh->fdpic_cnts.funcdesc_cnt);
16488 }
16489 }
16490
a4fd1a8e
PB		 16491 /* Allocate stubs for exported Thumb functions on v4t. */
16492 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 16493 && h->def_regular
39d911fc 16494 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 16495 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16496 {
16497 struct elf_link_hash_entry * th;
16498 struct bfd_link_hash_entry * bh;
16499 struct elf_link_hash_entry * myh;
16500 char name[1024];
16501 asection *s;
16502 bh = NULL;
16503 /* Create a new symbol to regist the real location of the function. */
16504 s = h->root.u.def.section;
906e58ca 16505 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 16506 _bfd_generic_link_add_one_symbol (info, s->owner,
16507 name, BSF_GLOBAL, s,
16508 h->root.u.def.value,
16509 NULL, TRUE, FALSE, &bh);
16510
16511 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 16512 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 16513 myh->forced_local = 1;
39d911fc 16514 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 16515 eh->export_glue = myh;
16516 th = record_arm_to_thumb_glue (info, h);
16517 /* Point the symbol at the stub. */
16518 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 16519 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 16520 h->root.u.def.section = th->root.u.def.section;
16521 h->root.u.def.value = th->root.u.def.value & ~1;
16522 }
16523
190eb1dd 16524 if (h->dyn_relocs == NULL)
5e681ec4
PB		 16525 return TRUE;
16526
16527 /* In the shared -Bsymbolic case, discard space allocated for
16528 dynamic pc-relative relocs against symbols which turn out to be
16529 defined in regular objects. For the normal shared case, discard
16530 space for pc-relative relocs that have become local due to symbol
16531 visibility changes. */
16532
e8b09b87 16533 if (bfd_link_pic (info) || htab->root.is_relocatable_executable || htab->fdpic_p)
5e681ec4 16534 {
469a3493
RM		 16535 /* Relocs that use pc_count are PC-relative forms, which will appear
16536 on something like ".long foo - ." or "movw REG, foo - .". We want
16537 calls to protected symbols to resolve directly to the function
16538 rather than going via the plt. If people want function pointer
16539 comparisons to work as expected then they should avoid writing
16540 assembly like ".long foo - .". */
ba93b8ac
DJ		 16541 if (SYMBOL_CALLS_LOCAL (info, h))
16542 {
0bdcacaf 16543 struct elf_dyn_relocs **pp;
ba93b8ac 16544
190eb1dd 16545 for (pp = &h->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 16546 {
16547 p->count -= p->pc_count;
16548 p->pc_count = 0;
16549 if (p->count == 0)
16550 *pp = p->next;
16551 else
16552 pp = &p->next;
16553 }
16554 }
16555
90c14f0c 16556 if (htab->root.target_os == is_vxworks)
3348747a 16557 {
0bdcacaf 16558 struct elf_dyn_relocs **pp;
3348747a 16559
190eb1dd 16560 for (pp = &h->dyn_relocs; (p = *pp) != NULL; )
3348747a 16561 {
0bdcacaf 16562 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 16563 *pp = p->next;
16564 else
16565 pp = &p->next;
16566 }
16567 }
16568
ba93b8ac 16569 /* Also discard relocs on undefined weak syms with non-default
99059e56 16570 visibility. */
190eb1dd 16571 if (h->dyn_relocs != NULL
5e681ec4 16572 && h->root.type == bfd_link_hash_undefweak)
22d606e9 16573 {
95b03e4a
L		 16574 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16575 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
190eb1dd 16576 h->dyn_relocs = NULL;
22d606e9
AM		 16577
16578 /* Make sure undefined weak symbols are output as a dynamic
16579 symbol in PIEs. */
e8b09b87 16580 else if (htab->root.dynamic_sections_created && h->dynindx == -1
22d606e9
AM		 16581 && !h->forced_local)
16582 {
16583 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16584 return FALSE;
16585 }
16586 }
16587
67687978
PB		 16588 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16589 && h->root.type == bfd_link_hash_new)
16590 {
16591 /* Output absolute symbols so that we can create relocations
16592 against them. For normal symbols we output a relocation
16593 against the section that contains them. */
16594 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16595 return FALSE;
16596 }
16597
5e681ec4
PB		 16598 }
16599 else
16600 {
16601 /* For the non-shared case, discard space for relocs against
16602 symbols which turn out to need copy relocs or are not
16603 dynamic. */
16604
f5385ebf
AM		 16605 if (!h->non_got_ref
16606 && ((h->def_dynamic
16607 && !h->def_regular)
5e681ec4
PB		 16608 || (htab->root.dynamic_sections_created
16609 && (h->root.type == bfd_link_hash_undefweak
16610 || h->root.type == bfd_link_hash_undefined))))
16611 {
16612 /* Make sure this symbol is output as a dynamic symbol.
16613 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16614 if (h->dynindx == -1 && !h->forced_local
16615 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16616 {
c152c796 16617 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16618 return FALSE;
16619 }
16620
16621 /* If that succeeded, we know we'll be keeping all the
16622 relocs. */
16623 if (h->dynindx != -1)
16624 goto keep;
16625 }
16626
190eb1dd 16627 h->dyn_relocs = NULL;
5e681ec4
PB		 16628
16629 keep: ;
16630 }
16631
16632 /* Finally, allocate space. */
190eb1dd 16633 for (p = h->dyn_relocs; p != NULL; p = p->next)
5e681ec4 16634 {
0bdcacaf 16635 asection *sreloc = elf_section_data (p->sec)->sreloc;
e8b09b87 16636
34e77a92
RS		 16637 if (h->type == STT_GNU_IFUNC
16638 && eh->plt.noncall_refcount == 0
16639 && SYMBOL_REFERENCES_LOCAL (info, h))
16640 elf32_arm_allocate_irelocs (info, sreloc, p->count);
e8b09b87
CL		 16641 else if (h->dynindx != -1 && (!bfd_link_pic(info) || !info->symbolic || !h->def_regular))
16642 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16643 else if (htab->fdpic_p && !bfd_link_pic(info))
16644 htab->srofixup->size += 4 * p->count;
34e77a92
RS		 16645 else
16646 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 16647 }
16648
16649 return TRUE;
16650}
16651
d504ffc8
DJ		 16652void
16653bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16654 int byteswap_code)
16655{
16656 struct elf32_arm_link_hash_table *globals;
16657
16658 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16659 if (globals == NULL)
16660 return;
16661
d504ffc8
DJ		 16662 globals->byteswap_code = byteswap_code;
16663}
16664
252b5132
RH		 16665/* Set the sizes of the dynamic sections. */
16666
b34976b6 16667static bfd_boolean
57e8b36a
NC		 16668elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16669 struct bfd_link_info * info)
252b5132
RH		 16670{
16671 bfd * dynobj;
16672 asection * s;
b34976b6 16673 bfd_boolean relocs;
5e681ec4
PB		 16674 bfd *ibfd;
16675 struct elf32_arm_link_hash_table *htab;
252b5132 16676
5e681ec4 16677 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16678 if (htab == NULL)
16679 return FALSE;
16680
252b5132
RH		 16681 dynobj = elf_hash_table (info)->dynobj;
16682 BFD_ASSERT (dynobj != NULL);
39b41c9c 16683 check_use_blx (htab);
252b5132
RH		 16684
16685 if (elf_hash_table (info)->dynamic_sections_created)
16686 {
16687 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 16688 if (bfd_link_executable (info) && !info->nointerp)
252b5132 16689 {
3d4d4302 16690 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 16691 BFD_ASSERT (s != NULL);
eea6121a 16692 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 16693 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16694 }
16695 }
5e681ec4
PB		 16696
16697 /* Set up .got offsets for local syms, and space for local dynamic
16698 relocs. */
c72f2fb2 16699 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 16700 {
5e681ec4
PB		 16701 bfd_signed_vma *local_got;
16702 bfd_signed_vma *end_local_got;
34e77a92 16703 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 16704 char *local_tls_type;
0855e32b 16705 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 16706 bfd_size_type locsymcount;
16707 Elf_Internal_Shdr *symtab_hdr;
16708 asection *srel;
34e77a92 16709 unsigned int symndx;
e8b09b87 16710 struct fdpic_local *local_fdpic_cnts;
5e681ec4 16711
0ffa91dd 16712 if (! is_arm_elf (ibfd))
5e681ec4
PB		 16713 continue;
16714
16715 for (s = ibfd->sections; s != NULL; s = s->next)
16716 {
0bdcacaf 16717 struct elf_dyn_relocs *p;
5e681ec4 16718
0bdcacaf 16719 for (p = (struct elf_dyn_relocs *)
99059e56 16720 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 16721 {
0bdcacaf
RS		 16722 if (!bfd_is_abs_section (p->sec)
16723 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 16724 {
16725 /* Input section has been discarded, either because
16726 it is a copy of a linkonce section or due to
16727 linker script /DISCARD/, so we'll be discarding
16728 the relocs too. */
16729 }
90c14f0c 16730 else if (htab->root.target_os == is_vxworks
0bdcacaf 16731 && strcmp (p->sec->output_section->name,
3348747a
NS		 16732 ".tls_vars") == 0)
16733 {
16734 /* Relocations in vxworks .tls_vars sections are
16735 handled specially by the loader. */
16736 }
5e681ec4
PB		 16737 else if (p->count != 0)
16738 {
0bdcacaf 16739 srel = elf_section_data (p->sec)->sreloc;
e8b09b87
CL		 16740 if (htab->fdpic_p && !bfd_link_pic(info))
16741 htab->srofixup->size += 4 * p->count;
16742 else
16743 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 16744 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 16745 info->flags |= DF_TEXTREL;
16746 }
16747 }
16748 }
16749
16750 local_got = elf_local_got_refcounts (ibfd);
16751 if (!local_got)
16752 continue;
16753
0ffa91dd 16754 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 16755 locsymcount = symtab_hdr->sh_info;
16756 end_local_got = local_got + locsymcount;
34e77a92 16757 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 16758 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 16759 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
e8b09b87 16760 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
34e77a92 16761 symndx = 0;
362d30a1
RS		 16762 s = htab->root.sgot;
16763 srel = htab->root.srelgot;
0855e32b 16764 for (; local_got < end_local_got;
34e77a92 16765 ++local_got, ++local_iplt_ptr, ++local_tls_type,
e8b09b87 16766 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
5e681ec4 16767 {
0855e32b 16768 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92 16769 local_iplt = *local_iplt_ptr;
e8b09b87
CL		 16770
16771 /* FDPIC support. */
16772 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16773 {
16774 if (local_fdpic_cnts->funcdesc_offset == -1)
16775 {
16776 local_fdpic_cnts->funcdesc_offset = s->size;
16777 s->size += 8;
16778
16779 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16780 if (bfd_link_pic(info))
16781 elf32_arm_allocate_dynrelocs (info, srel, 1);
16782 else
16783 htab->srofixup->size += 8;
16784 }
16785 }
16786
16787 if (local_fdpic_cnts->funcdesc_cnt > 0)
16788 {
16789 if (local_fdpic_cnts->funcdesc_offset == -1)
16790 {
16791 local_fdpic_cnts->funcdesc_offset = s->size;
16792 s->size += 8;
16793
16794 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16795 if (bfd_link_pic(info))
16796 elf32_arm_allocate_dynrelocs (info, srel, 1);
16797 else
16798 htab->srofixup->size += 8;
16799 }
16800
16801 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16802 if (bfd_link_pic(info))
16803 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16804 else
16805 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16806 }
16807
34e77a92
RS		 16808 if (local_iplt != NULL)
16809 {
16810 struct elf_dyn_relocs *p;
16811
16812 if (local_iplt->root.refcount > 0)
16813 {
16814 elf32_arm_allocate_plt_entry (info, TRUE,
16815 &local_iplt->root,
16816 &local_iplt->arm);
16817 if (local_iplt->arm.noncall_refcount == 0)
16818 /* All references to the PLT are calls, so all
16819 non-call references can resolve directly to the
16820 run-time target. This means that the .got entry
16821 would be the same as the .igot.plt entry, so there's
16822 no point creating both. */
16823 *local_got = 0;
16824 }
16825 else
16826 {
16827 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
16828 local_iplt->root.offset = (bfd_vma) -1;
16829 }
16830
16831 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
16832 {
16833 asection *psrel;
16834
16835 psrel = elf_section_data (p->sec)->sreloc;
16836 if (local_iplt->arm.noncall_refcount == 0)
16837 elf32_arm_allocate_irelocs (info, psrel, p->count);
16838 else
16839 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
16840 }
16841 }
5e681ec4
PB		 16842 if (*local_got > 0)
16843 {
34e77a92
RS		 16844 Elf_Internal_Sym *isym;
16845
eea6121a 16846 *local_got = s->size;
ba93b8ac
DJ		 16847 if (*local_tls_type & GOT_TLS_GD)
16848 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16849 s->size += 8;
0855e32b
NS		 16850 if (*local_tls_type & GOT_TLS_GDESC)
16851 {
16852 *local_tlsdesc_gotent = htab->root.sgotplt->size
16853 - elf32_arm_compute_jump_table_size (htab);
16854 htab->root.sgotplt->size += 8;
16855 *local_got = (bfd_vma) -2;
34e77a92 16856 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16857 reloc in the middle of .got.plt. */
99059e56 16858 htab->num_tls_desc++;
0855e32b 16859 }
ba93b8ac
DJ		 16860 if (*local_tls_type & GOT_TLS_IE)
16861 s->size += 4;
ba93b8ac 16862
0855e32b
NS		 16863 if (*local_tls_type & GOT_NORMAL)
16864 {
16865 /* If the symbol is both GD and GDESC, *local_got
16866 may have been overwritten. */
16867 *local_got = s->size;
16868 s->size += 4;
16869 }
16870
f1dfbfdb
L		 16871 isym = bfd_sym_from_r_symndx (&htab->root.sym_cache, ibfd,
16872 symndx);
34e77a92
RS		 16873 if (isym == NULL)
16874 return FALSE;
16875
16876 /* If all references to an STT_GNU_IFUNC PLT are calls,
16877 then all non-call references, including this GOT entry,
16878 resolve directly to the run-time target. */
16879 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
16880 && (local_iplt == NULL
16881 || local_iplt->arm.noncall_refcount == 0))
16882 elf32_arm_allocate_irelocs (info, srel, 1);
e8b09b87 16883 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
0855e32b 16884 {
e8b09b87 16885 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
3064e1ff 16886 elf32_arm_allocate_dynrelocs (info, srel, 1);
e8b09b87
CL		 16887 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
16888 htab->srofixup->size += 4;
99059e56 16889
e8b09b87
CL		 16890 if ((bfd_link_pic (info) || htab->fdpic_p)
16891 && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 16892 {
16893 elf32_arm_allocate_dynrelocs (info,
16894 htab->root.srelplt, 1);
16895 htab->tls_trampoline = -1;
16896 }
0855e32b 16897 }
5e681ec4
PB		 16898 }
16899 else
16900 *local_got = (bfd_vma) -1;
16901 }
252b5132
RH		 16902 }
16903
ba93b8ac
DJ		 16904 if (htab->tls_ldm_got.refcount > 0)
16905 {
16906 /* Allocate two GOT entries and one dynamic relocation (if necessary)
5c5a4843 16907 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
362d30a1
RS		 16908 htab->tls_ldm_got.offset = htab->root.sgot->size;
16909 htab->root.sgot->size += 8;
0e1862bb 16910 if (bfd_link_pic (info))
47beaa6a 16911 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16912 }
16913 else
16914 htab->tls_ldm_got.offset = -1;
16915
e8b09b87
CL		 16916 /* At the very end of the .rofixup section is a pointer to the GOT,
16917 reserve space for it. */
16918 if (htab->fdpic_p && htab->srofixup != NULL)
16919 htab->srofixup->size += 4;
16920
5e681ec4
PB		 16921 /* Allocate global sym .plt and .got entries, and space for global
16922 sym dynamic relocs. */
47beaa6a 16923 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 16924
d504ffc8 16925 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 16926 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 16927 {
0ffa91dd 16928 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 16929 continue;
16930
c7b8f16e
JB		 16931 /* Initialise mapping tables for code/data. */
16932 bfd_elf32_arm_init_maps (ibfd);
906e58ca 16933
c7b8f16e 16934 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 16935 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
16936 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 16937 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 16938 }
d504ffc8 16939
3e6b1042
DJ		 16940 /* Allocate space for the glue sections now that we've sized them. */
16941 bfd_elf32_arm_allocate_interworking_sections (info);
16942
0855e32b
NS		 16943 /* For every jump slot reserved in the sgotplt, reloc_count is
16944 incremented. However, when we reserve space for TLS descriptors,
16945 it's not incremented, so in order to compute the space reserved
16946 for them, it suffices to multiply the reloc count by the jump
16947 slot size. */
16948 if (htab->root.srelplt)
16949 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
16950
16951 if (htab->tls_trampoline)
16952 {
16953 if (htab->root.splt->size == 0)
16954 htab->root.splt->size += htab->plt_header_size;
b38cadfb 16955
0855e32b
NS		 16956 htab->tls_trampoline = htab->root.splt->size;
16957 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 16958
0855e32b 16959 /* If we're not using lazy TLS relocations, don't generate the
99059e56 16960 PLT and GOT entries they require. */
9bcc30e4
L		 16961 if ((info->flags & DF_BIND_NOW))
16962 htab->root.tlsdesc_plt = 0;
16963 else
0855e32b 16964 {
9bcc30e4 16965 htab->root.tlsdesc_got = htab->root.sgot->size;
0855e32b
NS		 16966 htab->root.sgot->size += 4;
16967
9bcc30e4 16968 htab->root.tlsdesc_plt = htab->root.splt->size;
0855e32b
NS		 16969 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
16970 }
16971 }
16972
252b5132
RH		 16973 /* The check_relocs and adjust_dynamic_symbol entry points have
16974 determined the sizes of the various dynamic sections. Allocate
16975 memory for them. */
b34976b6 16976 relocs = FALSE;
252b5132
RH		 16977 for (s = dynobj->sections; s != NULL; s = s->next)
16978 {
16979 const char * name;
252b5132
RH		 16980
16981 if ((s->flags & SEC_LINKER_CREATED) == 0)
16982 continue;
16983
16984 /* It's OK to base decisions on the section name, because none
16985 of the dynobj section names depend upon the input files. */
fd361982 16986 name = bfd_section_name (s);
252b5132 16987
34e77a92 16988 if (s == htab->root.splt)
252b5132 16989 {
c456f082 16990 /* Remember whether there is a PLT. */
3084d7a2 16991 ;
252b5132 16992 }
0112cd26 16993 else if (CONST_STRNEQ (name, ".rel"))
252b5132 16994 {
c456f082 16995 if (s->size != 0)
252b5132 16996 {
252b5132 16997 /* Remember whether there are any reloc sections other
00a97672 16998 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 16999 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 17000 relocs = TRUE;
252b5132
RH		 17001
17002 /* We use the reloc_count field as a counter if we need
17003 to copy relocs into the output file. */
17004 s->reloc_count = 0;
17005 }
17006 }
34e77a92
RS		 17007 else if (s != htab->root.sgot
17008 && s != htab->root.sgotplt
17009 && s != htab->root.iplt
17010 && s != htab->root.igotplt
5474d94f 17011 && s != htab->root.sdynbss
e8b09b87
CL		 17012 && s != htab->root.sdynrelro
17013 && s != htab->srofixup)
252b5132
RH		 17014 {
17015 /* It's not one of our sections, so don't allocate space. */
17016 continue;
17017 }
17018
c456f082 17019 if (s->size == 0)
252b5132 17020 {
c456f082 17021 /* If we don't need this section, strip it from the
00a97672
RS		 17022 output file. This is mostly to handle .rel(a).bss and
17023 .rel(a).plt. We must create both sections in
c456f082
AM		 17024 create_dynamic_sections, because they must be created
17025 before the linker maps input sections to output
17026 sections. The linker does that before
17027 adjust_dynamic_symbol is called, and it is that
17028 function which decides whether anything needs to go
17029 into these sections. */
8423293d 17030 s->flags |= SEC_EXCLUDE;
252b5132
RH		 17031 continue;
17032 }
17033
c456f082
AM		 17034 if ((s->flags & SEC_HAS_CONTENTS) == 0)
17035 continue;
17036
252b5132 17037 /* Allocate memory for the section contents. */
21d799b5 17038 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 17039 if (s->contents == NULL)
b34976b6 17040 return FALSE;
252b5132
RH		 17041 }
17042
3084d7a2
L		 17043 return _bfd_elf_maybe_vxworks_add_dynamic_tags (output_bfd, info,
17044 relocs);
252b5132
RH		 17045}
17046
0855e32b
NS		 17047/* Size sections even though they're not dynamic. We use it to setup
17048 _TLS_MODULE_BASE_, if needed. */
17049
17050static bfd_boolean
17051elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 17052 struct bfd_link_info *info)
0855e32b
NS		 17053{
17054 asection *tls_sec;
cb10292c
CL		 17055 struct elf32_arm_link_hash_table *htab;
17056
17057 htab = elf32_arm_hash_table (info);
0855e32b 17058
0e1862bb 17059 if (bfd_link_relocatable (info))
0855e32b
NS		 17060 return TRUE;
17061
17062 tls_sec = elf_hash_table (info)->tls_sec;
17063
17064 if (tls_sec)
17065 {
17066 struct elf_link_hash_entry *tlsbase;
17067
17068 tlsbase = elf_link_hash_lookup
17069 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
17070
17071 if (tlsbase)
99059e56
RM		 17072 {
17073 struct bfd_link_hash_entry *bh = NULL;
0855e32b 17074 const struct elf_backend_data *bed
99059e56 17075 = get_elf_backend_data (output_bfd);
0855e32b 17076
99059e56 17077 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 17078 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
17079 tls_sec, 0, NULL, FALSE,
17080 bed->collect, &bh)))
17081 return FALSE;
b38cadfb 17082
99059e56
RM		 17083 tlsbase->type = STT_TLS;
17084 tlsbase = (struct elf_link_hash_entry *)bh;
17085 tlsbase->def_regular = 1;
17086 tlsbase->other = STV_HIDDEN;
17087 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 17088 }
17089 }
cb10292c
CL		 17090
17091 if (htab->fdpic_p && !bfd_link_relocatable (info)
17092 && !bfd_elf_stack_segment_size (output_bfd, info,
17093 "__stacksize", DEFAULT_STACK_SIZE))
17094 return FALSE;
17095
0855e32b
NS		 17096 return TRUE;
17097}
17098
252b5132
RH		 17099/* Finish up dynamic symbol handling. We set the contents of various
17100 dynamic sections here. */
17101
b34976b6 17102static bfd_boolean
906e58ca
NC		 17103elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17104 struct bfd_link_info * info,
17105 struct elf_link_hash_entry * h,
17106 Elf_Internal_Sym * sym)
252b5132 17107{
e5a52504 17108 struct elf32_arm_link_hash_table *htab;
b7693d02 17109 struct elf32_arm_link_hash_entry *eh;
252b5132 17110
e5a52504 17111 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17112 if (htab == NULL)
17113 return FALSE;
17114
b7693d02 17115 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 17116
17117 if (h->plt.offset != (bfd_vma) -1)
17118 {
34e77a92 17119 if (!eh->is_iplt)
e5a52504 17120 {
34e77a92 17121 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 17122 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17123 h->dynindx, 0))
17124 return FALSE;
e5a52504 17125 }
57e8b36a 17126
f5385ebf 17127 if (!h->def_regular)
252b5132
RH		 17128 {
17129 /* Mark the symbol as undefined, rather than as defined in
3a635617 17130 the .plt section. */
252b5132 17131 sym->st_shndx = SHN_UNDEF;
3a635617 17132 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 17133 Otherwise, the PLT entry would provide a definition for
17134 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 17135 and so the symbol would never be NULL. Leave the value if
17136 there were any relocations where pointer equality matters
17137 (this is a clue for the dynamic linker, to make function
17138 pointer comparisons work between an application and shared
17139 library). */
97323ad1 17140 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 17141 sym->st_value = 0;
252b5132 17142 }
34e77a92
RS		 17143 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17144 {
17145 /* At least one non-call relocation references this .iplt entry,
17146 so the .iplt entry is the function's canonical address. */
17147 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 17148 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 17149 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17150 (output_bfd, htab->root.iplt->output_section));
17151 sym->st_value = (h->plt.offset
17152 + htab->root.iplt->output_section->vma
17153 + htab->root.iplt->output_offset);
17154 }
252b5132
RH		 17155 }
17156
f5385ebf 17157 if (h->needs_copy)
252b5132
RH		 17158 {
17159 asection * s;
947216bf 17160 Elf_Internal_Rela rel;
252b5132
RH		 17161
17162 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 17163 BFD_ASSERT (h->dynindx != -1
17164 && (h->root.type == bfd_link_hash_defined
17165 || h->root.type == bfd_link_hash_defweak));
17166
00a97672 17167 rel.r_addend = 0;
252b5132
RH		 17168 rel.r_offset = (h->root.u.def.value
17169 + h->root.u.def.section->output_section->vma
17170 + h->root.u.def.section->output_offset);
17171 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 17172 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 17173 s = htab->root.sreldynrelro;
17174 else
17175 s = htab->root.srelbss;
47beaa6a 17176 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 17177 }
17178
00a97672 17179 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
fac7bd64
CL		 17180 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17181 it is relative to the ".got" section. */
9637f6ef 17182 if (h == htab->root.hdynamic
90c14f0c
L		 17183 || (!htab->fdpic_p
17184 && htab->root.target_os != is_vxworks
17185 && h == htab->root.hgot))
252b5132
RH		 17186 sym->st_shndx = SHN_ABS;
17187
b34976b6 17188 return TRUE;
252b5132
RH		 17189}
17190
0855e32b
NS		 17191static void
17192arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17193 void *contents,
17194 const unsigned long *template, unsigned count)
17195{
17196 unsigned ix;
b38cadfb 17197
0855e32b
NS		 17198 for (ix = 0; ix != count; ix++)
17199 {
17200 unsigned long insn = template[ix];
17201
17202 /* Emit mov pc,rx if bx is not permitted. */
17203 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17204 insn = (insn & 0xf000000f) | 0x01a0f000;
17205 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17206 }
17207}
17208
99059e56
RM		 17209/* Install the special first PLT entry for elf32-arm-nacl. Unlike
17210 other variants, NaCl needs this entry in a static executable's
17211 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17212 zero. For .iplt really only the last bundle is useful, and .iplt
17213 could have a shorter first entry, with each individual PLT entry's
17214 relative branch calculated differently so it targets the last
17215 bundle instead of the instruction before it (labelled .Lplt_tail
17216 above). But it's simpler to keep the size and layout of PLT0
17217 consistent with the dynamic case, at the cost of some dead code at
17218 the start of .iplt and the one dead store to the stack at the start
17219 of .Lplt_tail. */
17220static void
17221arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17222 asection *plt, bfd_vma got_displacement)
17223{
17224 unsigned int i;
17225
17226 put_arm_insn (htab, output_bfd,
17227 elf32_arm_nacl_plt0_entry[0]
17228 | arm_movw_immediate (got_displacement),
17229 plt->contents + 0);
17230 put_arm_insn (htab, output_bfd,
17231 elf32_arm_nacl_plt0_entry[1]
17232 | arm_movt_immediate (got_displacement),
17233 plt->contents + 4);
17234
17235 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17236 put_arm_insn (htab, output_bfd,
17237 elf32_arm_nacl_plt0_entry[i],
17238 plt->contents + (i * 4));
17239}
17240
252b5132
RH		 17241/* Finish up the dynamic sections. */
17242
b34976b6 17243static bfd_boolean
57e8b36a 17244elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 17245{
17246 bfd * dynobj;
17247 asection * sgot;
17248 asection * sdyn;
4dfe6ac6
NC		 17249 struct elf32_arm_link_hash_table *htab;
17250
17251 htab = elf32_arm_hash_table (info);
17252 if (htab == NULL)
17253 return FALSE;
252b5132
RH		 17254
17255 dynobj = elf_hash_table (info)->dynobj;
17256
362d30a1 17257 sgot = htab->root.sgotplt;
894891db
NC		 17258 /* A broken linker script might have discarded the dynamic sections.
17259 Catch this here so that we do not seg-fault later on. */
17260 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17261 return FALSE;
3d4d4302 17262 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 17263
17264 if (elf_hash_table (info)->dynamic_sections_created)
17265 {
17266 asection *splt;
17267 Elf32_External_Dyn *dyncon, *dynconend;
17268
362d30a1 17269 splt = htab->root.splt;
24a1ba0f 17270 BFD_ASSERT (splt != NULL && sdyn != NULL);
90c14f0c 17271 BFD_ASSERT (htab->root.target_os == is_symbian || sgot != NULL);
252b5132
RH		 17272
17273 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 17274 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 17275
252b5132
RH		 17276 for (; dyncon < dynconend; dyncon++)
17277 {
17278 Elf_Internal_Dyn dyn;
17279 const char * name;
17280 asection * s;
17281
17282 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17283
17284 switch (dyn.d_tag)
17285 {
229fcec5
MM		 17286 unsigned int type;
17287
252b5132 17288 default:
90c14f0c 17289 if (htab->root.target_os == is_vxworks
7a2b07ff
NS		 17290 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17291 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 17292 break;
17293
229fcec5
MM		 17294 case DT_HASH:
17295 name = ".hash";
17296 goto get_vma_if_bpabi;
17297 case DT_STRTAB:
17298 name = ".dynstr";
17299 goto get_vma_if_bpabi;
17300 case DT_SYMTAB:
17301 name = ".dynsym";
17302 goto get_vma_if_bpabi;
c0042f5d
MM		 17303 case DT_VERSYM:
17304 name = ".gnu.version";
17305 goto get_vma_if_bpabi;
17306 case DT_VERDEF:
17307 name = ".gnu.version_d";
17308 goto get_vma_if_bpabi;
17309 case DT_VERNEED:
17310 name = ".gnu.version_r";
17311 goto get_vma_if_bpabi;
17312
252b5132 17313 case DT_PLTGOT:
90c14f0c
L		 17314 name = (htab->root.target_os == is_symbian
17315 ? ".got" : ".got.plt");
252b5132
RH		 17316 goto get_vma;
17317 case DT_JMPREL:
00a97672 17318 name = RELOC_SECTION (htab, ".plt");
252b5132 17319 get_vma:
4ade44b7 17320 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 17321 if (s == NULL)
17322 {
4eca0228 17323 _bfd_error_handler
4ade44b7 17324 (_("could not find section %s"), name);
05456594
NC		 17325 bfd_set_error (bfd_error_invalid_operation);
17326 return FALSE;
17327 }
90c14f0c 17328 if (htab->root.target_os != is_symbian)
4ade44b7 17329 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 17330 else
17331 /* In the BPABI, tags in the PT_DYNAMIC section point
17332 at the file offset, not the memory address, for the
17333 convenience of the post linker. */
4ade44b7 17334 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 17335 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17336 break;
17337
229fcec5 17338 get_vma_if_bpabi:
90c14f0c 17339 if (htab->root.target_os == is_symbian)
229fcec5
MM		 17340 goto get_vma;
17341 break;
17342
252b5132 17343 case DT_PLTRELSZ:
362d30a1 17344 s = htab->root.srelplt;
252b5132 17345 BFD_ASSERT (s != NULL);
eea6121a 17346 dyn.d_un.d_val = s->size;
252b5132
RH		 17347 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17348 break;
906e58ca 17349
252b5132 17350 case DT_RELSZ:
00a97672 17351 case DT_RELASZ:
229fcec5
MM		 17352 case DT_REL:
17353 case DT_RELA:
229fcec5
MM		 17354 /* In the BPABI, the DT_REL tag must point at the file
17355 offset, not the VMA, of the first relocation
17356 section. So, we use code similar to that in
17357 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 17358 relocation section, since relocation sections are
17359 never allocated under the BPABI. PLT relocs are also
17360 included. */
90c14f0c 17361 if (htab->root.target_os == is_symbian)
229fcec5
MM		 17362 {
17363 unsigned int i;
17364 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
17365 ? SHT_REL : SHT_RELA);
17366 dyn.d_un.d_val = 0;
17367 for (i = 1; i < elf_numsections (output_bfd); i++)
17368 {
906e58ca 17369 Elf_Internal_Shdr *hdr
229fcec5
MM		 17370 = elf_elfsections (output_bfd)[i];
17371 if (hdr->sh_type == type)
17372 {
906e58ca 17373 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 17374 || dyn.d_tag == DT_RELASZ)
17375 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 17376 else if ((ufile_ptr) hdr->sh_offset
17377 <= dyn.d_un.d_val - 1)
229fcec5
MM		 17378 dyn.d_un.d_val = hdr->sh_offset;
17379 }
17380 }
17381 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17382 }
252b5132 17383 break;
88f7bcd5 17384
0855e32b 17385 case DT_TLSDESC_PLT:
99059e56 17386 s = htab->root.splt;
0855e32b 17387 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
9bcc30e4 17388 + htab->root.tlsdesc_plt);
0855e32b
NS		 17389 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17390 break;
17391
17392 case DT_TLSDESC_GOT:
99059e56 17393 s = htab->root.sgot;
0855e32b 17394 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
9bcc30e4 17395 + htab->root.tlsdesc_got);
0855e32b
NS		 17396 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17397 break;
17398
88f7bcd5
NC		 17399 /* Set the bottom bit of DT_INIT/FINI if the
17400 corresponding function is Thumb. */
17401 case DT_INIT:
17402 name = info->init_function;
17403 goto get_sym;
17404 case DT_FINI:
17405 name = info->fini_function;
17406 get_sym:
17407 /* If it wasn't set by elf_bfd_final_link
4cc11e76 17408 then there is nothing to adjust. */
88f7bcd5
NC		 17409 if (dyn.d_un.d_val != 0)
17410 {
17411 struct elf_link_hash_entry * eh;
17412
17413 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 17414 FALSE, FALSE, TRUE);
39d911fc
TP		 17415 if (eh != NULL
17416 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17417 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 17418 {
17419 dyn.d_un.d_val |= 1;
b34976b6 17420 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 17421 }
17422 }
17423 break;
252b5132
RH		 17424 }
17425 }
17426
24a1ba0f 17427 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 17428 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 17429 {
00a97672
RS		 17430 const bfd_vma *plt0_entry;
17431 bfd_vma got_address, plt_address, got_displacement;
17432
17433 /* Calculate the addresses of the GOT and PLT. */
17434 got_address = sgot->output_section->vma + sgot->output_offset;
17435 plt_address = splt->output_section->vma + splt->output_offset;
17436
90c14f0c 17437 if (htab->root.target_os == is_vxworks)
00a97672
RS		 17438 {
17439 /* The VxWorks GOT is relocated by the dynamic linker.
17440 Therefore, we must emit relocations rather than simply
17441 computing the values now. */
17442 Elf_Internal_Rela rel;
17443
17444 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 17445 put_arm_insn (htab, output_bfd, plt0_entry[0],
17446 splt->contents + 0);
17447 put_arm_insn (htab, output_bfd, plt0_entry[1],
17448 splt->contents + 4);
17449 put_arm_insn (htab, output_bfd, plt0_entry[2],
17450 splt->contents + 8);
00a97672
RS		 17451 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17452
8029a119 17453 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 17454 rel.r_offset = plt_address + 12;
17455 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17456 rel.r_addend = 0;
17457 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17458 htab->srelplt2->contents);
17459 }
90c14f0c 17460 else if (htab->root.target_os == is_nacl)
99059e56
RM		 17461 arm_nacl_put_plt0 (htab, output_bfd, splt,
17462 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 17463 else if (using_thumb_only (htab))
17464 {
17465 got_displacement = got_address - (plt_address + 12);
17466
17467 plt0_entry = elf32_thumb2_plt0_entry;
17468 put_arm_insn (htab, output_bfd, plt0_entry[0],
17469 splt->contents + 0);
17470 put_arm_insn (htab, output_bfd, plt0_entry[1],
17471 splt->contents + 4);
17472 put_arm_insn (htab, output_bfd, plt0_entry[2],
17473 splt->contents + 8);
17474
17475 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17476 }
00a97672
RS		 17477 else
17478 {
17479 got_displacement = got_address - (plt_address + 16);
17480
17481 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 17482 put_arm_insn (htab, output_bfd, plt0_entry[0],
17483 splt->contents + 0);
17484 put_arm_insn (htab, output_bfd, plt0_entry[1],
17485 splt->contents + 4);
17486 put_arm_insn (htab, output_bfd, plt0_entry[2],
17487 splt->contents + 8);
17488 put_arm_insn (htab, output_bfd, plt0_entry[3],
17489 splt->contents + 12);
5e681ec4 17490
5e681ec4 17491#ifdef FOUR_WORD_PLT
00a97672
RS		 17492 /* The displacement value goes in the otherwise-unused
17493 last word of the second entry. */
17494 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 17495#else
00a97672 17496 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 17497#endif
00a97672 17498 }
f7a74f8c 17499 }
252b5132
RH		 17500
17501 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17502 really seem like the right value. */
74541ad4
AM		 17503 if (splt->output_section->owner == output_bfd)
17504 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 17505
9bcc30e4 17506 if (htab->root.tlsdesc_plt)
0855e32b
NS		 17507 {
17508 bfd_vma got_address
17509 = sgot->output_section->vma + sgot->output_offset;
17510 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17511 + htab->root.sgot->output_offset);
17512 bfd_vma plt_address
17513 = splt->output_section->vma + splt->output_offset;
17514
b38cadfb 17515 arm_put_trampoline (htab, output_bfd,
9bcc30e4 17516 splt->contents + htab->root.tlsdesc_plt,
0855e32b
NS		 17517 dl_tlsdesc_lazy_trampoline, 6);
17518
17519 bfd_put_32 (output_bfd,
9bcc30e4
L		 17520 gotplt_address + htab->root.tlsdesc_got
17521 - (plt_address + htab->root.tlsdesc_plt)
0855e32b 17522 - dl_tlsdesc_lazy_trampoline[6],
9bcc30e4 17523 splt->contents + htab->root.tlsdesc_plt + 24);
0855e32b 17524 bfd_put_32 (output_bfd,
9bcc30e4 17525 got_address - (plt_address + htab->root.tlsdesc_plt)
0855e32b 17526 - dl_tlsdesc_lazy_trampoline[7],
9bcc30e4 17527 splt->contents + htab->root.tlsdesc_plt + 24 + 4);
0855e32b
NS		 17528 }
17529
17530 if (htab->tls_trampoline)
17531 {
b38cadfb 17532 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17533 splt->contents + htab->tls_trampoline,
17534 tls_trampoline, 3);
17535#ifdef FOUR_WORD_PLT
17536 bfd_put_32 (output_bfd, 0x00000000,
17537 splt->contents + htab->tls_trampoline + 12);
b38cadfb 17538#endif
0855e32b
NS		 17539 }
17540
90c14f0c 17541 if (htab->root.target_os == is_vxworks
0e1862bb
L		 17542 && !bfd_link_pic (info)
17543 && htab->root.splt->size > 0)
00a97672
RS		 17544 {
17545 /* Correct the .rel(a).plt.unloaded relocations. They will have
17546 incorrect symbol indexes. */
17547 int num_plts;
eed62c48 17548 unsigned char *p;
00a97672 17549
362d30a1 17550 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 17551 / htab->plt_entry_size);
17552 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17553
17554 for (; num_plts; num_plts--)
17555 {
17556 Elf_Internal_Rela rel;
17557
17558 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17559 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17560 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17561 p += RELOC_SIZE (htab);
17562
17563 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17564 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17565 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17566 p += RELOC_SIZE (htab);
17567 }
17568 }
252b5132
RH		 17569 }
17570
90c14f0c
L		 17571 if (htab->root.target_os == is_nacl
17572 && htab->root.iplt != NULL
17573 && htab->root.iplt->size > 0)
99059e56
RM		 17574 /* NaCl uses a special first entry in .iplt too. */
17575 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17576
252b5132 17577 /* Fill in the first three entries in the global offset table. */
229fcec5 17578 if (sgot)
252b5132 17579 {
229fcec5
MM		 17580 if (sgot->size > 0)
17581 {
17582 if (sdyn == NULL)
17583 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17584 else
17585 bfd_put_32 (output_bfd,
17586 sdyn->output_section->vma + sdyn->output_offset,
17587 sgot->contents);
17588 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17589 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17590 }
252b5132 17591
229fcec5
MM		 17592 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17593 }
252b5132 17594
e8b09b87
CL		 17595 /* At the very end of the .rofixup section is a pointer to the GOT. */
17596 if (htab->fdpic_p && htab->srofixup != NULL)
17597 {
17598 struct elf_link_hash_entry *hgot = htab->root.hgot;
17599
17600 bfd_vma got_value = hgot->root.u.def.value
17601 + hgot->root.u.def.section->output_section->vma
17602 + hgot->root.u.def.section->output_offset;
17603
17604 arm_elf_add_rofixup(output_bfd, htab->srofixup, got_value);
17605
17606 /* Make sure we allocated and generated the same number of fixups. */
17607 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17608 }
17609
b34976b6 17610 return TRUE;
252b5132
RH		 17611}
17612
ed7e9d0b
AM		 17613static bfd_boolean
17614elf32_arm_init_file_header (bfd *abfd, struct bfd_link_info *link_info)
ba96a88f 17615{
9b485d32 17616 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 17617 struct elf32_arm_link_hash_table *globals;
ac4c9b04 17618 struct elf_segment_map *m;
ba96a88f 17619
ed7e9d0b
AM		 17620 if (!_bfd_elf_init_file_header (abfd, link_info))
17621 return FALSE;
17622
ba96a88f
NC		 17623 i_ehdrp = elf_elfheader (abfd);
17624
94a3258f
PB		 17625 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17626 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
ba96a88f 17627 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 17628
93204d3a
PB		 17629 if (link_info)
17630 {
17631 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 17632 if (globals != NULL && globals->byteswap_code)
93204d3a 17633 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 17634
17635 if (globals->fdpic_p)
17636 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 17637 }
3bfcb652
NC		 17638
17639 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17640 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17641 {
17642 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 17643 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 17644 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17645 else
17646 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17647 }
ac4c9b04
MG		 17648
17649 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 17650 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 17651 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17652 {
17653 unsigned int j;
17654
17655 if (m->count == 0)
17656 continue;
17657 for (j = 0; j < m->count; j++)
17658 {
f0728ee3 17659 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 17660 break;
17661 }
17662 if (j == m->count)
17663 {
17664 m->p_flags = PF_X;
17665 m->p_flags_valid = 1;
17666 }
17667 }
ed7e9d0b 17668 return TRUE;
ba96a88f
NC		 17669}
17670
99e4ae17 17671static enum elf_reloc_type_class
7e612e98
AM		 17672elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17673 const asection *rel_sec ATTRIBUTE_UNUSED,
17674 const Elf_Internal_Rela *rela)
99e4ae17 17675{
f51e552e 17676 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 17677 {
17678 case R_ARM_RELATIVE:
17679 return reloc_class_relative;
17680 case R_ARM_JUMP_SLOT:
17681 return reloc_class_plt;
17682 case R_ARM_COPY:
17683 return reloc_class_copy;
109575d7
JW		 17684 case R_ARM_IRELATIVE:
17685 return reloc_class_ifunc;
99e4ae17
AJ		 17686 default:
17687 return reloc_class_normal;
17688 }
17689}
17690
e489d0ae 17691static void
cc364be6 17692arm_final_write_processing (bfd *abfd)
e16bb312 17693{
5a6c6817 17694 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 17695}
17696
cc364be6
AM		 17697static bfd_boolean
17698elf32_arm_final_write_processing (bfd *abfd)
06f44071 17699{
cc364be6
AM		 17700 arm_final_write_processing (abfd);
17701 return _bfd_elf_final_write_processing (abfd);
06f44071
AM		 17702}
17703
40a18ebd
NC		 17704/* Return TRUE if this is an unwinding table entry. */
17705
17706static bfd_boolean
17707is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17708{
0112cd26
NC		 17709 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
17710 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 17711}
17712
17713
17714/* Set the type and flags for an ARM section. We do this by
17715 the section name, which is a hack, but ought to work. */
17716
17717static bfd_boolean
17718elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17719{
17720 const char * name;
17721
fd361982 17722 name = bfd_section_name (sec);
40a18ebd
NC		 17723
17724 if (is_arm_elf_unwind_section_name (abfd, name))
17725 {
17726 hdr->sh_type = SHT_ARM_EXIDX;
17727 hdr->sh_flags |= SHF_LINK_ORDER;
17728 }
ac4c9b04 17729
f0728ee3
AV		 17730 if (sec->flags & SEC_ELF_PURECODE)
17731 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 17732
40a18ebd
NC		 17733 return TRUE;
17734}
17735
6dc132d9
L		 17736/* Handle an ARM specific section when reading an object file. This is
17737 called when bfd_section_from_shdr finds a section with an unknown
17738 type. */
40a18ebd
NC		 17739
17740static bfd_boolean
17741elf32_arm_section_from_shdr (bfd *abfd,
17742 Elf_Internal_Shdr * hdr,
6dc132d9
L		 17743 const char *name,
17744 int shindex)
40a18ebd
NC		 17745{
17746 /* There ought to be a place to keep ELF backend specific flags, but
17747 at the moment there isn't one. We just keep track of the
17748 sections by their name, instead. Fortunately, the ABI gives
17749 names for all the ARM specific sections, so we will probably get
17750 away with this. */
17751 switch (hdr->sh_type)
17752 {
17753 case SHT_ARM_EXIDX:
0951f019
RE		 17754 case SHT_ARM_PREEMPTMAP:
17755 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 17756 break;
17757
17758 default:
17759 return FALSE;
17760 }
17761
6dc132d9 17762 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 17763 return FALSE;
17764
17765 return TRUE;
17766}
e489d0ae 17767
44444f50
NC		 17768static _arm_elf_section_data *
17769get_arm_elf_section_data (asection * sec)
17770{
47b2e99c
JZ		 17771 if (sec && sec->owner && is_arm_elf (sec->owner))
17772 return elf32_arm_section_data (sec);
44444f50
NC		 17773 else
17774 return NULL;
8e3de13a
NC		 17775}
17776
4e617b1e
PB		 17777typedef struct
17778{
57402f1e 17779 void *flaginfo;
4e617b1e 17780 struct bfd_link_info *info;
91a5743d
PB		 17781 asection *sec;
17782 int sec_shndx;
6e0b88f1
AM		 17783 int (*func) (void *, const char *, Elf_Internal_Sym *,
17784 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 17785} output_arch_syminfo;
17786
17787enum map_symbol_type
17788{
17789 ARM_MAP_ARM,
17790 ARM_MAP_THUMB,
17791 ARM_MAP_DATA
17792};
17793
17794
7413f23f 17795/* Output a single mapping symbol. */
4e617b1e
PB		 17796
17797static bfd_boolean
7413f23f
DJ		 17798elf32_arm_output_map_sym (output_arch_syminfo *osi,
17799 enum map_symbol_type type,
17800 bfd_vma offset)
4e617b1e
PB		 17801{
17802 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 17803 Elf_Internal_Sym sym;
17804
91a5743d
PB		 17805 sym.st_value = osi->sec->output_section->vma
17806 + osi->sec->output_offset
17807 + offset;
4e617b1e
PB		 17808 sym.st_size = 0;
17809 sym.st_other = 0;
17810 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 17811 sym.st_shndx = osi->sec_shndx;
35fc36a8 17812 sym.st_target_internal = 0;
fe33d2fa 17813 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 17814 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 17815}
17816
34e77a92
RS		 17817/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17818 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 17819
17820static bfd_boolean
34e77a92
RS		 17821elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
17822 bfd_boolean is_iplt_entry_p,
17823 union gotplt_union *root_plt,
17824 struct arm_plt_info *arm_plt)
4e617b1e 17825{
4e617b1e 17826 struct elf32_arm_link_hash_table *htab;
34e77a92 17827 bfd_vma addr, plt_header_size;
4e617b1e 17828
34e77a92 17829 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 17830 return TRUE;
17831
4dfe6ac6
NC		 17832 htab = elf32_arm_hash_table (osi->info);
17833 if (htab == NULL)
17834 return FALSE;
17835
34e77a92
RS		 17836 if (is_iplt_entry_p)
17837 {
17838 osi->sec = htab->root.iplt;
17839 plt_header_size = 0;
17840 }
17841 else
17842 {
17843 osi->sec = htab->root.splt;
17844 plt_header_size = htab->plt_header_size;
17845 }
17846 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
17847 (osi->info->output_bfd, osi->sec->output_section));
17848
17849 addr = root_plt->offset & -2;
90c14f0c 17850 if (htab->root.target_os == is_symbian)
4e617b1e 17851 {
7413f23f 17852 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17853 return FALSE;
7413f23f 17854 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 17855 return FALSE;
17856 }
90c14f0c 17857 else if (htab->root.target_os == is_vxworks)
4e617b1e 17858 {
7413f23f 17859 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17860 return FALSE;
7413f23f 17861 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 17862 return FALSE;
7413f23f 17863 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 17864 return FALSE;
7413f23f 17865 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 17866 return FALSE;
17867 }
90c14f0c 17868 else if (htab->root.target_os == is_nacl)
b38cadfb
NC		 17869 {
17870 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
17871 return FALSE;
17872 }
7801f98f
CL		 17873 else if (htab->fdpic_p)
17874 {
59029f57
CL		 17875 enum map_symbol_type type = using_thumb_only(htab)
17876 ? ARM_MAP_THUMB
17877 : ARM_MAP_ARM;
17878
7801f98f 17879 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
4b24dd1a
AM		 17880 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
17881 return FALSE;
59029f57 17882 if (!elf32_arm_output_map_sym (osi, type, addr))
4b24dd1a 17883 return FALSE;
7801f98f 17884 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
4b24dd1a 17885 return FALSE;
7801f98f 17886 if (htab->plt_entry_size == 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry))
4b24dd1a
AM		 17887 if (!elf32_arm_output_map_sym (osi, type, addr + 24))
17888 return FALSE;
7801f98f 17889 }
eed94f8f
NC		 17890 else if (using_thumb_only (htab))
17891 {
17892 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
17893 return FALSE;
6a631e86 17894 }
4e617b1e
PB		 17895 else
17896 {
34e77a92 17897 bfd_boolean thumb_stub_p;
bd97cb95 17898
34e77a92
RS		 17899 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
17900 if (thumb_stub_p)
4e617b1e 17901 {
7413f23f 17902 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 17903 return FALSE;
17904 }
17905#ifdef FOUR_WORD_PLT
7413f23f 17906 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17907 return FALSE;
7413f23f 17908 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 17909 return FALSE;
17910#else
906e58ca 17911 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 17912 so only need to output a mapping symbol for the first PLT entry and
17913 entries with thumb thunks. */
34e77a92 17914 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 17915 {
7413f23f 17916 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 17917 return FALSE;
17918 }
17919#endif
17920 }
17921
17922 return TRUE;
17923}
17924
34e77a92
RS		 17925/* Output mapping symbols for PLT entries associated with H. */
17926
17927static bfd_boolean
17928elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
17929{
17930 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
17931 struct elf32_arm_link_hash_entry *eh;
17932
17933 if (h->root.type == bfd_link_hash_indirect)
17934 return TRUE;
17935
17936 if (h->root.type == bfd_link_hash_warning)
17937 /* When warning symbols are created, they **replace** the "real"
17938 entry in the hash table, thus we never get to see the real
17939 symbol in a hash traversal. So look at it now. */
17940 h = (struct elf_link_hash_entry *) h->root.u.i.link;
17941
17942 eh = (struct elf32_arm_link_hash_entry *) h;
17943 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
17944 &h->plt, &eh->plt);
17945}
17946
4f4faa4d
TP		 17947/* Bind a veneered symbol to its veneer identified by its hash entry
17948 STUB_ENTRY. The veneered location thus loose its symbol. */
17949
17950static void
17951arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
17952{
17953 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
17954
17955 BFD_ASSERT (hash);
17956 hash->root.root.u.def.section = stub_entry->stub_sec;
17957 hash->root.root.u.def.value = stub_entry->stub_offset;
17958 hash->root.size = stub_entry->stub_size;
17959}
17960
7413f23f
DJ		 17961/* Output a single local symbol for a generated stub. */
17962
17963static bfd_boolean
17964elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
17965 bfd_vma offset, bfd_vma size)
17966{
7413f23f
DJ		 17967 Elf_Internal_Sym sym;
17968
7413f23f
DJ		 17969 sym.st_value = osi->sec->output_section->vma
17970 + osi->sec->output_offset
17971 + offset;
17972 sym.st_size = size;
17973 sym.st_other = 0;
17974 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
17975 sym.st_shndx = osi->sec_shndx;
35fc36a8 17976 sym.st_target_internal = 0;
57402f1e 17977 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 17978}
4e617b1e 17979
da5938a2 17980static bfd_boolean
8029a119
NC		 17981arm_map_one_stub (struct bfd_hash_entry * gen_entry,
17982 void * in_arg)
da5938a2
NC		 17983{
17984 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 17985 asection *stub_sec;
17986 bfd_vma addr;
7413f23f 17987 char *stub_name;
9a008db3 17988 output_arch_syminfo *osi;
d3ce72d0 17989 const insn_sequence *template_sequence;
461a49ca
DJ		 17990 enum stub_insn_type prev_type;
17991 int size;
17992 int i;
17993 enum map_symbol_type sym_type;
da5938a2
NC		 17994
17995 /* Massage our args to the form they really have. */
17996 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 17997 osi = (output_arch_syminfo *) in_arg;
da5938a2 17998
da5938a2
NC		 17999 stub_sec = stub_entry->stub_sec;
18000
18001 /* Ensure this stub is attached to the current section being
7413f23f 18002 processed. */
da5938a2
NC		 18003 if (stub_sec != osi->sec)
18004 return TRUE;
18005
7413f23f 18006 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 18007 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 18008
18009 if (arm_stub_sym_claimed (stub_entry->stub_type))
18010 arm_stub_claim_sym (stub_entry);
18011 else
7413f23f 18012 {
4f4faa4d
TP		 18013 stub_name = stub_entry->output_name;
18014 switch (template_sequence[0].type)
18015 {
18016 case ARM_TYPE:
18017 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
18018 stub_entry->stub_size))
18019 return FALSE;
18020 break;
18021 case THUMB16_TYPE:
18022 case THUMB32_TYPE:
18023 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
18024 stub_entry->stub_size))
18025 return FALSE;
18026 break;
18027 default:
18028 BFD_FAIL ();
18029 return 0;
18030 }
7413f23f 18031 }
da5938a2 18032
461a49ca
DJ		 18033 prev_type = DATA_TYPE;
18034 size = 0;
18035 for (i = 0; i < stub_entry->stub_template_size; i++)
18036 {
d3ce72d0 18037 switch (template_sequence[i].type)
461a49ca
DJ		 18038 {
18039 case ARM_TYPE:
18040 sym_type = ARM_MAP_ARM;
18041 break;
18042
18043 case THUMB16_TYPE:
48229727 18044 case THUMB32_TYPE:
461a49ca
DJ		 18045 sym_type = ARM_MAP_THUMB;
18046 break;
18047
18048 case DATA_TYPE:
18049 sym_type = ARM_MAP_DATA;
18050 break;
18051
18052 default:
18053 BFD_FAIL ();
4e31c731 18054 return FALSE;
461a49ca
DJ		 18055 }
18056
d3ce72d0 18057 if (template_sequence[i].type != prev_type)
461a49ca 18058 {
d3ce72d0 18059 prev_type = template_sequence[i].type;
461a49ca
DJ		 18060 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
18061 return FALSE;
18062 }
18063
d3ce72d0 18064 switch (template_sequence[i].type)
461a49ca
DJ		 18065 {
18066 case ARM_TYPE:
48229727 18067 case THUMB32_TYPE:
461a49ca
DJ		 18068 size += 4;
18069 break;
18070
18071 case THUMB16_TYPE:
18072 size += 2;
18073 break;
18074
18075 case DATA_TYPE:
18076 size += 4;
18077 break;
18078
18079 default:
18080 BFD_FAIL ();
4e31c731 18081 return FALSE;
461a49ca
DJ		 18082 }
18083 }
18084
da5938a2
NC		 18085 return TRUE;
18086}
18087
33811162
DG		 18088/* Output mapping symbols for linker generated sections,
18089 and for those data-only sections that do not have a
18090 $d. */
4e617b1e
PB		 18091
18092static bfd_boolean
18093elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 18094 struct bfd_link_info *info,
57402f1e 18095 void *flaginfo,
6e0b88f1
AM		 18096 int (*func) (void *, const char *,
18097 Elf_Internal_Sym *,
18098 asection *,
18099 struct elf_link_hash_entry *))
4e617b1e
PB		 18100{
18101 output_arch_syminfo osi;
18102 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 18103 bfd_vma offset;
18104 bfd_size_type size;
33811162 18105 bfd *input_bfd;
4e617b1e
PB		 18106
18107 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 18108 if (htab == NULL)
18109 return FALSE;
18110
906e58ca 18111 check_use_blx (htab);
91a5743d 18112
57402f1e 18113 osi.flaginfo = flaginfo;
4e617b1e
PB		 18114 osi.info = info;
18115 osi.func = func;
906e58ca 18116
33811162
DG		 18117 /* Add a $d mapping symbol to data-only sections that
18118 don't have any mapping symbol. This may result in (harmless) redundant
18119 mapping symbols. */
18120 for (input_bfd = info->input_bfds;
18121 input_bfd != NULL;
c72f2fb2 18122 input_bfd = input_bfd->link.next)
33811162
DG		 18123 {
18124 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18125 for (osi.sec = input_bfd->sections;
18126 osi.sec != NULL;
18127 osi.sec = osi.sec->next)
18128 {
18129 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 18130 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18131 != 0)
33811162
DG		 18132 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18133 == SEC_HAS_CONTENTS
18134 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 18135 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 18136 && osi.sec->size > 0
18137 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 18138 {
18139 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18140 (output_bfd, osi.sec->output_section);
18141 if (osi.sec_shndx != (int)SHN_BAD)
18142 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18143 }
18144 }
18145 }
18146
91a5743d
PB		 18147 /* ARM->Thumb glue. */
18148 if (htab->arm_glue_size > 0)
18149 {
3d4d4302
AM		 18150 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18151 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 18152
18153 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18154 (output_bfd, osi.sec->output_section);
0e1862bb 18155 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 18156 || htab->pic_veneer)
18157 size = ARM2THUMB_PIC_GLUE_SIZE;
18158 else if (htab->use_blx)
18159 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18160 else
18161 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 18162
91a5743d
PB		 18163 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18164 {
7413f23f
DJ		 18165 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18166 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 18167 }
18168 }
18169
18170 /* Thumb->ARM glue. */
18171 if (htab->thumb_glue_size > 0)
18172 {
3d4d4302
AM		 18173 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18174 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 18175
18176 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18177 (output_bfd, osi.sec->output_section);
18178 size = THUMB2ARM_GLUE_SIZE;
18179
18180 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18181 {
7413f23f
DJ		 18182 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18183 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 18184 }
18185 }
18186
845b51d6
PB		 18187 /* ARMv4 BX veneers. */
18188 if (htab->bx_glue_size > 0)
18189 {
3d4d4302
AM		 18190 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18191 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 18192
18193 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18194 (output_bfd, osi.sec->output_section);
18195
7413f23f 18196 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 18197 }
18198
8029a119
NC		 18199 /* Long calls stubs. */
18200 if (htab->stub_bfd && htab->stub_bfd->sections)
18201 {
da5938a2 18202 asection* stub_sec;
8029a119 18203
da5938a2
NC		 18204 for (stub_sec = htab->stub_bfd->sections;
18205 stub_sec != NULL;
8029a119
NC		 18206 stub_sec = stub_sec->next)
18207 {
18208 /* Ignore non-stub sections. */
18209 if (!strstr (stub_sec->name, STUB_SUFFIX))
18210 continue;
da5938a2 18211
8029a119 18212 osi.sec = stub_sec;
da5938a2 18213
8029a119
NC		 18214 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18215 (output_bfd, osi.sec->output_section);
da5938a2 18216
8029a119
NC		 18217 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18218 }
18219 }
da5938a2 18220
91a5743d 18221 /* Finally, output mapping symbols for the PLT. */
34e77a92 18222 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 18223 {
34e77a92
RS		 18224 osi.sec = htab->root.splt;
18225 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18226 (output_bfd, osi.sec->output_section));
18227
18228 /* Output mapping symbols for the plt header. SymbianOS does not have a
18229 plt header. */
90c14f0c 18230 if (htab->root.target_os == is_vxworks)
34e77a92
RS		 18231 {
18232 /* VxWorks shared libraries have no PLT header. */
0e1862bb 18233 if (!bfd_link_pic (info))
34e77a92
RS		 18234 {
18235 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18236 return FALSE;
18237 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18238 return FALSE;
18239 }
18240 }
90c14f0c 18241 else if (htab->root.target_os == is_nacl)
b38cadfb
NC		 18242 {
18243 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18244 return FALSE;
18245 }
59029f57 18246 else if (using_thumb_only (htab) && !htab->fdpic_p)
eed94f8f
NC		 18247 {
18248 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18249 return FALSE;
18250 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18251 return FALSE;
18252 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18253 return FALSE;
18254 }
90c14f0c 18255 else if (htab->root.target_os != is_symbian && !htab->fdpic_p)
4e617b1e 18256 {
7413f23f 18257 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 18258 return FALSE;
34e77a92
RS		 18259#ifndef FOUR_WORD_PLT
18260 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 18261 return FALSE;
34e77a92 18262#endif
4e617b1e
PB		 18263 }
18264 }
90c14f0c
L		 18265 if (htab->root.target_os == is_nacl
18266 && htab->root.iplt
18267 && htab->root.iplt->size > 0)
99059e56
RM		 18268 {
18269 /* NaCl uses a special first entry in .iplt too. */
18270 osi.sec = htab->root.iplt;
18271 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18272 (output_bfd, osi.sec->output_section));
18273 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18274 return FALSE;
18275 }
34e77a92
RS		 18276 if ((htab->root.splt && htab->root.splt->size > 0)
18277 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 18278 {
34e77a92
RS		 18279 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18280 for (input_bfd = info->input_bfds;
18281 input_bfd != NULL;
c72f2fb2 18282 input_bfd = input_bfd->link.next)
34e77a92
RS		 18283 {
18284 struct arm_local_iplt_info **local_iplt;
18285 unsigned int i, num_syms;
4e617b1e 18286
34e77a92
RS		 18287 local_iplt = elf32_arm_local_iplt (input_bfd);
18288 if (local_iplt != NULL)
18289 {
18290 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18291 for (i = 0; i < num_syms; i++)
18292 if (local_iplt[i] != NULL
18293 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
18294 &local_iplt[i]->root,
18295 &local_iplt[i]->arm))
18296 return FALSE;
18297 }
18298 }
18299 }
9bcc30e4 18300 if (htab->root.tlsdesc_plt != 0)
0855e32b
NS		 18301 {
18302 /* Mapping symbols for the lazy tls trampoline. */
9bcc30e4
L		 18303 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM,
18304 htab->root.tlsdesc_plt))
0855e32b 18305 return FALSE;
b38cadfb 18306
0855e32b 18307 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
9bcc30e4 18308 htab->root.tlsdesc_plt + 24))
0855e32b
NS		 18309 return FALSE;
18310 }
18311 if (htab->tls_trampoline != 0)
18312 {
18313 /* Mapping symbols for the tls trampoline. */
18314 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18315 return FALSE;
18316#ifdef FOUR_WORD_PLT
18317 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18318 htab->tls_trampoline + 12))
18319 return FALSE;
b38cadfb 18320#endif
0855e32b 18321 }
b38cadfb 18322
4e617b1e
PB		 18323 return TRUE;
18324}
18325
54ddd295
TP		 18326/* Filter normal symbols of CMSE entry functions of ABFD to include in
18327 the import library. All SYMCOUNT symbols of ABFD can be examined
18328 from their pointers in SYMS. Pointers of symbols to keep should be
18329 stored continuously at the beginning of that array.
18330
18331 Returns the number of symbols to keep. */
18332
18333static unsigned int
18334elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18335 struct bfd_link_info *info,
18336 asymbol **syms, long symcount)
18337{
18338 size_t maxnamelen;
18339 char *cmse_name;
18340 long src_count, dst_count = 0;
18341 struct elf32_arm_link_hash_table *htab;
18342
18343 htab = elf32_arm_hash_table (info);
18344 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18345 symcount = 0;
18346
18347 maxnamelen = 128;
18348 cmse_name = (char *) bfd_malloc (maxnamelen);
7a0fb7be
NC		 18349 BFD_ASSERT (cmse_name);
18350
54ddd295
TP		 18351 for (src_count = 0; src_count < symcount; src_count++)
18352 {
18353 struct elf32_arm_link_hash_entry *cmse_hash;
18354 asymbol *sym;
18355 flagword flags;
18356 char *name;
18357 size_t namelen;
18358
18359 sym = syms[src_count];
18360 flags = sym->flags;
18361 name = (char *) bfd_asymbol_name (sym);
18362
18363 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18364 continue;
18365 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18366 continue;
18367
18368 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18369 if (namelen > maxnamelen)
18370 {
18371 cmse_name = (char *)
18372 bfd_realloc (cmse_name, namelen);
18373 maxnamelen = namelen;
18374 }
18375 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18376 cmse_hash = (struct elf32_arm_link_hash_entry *)
18377 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
18378
18379 if (!cmse_hash
18380 || (cmse_hash->root.root.type != bfd_link_hash_defined
18381 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18382 || cmse_hash->root.type != STT_FUNC)
18383 continue;
18384
54ddd295
TP		 18385 syms[dst_count++] = sym;
18386 }
18387 free (cmse_name);
18388
18389 syms[dst_count] = NULL;
18390
18391 return dst_count;
18392}
18393
18394/* Filter symbols of ABFD to include in the import library. All
18395 SYMCOUNT symbols of ABFD can be examined from their pointers in
18396 SYMS. Pointers of symbols to keep should be stored continuously at
18397 the beginning of that array.
18398
18399 Returns the number of symbols to keep. */
18400
18401static unsigned int
18402elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18403 struct bfd_link_info *info,
18404 asymbol **syms, long symcount)
18405{
18406 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18407
046734ff
TP		 18408 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18409 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18410 library to be a relocatable object file. */
18411 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 18412 if (globals->cmse_implib)
18413 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18414 else
18415 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18416}
18417
e489d0ae
PB		 18418/* Allocate target specific section data. */
18419
18420static bfd_boolean
18421elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18422{
f592407e
AM		 18423 if (!sec->used_by_bfd)
18424 {
18425 _arm_elf_section_data *sdata;
986f0783 18426 size_t amt = sizeof (*sdata);
e489d0ae 18427
21d799b5 18428 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 18429 if (sdata == NULL)
18430 return FALSE;
18431 sec->used_by_bfd = sdata;
18432 }
e489d0ae
PB		 18433
18434 return _bfd_elf_new_section_hook (abfd, sec);
18435}
18436
18437
18438/* Used to order a list of mapping symbols by address. */
18439
18440static int
18441elf32_arm_compare_mapping (const void * a, const void * b)
18442{
7f6a71ff
JM		 18443 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18444 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18445
18446 if (amap->vma > bmap->vma)
18447 return 1;
18448 else if (amap->vma < bmap->vma)
18449 return -1;
18450 else if (amap->type > bmap->type)
18451 /* Ensure results do not depend on the host qsort for objects with
18452 multiple mapping symbols at the same address by sorting on type
18453 after vma. */
18454 return 1;
18455 else if (amap->type < bmap->type)
18456 return -1;
18457 else
18458 return 0;
e489d0ae
PB		 18459}
18460
2468f9c9
PB		 18461/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18462
18463static unsigned long
18464offset_prel31 (unsigned long addr, bfd_vma offset)
18465{
18466 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18467}
18468
18469/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18470 relocations. */
18471
18472static void
18473copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18474{
18475 unsigned long first_word = bfd_get_32 (output_bfd, from);
18476 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 18477
2468f9c9
PB		 18478 /* High bit of first word is supposed to be zero. */
18479 if ((first_word & 0x80000000ul) == 0)
18480 first_word = offset_prel31 (first_word, offset);
b38cadfb 18481
2468f9c9
PB		 18482 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18483 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18484 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18485 second_word = offset_prel31 (second_word, offset);
b38cadfb 18486
2468f9c9
PB		 18487 bfd_put_32 (output_bfd, first_word, to);
18488 bfd_put_32 (output_bfd, second_word, to + 4);
18489}
e489d0ae 18490
48229727
JB		 18491/* Data for make_branch_to_a8_stub(). */
18492
b38cadfb
NC		 18493struct a8_branch_to_stub_data
18494{
48229727
JB		 18495 asection *writing_section;
18496 bfd_byte *contents;
18497};
18498
18499
18500/* Helper to insert branches to Cortex-A8 erratum stubs in the right
18501 places for a particular section. */
18502
18503static bfd_boolean
18504make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 18505 void *in_arg)
48229727
JB		 18506{
18507 struct elf32_arm_stub_hash_entry *stub_entry;
18508 struct a8_branch_to_stub_data *data;
18509 bfd_byte *contents;
18510 unsigned long branch_insn;
18511 bfd_vma veneered_insn_loc, veneer_entry_loc;
18512 bfd_signed_vma branch_offset;
18513 bfd *abfd;
8d9d9490 18514 unsigned int loc;
48229727
JB		 18515
18516 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18517 data = (struct a8_branch_to_stub_data *) in_arg;
18518
18519 if (stub_entry->target_section != data->writing_section
4563a860 18520 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 18521 return TRUE;
18522
18523 contents = data->contents;
18524
8d9d9490
TP		 18525 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18526 generated when both source and target are in the same section. */
48229727
JB		 18527 veneered_insn_loc = stub_entry->target_section->output_section->vma
18528 + stub_entry->target_section->output_offset
8d9d9490 18529 + stub_entry->source_value;
48229727
JB		 18530
18531 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18532 + stub_entry->stub_sec->output_offset
18533 + stub_entry->stub_offset;
18534
18535 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18536 veneered_insn_loc &= ~3u;
18537
18538 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18539
18540 abfd = stub_entry->target_section->owner;
8d9d9490 18541 loc = stub_entry->source_value;
48229727
JB		 18542
18543 /* We attempt to avoid this condition by setting stubs_always_after_branch
18544 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18545 This check is just to be on the safe side... */
18546 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18547 {
871b3ab2 18548 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 18549 "allocated in unsafe location"), abfd);
48229727
JB		 18550 return FALSE;
18551 }
18552
18553 switch (stub_entry->stub_type)
18554 {
18555 case arm_stub_a8_veneer_b:
18556 case arm_stub_a8_veneer_b_cond:
18557 branch_insn = 0xf0009000;
18558 goto jump24;
18559
18560 case arm_stub_a8_veneer_blx:
18561 branch_insn = 0xf000e800;
18562 goto jump24;
18563
18564 case arm_stub_a8_veneer_bl:
18565 {
18566 unsigned int i1, j1, i2, j2, s;
18567
18568 branch_insn = 0xf000d000;
18569
18570 jump24:
18571 if (branch_offset < -16777216 || branch_offset > 16777214)
18572 {
18573 /* There's not much we can do apart from complain if this
18574 happens. */
871b3ab2 18575 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 18576 "of range (input file too large)"), abfd);
48229727
JB		 18577 return FALSE;
18578 }
18579
18580 /* i1 = not(j1 eor s), so:
18581 not i1 = j1 eor s
18582 j1 = (not i1) eor s. */
18583
18584 branch_insn |= (branch_offset >> 1) & 0x7ff;
18585 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18586 i2 = (branch_offset >> 22) & 1;
18587 i1 = (branch_offset >> 23) & 1;
18588 s = (branch_offset >> 24) & 1;
18589 j1 = (!i1) ^ s;
18590 j2 = (!i2) ^ s;
18591 branch_insn |= j2 << 11;
18592 branch_insn |= j1 << 13;
18593 branch_insn |= s << 26;
18594 }
18595 break;
18596
18597 default:
18598 BFD_FAIL ();
18599 return FALSE;
18600 }
18601
8d9d9490
TP		 18602 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18603 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 18604
18605 return TRUE;
18606}
18607
a504d23a
LA		 18608/* Beginning of stm32l4xx work-around. */
18609
18610/* Functions encoding instructions necessary for the emission of the
18611 fix-stm32l4xx-629360.
18612 Encoding is extracted from the
18613 ARM (C) Architecture Reference Manual
18614 ARMv7-A and ARMv7-R edition
18615 ARM DDI 0406C.b (ID072512). */
18616
18617static inline bfd_vma
82188b29 18618create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 18619{
18620 /* A8.8.18 B (A8-334)
18621 B target_address (Encoding T4). */
18622 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18623 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18624 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18625
a504d23a
LA		 18626 int s = ((branch_offset & 0x1000000) >> 24);
18627 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18628 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18629
18630 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18631 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18632
18633 bfd_vma patched_inst = 0xf0009000
18634 | s << 26 /* S. */
18635 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18636 | j1 << 13 /* J1. */
18637 | j2 << 11 /* J2. */
18638 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18639
18640 return patched_inst;
18641}
18642
18643static inline bfd_vma
18644create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18645{
18646 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18647 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18648 bfd_vma patched_inst = 0xe8900000
18649 | (/*W=*/wback << 21)
18650 | (base_reg << 16)
18651 | (reg_mask & 0x0000ffff);
18652
18653 return patched_inst;
18654}
18655
18656static inline bfd_vma
18657create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18658{
18659 /* A8.8.60 LDMDB/LDMEA (A8-402)
18660 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18661 bfd_vma patched_inst = 0xe9100000
18662 | (/*W=*/wback << 21)
18663 | (base_reg << 16)
18664 | (reg_mask & 0x0000ffff);
18665
18666 return patched_inst;
18667}
18668
18669static inline bfd_vma
18670create_instruction_mov (int target_reg, int source_reg)
18671{
18672 /* A8.8.103 MOV (register) (A8-486)
18673 MOV Rd, Rm (Encoding T1). */
18674 bfd_vma patched_inst = 0x4600
18675 | (target_reg & 0x7)
18676 | ((target_reg & 0x8) >> 3) << 7
18677 | (source_reg << 3);
18678
18679 return patched_inst;
18680}
18681
18682static inline bfd_vma
18683create_instruction_sub (int target_reg, int source_reg, int value)
18684{
18685 /* A8.8.221 SUB (immediate) (A8-708)
18686 SUB Rd, Rn, #value (Encoding T3). */
18687 bfd_vma patched_inst = 0xf1a00000
18688 | (target_reg << 8)
18689 | (source_reg << 16)
18690 | (/*S=*/0 << 20)
18691 | ((value & 0x800) >> 11) << 26
18692 | ((value & 0x700) >> 8) << 12
18693 | (value & 0x0ff);
18694
18695 return patched_inst;
18696}
18697
18698static inline bfd_vma
9239bbd3 18699create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 18700 int first_reg)
18701{
18702 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18703 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18704 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 18705 | (/*W=*/wback << 21)
18706 | (base_reg << 16)
9239bbd3
CM		 18707 | (num_words & 0x000000ff)
18708 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 18709 | (first_reg & 0x00000001) << 22;
18710
18711 return patched_inst;
18712}
18713
18714static inline bfd_vma
9239bbd3
CM		 18715create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18716 int first_reg)
a504d23a
LA		 18717{
18718 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18719 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18720 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 18721 | (base_reg << 16)
9239bbd3
CM		 18722 | (num_words & 0x000000ff)
18723 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 18724 | (first_reg & 0x00000001) << 22;
18725
18726 return patched_inst;
18727}
18728
18729static inline bfd_vma
18730create_instruction_udf_w (int value)
18731{
18732 /* A8.8.247 UDF (A8-758)
18733 Undefined (Encoding T2). */
18734 bfd_vma patched_inst = 0xf7f0a000
18735 | (value & 0x00000fff)
18736 | (value & 0x000f0000) << 16;
18737
18738 return patched_inst;
18739}
18740
18741static inline bfd_vma
18742create_instruction_udf (int value)
18743{
18744 /* A8.8.247 UDF (A8-758)
18745 Undefined (Encoding T1). */
18746 bfd_vma patched_inst = 0xde00
18747 | (value & 0xff);
18748
18749 return patched_inst;
18750}
18751
18752/* Functions writing an instruction in memory, returning the next
18753 memory position to write to. */
18754
18755static inline bfd_byte *
18756push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18757 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18758{
18759 put_thumb2_insn (htab, output_bfd, insn, pt);
18760 return pt + 4;
18761}
18762
18763static inline bfd_byte *
18764push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
18765 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18766{
18767 put_thumb_insn (htab, output_bfd, insn, pt);
18768 return pt + 2;
18769}
18770
18771/* Function filling up a region in memory with T1 and T2 UDFs taking
18772 care of alignment. */
18773
18774static bfd_byte *
18775stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 18776 bfd * output_bfd,
18777 const bfd_byte * const base_stub_contents,
18778 bfd_byte * const from_stub_contents,
18779 const bfd_byte * const end_stub_contents)
a504d23a
LA		 18780{
18781 bfd_byte *current_stub_contents = from_stub_contents;
18782
18783 /* Fill the remaining of the stub with deterministic contents : UDF
18784 instructions.
18785 Check if realignment is needed on modulo 4 frontier using T1, to
18786 further use T2. */
18787 if ((current_stub_contents < end_stub_contents)
18788 && !((current_stub_contents - base_stub_contents) % 2)
18789 && ((current_stub_contents - base_stub_contents) % 4))
18790 current_stub_contents =
18791 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18792 create_instruction_udf (0));
18793
18794 for (; current_stub_contents < end_stub_contents;)
18795 current_stub_contents =
18796 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18797 create_instruction_udf_w (0));
18798
18799 return current_stub_contents;
18800}
18801
18802/* Functions writing the stream of instructions equivalent to the
18803 derived sequence for ldmia, ldmdb, vldm respectively. */
18804
18805static void
18806stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
18807 bfd * output_bfd,
18808 const insn32 initial_insn,
18809 const bfd_byte *const initial_insn_addr,
18810 bfd_byte *const base_stub_contents)
18811{
18812 int wback = (initial_insn & 0x00200000) >> 21;
18813 int ri, rn = (initial_insn & 0x000F0000) >> 16;
18814 int insn_all_registers = initial_insn & 0x0000ffff;
18815 int insn_low_registers, insn_high_registers;
18816 int usable_register_mask;
b25e998d 18817 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18818 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18819 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
18820 bfd_byte *current_stub_contents = base_stub_contents;
18821
18822 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
18823
18824 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18825 smaller than 8 registers load sequences that do not cause the
18826 hardware issue. */
18827 if (nb_registers <= 8)
18828 {
18829 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18830 current_stub_contents =
18831 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18832 initial_insn);
18833
18834 /* B initial_insn_addr+4. */
18835 if (!restore_pc)
18836 current_stub_contents =
18837 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18838 create_instruction_branch_absolute
82188b29 18839 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18840
18841 /* Fill the remaining of the stub with deterministic contents. */
18842 current_stub_contents =
18843 stm32l4xx_fill_stub_udf (htab, output_bfd,
18844 base_stub_contents, current_stub_contents,
18845 base_stub_contents +
18846 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18847
18848 return;
18849 }
18850
18851 /* - reg_list[13] == 0. */
18852 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
18853
18854 /* - reg_list[14] & reg_list[15] != 1. */
18855 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18856
18857 /* - if (wback==1) reg_list[rn] == 0. */
18858 BFD_ASSERT (!wback || !restore_rn);
18859
18860 /* - nb_registers > 8. */
b25e998d 18861 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 18862
18863 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18864
18865 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
18866 - One with the 7 lowest registers (register mask 0x007F)
18867 This LDM will finally contain between 2 and 7 registers
18868 - One with the 7 highest registers (register mask 0xDF80)
18869 This ldm will finally contain between 2 and 7 registers. */
18870 insn_low_registers = insn_all_registers & 0x007F;
18871 insn_high_registers = insn_all_registers & 0xDF80;
18872
18873 /* A spare register may be needed during this veneer to temporarily
18874 handle the base register. This register will be restored with the
18875 last LDM operation.
18876 The usable register may be any general purpose register (that
18877 excludes PC, SP, LR : register mask is 0x1FFF). */
18878 usable_register_mask = 0x1FFF;
18879
18880 /* Generate the stub function. */
18881 if (wback)
18882 {
18883 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
18884 current_stub_contents =
18885 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18886 create_instruction_ldmia
18887 (rn, /*wback=*/1, insn_low_registers));
18888
18889 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
18890 current_stub_contents =
18891 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18892 create_instruction_ldmia
18893 (rn, /*wback=*/1, insn_high_registers));
18894 if (!restore_pc)
18895 {
18896 /* B initial_insn_addr+4. */
18897 current_stub_contents =
18898 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18899 create_instruction_branch_absolute
82188b29 18900 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18901 }
18902 }
18903 else /* if (!wback). */
18904 {
18905 ri = rn;
18906
18907 /* If Rn is not part of the high-register-list, move it there. */
18908 if (!(insn_high_registers & (1 << rn)))
18909 {
18910 /* Choose a Ri in the high-register-list that will be restored. */
18911 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18912
18913 /* MOV Ri, Rn. */
18914 current_stub_contents =
18915 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18916 create_instruction_mov (ri, rn));
18917 }
18918
18919 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18920 current_stub_contents =
18921 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18922 create_instruction_ldmia
18923 (ri, /*wback=*/1, insn_low_registers));
18924
18925 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18926 current_stub_contents =
18927 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18928 create_instruction_ldmia
18929 (ri, /*wback=*/0, insn_high_registers));
18930
18931 if (!restore_pc)
18932 {
18933 /* B initial_insn_addr+4. */
18934 current_stub_contents =
18935 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18936 create_instruction_branch_absolute
82188b29 18937 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18938 }
18939 }
18940
18941 /* Fill the remaining of the stub with deterministic contents. */
18942 current_stub_contents =
18943 stm32l4xx_fill_stub_udf (htab, output_bfd,
18944 base_stub_contents, current_stub_contents,
18945 base_stub_contents +
18946 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18947}
18948
18949static void
18950stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
18951 bfd * output_bfd,
18952 const insn32 initial_insn,
18953 const bfd_byte *const initial_insn_addr,
18954 bfd_byte *const base_stub_contents)
18955{
18956 int wback = (initial_insn & 0x00200000) >> 21;
18957 int ri, rn = (initial_insn & 0x000f0000) >> 16;
18958 int insn_all_registers = initial_insn & 0x0000ffff;
18959 int insn_low_registers, insn_high_registers;
18960 int usable_register_mask;
18961 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18962 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 18963 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18964 bfd_byte *current_stub_contents = base_stub_contents;
18965
18966 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
18967
18968 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18969 smaller than 8 registers load sequences that do not cause the
18970 hardware issue. */
18971 if (nb_registers <= 8)
18972 {
18973 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18974 current_stub_contents =
18975 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18976 initial_insn);
18977
18978 /* B initial_insn_addr+4. */
18979 current_stub_contents =
18980 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18981 create_instruction_branch_absolute
82188b29 18982 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18983
18984 /* Fill the remaining of the stub with deterministic contents. */
18985 current_stub_contents =
18986 stm32l4xx_fill_stub_udf (htab, output_bfd,
18987 base_stub_contents, current_stub_contents,
18988 base_stub_contents +
18989 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18990
18991 return;
18992 }
18993
18994 /* - reg_list[13] == 0. */
18995 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
18996
18997 /* - reg_list[14] & reg_list[15] != 1. */
18998 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18999
19000 /* - if (wback==1) reg_list[rn] == 0. */
19001 BFD_ASSERT (!wback || !restore_rn);
19002
19003 /* - nb_registers > 8. */
b25e998d 19004 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19005
19006 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19007
19008 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19009 - One with the 7 lowest registers (register mask 0x007F)
19010 This LDM will finally contain between 2 and 7 registers
19011 - One with the 7 highest registers (register mask 0xDF80)
19012 This ldm will finally contain between 2 and 7 registers. */
19013 insn_low_registers = insn_all_registers & 0x007F;
19014 insn_high_registers = insn_all_registers & 0xDF80;
19015
19016 /* A spare register may be needed during this veneer to temporarily
19017 handle the base register. This register will be restored with
19018 the last LDM operation.
19019 The usable register may be any general purpose register (that excludes
19020 PC, SP, LR : register mask is 0x1FFF). */
19021 usable_register_mask = 0x1FFF;
19022
19023 /* Generate the stub function. */
19024 if (!wback && !restore_pc && !restore_rn)
19025 {
19026 /* Choose a Ri in the low-register-list that will be restored. */
19027 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19028
19029 /* MOV Ri, Rn. */
19030 current_stub_contents =
19031 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19032 create_instruction_mov (ri, rn));
19033
19034 /* LDMDB Ri!, {R-high-register-list}. */
19035 current_stub_contents =
19036 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19037 create_instruction_ldmdb
19038 (ri, /*wback=*/1, insn_high_registers));
19039
19040 /* LDMDB Ri, {R-low-register-list}. */
19041 current_stub_contents =
19042 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19043 create_instruction_ldmdb
19044 (ri, /*wback=*/0, insn_low_registers));
19045
19046 /* B initial_insn_addr+4. */
19047 current_stub_contents =
19048 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19049 create_instruction_branch_absolute
82188b29 19050 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19051 }
19052 else if (wback && !restore_pc && !restore_rn)
19053 {
19054 /* LDMDB Rn!, {R-high-register-list}. */
19055 current_stub_contents =
19056 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19057 create_instruction_ldmdb
19058 (rn, /*wback=*/1, insn_high_registers));
19059
19060 /* LDMDB Rn!, {R-low-register-list}. */
19061 current_stub_contents =
19062 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19063 create_instruction_ldmdb
19064 (rn, /*wback=*/1, insn_low_registers));
19065
19066 /* B initial_insn_addr+4. */
19067 current_stub_contents =
19068 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19069 create_instruction_branch_absolute
82188b29 19070 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19071 }
19072 else if (!wback && restore_pc && !restore_rn)
19073 {
19074 /* Choose a Ri in the high-register-list that will be restored. */
19075 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19076
19077 /* SUB Ri, Rn, #(4*nb_registers). */
19078 current_stub_contents =
19079 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19080 create_instruction_sub (ri, rn, (4 * nb_registers)));
19081
19082 /* LDMIA Ri!, {R-low-register-list}. */
19083 current_stub_contents =
19084 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19085 create_instruction_ldmia
19086 (ri, /*wback=*/1, insn_low_registers));
19087
19088 /* LDMIA Ri, {R-high-register-list}. */
19089 current_stub_contents =
19090 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19091 create_instruction_ldmia
19092 (ri, /*wback=*/0, insn_high_registers));
19093 }
19094 else if (wback && restore_pc && !restore_rn)
19095 {
19096 /* Choose a Ri in the high-register-list that will be restored. */
19097 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19098
19099 /* SUB Rn, Rn, #(4*nb_registers) */
19100 current_stub_contents =
19101 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19102 create_instruction_sub (rn, rn, (4 * nb_registers)));
19103
19104 /* MOV Ri, Rn. */
19105 current_stub_contents =
19106 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19107 create_instruction_mov (ri, rn));
19108
19109 /* LDMIA Ri!, {R-low-register-list}. */
19110 current_stub_contents =
19111 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19112 create_instruction_ldmia
19113 (ri, /*wback=*/1, insn_low_registers));
19114
19115 /* LDMIA Ri, {R-high-register-list}. */
19116 current_stub_contents =
19117 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19118 create_instruction_ldmia
19119 (ri, /*wback=*/0, insn_high_registers));
19120 }
19121 else if (!wback && !restore_pc && restore_rn)
19122 {
19123 ri = rn;
19124 if (!(insn_low_registers & (1 << rn)))
19125 {
19126 /* Choose a Ri in the low-register-list that will be restored. */
19127 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19128
19129 /* MOV Ri, Rn. */
19130 current_stub_contents =
19131 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19132 create_instruction_mov (ri, rn));
19133 }
19134
19135 /* LDMDB Ri!, {R-high-register-list}. */
19136 current_stub_contents =
19137 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19138 create_instruction_ldmdb
19139 (ri, /*wback=*/1, insn_high_registers));
19140
19141 /* LDMDB Ri, {R-low-register-list}. */
19142 current_stub_contents =
19143 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19144 create_instruction_ldmdb
19145 (ri, /*wback=*/0, insn_low_registers));
19146
19147 /* B initial_insn_addr+4. */
19148 current_stub_contents =
19149 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19150 create_instruction_branch_absolute
82188b29 19151 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19152 }
19153 else if (!wback && restore_pc && restore_rn)
19154 {
19155 ri = rn;
19156 if (!(insn_high_registers & (1 << rn)))
19157 {
19158 /* Choose a Ri in the high-register-list that will be restored. */
19159 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19160 }
19161
19162 /* SUB Ri, Rn, #(4*nb_registers). */
19163 current_stub_contents =
19164 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19165 create_instruction_sub (ri, rn, (4 * nb_registers)));
19166
19167 /* LDMIA Ri!, {R-low-register-list}. */
19168 current_stub_contents =
19169 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19170 create_instruction_ldmia
19171 (ri, /*wback=*/1, insn_low_registers));
19172
19173 /* LDMIA Ri, {R-high-register-list}. */
19174 current_stub_contents =
19175 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19176 create_instruction_ldmia
19177 (ri, /*wback=*/0, insn_high_registers));
19178 }
19179 else if (wback && restore_rn)
19180 {
19181 /* The assembler should not have accepted to encode this. */
19182 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19183 "undefined behavior.\n");
19184 }
19185
19186 /* Fill the remaining of the stub with deterministic contents. */
19187 current_stub_contents =
19188 stm32l4xx_fill_stub_udf (htab, output_bfd,
19189 base_stub_contents, current_stub_contents,
19190 base_stub_contents +
19191 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19192
19193}
19194
19195static void
19196stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19197 bfd * output_bfd,
19198 const insn32 initial_insn,
19199 const bfd_byte *const initial_insn_addr,
19200 bfd_byte *const base_stub_contents)
19201{
13c9c485 19202 int num_words = initial_insn & 0xff;
a504d23a
LA		 19203 bfd_byte *current_stub_contents = base_stub_contents;
19204
19205 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19206
19207 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 19208 smaller than 8 words load sequences that do not cause the
a504d23a 19209 hardware issue. */
9239bbd3 19210 if (num_words <= 8)
a504d23a
LA		 19211 {
19212 /* Untouched instruction. */
19213 current_stub_contents =
19214 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19215 initial_insn);
19216
19217 /* B initial_insn_addr+4. */
19218 current_stub_contents =
19219 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19220 create_instruction_branch_absolute
82188b29 19221 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19222 }
19223 else
19224 {
9eaff861 19225 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 19226 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 19227 bfd_boolean is_ia_nobang = /* (IA without !). */
19228 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19229 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
19230 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19231 bfd_boolean is_db_bang = /* (DB with !). */
19232 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 19233 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 19234 /* d = UInt (Vd:D);. */
9239bbd3 19235 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 19236 | (((unsigned int)initial_insn << 9) >> 31);
19237
9239bbd3
CM		 19238 /* Compute the number of 8-words chunks needed to split. */
19239 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 19240 int chunk;
19241
19242 /* The test coverage has been done assuming the following
19243 hypothesis that exactly one of the previous is_ predicates is
19244 true. */
9239bbd3
CM		 19245 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19246 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 19247
9239bbd3 19248 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 19249 cases, then we emit the adjustments:
19250
19251 vldm rx, {...}
19252 -> vldm rx!, {8_words_or_less} for each needed 8_word
19253 -> sub rx, rx, #size (list)
19254
19255 vldm rx!, {...}
19256 -> vldm rx!, {8_words_or_less} for each needed 8_word
19257 This also handles vpop instruction (when rx is sp)
19258
19259 vldmd rx!, {...}
19260 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 19261 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 19262 {
9239bbd3
CM		 19263 bfd_vma new_insn = 0;
19264
a504d23a
LA		 19265 if (is_ia_nobang || is_ia_bang)
19266 {
9239bbd3
CM		 19267 new_insn = create_instruction_vldmia
19268 (base_reg,
19269 is_dp,
19270 /*wback= . */1,
19271 chunks - (chunk + 1) ?
19272 8 : num_words - chunk * 8,
19273 first_reg + chunk * 8);
a504d23a
LA		 19274 }
19275 else if (is_db_bang)
19276 {
9239bbd3
CM		 19277 new_insn = create_instruction_vldmdb
19278 (base_reg,
19279 is_dp,
19280 chunks - (chunk + 1) ?
19281 8 : num_words - chunk * 8,
19282 first_reg + chunk * 8);
a504d23a 19283 }
9239bbd3
CM		 19284
19285 if (new_insn)
19286 current_stub_contents =
19287 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19288 new_insn);
a504d23a
LA		 19289 }
19290
19291 /* Only this case requires the base register compensation
19292 subtract. */
19293 if (is_ia_nobang)
19294 {
19295 current_stub_contents =
19296 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19297 create_instruction_sub
9239bbd3 19298 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 19299 }
19300
19301 /* B initial_insn_addr+4. */
19302 current_stub_contents =
19303 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19304 create_instruction_branch_absolute
82188b29 19305 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19306 }
19307
19308 /* Fill the remaining of the stub with deterministic contents. */
19309 current_stub_contents =
19310 stm32l4xx_fill_stub_udf (htab, output_bfd,
19311 base_stub_contents, current_stub_contents,
19312 base_stub_contents +
19313 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19314}
19315
19316static void
19317stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19318 bfd * output_bfd,
19319 const insn32 wrong_insn,
19320 const bfd_byte *const wrong_insn_addr,
19321 bfd_byte *const stub_contents)
19322{
19323 if (is_thumb2_ldmia (wrong_insn))
19324 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19325 wrong_insn, wrong_insn_addr,
19326 stub_contents);
19327 else if (is_thumb2_ldmdb (wrong_insn))
19328 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19329 wrong_insn, wrong_insn_addr,
19330 stub_contents);
19331 else if (is_thumb2_vldm (wrong_insn))
19332 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19333 wrong_insn, wrong_insn_addr,
19334 stub_contents);
19335}
19336
19337/* End of stm32l4xx work-around. */
19338
19339
e489d0ae
PB		 19340/* Do code byteswapping. Return FALSE afterwards so that the section is
19341 written out as normal. */
19342
19343static bfd_boolean
c7b8f16e 19344elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 19345 struct bfd_link_info *link_info,
19346 asection *sec,
e489d0ae
PB		 19347 bfd_byte *contents)
19348{
48229727 19349 unsigned int mapcount, errcount;
8e3de13a 19350 _arm_elf_section_data *arm_data;
c7b8f16e 19351 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 19352 elf32_arm_section_map *map;
c7b8f16e 19353 elf32_vfp11_erratum_list *errnode;
a504d23a 19354 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 19355 bfd_vma ptr;
19356 bfd_vma end;
c7b8f16e 19357 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 19358 bfd_byte tmp;
48229727 19359 unsigned int i;
57e8b36a 19360
4dfe6ac6
NC		 19361 if (globals == NULL)
19362 return FALSE;
19363
8e3de13a
NC		 19364 /* If this section has not been allocated an _arm_elf_section_data
19365 structure then we cannot record anything. */
19366 arm_data = get_arm_elf_section_data (sec);
19367 if (arm_data == NULL)
19368 return FALSE;
19369
19370 mapcount = arm_data->mapcount;
19371 map = arm_data->map;
c7b8f16e
JB		 19372 errcount = arm_data->erratumcount;
19373
19374 if (errcount != 0)
19375 {
19376 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19377
19378 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 19379 errnode = errnode->next)
19380 {
19381 bfd_vma target = errnode->vma - offset;
19382
19383 switch (errnode->type)
19384 {
19385 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19386 {
19387 bfd_vma branch_to_veneer;
19388 /* Original condition code of instruction, plus bit mask for
19389 ARM B instruction. */
19390 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19391 | 0x0a000000;
c7b8f16e
JB		 19392
19393 /* The instruction is before the label. */
91d6fa6a 19394 target -= 4;
c7b8f16e
JB		 19395
19396 /* Above offset included in -4 below. */
19397 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 19398 - errnode->vma - 4;
c7b8f16e
JB		 19399
19400 if ((signed) branch_to_veneer < -(1 << 25)
19401 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 19402 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19403 "range"), output_bfd);
c7b8f16e 19404
99059e56
RM		 19405 insn |= (branch_to_veneer >> 2) & 0xffffff;
19406 contents[endianflip ^ target] = insn & 0xff;
19407 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19408 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19409 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19410 }
19411 break;
c7b8f16e
JB		 19412
19413 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 19414 {
19415 bfd_vma branch_from_veneer;
19416 unsigned int insn;
c7b8f16e 19417
99059e56
RM		 19418 /* Take size of veneer into account. */
19419 branch_from_veneer = errnode->u.v.branch->vma
19420 - errnode->vma - 12;
c7b8f16e
JB		 19421
19422 if ((signed) branch_from_veneer < -(1 << 25)
19423 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 19424 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19425 "range"), output_bfd);
c7b8f16e 19426
99059e56
RM		 19427 /* Original instruction. */
19428 insn = errnode->u.v.branch->u.b.vfp_insn;
19429 contents[endianflip ^ target] = insn & 0xff;
19430 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19431 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19432 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19433
19434 /* Branch back to insn after original insn. */
19435 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19436 contents[endianflip ^ (target + 4)] = insn & 0xff;
19437 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19438 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19439 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19440 }
19441 break;
c7b8f16e 19442
99059e56
RM		 19443 default:
19444 abort ();
19445 }
19446 }
c7b8f16e 19447 }
e489d0ae 19448
a504d23a
LA		 19449 if (arm_data->stm32l4xx_erratumcount != 0)
19450 {
19451 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19452 stm32l4xx_errnode != 0;
19453 stm32l4xx_errnode = stm32l4xx_errnode->next)
19454 {
19455 bfd_vma target = stm32l4xx_errnode->vma - offset;
19456
19457 switch (stm32l4xx_errnode->type)
19458 {
19459 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19460 {
19461 unsigned int insn;
19462 bfd_vma branch_to_veneer =
19463 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19464
19465 if ((signed) branch_to_veneer < -(1 << 24)
19466 || (signed) branch_to_veneer >= (1 << 24))
19467 {
19468 bfd_vma out_of_range =
19469 ((signed) branch_to_veneer < -(1 << 24)) ?
19470 - branch_to_veneer - (1 << 24) :
19471 ((signed) branch_to_veneer >= (1 << 24)) ?
19472 branch_to_veneer - (1 << 24) : 0;
19473
4eca0228 19474 _bfd_error_handler
2dcf00ce 19475 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 19476 "cannot create STM32L4XX veneer; "
19477 "jump out of range by %" PRId64 " bytes; "
19478 "cannot encode branch instruction"),
a504d23a 19479 output_bfd,
2dcf00ce
AM		 19480 (uint64_t) (stm32l4xx_errnode->vma - 4),
19481 (int64_t) out_of_range);
a504d23a
LA		 19482 continue;
19483 }
19484
19485 insn = create_instruction_branch_absolute
82188b29 19486 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a 19487
a2699ef2
AM		 19488 /* The instruction is before the label. */
19489 target -= 4;
19490
a504d23a
LA		 19491 put_thumb2_insn (globals, output_bfd,
19492 (bfd_vma) insn, contents + target);
19493 }
19494 break;
19495
19496 case STM32L4XX_ERRATUM_VENEER:
19497 {
82188b29
NC		 19498 bfd_byte * veneer;
19499 bfd_byte * veneer_r;
a504d23a
LA		 19500 unsigned int insn;
19501
82188b29
NC		 19502 veneer = contents + target;
19503 veneer_r = veneer
19504 + stm32l4xx_errnode->u.b.veneer->vma
19505 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 19506
19507 if ((signed) (veneer_r - veneer -
19508 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19509 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19510 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19511 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19512 || (signed) (veneer_r - veneer) >= (1 << 24))
19513 {
90b6238f
AM		 19514 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19515 "veneer"), output_bfd);
a504d23a
LA		 19516 continue;
19517 }
19518
19519 /* Original instruction. */
19520 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19521
19522 stm32l4xx_create_replacing_stub
19523 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19524 }
19525 break;
19526
19527 default:
19528 abort ();
19529 }
19530 }
19531 }
19532
2468f9c9
PB		 19533 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19534 {
19535 arm_unwind_table_edit *edit_node
99059e56 19536 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 19537 /* Now, sec->size is the size of the section we will write. The original
99059e56 19538 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 19539 markers) was sec->rawsize. (This isn't the case if we perform no
19540 edits, then rawsize will be zero and we should use size). */
21d799b5 19541 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 19542 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19543 unsigned int in_index, out_index;
19544 bfd_vma add_to_offsets = 0;
19545
7a0fb7be
NC		 19546 if (edited_contents == NULL)
19547 return FALSE;
2468f9c9 19548 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 19549 {
2468f9c9
PB		 19550 if (edit_node)
19551 {
19552 unsigned int edit_index = edit_node->index;
b38cadfb 19553
2468f9c9 19554 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 19555 {
2468f9c9
PB		 19556 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19557 contents + in_index * 8, add_to_offsets);
19558 out_index++;
19559 in_index++;
19560 }
19561 else if (in_index == edit_index
19562 || (in_index * 8 >= input_size
19563 && edit_index == UINT_MAX))
99059e56 19564 {
2468f9c9
PB		 19565 switch (edit_node->type)
19566 {
19567 case DELETE_EXIDX_ENTRY:
19568 in_index++;
19569 add_to_offsets += 8;
19570 break;
b38cadfb 19571
2468f9c9
PB		 19572 case INSERT_EXIDX_CANTUNWIND_AT_END:
19573 {
99059e56 19574 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 19575 bfd_vma text_offset = text_sec->output_section->vma
19576 + text_sec->output_offset
19577 + text_sec->size;
19578 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 19579 unsigned long prel31_offset;
2468f9c9
PB		 19580
19581 /* Note: this is meant to be equivalent to an
19582 R_ARM_PREL31 relocation. These synthetic
19583 EXIDX_CANTUNWIND markers are not relocated by the
19584 usual BFD method. */
19585 prel31_offset = (text_offset - exidx_offset)
19586 & 0x7ffffffful;
491d01d3
YU		 19587 if (bfd_link_relocatable (link_info))
19588 {
19589 /* Here relocation for new EXIDX_CANTUNWIND is
19590 created, so there is no need to
19591 adjust offset by hand. */
19592 prel31_offset = text_sec->output_offset
19593 + text_sec->size;
491d01d3 19594 }
2468f9c9
PB		 19595
19596 /* First address we can't unwind. */
19597 bfd_put_32 (output_bfd, prel31_offset,
19598 &edited_contents[out_index * 8]);
19599
19600 /* Code for EXIDX_CANTUNWIND. */
19601 bfd_put_32 (output_bfd, 0x1,
19602 &edited_contents[out_index * 8 + 4]);
19603
19604 out_index++;
19605 add_to_offsets -= 8;
19606 }
19607 break;
19608 }
b38cadfb 19609
2468f9c9
PB		 19610 edit_node = edit_node->next;
19611 }
19612 }
19613 else
19614 {
19615 /* No more edits, copy remaining entries verbatim. */
19616 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19617 contents + in_index * 8, add_to_offsets);
19618 out_index++;
19619 in_index++;
19620 }
19621 }
19622
19623 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19624 bfd_set_section_contents (output_bfd, sec->output_section,
19625 edited_contents,
19626 (file_ptr) sec->output_offset, sec->size);
19627
19628 return TRUE;
19629 }
19630
48229727
JB		 19631 /* Fix code to point to Cortex-A8 erratum stubs. */
19632 if (globals->fix_cortex_a8)
19633 {
19634 struct a8_branch_to_stub_data data;
19635
19636 data.writing_section = sec;
19637 data.contents = contents;
19638
a504d23a
LA		 19639 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19640 & data);
48229727
JB		 19641 }
19642
e489d0ae
PB		 19643 if (mapcount == 0)
19644 return FALSE;
19645
c7b8f16e 19646 if (globals->byteswap_code)
e489d0ae 19647 {
c7b8f16e 19648 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 19649
c7b8f16e
JB		 19650 ptr = map[0].vma;
19651 for (i = 0; i < mapcount; i++)
99059e56
RM		 19652 {
19653 if (i == mapcount - 1)
c7b8f16e 19654 end = sec->size;
99059e56
RM		 19655 else
19656 end = map[i + 1].vma;
e489d0ae 19657
99059e56 19658 switch (map[i].type)
e489d0ae 19659 {
c7b8f16e
JB		 19660 case 'a':
19661 /* Byte swap code words. */
19662 while (ptr + 3 < end)
99059e56
RM		 19663 {
19664 tmp = contents[ptr];
19665 contents[ptr] = contents[ptr + 3];
19666 contents[ptr + 3] = tmp;
19667 tmp = contents[ptr + 1];
19668 contents[ptr + 1] = contents[ptr + 2];
19669 contents[ptr + 2] = tmp;
19670 ptr += 4;
19671 }
c7b8f16e 19672 break;
e489d0ae 19673
c7b8f16e
JB		 19674 case 't':
19675 /* Byte swap code halfwords. */
19676 while (ptr + 1 < end)
99059e56
RM		 19677 {
19678 tmp = contents[ptr];
19679 contents[ptr] = contents[ptr + 1];
19680 contents[ptr + 1] = tmp;
19681 ptr += 2;
19682 }
c7b8f16e
JB		 19683 break;
19684
19685 case 'd':
19686 /* Leave data alone. */
19687 break;
19688 }
99059e56
RM		 19689 ptr = end;
19690 }
e489d0ae 19691 }
8e3de13a 19692
93204d3a 19693 free (map);
47b2e99c 19694 arm_data->mapcount = -1;
c7b8f16e 19695 arm_data->mapsize = 0;
8e3de13a 19696 arm_data->map = NULL;
8e3de13a 19697
e489d0ae
PB		 19698 return FALSE;
19699}
19700
0beaef2b
PB		 19701/* Mangle thumb function symbols as we read them in. */
19702
8384fb8f 19703static bfd_boolean
0beaef2b
PB		 19704elf32_arm_swap_symbol_in (bfd * abfd,
19705 const void *psrc,
19706 const void *pshn,
19707 Elf_Internal_Sym *dst)
19708{
8384fb8f
AM		 19709 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19710 return FALSE;
39d911fc 19711 dst->st_target_internal = 0;
0beaef2b
PB		 19712
19713 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 19714 the address. */
63e1a0fc
PB		 19715 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19716 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 19717 {
63e1a0fc
PB		 19718 if (dst->st_value & 1)
19719 {
19720 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 19721 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19722 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 19723 }
19724 else
39d911fc 19725 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 19726 }
19727 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19728 {
19729 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 19730 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 19731 }
35fc36a8 19732 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 19733 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 19734 else
39d911fc 19735 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 19736
8384fb8f 19737 return TRUE;
0beaef2b
PB		 19738}
19739
19740
19741/* Mangle thumb function symbols as we write them out. */
19742
19743static void
19744elf32_arm_swap_symbol_out (bfd *abfd,
19745 const Elf_Internal_Sym *src,
19746 void *cdst,
19747 void *shndx)
19748{
19749 Elf_Internal_Sym newsym;
19750
19751 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19752 of the address set, as per the new EABI. We do this unconditionally
19753 because objcopy does not set the elf header flags until after
19754 it writes out the symbol table. */
39d911fc 19755 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 19756 {
19757 newsym = *src;
34e77a92
RS		 19758 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19759 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 19760 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 19761 {
19762 /* Do this only for defined symbols. At link type, the static
19763 linker will simulate the work of dynamic linker of resolving
19764 symbols and will carry over the thumbness of found symbols to
19765 the output symbol table. It's not clear how it happens, but
19766 the thumbness of undefined symbols can well be different at
19767 runtime, and writing '1' for them will be confusing for users
19768 and possibly for dynamic linker itself.
19769 */
19770 newsym.st_value |= 1;
19771 }
906e58ca 19772
0beaef2b
PB		 19773 src = &newsym;
19774 }
19775 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
19776}
19777
b294bdf8
MM		 19778/* Add the PT_ARM_EXIDX program header. */
19779
19780static bfd_boolean
906e58ca 19781elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 19782 struct bfd_link_info *info ATTRIBUTE_UNUSED)
19783{
19784 struct elf_segment_map *m;
19785 asection *sec;
19786
19787 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19788 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19789 {
19790 /* If there is already a PT_ARM_EXIDX header, then we do not
19791 want to add another one. This situation arises when running
19792 "strip"; the input binary already has the header. */
12bd6957 19793 m = elf_seg_map (abfd);
b294bdf8
MM		 19794 while (m && m->p_type != PT_ARM_EXIDX)
19795 m = m->next;
19796 if (!m)
19797 {
21d799b5 19798 m = (struct elf_segment_map *)
99059e56 19799 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 19800 if (m == NULL)
19801 return FALSE;
19802 m->p_type = PT_ARM_EXIDX;
19803 m->count = 1;
19804 m->sections[0] = sec;
19805
12bd6957
AM		 19806 m->next = elf_seg_map (abfd);
19807 elf_seg_map (abfd) = m;
b294bdf8
MM		 19808 }
19809 }
19810
19811 return TRUE;
19812}
19813
19814/* We may add a PT_ARM_EXIDX program header. */
19815
19816static int
a6b96beb
AM		 19817elf32_arm_additional_program_headers (bfd *abfd,
19818 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 19819{
19820 asection *sec;
19821
19822 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19823 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19824 return 1;
19825 else
19826 return 0;
19827}
19828
34e77a92
RS		 19829/* Hook called by the linker routine which adds symbols from an object
19830 file. */
19831
19832static bfd_boolean
19833elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
19834 Elf_Internal_Sym *sym, const char **namep,
19835 flagword *flagsp, asection **secp, bfd_vma *valp)
19836{
c792917c
NC		 19837 if (elf32_arm_hash_table (info) == NULL)
19838 return FALSE;
19839
90c14f0c 19840 if (elf32_arm_hash_table (info)->root.target_os == is_vxworks
34e77a92
RS		 19841 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
19842 flagsp, secp, valp))
19843 return FALSE;
19844
19845 return TRUE;
19846}
19847
0beaef2b 19848/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 19849const struct elf_size_info elf32_arm_size_info =
19850{
0beaef2b
PB		 19851 sizeof (Elf32_External_Ehdr),
19852 sizeof (Elf32_External_Phdr),
19853 sizeof (Elf32_External_Shdr),
19854 sizeof (Elf32_External_Rel),
19855 sizeof (Elf32_External_Rela),
19856 sizeof (Elf32_External_Sym),
19857 sizeof (Elf32_External_Dyn),
19858 sizeof (Elf_External_Note),
19859 4,
19860 1,
19861 32, 2,
19862 ELFCLASS32, EV_CURRENT,
19863 bfd_elf32_write_out_phdrs,
19864 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 19865 bfd_elf32_checksum_contents,
0beaef2b
PB		 19866 bfd_elf32_write_relocs,
19867 elf32_arm_swap_symbol_in,
19868 elf32_arm_swap_symbol_out,
19869 bfd_elf32_slurp_reloc_table,
19870 bfd_elf32_slurp_symbol_table,
19871 bfd_elf32_swap_dyn_in,
19872 bfd_elf32_swap_dyn_out,
19873 bfd_elf32_swap_reloc_in,
19874 bfd_elf32_swap_reloc_out,
19875 bfd_elf32_swap_reloca_in,
19876 bfd_elf32_swap_reloca_out
19877};
19878
685e70ae
VK		 19879static bfd_vma
19880read_code32 (const bfd *abfd, const bfd_byte *addr)
19881{
19882 /* V7 BE8 code is always little endian. */
19883 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19884 return bfd_getl32 (addr);
19885
19886 return bfd_get_32 (abfd, addr);
19887}
19888
19889static bfd_vma
19890read_code16 (const bfd *abfd, const bfd_byte *addr)
19891{
19892 /* V7 BE8 code is always little endian. */
19893 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19894 return bfd_getl16 (addr);
19895
19896 return bfd_get_16 (abfd, addr);
19897}
19898
6a631e86
YG		 19899/* Return size of plt0 entry starting at ADDR
19900 or (bfd_vma) -1 if size can not be determined. */
19901
19902static bfd_vma
19903elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
19904{
19905 bfd_vma first_word;
19906 bfd_vma plt0_size;
19907
685e70ae 19908 first_word = read_code32 (abfd, addr);
6a631e86
YG		 19909
19910 if (first_word == elf32_arm_plt0_entry[0])
19911 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
19912 else if (first_word == elf32_thumb2_plt0_entry[0])
19913 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
19914 else
19915 /* We don't yet handle this PLT format. */
19916 return (bfd_vma) -1;
19917
19918 return plt0_size;
19919}
19920
19921/* Return size of plt entry starting at offset OFFSET
19922 of plt section located at address START
19923 or (bfd_vma) -1 if size can not be determined. */
19924
19925static bfd_vma
19926elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
19927{
19928 bfd_vma first_insn;
19929 bfd_vma plt_size = 0;
19930 const bfd_byte *addr = start + offset;
19931
19932 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 19933 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 19934 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
19935
19936 /* Respect Thumb stub if necessary. */
685e70ae 19937 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 19938 {
19939 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
19940 }
19941
19942 /* Strip immediate from first add. */
685e70ae 19943 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 19944
19945#ifdef FOUR_WORD_PLT
19946 if (first_insn == elf32_arm_plt_entry[0])
19947 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
19948#else
19949 if (first_insn == elf32_arm_plt_entry_long[0])
19950 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
19951 else if (first_insn == elf32_arm_plt_entry_short[0])
19952 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
19953#endif
19954 else
19955 /* We don't yet handle this PLT format. */
19956 return (bfd_vma) -1;
19957
19958 return plt_size;
19959}
19960
19961/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19962
19963static long
19964elf32_arm_get_synthetic_symtab (bfd *abfd,
19965 long symcount ATTRIBUTE_UNUSED,
19966 asymbol **syms ATTRIBUTE_UNUSED,
19967 long dynsymcount,
19968 asymbol **dynsyms,
19969 asymbol **ret)
19970{
19971 asection *relplt;
19972 asymbol *s;
19973 arelent *p;
19974 long count, i, n;
19975 size_t size;
19976 Elf_Internal_Shdr *hdr;
19977 char *names;
19978 asection *plt;
19979 bfd_vma offset;
19980 bfd_byte *data;
19981
19982 *ret = NULL;
19983
19984 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
19985 return 0;
19986
19987 if (dynsymcount <= 0)
19988 return 0;
19989
19990 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
19991 if (relplt == NULL)
19992 return 0;
19993
19994 hdr = &elf_section_data (relplt)->this_hdr;
19995 if (hdr->sh_link != elf_dynsymtab (abfd)
19996 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
19997 return 0;
19998
19999 plt = bfd_get_section_by_name (abfd, ".plt");
20000 if (plt == NULL)
20001 return 0;
20002
20003 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
20004 return -1;
20005
20006 data = plt->contents;
20007 if (data == NULL)
20008 {
20009 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
20010 return -1;
20011 bfd_cache_section_contents((asection *) plt, data);
20012 }
20013
20014 count = relplt->size / hdr->sh_entsize;
20015 size = count * sizeof (asymbol);
20016 p = relplt->relocation;
20017 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20018 {
20019 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
20020 if (p->addend != 0)
20021 size += sizeof ("+0x") - 1 + 8;
20022 }
20023
20024 s = *ret = (asymbol *) bfd_malloc (size);
20025 if (s == NULL)
20026 return -1;
20027
20028 offset = elf32_arm_plt0_size (abfd, data);
20029 if (offset == (bfd_vma) -1)
20030 return -1;
20031
20032 names = (char *) (s + count);
20033 p = relplt->relocation;
20034 n = 0;
20035 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20036 {
20037 size_t len;
20038
20039 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
20040 if (plt_size == (bfd_vma) -1)
20041 break;
20042
20043 *s = **p->sym_ptr_ptr;
20044 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20045 we are defining a symbol, ensure one of them is set. */
20046 if ((s->flags & BSF_LOCAL) == 0)
20047 s->flags |= BSF_GLOBAL;
20048 s->flags |= BSF_SYNTHETIC;
20049 s->section = plt;
20050 s->value = offset;
20051 s->name = names;
20052 s->udata.p = NULL;
20053 len = strlen ((*p->sym_ptr_ptr)->name);
20054 memcpy (names, (*p->sym_ptr_ptr)->name, len);
20055 names += len;
20056 if (p->addend != 0)
20057 {
20058 char buf[30], *a;
20059
20060 memcpy (names, "+0x", sizeof ("+0x") - 1);
20061 names += sizeof ("+0x") - 1;
20062 bfd_sprintf_vma (abfd, buf, p->addend);
20063 for (a = buf; *a == '0'; ++a)
20064 ;
20065 len = strlen (a);
20066 memcpy (names, a, len);
20067 names += len;
20068 }
20069 memcpy (names, "@plt", sizeof ("@plt"));
20070 names += sizeof ("@plt");
20071 ++s, ++n;
20072 offset += plt_size;
20073 }
20074
20075 return n;
20076}
20077
ac4c9b04 20078static bfd_boolean
8c803a2d 20079elf32_arm_section_flags (const Elf_Internal_Shdr *hdr)
ac4c9b04 20080{
f0728ee3 20081 if (hdr->sh_flags & SHF_ARM_PURECODE)
8c803a2d 20082 hdr->bfd_section->flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 20083 return TRUE;
20084}
20085
20086static flagword
20087elf32_arm_lookup_section_flags (char *flag_name)
20088{
f0728ee3
AV		 20089 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
20090 return SHF_ARM_PURECODE;
ac4c9b04
MG		 20091
20092 return SEC_NO_FLAGS;
20093}
20094
491d01d3
YU		 20095static unsigned int
20096elf32_arm_count_additional_relocs (asection *sec)
20097{
20098 struct _arm_elf_section_data *arm_data;
20099 arm_data = get_arm_elf_section_data (sec);
5025eb7c 20100
6342be70 20101 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 20102}
20103
5522f910 20104/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 20105 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 20106 FALSE otherwise. ISECTION is the best guess matching section from the
20107 input bfd IBFD, but it might be NULL. */
20108
20109static bfd_boolean
20110elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20111 bfd *obfd ATTRIBUTE_UNUSED,
20112 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20113 Elf_Internal_Shdr *osection)
20114{
20115 switch (osection->sh_type)
20116 {
20117 case SHT_ARM_EXIDX:
20118 {
20119 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20120 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20121 unsigned i = 0;
20122
20123 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20124 osection->sh_info = 0;
20125
20126 /* The sh_link field must be set to the text section associated with
20127 this index section. Unfortunately the ARM EHABI does not specify
20128 exactly how to determine this association. Our caller does try
20129 to match up OSECTION with its corresponding input section however
20130 so that is a good first guess. */
20131 if (isection != NULL
20132 && osection->bfd_section != NULL
20133 && isection->bfd_section != NULL
20134 && isection->bfd_section->output_section != NULL
20135 && isection->bfd_section->output_section == osection->bfd_section
20136 && iheaders != NULL
20137 && isection->sh_link > 0
20138 && isection->sh_link < elf_numsections (ibfd)
20139 && iheaders[isection->sh_link]->bfd_section != NULL
20140 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20141 )
20142 {
20143 for (i = elf_numsections (obfd); i-- > 0;)
20144 if (oheaders[i]->bfd_section
20145 == iheaders[isection->sh_link]->bfd_section->output_section)
20146 break;
20147 }
9eaff861 20148
5522f910
NC		 20149 if (i == 0)
20150 {
20151 /* Failing that we have to find a matching section ourselves. If
20152 we had the output section name available we could compare that
20153 with input section names. Unfortunately we don't. So instead
20154 we use a simple heuristic and look for the nearest executable
20155 section before this one. */
20156 for (i = elf_numsections (obfd); i-- > 0;)
20157 if (oheaders[i] == osection)
20158 break;
20159 if (i == 0)
20160 break;
20161
20162 while (i-- > 0)
20163 if (oheaders[i]->sh_type == SHT_PROGBITS
20164 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20165 == (SHF_ALLOC | SHF_EXECINSTR))
20166 break;
20167 }
20168
20169 if (i)
20170 {
20171 osection->sh_link = i;
20172 /* If the text section was part of a group
20173 then the index section should be too. */
20174 if (oheaders[i]->sh_flags & SHF_GROUP)
20175 osection->sh_flags |= SHF_GROUP;
20176 return TRUE;
20177 }
20178 }
20179 break;
20180
20181 case SHT_ARM_PREEMPTMAP:
20182 osection->sh_flags = SHF_ALLOC;
20183 break;
20184
20185 case SHT_ARM_ATTRIBUTES:
20186 case SHT_ARM_DEBUGOVERLAY:
20187 case SHT_ARM_OVERLAYSECTION:
20188 default:
20189 break;
20190 }
20191
20192 return FALSE;
20193}
20194
d691934d
NC		 20195/* Returns TRUE if NAME is an ARM mapping symbol.
20196 Traditionally the symbols $a, $d and $t have been used.
20197 The ARM ELF standard also defines $x (for A64 code). It also allows a
20198 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20199 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20200 not support them here. $t.x indicates the start of ThumbEE instructions. */
20201
20202static bfd_boolean
20203is_arm_mapping_symbol (const char * name)
20204{
20205 return name != NULL /* Paranoia. */
20206 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20207 the mapping symbols could have acquired a prefix.
20208 We do not support this here, since such symbols no
20209 longer conform to the ARM ELF ABI. */
20210 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20211 && (name[2] == 0 || name[2] == '.');
20212 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20213 any characters that follow the period are legal characters for the body
20214 of a symbol's name. For now we just assume that this is the case. */
20215}
20216
fca2a38f
NC		 20217/* Make sure that mapping symbols in object files are not removed via the
20218 "strip --strip-unneeded" tool. These symbols are needed in order to
20219 correctly generate interworking veneers, and for byte swapping code
20220 regions. Once an object file has been linked, it is safe to remove the
20221 symbols as they will no longer be needed. */
20222
20223static void
20224elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20225{
20226 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 20227 && sym->section != bfd_abs_section_ptr
d691934d 20228 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 20229 sym->flags |= BSF_KEEP;
20230}
20231
5522f910
NC		 20232#undef elf_backend_copy_special_section_fields
20233#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20234
252b5132 20235#define ELF_ARCH bfd_arch_arm
ae95ffa6 20236#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 20237#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 20238#ifdef __QNXTARGET__
20239#define ELF_MAXPAGESIZE 0x1000
20240#else
7572ca89 20241#define ELF_MAXPAGESIZE 0x10000
d0facd1b 20242#endif
b1342370 20243#define ELF_MINPAGESIZE 0x1000
24718e3b 20244#define ELF_COMMONPAGESIZE 0x1000
252b5132 20245
07d6d2b8 20246#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 20247
99e4ae17
AJ		 20248#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20249#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 20250#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20251#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 20252#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 20253#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 20254#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8 20255#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 20256#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 20257#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 20258#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 20259#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 20260
07d6d2b8 20261#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
e7679060 20262#define elf_backend_maybe_function_sym elf32_arm_maybe_function_sym
07d6d2b8 20263#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 20264#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 20265#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 20266#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 20267#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 20268#define elf_backend_write_section elf32_arm_write_section
252b5132 20269#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 20270#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 20271#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20272#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20273#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 20274#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 20275#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ed7e9d0b 20276#define elf_backend_init_file_header elf32_arm_init_file_header
99e4ae17 20277#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 20278#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 20279#define elf_backend_fake_sections elf32_arm_fake_sections
20280#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20281#define elf_backend_final_write_processing elf32_arm_final_write_processing
20282#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 20283#define elf_backend_size_info elf32_arm_size_info
b294bdf8 20284#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 20285#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20286#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 20287#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 20288#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 20289#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 20290#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 20291#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 20292
20293#define elf_backend_can_refcount 1
20294#define elf_backend_can_gc_sections 1
20295#define elf_backend_plt_readonly 1
20296#define elf_backend_want_got_plt 1
20297#define elf_backend_want_plt_sym 0
5474d94f 20298#define elf_backend_want_dynrelro 1
906e58ca
NC		 20299#define elf_backend_may_use_rel_p 1
20300#define elf_backend_may_use_rela_p 0
4e7fd91e 20301#define elf_backend_default_use_rela_p 0
64f52338 20302#define elf_backend_dtrel_excludes_plt 1
252b5132 20303
04f7c78d 20304#define elf_backend_got_header_size 12
b68a20d6 20305#define elf_backend_extern_protected_data 1
04f7c78d 20306
07d6d2b8 20307#undef elf_backend_obj_attrs_vendor
906e58ca 20308#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 20309#undef elf_backend_obj_attrs_section
906e58ca 20310#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 20311#undef elf_backend_obj_attrs_arg_type
906e58ca 20312#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 20313#undef elf_backend_obj_attrs_section_type
104d59d1 20314#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 20315#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 20316#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 20317
07d6d2b8 20318#undef elf_backend_section_flags
ac4c9b04 20319#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 20320#undef elf_backend_lookup_section_flags_hook
20321#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 20322
a2f63b2e
MR		 20323#define elf_backend_linux_prpsinfo32_ugid16 TRUE
20324
252b5132 20325#include "elf32-target.h"
7f266840 20326
b38cadfb
NC		 20327/* Native Client targets. */
20328
20329#undef TARGET_LITTLE_SYM
6d00b590 20330#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 20331#undef TARGET_LITTLE_NAME
20332#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20333#undef TARGET_BIG_SYM
6d00b590 20334#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 20335#undef TARGET_BIG_NAME
20336#define TARGET_BIG_NAME "elf32-bigarm-nacl"
20337
20338/* Like elf32_arm_link_hash_table_create -- but overrides
20339 appropriately for NaCl. */
20340
20341static struct bfd_link_hash_table *
20342elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20343{
20344 struct bfd_link_hash_table *ret;
20345
20346 ret = elf32_arm_link_hash_table_create (abfd);
20347 if (ret)
20348 {
20349 struct elf32_arm_link_hash_table *htab
20350 = (struct elf32_arm_link_hash_table *) ret;
20351
b38cadfb
NC		 20352 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20353 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20354 }
20355 return ret;
20356}
20357
20358/* Since NaCl doesn't use the ARM-specific unwind format, we don't
20359 really need to use elf32_arm_modify_segment_map. But we do it
20360 anyway just to reduce gratuitous differences with the stock ARM backend. */
20361
20362static bfd_boolean
20363elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20364{
20365 return (elf32_arm_modify_segment_map (abfd, info)
20366 && nacl_modify_segment_map (abfd, info));
20367}
20368
cc364be6
AM		 20369static bfd_boolean
20370elf32_arm_nacl_final_write_processing (bfd *abfd)
887badb3 20371{
cc364be6
AM		 20372 arm_final_write_processing (abfd);
20373 return nacl_final_write_processing (abfd);
887badb3
RM		 20374}
20375
6a631e86
YG		 20376static bfd_vma
20377elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20378 const arelent *rel ATTRIBUTE_UNUSED)
20379{
20380 return plt->vma
20381 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20382 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20383}
887badb3 20384
b38cadfb 20385#undef elf32_bed
6a631e86 20386#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 20387#undef bfd_elf32_bfd_link_hash_table_create
20388#define bfd_elf32_bfd_link_hash_table_create \
20389 elf32_arm_nacl_link_hash_table_create
20390#undef elf_backend_plt_alignment
6a631e86 20391#define elf_backend_plt_alignment 4
b38cadfb
NC		 20392#undef elf_backend_modify_segment_map
20393#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
6d6c25c8
AM		 20394#undef elf_backend_modify_headers
20395#define elf_backend_modify_headers nacl_modify_headers
887badb3
RM		 20396#undef elf_backend_final_write_processing
20397#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 20398#undef bfd_elf32_get_synthetic_symtab
20399#undef elf_backend_plt_sym_val
20400#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 20401#undef elf_backend_copy_special_section_fields
b38cadfb 20402
887badb3
RM		 20403#undef ELF_MINPAGESIZE
20404#undef ELF_COMMONPAGESIZE
20405
90c14f0c
L		 20406#undef ELF_TARGET_OS
20407#define ELF_TARGET_OS is_nacl
b38cadfb
NC		 20408
20409#include "elf32-target.h"
20410
20411/* Reset to defaults. */
20412#undef elf_backend_plt_alignment
20413#undef elf_backend_modify_segment_map
20414#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
6d6c25c8 20415#undef elf_backend_modify_headers
887badb3
RM		 20416#undef elf_backend_final_write_processing
20417#define elf_backend_final_write_processing elf32_arm_final_write_processing
20418#undef ELF_MINPAGESIZE
20419#define ELF_MINPAGESIZE 0x1000
20420#undef ELF_COMMONPAGESIZE
20421#define ELF_COMMONPAGESIZE 0x1000
20422
b38cadfb 20423
617a5ada
CL		 20424/* FDPIC Targets. */
20425
20426#undef TARGET_LITTLE_SYM
20427#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20428#undef TARGET_LITTLE_NAME
20429#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20430#undef TARGET_BIG_SYM
20431#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20432#undef TARGET_BIG_NAME
20433#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20434#undef elf_match_priority
20435#define elf_match_priority 128
18a20338
CL		 20436#undef ELF_OSABI
20437#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 20438
20439/* Like elf32_arm_link_hash_table_create -- but overrides
20440 appropriately for FDPIC. */
20441
20442static struct bfd_link_hash_table *
20443elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20444{
20445 struct bfd_link_hash_table *ret;
20446
20447 ret = elf32_arm_link_hash_table_create (abfd);
20448 if (ret)
20449 {
20450 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20451
20452 htab->fdpic_p = 1;
20453 }
20454 return ret;
20455}
20456
e8b09b87
CL		 20457/* We need dynamic symbols for every section, since segments can
20458 relocate independently. */
20459static bfd_boolean
20460elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20461 struct bfd_link_info *info
20462 ATTRIBUTE_UNUSED,
20463 asection *p ATTRIBUTE_UNUSED)
20464{
20465 switch (elf_section_data (p)->this_hdr.sh_type)
20466 {
20467 case SHT_PROGBITS:
20468 case SHT_NOBITS:
20469 /* If sh_type is yet undecided, assume it could be
20470 SHT_PROGBITS/SHT_NOBITS. */
20471 case SHT_NULL:
20472 return FALSE;
20473
20474 /* There shouldn't be section relative relocations
20475 against any other section. */
20476 default:
20477 return TRUE;
20478 }
20479}
20480
617a5ada
CL		 20481#undef elf32_bed
20482#define elf32_bed elf32_arm_fdpic_bed
20483
20484#undef bfd_elf32_bfd_link_hash_table_create
4b24dd1a 20485#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
617a5ada 20486
e8b09b87
CL		 20487#undef elf_backend_omit_section_dynsym
20488#define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20489
90c14f0c
L		 20490#undef ELF_TARGET_OS
20491
617a5ada 20492#include "elf32-target.h"
e8b09b87 20493
617a5ada 20494#undef elf_match_priority
18a20338 20495#undef ELF_OSABI
e8b09b87 20496#undef elf_backend_omit_section_dynsym
617a5ada 20497
906e58ca 20498/* VxWorks Targets. */
4e7fd91e 20499
07d6d2b8
AM		 20500#undef TARGET_LITTLE_SYM
20501#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20502#undef TARGET_LITTLE_NAME
20503#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20504#undef TARGET_BIG_SYM
20505#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20506#undef TARGET_BIG_NAME
20507#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 20508
20509/* Like elf32_arm_link_hash_table_create -- but overrides
20510 appropriately for VxWorks. */
906e58ca 20511
4e7fd91e
PB		 20512static struct bfd_link_hash_table *
20513elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20514{
20515 struct bfd_link_hash_table *ret;
20516
20517 ret = elf32_arm_link_hash_table_create (abfd);
20518 if (ret)
20519 {
20520 struct elf32_arm_link_hash_table *htab
00a97672 20521 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e
PB		 20522 htab->use_rel = 0;
20523 }
20524 return ret;
906e58ca 20525}
4e7fd91e 20526
cc364be6
AM		 20527static bfd_boolean
20528elf32_arm_vxworks_final_write_processing (bfd *abfd)
00a97672 20529{
cc364be6
AM		 20530 arm_final_write_processing (abfd);
20531 return elf_vxworks_final_write_processing (abfd);
00a97672
RS		 20532}
20533
906e58ca 20534#undef elf32_bed
4e7fd91e
PB		 20535#define elf32_bed elf32_arm_vxworks_bed
20536
906e58ca
NC		 20537#undef bfd_elf32_bfd_link_hash_table_create
20538#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 20539#undef elf_backend_final_write_processing
20540#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20541#undef elf_backend_emit_relocs
9eaff861 20542#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 20543
906e58ca 20544#undef elf_backend_may_use_rel_p
00a97672 20545#define elf_backend_may_use_rel_p 0
906e58ca 20546#undef elf_backend_may_use_rela_p
00a97672 20547#define elf_backend_may_use_rela_p 1
906e58ca 20548#undef elf_backend_default_use_rela_p
00a97672 20549#define elf_backend_default_use_rela_p 1
906e58ca 20550#undef elf_backend_want_plt_sym
00a97672 20551#define elf_backend_want_plt_sym 1
906e58ca 20552#undef ELF_MAXPAGESIZE
00a97672 20553#define ELF_MAXPAGESIZE 0x1000
90c14f0c
L		 20554#undef ELF_TARGET_OS
20555#define ELF_TARGET_OS is_vxworks
4e7fd91e
PB		 20556
20557#include "elf32-target.h"
20558
20559
21d799b5
NC		 20560/* Merge backend specific data from an object file to the output
20561 object file when linking. */
20562
20563static bfd_boolean
50e03d47 20564elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 20565{
50e03d47 20566 bfd *obfd = info->output_bfd;
21d799b5
NC		 20567 flagword out_flags;
20568 flagword in_flags;
20569 bfd_boolean flags_compatible = TRUE;
20570 asection *sec;
20571
cc643b88 20572 /* Check if we have the same endianness. */
50e03d47 20573 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 20574 return FALSE;
20575
20576 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20577 return TRUE;
20578
50e03d47 20579 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 20580 return FALSE;
20581
20582 /* The input BFD must have had its flags initialised. */
20583 /* The following seems bogus to me -- The flags are initialized in
20584 the assembler but I don't think an elf_flags_init field is
20585 written into the object. */
20586 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20587
20588 in_flags = elf_elfheader (ibfd)->e_flags;
20589 out_flags = elf_elfheader (obfd)->e_flags;
20590
20591 /* In theory there is no reason why we couldn't handle this. However
20592 in practice it isn't even close to working and there is no real
20593 reason to want it. */
20594 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20595 && !(ibfd->flags & DYNAMIC)
20596 && (in_flags & EF_ARM_BE8))
20597 {
871b3ab2 20598 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 20599 ibfd);
20600 return FALSE;
20601 }
20602
20603 if (!elf_flags_init (obfd))
20604 {
20605 /* If the input is the default architecture and had the default
20606 flags then do not bother setting the flags for the output
20607 architecture, instead allow future merges to do this. If no
20608 future merges ever set these flags then they will retain their
99059e56
RM		 20609 uninitialised values, which surprise surprise, correspond
20610 to the default values. */
21d799b5
NC		 20611 if (bfd_get_arch_info (ibfd)->the_default
20612 && elf_elfheader (ibfd)->e_flags == 0)
20613 return TRUE;
20614
20615 elf_flags_init (obfd) = TRUE;
20616 elf_elfheader (obfd)->e_flags = in_flags;
20617
20618 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20619 && bfd_get_arch_info (obfd)->the_default)
20620 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20621
20622 return TRUE;
20623 }
20624
20625 /* Determine what should happen if the input ARM architecture
20626 does not match the output ARM architecture. */
20627 if (! bfd_arm_merge_machines (ibfd, obfd))
20628 return FALSE;
20629
20630 /* Identical flags must be compatible. */
20631 if (in_flags == out_flags)
20632 return TRUE;
20633
20634 /* Check to see if the input BFD actually contains any sections. If
20635 not, its flags may not have been initialised either, but it
20636 cannot actually cause any incompatiblity. Do not short-circuit
20637 dynamic objects; their section list may be emptied by
20638 elf_link_add_object_symbols.
20639
20640 Also check to see if there are no code sections in the input.
20641 In this case there is no need to check for code specific flags.
20642 XXX - do we need to worry about floating-point format compatability
20643 in data sections ? */
20644 if (!(ibfd->flags & DYNAMIC))
20645 {
20646 bfd_boolean null_input_bfd = TRUE;
20647 bfd_boolean only_data_sections = TRUE;
20648
20649 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20650 {
20651 /* Ignore synthetic glue sections. */
20652 if (strcmp (sec->name, ".glue_7")
20653 && strcmp (sec->name, ".glue_7t"))
20654 {
fd361982 20655 if ((bfd_section_flags (sec)
21d799b5
NC		 20656 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20657 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 20658 only_data_sections = FALSE;
21d799b5
NC		 20659
20660 null_input_bfd = FALSE;
20661 break;
20662 }
20663 }
20664
20665 if (null_input_bfd || only_data_sections)
20666 return TRUE;
20667 }
20668
20669 /* Complain about various flag mismatches. */
20670 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20671 EF_ARM_EABI_VERSION (out_flags)))
20672 {
20673 _bfd_error_handler
90b6238f 20674 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 20675 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20676 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 20677 return FALSE;
20678 }
20679
20680 /* Not sure what needs to be checked for EABI versions >= 1. */
20681 /* VxWorks libraries do not use these flags. */
20682 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20683 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20684 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20685 {
20686 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20687 {
20688 _bfd_error_handler
871b3ab2 20689 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 20690 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20691 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 20692 flags_compatible = FALSE;
20693 }
20694
20695 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20696 {
20697 if (in_flags & EF_ARM_APCS_FLOAT)
20698 _bfd_error_handler
871b3ab2 20699 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 20700 ibfd, obfd);
20701 else
20702 _bfd_error_handler
871b3ab2 20703 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 20704 ibfd, obfd);
20705
20706 flags_compatible = FALSE;
20707 }
20708
20709 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20710 {
20711 if (in_flags & EF_ARM_VFP_FLOAT)
20712 _bfd_error_handler
90b6238f
AM		 20713 (_("error: %pB uses %s instructions, whereas %pB does not"),
20714 ibfd, "VFP", obfd);
21d799b5
NC		 20715 else
20716 _bfd_error_handler
90b6238f
AM		 20717 (_("error: %pB uses %s instructions, whereas %pB does not"),
20718 ibfd, "FPA", obfd);
21d799b5
NC		 20719
20720 flags_compatible = FALSE;
20721 }
20722
20723 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20724 {
20725 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20726 _bfd_error_handler
90b6238f
AM		 20727 (_("error: %pB uses %s instructions, whereas %pB does not"),
20728 ibfd, "Maverick", obfd);
21d799b5
NC		 20729 else
20730 _bfd_error_handler
90b6238f
AM		 20731 (_("error: %pB does not use %s instructions, whereas %pB does"),
20732 ibfd, "Maverick", obfd);
21d799b5
NC		 20733
20734 flags_compatible = FALSE;
20735 }
20736
20737#ifdef EF_ARM_SOFT_FLOAT
20738 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20739 {
20740 /* We can allow interworking between code that is VFP format
20741 layout, and uses either soft float or integer regs for
20742 passing floating point arguments and results. We already
20743 know that the APCS_FLOAT flags match; similarly for VFP
20744 flags. */
20745 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20746 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20747 {
20748 if (in_flags & EF_ARM_SOFT_FLOAT)
20749 _bfd_error_handler
871b3ab2 20750 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 20751 ibfd, obfd);
20752 else
20753 _bfd_error_handler
871b3ab2 20754 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 20755 ibfd, obfd);
20756
20757 flags_compatible = FALSE;
20758 }
20759 }
20760#endif
20761
20762 /* Interworking mismatch is only a warning. */
20763 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
20764 {
20765 if (in_flags & EF_ARM_INTERWORK)
20766 {
20767 _bfd_error_handler
90b6238f 20768 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 20769 ibfd, obfd);
20770 }
20771 else
20772 {
20773 _bfd_error_handler
90b6238f 20774 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 20775 ibfd, obfd);
20776 }
20777 }
20778 }
20779
20780 return flags_compatible;
20781}
20782
20783
906e58ca 20784/* Symbian OS Targets. */
7f266840 20785
07d6d2b8
AM		 20786#undef TARGET_LITTLE_SYM
20787#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
20788#undef TARGET_LITTLE_NAME
20789#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
20790#undef TARGET_BIG_SYM
20791#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
20792#undef TARGET_BIG_NAME
20793#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 20794
20795/* Like elf32_arm_link_hash_table_create -- but overrides
20796 appropriately for Symbian OS. */
906e58ca 20797
7f266840
DJ		 20798static struct bfd_link_hash_table *
20799elf32_arm_symbian_link_hash_table_create (bfd *abfd)
20800{
20801 struct bfd_link_hash_table *ret;
20802
20803 ret = elf32_arm_link_hash_table_create (abfd);
20804 if (ret)
20805 {
20806 struct elf32_arm_link_hash_table *htab
20807 = (struct elf32_arm_link_hash_table *)ret;
20808 /* There is no PLT header for Symbian OS. */
20809 htab->plt_header_size = 0;
95720a86
DJ		 20810 /* The PLT entries are each one instruction and one word. */
20811 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
33bfe774
JB		 20812 /* Symbian uses armv5t or above, so use_blx is always true. */
20813 htab->use_blx = 1;
67687978 20814 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 20815 }
20816 return ret;
906e58ca 20817}
7f266840 20818
b35d266b 20819static const struct bfd_elf_special_section
551b43fd 20820elf32_arm_symbian_special_sections[] =
7f266840 20821{
5cd3778d
MM		 20822 /* In a BPABI executable, the dynamic linking sections do not go in
20823 the loadable read-only segment. The post-linker may wish to
20824 refer to these sections, but they are not part of the final
20825 program image. */
07d6d2b8
AM		 20826 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
20827 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
20828 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
20829 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
20830 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 20831 /* These sections do not need to be writable as the SymbianOS
20832 postlinker will arrange things so that no dynamic relocation is
20833 required. */
07d6d2b8
AM		 20834 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
20835 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 20836 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 20837 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 20838};
20839
c3c76620 20840static void
906e58ca 20841elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 20842 struct bfd_link_info *link_info)
c3c76620
MM		 20843{
20844 /* BPABI objects are never loaded directly by an OS kernel; they are
20845 processed by a postlinker first, into an OS-specific format. If
20846 the D_PAGED bit is set on the file, BFD will align segments on
20847 page boundaries, so that an OS can directly map the file. With
20848 BPABI objects, that just results in wasted space. In addition,
20849 because we clear the D_PAGED bit, map_sections_to_segments will
20850 recognize that the program headers should not be mapped into any
20851 loadable segment. */
20852 abfd->flags &= ~D_PAGED;
906e58ca 20853 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 20854}
7f266840
DJ		 20855
20856static bfd_boolean
906e58ca 20857elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 20858 struct bfd_link_info *info)
7f266840
DJ		 20859{
20860 struct elf_segment_map *m;
20861 asection *dynsec;
20862
7f266840
DJ		 20863 /* BPABI shared libraries and executables should have a PT_DYNAMIC
20864 segment. However, because the .dynamic section is not marked
20865 with SEC_LOAD, the generic ELF code will not create such a
20866 segment. */
20867 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
20868 if (dynsec)
20869 {
12bd6957 20870 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 20871 if (m->p_type == PT_DYNAMIC)
20872 break;
20873
20874 if (m == NULL)
20875 {
20876 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 20877 m->next = elf_seg_map (abfd);
20878 elf_seg_map (abfd) = m;
8ded5a0f 20879 }
7f266840
DJ		 20880 }
20881
b294bdf8
MM		 20882 /* Also call the generic arm routine. */
20883 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 20884}
20885
95720a86
DJ		 20886/* Return address for Ith PLT stub in section PLT, for relocation REL
20887 or (bfd_vma) -1 if it should not be included. */
20888
20889static bfd_vma
20890elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
20891 const arelent *rel ATTRIBUTE_UNUSED)
20892{
20893 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
20894}
20895
8029a119 20896#undef elf32_bed
7f266840
DJ		 20897#define elf32_bed elf32_arm_symbian_bed
20898
20899/* The dynamic sections are not allocated on SymbianOS; the postlinker
20900 will process them and then discard them. */
906e58ca 20901#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 20902#define ELF_DYNAMIC_SEC_FLAGS \
20903 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
20904
9eaff861 20905#undef elf_backend_emit_relocs
c3c76620 20906
906e58ca
NC		 20907#undef bfd_elf32_bfd_link_hash_table_create
20908#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
20909#undef elf_backend_special_sections
07d6d2b8 20910#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 20911#undef elf_backend_begin_write_processing
20912#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
20913#undef elf_backend_final_write_processing
20914#define elf_backend_final_write_processing elf32_arm_final_write_processing
20915
20916#undef elf_backend_modify_segment_map
7f266840
DJ		 20917#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
20918
20919/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 20920#undef elf_backend_got_header_size
7f266840
DJ		 20921#define elf_backend_got_header_size 0
20922
20923/* Similarly, there is no .got.plt section. */
906e58ca 20924#undef elf_backend_want_got_plt
7f266840
DJ		 20925#define elf_backend_want_got_plt 0
20926
906e58ca 20927#undef elf_backend_plt_sym_val
95720a86
DJ		 20928#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
20929
906e58ca 20930#undef elf_backend_may_use_rel_p
00a97672 20931#define elf_backend_may_use_rel_p 1
906e58ca 20932#undef elf_backend_may_use_rela_p
00a97672 20933#define elf_backend_may_use_rela_p 0
906e58ca 20934#undef elf_backend_default_use_rela_p
00a97672 20935#define elf_backend_default_use_rela_p 0
906e58ca 20936#undef elf_backend_want_plt_sym
00a97672 20937#define elf_backend_want_plt_sym 0
64f52338
AM		 20938#undef elf_backend_dtrel_excludes_plt
20939#define elf_backend_dtrel_excludes_plt 0
906e58ca 20940#undef ELF_MAXPAGESIZE
00a97672 20941#define ELF_MAXPAGESIZE 0x8000
90c14f0c
L		 20942#undef ELF_TARGET_OS
20943#define ELF_TARGET_OS is_symbian
4e7fd91e 20944
7f266840 20945#include "elf32-target.h"
GDB Binutils - Deliverables
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