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Check corrupt VTENTRY entry in bfd_elf_gc_record_vtentry
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
82704155 2 Copyright (C) 1998-2019 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
00a97672 25#include "libiberty.h"
7f266840
DJ		 26#include "libbfd.h"
27#include "elf-bfd.h"
b38cadfb 28#include "elf-nacl.h"
00a97672 29#include "elf-vxworks.h"
ee065d83 30#include "elf/arm.h"
7f266840 31
00a97672
RS		 32/* Return the relocation section associated with NAME. HTAB is the
33 bfd's elf32_arm_link_hash_entry. */
34#define RELOC_SECTION(HTAB, NAME) \
35 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
36
37/* Return size of a relocation entry. HTAB is the bfd's
38 elf32_arm_link_hash_entry. */
39#define RELOC_SIZE(HTAB) \
40 ((HTAB)->use_rel \
41 ? sizeof (Elf32_External_Rel) \
42 : sizeof (Elf32_External_Rela))
43
44/* Return function to swap relocations in. HTAB is the bfd's
45 elf32_arm_link_hash_entry. */
46#define SWAP_RELOC_IN(HTAB) \
47 ((HTAB)->use_rel \
48 ? bfd_elf32_swap_reloc_in \
49 : bfd_elf32_swap_reloca_in)
50
51/* Return function to swap relocations out. HTAB is the bfd's
52 elf32_arm_link_hash_entry. */
53#define SWAP_RELOC_OUT(HTAB) \
54 ((HTAB)->use_rel \
55 ? bfd_elf32_swap_reloc_out \
56 : bfd_elf32_swap_reloca_out)
57
f3185997 58#define elf_info_to_howto NULL
07d6d2b8 59#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 60
61#define ARM_ELF_ABI_VERSION 0
62#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
63
79f08007
YZ		 64/* The Adjusted Place, as defined by AAELF. */
65#define Pa(X) ((X) & 0xfffffffc)
66
3e6b1042
DJ		 67static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
68 struct bfd_link_info *link_info,
69 asection *sec,
70 bfd_byte *contents);
71
7f266840
DJ		 72/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
73 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
74 in that slot. */
75
c19d1205 76static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 77{
8029a119 78 /* No relocation. */
7f266840
DJ		 79 HOWTO (R_ARM_NONE, /* type */
80 0, /* rightshift */
6346d5ca 81 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 82 0, /* bitsize */
83 FALSE, /* pc_relative */
84 0, /* bitpos */
85 complain_overflow_dont,/* complain_on_overflow */
86 bfd_elf_generic_reloc, /* special_function */
87 "R_ARM_NONE", /* name */
88 FALSE, /* partial_inplace */
89 0, /* src_mask */
90 0, /* dst_mask */
91 FALSE), /* pcrel_offset */
92
93 HOWTO (R_ARM_PC24, /* type */
94 2, /* rightshift */
95 2, /* size (0 = byte, 1 = short, 2 = long) */
96 24, /* bitsize */
97 TRUE, /* pc_relative */
98 0, /* bitpos */
99 complain_overflow_signed,/* complain_on_overflow */
100 bfd_elf_generic_reloc, /* special_function */
101 "R_ARM_PC24", /* name */
102 FALSE, /* partial_inplace */
103 0x00ffffff, /* src_mask */
104 0x00ffffff, /* dst_mask */
105 TRUE), /* pcrel_offset */
106
107 /* 32 bit absolute */
108 HOWTO (R_ARM_ABS32, /* type */
109 0, /* rightshift */
110 2, /* size (0 = byte, 1 = short, 2 = long) */
111 32, /* bitsize */
112 FALSE, /* pc_relative */
113 0, /* bitpos */
114 complain_overflow_bitfield,/* complain_on_overflow */
115 bfd_elf_generic_reloc, /* special_function */
116 "R_ARM_ABS32", /* name */
117 FALSE, /* partial_inplace */
118 0xffffffff, /* src_mask */
119 0xffffffff, /* dst_mask */
120 FALSE), /* pcrel_offset */
121
122 /* standard 32bit pc-relative reloc */
123 HOWTO (R_ARM_REL32, /* type */
124 0, /* rightshift */
125 2, /* size (0 = byte, 1 = short, 2 = long) */
126 32, /* bitsize */
127 TRUE, /* pc_relative */
128 0, /* bitpos */
129 complain_overflow_bitfield,/* complain_on_overflow */
130 bfd_elf_generic_reloc, /* special_function */
131 "R_ARM_REL32", /* name */
132 FALSE, /* partial_inplace */
133 0xffffffff, /* src_mask */
134 0xffffffff, /* dst_mask */
135 TRUE), /* pcrel_offset */
136
c19d1205 137 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 138 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 139 0, /* rightshift */
140 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 141 32, /* bitsize */
142 TRUE, /* pc_relative */
7f266840 143 0, /* bitpos */
4962c51a 144 complain_overflow_dont,/* complain_on_overflow */
7f266840 145 bfd_elf_generic_reloc, /* special_function */
4962c51a 146 "R_ARM_LDR_PC_G0", /* name */
7f266840 147 FALSE, /* partial_inplace */
4962c51a
MS		 148 0xffffffff, /* src_mask */
149 0xffffffff, /* dst_mask */
150 TRUE), /* pcrel_offset */
7f266840
DJ		 151
152 /* 16 bit absolute */
153 HOWTO (R_ARM_ABS16, /* type */
154 0, /* rightshift */
155 1, /* size (0 = byte, 1 = short, 2 = long) */
156 16, /* bitsize */
157 FALSE, /* pc_relative */
158 0, /* bitpos */
159 complain_overflow_bitfield,/* complain_on_overflow */
160 bfd_elf_generic_reloc, /* special_function */
161 "R_ARM_ABS16", /* name */
162 FALSE, /* partial_inplace */
163 0x0000ffff, /* src_mask */
164 0x0000ffff, /* dst_mask */
165 FALSE), /* pcrel_offset */
166
167 /* 12 bit absolute */
168 HOWTO (R_ARM_ABS12, /* type */
169 0, /* rightshift */
170 2, /* size (0 = byte, 1 = short, 2 = long) */
171 12, /* bitsize */
172 FALSE, /* pc_relative */
173 0, /* bitpos */
174 complain_overflow_bitfield,/* complain_on_overflow */
175 bfd_elf_generic_reloc, /* special_function */
176 "R_ARM_ABS12", /* name */
177 FALSE, /* partial_inplace */
00a97672
RS		 178 0x00000fff, /* src_mask */
179 0x00000fff, /* dst_mask */
7f266840
DJ		 180 FALSE), /* pcrel_offset */
181
182 HOWTO (R_ARM_THM_ABS5, /* type */
183 6, /* rightshift */
184 1, /* size (0 = byte, 1 = short, 2 = long) */
185 5, /* bitsize */
186 FALSE, /* pc_relative */
187 0, /* bitpos */
188 complain_overflow_bitfield,/* complain_on_overflow */
189 bfd_elf_generic_reloc, /* special_function */
190 "R_ARM_THM_ABS5", /* name */
191 FALSE, /* partial_inplace */
192 0x000007e0, /* src_mask */
193 0x000007e0, /* dst_mask */
194 FALSE), /* pcrel_offset */
195
196 /* 8 bit absolute */
197 HOWTO (R_ARM_ABS8, /* type */
198 0, /* rightshift */
199 0, /* size (0 = byte, 1 = short, 2 = long) */
200 8, /* bitsize */
201 FALSE, /* pc_relative */
202 0, /* bitpos */
203 complain_overflow_bitfield,/* complain_on_overflow */
204 bfd_elf_generic_reloc, /* special_function */
205 "R_ARM_ABS8", /* name */
206 FALSE, /* partial_inplace */
207 0x000000ff, /* src_mask */
208 0x000000ff, /* dst_mask */
209 FALSE), /* pcrel_offset */
210
211 HOWTO (R_ARM_SBREL32, /* type */
212 0, /* rightshift */
213 2, /* size (0 = byte, 1 = short, 2 = long) */
214 32, /* bitsize */
215 FALSE, /* pc_relative */
216 0, /* bitpos */
217 complain_overflow_dont,/* complain_on_overflow */
218 bfd_elf_generic_reloc, /* special_function */
219 "R_ARM_SBREL32", /* name */
220 FALSE, /* partial_inplace */
221 0xffffffff, /* src_mask */
222 0xffffffff, /* dst_mask */
223 FALSE), /* pcrel_offset */
224
c19d1205 225 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 226 1, /* rightshift */
227 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 228 24, /* bitsize */
7f266840
DJ		 229 TRUE, /* pc_relative */
230 0, /* bitpos */
231 complain_overflow_signed,/* complain_on_overflow */
232 bfd_elf_generic_reloc, /* special_function */
c19d1205 233 "R_ARM_THM_CALL", /* name */
7f266840 234 FALSE, /* partial_inplace */
7f6ab9f8
AM		 235 0x07ff2fff, /* src_mask */
236 0x07ff2fff, /* dst_mask */
7f266840
DJ		 237 TRUE), /* pcrel_offset */
238
07d6d2b8 239 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 240 1, /* rightshift */
241 1, /* size (0 = byte, 1 = short, 2 = long) */
242 8, /* bitsize */
243 TRUE, /* pc_relative */
244 0, /* bitpos */
245 complain_overflow_signed,/* complain_on_overflow */
246 bfd_elf_generic_reloc, /* special_function */
247 "R_ARM_THM_PC8", /* name */
248 FALSE, /* partial_inplace */
249 0x000000ff, /* src_mask */
250 0x000000ff, /* dst_mask */
251 TRUE), /* pcrel_offset */
252
c19d1205 253 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 254 1, /* rightshift */
255 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 256 32, /* bitsize */
257 FALSE, /* pc_relative */
7f266840
DJ		 258 0, /* bitpos */
259 complain_overflow_signed,/* complain_on_overflow */
260 bfd_elf_generic_reloc, /* special_function */
c19d1205 261 "R_ARM_BREL_ADJ", /* name */
7f266840 262 FALSE, /* partial_inplace */
c19d1205
ZW		 263 0xffffffff, /* src_mask */
264 0xffffffff, /* dst_mask */
265 FALSE), /* pcrel_offset */
7f266840 266
0855e32b 267 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 268 0, /* rightshift */
0855e32b
NS		 269 2, /* size (0 = byte, 1 = short, 2 = long) */
270 32, /* bitsize */
7f266840
DJ		 271 FALSE, /* pc_relative */
272 0, /* bitpos */
0855e32b 273 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 274 bfd_elf_generic_reloc, /* special_function */
0855e32b 275 "R_ARM_TLS_DESC", /* name */
7f266840 276 FALSE, /* partial_inplace */
0855e32b
NS		 277 0xffffffff, /* src_mask */
278 0xffffffff, /* dst_mask */
7f266840
DJ		 279 FALSE), /* pcrel_offset */
280
281 HOWTO (R_ARM_THM_SWI8, /* type */
282 0, /* rightshift */
283 0, /* size (0 = byte, 1 = short, 2 = long) */
284 0, /* bitsize */
285 FALSE, /* pc_relative */
286 0, /* bitpos */
287 complain_overflow_signed,/* complain_on_overflow */
288 bfd_elf_generic_reloc, /* special_function */
289 "R_ARM_SWI8", /* name */
290 FALSE, /* partial_inplace */
291 0x00000000, /* src_mask */
292 0x00000000, /* dst_mask */
293 FALSE), /* pcrel_offset */
294
295 /* BLX instruction for the ARM. */
296 HOWTO (R_ARM_XPC25, /* type */
297 2, /* rightshift */
298 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 299 24, /* bitsize */
7f266840
DJ		 300 TRUE, /* pc_relative */
301 0, /* bitpos */
302 complain_overflow_signed,/* complain_on_overflow */
303 bfd_elf_generic_reloc, /* special_function */
304 "R_ARM_XPC25", /* name */
305 FALSE, /* partial_inplace */
306 0x00ffffff, /* src_mask */
307 0x00ffffff, /* dst_mask */
308 TRUE), /* pcrel_offset */
309
310 /* BLX instruction for the Thumb. */
311 HOWTO (R_ARM_THM_XPC22, /* type */
312 2, /* rightshift */
313 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 314 24, /* bitsize */
7f266840
DJ		 315 TRUE, /* pc_relative */
316 0, /* bitpos */
317 complain_overflow_signed,/* complain_on_overflow */
318 bfd_elf_generic_reloc, /* special_function */
319 "R_ARM_THM_XPC22", /* name */
320 FALSE, /* partial_inplace */
7f6ab9f8
AM		 321 0x07ff2fff, /* src_mask */
322 0x07ff2fff, /* dst_mask */
7f266840
DJ		 323 TRUE), /* pcrel_offset */
324
ba93b8ac 325 /* Dynamic TLS relocations. */
7f266840 326
ba93b8ac 327 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 328 0, /* rightshift */
329 2, /* size (0 = byte, 1 = short, 2 = long) */
330 32, /* bitsize */
331 FALSE, /* pc_relative */
332 0, /* bitpos */
99059e56
RM		 333 complain_overflow_bitfield,/* complain_on_overflow */
334 bfd_elf_generic_reloc, /* special_function */
335 "R_ARM_TLS_DTPMOD32", /* name */
336 TRUE, /* partial_inplace */
337 0xffffffff, /* src_mask */
338 0xffffffff, /* dst_mask */
07d6d2b8 339 FALSE), /* pcrel_offset */
7f266840 340
ba93b8ac 341 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 342 0, /* rightshift */
343 2, /* size (0 = byte, 1 = short, 2 = long) */
344 32, /* bitsize */
345 FALSE, /* pc_relative */
346 0, /* bitpos */
99059e56
RM		 347 complain_overflow_bitfield,/* complain_on_overflow */
348 bfd_elf_generic_reloc, /* special_function */
349 "R_ARM_TLS_DTPOFF32", /* name */
350 TRUE, /* partial_inplace */
351 0xffffffff, /* src_mask */
352 0xffffffff, /* dst_mask */
07d6d2b8 353 FALSE), /* pcrel_offset */
7f266840 354
ba93b8ac 355 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 356 0, /* rightshift */
357 2, /* size (0 = byte, 1 = short, 2 = long) */
358 32, /* bitsize */
359 FALSE, /* pc_relative */
360 0, /* bitpos */
99059e56
RM		 361 complain_overflow_bitfield,/* complain_on_overflow */
362 bfd_elf_generic_reloc, /* special_function */
363 "R_ARM_TLS_TPOFF32", /* name */
364 TRUE, /* partial_inplace */
365 0xffffffff, /* src_mask */
366 0xffffffff, /* dst_mask */
07d6d2b8 367 FALSE), /* pcrel_offset */
7f266840
DJ		 368
369 /* Relocs used in ARM Linux */
370
371 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 372 0, /* rightshift */
373 2, /* size (0 = byte, 1 = short, 2 = long) */
374 32, /* bitsize */
375 FALSE, /* pc_relative */
376 0, /* bitpos */
99059e56
RM		 377 complain_overflow_bitfield,/* complain_on_overflow */
378 bfd_elf_generic_reloc, /* special_function */
379 "R_ARM_COPY", /* name */
380 TRUE, /* partial_inplace */
381 0xffffffff, /* src_mask */
382 0xffffffff, /* dst_mask */
07d6d2b8 383 FALSE), /* pcrel_offset */
7f266840
DJ		 384
385 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 386 0, /* rightshift */
387 2, /* size (0 = byte, 1 = short, 2 = long) */
388 32, /* bitsize */
389 FALSE, /* pc_relative */
390 0, /* bitpos */
99059e56
RM		 391 complain_overflow_bitfield,/* complain_on_overflow */
392 bfd_elf_generic_reloc, /* special_function */
393 "R_ARM_GLOB_DAT", /* name */
394 TRUE, /* partial_inplace */
395 0xffffffff, /* src_mask */
396 0xffffffff, /* dst_mask */
07d6d2b8 397 FALSE), /* pcrel_offset */
7f266840
DJ		 398
399 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 400 0, /* rightshift */
401 2, /* size (0 = byte, 1 = short, 2 = long) */
402 32, /* bitsize */
403 FALSE, /* pc_relative */
404 0, /* bitpos */
99059e56
RM		 405 complain_overflow_bitfield,/* complain_on_overflow */
406 bfd_elf_generic_reloc, /* special_function */
407 "R_ARM_JUMP_SLOT", /* name */
408 TRUE, /* partial_inplace */
409 0xffffffff, /* src_mask */
410 0xffffffff, /* dst_mask */
07d6d2b8 411 FALSE), /* pcrel_offset */
7f266840
DJ		 412
413 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 414 0, /* rightshift */
415 2, /* size (0 = byte, 1 = short, 2 = long) */
416 32, /* bitsize */
417 FALSE, /* pc_relative */
418 0, /* bitpos */
99059e56
RM		 419 complain_overflow_bitfield,/* complain_on_overflow */
420 bfd_elf_generic_reloc, /* special_function */
421 "R_ARM_RELATIVE", /* name */
422 TRUE, /* partial_inplace */
423 0xffffffff, /* src_mask */
424 0xffffffff, /* dst_mask */
07d6d2b8 425 FALSE), /* pcrel_offset */
7f266840 426
c19d1205 427 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 428 0, /* rightshift */
429 2, /* size (0 = byte, 1 = short, 2 = long) */
430 32, /* bitsize */
431 FALSE, /* pc_relative */
432 0, /* bitpos */
99059e56
RM		 433 complain_overflow_bitfield,/* complain_on_overflow */
434 bfd_elf_generic_reloc, /* special_function */
435 "R_ARM_GOTOFF32", /* name */
436 TRUE, /* partial_inplace */
437 0xffffffff, /* src_mask */
438 0xffffffff, /* dst_mask */
07d6d2b8 439 FALSE), /* pcrel_offset */
7f266840
DJ		 440
441 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 442 0, /* rightshift */
443 2, /* size (0 = byte, 1 = short, 2 = long) */
444 32, /* bitsize */
99059e56 445 TRUE, /* pc_relative */
07d6d2b8 446 0, /* bitpos */
99059e56
RM		 447 complain_overflow_bitfield,/* complain_on_overflow */
448 bfd_elf_generic_reloc, /* special_function */
449 "R_ARM_GOTPC", /* name */
450 TRUE, /* partial_inplace */
451 0xffffffff, /* src_mask */
452 0xffffffff, /* dst_mask */
453 TRUE), /* pcrel_offset */
7f266840
DJ		 454
455 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 456 0, /* rightshift */
457 2, /* size (0 = byte, 1 = short, 2 = long) */
458 32, /* bitsize */
99059e56 459 FALSE, /* pc_relative */
07d6d2b8 460 0, /* bitpos */
99059e56
RM		 461 complain_overflow_bitfield,/* complain_on_overflow */
462 bfd_elf_generic_reloc, /* special_function */
463 "R_ARM_GOT32", /* name */
464 TRUE, /* partial_inplace */
465 0xffffffff, /* src_mask */
466 0xffffffff, /* dst_mask */
467 FALSE), /* pcrel_offset */
7f266840
DJ		 468
469 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 470 2, /* rightshift */
471 2, /* size (0 = byte, 1 = short, 2 = long) */
472 24, /* bitsize */
99059e56 473 TRUE, /* pc_relative */
07d6d2b8 474 0, /* bitpos */
99059e56
RM		 475 complain_overflow_bitfield,/* complain_on_overflow */
476 bfd_elf_generic_reloc, /* special_function */
477 "R_ARM_PLT32", /* name */
478 FALSE, /* partial_inplace */
479 0x00ffffff, /* src_mask */
480 0x00ffffff, /* dst_mask */
481 TRUE), /* pcrel_offset */
7f266840
DJ		 482
483 HOWTO (R_ARM_CALL, /* type */
484 2, /* rightshift */
485 2, /* size (0 = byte, 1 = short, 2 = long) */
486 24, /* bitsize */
487 TRUE, /* pc_relative */
488 0, /* bitpos */
489 complain_overflow_signed,/* complain_on_overflow */
490 bfd_elf_generic_reloc, /* special_function */
491 "R_ARM_CALL", /* name */
492 FALSE, /* partial_inplace */
493 0x00ffffff, /* src_mask */
494 0x00ffffff, /* dst_mask */
495 TRUE), /* pcrel_offset */
496
497 HOWTO (R_ARM_JUMP24, /* type */
498 2, /* rightshift */
499 2, /* size (0 = byte, 1 = short, 2 = long) */
500 24, /* bitsize */
501 TRUE, /* pc_relative */
502 0, /* bitpos */
503 complain_overflow_signed,/* complain_on_overflow */
504 bfd_elf_generic_reloc, /* special_function */
505 "R_ARM_JUMP24", /* name */
506 FALSE, /* partial_inplace */
507 0x00ffffff, /* src_mask */
508 0x00ffffff, /* dst_mask */
509 TRUE), /* pcrel_offset */
510
c19d1205
ZW		 511 HOWTO (R_ARM_THM_JUMP24, /* type */
512 1, /* rightshift */
513 2, /* size (0 = byte, 1 = short, 2 = long) */
514 24, /* bitsize */
515 TRUE, /* pc_relative */
7f266840 516 0, /* bitpos */
c19d1205 517 complain_overflow_signed,/* complain_on_overflow */
7f266840 518 bfd_elf_generic_reloc, /* special_function */
c19d1205 519 "R_ARM_THM_JUMP24", /* name */
7f266840 520 FALSE, /* partial_inplace */
c19d1205
ZW		 521 0x07ff2fff, /* src_mask */
522 0x07ff2fff, /* dst_mask */
523 TRUE), /* pcrel_offset */
7f266840 524
c19d1205 525 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 526 0, /* rightshift */
c19d1205
ZW		 527 2, /* size (0 = byte, 1 = short, 2 = long) */
528 32, /* bitsize */
7f266840
DJ		 529 FALSE, /* pc_relative */
530 0, /* bitpos */
531 complain_overflow_dont,/* complain_on_overflow */
532 bfd_elf_generic_reloc, /* special_function */
c19d1205 533 "R_ARM_BASE_ABS", /* name */
7f266840 534 FALSE, /* partial_inplace */
c19d1205
ZW		 535 0xffffffff, /* src_mask */
536 0xffffffff, /* dst_mask */
7f266840
DJ		 537 FALSE), /* pcrel_offset */
538
539 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
540 0, /* rightshift */
541 2, /* size (0 = byte, 1 = short, 2 = long) */
542 12, /* bitsize */
543 TRUE, /* pc_relative */
544 0, /* bitpos */
545 complain_overflow_dont,/* complain_on_overflow */
546 bfd_elf_generic_reloc, /* special_function */
547 "R_ARM_ALU_PCREL_7_0", /* name */
548 FALSE, /* partial_inplace */
549 0x00000fff, /* src_mask */
550 0x00000fff, /* dst_mask */
551 TRUE), /* pcrel_offset */
552
553 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
554 0, /* rightshift */
555 2, /* size (0 = byte, 1 = short, 2 = long) */
556 12, /* bitsize */
557 TRUE, /* pc_relative */
558 8, /* bitpos */
559 complain_overflow_dont,/* complain_on_overflow */
560 bfd_elf_generic_reloc, /* special_function */
561 "R_ARM_ALU_PCREL_15_8",/* name */
562 FALSE, /* partial_inplace */
563 0x00000fff, /* src_mask */
564 0x00000fff, /* dst_mask */
565 TRUE), /* pcrel_offset */
566
567 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
568 0, /* rightshift */
569 2, /* size (0 = byte, 1 = short, 2 = long) */
570 12, /* bitsize */
571 TRUE, /* pc_relative */
572 16, /* bitpos */
573 complain_overflow_dont,/* complain_on_overflow */
574 bfd_elf_generic_reloc, /* special_function */
575 "R_ARM_ALU_PCREL_23_15",/* name */
576 FALSE, /* partial_inplace */
577 0x00000fff, /* src_mask */
578 0x00000fff, /* dst_mask */
579 TRUE), /* pcrel_offset */
580
581 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
582 0, /* rightshift */
583 2, /* size (0 = byte, 1 = short, 2 = long) */
584 12, /* bitsize */
585 FALSE, /* pc_relative */
586 0, /* bitpos */
587 complain_overflow_dont,/* complain_on_overflow */
588 bfd_elf_generic_reloc, /* special_function */
589 "R_ARM_LDR_SBREL_11_0",/* name */
590 FALSE, /* partial_inplace */
591 0x00000fff, /* src_mask */
592 0x00000fff, /* dst_mask */
593 FALSE), /* pcrel_offset */
594
595 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
596 0, /* rightshift */
597 2, /* size (0 = byte, 1 = short, 2 = long) */
598 8, /* bitsize */
599 FALSE, /* pc_relative */
600 12, /* bitpos */
601 complain_overflow_dont,/* complain_on_overflow */
602 bfd_elf_generic_reloc, /* special_function */
603 "R_ARM_ALU_SBREL_19_12",/* name */
604 FALSE, /* partial_inplace */
605 0x000ff000, /* src_mask */
606 0x000ff000, /* dst_mask */
607 FALSE), /* pcrel_offset */
608
609 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
610 0, /* rightshift */
611 2, /* size (0 = byte, 1 = short, 2 = long) */
612 8, /* bitsize */
613 FALSE, /* pc_relative */
614 20, /* bitpos */
615 complain_overflow_dont,/* complain_on_overflow */
616 bfd_elf_generic_reloc, /* special_function */
617 "R_ARM_ALU_SBREL_27_20",/* name */
618 FALSE, /* partial_inplace */
619 0x0ff00000, /* src_mask */
620 0x0ff00000, /* dst_mask */
621 FALSE), /* pcrel_offset */
622
623 HOWTO (R_ARM_TARGET1, /* type */
624 0, /* rightshift */
625 2, /* size (0 = byte, 1 = short, 2 = long) */
626 32, /* bitsize */
627 FALSE, /* pc_relative */
628 0, /* bitpos */
629 complain_overflow_dont,/* complain_on_overflow */
630 bfd_elf_generic_reloc, /* special_function */
631 "R_ARM_TARGET1", /* name */
632 FALSE, /* partial_inplace */
633 0xffffffff, /* src_mask */
634 0xffffffff, /* dst_mask */
635 FALSE), /* pcrel_offset */
636
637 HOWTO (R_ARM_ROSEGREL32, /* type */
638 0, /* rightshift */
639 2, /* size (0 = byte, 1 = short, 2 = long) */
640 32, /* bitsize */
641 FALSE, /* pc_relative */
642 0, /* bitpos */
643 complain_overflow_dont,/* complain_on_overflow */
644 bfd_elf_generic_reloc, /* special_function */
645 "R_ARM_ROSEGREL32", /* name */
646 FALSE, /* partial_inplace */
647 0xffffffff, /* src_mask */
648 0xffffffff, /* dst_mask */
649 FALSE), /* pcrel_offset */
650
651 HOWTO (R_ARM_V4BX, /* type */
652 0, /* rightshift */
653 2, /* size (0 = byte, 1 = short, 2 = long) */
654 32, /* bitsize */
655 FALSE, /* pc_relative */
656 0, /* bitpos */
657 complain_overflow_dont,/* complain_on_overflow */
658 bfd_elf_generic_reloc, /* special_function */
659 "R_ARM_V4BX", /* name */
660 FALSE, /* partial_inplace */
661 0xffffffff, /* src_mask */
662 0xffffffff, /* dst_mask */
663 FALSE), /* pcrel_offset */
664
665 HOWTO (R_ARM_TARGET2, /* type */
666 0, /* rightshift */
667 2, /* size (0 = byte, 1 = short, 2 = long) */
668 32, /* bitsize */
669 FALSE, /* pc_relative */
670 0, /* bitpos */
671 complain_overflow_signed,/* complain_on_overflow */
672 bfd_elf_generic_reloc, /* special_function */
673 "R_ARM_TARGET2", /* name */
674 FALSE, /* partial_inplace */
675 0xffffffff, /* src_mask */
676 0xffffffff, /* dst_mask */
677 TRUE), /* pcrel_offset */
678
679 HOWTO (R_ARM_PREL31, /* type */
680 0, /* rightshift */
681 2, /* size (0 = byte, 1 = short, 2 = long) */
682 31, /* bitsize */
683 TRUE, /* pc_relative */
684 0, /* bitpos */
685 complain_overflow_signed,/* complain_on_overflow */
686 bfd_elf_generic_reloc, /* special_function */
687 "R_ARM_PREL31", /* name */
688 FALSE, /* partial_inplace */
689 0x7fffffff, /* src_mask */
690 0x7fffffff, /* dst_mask */
691 TRUE), /* pcrel_offset */
c19d1205
ZW		 692
693 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
694 0, /* rightshift */
695 2, /* size (0 = byte, 1 = short, 2 = long) */
696 16, /* bitsize */
697 FALSE, /* pc_relative */
698 0, /* bitpos */
699 complain_overflow_dont,/* complain_on_overflow */
700 bfd_elf_generic_reloc, /* special_function */
701 "R_ARM_MOVW_ABS_NC", /* name */
702 FALSE, /* partial_inplace */
39623e12
PB		 703 0x000f0fff, /* src_mask */
704 0x000f0fff, /* dst_mask */
c19d1205
ZW		 705 FALSE), /* pcrel_offset */
706
707 HOWTO (R_ARM_MOVT_ABS, /* type */
708 0, /* rightshift */
709 2, /* size (0 = byte, 1 = short, 2 = long) */
710 16, /* bitsize */
711 FALSE, /* pc_relative */
712 0, /* bitpos */
713 complain_overflow_bitfield,/* complain_on_overflow */
714 bfd_elf_generic_reloc, /* special_function */
715 "R_ARM_MOVT_ABS", /* name */
716 FALSE, /* partial_inplace */
39623e12
PB		 717 0x000f0fff, /* src_mask */
718 0x000f0fff, /* dst_mask */
c19d1205
ZW		 719 FALSE), /* pcrel_offset */
720
721 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
722 0, /* rightshift */
723 2, /* size (0 = byte, 1 = short, 2 = long) */
724 16, /* bitsize */
725 TRUE, /* pc_relative */
726 0, /* bitpos */
727 complain_overflow_dont,/* complain_on_overflow */
728 bfd_elf_generic_reloc, /* special_function */
729 "R_ARM_MOVW_PREL_NC", /* name */
730 FALSE, /* partial_inplace */
39623e12
PB		 731 0x000f0fff, /* src_mask */
732 0x000f0fff, /* dst_mask */
c19d1205
ZW		 733 TRUE), /* pcrel_offset */
734
735 HOWTO (R_ARM_MOVT_PREL, /* type */
736 0, /* rightshift */
737 2, /* size (0 = byte, 1 = short, 2 = long) */
738 16, /* bitsize */
739 TRUE, /* pc_relative */
740 0, /* bitpos */
741 complain_overflow_bitfield,/* complain_on_overflow */
742 bfd_elf_generic_reloc, /* special_function */
743 "R_ARM_MOVT_PREL", /* name */
744 FALSE, /* partial_inplace */
39623e12
PB		 745 0x000f0fff, /* src_mask */
746 0x000f0fff, /* dst_mask */
c19d1205
ZW		 747 TRUE), /* pcrel_offset */
748
749 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
750 0, /* rightshift */
751 2, /* size (0 = byte, 1 = short, 2 = long) */
752 16, /* bitsize */
753 FALSE, /* pc_relative */
754 0, /* bitpos */
755 complain_overflow_dont,/* complain_on_overflow */
756 bfd_elf_generic_reloc, /* special_function */
757 "R_ARM_THM_MOVW_ABS_NC",/* name */
758 FALSE, /* partial_inplace */
759 0x040f70ff, /* src_mask */
760 0x040f70ff, /* dst_mask */
761 FALSE), /* pcrel_offset */
762
763 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
764 0, /* rightshift */
765 2, /* size (0 = byte, 1 = short, 2 = long) */
766 16, /* bitsize */
767 FALSE, /* pc_relative */
768 0, /* bitpos */
769 complain_overflow_bitfield,/* complain_on_overflow */
770 bfd_elf_generic_reloc, /* special_function */
771 "R_ARM_THM_MOVT_ABS", /* name */
772 FALSE, /* partial_inplace */
773 0x040f70ff, /* src_mask */
774 0x040f70ff, /* dst_mask */
775 FALSE), /* pcrel_offset */
776
777 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
778 0, /* rightshift */
779 2, /* size (0 = byte, 1 = short, 2 = long) */
780 16, /* bitsize */
781 TRUE, /* pc_relative */
782 0, /* bitpos */
783 complain_overflow_dont,/* complain_on_overflow */
784 bfd_elf_generic_reloc, /* special_function */
785 "R_ARM_THM_MOVW_PREL_NC",/* name */
786 FALSE, /* partial_inplace */
787 0x040f70ff, /* src_mask */
788 0x040f70ff, /* dst_mask */
789 TRUE), /* pcrel_offset */
790
791 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
792 0, /* rightshift */
793 2, /* size (0 = byte, 1 = short, 2 = long) */
794 16, /* bitsize */
795 TRUE, /* pc_relative */
796 0, /* bitpos */
797 complain_overflow_bitfield,/* complain_on_overflow */
798 bfd_elf_generic_reloc, /* special_function */
799 "R_ARM_THM_MOVT_PREL", /* name */
800 FALSE, /* partial_inplace */
801 0x040f70ff, /* src_mask */
802 0x040f70ff, /* dst_mask */
803 TRUE), /* pcrel_offset */
804
805 HOWTO (R_ARM_THM_JUMP19, /* type */
806 1, /* rightshift */
807 2, /* size (0 = byte, 1 = short, 2 = long) */
808 19, /* bitsize */
809 TRUE, /* pc_relative */
810 0, /* bitpos */
811 complain_overflow_signed,/* complain_on_overflow */
812 bfd_elf_generic_reloc, /* special_function */
813 "R_ARM_THM_JUMP19", /* name */
814 FALSE, /* partial_inplace */
815 0x043f2fff, /* src_mask */
816 0x043f2fff, /* dst_mask */
817 TRUE), /* pcrel_offset */
818
819 HOWTO (R_ARM_THM_JUMP6, /* type */
820 1, /* rightshift */
821 1, /* size (0 = byte, 1 = short, 2 = long) */
822 6, /* bitsize */
823 TRUE, /* pc_relative */
824 0, /* bitpos */
825 complain_overflow_unsigned,/* complain_on_overflow */
826 bfd_elf_generic_reloc, /* special_function */
827 "R_ARM_THM_JUMP6", /* name */
828 FALSE, /* partial_inplace */
829 0x02f8, /* src_mask */
830 0x02f8, /* dst_mask */
831 TRUE), /* pcrel_offset */
832
833 /* These are declared as 13-bit signed relocations because we can
834 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
835 versa. */
836 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
837 0, /* rightshift */
838 2, /* size (0 = byte, 1 = short, 2 = long) */
839 13, /* bitsize */
840 TRUE, /* pc_relative */
841 0, /* bitpos */
2cab6cc3 842 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 843 bfd_elf_generic_reloc, /* special_function */
844 "R_ARM_THM_ALU_PREL_11_0",/* name */
845 FALSE, /* partial_inplace */
2cab6cc3
MS		 846 0xffffffff, /* src_mask */
847 0xffffffff, /* dst_mask */
c19d1205
ZW		 848 TRUE), /* pcrel_offset */
849
850 HOWTO (R_ARM_THM_PC12, /* type */
851 0, /* rightshift */
852 2, /* size (0 = byte, 1 = short, 2 = long) */
853 13, /* bitsize */
854 TRUE, /* pc_relative */
855 0, /* bitpos */
2cab6cc3 856 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 857 bfd_elf_generic_reloc, /* special_function */
858 "R_ARM_THM_PC12", /* name */
859 FALSE, /* partial_inplace */
2cab6cc3
MS		 860 0xffffffff, /* src_mask */
861 0xffffffff, /* dst_mask */
c19d1205
ZW		 862 TRUE), /* pcrel_offset */
863
864 HOWTO (R_ARM_ABS32_NOI, /* type */
865 0, /* rightshift */
866 2, /* size (0 = byte, 1 = short, 2 = long) */
867 32, /* bitsize */
868 FALSE, /* pc_relative */
869 0, /* bitpos */
870 complain_overflow_dont,/* complain_on_overflow */
871 bfd_elf_generic_reloc, /* special_function */
872 "R_ARM_ABS32_NOI", /* name */
873 FALSE, /* partial_inplace */
874 0xffffffff, /* src_mask */
875 0xffffffff, /* dst_mask */
876 FALSE), /* pcrel_offset */
877
878 HOWTO (R_ARM_REL32_NOI, /* type */
879 0, /* rightshift */
880 2, /* size (0 = byte, 1 = short, 2 = long) */
881 32, /* bitsize */
882 TRUE, /* pc_relative */
883 0, /* bitpos */
884 complain_overflow_dont,/* complain_on_overflow */
885 bfd_elf_generic_reloc, /* special_function */
886 "R_ARM_REL32_NOI", /* name */
887 FALSE, /* partial_inplace */
888 0xffffffff, /* src_mask */
889 0xffffffff, /* dst_mask */
890 FALSE), /* pcrel_offset */
7f266840 891
4962c51a
MS		 892 /* Group relocations. */
893
894 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
895 0, /* rightshift */
896 2, /* size (0 = byte, 1 = short, 2 = long) */
897 32, /* bitsize */
898 TRUE, /* pc_relative */
899 0, /* bitpos */
900 complain_overflow_dont,/* complain_on_overflow */
901 bfd_elf_generic_reloc, /* special_function */
902 "R_ARM_ALU_PC_G0_NC", /* name */
903 FALSE, /* partial_inplace */
904 0xffffffff, /* src_mask */
905 0xffffffff, /* dst_mask */
906 TRUE), /* pcrel_offset */
907
07d6d2b8 908 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 909 0, /* rightshift */
910 2, /* size (0 = byte, 1 = short, 2 = long) */
911 32, /* bitsize */
912 TRUE, /* pc_relative */
913 0, /* bitpos */
914 complain_overflow_dont,/* complain_on_overflow */
915 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 916 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 917 FALSE, /* partial_inplace */
918 0xffffffff, /* src_mask */
919 0xffffffff, /* dst_mask */
920 TRUE), /* pcrel_offset */
921
922 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
923 0, /* rightshift */
924 2, /* size (0 = byte, 1 = short, 2 = long) */
925 32, /* bitsize */
926 TRUE, /* pc_relative */
927 0, /* bitpos */
928 complain_overflow_dont,/* complain_on_overflow */
929 bfd_elf_generic_reloc, /* special_function */
930 "R_ARM_ALU_PC_G1_NC", /* name */
931 FALSE, /* partial_inplace */
932 0xffffffff, /* src_mask */
933 0xffffffff, /* dst_mask */
934 TRUE), /* pcrel_offset */
935
07d6d2b8 936 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 937 0, /* rightshift */
938 2, /* size (0 = byte, 1 = short, 2 = long) */
939 32, /* bitsize */
940 TRUE, /* pc_relative */
941 0, /* bitpos */
942 complain_overflow_dont,/* complain_on_overflow */
943 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 944 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 945 FALSE, /* partial_inplace */
946 0xffffffff, /* src_mask */
947 0xffffffff, /* dst_mask */
948 TRUE), /* pcrel_offset */
949
07d6d2b8 950 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 951 0, /* rightshift */
952 2, /* size (0 = byte, 1 = short, 2 = long) */
953 32, /* bitsize */
954 TRUE, /* pc_relative */
955 0, /* bitpos */
956 complain_overflow_dont,/* complain_on_overflow */
957 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 958 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 959 FALSE, /* partial_inplace */
960 0xffffffff, /* src_mask */
961 0xffffffff, /* dst_mask */
962 TRUE), /* pcrel_offset */
963
07d6d2b8 964 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 965 0, /* rightshift */
966 2, /* size (0 = byte, 1 = short, 2 = long) */
967 32, /* bitsize */
968 TRUE, /* pc_relative */
969 0, /* bitpos */
970 complain_overflow_dont,/* complain_on_overflow */
971 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 972 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 973 FALSE, /* partial_inplace */
974 0xffffffff, /* src_mask */
975 0xffffffff, /* dst_mask */
976 TRUE), /* pcrel_offset */
977
07d6d2b8 978 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 979 0, /* rightshift */
980 2, /* size (0 = byte, 1 = short, 2 = long) */
981 32, /* bitsize */
982 TRUE, /* pc_relative */
983 0, /* bitpos */
984 complain_overflow_dont,/* complain_on_overflow */
985 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 986 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 987 FALSE, /* partial_inplace */
988 0xffffffff, /* src_mask */
989 0xffffffff, /* dst_mask */
990 TRUE), /* pcrel_offset */
991
07d6d2b8 992 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 993 0, /* rightshift */
994 2, /* size (0 = byte, 1 = short, 2 = long) */
995 32, /* bitsize */
996 TRUE, /* pc_relative */
997 0, /* bitpos */
998 complain_overflow_dont,/* complain_on_overflow */
999 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1000 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1001 FALSE, /* partial_inplace */
1002 0xffffffff, /* src_mask */
1003 0xffffffff, /* dst_mask */
1004 TRUE), /* pcrel_offset */
1005
07d6d2b8 1006 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1007 0, /* rightshift */
1008 2, /* size (0 = byte, 1 = short, 2 = long) */
1009 32, /* bitsize */
1010 TRUE, /* pc_relative */
1011 0, /* bitpos */
1012 complain_overflow_dont,/* complain_on_overflow */
1013 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1014 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1015 FALSE, /* partial_inplace */
1016 0xffffffff, /* src_mask */
1017 0xffffffff, /* dst_mask */
1018 TRUE), /* pcrel_offset */
1019
07d6d2b8 1020 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1021 0, /* rightshift */
1022 2, /* size (0 = byte, 1 = short, 2 = long) */
1023 32, /* bitsize */
1024 TRUE, /* pc_relative */
1025 0, /* bitpos */
1026 complain_overflow_dont,/* complain_on_overflow */
1027 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1028 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1029 FALSE, /* partial_inplace */
1030 0xffffffff, /* src_mask */
1031 0xffffffff, /* dst_mask */
1032 TRUE), /* pcrel_offset */
1033
07d6d2b8 1034 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1035 0, /* rightshift */
1036 2, /* size (0 = byte, 1 = short, 2 = long) */
1037 32, /* bitsize */
1038 TRUE, /* pc_relative */
1039 0, /* bitpos */
1040 complain_overflow_dont,/* complain_on_overflow */
1041 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1042 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1043 FALSE, /* partial_inplace */
1044 0xffffffff, /* src_mask */
1045 0xffffffff, /* dst_mask */
1046 TRUE), /* pcrel_offset */
1047
07d6d2b8 1048 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1049 0, /* rightshift */
1050 2, /* size (0 = byte, 1 = short, 2 = long) */
1051 32, /* bitsize */
1052 TRUE, /* pc_relative */
1053 0, /* bitpos */
1054 complain_overflow_dont,/* complain_on_overflow */
1055 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1056 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1057 FALSE, /* partial_inplace */
1058 0xffffffff, /* src_mask */
1059 0xffffffff, /* dst_mask */
1060 TRUE), /* pcrel_offset */
1061
07d6d2b8 1062 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1063 0, /* rightshift */
1064 2, /* size (0 = byte, 1 = short, 2 = long) */
1065 32, /* bitsize */
1066 TRUE, /* pc_relative */
1067 0, /* bitpos */
1068 complain_overflow_dont,/* complain_on_overflow */
1069 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1070 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1071 FALSE, /* partial_inplace */
1072 0xffffffff, /* src_mask */
1073 0xffffffff, /* dst_mask */
1074 TRUE), /* pcrel_offset */
1075
07d6d2b8 1076 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1077 0, /* rightshift */
1078 2, /* size (0 = byte, 1 = short, 2 = long) */
1079 32, /* bitsize */
1080 TRUE, /* pc_relative */
1081 0, /* bitpos */
1082 complain_overflow_dont,/* complain_on_overflow */
1083 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1084 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1085 FALSE, /* partial_inplace */
1086 0xffffffff, /* src_mask */
1087 0xffffffff, /* dst_mask */
1088 TRUE), /* pcrel_offset */
1089
07d6d2b8 1090 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1091 0, /* rightshift */
1092 2, /* size (0 = byte, 1 = short, 2 = long) */
1093 32, /* bitsize */
1094 TRUE, /* pc_relative */
1095 0, /* bitpos */
1096 complain_overflow_dont,/* complain_on_overflow */
1097 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1098 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1099 FALSE, /* partial_inplace */
1100 0xffffffff, /* src_mask */
1101 0xffffffff, /* dst_mask */
1102 TRUE), /* pcrel_offset */
1103
07d6d2b8 1104 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1105 0, /* rightshift */
1106 2, /* size (0 = byte, 1 = short, 2 = long) */
1107 32, /* bitsize */
1108 TRUE, /* pc_relative */
1109 0, /* bitpos */
1110 complain_overflow_dont,/* complain_on_overflow */
1111 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1112 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1113 FALSE, /* partial_inplace */
1114 0xffffffff, /* src_mask */
1115 0xffffffff, /* dst_mask */
1116 TRUE), /* pcrel_offset */
1117
07d6d2b8 1118 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1119 0, /* rightshift */
1120 2, /* size (0 = byte, 1 = short, 2 = long) */
1121 32, /* bitsize */
1122 TRUE, /* pc_relative */
1123 0, /* bitpos */
1124 complain_overflow_dont,/* complain_on_overflow */
1125 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1126 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1127 FALSE, /* partial_inplace */
1128 0xffffffff, /* src_mask */
1129 0xffffffff, /* dst_mask */
1130 TRUE), /* pcrel_offset */
1131
07d6d2b8 1132 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1133 0, /* rightshift */
1134 2, /* size (0 = byte, 1 = short, 2 = long) */
1135 32, /* bitsize */
1136 TRUE, /* pc_relative */
1137 0, /* bitpos */
1138 complain_overflow_dont,/* complain_on_overflow */
1139 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1140 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1141 FALSE, /* partial_inplace */
1142 0xffffffff, /* src_mask */
1143 0xffffffff, /* dst_mask */
1144 TRUE), /* pcrel_offset */
1145
07d6d2b8 1146 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1147 0, /* rightshift */
1148 2, /* size (0 = byte, 1 = short, 2 = long) */
1149 32, /* bitsize */
1150 TRUE, /* pc_relative */
1151 0, /* bitpos */
1152 complain_overflow_dont,/* complain_on_overflow */
1153 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1154 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1155 FALSE, /* partial_inplace */
1156 0xffffffff, /* src_mask */
1157 0xffffffff, /* dst_mask */
1158 TRUE), /* pcrel_offset */
1159
07d6d2b8 1160 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1161 0, /* rightshift */
1162 2, /* size (0 = byte, 1 = short, 2 = long) */
1163 32, /* bitsize */
1164 TRUE, /* pc_relative */
1165 0, /* bitpos */
1166 complain_overflow_dont,/* complain_on_overflow */
1167 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1168 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1169 FALSE, /* partial_inplace */
1170 0xffffffff, /* src_mask */
1171 0xffffffff, /* dst_mask */
1172 TRUE), /* pcrel_offset */
1173
07d6d2b8 1174 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1175 0, /* rightshift */
1176 2, /* size (0 = byte, 1 = short, 2 = long) */
1177 32, /* bitsize */
1178 TRUE, /* pc_relative */
1179 0, /* bitpos */
1180 complain_overflow_dont,/* complain_on_overflow */
1181 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1182 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1183 FALSE, /* partial_inplace */
1184 0xffffffff, /* src_mask */
1185 0xffffffff, /* dst_mask */
1186 TRUE), /* pcrel_offset */
1187
07d6d2b8 1188 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1189 0, /* rightshift */
1190 2, /* size (0 = byte, 1 = short, 2 = long) */
1191 32, /* bitsize */
1192 TRUE, /* pc_relative */
1193 0, /* bitpos */
1194 complain_overflow_dont,/* complain_on_overflow */
1195 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1196 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1197 FALSE, /* partial_inplace */
1198 0xffffffff, /* src_mask */
1199 0xffffffff, /* dst_mask */
1200 TRUE), /* pcrel_offset */
1201
07d6d2b8 1202 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1203 0, /* rightshift */
1204 2, /* size (0 = byte, 1 = short, 2 = long) */
1205 32, /* bitsize */
1206 TRUE, /* pc_relative */
1207 0, /* bitpos */
1208 complain_overflow_dont,/* complain_on_overflow */
1209 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1210 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1211 FALSE, /* partial_inplace */
1212 0xffffffff, /* src_mask */
1213 0xffffffff, /* dst_mask */
1214 TRUE), /* pcrel_offset */
1215
07d6d2b8 1216 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1217 0, /* rightshift */
1218 2, /* size (0 = byte, 1 = short, 2 = long) */
1219 32, /* bitsize */
1220 TRUE, /* pc_relative */
1221 0, /* bitpos */
1222 complain_overflow_dont,/* complain_on_overflow */
1223 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1224 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1225 FALSE, /* partial_inplace */
1226 0xffffffff, /* src_mask */
1227 0xffffffff, /* dst_mask */
1228 TRUE), /* pcrel_offset */
1229
07d6d2b8 1230 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1231 0, /* rightshift */
1232 2, /* size (0 = byte, 1 = short, 2 = long) */
1233 32, /* bitsize */
1234 TRUE, /* pc_relative */
1235 0, /* bitpos */
1236 complain_overflow_dont,/* complain_on_overflow */
1237 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1238 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1239 FALSE, /* partial_inplace */
1240 0xffffffff, /* src_mask */
1241 0xffffffff, /* dst_mask */
1242 TRUE), /* pcrel_offset */
1243
07d6d2b8 1244 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1245 0, /* rightshift */
1246 2, /* size (0 = byte, 1 = short, 2 = long) */
1247 32, /* bitsize */
1248 TRUE, /* pc_relative */
1249 0, /* bitpos */
1250 complain_overflow_dont,/* complain_on_overflow */
1251 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1252 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1253 FALSE, /* partial_inplace */
1254 0xffffffff, /* src_mask */
1255 0xffffffff, /* dst_mask */
1256 TRUE), /* pcrel_offset */
1257
07d6d2b8 1258 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1259 0, /* rightshift */
1260 2, /* size (0 = byte, 1 = short, 2 = long) */
1261 32, /* bitsize */
1262 TRUE, /* pc_relative */
1263 0, /* bitpos */
1264 complain_overflow_dont,/* complain_on_overflow */
1265 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1266 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1267 FALSE, /* partial_inplace */
1268 0xffffffff, /* src_mask */
1269 0xffffffff, /* dst_mask */
1270 TRUE), /* pcrel_offset */
1271
1272 /* End of group relocations. */
c19d1205 1273
c19d1205
ZW		 1274 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1275 0, /* rightshift */
1276 2, /* size (0 = byte, 1 = short, 2 = long) */
1277 16, /* bitsize */
1278 FALSE, /* pc_relative */
1279 0, /* bitpos */
1280 complain_overflow_dont,/* complain_on_overflow */
1281 bfd_elf_generic_reloc, /* special_function */
1282 "R_ARM_MOVW_BREL_NC", /* name */
1283 FALSE, /* partial_inplace */
1284 0x0000ffff, /* src_mask */
1285 0x0000ffff, /* dst_mask */
1286 FALSE), /* pcrel_offset */
1287
1288 HOWTO (R_ARM_MOVT_BREL, /* type */
1289 0, /* rightshift */
1290 2, /* size (0 = byte, 1 = short, 2 = long) */
1291 16, /* bitsize */
1292 FALSE, /* pc_relative */
1293 0, /* bitpos */
1294 complain_overflow_bitfield,/* complain_on_overflow */
1295 bfd_elf_generic_reloc, /* special_function */
1296 "R_ARM_MOVT_BREL", /* name */
1297 FALSE, /* partial_inplace */
1298 0x0000ffff, /* src_mask */
1299 0x0000ffff, /* dst_mask */
1300 FALSE), /* pcrel_offset */
1301
1302 HOWTO (R_ARM_MOVW_BREL, /* type */
1303 0, /* rightshift */
1304 2, /* size (0 = byte, 1 = short, 2 = long) */
1305 16, /* bitsize */
1306 FALSE, /* pc_relative */
1307 0, /* bitpos */
1308 complain_overflow_dont,/* complain_on_overflow */
1309 bfd_elf_generic_reloc, /* special_function */
1310 "R_ARM_MOVW_BREL", /* name */
1311 FALSE, /* partial_inplace */
1312 0x0000ffff, /* src_mask */
1313 0x0000ffff, /* dst_mask */
1314 FALSE), /* pcrel_offset */
1315
1316 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1317 0, /* rightshift */
1318 2, /* size (0 = byte, 1 = short, 2 = long) */
1319 16, /* bitsize */
1320 FALSE, /* pc_relative */
1321 0, /* bitpos */
1322 complain_overflow_dont,/* complain_on_overflow */
1323 bfd_elf_generic_reloc, /* special_function */
1324 "R_ARM_THM_MOVW_BREL_NC",/* name */
1325 FALSE, /* partial_inplace */
1326 0x040f70ff, /* src_mask */
1327 0x040f70ff, /* dst_mask */
1328 FALSE), /* pcrel_offset */
1329
1330 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1331 0, /* rightshift */
1332 2, /* size (0 = byte, 1 = short, 2 = long) */
1333 16, /* bitsize */
1334 FALSE, /* pc_relative */
1335 0, /* bitpos */
1336 complain_overflow_bitfield,/* complain_on_overflow */
1337 bfd_elf_generic_reloc, /* special_function */
1338 "R_ARM_THM_MOVT_BREL", /* name */
1339 FALSE, /* partial_inplace */
1340 0x040f70ff, /* src_mask */
1341 0x040f70ff, /* dst_mask */
1342 FALSE), /* pcrel_offset */
1343
1344 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1345 0, /* rightshift */
1346 2, /* size (0 = byte, 1 = short, 2 = long) */
1347 16, /* bitsize */
1348 FALSE, /* pc_relative */
1349 0, /* bitpos */
1350 complain_overflow_dont,/* complain_on_overflow */
1351 bfd_elf_generic_reloc, /* special_function */
1352 "R_ARM_THM_MOVW_BREL", /* name */
1353 FALSE, /* partial_inplace */
1354 0x040f70ff, /* src_mask */
1355 0x040f70ff, /* dst_mask */
1356 FALSE), /* pcrel_offset */
1357
0855e32b
NS		 1358 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1359 0, /* rightshift */
1360 2, /* size (0 = byte, 1 = short, 2 = long) */
1361 32, /* bitsize */
1362 FALSE, /* pc_relative */
1363 0, /* bitpos */
1364 complain_overflow_bitfield,/* complain_on_overflow */
1365 NULL, /* special_function */
1366 "R_ARM_TLS_GOTDESC", /* name */
1367 TRUE, /* partial_inplace */
1368 0xffffffff, /* src_mask */
1369 0xffffffff, /* dst_mask */
1370 FALSE), /* pcrel_offset */
1371
1372 HOWTO (R_ARM_TLS_CALL, /* type */
1373 0, /* rightshift */
1374 2, /* size (0 = byte, 1 = short, 2 = long) */
1375 24, /* bitsize */
1376 FALSE, /* pc_relative */
1377 0, /* bitpos */
1378 complain_overflow_dont,/* complain_on_overflow */
1379 bfd_elf_generic_reloc, /* special_function */
1380 "R_ARM_TLS_CALL", /* name */
1381 FALSE, /* partial_inplace */
1382 0x00ffffff, /* src_mask */
1383 0x00ffffff, /* dst_mask */
1384 FALSE), /* pcrel_offset */
1385
1386 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1387 0, /* rightshift */
1388 2, /* size (0 = byte, 1 = short, 2 = long) */
1389 0, /* bitsize */
1390 FALSE, /* pc_relative */
1391 0, /* bitpos */
1392 complain_overflow_bitfield,/* complain_on_overflow */
1393 bfd_elf_generic_reloc, /* special_function */
1394 "R_ARM_TLS_DESCSEQ", /* name */
1395 FALSE, /* partial_inplace */
1396 0x00000000, /* src_mask */
1397 0x00000000, /* dst_mask */
1398 FALSE), /* pcrel_offset */
1399
1400 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1401 0, /* rightshift */
1402 2, /* size (0 = byte, 1 = short, 2 = long) */
1403 24, /* bitsize */
1404 FALSE, /* pc_relative */
1405 0, /* bitpos */
1406 complain_overflow_dont,/* complain_on_overflow */
1407 bfd_elf_generic_reloc, /* special_function */
1408 "R_ARM_THM_TLS_CALL", /* name */
1409 FALSE, /* partial_inplace */
1410 0x07ff07ff, /* src_mask */
1411 0x07ff07ff, /* dst_mask */
1412 FALSE), /* pcrel_offset */
c19d1205
ZW		 1413
1414 HOWTO (R_ARM_PLT32_ABS, /* type */
1415 0, /* rightshift */
1416 2, /* size (0 = byte, 1 = short, 2 = long) */
1417 32, /* bitsize */
1418 FALSE, /* pc_relative */
1419 0, /* bitpos */
1420 complain_overflow_dont,/* complain_on_overflow */
1421 bfd_elf_generic_reloc, /* special_function */
1422 "R_ARM_PLT32_ABS", /* name */
1423 FALSE, /* partial_inplace */
1424 0xffffffff, /* src_mask */
1425 0xffffffff, /* dst_mask */
1426 FALSE), /* pcrel_offset */
1427
1428 HOWTO (R_ARM_GOT_ABS, /* type */
1429 0, /* rightshift */
1430 2, /* size (0 = byte, 1 = short, 2 = long) */
1431 32, /* bitsize */
1432 FALSE, /* pc_relative */
1433 0, /* bitpos */
1434 complain_overflow_dont,/* complain_on_overflow */
1435 bfd_elf_generic_reloc, /* special_function */
1436 "R_ARM_GOT_ABS", /* name */
1437 FALSE, /* partial_inplace */
1438 0xffffffff, /* src_mask */
1439 0xffffffff, /* dst_mask */
1440 FALSE), /* pcrel_offset */
1441
1442 HOWTO (R_ARM_GOT_PREL, /* type */
1443 0, /* rightshift */
1444 2, /* size (0 = byte, 1 = short, 2 = long) */
1445 32, /* bitsize */
1446 TRUE, /* pc_relative */
1447 0, /* bitpos */
1448 complain_overflow_dont, /* complain_on_overflow */
1449 bfd_elf_generic_reloc, /* special_function */
1450 "R_ARM_GOT_PREL", /* name */
1451 FALSE, /* partial_inplace */
1452 0xffffffff, /* src_mask */
1453 0xffffffff, /* dst_mask */
1454 TRUE), /* pcrel_offset */
1455
1456 HOWTO (R_ARM_GOT_BREL12, /* type */
1457 0, /* rightshift */
1458 2, /* size (0 = byte, 1 = short, 2 = long) */
1459 12, /* bitsize */
1460 FALSE, /* pc_relative */
1461 0, /* bitpos */
1462 complain_overflow_bitfield,/* complain_on_overflow */
1463 bfd_elf_generic_reloc, /* special_function */
1464 "R_ARM_GOT_BREL12", /* name */
1465 FALSE, /* partial_inplace */
1466 0x00000fff, /* src_mask */
1467 0x00000fff, /* dst_mask */
1468 FALSE), /* pcrel_offset */
1469
1470 HOWTO (R_ARM_GOTOFF12, /* type */
1471 0, /* rightshift */
1472 2, /* size (0 = byte, 1 = short, 2 = long) */
1473 12, /* bitsize */
1474 FALSE, /* pc_relative */
1475 0, /* bitpos */
1476 complain_overflow_bitfield,/* complain_on_overflow */
1477 bfd_elf_generic_reloc, /* special_function */
1478 "R_ARM_GOTOFF12", /* name */
1479 FALSE, /* partial_inplace */
1480 0x00000fff, /* src_mask */
1481 0x00000fff, /* dst_mask */
1482 FALSE), /* pcrel_offset */
1483
07d6d2b8 1484 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1485
1486 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1487 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1488 0, /* rightshift */
1489 2, /* size (0 = byte, 1 = short, 2 = long) */
1490 0, /* bitsize */
1491 FALSE, /* pc_relative */
1492 0, /* bitpos */
99059e56 1493 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1494 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1495 "R_ARM_GNU_VTENTRY", /* name */
1496 FALSE, /* partial_inplace */
1497 0, /* src_mask */
1498 0, /* dst_mask */
1499 FALSE), /* pcrel_offset */
c19d1205
ZW		 1500
1501 /* GNU extension to record C++ vtable hierarchy */
1502 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1503 0, /* rightshift */
1504 2, /* size (0 = byte, 1 = short, 2 = long) */
1505 0, /* bitsize */
1506 FALSE, /* pc_relative */
1507 0, /* bitpos */
99059e56 1508 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1509 NULL, /* special_function */
99059e56 1510 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1511 FALSE, /* partial_inplace */
1512 0, /* src_mask */
1513 0, /* dst_mask */
1514 FALSE), /* pcrel_offset */
c19d1205
ZW		 1515
1516 HOWTO (R_ARM_THM_JUMP11, /* type */
1517 1, /* rightshift */
1518 1, /* size (0 = byte, 1 = short, 2 = long) */
1519 11, /* bitsize */
1520 TRUE, /* pc_relative */
1521 0, /* bitpos */
1522 complain_overflow_signed, /* complain_on_overflow */
1523 bfd_elf_generic_reloc, /* special_function */
1524 "R_ARM_THM_JUMP11", /* name */
1525 FALSE, /* partial_inplace */
1526 0x000007ff, /* src_mask */
1527 0x000007ff, /* dst_mask */
1528 TRUE), /* pcrel_offset */
1529
1530 HOWTO (R_ARM_THM_JUMP8, /* type */
1531 1, /* rightshift */
1532 1, /* size (0 = byte, 1 = short, 2 = long) */
1533 8, /* bitsize */
1534 TRUE, /* pc_relative */
1535 0, /* bitpos */
1536 complain_overflow_signed, /* complain_on_overflow */
1537 bfd_elf_generic_reloc, /* special_function */
1538 "R_ARM_THM_JUMP8", /* name */
1539 FALSE, /* partial_inplace */
1540 0x000000ff, /* src_mask */
1541 0x000000ff, /* dst_mask */
1542 TRUE), /* pcrel_offset */
ba93b8ac 1543
c19d1205
ZW		 1544 /* TLS relocations */
1545 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1546 0, /* rightshift */
1547 2, /* size (0 = byte, 1 = short, 2 = long) */
1548 32, /* bitsize */
1549 FALSE, /* pc_relative */
1550 0, /* bitpos */
99059e56
RM		 1551 complain_overflow_bitfield,/* complain_on_overflow */
1552 NULL, /* special_function */
1553 "R_ARM_TLS_GD32", /* name */
1554 TRUE, /* partial_inplace */
1555 0xffffffff, /* src_mask */
1556 0xffffffff, /* dst_mask */
07d6d2b8 1557 FALSE), /* pcrel_offset */
ba93b8ac 1558
ba93b8ac 1559 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1560 0, /* rightshift */
1561 2, /* size (0 = byte, 1 = short, 2 = long) */
1562 32, /* bitsize */
1563 FALSE, /* pc_relative */
1564 0, /* bitpos */
99059e56
RM		 1565 complain_overflow_bitfield,/* complain_on_overflow */
1566 bfd_elf_generic_reloc, /* special_function */
1567 "R_ARM_TLS_LDM32", /* name */
1568 TRUE, /* partial_inplace */
1569 0xffffffff, /* src_mask */
1570 0xffffffff, /* dst_mask */
07d6d2b8 1571 FALSE), /* pcrel_offset */
ba93b8ac 1572
c19d1205 1573 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1574 0, /* rightshift */
1575 2, /* size (0 = byte, 1 = short, 2 = long) */
1576 32, /* bitsize */
1577 FALSE, /* pc_relative */
1578 0, /* bitpos */
99059e56
RM		 1579 complain_overflow_bitfield,/* complain_on_overflow */
1580 bfd_elf_generic_reloc, /* special_function */
1581 "R_ARM_TLS_LDO32", /* name */
1582 TRUE, /* partial_inplace */
1583 0xffffffff, /* src_mask */
1584 0xffffffff, /* dst_mask */
07d6d2b8 1585 FALSE), /* pcrel_offset */
ba93b8ac 1586
ba93b8ac 1587 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1588 0, /* rightshift */
1589 2, /* size (0 = byte, 1 = short, 2 = long) */
1590 32, /* bitsize */
1591 FALSE, /* pc_relative */
1592 0, /* bitpos */
99059e56
RM		 1593 complain_overflow_bitfield,/* complain_on_overflow */
1594 NULL, /* special_function */
1595 "R_ARM_TLS_IE32", /* name */
1596 TRUE, /* partial_inplace */
1597 0xffffffff, /* src_mask */
1598 0xffffffff, /* dst_mask */
07d6d2b8 1599 FALSE), /* pcrel_offset */
7f266840 1600
c19d1205 1601 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1602 0, /* rightshift */
1603 2, /* size (0 = byte, 1 = short, 2 = long) */
1604 32, /* bitsize */
1605 FALSE, /* pc_relative */
1606 0, /* bitpos */
99059e56 1607 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1608 NULL, /* special_function */
99059e56
RM		 1609 "R_ARM_TLS_LE32", /* name */
1610 TRUE, /* partial_inplace */
1611 0xffffffff, /* src_mask */
1612 0xffffffff, /* dst_mask */
07d6d2b8 1613 FALSE), /* pcrel_offset */
7f266840 1614
c19d1205
ZW		 1615 HOWTO (R_ARM_TLS_LDO12, /* type */
1616 0, /* rightshift */
1617 2, /* size (0 = byte, 1 = short, 2 = long) */
1618 12, /* bitsize */
1619 FALSE, /* pc_relative */
7f266840 1620 0, /* bitpos */
c19d1205 1621 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1622 bfd_elf_generic_reloc, /* special_function */
c19d1205 1623 "R_ARM_TLS_LDO12", /* name */
7f266840 1624 FALSE, /* partial_inplace */
c19d1205
ZW		 1625 0x00000fff, /* src_mask */
1626 0x00000fff, /* dst_mask */
1627 FALSE), /* pcrel_offset */
7f266840 1628
c19d1205
ZW		 1629 HOWTO (R_ARM_TLS_LE12, /* type */
1630 0, /* rightshift */
1631 2, /* size (0 = byte, 1 = short, 2 = long) */
1632 12, /* bitsize */
1633 FALSE, /* pc_relative */
7f266840 1634 0, /* bitpos */
c19d1205 1635 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1636 bfd_elf_generic_reloc, /* special_function */
c19d1205 1637 "R_ARM_TLS_LE12", /* name */
7f266840 1638 FALSE, /* partial_inplace */
c19d1205
ZW		 1639 0x00000fff, /* src_mask */
1640 0x00000fff, /* dst_mask */
1641 FALSE), /* pcrel_offset */
7f266840 1642
c19d1205 1643 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1644 0, /* rightshift */
1645 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1646 12, /* bitsize */
1647 FALSE, /* pc_relative */
7f266840 1648 0, /* bitpos */
c19d1205 1649 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1650 bfd_elf_generic_reloc, /* special_function */
c19d1205 1651 "R_ARM_TLS_IE12GP", /* name */
7f266840 1652 FALSE, /* partial_inplace */
c19d1205
ZW		 1653 0x00000fff, /* src_mask */
1654 0x00000fff, /* dst_mask */
1655 FALSE), /* pcrel_offset */
0855e32b 1656
34e77a92 1657 /* 112-127 private relocations. */
0855e32b
NS		 1658 EMPTY_HOWTO (112),
1659 EMPTY_HOWTO (113),
1660 EMPTY_HOWTO (114),
1661 EMPTY_HOWTO (115),
1662 EMPTY_HOWTO (116),
1663 EMPTY_HOWTO (117),
1664 EMPTY_HOWTO (118),
1665 EMPTY_HOWTO (119),
1666 EMPTY_HOWTO (120),
1667 EMPTY_HOWTO (121),
1668 EMPTY_HOWTO (122),
1669 EMPTY_HOWTO (123),
1670 EMPTY_HOWTO (124),
1671 EMPTY_HOWTO (125),
1672 EMPTY_HOWTO (126),
1673 EMPTY_HOWTO (127),
34e77a92
RS		 1674
1675 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1676 EMPTY_HOWTO (128),
1677
1678 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1679 0, /* rightshift */
1680 1, /* size (0 = byte, 1 = short, 2 = long) */
1681 0, /* bitsize */
1682 FALSE, /* pc_relative */
1683 0, /* bitpos */
1684 complain_overflow_bitfield,/* complain_on_overflow */
1685 bfd_elf_generic_reloc, /* special_function */
1686 "R_ARM_THM_TLS_DESCSEQ",/* name */
1687 FALSE, /* partial_inplace */
1688 0x00000000, /* src_mask */
1689 0x00000000, /* dst_mask */
1690 FALSE), /* pcrel_offset */
72d98d16
MG		 1691 EMPTY_HOWTO (130),
1692 EMPTY_HOWTO (131),
1693 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1694 0, /* rightshift. */
1695 1, /* size (0 = byte, 1 = short, 2 = long). */
1696 16, /* bitsize. */
1697 FALSE, /* pc_relative. */
1698 0, /* bitpos. */
1699 complain_overflow_bitfield,/* complain_on_overflow. */
1700 bfd_elf_generic_reloc, /* special_function. */
1701 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1702 FALSE, /* partial_inplace. */
1703 0x00000000, /* src_mask. */
1704 0x00000000, /* dst_mask. */
1705 FALSE), /* pcrel_offset. */
1706 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1707 0, /* rightshift. */
1708 1, /* size (0 = byte, 1 = short, 2 = long). */
1709 16, /* bitsize. */
1710 FALSE, /* pc_relative. */
1711 0, /* bitpos. */
1712 complain_overflow_bitfield,/* complain_on_overflow. */
1713 bfd_elf_generic_reloc, /* special_function. */
1714 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1715 FALSE, /* partial_inplace. */
1716 0x00000000, /* src_mask. */
1717 0x00000000, /* dst_mask. */
1718 FALSE), /* pcrel_offset. */
1719 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1720 0, /* rightshift. */
1721 1, /* size (0 = byte, 1 = short, 2 = long). */
1722 16, /* bitsize. */
1723 FALSE, /* pc_relative. */
1724 0, /* bitpos. */
1725 complain_overflow_bitfield,/* complain_on_overflow. */
1726 bfd_elf_generic_reloc, /* special_function. */
1727 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1728 FALSE, /* partial_inplace. */
1729 0x00000000, /* src_mask. */
1730 0x00000000, /* dst_mask. */
1731 FALSE), /* pcrel_offset. */
1732 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1733 0, /* rightshift. */
1734 1, /* size (0 = byte, 1 = short, 2 = long). */
1735 16, /* bitsize. */
1736 FALSE, /* pc_relative. */
1737 0, /* bitpos. */
1738 complain_overflow_bitfield,/* complain_on_overflow. */
1739 bfd_elf_generic_reloc, /* special_function. */
1740 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1741 FALSE, /* partial_inplace. */
1742 0x00000000, /* src_mask. */
1743 0x00000000, /* dst_mask. */
1744 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1745};
1746
34e77a92 1747/* 160 onwards: */
5c5a4843 1748static reloc_howto_type elf32_arm_howto_table_2[8] =
34e77a92
RS		 1749{
1750 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1751 0, /* rightshift */
1752 2, /* size (0 = byte, 1 = short, 2 = long) */
1753 32, /* bitsize */
1754 FALSE, /* pc_relative */
1755 0, /* bitpos */
99059e56
RM		 1756 complain_overflow_bitfield,/* complain_on_overflow */
1757 bfd_elf_generic_reloc, /* special_function */
1758 "R_ARM_IRELATIVE", /* name */
1759 TRUE, /* partial_inplace */
1760 0xffffffff, /* src_mask */
1761 0xffffffff, /* dst_mask */
188fd7ae
CL		 1762 FALSE), /* pcrel_offset */
1763 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1764 0, /* rightshift */
1765 2, /* size (0 = byte, 1 = short, 2 = long) */
1766 32, /* bitsize */
1767 FALSE, /* pc_relative */
1768 0, /* bitpos */
1769 complain_overflow_bitfield,/* complain_on_overflow */
1770 bfd_elf_generic_reloc, /* special_function */
1771 "R_ARM_GOTFUNCDESC", /* name */
1772 FALSE, /* partial_inplace */
1773 0, /* src_mask */
1774 0xffffffff, /* dst_mask */
1775 FALSE), /* pcrel_offset */
1776 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1777 0, /* rightshift */
1778 2, /* size (0 = byte, 1 = short, 2 = long) */
1779 32, /* bitsize */
1780 FALSE, /* pc_relative */
1781 0, /* bitpos */
1782 complain_overflow_bitfield,/* complain_on_overflow */
1783 bfd_elf_generic_reloc, /* special_function */
1784 "R_ARM_GOTOFFFUNCDESC",/* name */
1785 FALSE, /* partial_inplace */
1786 0, /* src_mask */
1787 0xffffffff, /* dst_mask */
1788 FALSE), /* pcrel_offset */
1789 HOWTO (R_ARM_FUNCDESC, /* type */
1790 0, /* rightshift */
1791 2, /* size (0 = byte, 1 = short, 2 = long) */
1792 32, /* bitsize */
1793 FALSE, /* pc_relative */
1794 0, /* bitpos */
1795 complain_overflow_bitfield,/* complain_on_overflow */
1796 bfd_elf_generic_reloc, /* special_function */
1797 "R_ARM_FUNCDESC", /* name */
1798 FALSE, /* partial_inplace */
1799 0, /* src_mask */
1800 0xffffffff, /* dst_mask */
1801 FALSE), /* pcrel_offset */
1802 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1803 0, /* rightshift */
1804 2, /* size (0 = byte, 1 = short, 2 = long) */
1805 64, /* bitsize */
1806 FALSE, /* pc_relative */
1807 0, /* bitpos */
1808 complain_overflow_bitfield,/* complain_on_overflow */
1809 bfd_elf_generic_reloc, /* special_function */
1810 "R_ARM_FUNCDESC_VALUE",/* name */
1811 FALSE, /* partial_inplace */
1812 0, /* src_mask */
1813 0xffffffff, /* dst_mask */
1814 FALSE), /* pcrel_offset */
5c5a4843
CL		 1815 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1816 0, /* rightshift */
1817 2, /* size (0 = byte, 1 = short, 2 = long) */
1818 32, /* bitsize */
1819 FALSE, /* pc_relative */
1820 0, /* bitpos */
1821 complain_overflow_bitfield,/* complain_on_overflow */
1822 bfd_elf_generic_reloc, /* special_function */
1823 "R_ARM_TLS_GD32_FDPIC",/* name */
1824 FALSE, /* partial_inplace */
1825 0, /* src_mask */
1826 0xffffffff, /* dst_mask */
1827 FALSE), /* pcrel_offset */
1828 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1829 0, /* rightshift */
1830 2, /* size (0 = byte, 1 = short, 2 = long) */
1831 32, /* bitsize */
1832 FALSE, /* pc_relative */
1833 0, /* bitpos */
1834 complain_overflow_bitfield,/* complain_on_overflow */
1835 bfd_elf_generic_reloc, /* special_function */
1836 "R_ARM_TLS_LDM32_FDPIC",/* name */
1837 FALSE, /* partial_inplace */
1838 0, /* src_mask */
1839 0xffffffff, /* dst_mask */
1840 FALSE), /* pcrel_offset */
1841 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1842 0, /* rightshift */
1843 2, /* size (0 = byte, 1 = short, 2 = long) */
1844 32, /* bitsize */
1845 FALSE, /* pc_relative */
1846 0, /* bitpos */
1847 complain_overflow_bitfield,/* complain_on_overflow */
1848 bfd_elf_generic_reloc, /* special_function */
1849 "R_ARM_TLS_IE32_FDPIC",/* name */
1850 FALSE, /* partial_inplace */
1851 0, /* src_mask */
1852 0xffffffff, /* dst_mask */
1853 FALSE), /* pcrel_offset */
34e77a92 1854};
c19d1205 1855
34e77a92
RS		 1856/* 249-255 extended, currently unused, relocations: */
1857static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1858{
1859 HOWTO (R_ARM_RREL32, /* type */
1860 0, /* rightshift */
1861 0, /* size (0 = byte, 1 = short, 2 = long) */
1862 0, /* bitsize */
1863 FALSE, /* pc_relative */
1864 0, /* bitpos */
1865 complain_overflow_dont,/* complain_on_overflow */
1866 bfd_elf_generic_reloc, /* special_function */
1867 "R_ARM_RREL32", /* name */
1868 FALSE, /* partial_inplace */
1869 0, /* src_mask */
1870 0, /* dst_mask */
1871 FALSE), /* pcrel_offset */
1872
1873 HOWTO (R_ARM_RABS32, /* type */
1874 0, /* rightshift */
1875 0, /* size (0 = byte, 1 = short, 2 = long) */
1876 0, /* bitsize */
1877 FALSE, /* pc_relative */
1878 0, /* bitpos */
1879 complain_overflow_dont,/* complain_on_overflow */
1880 bfd_elf_generic_reloc, /* special_function */
1881 "R_ARM_RABS32", /* name */
1882 FALSE, /* partial_inplace */
1883 0, /* src_mask */
1884 0, /* dst_mask */
1885 FALSE), /* pcrel_offset */
1886
1887 HOWTO (R_ARM_RPC24, /* type */
1888 0, /* rightshift */
1889 0, /* size (0 = byte, 1 = short, 2 = long) */
1890 0, /* bitsize */
1891 FALSE, /* pc_relative */
1892 0, /* bitpos */
1893 complain_overflow_dont,/* complain_on_overflow */
1894 bfd_elf_generic_reloc, /* special_function */
1895 "R_ARM_RPC24", /* name */
1896 FALSE, /* partial_inplace */
1897 0, /* src_mask */
1898 0, /* dst_mask */
1899 FALSE), /* pcrel_offset */
1900
1901 HOWTO (R_ARM_RBASE, /* type */
1902 0, /* rightshift */
1903 0, /* size (0 = byte, 1 = short, 2 = long) */
1904 0, /* bitsize */
1905 FALSE, /* pc_relative */
1906 0, /* bitpos */
1907 complain_overflow_dont,/* complain_on_overflow */
1908 bfd_elf_generic_reloc, /* special_function */
1909 "R_ARM_RBASE", /* name */
1910 FALSE, /* partial_inplace */
1911 0, /* src_mask */
1912 0, /* dst_mask */
1913 FALSE) /* pcrel_offset */
1914};
1915
1916static reloc_howto_type *
1917elf32_arm_howto_from_type (unsigned int r_type)
1918{
906e58ca 1919 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1920 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1921
188fd7ae
CL		 1922 if (r_type >= R_ARM_IRELATIVE
1923 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1924 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1925
c19d1205 1926 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1927 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1928 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1929
c19d1205 1930 return NULL;
7f266840
DJ		 1931}
1932
f3185997
NC		 1933static bfd_boolean
1934elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1935 Elf_Internal_Rela * elf_reloc)
1936{
1937 unsigned int r_type;
1938
1939 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1940 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1941 {
1942 /* xgettext:c-format */
1943 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1944 abfd, r_type);
1945 bfd_set_error (bfd_error_bad_value);
1946 return FALSE;
1947 }
1948 return TRUE;
7f266840
DJ		 1949}
1950
1951struct elf32_arm_reloc_map
1952 {
1953 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1954 unsigned char elf_reloc_val;
7f266840
DJ		 1955 };
1956
1957/* All entries in this list must also be present in elf32_arm_howto_table. */
1958static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1959 {
07d6d2b8 1960 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 1961 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1962 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1963 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 1964 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1965 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1966 {BFD_RELOC_32, R_ARM_ABS32},
1967 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1968 {BFD_RELOC_8, R_ARM_ABS8},
1969 {BFD_RELOC_16, R_ARM_ABS16},
1970 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 1971 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1972 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1973 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1974 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1975 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1976 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1977 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 1978 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1979 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1980 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
1981 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
1982 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
1983 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
1984 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1985 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 1986 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1987 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1988 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1989 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 1990 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 1991 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1992 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1993 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 1994 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 1995 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 1996 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 1997 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1998 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1999 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2000 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2001 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2002 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 2003 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2004 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2005 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2006 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 2007 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2008 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2009 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2010 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
5c5a4843
CL		 2011 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2012 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2013 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
c19d1205
ZW		 2014 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2015 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 2016 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2017 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2018 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2019 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2020 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2021 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2022 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2023 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 2024 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2025 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2026 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2027 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2028 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2029 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2030 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2031 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2032 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2033 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2034 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2035 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2036 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2037 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2038 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2039 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2040 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2041 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2042 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2043 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2044 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2045 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2046 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2047 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2048 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2049 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2050 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2051 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2052 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2053 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2054 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2055 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
2056 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 2057 };
2058
2059static reloc_howto_type *
f1c71a59
ZW		 2060elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2061 bfd_reloc_code_real_type code)
7f266840
DJ		 2062{
2063 unsigned int i;
8029a119 2064
906e58ca 2065 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2066 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2067 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2068
c19d1205 2069 return NULL;
7f266840
DJ		 2070}
2071
157090f7
AM		 2072static reloc_howto_type *
2073elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2074 const char *r_name)
2075{
2076 unsigned int i;
2077
906e58ca 2078 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2079 if (elf32_arm_howto_table_1[i].name != NULL
2080 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2081 return &elf32_arm_howto_table_1[i];
2082
906e58ca 2083 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2084 if (elf32_arm_howto_table_2[i].name != NULL
2085 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2086 return &elf32_arm_howto_table_2[i];
2087
34e77a92
RS		 2088 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2089 if (elf32_arm_howto_table_3[i].name != NULL
2090 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2091 return &elf32_arm_howto_table_3[i];
2092
157090f7
AM		 2093 return NULL;
2094}
2095
906e58ca
NC		 2096/* Support for core dump NOTE sections. */
2097
7f266840 2098static bfd_boolean
f1c71a59 2099elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2100{
2101 int offset;
2102 size_t size;
2103
2104 switch (note->descsz)
2105 {
2106 default:
2107 return FALSE;
2108
8029a119 2109 case 148: /* Linux/ARM 32-bit. */
7f266840 2110 /* pr_cursig */
228e534f 2111 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2112
2113 /* pr_pid */
228e534f 2114 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2115
2116 /* pr_reg */
2117 offset = 72;
2118 size = 72;
2119
2120 break;
2121 }
2122
2123 /* Make a ".reg/999" section. */
2124 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2125 size, note->descpos + offset);
2126}
2127
2128static bfd_boolean
f1c71a59 2129elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2130{
2131 switch (note->descsz)
2132 {
2133 default:
2134 return FALSE;
2135
8029a119 2136 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2137 elf_tdata (abfd)->core->pid
4395ee08 2138 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2139 elf_tdata (abfd)->core->program
7f266840 2140 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2141 elf_tdata (abfd)->core->command
7f266840
DJ		 2142 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2143 }
2144
2145 /* Note that for some reason, a spurious space is tacked
2146 onto the end of the args in some (at least one anyway)
2147 implementations, so strip it off if it exists. */
7f266840 2148 {
228e534f 2149 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2150 int n = strlen (command);
2151
2152 if (0 < n && command[n - 1] == ' ')
2153 command[n - 1] = '\0';
2154 }
2155
2156 return TRUE;
2157}
2158
1f20dca5
UW		 2159static char *
2160elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2161 int note_type, ...)
2162{
2163 switch (note_type)
2164 {
2165 default:
2166 return NULL;
2167
2168 case NT_PRPSINFO:
2169 {
602f1657 2170 char data[124] ATTRIBUTE_NONSTRING;
1f20dca5
UW		 2171 va_list ap;
2172
2173 va_start (ap, note_type);
2174 memset (data, 0, sizeof (data));
2175 strncpy (data + 28, va_arg (ap, const char *), 16);
be3e27bb 2176#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2177 DIAGNOSTIC_PUSH;
be3e27bb 2178 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
95da9854
L		 2179 -Wstringop-truncation:
2180 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2181 */
95da9854
L		 2182 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2183#endif
1f20dca5 2184 strncpy (data + 44, va_arg (ap, const char *), 80);
be3e27bb 2185#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2186 DIAGNOSTIC_POP;
fe75810f 2187#endif
1f20dca5
UW		 2188 va_end (ap);
2189
2190 return elfcore_write_note (abfd, buf, bufsiz,
2191 "CORE", note_type, data, sizeof (data));
2192 }
2193
2194 case NT_PRSTATUS:
2195 {
2196 char data[148];
2197 va_list ap;
2198 long pid;
2199 int cursig;
2200 const void *greg;
2201
2202 va_start (ap, note_type);
2203 memset (data, 0, sizeof (data));
2204 pid = va_arg (ap, long);
2205 bfd_put_32 (abfd, pid, data + 24);
2206 cursig = va_arg (ap, int);
2207 bfd_put_16 (abfd, cursig, data + 12);
2208 greg = va_arg (ap, const void *);
2209 memcpy (data + 72, greg, 72);
2210 va_end (ap);
2211
2212 return elfcore_write_note (abfd, buf, bufsiz,
2213 "CORE", note_type, data, sizeof (data));
2214 }
2215 }
2216}
2217
07d6d2b8
AM		 2218#define TARGET_LITTLE_SYM arm_elf32_le_vec
2219#define TARGET_LITTLE_NAME "elf32-littlearm"
2220#define TARGET_BIG_SYM arm_elf32_be_vec
2221#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2222
2223#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2224#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2225#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2226
252b5132
RH		 2227typedef unsigned long int insn32;
2228typedef unsigned short int insn16;
2229
3a4a14e9
PB		 2230/* In lieu of proper flags, assume all EABIv4 or later objects are
2231 interworkable. */
57e8b36a 2232#define INTERWORK_FLAG(abfd) \
3a4a14e9 2233 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2234 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2235 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2236
252b5132
RH		 2237/* The linker script knows the section names for placement.
2238 The entry_names are used to do simple name mangling on the stubs.
2239 Given a function name, and its type, the stub can be found. The
9b485d32 2240 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2241#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2242#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2243
2244#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2245#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2246
c7b8f16e
JB		 2247#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2248#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2249
a504d23a
LA		 2250#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2251#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2252
845b51d6
PB		 2253#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2254#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2255
7413f23f
DJ		 2256#define STUB_ENTRY_NAME "__%s_veneer"
2257
4ba2ef8f
TP		 2258#define CMSE_PREFIX "__acle_se_"
2259
252b5132
RH		 2260/* The name of the dynamic interpreter. This is put in the .interp
2261 section. */
2262#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2263
cb10292c
CL		 2264/* FDPIC default stack size. */
2265#define DEFAULT_STACK_SIZE 0x8000
2266
0855e32b 2267static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2268{
2269 0xe08e0000, /* add r0, lr, r0 */
2270 0xe5901004, /* ldr r1, [r0,#4] */
2271 0xe12fff11, /* bx r1 */
2272};
0855e32b
NS		 2273
2274static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2275{
2276 0xe52d2004, /* push {r2} */
2277 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2278 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2279 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2280 0xe081100f, /* 2: add r1, pc */
2281 0xe12fff12, /* bx r2 */
2282 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2283 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2284 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2285};
0855e32b 2286
7801f98f
CL		 2287/* ARM FDPIC PLT entry. */
2288/* The last 5 words contain PLT lazy fragment code and data. */
2289static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2290 {
2291 0xe59fc008, /* ldr r12, .L1 */
2292 0xe08cc009, /* add r12, r12, r9 */
2293 0xe59c9004, /* ldr r9, [r12, #4] */
2294 0xe59cf000, /* ldr pc, [r12] */
2295 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2296 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2297 0xe51fc00c, /* ldr r12, [pc, #-12] */
2298 0xe92d1000, /* push {r12} */
2299 0xe599c004, /* ldr r12, [r9, #4] */
2300 0xe599f000, /* ldr pc, [r9] */
2301 };
2302
59029f57
CL		 2303/* Thumb FDPIC PLT entry. */
2304/* The last 5 words contain PLT lazy fragment code and data. */
2305static const bfd_vma elf32_arm_fdpic_thumb_plt_entry [] =
2306 {
2307 0xc00cf8df, /* ldr.w r12, .L1 */
2308 0x0c09eb0c, /* add.w r12, r12, r9 */
2309 0x9004f8dc, /* ldr.w r9, [r12, #4] */
2310 0xf000f8dc, /* ldr.w pc, [r12] */
2311 0x00000000, /* .L1 .word foo(GOTOFFFUNCDESC) */
2312 0x00000000, /* .L2 .word foo(funcdesc_value_reloc_offset) */
2313 0xc008f85f, /* ldr.w r12, .L2 */
2314 0xcd04f84d, /* push {r12} */
2315 0xc004f8d9, /* ldr.w r12, [r9, #4] */
2316 0xf000f8d9, /* ldr.w pc, [r9] */
2317 };
2318
5e681ec4
PB		 2319#ifdef FOUR_WORD_PLT
2320
252b5132
RH		 2321/* The first entry in a procedure linkage table looks like
2322 this. It is set up so that any shared library function that is
59f2c4e7 2323 called before the relocation has been set up calls the dynamic
9b485d32 2324 linker first. */
e5a52504 2325static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2326{
2327 0xe52de004, /* str lr, [sp, #-4]! */
2328 0xe59fe010, /* ldr lr, [pc, #16] */
2329 0xe08fe00e, /* add lr, pc, lr */
2330 0xe5bef008, /* ldr pc, [lr, #8]! */
2331};
5e681ec4
PB		 2332
2333/* Subsequent entries in a procedure linkage table look like
2334 this. */
e5a52504 2335static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2336{
2337 0xe28fc600, /* add ip, pc, #NN */
2338 0xe28cca00, /* add ip, ip, #NN */
2339 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2340 0x00000000, /* unused */
2341};
5e681ec4 2342
eed94f8f 2343#else /* not FOUR_WORD_PLT */
5e681ec4 2344
5e681ec4
PB		 2345/* The first entry in a procedure linkage table looks like
2346 this. It is set up so that any shared library function that is
2347 called before the relocation has been set up calls the dynamic
2348 linker first. */
e5a52504 2349static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2350{
07d6d2b8
AM		 2351 0xe52de004, /* str lr, [sp, #-4]! */
2352 0xe59fe004, /* ldr lr, [pc, #4] */
2353 0xe08fe00e, /* add lr, pc, lr */
2354 0xe5bef008, /* ldr pc, [lr, #8]! */
2355 0x00000000, /* &GOT[0] - . */
b38cadfb 2356};
252b5132 2357
1db37fe6
YG		 2358/* By default subsequent entries in a procedure linkage table look like
2359 this. Offsets that don't fit into 28 bits will cause link error. */
2360static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2361{
2362 0xe28fc600, /* add ip, pc, #0xNN00000 */
2363 0xe28cca00, /* add ip, ip, #0xNN000 */
2364 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2365};
5e681ec4 2366
1db37fe6
YG		 2367/* When explicitly asked, we'll use this "long" entry format
2368 which can cope with arbitrary displacements. */
2369static const bfd_vma elf32_arm_plt_entry_long [] =
2370{
07d6d2b8
AM		 2371 0xe28fc200, /* add ip, pc, #0xN0000000 */
2372 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2373 0xe28cca00, /* add ip, ip, #0xNN000 */
2374 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2375};
2376
2377static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2378
eed94f8f
NC		 2379#endif /* not FOUR_WORD_PLT */
2380
2381/* The first entry in a procedure linkage table looks like this.
2382 It is set up so that any shared library function that is called before the
2383 relocation has been set up calls the dynamic linker first. */
2384static const bfd_vma elf32_thumb2_plt0_entry [] =
2385{
2386 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2387 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2388 0xf8dfb500, /* push {lr} */
2389 0x44fee008, /* ldr.w lr, [pc, #8] */
2390 /* add lr, pc */
eed94f8f 2391 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2392 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2393};
2394
2395/* Subsequent entries in a procedure linkage table for thumb only target
2396 look like this. */
2397static const bfd_vma elf32_thumb2_plt_entry [] =
2398{
2399 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2400 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2401 0x0c00f240, /* movw ip, #0xNNNN */
2402 0x0c00f2c0, /* movt ip, #0xNNNN */
2403 0xf8dc44fc, /* add ip, pc */
2404 0xbf00f000 /* ldr.w pc, [ip] */
2405 /* nop */
eed94f8f 2406};
252b5132 2407
00a97672
RS		 2408/* The format of the first entry in the procedure linkage table
2409 for a VxWorks executable. */
2410static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2411{
07d6d2b8
AM		 2412 0xe52dc008, /* str ip,[sp,#-8]! */
2413 0xe59fc000, /* ldr ip,[pc] */
2414 0xe59cf008, /* ldr pc,[ip,#8] */
2415 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2416};
00a97672
RS		 2417
2418/* The format of subsequent entries in a VxWorks executable. */
2419static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2420{
07d6d2b8
AM		 2421 0xe59fc000, /* ldr ip,[pc] */
2422 0xe59cf000, /* ldr pc,[ip] */
2423 0x00000000, /* .long @got */
2424 0xe59fc000, /* ldr ip,[pc] */
2425 0xea000000, /* b _PLT */
2426 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2427};
00a97672
RS		 2428
2429/* The format of entries in a VxWorks shared library. */
2430static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2431{
07d6d2b8
AM		 2432 0xe59fc000, /* ldr ip,[pc] */
2433 0xe79cf009, /* ldr pc,[ip,r9] */
2434 0x00000000, /* .long @got */
2435 0xe59fc000, /* ldr ip,[pc] */
2436 0xe599f008, /* ldr pc,[r9,#8] */
2437 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2438};
00a97672 2439
b7693d02
DJ		 2440/* An initial stub used if the PLT entry is referenced from Thumb code. */
2441#define PLT_THUMB_STUB_SIZE 4
2442static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2443{
2444 0x4778, /* bx pc */
2445 0x46c0 /* nop */
2446};
b7693d02 2447
e5a52504
MM		 2448/* The entries in a PLT when using a DLL-based target with multiple
2449 address spaces. */
906e58ca 2450static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2451{
07d6d2b8
AM		 2452 0xe51ff004, /* ldr pc, [pc, #-4] */
2453 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2454};
2455
2456/* The first entry in a procedure linkage table looks like
2457 this. It is set up so that any shared library function that is
2458 called before the relocation has been set up calls the dynamic
2459 linker first. */
2460static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2461{
2462 /* First bundle: */
2463 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2464 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2465 0xe08cc00f, /* add ip, ip, pc */
2466 0xe52dc008, /* str ip, [sp, #-8]! */
2467 /* Second bundle: */
edccdf7c
RM		 2468 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2469 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2470 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2471 0xe12fff1c, /* bx ip */
b38cadfb 2472 /* Third bundle: */
edccdf7c
RM		 2473 0xe320f000, /* nop */
2474 0xe320f000, /* nop */
2475 0xe320f000, /* nop */
b38cadfb
NC		 2476 /* .Lplt_tail: */
2477 0xe50dc004, /* str ip, [sp, #-4] */
2478 /* Fourth bundle: */
edccdf7c
RM		 2479 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2480 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2481 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2482 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2483};
2484#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2485
2486/* Subsequent entries in a procedure linkage table look like this. */
2487static const bfd_vma elf32_arm_nacl_plt_entry [] =
2488{
2489 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2490 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2491 0xe08cc00f, /* add ip, ip, pc */
2492 0xea000000, /* b .Lplt_tail */
2493};
e5a52504 2494
906e58ca
NC		 2495#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2496#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2497#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2498#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2499#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2500#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2501#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2502#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2503
461a49ca 2504enum stub_insn_type
b38cadfb
NC		 2505{
2506 THUMB16_TYPE = 1,
2507 THUMB32_TYPE,
2508 ARM_TYPE,
2509 DATA_TYPE
2510};
461a49ca 2511
48229727
JB		 2512#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2513/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2514 is inserted in arm_build_one_stub(). */
2515#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2516#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2517#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2518#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2519#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2520#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2521#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2522#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2523
2524typedef struct
2525{
07d6d2b8 2526 bfd_vma data;
b38cadfb 2527 enum stub_insn_type type;
07d6d2b8
AM		 2528 unsigned int r_type;
2529 int reloc_addend;
461a49ca
DJ		 2530} insn_sequence;
2531
fea2b4d6
CL		 2532/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2533 to reach the stub if necessary. */
461a49ca 2534static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2535{
07d6d2b8 2536 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2537 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2538};
906e58ca 2539
fea2b4d6
CL		 2540/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2541 available. */
461a49ca 2542static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2543{
07d6d2b8
AM		 2544 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2545 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2546 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2547};
906e58ca 2548
d3626fb0 2549/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2550static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2551{
07d6d2b8
AM		 2552 THUMB16_INSN (0xb401), /* push {r0} */
2553 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2554 THUMB16_INSN (0x4684), /* mov ip, r0 */
2555 THUMB16_INSN (0xbc01), /* pop {r0} */
2556 THUMB16_INSN (0x4760), /* bx ip */
2557 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2558 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2559};
906e58ca 2560
80c135e5
TP		 2561/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2562static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2563{
07d6d2b8 2564 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2565 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2566};
2567
d5a67c02
AV		 2568/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2569 M-profile architectures. */
2570static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2571{
2572 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2573 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2574 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2575};
2576
d3626fb0
CL		 2577/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2578 allowed. */
2579static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2580{
07d6d2b8
AM		 2581 THUMB16_INSN (0x4778), /* bx pc */
2582 THUMB16_INSN (0x46c0), /* nop */
2583 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2584 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2585 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2586};
d3626fb0 2587
fea2b4d6
CL		 2588/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2589 available. */
461a49ca 2590static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2591{
07d6d2b8
AM		 2592 THUMB16_INSN (0x4778), /* bx pc */
2593 THUMB16_INSN (0x46c0), /* nop */
2594 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2595 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2596};
906e58ca 2597
fea2b4d6
CL		 2598/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2599 one, when the destination is close enough. */
461a49ca 2600static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2601{
07d6d2b8
AM		 2602 THUMB16_INSN (0x4778), /* bx pc */
2603 THUMB16_INSN (0x46c0), /* nop */
b38cadfb
NC		 2604 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2605};
c820be07 2606
cf3eccff 2607/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2608 blx to reach the stub if necessary. */
cf3eccff 2609static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2610{
07d6d2b8
AM		 2611 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2612 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2613 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2614};
906e58ca 2615
cf3eccff
DJ		 2616/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2617 blx to reach the stub if necessary. We can not add into pc;
2618 it is not guaranteed to mode switch (different in ARMv6 and
2619 ARMv7). */
2620static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2621{
07d6d2b8
AM		 2622 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2623 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2624 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2625 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2626};
cf3eccff 2627
ebe24dd4
CL		 2628/* V4T ARM -> ARM long branch stub, PIC. */
2629static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2630{
07d6d2b8
AM		 2631 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2632 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2633 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2634 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2635};
ebe24dd4
CL		 2636
2637/* V4T Thumb -> ARM long branch stub, PIC. */
2638static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2639{
07d6d2b8
AM		 2640 THUMB16_INSN (0x4778), /* bx pc */
2641 THUMB16_INSN (0x46c0), /* nop */
2642 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2643 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2644 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2645};
ebe24dd4 2646
d3626fb0
CL		 2647/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2648 architectures. */
ebe24dd4 2649static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2650{
07d6d2b8
AM		 2651 THUMB16_INSN (0xb401), /* push {r0} */
2652 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2653 THUMB16_INSN (0x46fc), /* mov ip, pc */
2654 THUMB16_INSN (0x4484), /* add ip, r0 */
2655 THUMB16_INSN (0xbc01), /* pop {r0} */
2656 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2657 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2658};
ebe24dd4 2659
d3626fb0
CL		 2660/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2661 allowed. */
2662static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2663{
07d6d2b8
AM		 2664 THUMB16_INSN (0x4778), /* bx pc */
2665 THUMB16_INSN (0x46c0), /* nop */
2666 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2667 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2668 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2669 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2670};
d3626fb0 2671
0855e32b
NS		 2672/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2673 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2674static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2675{
07d6d2b8
AM		 2676 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2677 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2678 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2679};
2680
2681/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2682 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2683static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2684{
07d6d2b8
AM		 2685 THUMB16_INSN (0x4778), /* bx pc */
2686 THUMB16_INSN (0x46c0), /* nop */
2687 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2688 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2689 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2690};
2691
7a89b94e
NC		 2692/* NaCl ARM -> ARM long branch stub. */
2693static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2694{
2695 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2696 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2697 ARM_INSN (0xe12fff1c), /* bx ip */
2698 ARM_INSN (0xe320f000), /* nop */
2699 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2700 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2701 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2702 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2703};
2704
2705/* NaCl ARM -> ARM long branch stub, PIC. */
2706static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2707{
2708 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2709 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2710 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2711 ARM_INSN (0xe12fff1c), /* bx ip */
2712 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2713 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2714 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2715 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2716};
2717
4ba2ef8f
TP		 2718/* Stub used for transition to secure state (aka SG veneer). */
2719static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2720{
2721 THUMB32_INSN (0xe97fe97f), /* sg. */
2722 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2723};
2724
7a89b94e 2725
48229727
JB		 2726/* Cortex-A8 erratum-workaround stubs. */
2727
2728/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2729 can't use a conditional branch to reach this stub). */
2730
2731static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2732{
07d6d2b8 2733 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2734 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2735 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2736};
48229727
JB		 2737
2738/* Stub used for b.w and bl.w instructions. */
2739
2740static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2741{
2742 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2743};
48229727
JB		 2744
2745static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2746{
2747 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2748};
48229727
JB		 2749
2750/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2751 instruction (which switches to ARM mode) to point to this stub. Jump to the
2752 real destination using an ARM-mode branch. */
2753
2754static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2755{
2756 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2757};
48229727 2758
9553db3c
NC		 2759/* For each section group there can be a specially created linker section
2760 to hold the stubs for that group. The name of the stub section is based
2761 upon the name of another section within that group with the suffix below
2762 applied.
2763
2764 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2765 create what appeared to be a linker stub section when it actually
2766 contained user code/data. For example, consider this fragment:
b38cadfb 2767
9553db3c
NC		 2768 const char * stubborn_problems[] = { "np" };
2769
2770 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2771 section called:
2772
2773 .data.rel.local.stubborn_problems
2774
2775 This then causes problems in arm32_arm_build_stubs() as it triggers:
2776
2777 // Ignore non-stub sections.
2778 if (!strstr (stub_sec->name, STUB_SUFFIX))
2779 continue;
2780
2781 And so the section would be ignored instead of being processed. Hence
2782 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2783 C identifier. */
2784#define STUB_SUFFIX ".__stub"
906e58ca 2785
738a79f6
CL		 2786/* One entry per long/short branch stub defined above. */
2787#define DEF_STUBS \
2788 DEF_STUB(long_branch_any_any) \
2789 DEF_STUB(long_branch_v4t_arm_thumb) \
2790 DEF_STUB(long_branch_thumb_only) \
2791 DEF_STUB(long_branch_v4t_thumb_thumb) \
2792 DEF_STUB(long_branch_v4t_thumb_arm) \
2793 DEF_STUB(short_branch_v4t_thumb_arm) \
2794 DEF_STUB(long_branch_any_arm_pic) \
2795 DEF_STUB(long_branch_any_thumb_pic) \
2796 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2797 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2798 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2799 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2800 DEF_STUB(long_branch_any_tls_pic) \
2801 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2802 DEF_STUB(long_branch_arm_nacl) \
2803 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2804 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2805 DEF_STUB(a8_veneer_b_cond) \
2806 DEF_STUB(a8_veneer_b) \
2807 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2808 DEF_STUB(a8_veneer_blx) \
2809 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2810 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2811
2812#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2813enum elf32_arm_stub_type
2814{
906e58ca 2815 arm_stub_none,
738a79f6 2816 DEF_STUBS
4f4faa4d 2817 max_stub_type
738a79f6
CL		 2818};
2819#undef DEF_STUB
2820
8d9d9490
TP		 2821/* Note the first a8_veneer type. */
2822const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2823
738a79f6
CL		 2824typedef struct
2825{
d3ce72d0 2826 const insn_sequence* template_sequence;
738a79f6
CL		 2827 int template_size;
2828} stub_def;
2829
2830#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2831static const stub_def stub_definitions[] =
2832{
738a79f6
CL		 2833 {NULL, 0},
2834 DEF_STUBS
906e58ca
NC		 2835};
2836
2837struct elf32_arm_stub_hash_entry
2838{
2839 /* Base hash table entry structure. */
2840 struct bfd_hash_entry root;
2841
2842 /* The stub section. */
2843 asection *stub_sec;
2844
2845 /* Offset within stub_sec of the beginning of this stub. */
2846 bfd_vma stub_offset;
2847
2848 /* Given the symbol's value and its section we can determine its final
2849 value when building the stubs (so the stub knows where to jump). */
2850 bfd_vma target_value;
2851 asection *target_section;
2852
8d9d9490
TP		 2853 /* Same as above but for the source of the branch to the stub. Used for
2854 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2855 such, source section does not need to be recorded since Cortex-A8 erratum
2856 workaround stubs are only generated when both source and target are in the
2857 same section. */
2858 bfd_vma source_value;
48229727
JB		 2859
2860 /* The instruction which caused this stub to be generated (only valid for
2861 Cortex-A8 erratum workaround stubs at present). */
2862 unsigned long orig_insn;
2863
461a49ca 2864 /* The stub type. */
906e58ca 2865 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2866 /* Its encoding size in bytes. */
2867 int stub_size;
2868 /* Its template. */
2869 const insn_sequence *stub_template;
2870 /* The size of the template (number of entries). */
2871 int stub_template_size;
906e58ca
NC		 2872
2873 /* The symbol table entry, if any, that this was derived from. */
2874 struct elf32_arm_link_hash_entry *h;
2875
35fc36a8
RS		 2876 /* Type of branch. */
2877 enum arm_st_branch_type branch_type;
906e58ca
NC		 2878
2879 /* Where this stub is being called from, or, in the case of combined
2880 stub sections, the first input section in the group. */
2881 asection *id_sec;
7413f23f
DJ		 2882
2883 /* The name for the local symbol at the start of this stub. The
2884 stub name in the hash table has to be unique; this does not, so
2885 it can be friendlier. */
2886 char *output_name;
906e58ca
NC		 2887};
2888
e489d0ae
PB		 2889/* Used to build a map of a section. This is required for mixed-endian
2890 code/data. */
2891
2892typedef struct elf32_elf_section_map
2893{
2894 bfd_vma vma;
2895 char type;
2896}
2897elf32_arm_section_map;
2898
c7b8f16e
JB		 2899/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2900
2901typedef enum
2902{
2903 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2904 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2905 VFP11_ERRATUM_ARM_VENEER,
2906 VFP11_ERRATUM_THUMB_VENEER
2907}
2908elf32_vfp11_erratum_type;
2909
2910typedef struct elf32_vfp11_erratum_list
2911{
2912 struct elf32_vfp11_erratum_list *next;
2913 bfd_vma vma;
2914 union
2915 {
2916 struct
2917 {
2918 struct elf32_vfp11_erratum_list *veneer;
2919 unsigned int vfp_insn;
2920 } b;
2921 struct
2922 {
2923 struct elf32_vfp11_erratum_list *branch;
2924 unsigned int id;
2925 } v;
2926 } u;
2927 elf32_vfp11_erratum_type type;
2928}
2929elf32_vfp11_erratum_list;
2930
a504d23a
LA		 2931/* Information about a STM32L4XX erratum veneer, or a branch to such a
2932 veneer. */
2933typedef enum
2934{
2935 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2936 STM32L4XX_ERRATUM_VENEER
2937}
2938elf32_stm32l4xx_erratum_type;
2939
2940typedef struct elf32_stm32l4xx_erratum_list
2941{
2942 struct elf32_stm32l4xx_erratum_list *next;
2943 bfd_vma vma;
2944 union
2945 {
2946 struct
2947 {
2948 struct elf32_stm32l4xx_erratum_list *veneer;
2949 unsigned int insn;
2950 } b;
2951 struct
2952 {
2953 struct elf32_stm32l4xx_erratum_list *branch;
2954 unsigned int id;
2955 } v;
2956 } u;
2957 elf32_stm32l4xx_erratum_type type;
2958}
2959elf32_stm32l4xx_erratum_list;
2960
2468f9c9
PB		 2961typedef enum
2962{
2963 DELETE_EXIDX_ENTRY,
2964 INSERT_EXIDX_CANTUNWIND_AT_END
2965}
2966arm_unwind_edit_type;
2967
2968/* A (sorted) list of edits to apply to an unwind table. */
2969typedef struct arm_unwind_table_edit
2970{
2971 arm_unwind_edit_type type;
2972 /* Note: we sometimes want to insert an unwind entry corresponding to a
2973 section different from the one we're currently writing out, so record the
2974 (text) section this edit relates to here. */
2975 asection *linked_section;
2976 unsigned int index;
2977 struct arm_unwind_table_edit *next;
2978}
2979arm_unwind_table_edit;
2980
8e3de13a 2981typedef struct _arm_elf_section_data
e489d0ae 2982{
2468f9c9 2983 /* Information about mapping symbols. */
e489d0ae 2984 struct bfd_elf_section_data elf;
8e3de13a 2985 unsigned int mapcount;
c7b8f16e 2986 unsigned int mapsize;
e489d0ae 2987 elf32_arm_section_map *map;
2468f9c9 2988 /* Information about CPU errata. */
c7b8f16e
JB		 2989 unsigned int erratumcount;
2990 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2991 unsigned int stm32l4xx_erratumcount;
2992 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2993 unsigned int additional_reloc_count;
2468f9c9
PB		 2994 /* Information about unwind tables. */
2995 union
2996 {
2997 /* Unwind info attached to a text section. */
2998 struct
2999 {
3000 asection *arm_exidx_sec;
3001 } text;
3002
3003 /* Unwind info attached to an .ARM.exidx section. */
3004 struct
3005 {
3006 arm_unwind_table_edit *unwind_edit_list;
3007 arm_unwind_table_edit *unwind_edit_tail;
3008 } exidx;
3009 } u;
8e3de13a
NC		 3010}
3011_arm_elf_section_data;
e489d0ae
PB		 3012
3013#define elf32_arm_section_data(sec) \
8e3de13a 3014 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 3015
48229727
JB		 3016/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3017 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3018 so may be created multiple times: we use an array of these entries whilst
3019 relaxing which we can refresh easily, then create stubs for each potentially
3020 erratum-triggering instruction once we've settled on a solution. */
3021
b38cadfb
NC		 3022struct a8_erratum_fix
3023{
48229727
JB		 3024 bfd *input_bfd;
3025 asection *section;
3026 bfd_vma offset;
8d9d9490 3027 bfd_vma target_offset;
48229727
JB		 3028 unsigned long orig_insn;
3029 char *stub_name;
3030 enum elf32_arm_stub_type stub_type;
35fc36a8 3031 enum arm_st_branch_type branch_type;
48229727
JB		 3032};
3033
3034/* A table of relocs applied to branches which might trigger Cortex-A8
3035 erratum. */
3036
b38cadfb
NC		 3037struct a8_erratum_reloc
3038{
48229727
JB		 3039 bfd_vma from;
3040 bfd_vma destination;
92750f34
DJ		 3041 struct elf32_arm_link_hash_entry *hash;
3042 const char *sym_name;
48229727 3043 unsigned int r_type;
35fc36a8 3044 enum arm_st_branch_type branch_type;
48229727
JB		 3045 bfd_boolean non_a8_stub;
3046};
3047
ba93b8ac
DJ		 3048/* The size of the thread control block. */
3049#define TCB_SIZE 8
3050
34e77a92
RS		 3051/* ARM-specific information about a PLT entry, over and above the usual
3052 gotplt_union. */
b38cadfb
NC		 3053struct arm_plt_info
3054{
34e77a92
RS		 3055 /* We reference count Thumb references to a PLT entry separately,
3056 so that we can emit the Thumb trampoline only if needed. */
3057 bfd_signed_vma thumb_refcount;
3058
3059 /* Some references from Thumb code may be eliminated by BL->BLX
3060 conversion, so record them separately. */
3061 bfd_signed_vma maybe_thumb_refcount;
3062
3063 /* How many of the recorded PLT accesses were from non-call relocations.
3064 This information is useful when deciding whether anything takes the
3065 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3066 non-call references to the function should resolve directly to the
3067 real runtime target. */
3068 unsigned int noncall_refcount;
3069
3070 /* Since PLT entries have variable size if the Thumb prologue is
3071 used, we need to record the index into .got.plt instead of
3072 recomputing it from the PLT offset. */
3073 bfd_signed_vma got_offset;
3074};
3075
3076/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 3077struct arm_local_iplt_info
3078{
34e77a92
RS		 3079 /* The information that is usually found in the generic ELF part of
3080 the hash table entry. */
3081 union gotplt_union root;
3082
3083 /* The information that is usually found in the ARM-specific part of
3084 the hash table entry. */
3085 struct arm_plt_info arm;
3086
3087 /* A list of all potential dynamic relocations against this symbol. */
3088 struct elf_dyn_relocs *dyn_relocs;
3089};
3090
e8b09b87
CL		 3091/* Structure to handle FDPIC support for local functions. */
3092struct fdpic_local {
3093 unsigned int funcdesc_cnt;
3094 unsigned int gotofffuncdesc_cnt;
3095 int funcdesc_offset;
3096};
3097
0ffa91dd 3098struct elf_arm_obj_tdata
ba93b8ac
DJ		 3099{
3100 struct elf_obj_tdata root;
3101
3102 /* tls_type for each local got entry. */
3103 char *local_got_tls_type;
ee065d83 3104
0855e32b
NS		 3105 /* GOTPLT entries for TLS descriptors. */
3106 bfd_vma *local_tlsdesc_gotent;
3107
34e77a92
RS		 3108 /* Information for local symbols that need entries in .iplt. */
3109 struct arm_local_iplt_info **local_iplt;
3110
bf21ed78
MS		 3111 /* Zero to warn when linking objects with incompatible enum sizes. */
3112 int no_enum_size_warning;
a9dc9481
JM		 3113
3114 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3115 int no_wchar_size_warning;
e8b09b87
CL		 3116
3117 /* Maintains FDPIC counters and funcdesc info. */
3118 struct fdpic_local *local_fdpic_cnts;
ba93b8ac
DJ		 3119};
3120
0ffa91dd
NC		 3121#define elf_arm_tdata(bfd) \
3122 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3123
0ffa91dd
NC		 3124#define elf32_arm_local_got_tls_type(bfd) \
3125 (elf_arm_tdata (bfd)->local_got_tls_type)
3126
0855e32b
NS		 3127#define elf32_arm_local_tlsdesc_gotent(bfd) \
3128 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3129
34e77a92
RS		 3130#define elf32_arm_local_iplt(bfd) \
3131 (elf_arm_tdata (bfd)->local_iplt)
3132
e8b09b87
CL		 3133#define elf32_arm_local_fdpic_cnts(bfd) \
3134 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3135
0ffa91dd
NC		 3136#define is_arm_elf(bfd) \
3137 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3138 && elf_tdata (bfd) != NULL \
4dfe6ac6 3139 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3140
3141static bfd_boolean
3142elf32_arm_mkobject (bfd *abfd)
3143{
0ffa91dd 3144 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3145 ARM_ELF_DATA);
ba93b8ac
DJ		 3146}
3147
ba93b8ac
DJ		 3148#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3149
e8b09b87
CL		 3150/* Structure to handle FDPIC support for extern functions. */
3151struct fdpic_global {
3152 unsigned int gotofffuncdesc_cnt;
3153 unsigned int gotfuncdesc_cnt;
3154 unsigned int funcdesc_cnt;
3155 int funcdesc_offset;
3156 int gotfuncdesc_offset;
3157};
3158
ba96a88f 3159/* Arm ELF linker hash entry. */
252b5132 3160struct elf32_arm_link_hash_entry
b38cadfb
NC		 3161{
3162 struct elf_link_hash_entry root;
252b5132 3163
b38cadfb
NC		 3164 /* Track dynamic relocs copied for this symbol. */
3165 struct elf_dyn_relocs *dyn_relocs;
b7693d02 3166
b38cadfb
NC		 3167 /* ARM-specific PLT information. */
3168 struct arm_plt_info plt;
ba93b8ac
DJ		 3169
3170#define GOT_UNKNOWN 0
3171#define GOT_NORMAL 1
3172#define GOT_TLS_GD 2
3173#define GOT_TLS_IE 4
0855e32b
NS		 3174#define GOT_TLS_GDESC 8
3175#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3176 unsigned int tls_type : 8;
34e77a92 3177
b38cadfb
NC		 3178 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3179 unsigned int is_iplt : 1;
34e77a92 3180
b38cadfb 3181 unsigned int unused : 23;
a4fd1a8e 3182
b38cadfb
NC		 3183 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3184 starting at the end of the jump table. */
3185 bfd_vma tlsdesc_got;
0855e32b 3186
b38cadfb
NC		 3187 /* The symbol marking the real symbol location for exported thumb
3188 symbols with Arm stubs. */
3189 struct elf_link_hash_entry *export_glue;
906e58ca 3190
b38cadfb 3191 /* A pointer to the most recently used stub hash entry against this
8029a119 3192 symbol. */
b38cadfb 3193 struct elf32_arm_stub_hash_entry *stub_cache;
e8b09b87
CL		 3194
3195 /* Counter for FDPIC relocations against this symbol. */
3196 struct fdpic_global fdpic_cnts;
b38cadfb 3197};
252b5132 3198
252b5132 3199/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3200#define elf32_arm_link_hash_traverse(table, func, info) \
3201 (elf_link_hash_traverse \
3202 (&(table)->root, \
b7693d02 3203 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3204 (info)))
3205
3206/* Get the ARM elf linker hash table from a link_info structure. */
3207#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3208 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3209 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3210
906e58ca
NC		 3211#define arm_stub_hash_lookup(table, string, create, copy) \
3212 ((struct elf32_arm_stub_hash_entry *) \
3213 bfd_hash_lookup ((table), (string), (create), (copy)))
3214
21d799b5
NC		 3215/* Array to keep track of which stub sections have been created, and
3216 information on stub grouping. */
3217struct map_stub
3218{
3219 /* This is the section to which stubs in the group will be
3220 attached. */
3221 asection *link_sec;
3222 /* The stub section. */
3223 asection *stub_sec;
3224};
3225
0855e32b
NS		 3226#define elf32_arm_compute_jump_table_size(htab) \
3227 ((htab)->next_tls_desc_index * 4)
3228
9b485d32 3229/* ARM ELF linker hash table. */
252b5132 3230struct elf32_arm_link_hash_table
906e58ca
NC		 3231{
3232 /* The main hash table. */
3233 struct elf_link_hash_table root;
252b5132 3234
906e58ca
NC		 3235 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3236 bfd_size_type thumb_glue_size;
252b5132 3237
906e58ca
NC		 3238 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3239 bfd_size_type arm_glue_size;
252b5132 3240
906e58ca
NC		 3241 /* The size in bytes of section containing the ARMv4 BX veneers. */
3242 bfd_size_type bx_glue_size;
845b51d6 3243
906e58ca
NC		 3244 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3245 veneer has been populated. */
3246 bfd_vma bx_glue_offset[15];
845b51d6 3247
906e58ca
NC		 3248 /* The size in bytes of the section containing glue for VFP11 erratum
3249 veneers. */
3250 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3251
a504d23a
LA		 3252 /* The size in bytes of the section containing glue for STM32L4XX erratum
3253 veneers. */
3254 bfd_size_type stm32l4xx_erratum_glue_size;
3255
48229727
JB		 3256 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3257 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3258 elf32_arm_write_section(). */
3259 struct a8_erratum_fix *a8_erratum_fixes;
3260 unsigned int num_a8_erratum_fixes;
3261
906e58ca
NC		 3262 /* An arbitrary input BFD chosen to hold the glue sections. */
3263 bfd * bfd_of_glue_owner;
ba96a88f 3264
906e58ca
NC		 3265 /* Nonzero to output a BE8 image. */
3266 int byteswap_code;
e489d0ae 3267
906e58ca
NC		 3268 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3269 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3270 int target1_is_rel;
9c504268 3271
906e58ca
NC		 3272 /* The relocation to use for R_ARM_TARGET2 relocations. */
3273 int target2_reloc;
eb043451 3274
906e58ca
NC		 3275 /* 0 = Ignore R_ARM_V4BX.
3276 1 = Convert BX to MOV PC.
3277 2 = Generate v4 interworing stubs. */
3278 int fix_v4bx;
319850b4 3279
48229727
JB		 3280 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3281 int fix_cortex_a8;
3282
2de70689
MGD		 3283 /* Whether we should fix the ARM1176 BLX immediate issue. */
3284 int fix_arm1176;
3285
906e58ca
NC		 3286 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3287 int use_blx;
33bfe774 3288
906e58ca
NC		 3289 /* What sort of code sequences we should look for which may trigger the
3290 VFP11 denorm erratum. */
3291 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3292
906e58ca
NC		 3293 /* Global counter for the number of fixes we have emitted. */
3294 int num_vfp11_fixes;
c7b8f16e 3295
a504d23a
LA		 3296 /* What sort of code sequences we should look for which may trigger the
3297 STM32L4XX erratum. */
3298 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3299
3300 /* Global counter for the number of fixes we have emitted. */
3301 int num_stm32l4xx_fixes;
3302
906e58ca
NC		 3303 /* Nonzero to force PIC branch veneers. */
3304 int pic_veneer;
27e55c4d 3305
906e58ca
NC		 3306 /* The number of bytes in the initial entry in the PLT. */
3307 bfd_size_type plt_header_size;
e5a52504 3308
906e58ca
NC		 3309 /* The number of bytes in the subsequent PLT etries. */
3310 bfd_size_type plt_entry_size;
e5a52504 3311
906e58ca
NC		 3312 /* True if the target system is VxWorks. */
3313 int vxworks_p;
00a97672 3314
906e58ca
NC		 3315 /* True if the target system is Symbian OS. */
3316 int symbian_p;
e5a52504 3317
b38cadfb
NC		 3318 /* True if the target system is Native Client. */
3319 int nacl_p;
3320
906e58ca 3321 /* True if the target uses REL relocations. */
f3185997 3322 bfd_boolean use_rel;
4e7fd91e 3323
54ddd295
TP		 3324 /* Nonzero if import library must be a secure gateway import library
3325 as per ARMv8-M Security Extensions. */
3326 int cmse_implib;
3327
0955507f
TP		 3328 /* The import library whose symbols' address must remain stable in
3329 the import library generated. */
3330 bfd *in_implib_bfd;
3331
0855e32b
NS		 3332 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3333 bfd_vma next_tls_desc_index;
3334
3335 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3336 bfd_vma num_tls_desc;
3337
906e58ca
NC		 3338 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3339 asection *srelplt2;
00a97672 3340
0855e32b
NS		 3341 /* The offset into splt of the PLT entry for the TLS descriptor
3342 resolver. Special values are 0, if not necessary (or not found
3343 to be necessary yet), and -1 if needed but not determined
3344 yet. */
3345 bfd_vma dt_tlsdesc_plt;
3346
3347 /* The offset into sgot of the GOT entry used by the PLT entry
3348 above. */
b38cadfb 3349 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3350
3351 /* Offset in .plt section of tls_arm_trampoline. */
3352 bfd_vma tls_trampoline;
3353
5c5a4843 3354 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
906e58ca
NC		 3355 union
3356 {
3357 bfd_signed_vma refcount;
3358 bfd_vma offset;
3359 } tls_ldm_got;
b7693d02 3360
87d72d41
AM		 3361 /* Small local sym cache. */
3362 struct sym_cache sym_cache;
906e58ca
NC		 3363
3364 /* For convenience in allocate_dynrelocs. */
3365 bfd * obfd;
3366
0855e32b
NS		 3367 /* The amount of space used by the reserved portion of the sgotplt
3368 section, plus whatever space is used by the jump slots. */
3369 bfd_vma sgotplt_jump_table_size;
3370
906e58ca
NC		 3371 /* The stub hash table. */
3372 struct bfd_hash_table stub_hash_table;
3373
3374 /* Linker stub bfd. */
3375 bfd *stub_bfd;
3376
3377 /* Linker call-backs. */
6bde4c52
TP		 3378 asection * (*add_stub_section) (const char *, asection *, asection *,
3379 unsigned int);
906e58ca
NC		 3380 void (*layout_sections_again) (void);
3381
3382 /* Array to keep track of which stub sections have been created, and
3383 information on stub grouping. */
21d799b5 3384 struct map_stub *stub_group;
906e58ca 3385
4ba2ef8f
TP		 3386 /* Input stub section holding secure gateway veneers. */
3387 asection *cmse_stub_sec;
3388
0955507f
TP		 3389 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3390 start to be allocated. */
3391 bfd_vma new_cmse_stub_offset;
3392
fe33d2fa 3393 /* Number of elements in stub_group. */
7292b3ac 3394 unsigned int top_id;
fe33d2fa 3395
906e58ca
NC		 3396 /* Assorted information used by elf32_arm_size_stubs. */
3397 unsigned int bfd_count;
7292b3ac 3398 unsigned int top_index;
906e58ca 3399 asection **input_list;
617a5ada
CL		 3400
3401 /* True if the target system uses FDPIC. */
3402 int fdpic_p;
e8b09b87
CL		 3403
3404 /* Fixup section. Used for FDPIC. */
3405 asection *srofixup;
906e58ca 3406};
252b5132 3407
e8b09b87
CL		 3408/* Add an FDPIC read-only fixup. */
3409static void
3410arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3411{
3412 bfd_vma fixup_offset;
3413
3414 fixup_offset = srofixup->reloc_count++ * 4;
3415 BFD_ASSERT (fixup_offset < srofixup->size);
3416 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3417}
3418
a504d23a
LA		 3419static inline int
3420ctz (unsigned int mask)
3421{
3422#if GCC_VERSION >= 3004
3423 return __builtin_ctz (mask);
3424#else
3425 unsigned int i;
3426
3427 for (i = 0; i < 8 * sizeof (mask); i++)
3428 {
3429 if (mask & 0x1)
3430 break;
3431 mask = (mask >> 1);
3432 }
3433 return i;
3434#endif
3435}
3436
3437static inline int
b25e998d 3438elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3439{
3440#if GCC_VERSION >= 3004
3441 return __builtin_popcount (mask);
3442#else
b25e998d
CG		 3443 unsigned int i;
3444 int sum = 0;
a504d23a
LA		 3445
3446 for (i = 0; i < 8 * sizeof (mask); i++)
3447 {
3448 if (mask & 0x1)
3449 sum++;
3450 mask = (mask >> 1);
3451 }
3452 return sum;
3453#endif
3454}
3455
e8b09b87
CL		 3456static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3457 asection *sreloc, Elf_Internal_Rela *rel);
3458
3459static void
3460arm_elf_fill_funcdesc(bfd *output_bfd,
3461 struct bfd_link_info *info,
3462 int *funcdesc_offset,
3463 int dynindx,
3464 int offset,
3465 bfd_vma addr,
3466 bfd_vma dynreloc_value,
3467 bfd_vma seg)
3468{
3469 if ((*funcdesc_offset & 1) == 0)
3470 {
3471 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3472 asection *sgot = globals->root.sgot;
3473
3474 if (bfd_link_pic(info))
3475 {
3476 asection *srelgot = globals->root.srelgot;
3477 Elf_Internal_Rela outrel;
3478
3479 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3480 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3481 outrel.r_addend = 0;
3482
3483 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3484 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3485 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3486 }
3487 else
3488 {
3489 struct elf_link_hash_entry *hgot = globals->root.hgot;
3490 bfd_vma got_value = hgot->root.u.def.value
3491 + hgot->root.u.def.section->output_section->vma
3492 + hgot->root.u.def.section->output_offset;
3493
3494 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3495 sgot->output_section->vma + sgot->output_offset
3496 + offset);
3497 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3498 sgot->output_section->vma + sgot->output_offset
3499 + offset + 4);
3500 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3501 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3502 }
3503 *funcdesc_offset |= 1;
3504 }
3505}
3506
780a67af
NC		 3507/* Create an entry in an ARM ELF linker hash table. */
3508
3509static struct bfd_hash_entry *
57e8b36a 3510elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3511 struct bfd_hash_table * table,
3512 const char * string)
780a67af
NC		 3513{
3514 struct elf32_arm_link_hash_entry * ret =
3515 (struct elf32_arm_link_hash_entry *) entry;
3516
3517 /* Allocate the structure if it has not already been allocated by a
3518 subclass. */
906e58ca 3519 if (ret == NULL)
21d799b5 3520 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3521 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3522 if (ret == NULL)
780a67af
NC		 3523 return (struct bfd_hash_entry *) ret;
3524
3525 /* Call the allocation method of the superclass. */
3526 ret = ((struct elf32_arm_link_hash_entry *)
3527 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3528 table, string));
57e8b36a 3529 if (ret != NULL)
b7693d02 3530 {
0bdcacaf 3531 ret->dyn_relocs = NULL;
ba93b8ac 3532 ret->tls_type = GOT_UNKNOWN;
0855e32b 3533 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3534 ret->plt.thumb_refcount = 0;
3535 ret->plt.maybe_thumb_refcount = 0;
3536 ret->plt.noncall_refcount = 0;
3537 ret->plt.got_offset = -1;
3538 ret->is_iplt = FALSE;
a4fd1a8e 3539 ret->export_glue = NULL;
906e58ca
NC		 3540
3541 ret->stub_cache = NULL;
e8b09b87
CL		 3542
3543 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3544 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3545 ret->fdpic_cnts.funcdesc_cnt = 0;
3546 ret->fdpic_cnts.funcdesc_offset = -1;
3547 ret->fdpic_cnts.gotfuncdesc_offset = -1;
b7693d02 3548 }
780a67af
NC		 3549
3550 return (struct bfd_hash_entry *) ret;
3551}
3552
34e77a92
RS		 3553/* Ensure that we have allocated bookkeeping structures for ABFD's local
3554 symbols. */
3555
3556static bfd_boolean
3557elf32_arm_allocate_local_sym_info (bfd *abfd)
3558{
3559 if (elf_local_got_refcounts (abfd) == NULL)
3560 {
3561 bfd_size_type num_syms;
3562 bfd_size_type size;
3563 char *data;
3564
3565 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3566 size = num_syms * (sizeof (bfd_signed_vma)
3567 + sizeof (struct arm_local_iplt_info *)
3568 + sizeof (bfd_vma)
e8b09b87
CL		 3569 + sizeof (char)
3570 + sizeof (struct fdpic_local));
34e77a92
RS		 3571 data = bfd_zalloc (abfd, size);
3572 if (data == NULL)
3573 return FALSE;
3574
e8b09b87
CL		 3575 elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
3576 data += num_syms * sizeof (struct fdpic_local);
3577
34e77a92
RS		 3578 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3579 data += num_syms * sizeof (bfd_signed_vma);
3580
3581 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3582 data += num_syms * sizeof (struct arm_local_iplt_info *);
3583
3584 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3585 data += num_syms * sizeof (bfd_vma);
3586
3587 elf32_arm_local_got_tls_type (abfd) = data;
3588 }
3589 return TRUE;
3590}
3591
3592/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3593 to input bfd ABFD. Create the information if it doesn't already exist.
3594 Return null if an allocation fails. */
3595
3596static struct arm_local_iplt_info *
3597elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3598{
3599 struct arm_local_iplt_info **ptr;
3600
3601 if (!elf32_arm_allocate_local_sym_info (abfd))
3602 return NULL;
3603
3604 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3605 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3606 if (*ptr == NULL)
3607 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3608 return *ptr;
3609}
3610
3611/* Try to obtain PLT information for the symbol with index R_SYMNDX
3612 in ABFD's symbol table. If the symbol is global, H points to its
3613 hash table entry, otherwise H is null.
3614
3615 Return true if the symbol does have PLT information. When returning
3616 true, point *ROOT_PLT at the target-independent reference count/offset
3617 union and *ARM_PLT at the ARM-specific information. */
3618
3619static bfd_boolean
4ba2ef8f
TP		 3620elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3621 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3622 unsigned long r_symndx, union gotplt_union **root_plt,
3623 struct arm_plt_info **arm_plt)
3624{
3625 struct arm_local_iplt_info *local_iplt;
3626
4ba2ef8f
TP		 3627 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3628 return FALSE;
3629
34e77a92
RS		 3630 if (h != NULL)
3631 {
3632 *root_plt = &h->root.plt;
3633 *arm_plt = &h->plt;
3634 return TRUE;
3635 }
3636
3637 if (elf32_arm_local_iplt (abfd) == NULL)
3638 return FALSE;
3639
3640 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3641 if (local_iplt == NULL)
3642 return FALSE;
3643
3644 *root_plt = &local_iplt->root;
3645 *arm_plt = &local_iplt->arm;
3646 return TRUE;
3647}
3648
59029f57
CL		 3649static bfd_boolean using_thumb_only (struct elf32_arm_link_hash_table *globals);
3650
34e77a92
RS		 3651/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3652 before it. */
3653
3654static bfd_boolean
3655elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3656 struct arm_plt_info *arm_plt)
3657{
3658 struct elf32_arm_link_hash_table *htab;
3659
3660 htab = elf32_arm_hash_table (info);
59029f57
CL		 3661
3662 return (!using_thumb_only(htab) && (arm_plt->thumb_refcount != 0
3663 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0)));
34e77a92
RS		 3664}
3665
3666/* Return a pointer to the head of the dynamic reloc list that should
3667 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3668 ABFD's symbol table. Return null if an error occurs. */
3669
3670static struct elf_dyn_relocs **
3671elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3672 Elf_Internal_Sym *isym)
3673{
3674 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3675 {
3676 struct arm_local_iplt_info *local_iplt;
3677
3678 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3679 if (local_iplt == NULL)
3680 return NULL;
3681 return &local_iplt->dyn_relocs;
3682 }
3683 else
3684 {
3685 /* Track dynamic relocs needed for local syms too.
3686 We really need local syms available to do this
3687 easily. Oh well. */
3688 asection *s;
3689 void *vpp;
3690
3691 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3692 if (s == NULL)
3693 abort ();
3694
3695 vpp = &elf_section_data (s)->local_dynrel;
3696 return (struct elf_dyn_relocs **) vpp;
3697 }
3698}
3699
906e58ca
NC		 3700/* Initialize an entry in the stub hash table. */
3701
3702static struct bfd_hash_entry *
3703stub_hash_newfunc (struct bfd_hash_entry *entry,
3704 struct bfd_hash_table *table,
3705 const char *string)
3706{
3707 /* Allocate the structure if it has not already been allocated by a
3708 subclass. */
3709 if (entry == NULL)
3710 {
21d799b5 3711 entry = (struct bfd_hash_entry *)
99059e56 3712 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3713 if (entry == NULL)
3714 return entry;
3715 }
3716
3717 /* Call the allocation method of the superclass. */
3718 entry = bfd_hash_newfunc (entry, table, string);
3719 if (entry != NULL)
3720 {
3721 struct elf32_arm_stub_hash_entry *eh;
3722
3723 /* Initialize the local fields. */
3724 eh = (struct elf32_arm_stub_hash_entry *) entry;
3725 eh->stub_sec = NULL;
0955507f 3726 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3727 eh->source_value = 0;
906e58ca
NC		 3728 eh->target_value = 0;
3729 eh->target_section = NULL;
cedfb179 3730 eh->orig_insn = 0;
906e58ca 3731 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3732 eh->stub_size = 0;
3733 eh->stub_template = NULL;
0955507f 3734 eh->stub_template_size = -1;
906e58ca
NC		 3735 eh->h = NULL;
3736 eh->id_sec = NULL;
d8d2f433 3737 eh->output_name = NULL;
906e58ca
NC		 3738 }
3739
3740 return entry;
3741}
3742
00a97672 3743/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3744 shortcuts to them in our hash table. */
3745
3746static bfd_boolean
57e8b36a 3747create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3748{
3749 struct elf32_arm_link_hash_table *htab;
3750
e5a52504 3751 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3752 if (htab == NULL)
3753 return FALSE;
3754
e5a52504
MM		 3755 /* BPABI objects never have a GOT, or associated sections. */
3756 if (htab->symbian_p)
3757 return TRUE;
3758
5e681ec4
PB		 3759 if (! _bfd_elf_create_got_section (dynobj, info))
3760 return FALSE;
3761
e8b09b87
CL		 3762 /* Also create .rofixup. */
3763 if (htab->fdpic_p)
3764 {
3765 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3766 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3767 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
3768 if (htab->srofixup == NULL || ! bfd_set_section_alignment (dynobj, htab->srofixup, 2))
3769 return FALSE;
3770 }
3771
5e681ec4
PB		 3772 return TRUE;
3773}
3774
34e77a92
RS		 3775/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3776
3777static bfd_boolean
3778create_ifunc_sections (struct bfd_link_info *info)
3779{
3780 struct elf32_arm_link_hash_table *htab;
3781 const struct elf_backend_data *bed;
3782 bfd *dynobj;
3783 asection *s;
3784 flagword flags;
b38cadfb 3785
34e77a92
RS		 3786 htab = elf32_arm_hash_table (info);
3787 dynobj = htab->root.dynobj;
3788 bed = get_elf_backend_data (dynobj);
3789 flags = bed->dynamic_sec_flags;
3790
3791 if (htab->root.iplt == NULL)
3792 {
3d4d4302
AM		 3793 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3794 flags | SEC_READONLY | SEC_CODE);
34e77a92 3795 if (s == NULL
a0f49396 3796 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3797 return FALSE;
3798 htab->root.iplt = s;
3799 }
3800
3801 if (htab->root.irelplt == NULL)
3802 {
3d4d4302
AM		 3803 s = bfd_make_section_anyway_with_flags (dynobj,
3804 RELOC_SECTION (htab, ".iplt"),
3805 flags | SEC_READONLY);
34e77a92 3806 if (s == NULL
a0f49396 3807 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3808 return FALSE;
3809 htab->root.irelplt = s;
3810 }
3811
3812 if (htab->root.igotplt == NULL)
3813 {
3d4d4302 3814 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3815 if (s == NULL
3816 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3817 return FALSE;
3818 htab->root.igotplt = s;
3819 }
3820 return TRUE;
3821}
3822
eed94f8f
NC		 3823/* Determine if we're dealing with a Thumb only architecture. */
3824
3825static bfd_boolean
3826using_thumb_only (struct elf32_arm_link_hash_table *globals)
3827{
2fd158eb
TP		 3828 int arch;
3829 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3830 Tag_CPU_arch_profile);
eed94f8f 3831
2fd158eb
TP		 3832 if (profile)
3833 return profile == 'M';
eed94f8f 3834
2fd158eb 3835 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3836
60a019a0 3837 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3838 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0 3839
2fd158eb
TP		 3840 if (arch == TAG_CPU_ARCH_V6_M
3841 || arch == TAG_CPU_ARCH_V6S_M
3842 || arch == TAG_CPU_ARCH_V7E_M
3843 || arch == TAG_CPU_ARCH_V8M_BASE
3844 || arch == TAG_CPU_ARCH_V8M_MAIN)
3845 return TRUE;
eed94f8f 3846
2fd158eb 3847 return FALSE;
eed94f8f
NC		 3848}
3849
3850/* Determine if we're dealing with a Thumb-2 object. */
3851
3852static bfd_boolean
3853using_thumb2 (struct elf32_arm_link_hash_table *globals)
3854{
60a019a0
TP		 3855 int arch;
3856 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3857 Tag_THUMB_ISA_use);
3858
3859 if (thumb_isa)
3860 return thumb_isa == 2;
3861
3862 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3863
3864 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3865 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0
TP		 3866
3867 return (arch == TAG_CPU_ARCH_V6T2
3868 || arch == TAG_CPU_ARCH_V7
3869 || arch == TAG_CPU_ARCH_V7E_M
3870 || arch == TAG_CPU_ARCH_V8
bff0500d 3871 || arch == TAG_CPU_ARCH_V8R
60a019a0 3872 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3873}
3874
5e866f5a
TP		 3875/* Determine whether Thumb-2 BL instruction is available. */
3876
3877static bfd_boolean
3878using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3879{
3880 int arch =
3881 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3882
3883 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3884 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
5e866f5a
TP		 3885
3886 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3887 return (arch == TAG_CPU_ARCH_V6T2
3888 || arch >= TAG_CPU_ARCH_V7);
3889}
3890
00a97672
RS		 3891/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3892 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3893 hash table. */
3894
3895static bfd_boolean
57e8b36a 3896elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3897{
3898 struct elf32_arm_link_hash_table *htab;
3899
3900 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3901 if (htab == NULL)
3902 return FALSE;
3903
362d30a1 3904 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3905 return FALSE;
3906
3907 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3908 return FALSE;
3909
00a97672
RS		 3910 if (htab->vxworks_p)
3911 {
3912 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3913 return FALSE;
3914
0e1862bb 3915 if (bfd_link_pic (info))
00a97672
RS		 3916 {
3917 htab->plt_header_size = 0;
3918 htab->plt_entry_size
3919 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3920 }
3921 else
3922 {
3923 htab->plt_header_size
3924 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3925 htab->plt_entry_size
3926 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3927 }
aebf9be7
NC		 3928
3929 if (elf_elfheader (dynobj))
3930 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3931 }
eed94f8f
NC		 3932 else
3933 {
3934 /* PR ld/16017
3935 Test for thumb only architectures. Note - we cannot just call
3936 using_thumb_only() as the attributes in the output bfd have not been
3937 initialised at this point, so instead we use the input bfd. */
3938 bfd * saved_obfd = htab->obfd;
3939
3940 htab->obfd = dynobj;
3941 if (using_thumb_only (htab))
3942 {
3943 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3944 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3945 }
3946 htab->obfd = saved_obfd;
3947 }
5e681ec4 3948
7801f98f
CL		 3949 if (htab->fdpic_p) {
3950 htab->plt_header_size = 0;
3951 if (info->flags & DF_BIND_NOW)
3952 htab->plt_entry_size = 4 * (ARRAY_SIZE(elf32_arm_fdpic_plt_entry) - 5);
3953 else
3954 htab->plt_entry_size = 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry);
3955 }
3956
362d30a1
RS		 3957 if (!htab->root.splt
3958 || !htab->root.srelplt
9d19e4fd
AM		 3959 || !htab->root.sdynbss
3960 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 3961 abort ();
3962
3963 return TRUE;
3964}
3965
906e58ca
NC		 3966/* Copy the extra info we tack onto an elf_link_hash_entry. */
3967
3968static void
3969elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3970 struct elf_link_hash_entry *dir,
3971 struct elf_link_hash_entry *ind)
3972{
3973 struct elf32_arm_link_hash_entry *edir, *eind;
3974
3975 edir = (struct elf32_arm_link_hash_entry *) dir;
3976 eind = (struct elf32_arm_link_hash_entry *) ind;
3977
0bdcacaf 3978 if (eind->dyn_relocs != NULL)
906e58ca 3979 {
0bdcacaf 3980 if (edir->dyn_relocs != NULL)
906e58ca 3981 {
0bdcacaf
RS		 3982 struct elf_dyn_relocs **pp;
3983 struct elf_dyn_relocs *p;
906e58ca
NC		 3984
3985 /* Add reloc counts against the indirect sym to the direct sym
3986 list. Merge any entries against the same section. */
0bdcacaf 3987 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3988 {
0bdcacaf 3989 struct elf_dyn_relocs *q;
906e58ca 3990
0bdcacaf
RS		 3991 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3992 if (q->sec == p->sec)
906e58ca
NC		 3993 {
3994 q->pc_count += p->pc_count;
3995 q->count += p->count;
3996 *pp = p->next;
3997 break;
3998 }
3999 if (q == NULL)
4000 pp = &p->next;
4001 }
0bdcacaf 4002 *pp = edir->dyn_relocs;
906e58ca
NC		 4003 }
4004
0bdcacaf
RS		 4005 edir->dyn_relocs = eind->dyn_relocs;
4006 eind->dyn_relocs = NULL;
906e58ca
NC		 4007 }
4008
4009 if (ind->root.type == bfd_link_hash_indirect)
4010 {
4011 /* Copy over PLT info. */
34e77a92
RS		 4012 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
4013 eind->plt.thumb_refcount = 0;
4014 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
4015 eind->plt.maybe_thumb_refcount = 0;
4016 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
4017 eind->plt.noncall_refcount = 0;
4018
e8b09b87
CL		 4019 /* Copy FDPIC counters. */
4020 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
4021 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
4022 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
4023
34e77a92
RS		 4024 /* We should only allocate a function to .iplt once the final
4025 symbol information is known. */
4026 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 4027
4028 if (dir->got.refcount <= 0)
4029 {
4030 edir->tls_type = eind->tls_type;
4031 eind->tls_type = GOT_UNKNOWN;
4032 }
4033 }
4034
4035 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4036}
4037
68faa637
AM		 4038/* Destroy an ARM elf linker hash table. */
4039
4040static void
d495ab0d 4041elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 4042{
4043 struct elf32_arm_link_hash_table *ret
d495ab0d 4044 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 4045
4046 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 4047 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 4048}
4049
906e58ca
NC		 4050/* Create an ARM elf linker hash table. */
4051
4052static struct bfd_link_hash_table *
4053elf32_arm_link_hash_table_create (bfd *abfd)
4054{
4055 struct elf32_arm_link_hash_table *ret;
4056 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
4057
7bf52ea2 4058 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 4059 if (ret == NULL)
4060 return NULL;
4061
4062 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4063 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 4064 sizeof (struct elf32_arm_link_hash_entry),
4065 ARM_ELF_DATA))
906e58ca
NC		 4066 {
4067 free (ret);
4068 return NULL;
4069 }
4070
906e58ca 4071 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 4072 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 4073#ifdef FOUR_WORD_PLT
4074 ret->plt_header_size = 16;
4075 ret->plt_entry_size = 16;
4076#else
4077 ret->plt_header_size = 20;
1db37fe6 4078 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 4079#endif
f3185997 4080 ret->use_rel = TRUE;
906e58ca 4081 ret->obfd = abfd;
617a5ada 4082 ret->fdpic_p = 0;
906e58ca
NC		 4083
4084 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4085 sizeof (struct elf32_arm_stub_hash_entry)))
4086 {
d495ab0d 4087 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 4088 return NULL;
4089 }
d495ab0d 4090 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 4091
4092 return &ret->root.root;
4093}
4094
cd1dac3d
DG		 4095/* Determine what kind of NOPs are available. */
4096
4097static bfd_boolean
4098arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4099{
4100 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4101 Tag_CPU_arch);
cd1dac3d 4102
60a019a0 4103 /* Force return logic to be reviewed for each new architecture. */
bff0500d 4104 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0
TP		 4105
4106 return (arch == TAG_CPU_ARCH_V6T2
4107 || arch == TAG_CPU_ARCH_V6K
4108 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 4109 || arch == TAG_CPU_ARCH_V8
4110 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 4111}
4112
f4ac8484
DJ		 4113static bfd_boolean
4114arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4115{
4116 switch (stub_type)
4117 {
fea2b4d6 4118 case arm_stub_long_branch_thumb_only:
80c135e5 4119 case arm_stub_long_branch_thumb2_only:
d5a67c02 4120 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 4121 case arm_stub_long_branch_v4t_thumb_arm:
4122 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 4123 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 4124 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 4125 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 4126 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 4127 return TRUE;
4128 case arm_stub_none:
4129 BFD_FAIL ();
4130 return FALSE;
4131 break;
4132 default:
4133 return FALSE;
4134 }
4135}
4136
906e58ca
NC		 4137/* Determine the type of stub needed, if any, for a call. */
4138
4139static enum elf32_arm_stub_type
4140arm_type_of_stub (struct bfd_link_info *info,
4141 asection *input_sec,
4142 const Elf_Internal_Rela *rel,
34e77a92 4143 unsigned char st_type,
35fc36a8 4144 enum arm_st_branch_type *actual_branch_type,
906e58ca 4145 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 4146 bfd_vma destination,
4147 asection *sym_sec,
4148 bfd *input_bfd,
4149 const char *name)
906e58ca
NC		 4150{
4151 bfd_vma location;
4152 bfd_signed_vma branch_offset;
4153 unsigned int r_type;
4154 struct elf32_arm_link_hash_table * globals;
5e866f5a 4155 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 4156 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 4157 int use_plt = 0;
35fc36a8 4158 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 4159 union gotplt_union *root_plt;
4160 struct arm_plt_info *arm_plt;
d5a67c02
AV		 4161 int arch;
4162 int thumb2_movw;
906e58ca 4163
35fc36a8 4164 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 4165 return stub_type;
4166
906e58ca 4167 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4168 if (globals == NULL)
4169 return stub_type;
906e58ca
NC		 4170
4171 thumb_only = using_thumb_only (globals);
906e58ca 4172 thumb2 = using_thumb2 (globals);
5e866f5a 4173 thumb2_bl = using_thumb2_bl (globals);
906e58ca 4174
d5a67c02
AV		 4175 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4176
4177 /* True for architectures that implement the thumb2 movw instruction. */
4178 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4179
906e58ca
NC		 4180 /* Determine where the call point is. */
4181 location = (input_sec->output_offset
4182 + input_sec->output_section->vma
4183 + rel->r_offset);
4184
906e58ca
NC		 4185 r_type = ELF32_R_TYPE (rel->r_info);
4186
39f21624
NC		 4187 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4188 are considering a function call relocation. */
c5423981 4189 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 4190 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 4191 && branch_type == ST_BRANCH_TO_ARM)
4192 branch_type = ST_BRANCH_TO_THUMB;
4193
34e77a92
RS		 4194 /* For TLS call relocs, it is the caller's responsibility to provide
4195 the address of the appropriate trampoline. */
4196 if (r_type != R_ARM_TLS_CALL
4197 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 4198 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4199 ELF32_R_SYM (rel->r_info), &root_plt,
4200 &arm_plt)
34e77a92 4201 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 4202 {
34e77a92 4203 asection *splt;
fe33d2fa 4204
34e77a92
RS		 4205 if (hash == NULL || hash->is_iplt)
4206 splt = globals->root.iplt;
4207 else
4208 splt = globals->root.splt;
4209 if (splt != NULL)
b38cadfb 4210 {
34e77a92
RS		 4211 use_plt = 1;
4212
4213 /* Note when dealing with PLT entries: the main PLT stub is in
4214 ARM mode, so if the branch is in Thumb mode, another
4215 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4216 PLT stub. If a long branch stub is needed, we'll add a
4217 Thumb->Arm one and branch directly to the ARM PLT entry.
4218 Here, we have to check if a pre-PLT Thumb->ARM stub
4219 is needed and if it will be close enough. */
34e77a92
RS		 4220
4221 destination = (splt->output_section->vma
4222 + splt->output_offset
4223 + root_plt->offset);
4224 st_type = STT_FUNC;
2df2751d
CL		 4225
4226 /* Thumb branch/call to PLT: it can become a branch to ARM
4227 or to Thumb. We must perform the same checks and
4228 corrections as in elf32_arm_final_link_relocate. */
4229 if ((r_type == R_ARM_THM_CALL)
4230 || (r_type == R_ARM_THM_JUMP24))
4231 {
4232 if (globals->use_blx
4233 && r_type == R_ARM_THM_CALL
4234 && !thumb_only)
4235 {
4236 /* If the Thumb BLX instruction is available, convert
4237 the BL to a BLX instruction to call the ARM-mode
4238 PLT entry. */
4239 branch_type = ST_BRANCH_TO_ARM;
4240 }
4241 else
4242 {
4243 if (!thumb_only)
4244 /* Target the Thumb stub before the ARM PLT entry. */
4245 destination -= PLT_THUMB_STUB_SIZE;
4246 branch_type = ST_BRANCH_TO_THUMB;
4247 }
4248 }
4249 else
4250 {
4251 branch_type = ST_BRANCH_TO_ARM;
4252 }
34e77a92 4253 }
5fa9e92f 4254 }
34e77a92
RS		 4255 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4256 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4257
fe33d2fa
CL		 4258 branch_offset = (bfd_signed_vma)(destination - location);
4259
0855e32b 4260 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4261 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4262 {
5fa9e92f
CL		 4263 /* Handle cases where:
4264 - this call goes too far (different Thumb/Thumb2 max
99059e56 4265 distance)
155d87d7 4266 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4267 Thumb->Arm branch (not bl). A stub is needed in this case,
4268 but only if this call is not through a PLT entry. Indeed,
695344c0 4269 PLT stubs handle mode switching already. */
5e866f5a 4270 if ((!thumb2_bl
906e58ca
NC		 4271 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4272 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4273 || (thumb2_bl
906e58ca
NC		 4274 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4275 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4276 || (thumb2
4277 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4278 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4279 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4280 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4281 && (((r_type == R_ARM_THM_CALL
4282 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4283 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4284 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4285 && !use_plt))
906e58ca 4286 {
2df2751d
CL		 4287 /* If we need to insert a Thumb-Thumb long branch stub to a
4288 PLT, use one that branches directly to the ARM PLT
4289 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4290 stub, undo this now. */
695344c0
NC		 4291 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4292 {
4293 branch_type = ST_BRANCH_TO_ARM;
4294 branch_offset += PLT_THUMB_STUB_SIZE;
4295 }
2df2751d 4296
35fc36a8 4297 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4298 {
4299 /* Thumb to thumb. */
4300 if (!thumb_only)
4301 {
d5a67c02 4302 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4303 _bfd_error_handler
871b3ab2 4304 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4305 " section with SHF_ARM_PURECODE section"
4306 " attribute is only supported for M-profile"
90b6238f 4307 " targets that implement the movw instruction"),
10463f39 4308 input_bfd, input_sec);
d5a67c02 4309
0e1862bb 4310 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4311 /* PIC stubs. */
155d87d7 4312 ? ((globals->use_blx
9553db3c 4313 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4314 /* V5T and above. Stub starts with ARM code, so
4315 we must be able to switch mode before
4316 reaching it, which is only possible for 'bl'
4317 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4318 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4319 /* On V4T, use Thumb code only. */
d3626fb0 4320 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4321
4322 /* non-PIC stubs. */
155d87d7 4323 : ((globals->use_blx
9553db3c 4324 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4325 /* V5T and above. */
4326 ? arm_stub_long_branch_any_any
4327 /* V4T. */
d3626fb0 4328 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4329 }
4330 else
4331 {
d5a67c02
AV		 4332 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4333 stub_type = arm_stub_long_branch_thumb2_only_pure;
4334 else
4335 {
4336 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4337 _bfd_error_handler
871b3ab2 4338 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4339 " section with SHF_ARM_PURECODE section"
4340 " attribute is only supported for M-profile"
90b6238f 4341 " targets that implement the movw instruction"),
10463f39 4342 input_bfd, input_sec);
d5a67c02
AV		 4343
4344 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4345 /* PIC stub. */
4346 ? arm_stub_long_branch_thumb_only_pic
4347 /* non-PIC stub. */
4348 : (thumb2 ? arm_stub_long_branch_thumb2_only
4349 : arm_stub_long_branch_thumb_only);
4350 }
906e58ca
NC		 4351 }
4352 }
4353 else
4354 {
d5a67c02 4355 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4356 _bfd_error_handler
871b3ab2 4357 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4358 " section with SHF_ARM_PURECODE section"
4359 " attribute is only supported" " for M-profile"
90b6238f 4360 " targets that implement the movw instruction"),
10463f39 4361 input_bfd, input_sec);
d5a67c02 4362
906e58ca 4363 /* Thumb to arm. */
c820be07
NC		 4364 if (sym_sec != NULL
4365 && sym_sec->owner != NULL
4366 && !INTERWORK_FLAG (sym_sec->owner))
4367 {
4eca0228 4368 _bfd_error_handler
90b6238f
AM		 4369 (_("%pB(%s): warning: interworking not enabled;"
4370 " first occurrence: %pB: %s call to %s"),
4371 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4372 }
4373
0855e32b 4374 stub_type =
0e1862bb 4375 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4376 /* PIC stubs. */
0855e32b 4377 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4378 /* TLS PIC stubs. */
0855e32b
NS		 4379 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4380 : arm_stub_long_branch_v4t_thumb_tls_pic)
4381 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4382 /* V5T PIC and above. */
4383 ? arm_stub_long_branch_any_arm_pic
4384 /* V4T PIC stub. */
4385 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4386
4387 /* non-PIC stubs. */
0855e32b 4388 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4389 /* V5T and above. */
4390 ? arm_stub_long_branch_any_any
4391 /* V4T. */
4392 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4393
4394 /* Handle v4t short branches. */
fea2b4d6 4395 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4396 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4397 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4398 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4399 }
4400 }
4401 }
fe33d2fa
CL		 4402 else if (r_type == R_ARM_CALL
4403 || r_type == R_ARM_JUMP24
0855e32b
NS		 4404 || r_type == R_ARM_PLT32
4405 || r_type == R_ARM_TLS_CALL)
906e58ca 4406 {
d5a67c02 4407 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4408 _bfd_error_handler
871b3ab2 4409 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4410 " section with SHF_ARM_PURECODE section"
4411 " attribute is only supported for M-profile"
90b6238f 4412 " targets that implement the movw instruction"),
10463f39 4413 input_bfd, input_sec);
35fc36a8 4414 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4415 {
4416 /* Arm to thumb. */
c820be07
NC		 4417
4418 if (sym_sec != NULL
4419 && sym_sec->owner != NULL
4420 && !INTERWORK_FLAG (sym_sec->owner))
4421 {
4eca0228 4422 _bfd_error_handler
90b6238f
AM		 4423 (_("%pB(%s): warning: interworking not enabled;"
4424 " first occurrence: %pB: %s call to %s"),
4425 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4426 }
4427
4428 /* We have an extra 2-bytes reach because of
4429 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4430 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4431 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4432 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4433 || (r_type == R_ARM_JUMP24)
4434 || (r_type == R_ARM_PLT32))
906e58ca 4435 {
0e1862bb 4436 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4437 /* PIC stubs. */
ebe24dd4
CL		 4438 ? ((globals->use_blx)
4439 /* V5T and above. */
4440 ? arm_stub_long_branch_any_thumb_pic
4441 /* V4T stub. */
4442 : arm_stub_long_branch_v4t_arm_thumb_pic)
4443
c2b4a39d
CL		 4444 /* non-PIC stubs. */
4445 : ((globals->use_blx)
4446 /* V5T and above. */
4447 ? arm_stub_long_branch_any_any
4448 /* V4T. */
4449 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4450 }
4451 }
4452 else
4453 {
4454 /* Arm to arm. */
4455 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4456 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4457 {
0855e32b 4458 stub_type =
0e1862bb 4459 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4460 /* PIC stubs. */
0855e32b 4461 ? (r_type == R_ARM_TLS_CALL
6a631e86 4462 /* TLS PIC Stub. */
0855e32b 4463 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4464 : (globals->nacl_p
4465 ? arm_stub_long_branch_arm_nacl_pic
4466 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4467 /* non-PIC stubs. */
7a89b94e
NC		 4468 : (globals->nacl_p
4469 ? arm_stub_long_branch_arm_nacl
4470 : arm_stub_long_branch_any_any);
906e58ca
NC		 4471 }
4472 }
4473 }
4474
fe33d2fa
CL		 4475 /* If a stub is needed, record the actual destination type. */
4476 if (stub_type != arm_stub_none)
35fc36a8 4477 *actual_branch_type = branch_type;
fe33d2fa 4478
906e58ca
NC		 4479 return stub_type;
4480}
4481
4482/* Build a name for an entry in the stub hash table. */
4483
4484static char *
4485elf32_arm_stub_name (const asection *input_section,
4486 const asection *sym_sec,
4487 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4488 const Elf_Internal_Rela *rel,
4489 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4490{
4491 char *stub_name;
4492 bfd_size_type len;
4493
4494 if (hash)
4495 {
fe33d2fa 4496 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4497 stub_name = (char *) bfd_malloc (len);
906e58ca 4498 if (stub_name != NULL)
fe33d2fa 4499 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4500 input_section->id & 0xffffffff,
4501 hash->root.root.root.string,
fe33d2fa
CL		 4502 (int) rel->r_addend & 0xffffffff,
4503 (int) stub_type);
906e58ca
NC		 4504 }
4505 else
4506 {
fe33d2fa 4507 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4508 stub_name = (char *) bfd_malloc (len);
906e58ca 4509 if (stub_name != NULL)
fe33d2fa 4510 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4511 input_section->id & 0xffffffff,
4512 sym_sec->id & 0xffffffff,
0855e32b
NS		 4513 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4514 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4515 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4516 (int) rel->r_addend & 0xffffffff,
4517 (int) stub_type);
906e58ca
NC		 4518 }
4519
4520 return stub_name;
4521}
4522
4523/* Look up an entry in the stub hash. Stub entries are cached because
4524 creating the stub name takes a bit of time. */
4525
4526static struct elf32_arm_stub_hash_entry *
4527elf32_arm_get_stub_entry (const asection *input_section,
4528 const asection *sym_sec,
4529 struct elf_link_hash_entry *hash,
4530 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4531 struct elf32_arm_link_hash_table *htab,
4532 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4533{
4534 struct elf32_arm_stub_hash_entry *stub_entry;
4535 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4536 const asection *id_sec;
4537
4538 if ((input_section->flags & SEC_CODE) == 0)
4539 return NULL;
4540
4541 /* If this input section is part of a group of sections sharing one
4542 stub section, then use the id of the first section in the group.
4543 Stub names need to include a section id, as there may well be
4544 more than one stub used to reach say, printf, and we need to
4545 distinguish between them. */
c2abbbeb 4546 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4547 id_sec = htab->stub_group[input_section->id].link_sec;
4548
4549 if (h != NULL && h->stub_cache != NULL
4550 && h->stub_cache->h == h
fe33d2fa
CL		 4551 && h->stub_cache->id_sec == id_sec
4552 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4553 {
4554 stub_entry = h->stub_cache;
4555 }
4556 else
4557 {
4558 char *stub_name;
4559
fe33d2fa 4560 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4561 if (stub_name == NULL)
4562 return NULL;
4563
4564 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4565 stub_name, FALSE, FALSE);
4566 if (h != NULL)
4567 h->stub_cache = stub_entry;
4568
4569 free (stub_name);
4570 }
4571
4572 return stub_entry;
4573}
4574
daa4adae
TP		 4575/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4576 section. */
4577
4578static bfd_boolean
4579arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4580{
4581 if (stub_type >= max_stub_type)
4582 abort (); /* Should be unreachable. */
4583
4ba2ef8f
TP		 4584 switch (stub_type)
4585 {
4586 case arm_stub_cmse_branch_thumb_only:
4587 return TRUE;
4588
4589 default:
4590 return FALSE;
4591 }
4592
4593 abort (); /* Should be unreachable. */
daa4adae
TP		 4594}
4595
4596/* Required alignment (as a power of 2) for the dedicated section holding
4597 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4598 with input sections. */
4599
4600static int
4601arm_dedicated_stub_output_section_required_alignment
4602 (enum elf32_arm_stub_type stub_type)
4603{
4604 if (stub_type >= max_stub_type)
4605 abort (); /* Should be unreachable. */
4606
4ba2ef8f
TP		 4607 switch (stub_type)
4608 {
4609 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4610 boundary. */
4611 case arm_stub_cmse_branch_thumb_only:
4612 return 5;
4613
4614 default:
4615 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4616 return 0;
4617 }
4618
4619 abort (); /* Should be unreachable. */
daa4adae
TP		 4620}
4621
4622/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4623 NULL if veneers of this type are interspersed with input sections. */
4624
4625static const char *
4626arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4627{
4628 if (stub_type >= max_stub_type)
4629 abort (); /* Should be unreachable. */
4630
4ba2ef8f
TP		 4631 switch (stub_type)
4632 {
4633 case arm_stub_cmse_branch_thumb_only:
4634 return ".gnu.sgstubs";
4635
4636 default:
4637 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4638 return NULL;
4639 }
4640
4641 abort (); /* Should be unreachable. */
daa4adae
TP		 4642}
4643
4644/* If veneers of type STUB_TYPE should go in a dedicated output section,
4645 returns the address of the hash table field in HTAB holding a pointer to the
4646 corresponding input section. Otherwise, returns NULL. */
4647
4648static asection **
4ba2ef8f
TP		 4649arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4650 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4651{
4652 if (stub_type >= max_stub_type)
4653 abort (); /* Should be unreachable. */
4654
4ba2ef8f
TP		 4655 switch (stub_type)
4656 {
4657 case arm_stub_cmse_branch_thumb_only:
4658 return &htab->cmse_stub_sec;
4659
4660 default:
4661 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4662 return NULL;
4663 }
4664
4665 abort (); /* Should be unreachable. */
daa4adae
TP		 4666}
4667
4668/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4669 is the section that branch into veneer and can be NULL if stub should go in
4670 a dedicated output section. Returns a pointer to the stub section, and the
4671 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4672 LINK_SEC_P may be NULL. */
906e58ca 4673
48229727
JB		 4674static asection *
4675elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4676 struct elf32_arm_link_hash_table *htab,
4677 enum elf32_arm_stub_type stub_type)
906e58ca 4678{
daa4adae
TP		 4679 asection *link_sec, *out_sec, **stub_sec_p;
4680 const char *stub_sec_prefix;
4681 bfd_boolean dedicated_output_section =
4682 arm_dedicated_stub_output_section_required (stub_type);
4683 int align;
906e58ca 4684
daa4adae 4685 if (dedicated_output_section)
906e58ca 4686 {
daa4adae
TP		 4687 bfd *output_bfd = htab->obfd;
4688 const char *out_sec_name =
4689 arm_dedicated_stub_output_section_name (stub_type);
4690 link_sec = NULL;
4691 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4692 stub_sec_prefix = out_sec_name;
4693 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4694 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4695 if (out_sec == NULL)
906e58ca 4696 {
90b6238f 4697 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4698 "section %s"), out_sec_name);
daa4adae 4699 return NULL;
906e58ca 4700 }
daa4adae
TP		 4701 }
4702 else
4703 {
c2abbbeb 4704 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4705 link_sec = htab->stub_group[section->id].link_sec;
4706 BFD_ASSERT (link_sec != NULL);
4707 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4708 if (*stub_sec_p == NULL)
4709 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4710 stub_sec_prefix = link_sec->name;
4711 out_sec = link_sec->output_section;
4712 align = htab->nacl_p ? 4 : 3;
906e58ca 4713 }
b38cadfb 4714
daa4adae
TP		 4715 if (*stub_sec_p == NULL)
4716 {
4717 size_t namelen;
4718 bfd_size_type len;
4719 char *s_name;
4720
4721 namelen = strlen (stub_sec_prefix);
4722 len = namelen + sizeof (STUB_SUFFIX);
4723 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4724 if (s_name == NULL)
4725 return NULL;
4726
4727 memcpy (s_name, stub_sec_prefix, namelen);
4728 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4729 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4730 align);
4731 if (*stub_sec_p == NULL)
4732 return NULL;
4733
4734 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4735 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4736 | SEC_KEEP;
4737 }
4738
4739 if (!dedicated_output_section)
4740 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4741
48229727
JB		 4742 if (link_sec_p)
4743 *link_sec_p = link_sec;
b38cadfb 4744
daa4adae 4745 return *stub_sec_p;
48229727
JB		 4746}
4747
4748/* Add a new stub entry to the stub hash. Not all fields of the new
4749 stub entry are initialised. */
4750
4751static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4752elf32_arm_add_stub (const char *stub_name, asection *section,
4753 struct elf32_arm_link_hash_table *htab,
4754 enum elf32_arm_stub_type stub_type)
48229727
JB		 4755{
4756 asection *link_sec;
4757 asection *stub_sec;
4758 struct elf32_arm_stub_hash_entry *stub_entry;
4759
daa4adae
TP		 4760 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4761 stub_type);
48229727
JB		 4762 if (stub_sec == NULL)
4763 return NULL;
906e58ca
NC		 4764
4765 /* Enter this entry into the linker stub hash table. */
4766 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4767 TRUE, FALSE);
4768 if (stub_entry == NULL)
4769 {
6bde4c52
TP		 4770 if (section == NULL)
4771 section = stub_sec;
871b3ab2 4772 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4773 section->owner, stub_name);
906e58ca
NC		 4774 return NULL;
4775 }
4776
4777 stub_entry->stub_sec = stub_sec;
0955507f 4778 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4779 stub_entry->id_sec = link_sec;
4780
906e58ca
NC		 4781 return stub_entry;
4782}
4783
4784/* Store an Arm insn into an output section not processed by
4785 elf32_arm_write_section. */
4786
4787static void
8029a119
NC		 4788put_arm_insn (struct elf32_arm_link_hash_table * htab,
4789 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4790{
4791 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4792 bfd_putl32 (val, ptr);
4793 else
4794 bfd_putb32 (val, ptr);
4795}
4796
4797/* Store a 16-bit Thumb insn into an output section not processed by
4798 elf32_arm_write_section. */
4799
4800static void
8029a119
NC		 4801put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4802 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4803{
4804 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4805 bfd_putl16 (val, ptr);
4806 else
4807 bfd_putb16 (val, ptr);
4808}
4809
a504d23a
LA		 4810/* Store a Thumb2 insn into an output section not processed by
4811 elf32_arm_write_section. */
4812
4813static void
4814put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4815 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4816{
4817 /* T2 instructions are 16-bit streamed. */
4818 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4819 {
4820 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4821 bfd_putl16 ((val & 0xffff), ptr + 2);
4822 }
4823 else
4824 {
4825 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4826 bfd_putb16 ((val & 0xffff), ptr + 2);
4827 }
4828}
4829
0855e32b
NS		 4830/* If it's possible to change R_TYPE to a more efficient access
4831 model, return the new reloc type. */
4832
4833static unsigned
b38cadfb 4834elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4835 struct elf_link_hash_entry *h)
4836{
4837 int is_local = (h == NULL);
4838
0e1862bb
L		 4839 if (bfd_link_pic (info)
4840 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4841 return r_type;
4842
b38cadfb 4843 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4844 switch (r_type)
4845 {
4846 case R_ARM_TLS_GOTDESC:
4847 case R_ARM_TLS_CALL:
4848 case R_ARM_THM_TLS_CALL:
4849 case R_ARM_TLS_DESCSEQ:
4850 case R_ARM_THM_TLS_DESCSEQ:
4851 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4852 }
4853
4854 return r_type;
4855}
4856
48229727
JB		 4857static bfd_reloc_status_type elf32_arm_final_link_relocate
4858 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4859 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4860 const char *, unsigned char, enum arm_st_branch_type,
4861 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4862
4563a860
JB		 4863static unsigned int
4864arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4865{
4866 switch (stub_type)
4867 {
4868 case arm_stub_a8_veneer_b_cond:
4869 case arm_stub_a8_veneer_b:
4870 case arm_stub_a8_veneer_bl:
4871 return 2;
4872
4873 case arm_stub_long_branch_any_any:
4874 case arm_stub_long_branch_v4t_arm_thumb:
4875 case arm_stub_long_branch_thumb_only:
80c135e5 4876 case arm_stub_long_branch_thumb2_only:
d5a67c02 4877 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4878 case arm_stub_long_branch_v4t_thumb_thumb:
4879 case arm_stub_long_branch_v4t_thumb_arm:
4880 case arm_stub_short_branch_v4t_thumb_arm:
4881 case arm_stub_long_branch_any_arm_pic:
4882 case arm_stub_long_branch_any_thumb_pic:
4883 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4884 case arm_stub_long_branch_v4t_arm_thumb_pic:
4885 case arm_stub_long_branch_v4t_thumb_arm_pic:
4886 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4887 case arm_stub_long_branch_any_tls_pic:
4888 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4889 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4890 case arm_stub_a8_veneer_blx:
4891 return 4;
b38cadfb 4892
7a89b94e
NC		 4893 case arm_stub_long_branch_arm_nacl:
4894 case arm_stub_long_branch_arm_nacl_pic:
4895 return 16;
4896
4563a860
JB		 4897 default:
4898 abort (); /* Should be unreachable. */
4899 }
4900}
4901
4f4faa4d
TP		 4902/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4903 veneering (TRUE) or have their own symbol (FALSE). */
4904
4905static bfd_boolean
4906arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4907{
4908 if (stub_type >= max_stub_type)
4909 abort (); /* Should be unreachable. */
4910
4ba2ef8f
TP		 4911 switch (stub_type)
4912 {
4913 case arm_stub_cmse_branch_thumb_only:
4914 return TRUE;
4915
4916 default:
4917 return FALSE;
4918 }
4919
4920 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4921}
4922
d7c5bd02
TP		 4923/* Returns the padding needed for the dedicated section used stubs of type
4924 STUB_TYPE. */
4925
4926static int
4927arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4928{
4929 if (stub_type >= max_stub_type)
4930 abort (); /* Should be unreachable. */
4931
4ba2ef8f
TP		 4932 switch (stub_type)
4933 {
4934 case arm_stub_cmse_branch_thumb_only:
4935 return 32;
4936
4937 default:
4938 return 0;
4939 }
4940
4941 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4942}
4943
0955507f
TP		 4944/* If veneers of type STUB_TYPE should go in a dedicated output section,
4945 returns the address of the hash table field in HTAB holding the offset at
4946 which new veneers should be layed out in the stub section. */
4947
4948static bfd_vma*
4949arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4950 enum elf32_arm_stub_type stub_type)
4951{
4952 switch (stub_type)
4953 {
4954 case arm_stub_cmse_branch_thumb_only:
4955 return &htab->new_cmse_stub_offset;
4956
4957 default:
4958 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4959 return NULL;
4960 }
4961}
4962
906e58ca
NC		 4963static bfd_boolean
4964arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4965 void * in_arg)
4966{
7a89b94e 4967#define MAXRELOCS 3
0955507f 4968 bfd_boolean removed_sg_veneer;
906e58ca 4969 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4970 struct elf32_arm_link_hash_table *globals;
906e58ca 4971 struct bfd_link_info *info;
906e58ca
NC		 4972 asection *stub_sec;
4973 bfd *stub_bfd;
906e58ca
NC		 4974 bfd_byte *loc;
4975 bfd_vma sym_value;
4976 int template_size;
4977 int size;
d3ce72d0 4978 const insn_sequence *template_sequence;
906e58ca 4979 int i;
48229727
JB		 4980 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4981 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4982 int nrelocs = 0;
0955507f 4983 int just_allocated = 0;
906e58ca
NC		 4984
4985 /* Massage our args to the form they really have. */
4986 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4987 info = (struct bfd_link_info *) in_arg;
4988
4989 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4990 if (globals == NULL)
4991 return FALSE;
906e58ca 4992
906e58ca
NC		 4993 stub_sec = stub_entry->stub_sec;
4994
4dfe6ac6 4995 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4996 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4997 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4998 return TRUE;
fe33d2fa 4999
0955507f
TP		 5000 /* Assign a slot at the end of section if none assigned yet. */
5001 if (stub_entry->stub_offset == (bfd_vma) -1)
5002 {
5003 stub_entry->stub_offset = stub_sec->size;
5004 just_allocated = 1;
5005 }
906e58ca
NC		 5006 loc = stub_sec->contents + stub_entry->stub_offset;
5007
5008 stub_bfd = stub_sec->owner;
5009
906e58ca
NC		 5010 /* This is the address of the stub destination. */
5011 sym_value = (stub_entry->target_value
5012 + stub_entry->target_section->output_offset
5013 + stub_entry->target_section->output_section->vma);
5014
d3ce72d0 5015 template_sequence = stub_entry->stub_template;
461a49ca 5016 template_size = stub_entry->stub_template_size;
906e58ca
NC		 5017
5018 size = 0;
461a49ca 5019 for (i = 0; i < template_size; i++)
906e58ca 5020 {
d3ce72d0 5021 switch (template_sequence[i].type)
461a49ca
DJ		 5022 {
5023 case THUMB16_TYPE:
48229727 5024 {
d3ce72d0
NC		 5025 bfd_vma data = (bfd_vma) template_sequence[i].data;
5026 if (template_sequence[i].reloc_addend != 0)
48229727 5027 {
99059e56
RM		 5028 /* We've borrowed the reloc_addend field to mean we should
5029 insert a condition code into this (Thumb-1 branch)
5030 instruction. See THUMB16_BCOND_INSN. */
5031 BFD_ASSERT ((data & 0xff00) == 0xd000);
5032 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 5033 }
fe33d2fa 5034 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 5035 size += 2;
5036 }
461a49ca 5037 break;
906e58ca 5038
48229727 5039 case THUMB32_TYPE:
fe33d2fa
CL		 5040 bfd_put_16 (stub_bfd,
5041 (template_sequence[i].data >> 16) & 0xffff,
5042 loc + size);
5043 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5044 loc + size + 2);
99059e56
RM		 5045 if (template_sequence[i].r_type != R_ARM_NONE)
5046 {
5047 stub_reloc_idx[nrelocs] = i;
5048 stub_reloc_offset[nrelocs++] = size;
5049 }
5050 size += 4;
5051 break;
48229727 5052
461a49ca 5053 case ARM_TYPE:
fe33d2fa
CL		 5054 bfd_put_32 (stub_bfd, template_sequence[i].data,
5055 loc + size);
461a49ca
DJ		 5056 /* Handle cases where the target is encoded within the
5057 instruction. */
d3ce72d0 5058 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 5059 {
48229727
JB		 5060 stub_reloc_idx[nrelocs] = i;
5061 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5062 }
5063 size += 4;
5064 break;
5065
5066 case DATA_TYPE:
d3ce72d0 5067 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 5068 stub_reloc_idx[nrelocs] = i;
5069 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5070 size += 4;
5071 break;
5072
5073 default:
5074 BFD_FAIL ();
5075 return FALSE;
5076 }
906e58ca 5077 }
461a49ca 5078
0955507f
TP		 5079 if (just_allocated)
5080 stub_sec->size += size;
906e58ca 5081
461a49ca
DJ		 5082 /* Stub size has already been computed in arm_size_one_stub. Check
5083 consistency. */
5084 BFD_ASSERT (size == stub_entry->stub_size);
5085
906e58ca 5086 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 5087 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 5088 sym_value |= 1;
5089
0955507f
TP		 5090 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5091 to relocate in each stub. */
5092 removed_sg_veneer =
5093 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5094 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 5095
48229727 5096 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 5097 {
5098 Elf_Internal_Rela rel;
5099 bfd_boolean unresolved_reloc;
5100 char *error_message;
5101 bfd_vma points_to =
5102 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5103
5104 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5105 rel.r_info = ELF32_R_INFO (0,
5106 template_sequence[stub_reloc_idx[i]].r_type);
5107 rel.r_addend = 0;
5108
5109 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5110 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5111 template should refer back to the instruction after the original
5112 branch. We use target_section as Cortex-A8 erratum workaround stubs
5113 are only generated when both source and target are in the same
5114 section. */
5115 points_to = stub_entry->target_section->output_section->vma
5116 + stub_entry->target_section->output_offset
5117 + stub_entry->source_value;
5118
5119 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5120 (template_sequence[stub_reloc_idx[i]].r_type),
5121 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5122 points_to, info, stub_entry->target_section, "", STT_FUNC,
5123 stub_entry->branch_type,
5124 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5125 &error_message);
5126 }
906e58ca
NC		 5127
5128 return TRUE;
48229727 5129#undef MAXRELOCS
906e58ca
NC		 5130}
5131
48229727
JB		 5132/* Calculate the template, template size and instruction size for a stub.
5133 Return value is the instruction size. */
906e58ca 5134
48229727
JB		 5135static unsigned int
5136find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5137 const insn_sequence **stub_template,
5138 int *stub_template_size)
906e58ca 5139{
d3ce72d0 5140 const insn_sequence *template_sequence = NULL;
48229727
JB		 5141 int template_size = 0, i;
5142 unsigned int size;
906e58ca 5143
d3ce72d0 5144 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 5145 if (stub_template)
5146 *stub_template = template_sequence;
5147
48229727 5148 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 5149 if (stub_template_size)
5150 *stub_template_size = template_size;
906e58ca
NC		 5151
5152 size = 0;
461a49ca
DJ		 5153 for (i = 0; i < template_size; i++)
5154 {
d3ce72d0 5155 switch (template_sequence[i].type)
461a49ca
DJ		 5156 {
5157 case THUMB16_TYPE:
5158 size += 2;
5159 break;
5160
5161 case ARM_TYPE:
48229727 5162 case THUMB32_TYPE:
461a49ca
DJ		 5163 case DATA_TYPE:
5164 size += 4;
5165 break;
5166
5167 default:
5168 BFD_FAIL ();
2a229407 5169 return 0;
461a49ca
DJ		 5170 }
5171 }
5172
48229727
JB		 5173 return size;
5174}
5175
5176/* As above, but don't actually build the stub. Just bump offset so
5177 we know stub section sizes. */
5178
5179static bfd_boolean
5180arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 5181 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 5182{
5183 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 5184 const insn_sequence *template_sequence;
48229727
JB		 5185 int template_size, size;
5186
5187 /* Massage our args to the form they really have. */
5188 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 5189
5190 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
5191 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
5192
d3ce72d0 5193 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 5194 &template_size);
5195
0955507f
TP		 5196 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5197 if (stub_entry->stub_template_size)
5198 {
5199 stub_entry->stub_size = size;
5200 stub_entry->stub_template = template_sequence;
5201 stub_entry->stub_template_size = template_size;
5202 }
5203
5204 /* Already accounted for. */
5205 if (stub_entry->stub_offset != (bfd_vma) -1)
5206 return TRUE;
461a49ca 5207
906e58ca
NC		 5208 size = (size + 7) & ~7;
5209 stub_entry->stub_sec->size += size;
461a49ca 5210
906e58ca
NC		 5211 return TRUE;
5212}
5213
5214/* External entry points for sizing and building linker stubs. */
5215
5216/* Set up various things so that we can make a list of input sections
5217 for each output section included in the link. Returns -1 on error,
5218 0 when no stubs will be needed, and 1 on success. */
5219
5220int
5221elf32_arm_setup_section_lists (bfd *output_bfd,
5222 struct bfd_link_info *info)
5223{
5224 bfd *input_bfd;
5225 unsigned int bfd_count;
7292b3ac 5226 unsigned int top_id, top_index;
906e58ca
NC		 5227 asection *section;
5228 asection **input_list, **list;
5229 bfd_size_type amt;
5230 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5231
4dfe6ac6
NC		 5232 if (htab == NULL)
5233 return 0;
906e58ca
NC		 5234 if (! is_elf_hash_table (htab))
5235 return 0;
5236
5237 /* Count the number of input BFDs and find the top input section id. */
5238 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5239 input_bfd != NULL;
c72f2fb2 5240 input_bfd = input_bfd->link.next)
906e58ca
NC		 5241 {
5242 bfd_count += 1;
5243 for (section = input_bfd->sections;
5244 section != NULL;
5245 section = section->next)
5246 {
5247 if (top_id < section->id)
5248 top_id = section->id;
5249 }
5250 }
5251 htab->bfd_count = bfd_count;
5252
5253 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5254 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5255 if (htab->stub_group == NULL)
5256 return -1;
fe33d2fa 5257 htab->top_id = top_id;
906e58ca
NC		 5258
5259 /* We can't use output_bfd->section_count here to find the top output
5260 section index as some sections may have been removed, and
5261 _bfd_strip_section_from_output doesn't renumber the indices. */
5262 for (section = output_bfd->sections, top_index = 0;
5263 section != NULL;
5264 section = section->next)
5265 {
5266 if (top_index < section->index)
5267 top_index = section->index;
5268 }
5269
5270 htab->top_index = top_index;
5271 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5272 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5273 htab->input_list = input_list;
5274 if (input_list == NULL)
5275 return -1;
5276
5277 /* For sections we aren't interested in, mark their entries with a
5278 value we can check later. */
5279 list = input_list + top_index;
5280 do
5281 *list = bfd_abs_section_ptr;
5282 while (list-- != input_list);
5283
5284 for (section = output_bfd->sections;
5285 section != NULL;
5286 section = section->next)
5287 {
5288 if ((section->flags & SEC_CODE) != 0)
5289 input_list[section->index] = NULL;
5290 }
5291
5292 return 1;
5293}
5294
5295/* The linker repeatedly calls this function for each input section,
5296 in the order that input sections are linked into output sections.
5297 Build lists of input sections to determine groupings between which
5298 we may insert linker stubs. */
5299
5300void
5301elf32_arm_next_input_section (struct bfd_link_info *info,
5302 asection *isec)
5303{
5304 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5305
4dfe6ac6
NC		 5306 if (htab == NULL)
5307 return;
5308
906e58ca
NC		 5309 if (isec->output_section->index <= htab->top_index)
5310 {
5311 asection **list = htab->input_list + isec->output_section->index;
5312
a7470592 5313 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5314 {
5315 /* Steal the link_sec pointer for our list. */
5316#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5317 /* This happens to make the list in reverse order,
07d72278 5318 which we reverse later. */
906e58ca
NC		 5319 PREV_SEC (isec) = *list;
5320 *list = isec;
5321 }
5322 }
5323}
5324
5325/* See whether we can group stub sections together. Grouping stub
5326 sections may result in fewer stubs. More importantly, we need to
07d72278 5327 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5328 .fini output sections respectively, because glibc splits the
5329 _init and _fini functions into multiple parts. Putting a stub in
5330 the middle of a function is not a good idea. */
5331
5332static void
5333group_sections (struct elf32_arm_link_hash_table *htab,
5334 bfd_size_type stub_group_size,
07d72278 5335 bfd_boolean stubs_always_after_branch)
906e58ca 5336{
07d72278 5337 asection **list = htab->input_list;
906e58ca
NC		 5338
5339 do
5340 {
5341 asection *tail = *list;
07d72278 5342 asection *head;
906e58ca
NC		 5343
5344 if (tail == bfd_abs_section_ptr)
5345 continue;
5346
07d72278
DJ		 5347 /* Reverse the list: we must avoid placing stubs at the
5348 beginning of the section because the beginning of the text
5349 section may be required for an interrupt vector in bare metal
5350 code. */
5351#define NEXT_SEC PREV_SEC
e780aef2
CL		 5352 head = NULL;
5353 while (tail != NULL)
99059e56
RM		 5354 {
5355 /* Pop from tail. */
5356 asection *item = tail;
5357 tail = PREV_SEC (item);
e780aef2 5358
99059e56
RM		 5359 /* Push on head. */
5360 NEXT_SEC (item) = head;
5361 head = item;
5362 }
07d72278
DJ		 5363
5364 while (head != NULL)
906e58ca
NC		 5365 {
5366 asection *curr;
07d72278 5367 asection *next;
e780aef2
CL		 5368 bfd_vma stub_group_start = head->output_offset;
5369 bfd_vma end_of_next;
906e58ca 5370
07d72278 5371 curr = head;
e780aef2 5372 while (NEXT_SEC (curr) != NULL)
8cd931b7 5373 {
e780aef2
CL		 5374 next = NEXT_SEC (curr);
5375 end_of_next = next->output_offset + next->size;
5376 if (end_of_next - stub_group_start >= stub_group_size)
5377 /* End of NEXT is too far from start, so stop. */
8cd931b7 5378 break;
e780aef2
CL		 5379 /* Add NEXT to the group. */
5380 curr = next;
8cd931b7 5381 }
906e58ca 5382
07d72278 5383 /* OK, the size from the start to the start of CURR is less
906e58ca 5384 than stub_group_size and thus can be handled by one stub
07d72278 5385 section. (Or the head section is itself larger than
906e58ca
NC		 5386 stub_group_size, in which case we may be toast.)
5387 We should really be keeping track of the total size of
5388 stubs added here, as stubs contribute to the final output
7fb9f789 5389 section size. */
906e58ca
NC		 5390 do
5391 {
07d72278 5392 next = NEXT_SEC (head);
906e58ca 5393 /* Set up this stub group. */
07d72278 5394 htab->stub_group[head->id].link_sec = curr;
906e58ca 5395 }
07d72278 5396 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5397
5398 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5399 bytes after the stub section can be handled by it too. */
5400 if (!stubs_always_after_branch)
906e58ca 5401 {
e780aef2
CL		 5402 stub_group_start = curr->output_offset + curr->size;
5403
8cd931b7 5404 while (next != NULL)
906e58ca 5405 {
e780aef2
CL		 5406 end_of_next = next->output_offset + next->size;
5407 if (end_of_next - stub_group_start >= stub_group_size)
5408 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5409 break;
e780aef2 5410 /* Add NEXT to the stub group. */
07d72278
DJ		 5411 head = next;
5412 next = NEXT_SEC (head);
5413 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5414 }
5415 }
07d72278 5416 head = next;
906e58ca
NC		 5417 }
5418 }
07d72278 5419 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5420
5421 free (htab->input_list);
5422#undef PREV_SEC
07d72278 5423#undef NEXT_SEC
906e58ca
NC		 5424}
5425
48229727
JB		 5426/* Comparison function for sorting/searching relocations relating to Cortex-A8
5427 erratum fix. */
5428
5429static int
5430a8_reloc_compare (const void *a, const void *b)
5431{
21d799b5
NC		 5432 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5433 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5434
5435 if (ra->from < rb->from)
5436 return -1;
5437 else if (ra->from > rb->from)
5438 return 1;
5439 else
5440 return 0;
5441}
5442
5443static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5444 const char *, char **);
5445
5446/* Helper function to scan code for sequences which might trigger the Cortex-A8
5447 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5448 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5449 otherwise. */
5450
81694485
NC		 5451static bfd_boolean
5452cortex_a8_erratum_scan (bfd *input_bfd,
5453 struct bfd_link_info *info,
48229727
JB		 5454 struct a8_erratum_fix **a8_fixes_p,
5455 unsigned int *num_a8_fixes_p,
5456 unsigned int *a8_fix_table_size_p,
5457 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5458 unsigned int num_a8_relocs,
5459 unsigned prev_num_a8_fixes,
5460 bfd_boolean *stub_changed_p)
48229727
JB		 5461{
5462 asection *section;
5463 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5464 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5465 unsigned int num_a8_fixes = *num_a8_fixes_p;
5466 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5467
4dfe6ac6
NC		 5468 if (htab == NULL)
5469 return FALSE;
5470
48229727
JB		 5471 for (section = input_bfd->sections;
5472 section != NULL;
5473 section = section->next)
5474 {
5475 bfd_byte *contents = NULL;
5476 struct _arm_elf_section_data *sec_data;
5477 unsigned int span;
5478 bfd_vma base_vma;
5479
5480 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5481 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5482 || (section->flags & SEC_EXCLUDE) != 0
5483 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5484 || (section->output_section == bfd_abs_section_ptr))
5485 continue;
48229727
JB		 5486
5487 base_vma = section->output_section->vma + section->output_offset;
5488
5489 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5490 contents = elf_section_data (section)->this_hdr.contents;
48229727 5491 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5492 return TRUE;
48229727
JB		 5493
5494 sec_data = elf32_arm_section_data (section);
5495
5496 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5497 {
5498 unsigned int span_start = sec_data->map[span].vma;
5499 unsigned int span_end = (span == sec_data->mapcount - 1)
5500 ? section->size : sec_data->map[span + 1].vma;
5501 unsigned int i;
5502 char span_type = sec_data->map[span].type;
5503 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5504
5505 if (span_type != 't')
5506 continue;
5507
5508 /* Span is entirely within a single 4KB region: skip scanning. */
5509 if (((base_vma + span_start) & ~0xfff)
48229727 5510 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5511 continue;
5512
5513 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5514
5515 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5516 * The branch target is in the same 4KB region as the
5517 first half of the branch.
5518 * The instruction before the branch is a 32-bit
5519 length non-branch instruction. */
5520 for (i = span_start; i < span_end;)
5521 {
5522 unsigned int insn = bfd_getl16 (&contents[i]);
5523 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5524 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5525
99059e56
RM		 5526 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5527 insn_32bit = TRUE;
48229727
JB		 5528
5529 if (insn_32bit)
99059e56
RM		 5530 {
5531 /* Load the rest of the insn (in manual-friendly order). */
5532 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5533
5534 /* Encoding T4: B<c>.W. */
5535 is_b = (insn & 0xf800d000) == 0xf0009000;
5536 /* Encoding T1: BL<c>.W. */
5537 is_bl = (insn & 0xf800d000) == 0xf000d000;
5538 /* Encoding T2: BLX<c>.W. */
5539 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5540 /* Encoding T3: B<c>.W (not permitted in IT block). */
5541 is_bcc = (insn & 0xf800d000) == 0xf0008000
5542 && (insn & 0x07f00000) != 0x03800000;
5543 }
5544
5545 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5546
99059e56 5547 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5548 && insn_32bit
5549 && is_32bit_branch
5550 && last_was_32bit
5551 && ! last_was_branch)
99059e56
RM		 5552 {
5553 bfd_signed_vma offset = 0;
5554 bfd_boolean force_target_arm = FALSE;
48229727 5555 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5556 bfd_vma target;
5557 enum elf32_arm_stub_type stub_type = arm_stub_none;
5558 struct a8_erratum_reloc key, *found;
5559 bfd_boolean use_plt = FALSE;
48229727 5560
99059e56
RM		 5561 key.from = base_vma + i;
5562 found = (struct a8_erratum_reloc *)
5563 bsearch (&key, a8_relocs, num_a8_relocs,
5564 sizeof (struct a8_erratum_reloc),
5565 &a8_reloc_compare);
48229727
JB		 5566
5567 if (found)
5568 {
5569 char *error_message = NULL;
5570 struct elf_link_hash_entry *entry;
5571
5572 /* We don't care about the error returned from this
99059e56 5573 function, only if there is glue or not. */
48229727
JB		 5574 entry = find_thumb_glue (info, found->sym_name,
5575 &error_message);
5576
5577 if (entry)
5578 found->non_a8_stub = TRUE;
5579
92750f34 5580 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5581 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5582 && found->hash->root.plt.offset != (bfd_vma) -1)
5583 use_plt = TRUE;
5584
5585 if (found->r_type == R_ARM_THM_CALL)
5586 {
35fc36a8
RS		 5587 if (found->branch_type == ST_BRANCH_TO_ARM
5588 || use_plt)
92750f34
DJ		 5589 force_target_arm = TRUE;
5590 else
5591 force_target_thumb = TRUE;
5592 }
48229727
JB		 5593 }
5594
99059e56 5595 /* Check if we have an offending branch instruction. */
48229727
JB		 5596
5597 if (found && found->non_a8_stub)
5598 /* We've already made a stub for this instruction, e.g.
5599 it's a long branch or a Thumb->ARM stub. Assume that
5600 stub will suffice to work around the A8 erratum (see
5601 setting of always_after_branch above). */
5602 ;
99059e56
RM		 5603 else if (is_bcc)
5604 {
5605 offset = (insn & 0x7ff) << 1;
5606 offset |= (insn & 0x3f0000) >> 4;
5607 offset |= (insn & 0x2000) ? 0x40000 : 0;
5608 offset |= (insn & 0x800) ? 0x80000 : 0;
5609 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5610 if (offset & 0x100000)
5611 offset |= ~ ((bfd_signed_vma) 0xfffff);
5612 stub_type = arm_stub_a8_veneer_b_cond;
5613 }
5614 else if (is_b || is_bl || is_blx)
5615 {
5616 int s = (insn & 0x4000000) != 0;
5617 int j1 = (insn & 0x2000) != 0;
5618 int j2 = (insn & 0x800) != 0;
5619 int i1 = !(j1 ^ s);
5620 int i2 = !(j2 ^ s);
5621
5622 offset = (insn & 0x7ff) << 1;
5623 offset |= (insn & 0x3ff0000) >> 4;
5624 offset |= i2 << 22;
5625 offset |= i1 << 23;
5626 offset |= s << 24;
5627 if (offset & 0x1000000)
5628 offset |= ~ ((bfd_signed_vma) 0xffffff);
5629
5630 if (is_blx)
5631 offset &= ~ ((bfd_signed_vma) 3);
5632
5633 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5634 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5635 }
5636
5637 if (stub_type != arm_stub_none)
5638 {
5639 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5640
5641 /* The original instruction is a BL, but the target is
99059e56 5642 an ARM instruction. If we were not making a stub,
48229727
JB		 5643 the BL would have been converted to a BLX. Use the
5644 BLX stub instead in that case. */
5645 if (htab->use_blx && force_target_arm
5646 && stub_type == arm_stub_a8_veneer_bl)
5647 {
5648 stub_type = arm_stub_a8_veneer_blx;
5649 is_blx = TRUE;
5650 is_bl = FALSE;
5651 }
5652 /* Conversely, if the original instruction was
5653 BLX but the target is Thumb mode, use the BL
5654 stub. */
5655 else if (force_target_thumb
5656 && stub_type == arm_stub_a8_veneer_blx)
5657 {
5658 stub_type = arm_stub_a8_veneer_bl;
5659 is_blx = FALSE;
5660 is_bl = TRUE;
5661 }
5662
99059e56
RM		 5663 if (is_blx)
5664 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5665
99059e56
RM		 5666 /* If we found a relocation, use the proper destination,
5667 not the offset in the (unrelocated) instruction.
48229727
JB		 5668 Note this is always done if we switched the stub type
5669 above. */
99059e56
RM		 5670 if (found)
5671 offset =
81694485 5672 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5673
99059e56
RM		 5674 /* If the stub will use a Thumb-mode branch to a
5675 PLT target, redirect it to the preceding Thumb
5676 entry point. */
5677 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5678 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5679
99059e56 5680 target = pc_for_insn + offset;
48229727 5681
99059e56
RM		 5682 /* The BLX stub is ARM-mode code. Adjust the offset to
5683 take the different PC value (+8 instead of +4) into
48229727 5684 account. */
99059e56
RM		 5685 if (stub_type == arm_stub_a8_veneer_blx)
5686 offset += 4;
5687
5688 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5689 {
5690 char *stub_name = NULL;
5691
5692 if (num_a8_fixes == a8_fix_table_size)
5693 {
5694 a8_fix_table_size *= 2;
5695 a8_fixes = (struct a8_erratum_fix *)
5696 bfd_realloc (a8_fixes,
5697 sizeof (struct a8_erratum_fix)
5698 * a8_fix_table_size);
5699 }
48229727 5700
eb7c4339
NS		 5701 if (num_a8_fixes < prev_num_a8_fixes)
5702 {
5703 /* If we're doing a subsequent scan,
5704 check if we've found the same fix as
5705 before, and try and reuse the stub
5706 name. */
5707 stub_name = a8_fixes[num_a8_fixes].stub_name;
5708 if ((a8_fixes[num_a8_fixes].section != section)
5709 || (a8_fixes[num_a8_fixes].offset != i))
5710 {
5711 free (stub_name);
5712 stub_name = NULL;
5713 *stub_changed_p = TRUE;
5714 }
5715 }
5716
5717 if (!stub_name)
5718 {
21d799b5 5719 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5720 if (stub_name != NULL)
5721 sprintf (stub_name, "%x:%x", section->id, i);
5722 }
48229727 5723
99059e56
RM		 5724 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5725 a8_fixes[num_a8_fixes].section = section;
5726 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5727 a8_fixes[num_a8_fixes].target_offset =
5728 target - base_vma;
99059e56
RM		 5729 a8_fixes[num_a8_fixes].orig_insn = insn;
5730 a8_fixes[num_a8_fixes].stub_name = stub_name;
5731 a8_fixes[num_a8_fixes].stub_type = stub_type;
5732 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5733 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5734
99059e56
RM		 5735 num_a8_fixes++;
5736 }
5737 }
5738 }
48229727 5739
99059e56
RM		 5740 i += insn_32bit ? 4 : 2;
5741 last_was_32bit = insn_32bit;
48229727 5742 last_was_branch = is_32bit_branch;
99059e56
RM		 5743 }
5744 }
48229727
JB		 5745
5746 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5747 free (contents);
48229727 5748 }
fe33d2fa 5749
48229727
JB		 5750 *a8_fixes_p = a8_fixes;
5751 *num_a8_fixes_p = num_a8_fixes;
5752 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5753
81694485 5754 return FALSE;
48229727
JB		 5755}
5756
b715f643
TP		 5757/* Create or update a stub entry depending on whether the stub can already be
5758 found in HTAB. The stub is identified by:
5759 - its type STUB_TYPE
5760 - its source branch (note that several can share the same stub) whose
5761 section and relocation (if any) are given by SECTION and IRELA
5762 respectively
5763 - its target symbol whose input section, hash, name, value and branch type
5764 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5765 respectively
5766
5767 If found, the value of the stub's target symbol is updated from SYM_VALUE
5768 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5769 TRUE and the stub entry is initialized.
5770
0955507f
TP		 5771 Returns the stub that was created or updated, or NULL if an error
5772 occurred. */
b715f643 5773
0955507f 5774static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5775elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5776 enum elf32_arm_stub_type stub_type, asection *section,
5777 Elf_Internal_Rela *irela, asection *sym_sec,
5778 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5779 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5780 bfd_boolean *new_stub)
5781{
5782 const asection *id_sec;
5783 char *stub_name;
5784 struct elf32_arm_stub_hash_entry *stub_entry;
5785 unsigned int r_type;
4f4faa4d 5786 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5787
5788 BFD_ASSERT (stub_type != arm_stub_none);
5789 *new_stub = FALSE;
5790
4f4faa4d
TP		 5791 if (sym_claimed)
5792 stub_name = sym_name;
5793 else
5794 {
5795 BFD_ASSERT (irela);
5796 BFD_ASSERT (section);
c2abbbeb 5797 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5798
4f4faa4d
TP		 5799 /* Support for grouping stub sections. */
5800 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5801
4f4faa4d
TP		 5802 /* Get the name of this stub. */
5803 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5804 stub_type);
5805 if (!stub_name)
0955507f 5806 return NULL;
4f4faa4d 5807 }
b715f643
TP		 5808
5809 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5810 FALSE);
5811 /* The proper stub has already been created, just update its value. */
5812 if (stub_entry != NULL)
5813 {
4f4faa4d
TP		 5814 if (!sym_claimed)
5815 free (stub_name);
b715f643 5816 stub_entry->target_value = sym_value;
0955507f 5817 return stub_entry;
b715f643
TP		 5818 }
5819
daa4adae 5820 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5821 if (stub_entry == NULL)
5822 {
4f4faa4d
TP		 5823 if (!sym_claimed)
5824 free (stub_name);
0955507f 5825 return NULL;
b715f643
TP		 5826 }
5827
5828 stub_entry->target_value = sym_value;
5829 stub_entry->target_section = sym_sec;
5830 stub_entry->stub_type = stub_type;
5831 stub_entry->h = hash;
5832 stub_entry->branch_type = branch_type;
5833
4f4faa4d
TP		 5834 if (sym_claimed)
5835 stub_entry->output_name = sym_name;
5836 else
b715f643 5837 {
4f4faa4d
TP		 5838 if (sym_name == NULL)
5839 sym_name = "unnamed";
5840 stub_entry->output_name = (char *)
5841 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5842 + strlen (sym_name));
5843 if (stub_entry->output_name == NULL)
5844 {
5845 free (stub_name);
0955507f 5846 return NULL;
4f4faa4d 5847 }
b715f643 5848
4f4faa4d
TP		 5849 /* For historical reasons, use the existing names for ARM-to-Thumb and
5850 Thumb-to-ARM stubs. */
5851 r_type = ELF32_R_TYPE (irela->r_info);
5852 if ((r_type == (unsigned int) R_ARM_THM_CALL
5853 || r_type == (unsigned int) R_ARM_THM_JUMP24
5854 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5855 && branch_type == ST_BRANCH_TO_ARM)
5856 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5857 else if ((r_type == (unsigned int) R_ARM_CALL
5858 || r_type == (unsigned int) R_ARM_JUMP24)
5859 && branch_type == ST_BRANCH_TO_THUMB)
5860 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5861 else
5862 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5863 }
b715f643
TP		 5864
5865 *new_stub = TRUE;
0955507f 5866 return stub_entry;
b715f643
TP		 5867}
5868
4ba2ef8f
TP		 5869/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5870 gateway veneer to transition from non secure to secure state and create them
5871 accordingly.
5872
5873 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5874 defines the conditions that govern Secure Gateway veneer creation for a
5875 given symbol <SYM> as follows:
5876 - it has function type
5877 - it has non local binding
5878 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5879 same type, binding and value as <SYM> (called normal symbol).
5880 An entry function can handle secure state transition itself in which case
5881 its special symbol would have a different value from the normal symbol.
5882
5883 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5884 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5885 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5886 created.
4ba2ef8f 5887
0955507f 5888 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5889
5890static bfd_boolean
5891cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5892 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5893 int *cmse_stub_created)
4ba2ef8f
TP		 5894{
5895 const struct elf_backend_data *bed;
5896 Elf_Internal_Shdr *symtab_hdr;
5897 unsigned i, j, sym_count, ext_start;
5898 Elf_Internal_Sym *cmse_sym, *local_syms;
5899 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5900 enum arm_st_branch_type branch_type;
5901 char *sym_name, *lsym_name;
5902 bfd_vma sym_value;
5903 asection *section;
0955507f
TP		 5904 struct elf32_arm_stub_hash_entry *stub_entry;
5905 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5906
5907 bed = get_elf_backend_data (input_bfd);
5908 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5909 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5910 ext_start = symtab_hdr->sh_info;
5911 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5912 && out_attr[Tag_CPU_arch_profile].i == 'M');
5913
5914 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5915 if (local_syms == NULL)
5916 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5917 symtab_hdr->sh_info, 0, NULL, NULL,
5918 NULL);
5919 if (symtab_hdr->sh_info && local_syms == NULL)
5920 return FALSE;
5921
5922 /* Scan symbols. */
5923 for (i = 0; i < sym_count; i++)
5924 {
5925 cmse_invalid = FALSE;
5926
5927 if (i < ext_start)
5928 {
5929 cmse_sym = &local_syms[i];
5930 /* Not a special symbol. */
5931 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5932 continue;
5933 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5934 symtab_hdr->sh_link,
5935 cmse_sym->st_name);
5936 /* Special symbol with local binding. */
5937 cmse_invalid = TRUE;
5938 }
5939 else
5940 {
5941 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5942 sym_name = (char *) cmse_hash->root.root.root.string;
5943
5944 /* Not a special symbol. */
5945 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5946 continue;
5947
5948 /* Special symbol has incorrect binding or type. */
5949 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5950 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5951 || cmse_hash->root.type != STT_FUNC)
5952 cmse_invalid = TRUE;
5953 }
5954
5955 if (!is_v8m)
5956 {
90b6238f
AM		 5957 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
5958 "ARMv8-M architecture or later"),
4eca0228 5959 input_bfd, sym_name);
4ba2ef8f
TP		 5960 is_v8m = TRUE; /* Avoid multiple warning. */
5961 ret = FALSE;
5962 }
5963
5964 if (cmse_invalid)
5965 {
90b6238f
AM		 5966 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
5967 " a global or weak function symbol"),
4eca0228 5968 input_bfd, sym_name);
4ba2ef8f
TP		 5969 ret = FALSE;
5970 if (i < ext_start)
5971 continue;
5972 }
5973
5974 sym_name += strlen (CMSE_PREFIX);
5975 hash = (struct elf32_arm_link_hash_entry *)
5976 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5977
5978 /* No associated normal symbol or it is neither global nor weak. */
5979 if (!hash
5980 || (hash->root.root.type != bfd_link_hash_defined
5981 && hash->root.root.type != bfd_link_hash_defweak)
5982 || hash->root.type != STT_FUNC)
5983 {
5984 /* Initialize here to avoid warning about use of possibly
5985 uninitialized variable. */
5986 j = 0;
5987
5988 if (!hash)
5989 {
5990 /* Searching for a normal symbol with local binding. */
5991 for (; j < ext_start; j++)
5992 {
5993 lsym_name =
5994 bfd_elf_string_from_elf_section (input_bfd,
5995 symtab_hdr->sh_link,
5996 local_syms[j].st_name);
5997 if (!strcmp (sym_name, lsym_name))
5998 break;
5999 }
6000 }
6001
6002 if (hash || j < ext_start)
6003 {
4eca0228 6004 _bfd_error_handler
90b6238f
AM		 6005 (_("%pB: invalid standard symbol `%s'; it must be "
6006 "a global or weak function symbol"),
6007 input_bfd, sym_name);
4ba2ef8f
TP		 6008 }
6009 else
4eca0228 6010 _bfd_error_handler
90b6238f 6011 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 6012 ret = FALSE;
6013 if (!hash)
6014 continue;
6015 }
6016
6017 sym_value = hash->root.root.u.def.value;
6018 section = hash->root.root.u.def.section;
6019
6020 if (cmse_hash->root.root.u.def.section != section)
6021 {
4eca0228 6022 _bfd_error_handler
90b6238f 6023 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 6024 input_bfd, sym_name);
6025 ret = FALSE;
6026 }
6027 if (cmse_hash->root.root.u.def.value != sym_value)
6028 continue; /* Ignore: could be an entry function starting with SG. */
6029
6030 /* If this section is a link-once section that will be discarded, then
6031 don't create any stubs. */
6032 if (section->output_section == NULL)
6033 {
4eca0228 6034 _bfd_error_handler
90b6238f 6035 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 6036 continue;
6037 }
6038
6039 if (hash->root.size == 0)
6040 {
4eca0228 6041 _bfd_error_handler
90b6238f 6042 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 6043 ret = FALSE;
6044 }
6045
6046 if (!ret)
6047 continue;
6048 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 6049 stub_entry
4ba2ef8f
TP		 6050 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6051 NULL, NULL, section, hash, sym_name,
6052 sym_value, branch_type, &new_stub);
6053
0955507f 6054 if (stub_entry == NULL)
4ba2ef8f
TP		 6055 ret = FALSE;
6056 else
6057 {
6058 BFD_ASSERT (new_stub);
0955507f 6059 (*cmse_stub_created)++;
4ba2ef8f
TP		 6060 }
6061 }
6062
6063 if (!symtab_hdr->contents)
6064 free (local_syms);
6065 return ret;
6066}
6067
0955507f
TP		 6068/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6069 code entry function, ie can be called from non secure code without using a
6070 veneer. */
6071
6072static bfd_boolean
6073cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6074{
42484486 6075 bfd_byte contents[4];
0955507f
TP		 6076 uint32_t first_insn;
6077 asection *section;
6078 file_ptr offset;
6079 bfd *abfd;
6080
6081 /* Defined symbol of function type. */
6082 if (hash->root.root.type != bfd_link_hash_defined
6083 && hash->root.root.type != bfd_link_hash_defweak)
6084 return FALSE;
6085 if (hash->root.type != STT_FUNC)
6086 return FALSE;
6087
6088 /* Read first instruction. */
6089 section = hash->root.root.u.def.section;
6090 abfd = section->owner;
6091 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 6092 if (!bfd_get_section_contents (abfd, section, contents, offset,
6093 sizeof (contents)))
0955507f
TP		 6094 return FALSE;
6095
42484486
TP		 6096 first_insn = bfd_get_32 (abfd, contents);
6097
6098 /* Starts by SG instruction. */
0955507f
TP		 6099 return first_insn == 0xe97fe97f;
6100}
6101
6102/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6103 secure gateway veneers (ie. the veneers was not in the input import library)
6104 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6105
6106static bfd_boolean
6107arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6108{
6109 struct elf32_arm_stub_hash_entry *stub_entry;
6110 struct bfd_link_info *info;
6111
6112 /* Massage our args to the form they really have. */
6113 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6114 info = (struct bfd_link_info *) gen_info;
6115
6116 if (info->out_implib_bfd)
6117 return TRUE;
6118
6119 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6120 return TRUE;
6121
6122 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 6123 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 6124
6125 return TRUE;
6126}
6127
6128/* Set offset of each secure gateway veneers so that its address remain
6129 identical to the one in the input import library referred by
6130 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6131 (present in input import library but absent from the executable being
6132 linked) or if new veneers appeared and there is no output import library
6133 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6134 number of secure gateway veneers found in the input import library.
6135
6136 The function returns whether an error occurred. If no error occurred,
6137 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6138 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6139 veneer observed set for new veneers to be layed out after. */
6140
6141static bfd_boolean
6142set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6143 struct elf32_arm_link_hash_table *htab,
6144 int *cmse_stub_created)
6145{
6146 long symsize;
6147 char *sym_name;
6148 flagword flags;
6149 long i, symcount;
6150 bfd *in_implib_bfd;
6151 asection *stub_out_sec;
6152 bfd_boolean ret = TRUE;
6153 Elf_Internal_Sym *intsym;
6154 const char *out_sec_name;
6155 bfd_size_type cmse_stub_size;
6156 asymbol **sympp = NULL, *sym;
6157 struct elf32_arm_link_hash_entry *hash;
6158 const insn_sequence *cmse_stub_template;
6159 struct elf32_arm_stub_hash_entry *stub_entry;
6160 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6161 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6162 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6163
6164 /* No input secure gateway import library. */
6165 if (!htab->in_implib_bfd)
6166 return TRUE;
6167
6168 in_implib_bfd = htab->in_implib_bfd;
6169 if (!htab->cmse_implib)
6170 {
871b3ab2 6171 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 6172 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 6173 return FALSE;
6174 }
6175
6176 /* Get symbol table size. */
6177 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6178 if (symsize < 0)
6179 return FALSE;
6180
6181 /* Read in the input secure gateway import library's symbol table. */
6182 sympp = (asymbol **) xmalloc (symsize);
6183 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6184 if (symcount < 0)
6185 {
6186 ret = FALSE;
6187 goto free_sym_buf;
6188 }
6189
6190 htab->new_cmse_stub_offset = 0;
6191 cmse_stub_size =
6192 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6193 &cmse_stub_template,
6194 &cmse_stub_template_size);
6195 out_sec_name =
6196 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6197 stub_out_sec =
6198 bfd_get_section_by_name (htab->obfd, out_sec_name);
6199 if (stub_out_sec != NULL)
6200 cmse_stub_sec_vma = stub_out_sec->vma;
6201
6202 /* Set addresses of veneers mentionned in input secure gateway import
6203 library's symbol table. */
6204 for (i = 0; i < symcount; i++)
6205 {
6206 sym = sympp[i];
6207 flags = sym->flags;
6208 sym_name = (char *) bfd_asymbol_name (sym);
6209 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6210
6211 if (sym->section != bfd_abs_section_ptr
6212 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6213 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6214 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6215 != ST_BRANCH_TO_THUMB))
6216 {
90b6238f
AM		 6217 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6218 "symbol should be absolute, global and "
6219 "refer to Thumb functions"),
4eca0228 6220 in_implib_bfd, sym_name);
0955507f
TP		 6221 ret = FALSE;
6222 continue;
6223 }
6224
6225 veneer_value = bfd_asymbol_value (sym);
6226 stub_offset = veneer_value - cmse_stub_sec_vma;
6227 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6228 FALSE, FALSE);
6229 hash = (struct elf32_arm_link_hash_entry *)
6230 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6231
6232 /* Stub entry should have been created by cmse_scan or the symbol be of
6233 a secure function callable from non secure code. */
6234 if (!stub_entry && !hash)
6235 {
6236 bfd_boolean new_stub;
6237
4eca0228 6238 _bfd_error_handler
90b6238f 6239 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6240 hash = (struct elf32_arm_link_hash_entry *)
6241 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6242 stub_entry
6243 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6244 NULL, NULL, bfd_abs_section_ptr, hash,
6245 sym_name, veneer_value,
6246 ST_BRANCH_TO_THUMB, &new_stub);
6247 if (stub_entry == NULL)
6248 ret = FALSE;
6249 else
6250 {
6251 BFD_ASSERT (new_stub);
6252 new_cmse_stubs_created++;
6253 (*cmse_stub_created)++;
6254 }
6255 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6256 stub_entry->stub_offset = stub_offset;
6257 }
6258 /* Symbol found is not callable from non secure code. */
6259 else if (!stub_entry)
6260 {
6261 if (!cmse_entry_fct_p (hash))
6262 {
90b6238f 6263 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6264 sym_name);
0955507f
TP		 6265 ret = FALSE;
6266 }
6267 continue;
6268 }
6269 else
6270 {
6271 /* Only stubs for SG veneers should have been created. */
6272 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6273
6274 /* Check visibility hasn't changed. */
6275 if (!!(flags & BSF_GLOBAL)
6276 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6277 _bfd_error_handler
90b6238f 6278 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6279 sym_name);
6280
6281 stub_entry->stub_offset = stub_offset;
6282 }
6283
6284 /* Size should match that of a SG veneer. */
6285 if (intsym->st_size != cmse_stub_size)
6286 {
90b6238f 6287 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6288 in_implib_bfd, sym_name);
0955507f
TP		 6289 ret = FALSE;
6290 }
6291
6292 /* Previous veneer address is before current SG veneer section. */
6293 if (veneer_value < cmse_stub_sec_vma)
6294 {
6295 /* Avoid offset underflow. */
6296 if (stub_entry)
6297 stub_entry->stub_offset = 0;
6298 stub_offset = 0;
6299 ret = FALSE;
6300 }
6301
6302 /* Complain if stub offset not a multiple of stub size. */
6303 if (stub_offset % cmse_stub_size)
6304 {
4eca0228 6305 _bfd_error_handler
90b6238f
AM		 6306 (_("offset of veneer for entry function `%s' not a multiple of "
6307 "its size"), sym_name);
0955507f
TP		 6308 ret = FALSE;
6309 }
6310
6311 if (!ret)
6312 continue;
6313
6314 new_cmse_stubs_created--;
6315 if (veneer_value < cmse_stub_array_start)
6316 cmse_stub_array_start = veneer_value;
6317 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6318 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6319 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6320 }
6321
6322 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6323 {
6324 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6325 _bfd_error_handler
0955507f
TP		 6326 (_("new entry function(s) introduced but no output import library "
6327 "specified:"));
6328 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6329 }
6330
6331 if (cmse_stub_array_start != cmse_stub_sec_vma)
6332 {
4eca0228 6333 _bfd_error_handler
90b6238f 6334 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6335 out_sec_name);
6336 ret = FALSE;
6337 }
6338
6339free_sym_buf:
6340 free (sympp);
6341 return ret;
6342}
6343
906e58ca
NC		 6344/* Determine and set the size of the stub section for a final link.
6345
6346 The basic idea here is to examine all the relocations looking for
6347 PC-relative calls to a target that is unreachable with a "bl"
6348 instruction. */
6349
6350bfd_boolean
6351elf32_arm_size_stubs (bfd *output_bfd,
6352 bfd *stub_bfd,
6353 struct bfd_link_info *info,
6354 bfd_signed_vma group_size,
7a89b94e 6355 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6356 asection *,
7a89b94e 6357 unsigned int),
906e58ca
NC		 6358 void (*layout_sections_again) (void))
6359{
0955507f 6360 bfd_boolean ret = TRUE;
4ba2ef8f 6361 obj_attribute *out_attr;
0955507f 6362 int cmse_stub_created = 0;
906e58ca 6363 bfd_size_type stub_group_size;
4ba2ef8f 6364 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6365 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6366 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6367 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6368 struct a8_erratum_reloc *a8_relocs = NULL;
6369 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6370
4dfe6ac6
NC		 6371 if (htab == NULL)
6372 return FALSE;
6373
48229727
JB		 6374 if (htab->fix_cortex_a8)
6375 {
21d799b5 6376 a8_fixes = (struct a8_erratum_fix *)
99059e56 6377 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6378 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6379 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6380 }
906e58ca
NC		 6381
6382 /* Propagate mach to stub bfd, because it may not have been
6383 finalized when we created stub_bfd. */
6384 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6385 bfd_get_mach (output_bfd));
6386
6387 /* Stash our params away. */
6388 htab->stub_bfd = stub_bfd;
6389 htab->add_stub_section = add_stub_section;
6390 htab->layout_sections_again = layout_sections_again;
07d72278 6391 stubs_always_after_branch = group_size < 0;
48229727 6392
4ba2ef8f
TP		 6393 out_attr = elf_known_obj_attributes_proc (output_bfd);
6394 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6395
48229727
JB		 6396 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6397 as the first half of a 32-bit branch straddling two 4K pages. This is a
6398 crude way of enforcing that. */
6399 if (htab->fix_cortex_a8)
6400 stubs_always_after_branch = 1;
6401
906e58ca
NC		 6402 if (group_size < 0)
6403 stub_group_size = -group_size;
6404 else
6405 stub_group_size = group_size;
6406
6407 if (stub_group_size == 1)
6408 {
6409 /* Default values. */
6410 /* Thumb branch range is +-4MB has to be used as the default
6411 maximum size (a given section can contain both ARM and Thumb
6412 code, so the worst case has to be taken into account).
6413
6414 This value is 24K less than that, which allows for 2025
6415 12-byte stubs. If we exceed that, then we will fail to link.
6416 The user will have to relink with an explicit group size
6417 option. */
6418 stub_group_size = 4170000;
6419 }
6420
07d72278 6421 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6422
3ae046cc
NS		 6423 /* If we're applying the cortex A8 fix, we need to determine the
6424 program header size now, because we cannot change it later --
6425 that could alter section placements. Notice the A8 erratum fix
6426 ends up requiring the section addresses to remain unchanged
6427 modulo the page size. That's something we cannot represent
6428 inside BFD, and we don't want to force the section alignment to
6429 be the page size. */
6430 if (htab->fix_cortex_a8)
6431 (*htab->layout_sections_again) ();
6432
906e58ca
NC		 6433 while (1)
6434 {
6435 bfd *input_bfd;
6436 unsigned int bfd_indx;
6437 asection *stub_sec;
d7c5bd02 6438 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6439 bfd_boolean stub_changed = FALSE;
6440 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6441
48229727 6442 num_a8_fixes = 0;
906e58ca
NC		 6443 for (input_bfd = info->input_bfds, bfd_indx = 0;
6444 input_bfd != NULL;
c72f2fb2 6445 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6446 {
6447 Elf_Internal_Shdr *symtab_hdr;
6448 asection *section;
6449 Elf_Internal_Sym *local_syms = NULL;
6450
8c246a60
AM		 6451 if (!is_arm_elf (input_bfd)
6452 || (elf_dyn_lib_class (input_bfd) & DYN_AS_NEEDED) != 0)
99059e56 6453 continue;
adbcc655 6454
48229727
JB		 6455 num_a8_relocs = 0;
6456
906e58ca
NC		 6457 /* We'll need the symbol table in a second. */
6458 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6459 if (symtab_hdr->sh_info == 0)
6460 continue;
6461
4ba2ef8f
TP		 6462 /* Limit scan of symbols to object file whose profile is
6463 Microcontroller to not hinder performance in the general case. */
6464 if (m_profile && first_veneer_scan)
6465 {
6466 struct elf_link_hash_entry **sym_hashes;
6467
6468 sym_hashes = elf_sym_hashes (input_bfd);
6469 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6470 &cmse_stub_created))
4ba2ef8f 6471 goto error_ret_free_local;
0955507f
TP		 6472
6473 if (cmse_stub_created != 0)
6474 stub_changed = TRUE;
4ba2ef8f
TP		 6475 }
6476
906e58ca
NC		 6477 /* Walk over each section attached to the input bfd. */
6478 for (section = input_bfd->sections;
6479 section != NULL;
6480 section = section->next)
6481 {
6482 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6483
6484 /* If there aren't any relocs, then there's nothing more
6485 to do. */
6486 if ((section->flags & SEC_RELOC) == 0
6487 || section->reloc_count == 0
6488 || (section->flags & SEC_CODE) == 0)
6489 continue;
6490
6491 /* If this section is a link-once section that will be
6492 discarded, then don't create any stubs. */
6493 if (section->output_section == NULL
6494 || section->output_section->owner != output_bfd)
6495 continue;
6496
6497 /* Get the relocs. */
6498 internal_relocs
6499 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6500 NULL, info->keep_memory);
6501 if (internal_relocs == NULL)
6502 goto error_ret_free_local;
6503
6504 /* Now examine each relocation. */
6505 irela = internal_relocs;
6506 irelaend = irela + section->reloc_count;
6507 for (; irela < irelaend; irela++)
6508 {
6509 unsigned int r_type, r_indx;
906e58ca
NC		 6510 asection *sym_sec;
6511 bfd_vma sym_value;
6512 bfd_vma destination;
6513 struct elf32_arm_link_hash_entry *hash;
7413f23f 6514 const char *sym_name;
34e77a92 6515 unsigned char st_type;
35fc36a8 6516 enum arm_st_branch_type branch_type;
48229727 6517 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6518
6519 r_type = ELF32_R_TYPE (irela->r_info);
6520 r_indx = ELF32_R_SYM (irela->r_info);
6521
6522 if (r_type >= (unsigned int) R_ARM_max)
6523 {
6524 bfd_set_error (bfd_error_bad_value);
6525 error_ret_free_internal:
6526 if (elf_section_data (section)->relocs == NULL)
6527 free (internal_relocs);
15dd01b1
TP		 6528 /* Fall through. */
6529 error_ret_free_local:
6530 if (local_syms != NULL
6531 && (symtab_hdr->contents
6532 != (unsigned char *) local_syms))
6533 free (local_syms);
6534 return FALSE;
906e58ca 6535 }
b38cadfb 6536
0855e32b
NS		 6537 hash = NULL;
6538 if (r_indx >= symtab_hdr->sh_info)
6539 hash = elf32_arm_hash_entry
6540 (elf_sym_hashes (input_bfd)
6541 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6542
0855e32b
NS		 6543 /* Only look for stubs on branch instructions, or
6544 non-relaxed TLSCALL */
906e58ca 6545 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6546 && (r_type != (unsigned int) R_ARM_THM_CALL)
6547 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6548 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6549 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6550 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6551 && (r_type != (unsigned int) R_ARM_PLT32)
6552 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6553 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6554 && r_type == elf32_arm_tls_transition
6555 (info, r_type, &hash->root)
6556 && ((hash ? hash->tls_type
6557 : (elf32_arm_local_got_tls_type
6558 (input_bfd)[r_indx]))
6559 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6560 continue;
6561
6562 /* Now determine the call target, its name, value,
6563 section. */
6564 sym_sec = NULL;
6565 sym_value = 0;
6566 destination = 0;
7413f23f 6567 sym_name = NULL;
b38cadfb 6568
0855e32b
NS		 6569 if (r_type == (unsigned int) R_ARM_TLS_CALL
6570 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6571 {
6572 /* A non-relaxed TLS call. The target is the
6573 plt-resident trampoline and nothing to do
6574 with the symbol. */
6575 BFD_ASSERT (htab->tls_trampoline > 0);
6576 sym_sec = htab->root.splt;
6577 sym_value = htab->tls_trampoline;
6578 hash = 0;
34e77a92 6579 st_type = STT_FUNC;
35fc36a8 6580 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6581 }
6582 else if (!hash)
906e58ca
NC		 6583 {
6584 /* It's a local symbol. */
6585 Elf_Internal_Sym *sym;
906e58ca
NC		 6586
6587 if (local_syms == NULL)
6588 {
6589 local_syms
6590 = (Elf_Internal_Sym *) symtab_hdr->contents;
6591 if (local_syms == NULL)
6592 local_syms
6593 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6594 symtab_hdr->sh_info, 0,
6595 NULL, NULL, NULL);
6596 if (local_syms == NULL)
6597 goto error_ret_free_internal;
6598 }
6599
6600 sym = local_syms + r_indx;
f6d250ce
TS		 6601 if (sym->st_shndx == SHN_UNDEF)
6602 sym_sec = bfd_und_section_ptr;
6603 else if (sym->st_shndx == SHN_ABS)
6604 sym_sec = bfd_abs_section_ptr;
6605 else if (sym->st_shndx == SHN_COMMON)
6606 sym_sec = bfd_com_section_ptr;
6607 else
6608 sym_sec =
6609 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6610
ffcb4889
NS		 6611 if (!sym_sec)
6612 /* This is an undefined symbol. It can never
6a631e86 6613 be resolved. */
ffcb4889 6614 continue;
fe33d2fa 6615
906e58ca
NC		 6616 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6617 sym_value = sym->st_value;
6618 destination = (sym_value + irela->r_addend
6619 + sym_sec->output_offset
6620 + sym_sec->output_section->vma);
34e77a92 6621 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6622 branch_type =
6623 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6624 sym_name
6625 = bfd_elf_string_from_elf_section (input_bfd,
6626 symtab_hdr->sh_link,
6627 sym->st_name);
906e58ca
NC		 6628 }
6629 else
6630 {
6631 /* It's an external symbol. */
906e58ca
NC		 6632 while (hash->root.root.type == bfd_link_hash_indirect
6633 || hash->root.root.type == bfd_link_hash_warning)
6634 hash = ((struct elf32_arm_link_hash_entry *)
6635 hash->root.root.u.i.link);
6636
6637 if (hash->root.root.type == bfd_link_hash_defined
6638 || hash->root.root.type == bfd_link_hash_defweak)
6639 {
6640 sym_sec = hash->root.root.u.def.section;
6641 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6642
6643 struct elf32_arm_link_hash_table *globals =
6644 elf32_arm_hash_table (info);
6645
6646 /* For a destination in a shared library,
6647 use the PLT stub as target address to
6648 decide whether a branch stub is
6649 needed. */
4dfe6ac6 6650 if (globals != NULL
362d30a1 6651 && globals->root.splt != NULL
4dfe6ac6 6652 && hash != NULL
022f8312
CL		 6653 && hash->root.plt.offset != (bfd_vma) -1)
6654 {
362d30a1 6655 sym_sec = globals->root.splt;
022f8312
CL		 6656 sym_value = hash->root.plt.offset;
6657 if (sym_sec->output_section != NULL)
6658 destination = (sym_value
6659 + sym_sec->output_offset
6660 + sym_sec->output_section->vma);
6661 }
6662 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6663 destination = (sym_value + irela->r_addend
6664 + sym_sec->output_offset
6665 + sym_sec->output_section->vma);
6666 }
69c5861e
CL		 6667 else if ((hash->root.root.type == bfd_link_hash_undefined)
6668 || (hash->root.root.type == bfd_link_hash_undefweak))
6669 {
6670 /* For a shared library, use the PLT stub as
6671 target address to decide whether a long
6672 branch stub is needed.
6673 For absolute code, they cannot be handled. */
6674 struct elf32_arm_link_hash_table *globals =
6675 elf32_arm_hash_table (info);
6676
4dfe6ac6 6677 if (globals != NULL
362d30a1 6678 && globals->root.splt != NULL
4dfe6ac6 6679 && hash != NULL
69c5861e
CL		 6680 && hash->root.plt.offset != (bfd_vma) -1)
6681 {
362d30a1 6682 sym_sec = globals->root.splt;
69c5861e
CL		 6683 sym_value = hash->root.plt.offset;
6684 if (sym_sec->output_section != NULL)
6685 destination = (sym_value
6686 + sym_sec->output_offset
6687 + sym_sec->output_section->vma);
6688 }
6689 else
6690 continue;
6691 }
906e58ca
NC		 6692 else
6693 {
6694 bfd_set_error (bfd_error_bad_value);
6695 goto error_ret_free_internal;
6696 }
34e77a92 6697 st_type = hash->root.type;
39d911fc
TP		 6698 branch_type =
6699 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6700 sym_name = hash->root.root.root.string;
906e58ca
NC		 6701 }
6702
48229727 6703 do
7413f23f 6704 {
b715f643 6705 bfd_boolean new_stub;
0955507f 6706 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6707
48229727
JB		 6708 /* Determine what (if any) linker stub is needed. */
6709 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6710 st_type, &branch_type,
6711 hash, destination, sym_sec,
48229727
JB		 6712 input_bfd, sym_name);
6713 if (stub_type == arm_stub_none)
6714 break;
6715
48229727
JB		 6716 /* We've either created a stub for this reloc already,
6717 or we are about to. */
0955507f 6718 stub_entry =
b715f643
TP		 6719 elf32_arm_create_stub (htab, stub_type, section, irela,
6720 sym_sec, hash,
6721 (char *) sym_name, sym_value,
6722 branch_type, &new_stub);
7413f23f 6723
0955507f 6724 created_stub = stub_entry != NULL;
b715f643
TP		 6725 if (!created_stub)
6726 goto error_ret_free_internal;
6727 else if (!new_stub)
6728 break;
99059e56 6729 else
b715f643 6730 stub_changed = TRUE;
99059e56
RM		 6731 }
6732 while (0);
6733
6734 /* Look for relocations which might trigger Cortex-A8
6735 erratum. */
6736 if (htab->fix_cortex_a8
6737 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6738 || r_type == (unsigned int) R_ARM_THM_JUMP19
6739 || r_type == (unsigned int) R_ARM_THM_CALL
6740 || r_type == (unsigned int) R_ARM_THM_XPC22))
6741 {
6742 bfd_vma from = section->output_section->vma
6743 + section->output_offset
6744 + irela->r_offset;
6745
6746 if ((from & 0xfff) == 0xffe)
6747 {
6748 /* Found a candidate. Note we haven't checked the
6749 destination is within 4K here: if we do so (and
6750 don't create an entry in a8_relocs) we can't tell
6751 that a branch should have been relocated when
6752 scanning later. */
6753 if (num_a8_relocs == a8_reloc_table_size)
6754 {
6755 a8_reloc_table_size *= 2;
6756 a8_relocs = (struct a8_erratum_reloc *)
6757 bfd_realloc (a8_relocs,
6758 sizeof (struct a8_erratum_reloc)
6759 * a8_reloc_table_size);
6760 }
6761
6762 a8_relocs[num_a8_relocs].from = from;
6763 a8_relocs[num_a8_relocs].destination = destination;
6764 a8_relocs[num_a8_relocs].r_type = r_type;
6765 a8_relocs[num_a8_relocs].branch_type = branch_type;
6766 a8_relocs[num_a8_relocs].sym_name = sym_name;
6767 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6768 a8_relocs[num_a8_relocs].hash = hash;
6769
6770 num_a8_relocs++;
6771 }
6772 }
906e58ca
NC		 6773 }
6774
99059e56
RM		 6775 /* We're done with the internal relocs, free them. */
6776 if (elf_section_data (section)->relocs == NULL)
6777 free (internal_relocs);
6778 }
48229727 6779
99059e56 6780 if (htab->fix_cortex_a8)
48229727 6781 {
99059e56
RM		 6782 /* Sort relocs which might apply to Cortex-A8 erratum. */
6783 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6784 sizeof (struct a8_erratum_reloc),
99059e56 6785 &a8_reloc_compare);
48229727 6786
99059e56
RM		 6787 /* Scan for branches which might trigger Cortex-A8 erratum. */
6788 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6789 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6790 a8_relocs, num_a8_relocs,
6791 prev_num_a8_fixes, &stub_changed)
6792 != 0)
48229727 6793 goto error_ret_free_local;
5e681ec4 6794 }
7f991970
AM		 6795
6796 if (local_syms != NULL
6797 && symtab_hdr->contents != (unsigned char *) local_syms)
6798 {
6799 if (!info->keep_memory)
6800 free (local_syms);
6801 else
6802 symtab_hdr->contents = (unsigned char *) local_syms;
6803 }
5e681ec4
PB		 6804 }
6805
0955507f
TP		 6806 if (first_veneer_scan
6807 && !set_cmse_veneer_addr_from_implib (info, htab,
6808 &cmse_stub_created))
6809 ret = FALSE;
6810
eb7c4339 6811 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6812 stub_changed = TRUE;
48229727 6813
906e58ca
NC		 6814 if (!stub_changed)
6815 break;
5e681ec4 6816
906e58ca
NC		 6817 /* OK, we've added some stubs. Find out the new size of the
6818 stub sections. */
6819 for (stub_sec = htab->stub_bfd->sections;
6820 stub_sec != NULL;
6821 stub_sec = stub_sec->next)
3e6b1042
DJ		 6822 {
6823 /* Ignore non-stub sections. */
6824 if (!strstr (stub_sec->name, STUB_SUFFIX))
6825 continue;
6826
6827 stub_sec->size = 0;
6828 }
b34b2d70 6829
0955507f
TP		 6830 /* Add new SG veneers after those already in the input import
6831 library. */
6832 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6833 stub_type++)
6834 {
6835 bfd_vma *start_offset_p;
6836 asection **stub_sec_p;
6837
6838 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6839 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6840 if (start_offset_p == NULL)
6841 continue;
6842
6843 BFD_ASSERT (stub_sec_p != NULL);
6844 if (*stub_sec_p != NULL)
6845 (*stub_sec_p)->size = *start_offset_p;
6846 }
6847
d7c5bd02 6848 /* Compute stub section size, considering padding. */
906e58ca 6849 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6850 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6851 stub_type++)
6852 {
6853 int size, padding;
6854 asection **stub_sec_p;
6855
6856 padding = arm_dedicated_stub_section_padding (stub_type);
6857 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6858 /* Skip if no stub input section or no stub section padding
6859 required. */
6860 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6861 continue;
6862 /* Stub section padding required but no dedicated section. */
6863 BFD_ASSERT (stub_sec_p);
6864
6865 size = (*stub_sec_p)->size;
6866 size = (size + padding - 1) & ~(padding - 1);
6867 (*stub_sec_p)->size = size;
6868 }
906e58ca 6869
48229727
JB		 6870 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6871 if (htab->fix_cortex_a8)
99059e56
RM		 6872 for (i = 0; i < num_a8_fixes; i++)
6873 {
48229727 6874 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6875 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6876
6877 if (stub_sec == NULL)
7f991970 6878 return FALSE;
48229727 6879
99059e56
RM		 6880 stub_sec->size
6881 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6882 NULL);
6883 }
48229727
JB		 6884
6885
906e58ca
NC		 6886 /* Ask the linker to do its stuff. */
6887 (*htab->layout_sections_again) ();
4ba2ef8f 6888 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6889 }
6890
48229727
JB		 6891 /* Add stubs for Cortex-A8 erratum fixes now. */
6892 if (htab->fix_cortex_a8)
6893 {
6894 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6895 {
6896 struct elf32_arm_stub_hash_entry *stub_entry;
6897 char *stub_name = a8_fixes[i].stub_name;
6898 asection *section = a8_fixes[i].section;
6899 unsigned int section_id = a8_fixes[i].section->id;
6900 asection *link_sec = htab->stub_group[section_id].link_sec;
6901 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6902 const insn_sequence *template_sequence;
6903 int template_size, size = 0;
6904
6905 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6906 TRUE, FALSE);
6907 if (stub_entry == NULL)
6908 {
871b3ab2 6909 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6910 section->owner, stub_name);
99059e56
RM		 6911 return FALSE;
6912 }
6913
6914 stub_entry->stub_sec = stub_sec;
0955507f 6915 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6916 stub_entry->id_sec = link_sec;
6917 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6918 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6919 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6920 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6921 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6922 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6923
99059e56
RM		 6924 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6925 &template_sequence,
6926 &template_size);
48229727 6927
99059e56
RM		 6928 stub_entry->stub_size = size;
6929 stub_entry->stub_template = template_sequence;
6930 stub_entry->stub_template_size = template_size;
6931 }
48229727
JB		 6932
6933 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6934 elf32_arm_write_section(). */
48229727
JB		 6935 htab->a8_erratum_fixes = a8_fixes;
6936 htab->num_a8_erratum_fixes = num_a8_fixes;
6937 }
6938 else
6939 {
6940 htab->a8_erratum_fixes = NULL;
6941 htab->num_a8_erratum_fixes = 0;
6942 }
0955507f 6943 return ret;
5e681ec4
PB		 6944}
6945
906e58ca
NC		 6946/* Build all the stubs associated with the current output file. The
6947 stubs are kept in a hash table attached to the main linker hash
6948 table. We also set up the .plt entries for statically linked PIC
6949 functions here. This function is called via arm_elf_finish in the
6950 linker. */
252b5132 6951
906e58ca
NC		 6952bfd_boolean
6953elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6954{
906e58ca
NC		 6955 asection *stub_sec;
6956 struct bfd_hash_table *table;
0955507f 6957 enum elf32_arm_stub_type stub_type;
906e58ca 6958 struct elf32_arm_link_hash_table *htab;
252b5132 6959
906e58ca 6960 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6961 if (htab == NULL)
6962 return FALSE;
252b5132 6963
906e58ca
NC		 6964 for (stub_sec = htab->stub_bfd->sections;
6965 stub_sec != NULL;
6966 stub_sec = stub_sec->next)
252b5132 6967 {
906e58ca
NC		 6968 bfd_size_type size;
6969
8029a119 6970 /* Ignore non-stub sections. */
906e58ca
NC		 6971 if (!strstr (stub_sec->name, STUB_SUFFIX))
6972 continue;
6973
d7c5bd02 6974 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 6975 must at least be done for stub section requiring padding and for SG
6976 veneers to ensure that a non secure code branching to a removed SG
6977 veneer causes an error. */
906e58ca 6978 size = stub_sec->size;
21d799b5 6979 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6980 if (stub_sec->contents == NULL && size != 0)
6981 return FALSE;
0955507f 6982
906e58ca 6983 stub_sec->size = 0;
252b5132
RH		 6984 }
6985
0955507f
TP		 6986 /* Add new SG veneers after those already in the input import library. */
6987 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6988 {
6989 bfd_vma *start_offset_p;
6990 asection **stub_sec_p;
6991
6992 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6993 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6994 if (start_offset_p == NULL)
6995 continue;
6996
6997 BFD_ASSERT (stub_sec_p != NULL);
6998 if (*stub_sec_p != NULL)
6999 (*stub_sec_p)->size = *start_offset_p;
7000 }
7001
906e58ca
NC		 7002 /* Build the stubs as directed by the stub hash table. */
7003 table = &htab->stub_hash_table;
7004 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 7005 if (htab->fix_cortex_a8)
7006 {
7007 /* Place the cortex a8 stubs last. */
7008 htab->fix_cortex_a8 = -1;
7009 bfd_hash_traverse (table, arm_build_one_stub, info);
7010 }
252b5132 7011
906e58ca 7012 return TRUE;
252b5132
RH		 7013}
7014
9b485d32
NC		 7015/* Locate the Thumb encoded calling stub for NAME. */
7016
252b5132 7017static struct elf_link_hash_entry *
57e8b36a
NC		 7018find_thumb_glue (struct bfd_link_info *link_info,
7019 const char *name,
f2a9dd69 7020 char **error_message)
252b5132
RH		 7021{
7022 char *tmp_name;
7023 struct elf_link_hash_entry *hash;
7024 struct elf32_arm_link_hash_table *hash_table;
7025
7026 /* We need a pointer to the armelf specific hash table. */
7027 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7028 if (hash_table == NULL)
7029 return NULL;
252b5132 7030
21d799b5 7031 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7032 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7033
7034 BFD_ASSERT (tmp_name);
7035
7036 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7037
7038 hash = elf_link_hash_lookup
b34976b6 7039 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7040
b1657152 7041 if (hash == NULL
90b6238f
AM		 7042 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7043 "Thumb", tmp_name, name) == -1)
b1657152 7044 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7045
7046 free (tmp_name);
7047
7048 return hash;
7049}
7050
9b485d32
NC		 7051/* Locate the ARM encoded calling stub for NAME. */
7052
252b5132 7053static struct elf_link_hash_entry *
57e8b36a
NC		 7054find_arm_glue (struct bfd_link_info *link_info,
7055 const char *name,
f2a9dd69 7056 char **error_message)
252b5132
RH		 7057{
7058 char *tmp_name;
7059 struct elf_link_hash_entry *myh;
7060 struct elf32_arm_link_hash_table *hash_table;
7061
7062 /* We need a pointer to the elfarm specific hash table. */
7063 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7064 if (hash_table == NULL)
7065 return NULL;
252b5132 7066
21d799b5 7067 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7068 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7069
7070 BFD_ASSERT (tmp_name);
7071
7072 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7073
7074 myh = elf_link_hash_lookup
b34976b6 7075 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7076
b1657152 7077 if (myh == NULL
90b6238f
AM		 7078 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7079 "ARM", tmp_name, name) == -1)
b1657152 7080 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7081
7082 free (tmp_name);
7083
7084 return myh;
7085}
7086
8f6277f5 7087/* ARM->Thumb glue (static images):
252b5132
RH		 7088
7089 .arm
7090 __func_from_arm:
7091 ldr r12, __func_addr
7092 bx r12
7093 __func_addr:
906e58ca 7094 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 7095
26079076
PB		 7096 (v5t static images)
7097 .arm
7098 __func_from_arm:
7099 ldr pc, __func_addr
7100 __func_addr:
906e58ca 7101 .word func @ behave as if you saw a ARM_32 reloc.
26079076 7102
8f6277f5
PB		 7103 (relocatable images)
7104 .arm
7105 __func_from_arm:
7106 ldr r12, __func_offset
7107 add r12, r12, pc
7108 bx r12
7109 __func_offset:
8029a119 7110 .word func - . */
8f6277f5
PB		 7111
7112#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 7113static const insn32 a2t1_ldr_insn = 0xe59fc000;
7114static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7115static const insn32 a2t3_func_addr_insn = 0x00000001;
7116
26079076
PB		 7117#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7118static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7119static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7120
8f6277f5
PB		 7121#define ARM2THUMB_PIC_GLUE_SIZE 16
7122static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7123static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7124static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7125
07d6d2b8 7126/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 7127
07d6d2b8
AM		 7128 .thumb .thumb
7129 .align 2 .align 2
7130 __func_from_thumb: __func_from_thumb:
7131 bx pc push {r6, lr}
7132 nop ldr r6, __func_addr
7133 .arm mov lr, pc
7134 b func bx r6
99059e56
RM		 7135 .arm
7136 ;; back_to_thumb
7137 ldmia r13! {r6, lr}
7138 bx lr
7139 __func_addr:
07d6d2b8 7140 .word func */
252b5132
RH		 7141
7142#define THUMB2ARM_GLUE_SIZE 8
7143static const insn16 t2a1_bx_pc_insn = 0x4778;
7144static const insn16 t2a2_noop_insn = 0x46c0;
7145static const insn32 t2a3_b_insn = 0xea000000;
7146
c7b8f16e 7147#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 7148#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7149#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 7150
845b51d6
PB		 7151#define ARM_BX_VENEER_SIZE 12
7152static const insn32 armbx1_tst_insn = 0xe3100001;
7153static const insn32 armbx2_moveq_insn = 0x01a0f000;
7154static const insn32 armbx3_bx_insn = 0xe12fff10;
7155
7e392df6 7156#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 7157static void
7158arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 7159{
7160 asection * s;
8029a119 7161 bfd_byte * contents;
252b5132 7162
8029a119 7163 if (size == 0)
3e6b1042
DJ		 7164 {
7165 /* Do not include empty glue sections in the output. */
7166 if (abfd != NULL)
7167 {
3d4d4302 7168 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 7169 if (s != NULL)
7170 s->flags |= SEC_EXCLUDE;
7171 }
7172 return;
7173 }
252b5132 7174
8029a119 7175 BFD_ASSERT (abfd != NULL);
252b5132 7176
3d4d4302 7177 s = bfd_get_linker_section (abfd, name);
8029a119 7178 BFD_ASSERT (s != NULL);
252b5132 7179
21d799b5 7180 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 7181
8029a119
NC		 7182 BFD_ASSERT (s->size == size);
7183 s->contents = contents;
7184}
906e58ca 7185
8029a119
NC		 7186bfd_boolean
7187bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7188{
7189 struct elf32_arm_link_hash_table * globals;
906e58ca 7190
8029a119
NC		 7191 globals = elf32_arm_hash_table (info);
7192 BFD_ASSERT (globals != NULL);
906e58ca 7193
8029a119
NC		 7194 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7195 globals->arm_glue_size,
7196 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 7197
8029a119
NC		 7198 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7199 globals->thumb_glue_size,
7200 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 7201
8029a119
NC		 7202 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7203 globals->vfp11_erratum_glue_size,
7204 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 7205
a504d23a
LA		 7206 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7207 globals->stm32l4xx_erratum_glue_size,
7208 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7209
8029a119
NC		 7210 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7211 globals->bx_glue_size,
845b51d6
PB		 7212 ARM_BX_GLUE_SECTION_NAME);
7213
b34976b6 7214 return TRUE;
252b5132
RH		 7215}
7216
a4fd1a8e 7217/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7218 returns the symbol identifying the stub. */
7219
a4fd1a8e 7220static struct elf_link_hash_entry *
57e8b36a
NC		 7221record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7222 struct elf_link_hash_entry * h)
252b5132
RH		 7223{
7224 const char * name = h->root.root.string;
63b0f745 7225 asection * s;
252b5132
RH		 7226 char * tmp_name;
7227 struct elf_link_hash_entry * myh;
14a793b2 7228 struct bfd_link_hash_entry * bh;
252b5132 7229 struct elf32_arm_link_hash_table * globals;
dc810e39 7230 bfd_vma val;
2f475487 7231 bfd_size_type size;
252b5132
RH		 7232
7233 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7234 BFD_ASSERT (globals != NULL);
7235 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7236
3d4d4302 7237 s = bfd_get_linker_section
252b5132
RH		 7238 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7239
252b5132
RH		 7240 BFD_ASSERT (s != NULL);
7241
21d799b5 7242 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7243 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7244
7245 BFD_ASSERT (tmp_name);
7246
7247 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7248
7249 myh = elf_link_hash_lookup
b34976b6 7250 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7251
7252 if (myh != NULL)
7253 {
9b485d32 7254 /* We've already seen this guy. */
252b5132 7255 free (tmp_name);
a4fd1a8e 7256 return myh;
252b5132
RH		 7257 }
7258
57e8b36a
NC		 7259 /* The only trick here is using hash_table->arm_glue_size as the value.
7260 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7261 putting it. The +1 on the value marks that the stub has not been
7262 output yet - not that it is a Thumb function. */
14a793b2 7263 bh = NULL;
dc810e39
AM		 7264 val = globals->arm_glue_size + 1;
7265 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7266 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7267 NULL, TRUE, FALSE, &bh);
252b5132 7268
b7693d02
DJ		 7269 myh = (struct elf_link_hash_entry *) bh;
7270 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7271 myh->forced_local = 1;
7272
252b5132
RH		 7273 free (tmp_name);
7274
0e1862bb
L		 7275 if (bfd_link_pic (link_info)
7276 || globals->root.is_relocatable_executable
27e55c4d 7277 || globals->pic_veneer)
2f475487 7278 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7279 else if (globals->use_blx)
7280 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7281 else
2f475487
AM		 7282 size = ARM2THUMB_STATIC_GLUE_SIZE;
7283
7284 s->size += size;
7285 globals->arm_glue_size += size;
252b5132 7286
a4fd1a8e 7287 return myh;
252b5132
RH		 7288}
7289
845b51d6
PB		 7290/* Allocate space for ARMv4 BX veneers. */
7291
7292static void
7293record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7294{
7295 asection * s;
7296 struct elf32_arm_link_hash_table *globals;
7297 char *tmp_name;
7298 struct elf_link_hash_entry *myh;
7299 struct bfd_link_hash_entry *bh;
7300 bfd_vma val;
7301
7302 /* BX PC does not need a veneer. */
7303 if (reg == 15)
7304 return;
7305
7306 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7307 BFD_ASSERT (globals != NULL);
7308 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7309
7310 /* Check if this veneer has already been allocated. */
7311 if (globals->bx_glue_offset[reg])
7312 return;
7313
3d4d4302 7314 s = bfd_get_linker_section
845b51d6
PB		 7315 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7316
7317 BFD_ASSERT (s != NULL);
7318
7319 /* Add symbol for veneer. */
21d799b5
NC		 7320 tmp_name = (char *)
7321 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7322
845b51d6 7323 BFD_ASSERT (tmp_name);
906e58ca 7324
845b51d6 7325 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7326
845b51d6
PB		 7327 myh = elf_link_hash_lookup
7328 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7329
845b51d6 7330 BFD_ASSERT (myh == NULL);
906e58ca 7331
845b51d6
PB		 7332 bh = NULL;
7333 val = globals->bx_glue_size;
7334 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7335 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7336 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7337
7338 myh = (struct elf_link_hash_entry *) bh;
7339 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7340 myh->forced_local = 1;
7341
7342 s->size += ARM_BX_VENEER_SIZE;
7343 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7344 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7345}
7346
7347
c7b8f16e
JB		 7348/* Add an entry to the code/data map for section SEC. */
7349
7350static void
7351elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7352{
7353 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7354 unsigned int newidx;
906e58ca 7355
c7b8f16e
JB		 7356 if (sec_data->map == NULL)
7357 {
21d799b5 7358 sec_data->map = (elf32_arm_section_map *)
99059e56 7359 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7360 sec_data->mapcount = 0;
7361 sec_data->mapsize = 1;
7362 }
906e58ca 7363
c7b8f16e 7364 newidx = sec_data->mapcount++;
906e58ca 7365
c7b8f16e
JB		 7366 if (sec_data->mapcount > sec_data->mapsize)
7367 {
7368 sec_data->mapsize *= 2;
21d799b5 7369 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7370 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7371 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7372 }
7373
7374 if (sec_data->map)
7375 {
7376 sec_data->map[newidx].vma = vma;
7377 sec_data->map[newidx].type = type;
c7b8f16e 7378 }
c7b8f16e
JB		 7379}
7380
7381
7382/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7383 veneers are handled for now. */
7384
7385static bfd_vma
7386record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7387 elf32_vfp11_erratum_list *branch,
7388 bfd *branch_bfd,
7389 asection *branch_sec,
7390 unsigned int offset)
c7b8f16e
JB		 7391{
7392 asection *s;
7393 struct elf32_arm_link_hash_table *hash_table;
7394 char *tmp_name;
7395 struct elf_link_hash_entry *myh;
7396 struct bfd_link_hash_entry *bh;
7397 bfd_vma val;
7398 struct _arm_elf_section_data *sec_data;
c7b8f16e 7399 elf32_vfp11_erratum_list *newerr;
906e58ca 7400
c7b8f16e 7401 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7402 BFD_ASSERT (hash_table != NULL);
7403 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7404
3d4d4302 7405 s = bfd_get_linker_section
c7b8f16e 7406 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7407
c7b8f16e 7408 sec_data = elf32_arm_section_data (s);
906e58ca 7409
c7b8f16e 7410 BFD_ASSERT (s != NULL);
906e58ca 7411
21d799b5 7412 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7413 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7414
c7b8f16e 7415 BFD_ASSERT (tmp_name);
906e58ca 7416
c7b8f16e
JB		 7417 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7418 hash_table->num_vfp11_fixes);
906e58ca 7419
c7b8f16e
JB		 7420 myh = elf_link_hash_lookup
7421 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7422
c7b8f16e 7423 BFD_ASSERT (myh == NULL);
906e58ca 7424
c7b8f16e
JB		 7425 bh = NULL;
7426 val = hash_table->vfp11_erratum_glue_size;
7427 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7428 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7429 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7430
7431 myh = (struct elf_link_hash_entry *) bh;
7432 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7433 myh->forced_local = 1;
7434
7435 /* Link veneer back to calling location. */
c7e2358a 7436 sec_data->erratumcount += 1;
21d799b5
NC		 7437 newerr = (elf32_vfp11_erratum_list *)
7438 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7439
c7b8f16e
JB		 7440 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7441 newerr->vma = -1;
7442 newerr->u.v.branch = branch;
7443 newerr->u.v.id = hash_table->num_vfp11_fixes;
7444 branch->u.b.veneer = newerr;
7445
7446 newerr->next = sec_data->erratumlist;
7447 sec_data->erratumlist = newerr;
7448
7449 /* A symbol for the return from the veneer. */
7450 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7451 hash_table->num_vfp11_fixes);
7452
7453 myh = elf_link_hash_lookup
7454 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7455
c7b8f16e
JB		 7456 if (myh != NULL)
7457 abort ();
7458
7459 bh = NULL;
7460 val = offset + 4;
7461 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7462 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7463
c7b8f16e
JB		 7464 myh = (struct elf_link_hash_entry *) bh;
7465 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7466 myh->forced_local = 1;
7467
7468 free (tmp_name);
906e58ca 7469
c7b8f16e
JB		 7470 /* Generate a mapping symbol for the veneer section, and explicitly add an
7471 entry for that symbol to the code/data map for the section. */
7472 if (hash_table->vfp11_erratum_glue_size == 0)
7473 {
7474 bh = NULL;
7475 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7476 ever requires this erratum fix. */
c7b8f16e
JB		 7477 _bfd_generic_link_add_one_symbol (link_info,
7478 hash_table->bfd_of_glue_owner, "$a",
7479 BSF_LOCAL, s, 0, NULL,
99059e56 7480 TRUE, FALSE, &bh);
c7b8f16e
JB		 7481
7482 myh = (struct elf_link_hash_entry *) bh;
7483 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7484 myh->forced_local = 1;
906e58ca 7485
c7b8f16e 7486 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7487 BFDs. We must make a note of this generated mapping symbol
7488 ourselves so that code byteswapping works properly in
7489 elf32_arm_write_section. */
c7b8f16e
JB		 7490 elf32_arm_section_map_add (s, 'a', 0);
7491 }
906e58ca 7492
c7b8f16e
JB		 7493 s->size += VFP11_ERRATUM_VENEER_SIZE;
7494 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7495 hash_table->num_vfp11_fixes++;
906e58ca 7496
c7b8f16e
JB		 7497 /* The offset of the veneer. */
7498 return val;
7499}
7500
a504d23a
LA		 7501/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7502 veneers need to be handled because used only in Cortex-M. */
7503
7504static bfd_vma
7505record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7506 elf32_stm32l4xx_erratum_list *branch,
7507 bfd *branch_bfd,
7508 asection *branch_sec,
7509 unsigned int offset,
7510 bfd_size_type veneer_size)
7511{
7512 asection *s;
7513 struct elf32_arm_link_hash_table *hash_table;
7514 char *tmp_name;
7515 struct elf_link_hash_entry *myh;
7516 struct bfd_link_hash_entry *bh;
7517 bfd_vma val;
7518 struct _arm_elf_section_data *sec_data;
7519 elf32_stm32l4xx_erratum_list *newerr;
7520
7521 hash_table = elf32_arm_hash_table (link_info);
7522 BFD_ASSERT (hash_table != NULL);
7523 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7524
7525 s = bfd_get_linker_section
7526 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7527
7528 BFD_ASSERT (s != NULL);
7529
7530 sec_data = elf32_arm_section_data (s);
7531
7532 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7533 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7534
7535 BFD_ASSERT (tmp_name);
7536
7537 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7538 hash_table->num_stm32l4xx_fixes);
7539
7540 myh = elf_link_hash_lookup
7541 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7542
7543 BFD_ASSERT (myh == NULL);
7544
7545 bh = NULL;
7546 val = hash_table->stm32l4xx_erratum_glue_size;
7547 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7548 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7549 NULL, TRUE, FALSE, &bh);
7550
7551 myh = (struct elf_link_hash_entry *) bh;
7552 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7553 myh->forced_local = 1;
7554
7555 /* Link veneer back to calling location. */
7556 sec_data->stm32l4xx_erratumcount += 1;
7557 newerr = (elf32_stm32l4xx_erratum_list *)
7558 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7559
7560 newerr->type = STM32L4XX_ERRATUM_VENEER;
7561 newerr->vma = -1;
7562 newerr->u.v.branch = branch;
7563 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7564 branch->u.b.veneer = newerr;
7565
7566 newerr->next = sec_data->stm32l4xx_erratumlist;
7567 sec_data->stm32l4xx_erratumlist = newerr;
7568
7569 /* A symbol for the return from the veneer. */
7570 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7571 hash_table->num_stm32l4xx_fixes);
7572
7573 myh = elf_link_hash_lookup
7574 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7575
7576 if (myh != NULL)
7577 abort ();
7578
7579 bh = NULL;
7580 val = offset + 4;
7581 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7582 branch_sec, val, NULL, TRUE, FALSE, &bh);
7583
7584 myh = (struct elf_link_hash_entry *) bh;
7585 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7586 myh->forced_local = 1;
7587
7588 free (tmp_name);
7589
7590 /* Generate a mapping symbol for the veneer section, and explicitly add an
7591 entry for that symbol to the code/data map for the section. */
7592 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7593 {
7594 bh = NULL;
7595 /* Creates a THUMB symbol since there is no other choice. */
7596 _bfd_generic_link_add_one_symbol (link_info,
7597 hash_table->bfd_of_glue_owner, "$t",
7598 BSF_LOCAL, s, 0, NULL,
7599 TRUE, FALSE, &bh);
7600
7601 myh = (struct elf_link_hash_entry *) bh;
7602 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7603 myh->forced_local = 1;
7604
7605 /* The elf32_arm_init_maps function only cares about symbols from input
7606 BFDs. We must make a note of this generated mapping symbol
7607 ourselves so that code byteswapping works properly in
7608 elf32_arm_write_section. */
7609 elf32_arm_section_map_add (s, 't', 0);
7610 }
7611
7612 s->size += veneer_size;
7613 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7614 hash_table->num_stm32l4xx_fixes++;
7615
7616 /* The offset of the veneer. */
7617 return val;
7618}
7619
8029a119 7620#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7621 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7622 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7623
7624/* Create a fake section for use by the ARM backend of the linker. */
7625
7626static bfd_boolean
7627arm_make_glue_section (bfd * abfd, const char * name)
7628{
7629 asection * sec;
7630
3d4d4302 7631 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7632 if (sec != NULL)
7633 /* Already made. */
7634 return TRUE;
7635
3d4d4302 7636 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7637
7638 if (sec == NULL
7639 || !bfd_set_section_alignment (abfd, sec, 2))
7640 return FALSE;
7641
7642 /* Set the gc mark to prevent the section from being removed by garbage
7643 collection, despite the fact that no relocs refer to this section. */
7644 sec->gc_mark = 1;
7645
7646 return TRUE;
7647}
7648
1db37fe6
YG		 7649/* Set size of .plt entries. This function is called from the
7650 linker scripts in ld/emultempl/{armelf}.em. */
7651
7652void
7653bfd_elf32_arm_use_long_plt (void)
7654{
7655 elf32_arm_use_long_plt_entry = TRUE;
7656}
7657
8afb0e02
NC		 7658/* Add the glue sections to ABFD. This function is called from the
7659 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7660
b34976b6 7661bfd_boolean
57e8b36a
NC		 7662bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7663 struct bfd_link_info *info)
252b5132 7664{
a504d23a
LA		 7665 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7666 bfd_boolean dostm32l4xx = globals
7667 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7668 bfd_boolean addglue;
7669
8afb0e02
NC		 7670 /* If we are only performing a partial
7671 link do not bother adding the glue. */
0e1862bb 7672 if (bfd_link_relocatable (info))
b34976b6 7673 return TRUE;
252b5132 7674
a504d23a 7675 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7676 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7677 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7678 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7679
7680 if (!dostm32l4xx)
7681 return addglue;
7682
7683 return addglue
7684 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7685}
7686
daa4adae
TP		 7687/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7688 ensures they are not marked for deletion by
7689 strip_excluded_output_sections () when veneers are going to be created
7690 later. Not doing so would trigger assert on empty section size in
7691 lang_size_sections_1 (). */
7692
7693void
7694bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7695{
7696 enum elf32_arm_stub_type stub_type;
7697
7698 /* If we are only performing a partial
7699 link do not bother adding the glue. */
7700 if (bfd_link_relocatable (info))
7701 return;
7702
7703 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7704 {
7705 asection *out_sec;
7706 const char *out_sec_name;
7707
7708 if (!arm_dedicated_stub_output_section_required (stub_type))
7709 continue;
7710
7711 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7712 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7713 if (out_sec != NULL)
7714 out_sec->flags |= SEC_KEEP;
7715 }
7716}
7717
8afb0e02
NC		 7718/* Select a BFD to be used to hold the sections used by the glue code.
7719 This function is called from the linker scripts in ld/emultempl/
8029a119 7720 {armelf/pe}.em. */
8afb0e02 7721
b34976b6 7722bfd_boolean
57e8b36a 7723bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7724{
7725 struct elf32_arm_link_hash_table *globals;
7726
7727 /* If we are only performing a partial link
7728 do not bother getting a bfd to hold the glue. */
0e1862bb 7729 if (bfd_link_relocatable (info))
b34976b6 7730 return TRUE;
8afb0e02 7731
b7693d02
DJ		 7732 /* Make sure we don't attach the glue sections to a dynamic object. */
7733 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7734
8afb0e02 7735 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7736 BFD_ASSERT (globals != NULL);
7737
7738 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7739 return TRUE;
8afb0e02 7740
252b5132
RH		 7741 /* Save the bfd for later use. */
7742 globals->bfd_of_glue_owner = abfd;
cedb70c5 7743
b34976b6 7744 return TRUE;
252b5132
RH		 7745}
7746
906e58ca
NC		 7747static void
7748check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7749{
2de70689
MGD		 7750 int cpu_arch;
7751
b38cadfb 7752 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7753 Tag_CPU_arch);
7754
7755 if (globals->fix_arm1176)
7756 {
7757 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7758 globals->use_blx = 1;
7759 }
7760 else
7761 {
7762 if (cpu_arch > TAG_CPU_ARCH_V4T)
7763 globals->use_blx = 1;
7764 }
39b41c9c
PB		 7765}
7766
b34976b6 7767bfd_boolean
57e8b36a 7768bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7769 struct bfd_link_info *link_info)
252b5132
RH		 7770{
7771 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7772 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7773 Elf_Internal_Rela *irel, *irelend;
7774 bfd_byte *contents = NULL;
252b5132
RH		 7775
7776 asection *sec;
7777 struct elf32_arm_link_hash_table *globals;
7778
7779 /* If we are only performing a partial link do not bother
7780 to construct any glue. */
0e1862bb 7781 if (bfd_link_relocatable (link_info))
b34976b6 7782 return TRUE;
252b5132 7783
39ce1a6a
NC		 7784 /* Here we have a bfd that is to be included on the link. We have a
7785 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7786 globals = elf32_arm_hash_table (link_info);
252b5132 7787 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7788
7789 check_use_blx (globals);
252b5132 7790
d504ffc8 7791 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7792 {
90b6238f 7793 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7794 abfd);
e489d0ae
PB		 7795 return FALSE;
7796 }
f21f3fe0 7797
39ce1a6a
NC		 7798 /* PR 5398: If we have not decided to include any loadable sections in
7799 the output then we will not have a glue owner bfd. This is OK, it
7800 just means that there is nothing else for us to do here. */
7801 if (globals->bfd_of_glue_owner == NULL)
7802 return TRUE;
7803
252b5132
RH		 7804 /* Rummage around all the relocs and map the glue vectors. */
7805 sec = abfd->sections;
7806
7807 if (sec == NULL)
b34976b6 7808 return TRUE;
252b5132
RH		 7809
7810 for (; sec != NULL; sec = sec->next)
7811 {
7812 if (sec->reloc_count == 0)
7813 continue;
7814
2f475487
AM		 7815 if ((sec->flags & SEC_EXCLUDE) != 0)
7816 continue;
7817
0ffa91dd 7818 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7819
9b485d32 7820 /* Load the relocs. */
6cdc0ccc 7821 internal_relocs
906e58ca 7822 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7823
6cdc0ccc
AM		 7824 if (internal_relocs == NULL)
7825 goto error_return;
252b5132 7826
6cdc0ccc
AM		 7827 irelend = internal_relocs + sec->reloc_count;
7828 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7829 {
7830 long r_type;
7831 unsigned long r_index;
252b5132
RH		 7832
7833 struct elf_link_hash_entry *h;
7834
7835 r_type = ELF32_R_TYPE (irel->r_info);
7836 r_index = ELF32_R_SYM (irel->r_info);
7837
9b485d32 7838 /* These are the only relocation types we care about. */
ba96a88f 7839 if ( r_type != R_ARM_PC24
845b51d6 7840 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7841 continue;
7842
7843 /* Get the section contents if we haven't done so already. */
7844 if (contents == NULL)
7845 {
7846 /* Get cached copy if it exists. */
7847 if (elf_section_data (sec)->this_hdr.contents != NULL)
7848 contents = elf_section_data (sec)->this_hdr.contents;
7849 else
7850 {
7851 /* Go get them off disk. */
57e8b36a 7852 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7853 goto error_return;
7854 }
7855 }
7856
845b51d6
PB		 7857 if (r_type == R_ARM_V4BX)
7858 {
7859 int reg;
7860
7861 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7862 record_arm_bx_glue (link_info, reg);
7863 continue;
7864 }
7865
a7c10850 7866 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7867 h = NULL;
7868
9b485d32 7869 /* We don't care about local symbols. */
252b5132
RH		 7870 if (r_index < symtab_hdr->sh_info)
7871 continue;
7872
9b485d32 7873 /* This is an external symbol. */
252b5132
RH		 7874 r_index -= symtab_hdr->sh_info;
7875 h = (struct elf_link_hash_entry *)
7876 elf_sym_hashes (abfd)[r_index];
7877
7878 /* If the relocation is against a static symbol it must be within
7879 the current section and so cannot be a cross ARM/Thumb relocation. */
7880 if (h == NULL)
7881 continue;
7882
d504ffc8
DJ		 7883 /* If the call will go through a PLT entry then we do not need
7884 glue. */
362d30a1 7885 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7886 continue;
7887
252b5132
RH		 7888 switch (r_type)
7889 {
7890 case R_ARM_PC24:
7891 /* This one is a call from arm code. We need to look up
99059e56
RM		 7892 the target of the call. If it is a thumb target, we
7893 insert glue. */
39d911fc
TP		 7894 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7895 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7896 record_arm_to_thumb_glue (link_info, h);
7897 break;
7898
252b5132 7899 default:
c6596c5e 7900 abort ();
252b5132
RH		 7901 }
7902 }
6cdc0ccc
AM		 7903
7904 if (contents != NULL
7905 && elf_section_data (sec)->this_hdr.contents != contents)
7906 free (contents);
7907 contents = NULL;
7908
7909 if (internal_relocs != NULL
7910 && elf_section_data (sec)->relocs != internal_relocs)
7911 free (internal_relocs);
7912 internal_relocs = NULL;
252b5132
RH		 7913 }
7914
b34976b6 7915 return TRUE;
9a5aca8c 7916
252b5132 7917error_return:
6cdc0ccc
AM		 7918 if (contents != NULL
7919 && elf_section_data (sec)->this_hdr.contents != contents)
7920 free (contents);
7921 if (internal_relocs != NULL
7922 && elf_section_data (sec)->relocs != internal_relocs)
7923 free (internal_relocs);
9a5aca8c 7924
b34976b6 7925 return FALSE;
252b5132 7926}
7e392df6 7927#endif
252b5132 7928
eb043451 7929
c7b8f16e
JB		 7930/* Initialise maps of ARM/Thumb/data for input BFDs. */
7931
7932void
7933bfd_elf32_arm_init_maps (bfd *abfd)
7934{
7935 Elf_Internal_Sym *isymbuf;
7936 Elf_Internal_Shdr *hdr;
7937 unsigned int i, localsyms;
7938
af1f4419
NC		 7939 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7940 if (! is_arm_elf (abfd))
7941 return;
7942
c7b8f16e
JB		 7943 if ((abfd->flags & DYNAMIC) != 0)
7944 return;
7945
0ffa91dd 7946 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7947 localsyms = hdr->sh_info;
7948
7949 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7950 should contain the number of local symbols, which should come before any
7951 global symbols. Mapping symbols are always local. */
7952 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7953 NULL);
7954
7955 /* No internal symbols read? Skip this BFD. */
7956 if (isymbuf == NULL)
7957 return;
7958
7959 for (i = 0; i < localsyms; i++)
7960 {
7961 Elf_Internal_Sym *isym = &isymbuf[i];
7962 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7963 const char *name;
906e58ca 7964
c7b8f16e 7965 if (sec != NULL
99059e56
RM		 7966 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7967 {
7968 name = bfd_elf_string_from_elf_section (abfd,
7969 hdr->sh_link, isym->st_name);
906e58ca 7970
99059e56 7971 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7972 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7973 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7974 }
c7b8f16e
JB		 7975 }
7976}
7977
7978
48229727
JB		 7979/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7980 say what they wanted. */
7981
7982void
7983bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7984{
7985 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7986 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7987
4dfe6ac6
NC		 7988 if (globals == NULL)
7989 return;
7990
48229727
JB		 7991 if (globals->fix_cortex_a8 == -1)
7992 {
7993 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7994 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7995 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7996 || out_attr[Tag_CPU_arch_profile].i == 0))
7997 globals->fix_cortex_a8 = 1;
7998 else
7999 globals->fix_cortex_a8 = 0;
8000 }
8001}
8002
8003
c7b8f16e
JB		 8004void
8005bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
8006{
8007 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 8008 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 8009
4dfe6ac6
NC		 8010 if (globals == NULL)
8011 return;
c7b8f16e
JB		 8012 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8013 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
8014 {
8015 switch (globals->vfp11_fix)
99059e56
RM		 8016 {
8017 case BFD_ARM_VFP11_FIX_DEFAULT:
8018 case BFD_ARM_VFP11_FIX_NONE:
8019 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8020 break;
8021
8022 default:
8023 /* Give a warning, but do as the user requests anyway. */
871b3ab2 8024 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 8025 "workaround is not necessary for target architecture"), obfd);
8026 }
c7b8f16e
JB		 8027 }
8028 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
8029 /* For earlier architectures, we might need the workaround, but do not
8030 enable it by default. If users is running with broken hardware, they
8031 must enable the erratum fix explicitly. */
8032 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8033}
8034
a504d23a
LA		 8035void
8036bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8037{
8038 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8039 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8040
8041 if (globals == NULL)
8042 return;
8043
8044 /* We assume only Cortex-M4 may require the fix. */
8045 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8046 || out_attr[Tag_CPU_arch_profile].i != 'M')
8047 {
8048 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8049 /* Give a warning, but do as the user requests anyway. */
4eca0228 8050 _bfd_error_handler
871b3ab2 8051 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 8052 "workaround is not necessary for target architecture"), obfd);
8053 }
8054}
c7b8f16e 8055
906e58ca
NC		 8056enum bfd_arm_vfp11_pipe
8057{
c7b8f16e
JB		 8058 VFP11_FMAC,
8059 VFP11_LS,
8060 VFP11_DS,
8061 VFP11_BAD
8062};
8063
8064/* Return a VFP register number. This is encoded as RX:X for single-precision
8065 registers, or X:RX for double-precision registers, where RX is the group of
8066 four bits in the instruction encoding and X is the single extension bit.
8067 RX and X fields are specified using their lowest (starting) bit. The return
8068 value is:
8069
8070 0...31: single-precision registers s0...s31
8071 32...63: double-precision registers d0...d31.
906e58ca 8072
c7b8f16e
JB		 8073 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8074 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 8075
c7b8f16e
JB		 8076static unsigned int
8077bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 8078 unsigned int x)
c7b8f16e
JB		 8079{
8080 if (is_double)
8081 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8082 else
8083 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8084}
8085
8086/* Set bits in *WMASK according to a register number REG as encoded by
8087 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8088
8089static void
8090bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8091{
8092 if (reg < 32)
8093 *wmask |= 1 << reg;
8094 else if (reg < 48)
8095 *wmask |= 3 << ((reg - 32) * 2);
8096}
8097
8098/* Return TRUE if WMASK overwrites anything in REGS. */
8099
8100static bfd_boolean
8101bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8102{
8103 int i;
906e58ca 8104
c7b8f16e
JB		 8105 for (i = 0; i < numregs; i++)
8106 {
8107 unsigned int reg = regs[i];
8108
8109 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 8110 return TRUE;
906e58ca 8111
c7b8f16e
JB		 8112 reg -= 32;
8113
8114 if (reg >= 16)
99059e56 8115 continue;
906e58ca 8116
c7b8f16e 8117 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 8118 return TRUE;
c7b8f16e 8119 }
906e58ca 8120
c7b8f16e
JB		 8121 return FALSE;
8122}
8123
8124/* In this function, we're interested in two things: finding input registers
8125 for VFP data-processing instructions, and finding the set of registers which
8126 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8127 hold the written set, so FLDM etc. are easy to deal with (we're only
8128 interested in 32 SP registers or 16 dp registers, due to the VFP version
8129 implemented by the chip in question). DP registers are marked by setting
8130 both SP registers in the write mask). */
8131
8132static enum bfd_arm_vfp11_pipe
8133bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 8134 int *numregs)
c7b8f16e 8135{
91d6fa6a 8136 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 8137 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8138
8139 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8140 {
8141 unsigned int pqrs;
8142 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8143 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8144
8145 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 8146 | ((insn & 0x00300000) >> 19)
8147 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 8148
8149 switch (pqrs)
99059e56
RM		 8150 {
8151 case 0: /* fmac[sd]. */
8152 case 1: /* fnmac[sd]. */
8153 case 2: /* fmsc[sd]. */
8154 case 3: /* fnmsc[sd]. */
8155 vpipe = VFP11_FMAC;
8156 bfd_arm_vfp11_write_mask (destmask, fd);
8157 regs[0] = fd;
8158 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8159 regs[2] = fm;
8160 *numregs = 3;
8161 break;
8162
8163 case 4: /* fmul[sd]. */
8164 case 5: /* fnmul[sd]. */
8165 case 6: /* fadd[sd]. */
8166 case 7: /* fsub[sd]. */
8167 vpipe = VFP11_FMAC;
8168 goto vfp_binop;
8169
8170 case 8: /* fdiv[sd]. */
8171 vpipe = VFP11_DS;
8172 vfp_binop:
8173 bfd_arm_vfp11_write_mask (destmask, fd);
8174 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8175 regs[1] = fm;
8176 *numregs = 2;
8177 break;
8178
8179 case 15: /* extended opcode. */
8180 {
8181 unsigned int extn = ((insn >> 15) & 0x1e)
8182 | ((insn >> 7) & 1);
8183
8184 switch (extn)
8185 {
8186 case 0: /* fcpy[sd]. */
8187 case 1: /* fabs[sd]. */
8188 case 2: /* fneg[sd]. */
8189 case 8: /* fcmp[sd]. */
8190 case 9: /* fcmpe[sd]. */
8191 case 10: /* fcmpz[sd]. */
8192 case 11: /* fcmpez[sd]. */
8193 case 16: /* fuito[sd]. */
8194 case 17: /* fsito[sd]. */
8195 case 24: /* ftoui[sd]. */
8196 case 25: /* ftouiz[sd]. */
8197 case 26: /* ftosi[sd]. */
8198 case 27: /* ftosiz[sd]. */
8199 /* These instructions will not bounce due to underflow. */
8200 *numregs = 0;
8201 vpipe = VFP11_FMAC;
8202 break;
8203
8204 case 3: /* fsqrt[sd]. */
8205 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8206 registers to cause the erratum in previous instructions. */
8207 bfd_arm_vfp11_write_mask (destmask, fd);
8208 vpipe = VFP11_DS;
8209 break;
8210
8211 case 15: /* fcvt{ds,sd}. */
8212 {
8213 int rnum = 0;
8214
8215 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8216
8217 /* Only FCVTSD can underflow. */
99059e56
RM		 8218 if ((insn & 0x100) != 0)
8219 regs[rnum++] = fm;
c7b8f16e 8220
99059e56 8221 *numregs = rnum;
c7b8f16e 8222
99059e56
RM		 8223 vpipe = VFP11_FMAC;
8224 }
8225 break;
c7b8f16e 8226
99059e56
RM		 8227 default:
8228 return VFP11_BAD;
8229 }
8230 }
8231 break;
c7b8f16e 8232
99059e56
RM		 8233 default:
8234 return VFP11_BAD;
8235 }
c7b8f16e
JB		 8236 }
8237 /* Two-register transfer. */
8238 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8239 {
8240 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8241
c7b8f16e
JB		 8242 if ((insn & 0x100000) == 0)
8243 {
99059e56
RM		 8244 if (is_double)
8245 bfd_arm_vfp11_write_mask (destmask, fm);
8246 else
8247 {
8248 bfd_arm_vfp11_write_mask (destmask, fm);
8249 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8250 }
c7b8f16e
JB		 8251 }
8252
91d6fa6a 8253 vpipe = VFP11_LS;
c7b8f16e
JB		 8254 }
8255 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8256 {
8257 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8258 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8259
c7b8f16e 8260 switch (puw)
99059e56
RM		 8261 {
8262 case 0: /* Two-reg transfer. We should catch these above. */
8263 abort ();
906e58ca 8264
99059e56
RM		 8265 case 2: /* fldm[sdx]. */
8266 case 3:
8267 case 5:
8268 {
8269 unsigned int i, offset = insn & 0xff;
c7b8f16e 8270
99059e56
RM		 8271 if (is_double)
8272 offset >>= 1;
c7b8f16e 8273
99059e56
RM		 8274 for (i = fd; i < fd + offset; i++)
8275 bfd_arm_vfp11_write_mask (destmask, i);
8276 }
8277 break;
906e58ca 8278
99059e56
RM		 8279 case 4: /* fld[sd]. */
8280 case 6:
8281 bfd_arm_vfp11_write_mask (destmask, fd);
8282 break;
906e58ca 8283
99059e56
RM		 8284 default:
8285 return VFP11_BAD;
8286 }
c7b8f16e 8287
91d6fa6a 8288 vpipe = VFP11_LS;
c7b8f16e
JB		 8289 }
8290 /* Single-register transfer. Note L==0. */
8291 else if ((insn & 0x0f100e10) == 0x0e000a10)
8292 {
8293 unsigned int opcode = (insn >> 21) & 7;
8294 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8295
8296 switch (opcode)
99059e56
RM		 8297 {
8298 case 0: /* fmsr/fmdlr. */
8299 case 1: /* fmdhr. */
8300 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8301 destination register. I don't know if this is exactly right,
8302 but it is the conservative choice. */
8303 bfd_arm_vfp11_write_mask (destmask, fn);
8304 break;
8305
8306 case 7: /* fmxr. */
8307 break;
8308 }
c7b8f16e 8309
91d6fa6a 8310 vpipe = VFP11_LS;
c7b8f16e
JB		 8311 }
8312
91d6fa6a 8313 return vpipe;
c7b8f16e
JB		 8314}
8315
8316
8317static int elf32_arm_compare_mapping (const void * a, const void * b);
8318
8319
8320/* Look for potentially-troublesome code sequences which might trigger the
8321 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8322 (available from ARM) for details of the erratum. A short version is
8323 described in ld.texinfo. */
8324
8325bfd_boolean
8326bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8327{
8328 asection *sec;
8329 bfd_byte *contents = NULL;
8330 int state = 0;
8331 int regs[3], numregs = 0;
8332 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8333 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8334
4dfe6ac6
NC		 8335 if (globals == NULL)
8336 return FALSE;
8337
c7b8f16e
JB		 8338 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8339 The states transition as follows:
906e58ca 8340
c7b8f16e 8341 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8342 A VFP FMAC-pipeline instruction has been seen. Fill
8343 regs[0]..regs[numregs-1] with its input operands. Remember this
8344 instruction in 'first_fmac'.
c7b8f16e
JB		 8345
8346 1 -> 2
99059e56
RM		 8347 Any instruction, except for a VFP instruction which overwrites
8348 regs[*].
906e58ca 8349
c7b8f16e
JB		 8350 1 -> 3 [ -> 0 ] or
8351 2 -> 3 [ -> 0 ]
99059e56
RM		 8352 A VFP instruction has been seen which overwrites any of regs[*].
8353 We must make a veneer! Reset state to 0 before examining next
8354 instruction.
906e58ca 8355
c7b8f16e 8356 2 -> 0
99059e56
RM		 8357 If we fail to match anything in state 2, reset to state 0 and reset
8358 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8359
8360 If the VFP11 vector mode is in use, there must be at least two unrelated
8361 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8362 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8363
8364 /* If we are only performing a partial link do not bother
8365 to construct any glue. */
0e1862bb 8366 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8367 return TRUE;
8368
0ffa91dd
NC		 8369 /* Skip if this bfd does not correspond to an ELF image. */
8370 if (! is_arm_elf (abfd))
8371 return TRUE;
906e58ca 8372
c7b8f16e
JB		 8373 /* We should have chosen a fix type by the time we get here. */
8374 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8375
8376 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8377 return TRUE;
2e6030b9 8378
33a7ffc2
JM		 8379 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8380 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8381 return TRUE;
8382
c7b8f16e
JB		 8383 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8384 {
8385 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8386 struct _arm_elf_section_data *sec_data;
8387
8388 /* If we don't have executable progbits, we're not interested in this
99059e56 8389 section. Also skip if section is to be excluded. */
c7b8f16e 8390 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8391 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8392 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8393 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8394 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8395 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8396 continue;
c7b8f16e
JB		 8397
8398 sec_data = elf32_arm_section_data (sec);
906e58ca 8399
c7b8f16e 8400 if (sec_data->mapcount == 0)
99059e56 8401 continue;
906e58ca 8402
c7b8f16e
JB		 8403 if (elf_section_data (sec)->this_hdr.contents != NULL)
8404 contents = elf_section_data (sec)->this_hdr.contents;
8405 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8406 goto error_return;
8407
8408 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8409 elf32_arm_compare_mapping);
8410
8411 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8412 {
8413 unsigned int span_start = sec_data->map[span].vma;
8414 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8415 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8416 char span_type = sec_data->map[span].type;
8417
8418 /* FIXME: Only ARM mode is supported at present. We may need to
8419 support Thumb-2 mode also at some point. */
8420 if (span_type != 'a')
8421 continue;
8422
8423 for (i = span_start; i < span_end;)
8424 {
8425 unsigned int next_i = i + 4;
8426 unsigned int insn = bfd_big_endian (abfd)
8427 ? (contents[i] << 24)
8428 | (contents[i + 1] << 16)
8429 | (contents[i + 2] << 8)
8430 | contents[i + 3]
8431 : (contents[i + 3] << 24)
8432 | (contents[i + 2] << 16)
8433 | (contents[i + 1] << 8)
8434 | contents[i];
8435 unsigned int writemask = 0;
8436 enum bfd_arm_vfp11_pipe vpipe;
8437
8438 switch (state)
8439 {
8440 case 0:
8441 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8442 &numregs);
8443 /* I'm assuming the VFP11 erratum can trigger with denorm
8444 operands on either the FMAC or the DS pipeline. This might
8445 lead to slightly overenthusiastic veneer insertion. */
8446 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8447 {
8448 state = use_vector ? 1 : 2;
8449 first_fmac = i;
8450 veneer_of_insn = insn;
8451 }
8452 break;
8453
8454 case 1:
8455 {
8456 int other_regs[3], other_numregs;
8457 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8458 other_regs,
99059e56
RM		 8459 &other_numregs);
8460 if (vpipe != VFP11_BAD
8461 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8462 numregs))
99059e56
RM		 8463 state = 3;
8464 else
8465 state = 2;
8466 }
8467 break;
8468
8469 case 2:
8470 {
8471 int other_regs[3], other_numregs;
8472 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8473 other_regs,
99059e56
RM		 8474 &other_numregs);
8475 if (vpipe != VFP11_BAD
8476 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8477 numregs))
99059e56
RM		 8478 state = 3;
8479 else
8480 {
8481 state = 0;
8482 next_i = first_fmac + 4;
8483 }
8484 }
8485 break;
8486
8487 case 3:
8488 abort (); /* Should be unreachable. */
8489 }
8490
8491 if (state == 3)
8492 {
8493 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8494 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8495
8496 elf32_arm_section_data (sec)->erratumcount += 1;
8497
8498 newerr->u.b.vfp_insn = veneer_of_insn;
8499
8500 switch (span_type)
8501 {
8502 case 'a':
8503 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8504 break;
8505
8506 default:
8507 abort ();
8508 }
8509
8510 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8511 first_fmac);
8512
99059e56 8513 newerr->vma = -1;
c7b8f16e 8514
99059e56
RM		 8515 newerr->next = sec_data->erratumlist;
8516 sec_data->erratumlist = newerr;
c7b8f16e 8517
99059e56
RM		 8518 state = 0;
8519 }
c7b8f16e 8520
99059e56
RM		 8521 i = next_i;
8522 }
8523 }
906e58ca 8524
c7b8f16e 8525 if (contents != NULL
99059e56
RM		 8526 && elf_section_data (sec)->this_hdr.contents != contents)
8527 free (contents);
c7b8f16e
JB		 8528 contents = NULL;
8529 }
8530
8531 return TRUE;
8532
8533error_return:
8534 if (contents != NULL
8535 && elf_section_data (sec)->this_hdr.contents != contents)
8536 free (contents);
906e58ca 8537
c7b8f16e
JB		 8538 return FALSE;
8539}
8540
8541/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8542 after sections have been laid out, using specially-named symbols. */
8543
8544void
8545bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8546 struct bfd_link_info *link_info)
8547{
8548 asection *sec;
8549 struct elf32_arm_link_hash_table *globals;
8550 char *tmp_name;
906e58ca 8551
0e1862bb 8552 if (bfd_link_relocatable (link_info))
c7b8f16e 8553 return;
2e6030b9
MS		 8554
8555 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8556 if (! is_arm_elf (abfd))
2e6030b9
MS		 8557 return;
8558
c7b8f16e 8559 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8560 if (globals == NULL)
8561 return;
906e58ca 8562
21d799b5 8563 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8564 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8565
8566 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8567 {
8568 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8569 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8570
c7b8f16e 8571 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8572 {
8573 struct elf_link_hash_entry *myh;
8574 bfd_vma vma;
8575
8576 switch (errnode->type)
8577 {
8578 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8579 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8580 /* Find veneer symbol. */
8581 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8582 errnode->u.b.veneer->u.v.id);
8583
99059e56
RM		 8584 myh = elf_link_hash_lookup
8585 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8586
a504d23a 8587 if (myh == NULL)
90b6238f
AM		 8588 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8589 abfd, "VFP11", tmp_name);
a504d23a
LA		 8590
8591 vma = myh->root.u.def.section->output_section->vma
8592 + myh->root.u.def.section->output_offset
8593 + myh->root.u.def.value;
8594
8595 errnode->u.b.veneer->vma = vma;
8596 break;
8597
8598 case VFP11_ERRATUM_ARM_VENEER:
8599 case VFP11_ERRATUM_THUMB_VENEER:
8600 /* Find return location. */
8601 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8602 errnode->u.v.id);
8603
8604 myh = elf_link_hash_lookup
8605 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8606
8607 if (myh == NULL)
90b6238f
AM		 8608 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8609 abfd, "VFP11", tmp_name);
a504d23a
LA		 8610
8611 vma = myh->root.u.def.section->output_section->vma
8612 + myh->root.u.def.section->output_offset
8613 + myh->root.u.def.value;
8614
8615 errnode->u.v.branch->vma = vma;
8616 break;
8617
8618 default:
8619 abort ();
8620 }
8621 }
8622 }
8623
8624 free (tmp_name);
8625}
8626
8627/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8628 return locations after sections have been laid out, using
8629 specially-named symbols. */
8630
8631void
8632bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8633 struct bfd_link_info *link_info)
8634{
8635 asection *sec;
8636 struct elf32_arm_link_hash_table *globals;
8637 char *tmp_name;
8638
8639 if (bfd_link_relocatable (link_info))
8640 return;
8641
8642 /* Skip if this bfd does not correspond to an ELF image. */
8643 if (! is_arm_elf (abfd))
8644 return;
8645
8646 globals = elf32_arm_hash_table (link_info);
8647 if (globals == NULL)
8648 return;
8649
8650 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8651 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8652
8653 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8654 {
8655 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8656 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8657
8658 for (; errnode != NULL; errnode = errnode->next)
8659 {
8660 struct elf_link_hash_entry *myh;
8661 bfd_vma vma;
8662
8663 switch (errnode->type)
8664 {
8665 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8666 /* Find veneer symbol. */
8667 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8668 errnode->u.b.veneer->u.v.id);
8669
8670 myh = elf_link_hash_lookup
8671 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8672
8673 if (myh == NULL)
90b6238f
AM		 8674 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8675 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8676
8677 vma = myh->root.u.def.section->output_section->vma
8678 + myh->root.u.def.section->output_offset
8679 + myh->root.u.def.value;
8680
8681 errnode->u.b.veneer->vma = vma;
8682 break;
8683
8684 case STM32L4XX_ERRATUM_VENEER:
8685 /* Find return location. */
8686 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8687 errnode->u.v.id);
8688
8689 myh = elf_link_hash_lookup
8690 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8691
8692 if (myh == NULL)
90b6238f
AM		 8693 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8694 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8695
8696 vma = myh->root.u.def.section->output_section->vma
8697 + myh->root.u.def.section->output_offset
8698 + myh->root.u.def.value;
8699
8700 errnode->u.v.branch->vma = vma;
8701 break;
8702
8703 default:
8704 abort ();
8705 }
8706 }
8707 }
8708
8709 free (tmp_name);
8710}
8711
8712static inline bfd_boolean
8713is_thumb2_ldmia (const insn32 insn)
8714{
8715 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8716 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8717 return (insn & 0xffd02000) == 0xe8900000;
8718}
8719
8720static inline bfd_boolean
8721is_thumb2_ldmdb (const insn32 insn)
8722{
8723 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8724 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8725 return (insn & 0xffd02000) == 0xe9100000;
8726}
8727
8728static inline bfd_boolean
8729is_thumb2_vldm (const insn32 insn)
8730{
8731 /* A6.5 Extension register load or store instruction
8732 A7.7.229
9239bbd3
CM		 8733 We look for SP 32-bit and DP 64-bit registers.
8734 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8735 <list> is consecutive 64-bit registers
8736 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8737 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8738 <list> is consecutive 32-bit registers
8739 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8740 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8741 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8742 return
9239bbd3
CM		 8743 (((insn & 0xfe100f00) == 0xec100b00) ||
8744 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8745 && /* (IA without !). */
8746 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8747 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8748 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8749 /* (DB with !). */
8750 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8751}
8752
8753/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8754 VLDM opcode and:
8755 - computes the number and the mode of memory accesses
8756 - decides if the replacement should be done:
8757 . replaces only if > 8-word accesses
8758 . or (testing purposes only) replaces all accesses. */
8759
8760static bfd_boolean
8761stm32l4xx_need_create_replacing_stub (const insn32 insn,
8762 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8763{
9239bbd3 8764 int nb_words = 0;
a504d23a
LA		 8765
8766 /* The field encoding the register list is the same for both LDMIA
8767 and LDMDB encodings. */
8768 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8769 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8770 else if (is_thumb2_vldm (insn))
9239bbd3 8771 nb_words = (insn & 0xff);
a504d23a
LA		 8772
8773 /* DEFAULT mode accounts for the real bug condition situation,
8774 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8775 return
9239bbd3 8776 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8777 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8778}
8779
8780/* Look for potentially-troublesome code sequences which might trigger
8781 the STM STM32L4XX erratum. */
8782
8783bfd_boolean
8784bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8785 struct bfd_link_info *link_info)
8786{
8787 asection *sec;
8788 bfd_byte *contents = NULL;
8789 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8790
8791 if (globals == NULL)
8792 return FALSE;
8793
8794 /* If we are only performing a partial link do not bother
8795 to construct any glue. */
8796 if (bfd_link_relocatable (link_info))
8797 return TRUE;
8798
8799 /* Skip if this bfd does not correspond to an ELF image. */
8800 if (! is_arm_elf (abfd))
8801 return TRUE;
8802
8803 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8804 return TRUE;
8805
8806 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8807 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8808 return TRUE;
8809
8810 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8811 {
8812 unsigned int i, span;
8813 struct _arm_elf_section_data *sec_data;
8814
8815 /* If we don't have executable progbits, we're not interested in this
8816 section. Also skip if section is to be excluded. */
8817 if (elf_section_type (sec) != SHT_PROGBITS
8818 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8819 || (sec->flags & SEC_EXCLUDE) != 0
8820 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8821 || sec->output_section == bfd_abs_section_ptr
8822 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8823 continue;
8824
8825 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8826
a504d23a
LA		 8827 if (sec_data->mapcount == 0)
8828 continue;
c7b8f16e 8829
a504d23a
LA		 8830 if (elf_section_data (sec)->this_hdr.contents != NULL)
8831 contents = elf_section_data (sec)->this_hdr.contents;
8832 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8833 goto error_return;
c7b8f16e 8834
a504d23a
LA		 8835 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8836 elf32_arm_compare_mapping);
c7b8f16e 8837
a504d23a
LA		 8838 for (span = 0; span < sec_data->mapcount; span++)
8839 {
8840 unsigned int span_start = sec_data->map[span].vma;
8841 unsigned int span_end = (span == sec_data->mapcount - 1)
8842 ? sec->size : sec_data->map[span + 1].vma;
8843 char span_type = sec_data->map[span].type;
8844 int itblock_current_pos = 0;
c7b8f16e 8845
a504d23a
LA		 8846 /* Only Thumb2 mode need be supported with this CM4 specific
8847 code, we should not encounter any arm mode eg span_type
8848 != 'a'. */
8849 if (span_type != 't')
8850 continue;
c7b8f16e 8851
a504d23a
LA		 8852 for (i = span_start; i < span_end;)
8853 {
8854 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8855 bfd_boolean insn_32bit = FALSE;
8856 bfd_boolean is_ldm = FALSE;
8857 bfd_boolean is_vldm = FALSE;
8858 bfd_boolean is_not_last_in_it_block = FALSE;
8859
8860 /* The first 16-bits of all 32-bit thumb2 instructions start
8861 with opcode[15..13]=0b111 and the encoded op1 can be anything
8862 except opcode[12..11]!=0b00.
8863 See 32-bit Thumb instruction encoding. */
8864 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8865 insn_32bit = TRUE;
c7b8f16e 8866
a504d23a
LA		 8867 /* Compute the predicate that tells if the instruction
8868 is concerned by the IT block
8869 - Creates an error if there is a ldm that is not
8870 last in the IT block thus cannot be replaced
8871 - Otherwise we can create a branch at the end of the
8872 IT block, it will be controlled naturally by IT
8873 with the proper pseudo-predicate
8874 - So the only interesting predicate is the one that
8875 tells that we are not on the last item of an IT
8876 block. */
8877 if (itblock_current_pos != 0)
8878 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8879
a504d23a
LA		 8880 if (insn_32bit)
8881 {
8882 /* Load the rest of the insn (in manual-friendly order). */
8883 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8884 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8885 is_vldm = is_thumb2_vldm (insn);
8886
8887 /* Veneers are created for (v)ldm depending on
8888 option flags and memory accesses conditions; but
8889 if the instruction is not the last instruction of
8890 an IT block, we cannot create a jump there, so we
8891 bail out. */
5025eb7c
AO		 8892 if ((is_ldm || is_vldm)
8893 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8894 (insn, globals->stm32l4xx_fix))
8895 {
8896 if (is_not_last_in_it_block)
8897 {
4eca0228 8898 _bfd_error_handler
695344c0 8899 /* xgettext:c-format */
871b3ab2 8900 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8901 " in non-last IT block instruction:"
8902 " STM32L4XX veneer cannot be generated; "
8903 "use gcc option -mrestrict-it to generate"
8904 " only one instruction per IT block"),
d42c267e 8905 abfd, sec, i);
a504d23a
LA		 8906 }
8907 else
8908 {
8909 elf32_stm32l4xx_erratum_list *newerr =
8910 (elf32_stm32l4xx_erratum_list *)
8911 bfd_zmalloc
8912 (sizeof (elf32_stm32l4xx_erratum_list));
8913
8914 elf32_arm_section_data (sec)
8915 ->stm32l4xx_erratumcount += 1;
8916 newerr->u.b.insn = insn;
8917 /* We create only thumb branches. */
8918 newerr->type =
8919 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8920 record_stm32l4xx_erratum_veneer
8921 (link_info, newerr, abfd, sec,
8922 i,
8923 is_ldm ?
8924 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8925 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8926 newerr->vma = -1;
8927 newerr->next = sec_data->stm32l4xx_erratumlist;
8928 sec_data->stm32l4xx_erratumlist = newerr;
8929 }
8930 }
8931 }
8932 else
8933 {
8934 /* A7.7.37 IT p208
8935 IT blocks are only encoded in T1
8936 Encoding T1: IT{x{y{z}}} <firstcond>
8937 1 0 1 1 - 1 1 1 1 - firstcond - mask
8938 if mask = '0000' then see 'related encodings'
8939 We don't deal with UNPREDICTABLE, just ignore these.
8940 There can be no nested IT blocks so an IT block
8941 is naturally a new one for which it is worth
8942 computing its size. */
5025eb7c
AO		 8943 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8944 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8945 /* If we have a new IT block we compute its size. */
8946 if (is_newitblock)
8947 {
8948 /* Compute the number of instructions controlled
8949 by the IT block, it will be used to decide
8950 whether we are inside an IT block or not. */
8951 unsigned int mask = insn & 0x000f;
8952 itblock_current_pos = 4 - ctz (mask);
8953 }
8954 }
8955
8956 i += insn_32bit ? 4 : 2;
99059e56
RM		 8957 }
8958 }
a504d23a
LA		 8959
8960 if (contents != NULL
8961 && elf_section_data (sec)->this_hdr.contents != contents)
8962 free (contents);
8963 contents = NULL;
c7b8f16e 8964 }
906e58ca 8965
a504d23a
LA		 8966 return TRUE;
8967
8968error_return:
8969 if (contents != NULL
8970 && elf_section_data (sec)->this_hdr.contents != contents)
8971 free (contents);
c7b8f16e 8972
a504d23a
LA		 8973 return FALSE;
8974}
c7b8f16e 8975
eb043451
PB		 8976/* Set target relocation values needed during linking. */
8977
8978void
68c39892 8979bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 8980 struct bfd_link_info *link_info,
68c39892 8981 struct elf32_arm_params *params)
eb043451
PB		 8982{
8983 struct elf32_arm_link_hash_table *globals;
8984
8985 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8986 if (globals == NULL)
8987 return;
eb043451 8988
68c39892 8989 globals->target1_is_rel = params->target1_is_rel;
29e9b073
CL		 8990 if (globals->fdpic_p)
8991 globals->target2_reloc = R_ARM_GOT32;
8992 else if (strcmp (params->target2_type, "rel") == 0)
eb043451 8993 globals->target2_reloc = R_ARM_REL32;
68c39892 8994 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 8995 globals->target2_reloc = R_ARM_ABS32;
68c39892 8996 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 8997 globals->target2_reloc = R_ARM_GOT_PREL;
8998 else
8999 {
90b6238f 9000 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 9001 params->target2_type);
eb043451 9002 }
68c39892
TP		 9003 globals->fix_v4bx = params->fix_v4bx;
9004 globals->use_blx |= params->use_blx;
9005 globals->vfp11_fix = params->vfp11_denorm_fix;
9006 globals->stm32l4xx_fix = params->stm32l4xx_fix;
e8b09b87
CL		 9007 if (globals->fdpic_p)
9008 globals->pic_veneer = 1;
9009 else
9010 globals->pic_veneer = params->pic_veneer;
68c39892
TP		 9011 globals->fix_cortex_a8 = params->fix_cortex_a8;
9012 globals->fix_arm1176 = params->fix_arm1176;
9013 globals->cmse_implib = params->cmse_implib;
9014 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 9015
0ffa91dd 9016 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 9017 elf_arm_tdata (output_bfd)->no_enum_size_warning
9018 = params->no_enum_size_warning;
9019 elf_arm_tdata (output_bfd)->no_wchar_size_warning
9020 = params->no_wchar_size_warning;
eb043451 9021}
eb043451 9022
12a0a0fd 9023/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 9024
12a0a0fd
PB		 9025static void
9026insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
9027{
9028 bfd_vma upper;
9029 bfd_vma lower;
9030 int reloc_sign;
9031
9032 BFD_ASSERT ((offset & 1) == 0);
9033
9034 upper = bfd_get_16 (abfd, insn);
9035 lower = bfd_get_16 (abfd, insn + 2);
9036 reloc_sign = (offset < 0) ? 1 : 0;
9037 upper = (upper & ~(bfd_vma) 0x7ff)
9038 | ((offset >> 12) & 0x3ff)
9039 | (reloc_sign << 10);
906e58ca 9040 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 9041 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9042 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9043 | ((offset >> 1) & 0x7ff);
9044 bfd_put_16 (abfd, upper, insn);
9045 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 9046}
9047
9b485d32
NC		 9048/* Thumb code calling an ARM function. */
9049
252b5132 9050static int
57e8b36a 9051elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9052 const char * name,
9053 bfd * input_bfd,
9054 bfd * output_bfd,
9055 asection * input_section,
9056 bfd_byte * hit_data,
9057 asection * sym_sec,
9058 bfd_vma offset,
9059 bfd_signed_vma addend,
9060 bfd_vma val,
f2a9dd69 9061 char **error_message)
252b5132 9062{
bcbdc74c 9063 asection * s = 0;
dc810e39 9064 bfd_vma my_offset;
252b5132 9065 long int ret_offset;
bcbdc74c
NC		 9066 struct elf_link_hash_entry * myh;
9067 struct elf32_arm_link_hash_table * globals;
252b5132 9068
f2a9dd69 9069 myh = find_thumb_glue (info, name, error_message);
252b5132 9070 if (myh == NULL)
b34976b6 9071 return FALSE;
252b5132
RH		 9072
9073 globals = elf32_arm_hash_table (info);
252b5132
RH		 9074 BFD_ASSERT (globals != NULL);
9075 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9076
9077 my_offset = myh->root.u.def.value;
9078
3d4d4302
AM		 9079 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9080 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 9081
9082 BFD_ASSERT (s != NULL);
9083 BFD_ASSERT (s->contents != NULL);
9084 BFD_ASSERT (s->output_section != NULL);
9085
9086 if ((my_offset & 0x01) == 0x01)
9087 {
9088 if (sym_sec != NULL
9089 && sym_sec->owner != NULL
9090 && !INTERWORK_FLAG (sym_sec->owner))
9091 {
4eca0228 9092 _bfd_error_handler
90b6238f
AM		 9093 (_("%pB(%s): warning: interworking not enabled;"
9094 " first occurrence: %pB: %s call to %s"),
9095 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 9096
b34976b6 9097 return FALSE;
252b5132
RH		 9098 }
9099
9100 --my_offset;
9101 myh->root.u.def.value = my_offset;
9102
52ab56c2
PB		 9103 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9104 s->contents + my_offset);
252b5132 9105
52ab56c2
PB		 9106 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9107 s->contents + my_offset + 2);
252b5132
RH		 9108
9109 ret_offset =
9b485d32
NC		 9110 /* Address of destination of the stub. */
9111 ((bfd_signed_vma) val)
252b5132 9112 - ((bfd_signed_vma)
57e8b36a
NC		 9113 /* Offset from the start of the current section
9114 to the start of the stubs. */
9b485d32
NC		 9115 (s->output_offset
9116 /* Offset of the start of this stub from the start of the stubs. */
9117 + my_offset
9118 /* Address of the start of the current section. */
9119 + s->output_section->vma)
9120 /* The branch instruction is 4 bytes into the stub. */
9121 + 4
9122 /* ARM branches work from the pc of the instruction + 8. */
9123 + 8);
252b5132 9124
52ab56c2
PB		 9125 put_arm_insn (globals, output_bfd,
9126 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9127 s->contents + my_offset + 4);
252b5132
RH		 9128 }
9129
9130 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9131
427bfd90
NC		 9132 /* Now go back and fix up the original BL insn to point to here. */
9133 ret_offset =
9134 /* Address of where the stub is located. */
9135 (s->output_section->vma + s->output_offset + my_offset)
9136 /* Address of where the BL is located. */
57e8b36a
NC		 9137 - (input_section->output_section->vma + input_section->output_offset
9138 + offset)
427bfd90
NC		 9139 /* Addend in the relocation. */
9140 - addend
9141 /* Biassing for PC-relative addressing. */
9142 - 8;
252b5132 9143
12a0a0fd 9144 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 9145
b34976b6 9146 return TRUE;
252b5132
RH		 9147}
9148
a4fd1a8e 9149/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 9150
a4fd1a8e
PB		 9151static struct elf_link_hash_entry *
9152elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9153 const char * name,
9154 bfd * input_bfd,
9155 bfd * output_bfd,
9156 asection * sym_sec,
9157 bfd_vma val,
9158 asection * s,
9159 char ** error_message)
252b5132 9160{
dc810e39 9161 bfd_vma my_offset;
252b5132 9162 long int ret_offset;
bcbdc74c
NC		 9163 struct elf_link_hash_entry * myh;
9164 struct elf32_arm_link_hash_table * globals;
252b5132 9165
f2a9dd69 9166 myh = find_arm_glue (info, name, error_message);
252b5132 9167 if (myh == NULL)
a4fd1a8e 9168 return NULL;
252b5132
RH		 9169
9170 globals = elf32_arm_hash_table (info);
252b5132
RH		 9171 BFD_ASSERT (globals != NULL);
9172 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9173
9174 my_offset = myh->root.u.def.value;
252b5132
RH		 9175
9176 if ((my_offset & 0x01) == 0x01)
9177 {
9178 if (sym_sec != NULL
9179 && sym_sec->owner != NULL
9180 && !INTERWORK_FLAG (sym_sec->owner))
9181 {
4eca0228 9182 _bfd_error_handler
90b6238f
AM		 9183 (_("%pB(%s): warning: interworking not enabled;"
9184 " first occurrence: %pB: %s call to %s"),
9185 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 9186 }
9b485d32 9187
252b5132
RH		 9188 --my_offset;
9189 myh->root.u.def.value = my_offset;
9190
0e1862bb
L		 9191 if (bfd_link_pic (info)
9192 || globals->root.is_relocatable_executable
27e55c4d 9193 || globals->pic_veneer)
8f6277f5
PB		 9194 {
9195 /* For relocatable objects we can't use absolute addresses,
9196 so construct the address from a relative offset. */
9197 /* TODO: If the offset is small it's probably worth
9198 constructing the address with adds. */
52ab56c2
PB		 9199 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9200 s->contents + my_offset);
9201 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9202 s->contents + my_offset + 4);
9203 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9204 s->contents + my_offset + 8);
8f6277f5
PB		 9205 /* Adjust the offset by 4 for the position of the add,
9206 and 8 for the pipeline offset. */
9207 ret_offset = (val - (s->output_offset
9208 + s->output_section->vma
9209 + my_offset + 12))
9210 | 1;
9211 bfd_put_32 (output_bfd, ret_offset,
9212 s->contents + my_offset + 12);
9213 }
26079076
PB		 9214 else if (globals->use_blx)
9215 {
9216 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9217 s->contents + my_offset);
9218
9219 /* It's a thumb address. Add the low order bit. */
9220 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9221 s->contents + my_offset + 4);
9222 }
8f6277f5
PB		 9223 else
9224 {
52ab56c2
PB		 9225 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9226 s->contents + my_offset);
252b5132 9227
52ab56c2
PB		 9228 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9229 s->contents + my_offset + 4);
252b5132 9230
8f6277f5
PB		 9231 /* It's a thumb address. Add the low order bit. */
9232 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9233 s->contents + my_offset + 8);
8029a119
NC		 9234
9235 my_offset += 12;
8f6277f5 9236 }
252b5132
RH		 9237 }
9238
9239 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9240
a4fd1a8e
PB		 9241 return myh;
9242}
9243
9244/* Arm code calling a Thumb function. */
9245
9246static int
9247elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9248 const char * name,
9249 bfd * input_bfd,
9250 bfd * output_bfd,
9251 asection * input_section,
9252 bfd_byte * hit_data,
9253 asection * sym_sec,
9254 bfd_vma offset,
9255 bfd_signed_vma addend,
9256 bfd_vma val,
f2a9dd69 9257 char **error_message)
a4fd1a8e
PB		 9258{
9259 unsigned long int tmp;
9260 bfd_vma my_offset;
9261 asection * s;
9262 long int ret_offset;
9263 struct elf_link_hash_entry * myh;
9264 struct elf32_arm_link_hash_table * globals;
9265
9266 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9267 BFD_ASSERT (globals != NULL);
9268 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9269
3d4d4302
AM		 9270 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9271 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9272 BFD_ASSERT (s != NULL);
9273 BFD_ASSERT (s->contents != NULL);
9274 BFD_ASSERT (s->output_section != NULL);
9275
9276 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9277 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9278 if (!myh)
9279 return FALSE;
9280
9281 my_offset = myh->root.u.def.value;
252b5132
RH		 9282 tmp = bfd_get_32 (input_bfd, hit_data);
9283 tmp = tmp & 0xFF000000;
9284
9b485d32 9285 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9286 ret_offset = (s->output_offset
9287 + my_offset
9288 + s->output_section->vma
9289 - (input_section->output_offset
9290 + input_section->output_section->vma
9291 + offset + addend)
9292 - 8);
9a5aca8c 9293
252b5132
RH		 9294 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9295
dc810e39 9296 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9297
b34976b6 9298 return TRUE;
252b5132
RH		 9299}
9300
a4fd1a8e
PB		 9301/* Populate Arm stub for an exported Thumb function. */
9302
9303static bfd_boolean
9304elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9305{
9306 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9307 asection * s;
9308 struct elf_link_hash_entry * myh;
9309 struct elf32_arm_link_hash_entry *eh;
9310 struct elf32_arm_link_hash_table * globals;
9311 asection *sec;
9312 bfd_vma val;
f2a9dd69 9313 char *error_message;
a4fd1a8e 9314
906e58ca 9315 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9316 /* Allocate stubs for exported Thumb functions on v4t. */
9317 if (eh->export_glue == NULL)
9318 return TRUE;
9319
9320 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9321 BFD_ASSERT (globals != NULL);
9322 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9323
3d4d4302
AM		 9324 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9325 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9326 BFD_ASSERT (s != NULL);
9327 BFD_ASSERT (s->contents != NULL);
9328 BFD_ASSERT (s->output_section != NULL);
9329
9330 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9331
9332 BFD_ASSERT (sec->output_section != NULL);
9333
a4fd1a8e
PB		 9334 val = eh->export_glue->root.u.def.value + sec->output_offset
9335 + sec->output_section->vma;
8029a119 9336
a4fd1a8e
PB		 9337 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9338 h->root.u.def.section->owner,
f2a9dd69
DJ		 9339 globals->obfd, sec, val, s,
9340 &error_message);
a4fd1a8e
PB		 9341 BFD_ASSERT (myh);
9342 return TRUE;
9343}
9344
845b51d6
PB		 9345/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9346
9347static bfd_vma
9348elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9349{
9350 bfd_byte *p;
9351 bfd_vma glue_addr;
9352 asection *s;
9353 struct elf32_arm_link_hash_table *globals;
9354
9355 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9356 BFD_ASSERT (globals != NULL);
9357 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9358
3d4d4302
AM		 9359 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9360 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9361 BFD_ASSERT (s != NULL);
9362 BFD_ASSERT (s->contents != NULL);
9363 BFD_ASSERT (s->output_section != NULL);
9364
9365 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9366
9367 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9368
9369 if ((globals->bx_glue_offset[reg] & 1) == 0)
9370 {
9371 p = s->contents + glue_addr;
9372 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9373 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9374 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9375 globals->bx_glue_offset[reg] |= 1;
9376 }
9377
9378 return glue_addr + s->output_section->vma + s->output_offset;
9379}
9380
a4fd1a8e
PB		 9381/* Generate Arm stubs for exported Thumb symbols. */
9382static void
906e58ca 9383elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9384 struct bfd_link_info *link_info)
9385{
9386 struct elf32_arm_link_hash_table * globals;
9387
8029a119
NC		 9388 if (link_info == NULL)
9389 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9390 return;
9391
9392 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9393 if (globals == NULL)
9394 return;
9395
84c08195
PB		 9396 /* If blx is available then exported Thumb symbols are OK and there is
9397 nothing to do. */
a4fd1a8e
PB		 9398 if (globals->use_blx)
9399 return;
9400
9401 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9402 link_info);
9403}
9404
47beaa6a
RS		 9405/* Reserve space for COUNT dynamic relocations in relocation selection
9406 SRELOC. */
9407
9408static void
9409elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9410 bfd_size_type count)
9411{
9412 struct elf32_arm_link_hash_table *htab;
9413
9414 htab = elf32_arm_hash_table (info);
9415 BFD_ASSERT (htab->root.dynamic_sections_created);
9416 if (sreloc == NULL)
9417 abort ();
9418 sreloc->size += RELOC_SIZE (htab) * count;
9419}
9420
34e77a92
RS		 9421/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9422 dynamic, the relocations should go in SRELOC, otherwise they should
9423 go in the special .rel.iplt section. */
9424
9425static void
9426elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9427 bfd_size_type count)
9428{
9429 struct elf32_arm_link_hash_table *htab;
9430
9431 htab = elf32_arm_hash_table (info);
9432 if (!htab->root.dynamic_sections_created)
9433 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9434 else
9435 {
9436 BFD_ASSERT (sreloc != NULL);
9437 sreloc->size += RELOC_SIZE (htab) * count;
9438 }
9439}
9440
47beaa6a
RS		 9441/* Add relocation REL to the end of relocation section SRELOC. */
9442
9443static void
9444elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9445 asection *sreloc, Elf_Internal_Rela *rel)
9446{
9447 bfd_byte *loc;
9448 struct elf32_arm_link_hash_table *htab;
9449
9450 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9451 if (!htab->root.dynamic_sections_created
9452 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9453 sreloc = htab->root.irelplt;
47beaa6a
RS		 9454 if (sreloc == NULL)
9455 abort ();
9456 loc = sreloc->contents;
9457 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9458 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9459 abort ();
9460 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9461}
9462
34e77a92
RS		 9463/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9464 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9465 to .plt. */
9466
9467static void
9468elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9469 bfd_boolean is_iplt_entry,
9470 union gotplt_union *root_plt,
9471 struct arm_plt_info *arm_plt)
9472{
9473 struct elf32_arm_link_hash_table *htab;
9474 asection *splt;
9475 asection *sgotplt;
9476
9477 htab = elf32_arm_hash_table (info);
9478
9479 if (is_iplt_entry)
9480 {
9481 splt = htab->root.iplt;
9482 sgotplt = htab->root.igotplt;
9483
99059e56
RM		 9484 /* NaCl uses a special first entry in .iplt too. */
9485 if (htab->nacl_p && splt->size == 0)
9486 splt->size += htab->plt_header_size;
9487
34e77a92
RS		 9488 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9489 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9490 }
9491 else
9492 {
9493 splt = htab->root.splt;
9494 sgotplt = htab->root.sgotplt;
9495
7801f98f
CL		 9496 if (htab->fdpic_p)
9497 {
9498 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9499 /* For lazy binding, relocations will be put into .rel.plt, in
9500 .rel.got otherwise. */
9501 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9502 if (info->flags & DF_BIND_NOW)
9503 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9504 else
9505 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9506 }
9507 else
9508 {
9509 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9510 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9511 }
34e77a92
RS		 9512
9513 /* If this is the first .plt entry, make room for the special
9514 first entry. */
9515 if (splt->size == 0)
9516 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9517
9518 htab->next_tls_desc_index++;
34e77a92
RS		 9519 }
9520
9521 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9522 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9523 splt->size += PLT_THUMB_STUB_SIZE;
9524 root_plt->offset = splt->size;
9525 splt->size += htab->plt_entry_size;
9526
9527 if (!htab->symbian_p)
9528 {
9529 /* We also need to make an entry in the .got.plt section, which
9530 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9531 if (is_iplt_entry)
9532 arm_plt->got_offset = sgotplt->size;
9533 else
9534 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
7801f98f
CL		 9535 if (htab->fdpic_p)
9536 /* Function descriptor takes 64 bits in GOT. */
4b24dd1a 9537 sgotplt->size += 8;
7801f98f
CL		 9538 else
9539 sgotplt->size += 4;
34e77a92
RS		 9540 }
9541}
9542
b38cadfb
NC		 9543static bfd_vma
9544arm_movw_immediate (bfd_vma value)
9545{
9546 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9547}
9548
9549static bfd_vma
9550arm_movt_immediate (bfd_vma value)
9551{
9552 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9553}
9554
34e77a92
RS		 9555/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9556 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9557 Otherwise, DYNINDX is the index of the symbol in the dynamic
9558 symbol table and SYM_VALUE is undefined.
9559
9560 ROOT_PLT points to the offset of the PLT entry from the start of its
9561 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9562 bookkeeping information.
34e77a92 9563
57460bcf
NC		 9564 Returns FALSE if there was a problem. */
9565
9566static bfd_boolean
34e77a92
RS		 9567elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9568 union gotplt_union *root_plt,
9569 struct arm_plt_info *arm_plt,
9570 int dynindx, bfd_vma sym_value)
9571{
9572 struct elf32_arm_link_hash_table *htab;
9573 asection *sgot;
9574 asection *splt;
9575 asection *srel;
9576 bfd_byte *loc;
9577 bfd_vma plt_index;
9578 Elf_Internal_Rela rel;
9579 bfd_vma plt_header_size;
9580 bfd_vma got_header_size;
9581
9582 htab = elf32_arm_hash_table (info);
9583
9584 /* Pick the appropriate sections and sizes. */
9585 if (dynindx == -1)
9586 {
9587 splt = htab->root.iplt;
9588 sgot = htab->root.igotplt;
9589 srel = htab->root.irelplt;
9590
9591 /* There are no reserved entries in .igot.plt, and no special
9592 first entry in .iplt. */
9593 got_header_size = 0;
9594 plt_header_size = 0;
9595 }
9596 else
9597 {
9598 splt = htab->root.splt;
9599 sgot = htab->root.sgotplt;
9600 srel = htab->root.srelplt;
9601
9602 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9603 plt_header_size = htab->plt_header_size;
9604 }
9605 BFD_ASSERT (splt != NULL && srel != NULL);
9606
9607 /* Fill in the entry in the procedure linkage table. */
9608 if (htab->symbian_p)
9609 {
9610 BFD_ASSERT (dynindx >= 0);
9611 put_arm_insn (htab, output_bfd,
9612 elf32_arm_symbian_plt_entry[0],
9613 splt->contents + root_plt->offset);
9614 bfd_put_32 (output_bfd,
9615 elf32_arm_symbian_plt_entry[1],
9616 splt->contents + root_plt->offset + 4);
9617
9618 /* Fill in the entry in the .rel.plt section. */
9619 rel.r_offset = (splt->output_section->vma
9620 + splt->output_offset
9621 + root_plt->offset + 4);
9622 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9623
9624 /* Get the index in the procedure linkage table which
9625 corresponds to this symbol. This is the index of this symbol
9626 in all the symbols for which we are making plt entries. The
9627 first entry in the procedure linkage table is reserved. */
9628 plt_index = ((root_plt->offset - plt_header_size)
9629 / htab->plt_entry_size);
9630 }
9631 else
9632 {
9633 bfd_vma got_offset, got_address, plt_address;
9634 bfd_vma got_displacement, initial_got_entry;
9635 bfd_byte * ptr;
9636
9637 BFD_ASSERT (sgot != NULL);
9638
9639 /* Get the offset into the .(i)got.plt table of the entry that
9640 corresponds to this function. */
9641 got_offset = (arm_plt->got_offset & -2);
9642
9643 /* Get the index in the procedure linkage table which
9644 corresponds to this symbol. This is the index of this symbol
9645 in all the symbols for which we are making plt entries.
9646 After the reserved .got.plt entries, all symbols appear in
9647 the same order as in .plt. */
7801f98f 9648 if (htab->fdpic_p)
4b24dd1a
AM		 9649 /* Function descriptor takes 8 bytes. */
9650 plt_index = (got_offset - got_header_size) / 8;
7801f98f 9651 else
4b24dd1a 9652 plt_index = (got_offset - got_header_size) / 4;
34e77a92
RS		 9653
9654 /* Calculate the address of the GOT entry. */
9655 got_address = (sgot->output_section->vma
9656 + sgot->output_offset
9657 + got_offset);
9658
9659 /* ...and the address of the PLT entry. */
9660 plt_address = (splt->output_section->vma
9661 + splt->output_offset
9662 + root_plt->offset);
9663
9664 ptr = splt->contents + root_plt->offset;
0e1862bb 9665 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9666 {
9667 unsigned int i;
9668 bfd_vma val;
9669
9670 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9671 {
9672 val = elf32_arm_vxworks_shared_plt_entry[i];
9673 if (i == 2)
9674 val |= got_address - sgot->output_section->vma;
9675 if (i == 5)
9676 val |= plt_index * RELOC_SIZE (htab);
9677 if (i == 2 || i == 5)
9678 bfd_put_32 (output_bfd, val, ptr);
9679 else
9680 put_arm_insn (htab, output_bfd, val, ptr);
9681 }
9682 }
9683 else if (htab->vxworks_p)
9684 {
9685 unsigned int i;
9686 bfd_vma val;
9687
9688 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9689 {
9690 val = elf32_arm_vxworks_exec_plt_entry[i];
9691 if (i == 2)
9692 val |= got_address;
9693 if (i == 4)
9694 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9695 if (i == 5)
9696 val |= plt_index * RELOC_SIZE (htab);
9697 if (i == 2 || i == 5)
9698 bfd_put_32 (output_bfd, val, ptr);
9699 else
9700 put_arm_insn (htab, output_bfd, val, ptr);
9701 }
9702
9703 loc = (htab->srelplt2->contents
9704 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9705
9706 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9707 referencing the GOT for this PLT entry. */
9708 rel.r_offset = plt_address + 8;
9709 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9710 rel.r_addend = got_offset;
9711 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9712 loc += RELOC_SIZE (htab);
9713
9714 /* Create the R_ARM_ABS32 relocation referencing the
9715 beginning of the PLT for this GOT entry. */
9716 rel.r_offset = got_address;
9717 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9718 rel.r_addend = 0;
9719 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9720 }
b38cadfb
NC		 9721 else if (htab->nacl_p)
9722 {
9723 /* Calculate the displacement between the PLT slot and the
9724 common tail that's part of the special initial PLT slot. */
6034aab8 9725 int32_t tail_displacement
b38cadfb
NC		 9726 = ((splt->output_section->vma + splt->output_offset
9727 + ARM_NACL_PLT_TAIL_OFFSET)
9728 - (plt_address + htab->plt_entry_size + 4));
9729 BFD_ASSERT ((tail_displacement & 3) == 0);
9730 tail_displacement >>= 2;
9731
9732 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9733 || (-tail_displacement & 0xff000000) == 0);
9734
9735 /* Calculate the displacement between the PLT slot and the entry
9736 in the GOT. The offset accounts for the value produced by
9737 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9738 got_displacement = (got_address
99059e56 9739 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9740
9741 /* NaCl does not support interworking at all. */
9742 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9743
9744 put_arm_insn (htab, output_bfd,
9745 elf32_arm_nacl_plt_entry[0]
9746 | arm_movw_immediate (got_displacement),
9747 ptr + 0);
9748 put_arm_insn (htab, output_bfd,
9749 elf32_arm_nacl_plt_entry[1]
9750 | arm_movt_immediate (got_displacement),
9751 ptr + 4);
9752 put_arm_insn (htab, output_bfd,
9753 elf32_arm_nacl_plt_entry[2],
9754 ptr + 8);
9755 put_arm_insn (htab, output_bfd,
9756 elf32_arm_nacl_plt_entry[3]
9757 | (tail_displacement & 0x00ffffff),
9758 ptr + 12);
9759 }
7801f98f
CL		 9760 else if (htab->fdpic_p)
9761 {
59029f57
CL		 9762 const bfd_vma *plt_entry = using_thumb_only(htab)
9763 ? elf32_arm_fdpic_thumb_plt_entry
9764 : elf32_arm_fdpic_plt_entry;
9765
7801f98f
CL		 9766 /* Fill-up Thumb stub if needed. */
9767 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9768 {
9769 put_thumb_insn (htab, output_bfd,
9770 elf32_arm_plt_thumb_stub[0], ptr - 4);
9771 put_thumb_insn (htab, output_bfd,
9772 elf32_arm_plt_thumb_stub[1], ptr - 2);
9773 }
59029f57
CL		 9774 /* As we are using 32 bit instructions even for the Thumb
9775 version, we have to use 'put_arm_insn' instead of
9776 'put_thumb_insn'. */
9777 put_arm_insn(htab, output_bfd, plt_entry[0], ptr + 0);
9778 put_arm_insn(htab, output_bfd, plt_entry[1], ptr + 4);
9779 put_arm_insn(htab, output_bfd, plt_entry[2], ptr + 8);
9780 put_arm_insn(htab, output_bfd, plt_entry[3], ptr + 12);
7801f98f
CL		 9781 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9782
9783 if (!(info->flags & DF_BIND_NOW))
9784 {
9785 /* funcdesc_value_reloc_offset. */
9786 bfd_put_32 (output_bfd,
9787 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9788 ptr + 20);
59029f57
CL		 9789 put_arm_insn(htab, output_bfd, plt_entry[6], ptr + 24);
9790 put_arm_insn(htab, output_bfd, plt_entry[7], ptr + 28);
9791 put_arm_insn(htab, output_bfd, plt_entry[8], ptr + 32);
9792 put_arm_insn(htab, output_bfd, plt_entry[9], ptr + 36);
7801f98f
CL		 9793 }
9794 }
57460bcf
NC		 9795 else if (using_thumb_only (htab))
9796 {
eed94f8f 9797 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9798 if (!using_thumb2 (htab))
eed94f8f
NC		 9799 {
9800 /* FIXME: We ought to be able to generate thumb-1 PLT
9801 instructions... */
90b6238f 9802 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9803 output_bfd);
9804 return FALSE;
9805 }
57460bcf 9806
eed94f8f
NC		 9807 /* Calculate the displacement between the PLT slot and the entry in
9808 the GOT. The 12-byte offset accounts for the value produced by
9809 adding to pc in the 3rd instruction of the PLT stub. */
9810 got_displacement = got_address - (plt_address + 12);
9811
9812 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9813 instead of 'put_thumb_insn'. */
9814 put_arm_insn (htab, output_bfd,
9815 elf32_thumb2_plt_entry[0]
9816 | ((got_displacement & 0x000000ff) << 16)
9817 | ((got_displacement & 0x00000700) << 20)
9818 | ((got_displacement & 0x00000800) >> 1)
9819 | ((got_displacement & 0x0000f000) >> 12),
9820 ptr + 0);
9821 put_arm_insn (htab, output_bfd,
9822 elf32_thumb2_plt_entry[1]
9823 | ((got_displacement & 0x00ff0000) )
9824 | ((got_displacement & 0x07000000) << 4)
9825 | ((got_displacement & 0x08000000) >> 17)
9826 | ((got_displacement & 0xf0000000) >> 28),
9827 ptr + 4);
9828 put_arm_insn (htab, output_bfd,
9829 elf32_thumb2_plt_entry[2],
9830 ptr + 8);
9831 put_arm_insn (htab, output_bfd,
9832 elf32_thumb2_plt_entry[3],
9833 ptr + 12);
57460bcf 9834 }
34e77a92
RS		 9835 else
9836 {
9837 /* Calculate the displacement between the PLT slot and the
9838 entry in the GOT. The eight-byte offset accounts for the
9839 value produced by adding to pc in the first instruction
9840 of the PLT stub. */
9841 got_displacement = got_address - (plt_address + 8);
9842
34e77a92
RS		 9843 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9844 {
9845 put_thumb_insn (htab, output_bfd,
9846 elf32_arm_plt_thumb_stub[0], ptr - 4);
9847 put_thumb_insn (htab, output_bfd,
9848 elf32_arm_plt_thumb_stub[1], ptr - 2);
9849 }
9850
1db37fe6
YG		 9851 if (!elf32_arm_use_long_plt_entry)
9852 {
9853 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9854
9855 put_arm_insn (htab, output_bfd,
9856 elf32_arm_plt_entry_short[0]
9857 | ((got_displacement & 0x0ff00000) >> 20),
9858 ptr + 0);
9859 put_arm_insn (htab, output_bfd,
9860 elf32_arm_plt_entry_short[1]
9861 | ((got_displacement & 0x000ff000) >> 12),
9862 ptr+ 4);
9863 put_arm_insn (htab, output_bfd,
9864 elf32_arm_plt_entry_short[2]
9865 | (got_displacement & 0x00000fff),
9866 ptr + 8);
34e77a92 9867#ifdef FOUR_WORD_PLT
1db37fe6 9868 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9869#endif
1db37fe6
YG		 9870 }
9871 else
9872 {
9873 put_arm_insn (htab, output_bfd,
9874 elf32_arm_plt_entry_long[0]
9875 | ((got_displacement & 0xf0000000) >> 28),
9876 ptr + 0);
9877 put_arm_insn (htab, output_bfd,
9878 elf32_arm_plt_entry_long[1]
9879 | ((got_displacement & 0x0ff00000) >> 20),
9880 ptr + 4);
9881 put_arm_insn (htab, output_bfd,
9882 elf32_arm_plt_entry_long[2]
9883 | ((got_displacement & 0x000ff000) >> 12),
9884 ptr+ 8);
9885 put_arm_insn (htab, output_bfd,
9886 elf32_arm_plt_entry_long[3]
9887 | (got_displacement & 0x00000fff),
9888 ptr + 12);
9889 }
34e77a92
RS		 9890 }
9891
9892 /* Fill in the entry in the .rel(a).(i)plt section. */
9893 rel.r_offset = got_address;
9894 rel.r_addend = 0;
9895 if (dynindx == -1)
9896 {
9897 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9898 The dynamic linker or static executable then calls SYM_VALUE
9899 to determine the correct run-time value of the .igot.plt entry. */
9900 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9901 initial_got_entry = sym_value;
9902 }
9903 else
9904 {
7801f98f
CL		 9905 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9906 used by PLT entry. */
9907 if (htab->fdpic_p)
9908 {
9909 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
9910 initial_got_entry = 0;
9911 }
9912 else
9913 {
9914 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9915 initial_got_entry = (splt->output_section->vma
9916 + splt->output_offset);
9917 }
34e77a92
RS		 9918 }
9919
9920 /* Fill in the entry in the global offset table. */
9921 bfd_put_32 (output_bfd, initial_got_entry,
9922 sgot->contents + got_offset);
7801f98f
CL		 9923
9924 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
9925 {
9926 /* Setup initial funcdesc value. */
9927 /* FIXME: we don't support lazy binding because there is a
9928 race condition between both words getting written and
9929 some other thread attempting to read them. The ARM
9930 architecture does not have an atomic 64 bit load/store
9931 instruction that could be used to prevent it; it is
9932 recommended that threaded FDPIC applications run with the
9933 LD_BIND_NOW environment variable set. */
9934 bfd_put_32(output_bfd, plt_address + 0x18,
9935 sgot->contents + got_offset);
9936 bfd_put_32(output_bfd, -1 /*TODO*/,
9937 sgot->contents + got_offset + 4);
9938 }
34e77a92
RS		 9939 }
9940
aba8c3de
WN		 9941 if (dynindx == -1)
9942 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9943 else
9944 {
7801f98f
CL		 9945 if (htab->fdpic_p)
9946 {
9947 /* For FDPIC we put PLT relocationss into .rel.got when not
9948 lazy binding otherwise we put them in .rel.plt. For now,
9949 we don't support lazy binding so put it in .rel.got. */
9950 if (info->flags & DF_BIND_NOW)
9951 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelgot, &rel);
9952 else
9953 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelplt, &rel);
9954 }
9955 else
9956 {
9957 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9958 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9959 }
aba8c3de 9960 }
57460bcf
NC		 9961
9962 return TRUE;
34e77a92
RS		 9963}
9964
eb043451
PB		 9965/* Some relocations map to different relocations depending on the
9966 target. Return the real relocation. */
8029a119 9967
eb043451
PB		 9968static int
9969arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9970 int r_type)
9971{
9972 switch (r_type)
9973 {
9974 case R_ARM_TARGET1:
9975 if (globals->target1_is_rel)
9976 return R_ARM_REL32;
9977 else
9978 return R_ARM_ABS32;
9979
9980 case R_ARM_TARGET2:
9981 return globals->target2_reloc;
9982
9983 default:
9984 return r_type;
9985 }
9986}
eb043451 9987
ba93b8ac
DJ		 9988/* Return the base VMA address which should be subtracted from real addresses
9989 when resolving @dtpoff relocation.
9990 This is PT_TLS segment p_vaddr. */
9991
9992static bfd_vma
9993dtpoff_base (struct bfd_link_info *info)
9994{
9995 /* If tls_sec is NULL, we should have signalled an error already. */
9996 if (elf_hash_table (info)->tls_sec == NULL)
9997 return 0;
9998 return elf_hash_table (info)->tls_sec->vma;
9999}
10000
10001/* Return the relocation value for @tpoff relocation
10002 if STT_TLS virtual address is ADDRESS. */
10003
10004static bfd_vma
10005tpoff (struct bfd_link_info *info, bfd_vma address)
10006{
10007 struct elf_link_hash_table *htab = elf_hash_table (info);
10008 bfd_vma base;
10009
10010 /* If tls_sec is NULL, we should have signalled an error already. */
10011 if (htab->tls_sec == NULL)
10012 return 0;
10013 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
10014 return address - htab->tls_sec->vma + base;
10015}
10016
00a97672
RS		 10017/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10018 VALUE is the relocation value. */
10019
10020static bfd_reloc_status_type
10021elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
10022{
10023 if (value > 0xfff)
10024 return bfd_reloc_overflow;
10025
10026 value |= bfd_get_32 (abfd, data) & 0xfffff000;
10027 bfd_put_32 (abfd, value, data);
10028 return bfd_reloc_ok;
10029}
10030
0855e32b
NS		 10031/* Handle TLS relaxations. Relaxing is possible for symbols that use
10032 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10033 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10034
10035 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10036 is to then call final_link_relocate. Return other values in the
62672b10
NS		 10037 case of error.
10038
10039 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10040 the pre-relaxed code. It would be nice if the relocs were updated
10041 to match the optimization. */
0855e32b 10042
b38cadfb 10043static bfd_reloc_status_type
0855e32b 10044elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 10045 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 10046 Elf_Internal_Rela *rel, unsigned long is_local)
10047{
10048 unsigned long insn;
b38cadfb 10049
0855e32b
NS		 10050 switch (ELF32_R_TYPE (rel->r_info))
10051 {
10052 default:
10053 return bfd_reloc_notsupported;
b38cadfb 10054
0855e32b
NS		 10055 case R_ARM_TLS_GOTDESC:
10056 if (is_local)
10057 insn = 0;
10058 else
10059 {
10060 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10061 if (insn & 1)
10062 insn -= 5; /* THUMB */
10063 else
10064 insn -= 8; /* ARM */
10065 }
10066 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10067 return bfd_reloc_continue;
10068
10069 case R_ARM_THM_TLS_DESCSEQ:
10070 /* Thumb insn. */
10071 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10072 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10073 {
10074 if (is_local)
10075 /* nop */
10076 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10077 }
10078 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10079 {
10080 if (is_local)
10081 /* nop */
10082 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10083 else
10084 /* ldr rx,[ry] */
10085 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10086 }
10087 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10088 {
10089 if (is_local)
10090 /* nop */
10091 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10092 else
10093 /* mov r0, rx */
10094 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10095 contents + rel->r_offset);
10096 }
10097 else
10098 {
10099 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10100 /* It's a 32 bit instruction, fetch the rest of it for
10101 error generation. */
10102 insn = (insn << 16)
10103 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 10104 _bfd_error_handler
695344c0 10105 /* xgettext:c-format */
2dcf00ce 10106 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10107 "unexpected %s instruction '%#lx' in TLS trampoline"),
10108 input_bfd, input_sec, (uint64_t) rel->r_offset,
10109 "Thumb", insn);
0855e32b
NS		 10110 return bfd_reloc_notsupported;
10111 }
10112 break;
b38cadfb 10113
0855e32b
NS		 10114 case R_ARM_TLS_DESCSEQ:
10115 /* arm insn. */
10116 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10117 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10118 {
10119 if (is_local)
10120 /* mov rx, ry */
10121 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10122 contents + rel->r_offset);
10123 }
10124 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10125 {
10126 if (is_local)
10127 /* nop */
10128 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10129 else
10130 /* ldr rx,[ry] */
10131 bfd_put_32 (input_bfd, insn & 0xfffff000,
10132 contents + rel->r_offset);
10133 }
10134 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10135 {
10136 if (is_local)
10137 /* nop */
10138 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10139 else
10140 /* mov r0, rx */
10141 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10142 contents + rel->r_offset);
10143 }
10144 else
10145 {
4eca0228 10146 _bfd_error_handler
695344c0 10147 /* xgettext:c-format */
2dcf00ce 10148 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10149 "unexpected %s instruction '%#lx' in TLS trampoline"),
10150 input_bfd, input_sec, (uint64_t) rel->r_offset,
10151 "ARM", insn);
0855e32b
NS		 10152 return bfd_reloc_notsupported;
10153 }
10154 break;
10155
10156 case R_ARM_TLS_CALL:
10157 /* GD->IE relaxation, turn the instruction into 'nop' or
10158 'ldr r0, [pc,r0]' */
10159 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10160 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10161 break;
b38cadfb 10162
0855e32b 10163 case R_ARM_THM_TLS_CALL:
6a631e86 10164 /* GD->IE relaxation. */
0855e32b
NS		 10165 if (!is_local)
10166 /* add r0,pc; ldr r0, [r0] */
10167 insn = 0x44786800;
60a019a0 10168 else if (using_thumb2 (globals))
0855e32b
NS		 10169 /* nop.w */
10170 insn = 0xf3af8000;
10171 else
10172 /* nop; nop */
10173 insn = 0xbf00bf00;
b38cadfb 10174
0855e32b
NS		 10175 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10176 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10177 break;
10178 }
10179 return bfd_reloc_ok;
10180}
10181
4962c51a
MS		 10182/* For a given value of n, calculate the value of G_n as required to
10183 deal with group relocations. We return it in the form of an
10184 encoded constant-and-rotation, together with the final residual. If n is
10185 specified as less than zero, then final_residual is filled with the
10186 input value and no further action is performed. */
10187
10188static bfd_vma
10189calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10190{
10191 int current_n;
10192 bfd_vma g_n;
10193 bfd_vma encoded_g_n = 0;
10194 bfd_vma residual = value; /* Also known as Y_n. */
10195
10196 for (current_n = 0; current_n <= n; current_n++)
10197 {
10198 int shift;
10199
10200 /* Calculate which part of the value to mask. */
10201 if (residual == 0)
99059e56 10202 shift = 0;
4962c51a 10203 else
99059e56
RM		 10204 {
10205 int msb;
10206
10207 /* Determine the most significant bit in the residual and
10208 align the resulting value to a 2-bit boundary. */
10209 for (msb = 30; msb >= 0; msb -= 2)
10210 if (residual & (3 << msb))
10211 break;
10212
10213 /* The desired shift is now (msb - 6), or zero, whichever
10214 is the greater. */
10215 shift = msb - 6;
10216 if (shift < 0)
10217 shift = 0;
10218 }
4962c51a
MS		 10219
10220 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10221 g_n = residual & (0xff << shift);
10222 encoded_g_n = (g_n >> shift)
99059e56 10223 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 10224
10225 /* Calculate the residual for the next time around. */
10226 residual &= ~g_n;
10227 }
10228
10229 *final_residual = residual;
10230
10231 return encoded_g_n;
10232}
10233
10234/* Given an ARM instruction, determine whether it is an ADD or a SUB.
10235 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 10236
4962c51a 10237static int
906e58ca 10238identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 10239{
10240 int opcode = insn & 0x1e00000;
10241
10242 if (opcode == 1 << 23) /* ADD */
10243 return 1;
10244
10245 if (opcode == 1 << 22) /* SUB */
10246 return -1;
10247
10248 return 0;
10249}
10250
252b5132 10251/* Perform a relocation as part of a final link. */
9b485d32 10252
252b5132 10253static bfd_reloc_status_type
07d6d2b8
AM		 10254elf32_arm_final_link_relocate (reloc_howto_type * howto,
10255 bfd * input_bfd,
10256 bfd * output_bfd,
10257 asection * input_section,
10258 bfd_byte * contents,
10259 Elf_Internal_Rela * rel,
10260 bfd_vma value,
10261 struct bfd_link_info * info,
10262 asection * sym_sec,
10263 const char * sym_name,
10264 unsigned char st_type,
10265 enum arm_st_branch_type branch_type,
0945cdfd 10266 struct elf_link_hash_entry * h,
07d6d2b8
AM		 10267 bfd_boolean * unresolved_reloc_p,
10268 char ** error_message)
10269{
10270 unsigned long r_type = howto->type;
10271 unsigned long r_symndx;
10272 bfd_byte * hit_data = contents + rel->r_offset;
10273 bfd_vma * local_got_offsets;
10274 bfd_vma * local_tlsdesc_gotents;
10275 asection * sgot;
10276 asection * splt;
10277 asection * sreloc = NULL;
10278 asection * srelgot;
10279 bfd_vma addend;
10280 bfd_signed_vma signed_addend;
10281 unsigned char dynreloc_st_type;
10282 bfd_vma dynreloc_value;
ba96a88f 10283 struct elf32_arm_link_hash_table * globals;
34e77a92 10284 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 10285 union gotplt_union *root_plt;
10286 struct arm_plt_info *arm_plt;
10287 bfd_vma plt_offset;
10288 bfd_vma gotplt_offset;
10289 bfd_boolean has_iplt_entry;
10290 bfd_boolean resolved_to_zero;
f21f3fe0 10291
9c504268 10292 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 10293 if (globals == NULL)
10294 return bfd_reloc_notsupported;
9c504268 10295
0ffa91dd 10296 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 10297 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 10298
10299 /* Some relocation types map to different relocations depending on the
9c504268 10300 target. We pick the right one here. */
eb043451 10301 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 10302
10303 /* It is possible to have linker relaxations on some TLS access
10304 models. Update our information here. */
10305 r_type = elf32_arm_tls_transition (info, r_type, h);
10306
eb043451
PB		 10307 if (r_type != howto->type)
10308 howto = elf32_arm_howto_from_type (r_type);
9c504268 10309
34e77a92 10310 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 10311 sgot = globals->root.sgot;
252b5132 10312 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 10313 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10314
34e77a92
RS		 10315 if (globals->root.dynamic_sections_created)
10316 srelgot = globals->root.srelgot;
10317 else
10318 srelgot = NULL;
10319
252b5132
RH		 10320 r_symndx = ELF32_R_SYM (rel->r_info);
10321
4e7fd91e 10322 if (globals->use_rel)
ba96a88f 10323 {
4e7fd91e
PB		 10324 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
10325
10326 if (addend & ((howto->src_mask + 1) >> 1))
10327 {
10328 signed_addend = -1;
10329 signed_addend &= ~ howto->src_mask;
10330 signed_addend |= addend;
10331 }
10332 else
10333 signed_addend = addend;
ba96a88f
NC		 10334 }
10335 else
4e7fd91e 10336 addend = signed_addend = rel->r_addend;
f21f3fe0 10337
39f21624
NC		 10338 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10339 are resolving a function call relocation. */
10340 if (using_thumb_only (globals)
10341 && (r_type == R_ARM_THM_CALL
10342 || r_type == R_ARM_THM_JUMP24)
10343 && branch_type == ST_BRANCH_TO_ARM)
10344 branch_type = ST_BRANCH_TO_THUMB;
10345
34e77a92
RS		 10346 /* Record the symbol information that should be used in dynamic
10347 relocations. */
10348 dynreloc_st_type = st_type;
10349 dynreloc_value = value;
10350 if (branch_type == ST_BRANCH_TO_THUMB)
10351 dynreloc_value |= 1;
10352
10353 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10354 VALUE appropriately for relocations that we resolve at link time. */
10355 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10356 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10357 &arm_plt)
34e77a92
RS		 10358 && root_plt->offset != (bfd_vma) -1)
10359 {
10360 plt_offset = root_plt->offset;
10361 gotplt_offset = arm_plt->got_offset;
10362
10363 if (h == NULL || eh->is_iplt)
10364 {
10365 has_iplt_entry = TRUE;
10366 splt = globals->root.iplt;
10367
10368 /* Populate .iplt entries here, because not all of them will
10369 be seen by finish_dynamic_symbol. The lower bit is set if
10370 we have already populated the entry. */
10371 if (plt_offset & 1)
10372 plt_offset--;
10373 else
10374 {
57460bcf
NC		 10375 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10376 -1, dynreloc_value))
10377 root_plt->offset |= 1;
10378 else
10379 return bfd_reloc_notsupported;
34e77a92
RS		 10380 }
10381
10382 /* Static relocations always resolve to the .iplt entry. */
10383 st_type = STT_FUNC;
10384 value = (splt->output_section->vma
10385 + splt->output_offset
10386 + plt_offset);
10387 branch_type = ST_BRANCH_TO_ARM;
10388
10389 /* If there are non-call relocations that resolve to the .iplt
10390 entry, then all dynamic ones must too. */
10391 if (arm_plt->noncall_refcount != 0)
10392 {
10393 dynreloc_st_type = st_type;
10394 dynreloc_value = value;
10395 }
10396 }
10397 else
10398 /* We populate the .plt entry in finish_dynamic_symbol. */
10399 splt = globals->root.splt;
10400 }
10401 else
10402 {
10403 splt = NULL;
10404 plt_offset = (bfd_vma) -1;
10405 gotplt_offset = (bfd_vma) -1;
10406 }
10407
95b03e4a
L		 10408 resolved_to_zero = (h != NULL
10409 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10410
252b5132
RH		 10411 switch (r_type)
10412 {
10413 case R_ARM_NONE:
28a094c2
DJ		 10414 /* We don't need to find a value for this symbol. It's just a
10415 marker. */
10416 *unresolved_reloc_p = FALSE;
252b5132
RH		 10417 return bfd_reloc_ok;
10418
00a97672
RS		 10419 case R_ARM_ABS12:
10420 if (!globals->vxworks_p)
10421 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10422 /* Fall through. */
00a97672 10423
252b5132
RH		 10424 case R_ARM_PC24:
10425 case R_ARM_ABS32:
bb224fc3 10426 case R_ARM_ABS32_NOI:
252b5132 10427 case R_ARM_REL32:
bb224fc3 10428 case R_ARM_REL32_NOI:
5b5bb741
PB		 10429 case R_ARM_CALL:
10430 case R_ARM_JUMP24:
dfc5f959 10431 case R_ARM_XPC25:
eb043451 10432 case R_ARM_PREL31:
7359ea65 10433 case R_ARM_PLT32:
7359ea65
DJ		 10434 /* Handle relocations which should use the PLT entry. ABS32/REL32
10435 will use the symbol's value, which may point to a PLT entry, but we
10436 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10437 branches in this object should go to it, except if the PLT is too
10438 far away, in which case a long branch stub should be inserted. */
bb224fc3 10439 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10440 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10441 && r_type != R_ARM_CALL
10442 && r_type != R_ARM_JUMP24
10443 && r_type != R_ARM_PLT32)
34e77a92 10444 && plt_offset != (bfd_vma) -1)
7359ea65 10445 {
34e77a92
RS		 10446 /* If we've created a .plt section, and assigned a PLT entry
10447 to this function, it must either be a STT_GNU_IFUNC reference
10448 or not be known to bind locally. In other cases, we should
10449 have cleared the PLT entry by now. */
10450 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10451
10452 value = (splt->output_section->vma
10453 + splt->output_offset
34e77a92 10454 + plt_offset);
0945cdfd 10455 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10456 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10457 contents, rel->r_offset, value,
00a97672 10458 rel->r_addend);
7359ea65
DJ		 10459 }
10460
67687978
PB		 10461 /* When generating a shared object or relocatable executable, these
10462 relocations are copied into the output file to be resolved at
10463 run time. */
0e1862bb 10464 if ((bfd_link_pic (info)
e8b09b87
CL		 10465 || globals->root.is_relocatable_executable
10466 || globals->fdpic_p)
7359ea65 10467 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10468 && !(globals->vxworks_p
3348747a
NS		 10469 && strcmp (input_section->output_section->name,
10470 ".tls_vars") == 0)
bb224fc3 10471 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10472 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10473 && !(input_bfd == globals->stub_bfd
10474 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10475 && (h == NULL
95b03e4a
L		 10476 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10477 && !resolved_to_zero)
7359ea65
DJ		 10478 || h->root.type != bfd_link_hash_undefweak)
10479 && r_type != R_ARM_PC24
5b5bb741
PB		 10480 && r_type != R_ARM_CALL
10481 && r_type != R_ARM_JUMP24
ee06dc07 10482 && r_type != R_ARM_PREL31
7359ea65 10483 && r_type != R_ARM_PLT32)
252b5132 10484 {
947216bf 10485 Elf_Internal_Rela outrel;
b34976b6 10486 bfd_boolean skip, relocate;
e8b09b87 10487 int isrofixup = 0;
f21f3fe0 10488
52db4ec2
JW		 10489 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10490 && !h->def_regular)
10491 {
10492 char *v = _("shared object");
10493
0e1862bb 10494 if (bfd_link_executable (info))
52db4ec2
JW		 10495 v = _("PIE executable");
10496
4eca0228 10497 _bfd_error_handler
871b3ab2 10498 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10499 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10500 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10501 return bfd_reloc_notsupported;
10502 }
10503
0945cdfd
DJ		 10504 *unresolved_reloc_p = FALSE;
10505
34e77a92 10506 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10507 {
83bac4b0
NC		 10508 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10509 ! globals->use_rel);
f21f3fe0 10510
83bac4b0 10511 if (sreloc == NULL)
252b5132 10512 return bfd_reloc_notsupported;
252b5132 10513 }
f21f3fe0 10514
b34976b6
AM		 10515 skip = FALSE;
10516 relocate = FALSE;
f21f3fe0 10517
00a97672 10518 outrel.r_addend = addend;
c629eae0
JJ		 10519 outrel.r_offset =
10520 _bfd_elf_section_offset (output_bfd, info, input_section,
10521 rel->r_offset);
10522 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10523 skip = TRUE;
0bb2d96a 10524 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10525 skip = TRUE, relocate = TRUE;
252b5132
RH		 10526 outrel.r_offset += (input_section->output_section->vma
10527 + input_section->output_offset);
f21f3fe0 10528
252b5132 10529 if (skip)
0bb2d96a 10530 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10531 else if (h != NULL
10532 && h->dynindx != -1
0e1862bb 10533 && (!bfd_link_pic (info)
1dcb9720
JW		 10534 || !(bfd_link_pie (info)
10535 || SYMBOLIC_BIND (info, h))
f5385ebf 10536 || !h->def_regular))
5e681ec4 10537 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10538 else
10539 {
a16385dc
MM		 10540 int symbol;
10541
5e681ec4 10542 /* This symbol is local, or marked to become local. */
e8b09b87
CL		 10543 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10544 || (globals->fdpic_p && !bfd_link_pic(info)));
a16385dc 10545 if (globals->symbian_p)
6366ff1e 10546 {
74541ad4
AM		 10547 asection *osec;
10548
6366ff1e
MM		 10549 /* On Symbian OS, the data segment and text segement
10550 can be relocated independently. Therefore, we
10551 must indicate the segment to which this
10552 relocation is relative. The BPABI allows us to
10553 use any symbol in the right segment; we just use
10554 the section symbol as it is convenient. (We
10555 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10556 will not appear in the dynamic symbol table.)
10557
10558 Note that the dynamic linker ignores the section
10559 symbol value, so we don't subtract osec->vma
10560 from the emitted reloc addend. */
10dbd1f3 10561 if (sym_sec)
74541ad4 10562 osec = sym_sec->output_section;
10dbd1f3 10563 else
74541ad4
AM		 10564 osec = input_section->output_section;
10565 symbol = elf_section_data (osec)->dynindx;
10566 if (symbol == 0)
10567 {
10568 struct elf_link_hash_table *htab = elf_hash_table (info);
10569
10570 if ((osec->flags & SEC_READONLY) == 0
10571 && htab->data_index_section != NULL)
10572 osec = htab->data_index_section;
10573 else
10574 osec = htab->text_index_section;
10575 symbol = elf_section_data (osec)->dynindx;
10576 }
6366ff1e
MM		 10577 BFD_ASSERT (symbol != 0);
10578 }
a16385dc
MM		 10579 else
10580 /* On SVR4-ish systems, the dynamic loader cannot
10581 relocate the text and data segments independently,
10582 so the symbol does not matter. */
10583 symbol = 0;
34e77a92
RS		 10584 if (dynreloc_st_type == STT_GNU_IFUNC)
10585 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10586 to the .iplt entry. Instead, every non-call reference
10587 must use an R_ARM_IRELATIVE relocation to obtain the
10588 correct run-time address. */
10589 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
e8b09b87
CL		 10590 else if (globals->fdpic_p && !bfd_link_pic(info))
10591 isrofixup = 1;
34e77a92
RS		 10592 else
10593 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10594 if (globals->use_rel)
10595 relocate = TRUE;
10596 else
34e77a92 10597 outrel.r_addend += dynreloc_value;
252b5132 10598 }
f21f3fe0 10599
e8b09b87
CL		 10600 if (isrofixup)
10601 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
10602 else
10603 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10604
f21f3fe0 10605 /* If this reloc is against an external symbol, we do not want to
252b5132 10606 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10607 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10608 if (! relocate)
10609 return bfd_reloc_ok;
9a5aca8c 10610
f21f3fe0 10611 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10612 contents, rel->r_offset,
10613 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10614 }
10615 else switch (r_type)
10616 {
00a97672
RS		 10617 case R_ARM_ABS12:
10618 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10619
dfc5f959 10620 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10621 case R_ARM_CALL:
10622 case R_ARM_JUMP24:
8029a119 10623 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10624 case R_ARM_PLT32:
906e58ca 10625 {
906e58ca
NC		 10626 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10627
dfc5f959 10628 if (r_type == R_ARM_XPC25)
252b5132 10629 {
dfc5f959
NC		 10630 /* Check for Arm calling Arm function. */
10631 /* FIXME: Should we translate the instruction into a BL
10632 instruction instead ? */
35fc36a8 10633 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10634 _bfd_error_handler
90b6238f
AM		 10635 (_("\%pB: warning: %s BLX instruction targets"
10636 " %s function '%s'"),
10637 input_bfd, "ARM",
10638 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10639 }
155d87d7 10640 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10641 {
10642 /* Check for Arm calling Thumb function. */
35fc36a8 10643 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10644 {
f2a9dd69
DJ		 10645 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10646 output_bfd, input_section,
10647 hit_data, sym_sec, rel->r_offset,
10648 signed_addend, value,
10649 error_message))
10650 return bfd_reloc_ok;
10651 else
10652 return bfd_reloc_dangerous;
dfc5f959 10653 }
252b5132 10654 }
ba96a88f 10655
906e58ca 10656 /* Check if a stub has to be inserted because the
8029a119 10657 destination is too far or we are changing mode. */
155d87d7
CL		 10658 if ( r_type == R_ARM_CALL
10659 || r_type == R_ARM_JUMP24
10660 || r_type == R_ARM_PLT32)
906e58ca 10661 {
fe33d2fa
CL		 10662 enum elf32_arm_stub_type stub_type = arm_stub_none;
10663 struct elf32_arm_link_hash_entry *hash;
10664
10665 hash = (struct elf32_arm_link_hash_entry *) h;
10666 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10667 st_type, &branch_type,
10668 hash, value, sym_sec,
fe33d2fa 10669 input_bfd, sym_name);
5fa9e92f 10670
fe33d2fa 10671 if (stub_type != arm_stub_none)
906e58ca
NC		 10672 {
10673 /* The target is out of reach, so redirect the
10674 branch to the local stub for this function. */
906e58ca
NC		 10675 stub_entry = elf32_arm_get_stub_entry (input_section,
10676 sym_sec, h,
fe33d2fa
CL		 10677 rel, globals,
10678 stub_type);
9cd3e4e5
NC		 10679 {
10680 if (stub_entry != NULL)
10681 value = (stub_entry->stub_offset
10682 + stub_entry->stub_sec->output_offset
10683 + stub_entry->stub_sec->output_section->vma);
10684
10685 if (plt_offset != (bfd_vma) -1)
10686 *unresolved_reloc_p = FALSE;
10687 }
906e58ca 10688 }
fe33d2fa
CL		 10689 else
10690 {
10691 /* If the call goes through a PLT entry, make sure to
10692 check distance to the right destination address. */
34e77a92 10693 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10694 {
10695 value = (splt->output_section->vma
10696 + splt->output_offset
34e77a92 10697 + plt_offset);
fe33d2fa
CL		 10698 *unresolved_reloc_p = FALSE;
10699 /* The PLT entry is in ARM mode, regardless of the
10700 target function. */
35fc36a8 10701 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10702 }
10703 }
906e58ca
NC		 10704 }
10705
dea514f5
PB		 10706 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10707 where:
10708 S is the address of the symbol in the relocation.
10709 P is address of the instruction being relocated.
10710 A is the addend (extracted from the instruction) in bytes.
10711
10712 S is held in 'value'.
10713 P is the base address of the section containing the
10714 instruction plus the offset of the reloc into that
10715 section, ie:
10716 (input_section->output_section->vma +
10717 input_section->output_offset +
10718 rel->r_offset).
10719 A is the addend, converted into bytes, ie:
10720 (signed_addend * 4)
10721
10722 Note: None of these operations have knowledge of the pipeline
10723 size of the processor, thus it is up to the assembler to
10724 encode this information into the addend. */
10725 value -= (input_section->output_section->vma
10726 + input_section->output_offset);
10727 value -= rel->r_offset;
4e7fd91e
PB		 10728 if (globals->use_rel)
10729 value += (signed_addend << howto->size);
10730 else
10731 /* RELA addends do not have to be adjusted by howto->size. */
10732 value += signed_addend;
23080146 10733
dcb5e6e6
NC		 10734 signed_addend = value;
10735 signed_addend >>= howto->rightshift;
9a5aca8c 10736
5ab79981 10737 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10738 the next instruction unless a PLT entry will be created.
77b4f08f 10739 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10740 The jump to the next instruction is optimized as a NOP depending
10741 on the architecture. */
ffcb4889 10742 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10743 && plt_offset == (bfd_vma) -1)
77b4f08f 10744 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10745 {
cd1dac3d
DG		 10746 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10747
10748 if (arch_has_arm_nop (globals))
10749 value |= 0x0320f000;
10750 else
10751 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10752 }
10753 else
59f2c4e7 10754 {
9b485d32 10755 /* Perform a signed range check. */
dcb5e6e6 10756 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10757 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10758 return bfd_reloc_overflow;
9a5aca8c 10759
5ab79981 10760 addend = (value & 2);
39b41c9c 10761
5ab79981
PB		 10762 value = (signed_addend & howto->dst_mask)
10763 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10764
5ab79981
PB		 10765 if (r_type == R_ARM_CALL)
10766 {
155d87d7 10767 /* Set the H bit in the BLX instruction. */
35fc36a8 10768 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10769 {
10770 if (addend)
10771 value |= (1 << 24);
10772 else
10773 value &= ~(bfd_vma)(1 << 24);
10774 }
10775
5ab79981 10776 /* Select the correct instruction (BL or BLX). */
906e58ca 10777 /* Only if we are not handling a BL to a stub. In this
8029a119 10778 case, mode switching is performed by the stub. */
35fc36a8 10779 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10780 value |= (1 << 28);
63e1a0fc 10781 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10782 {
10783 value &= ~(bfd_vma)(1 << 28);
10784 value |= (1 << 24);
10785 }
39b41c9c
PB		 10786 }
10787 }
906e58ca 10788 }
252b5132 10789 break;
f21f3fe0 10790
252b5132
RH		 10791 case R_ARM_ABS32:
10792 value += addend;
35fc36a8 10793 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10794 value |= 1;
10795 break;
f21f3fe0 10796
bb224fc3
MS		 10797 case R_ARM_ABS32_NOI:
10798 value += addend;
10799 break;
10800
252b5132 10801 case R_ARM_REL32:
a8bc6c78 10802 value += addend;
35fc36a8 10803 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10804 value |= 1;
252b5132 10805 value -= (input_section->output_section->vma
62efb346 10806 + input_section->output_offset + rel->r_offset);
252b5132 10807 break;
eb043451 10808
bb224fc3
MS		 10809 case R_ARM_REL32_NOI:
10810 value += addend;
10811 value -= (input_section->output_section->vma
10812 + input_section->output_offset + rel->r_offset);
10813 break;
10814
eb043451
PB		 10815 case R_ARM_PREL31:
10816 value -= (input_section->output_section->vma
10817 + input_section->output_offset + rel->r_offset);
10818 value += signed_addend;
10819 if (! h || h->root.type != bfd_link_hash_undefweak)
10820 {
8029a119 10821 /* Check for overflow. */
eb043451
PB		 10822 if ((value ^ (value >> 1)) & (1 << 30))
10823 return bfd_reloc_overflow;
10824 }
10825 value &= 0x7fffffff;
10826 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10827 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10828 value |= 1;
10829 break;
252b5132 10830 }
f21f3fe0 10831
252b5132
RH		 10832 bfd_put_32 (input_bfd, value, hit_data);
10833 return bfd_reloc_ok;
10834
10835 case R_ARM_ABS8:
fd0fd00c
MJ		 10836 /* PR 16202: Refectch the addend using the correct size. */
10837 if (globals->use_rel)
10838 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10839 value += addend;
4e67d4ca
DG		 10840
10841 /* There is no way to tell whether the user intended to use a signed or
10842 unsigned addend. When checking for overflow we accept either,
10843 as specified by the AAELF. */
10844 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10845 return bfd_reloc_overflow;
10846
10847 bfd_put_8 (input_bfd, value, hit_data);
10848 return bfd_reloc_ok;
10849
10850 case R_ARM_ABS16:
fd0fd00c
MJ		 10851 /* PR 16202: Refectch the addend using the correct size. */
10852 if (globals->use_rel)
10853 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10854 value += addend;
10855
4e67d4ca
DG		 10856 /* See comment for R_ARM_ABS8. */
10857 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10858 return bfd_reloc_overflow;
10859
10860 bfd_put_16 (input_bfd, value, hit_data);
10861 return bfd_reloc_ok;
10862
252b5132 10863 case R_ARM_THM_ABS5:
9b485d32 10864 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10865 if (globals->use_rel)
10866 {
10867 /* Need to refetch addend. */
10868 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10869 /* ??? Need to determine shift amount from operand size. */
10870 addend >>= howto->rightshift;
10871 }
252b5132
RH		 10872 value += addend;
10873
10874 /* ??? Isn't value unsigned? */
10875 if ((long) value > 0x1f || (long) value < -0x10)
10876 return bfd_reloc_overflow;
10877
10878 /* ??? Value needs to be properly shifted into place first. */
10879 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10880 bfd_put_16 (input_bfd, value, hit_data);
10881 return bfd_reloc_ok;
10882
2cab6cc3
MS		 10883 case R_ARM_THM_ALU_PREL_11_0:
10884 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10885 {
10886 bfd_vma insn;
10887 bfd_signed_vma relocation;
10888
10889 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10890 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10891
99059e56
RM		 10892 if (globals->use_rel)
10893 {
10894 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10895 | ((insn & (1 << 26)) >> 15);
10896 if (insn & 0xf00000)
10897 signed_addend = -signed_addend;
10898 }
2cab6cc3
MS		 10899
10900 relocation = value + signed_addend;
79f08007 10901 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10902 + input_section->output_offset
10903 + rel->r_offset);
2cab6cc3 10904
8c65b54f
CS		 10905 /* PR 21523: Use an absolute value. The user of this reloc will
10906 have already selected an ADD or SUB insn appropriately. */
453f8e1e 10907 value = llabs (relocation);
2cab6cc3 10908
99059e56
RM		 10909 if (value >= 0x1000)
10910 return bfd_reloc_overflow;
2cab6cc3 10911
e645cf40
AG		 10912 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10913 if (branch_type == ST_BRANCH_TO_THUMB)
10914 value |= 1;
10915
2cab6cc3 10916 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10917 | ((value & 0x700) << 4)
10918 | ((value & 0x800) << 15);
10919 if (relocation < 0)
10920 insn |= 0xa00000;
2cab6cc3
MS		 10921
10922 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10923 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10924
99059e56 10925 return bfd_reloc_ok;
2cab6cc3
MS		 10926 }
10927
e1ec24c6
NC		 10928 case R_ARM_THM_PC8:
10929 /* PR 10073: This reloc is not generated by the GNU toolchain,
10930 but it is supported for compatibility with third party libraries
10931 generated by other compilers, specifically the ARM/IAR. */
10932 {
10933 bfd_vma insn;
10934 bfd_signed_vma relocation;
10935
10936 insn = bfd_get_16 (input_bfd, hit_data);
10937
99059e56 10938 if (globals->use_rel)
79f08007 10939 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10940
10941 relocation = value + addend;
79f08007 10942 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10943 + input_section->output_offset
10944 + rel->r_offset);
e1ec24c6 10945
b6518b38 10946 value = relocation;
e1ec24c6
NC		 10947
10948 /* We do not check for overflow of this reloc. Although strictly
10949 speaking this is incorrect, it appears to be necessary in order
10950 to work with IAR generated relocs. Since GCC and GAS do not
10951 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10952 a problem for them. */
10953 value &= 0x3fc;
10954
10955 insn = (insn & 0xff00) | (value >> 2);
10956
10957 bfd_put_16 (input_bfd, insn, hit_data);
10958
99059e56 10959 return bfd_reloc_ok;
e1ec24c6
NC		 10960 }
10961
2cab6cc3
MS		 10962 case R_ARM_THM_PC12:
10963 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10964 {
10965 bfd_vma insn;
10966 bfd_signed_vma relocation;
10967
10968 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10969 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10970
99059e56
RM		 10971 if (globals->use_rel)
10972 {
10973 signed_addend = insn & 0xfff;
10974 if (!(insn & (1 << 23)))
10975 signed_addend = -signed_addend;
10976 }
2cab6cc3
MS		 10977
10978 relocation = value + signed_addend;
79f08007 10979 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10980 + input_section->output_offset
10981 + rel->r_offset);
2cab6cc3 10982
b6518b38 10983 value = relocation;
2cab6cc3 10984
99059e56
RM		 10985 if (value >= 0x1000)
10986 return bfd_reloc_overflow;
2cab6cc3
MS		 10987
10988 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10989 if (relocation >= 0)
10990 insn |= (1 << 23);
2cab6cc3
MS		 10991
10992 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10993 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10994
99059e56 10995 return bfd_reloc_ok;
2cab6cc3
MS		 10996 }
10997
dfc5f959 10998 case R_ARM_THM_XPC22:
c19d1205 10999 case R_ARM_THM_CALL:
bd97cb95 11000 case R_ARM_THM_JUMP24:
dfc5f959 11001 /* Thumb BL (branch long instruction). */
252b5132 11002 {
b34976b6 11003 bfd_vma relocation;
99059e56 11004 bfd_vma reloc_sign;
b34976b6
AM		 11005 bfd_boolean overflow = FALSE;
11006 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11007 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 11008 bfd_signed_vma reloc_signed_max;
11009 bfd_signed_vma reloc_signed_min;
b34976b6 11010 bfd_vma check;
252b5132 11011 bfd_signed_vma signed_check;
e95de063 11012 int bitsize;
cd1dac3d 11013 const int thumb2 = using_thumb2 (globals);
5e866f5a 11014 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 11015
5ab79981 11016 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 11017 the next instruction unless a PLT entry will be created.
11018 The jump to the next instruction is optimized as a NOP.W for
11019 Thumb-2 enabled architectures. */
19540007 11020 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 11021 && plt_offset == (bfd_vma) -1)
5ab79981 11022 {
60a019a0 11023 if (thumb2)
cd1dac3d
DG		 11024 {
11025 bfd_put_16 (input_bfd, 0xf3af, hit_data);
11026 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
11027 }
11028 else
11029 {
11030 bfd_put_16 (input_bfd, 0xe000, hit_data);
11031 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11032 }
5ab79981
PB		 11033 return bfd_reloc_ok;
11034 }
11035
e95de063 11036 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 11037 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 11038 if (globals->use_rel)
11039 {
99059e56
RM		 11040 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11041 bfd_vma upper = upper_insn & 0x3ff;
11042 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 11043 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11044 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 11045 bfd_vma i1 = j1 ^ s ? 0 : 1;
11046 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 11047
99059e56
RM		 11048 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11049 /* Sign extend. */
11050 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 11051
4e7fd91e
PB		 11052 signed_addend = addend;
11053 }
cb1afa5c 11054
dfc5f959
NC		 11055 if (r_type == R_ARM_THM_XPC22)
11056 {
11057 /* Check for Thumb to Thumb call. */
11058 /* FIXME: Should we translate the instruction into a BL
11059 instruction instead ? */
35fc36a8 11060 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 11061 _bfd_error_handler
90b6238f
AM		 11062 (_("%pB: warning: %s BLX instruction targets"
11063 " %s function '%s'"),
11064 input_bfd, "Thumb",
11065 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 11066 }
11067 else
252b5132 11068 {
dfc5f959
NC		 11069 /* If it is not a call to Thumb, assume call to Arm.
11070 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 11071 function call at all, but rather a long jump. Calls through
11072 the PLT do not require stubs. */
34e77a92 11073 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 11074 {
bd97cb95 11075 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11076 {
11077 /* Convert BL to BLX. */
11078 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11079 }
155d87d7
CL		 11080 else if (( r_type != R_ARM_THM_CALL)
11081 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 11082 {
11083 if (elf32_thumb_to_arm_stub
11084 (info, sym_name, input_bfd, output_bfd, input_section,
11085 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11086 error_message))
11087 return bfd_reloc_ok;
11088 else
11089 return bfd_reloc_dangerous;
11090 }
da5938a2 11091 }
35fc36a8
RS		 11092 else if (branch_type == ST_BRANCH_TO_THUMB
11093 && globals->use_blx
bd97cb95 11094 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11095 {
11096 /* Make sure this is a BL. */
11097 lower_insn |= 0x1800;
11098 }
252b5132 11099 }
f21f3fe0 11100
fe33d2fa 11101 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 11102 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 11103 {
11104 /* Check if a stub has to be inserted because the destination
8029a119 11105 is too far. */
fe33d2fa
CL		 11106 struct elf32_arm_stub_hash_entry *stub_entry;
11107 struct elf32_arm_link_hash_entry *hash;
11108
11109 hash = (struct elf32_arm_link_hash_entry *) h;
11110
11111 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 11112 st_type, &branch_type,
11113 hash, value, sym_sec,
fe33d2fa
CL		 11114 input_bfd, sym_name);
11115
11116 if (stub_type != arm_stub_none)
906e58ca
NC		 11117 {
11118 /* The target is out of reach or we are changing modes, so
11119 redirect the branch to the local stub for this
11120 function. */
11121 stub_entry = elf32_arm_get_stub_entry (input_section,
11122 sym_sec, h,
fe33d2fa
CL		 11123 rel, globals,
11124 stub_type);
906e58ca 11125 if (stub_entry != NULL)
9cd3e4e5
NC		 11126 {
11127 value = (stub_entry->stub_offset
11128 + stub_entry->stub_sec->output_offset
11129 + stub_entry->stub_sec->output_section->vma);
11130
11131 if (plt_offset != (bfd_vma) -1)
11132 *unresolved_reloc_p = FALSE;
11133 }
906e58ca 11134
f4ac8484 11135 /* If this call becomes a call to Arm, force BLX. */
155d87d7 11136 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 11137 {
11138 if ((stub_entry
11139 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 11140 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 11141 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11142 }
906e58ca
NC		 11143 }
11144 }
11145
fe33d2fa 11146 /* Handle calls via the PLT. */
34e77a92 11147 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 11148 {
11149 value = (splt->output_section->vma
11150 + splt->output_offset
34e77a92 11151 + plt_offset);
fe33d2fa 11152
eed94f8f
NC		 11153 if (globals->use_blx
11154 && r_type == R_ARM_THM_CALL
11155 && ! using_thumb_only (globals))
fe33d2fa
CL		 11156 {
11157 /* If the Thumb BLX instruction is available, convert
11158 the BL to a BLX instruction to call the ARM-mode
11159 PLT entry. */
11160 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 11161 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 11162 }
11163 else
11164 {
eed94f8f
NC		 11165 if (! using_thumb_only (globals))
11166 /* Target the Thumb stub before the ARM PLT entry. */
11167 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 11168 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 11169 }
11170 *unresolved_reloc_p = FALSE;
11171 }
11172
ba96a88f 11173 relocation = value + signed_addend;
f21f3fe0 11174
252b5132 11175 relocation -= (input_section->output_section->vma
ba96a88f
NC		 11176 + input_section->output_offset
11177 + rel->r_offset);
9a5aca8c 11178
252b5132
RH		 11179 check = relocation >> howto->rightshift;
11180
11181 /* If this is a signed value, the rightshift just dropped
11182 leading 1 bits (assuming twos complement). */
11183 if ((bfd_signed_vma) relocation >= 0)
11184 signed_check = check;
11185 else
11186 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11187
e95de063
MS		 11188 /* Calculate the permissable maximum and minimum values for
11189 this relocation according to whether we're relocating for
11190 Thumb-2 or not. */
11191 bitsize = howto->bitsize;
5e866f5a 11192 if (!thumb2_bl)
e95de063 11193 bitsize -= 2;
f6ebfac0 11194 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 11195 reloc_signed_min = ~reloc_signed_max;
11196
252b5132 11197 /* Assumes two's complement. */
ba96a88f 11198 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 11199 overflow = TRUE;
252b5132 11200
bd97cb95 11201 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 11202 /* For a BLX instruction, make sure that the relocation is rounded up
11203 to a word boundary. This follows the semantics of the instruction
11204 which specifies that bit 1 of the target address will come from bit
11205 1 of the base address. */
11206 relocation = (relocation + 2) & ~ 3;
cb1afa5c 11207
e95de063
MS		 11208 /* Put RELOCATION back into the insn. Assumes two's complement.
11209 We use the Thumb-2 encoding, which is safe even if dealing with
11210 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 11211 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 11212 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 11213 | ((relocation >> 12) & 0x3ff)
11214 | (reloc_sign << 10);
906e58ca 11215 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 11216 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11217 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11218 | ((relocation >> 1) & 0x7ff);
c62e1cc3 11219
252b5132
RH		 11220 /* Put the relocated value back in the object file: */
11221 bfd_put_16 (input_bfd, upper_insn, hit_data);
11222 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11223
11224 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11225 }
11226 break;
11227
c19d1205
ZW		 11228 case R_ARM_THM_JUMP19:
11229 /* Thumb32 conditional branch instruction. */
11230 {
11231 bfd_vma relocation;
11232 bfd_boolean overflow = FALSE;
11233 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11234 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 11235 bfd_signed_vma reloc_signed_max = 0xffffe;
11236 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 11237 bfd_signed_vma signed_check;
07d6d2b8 11238 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 11239 struct elf32_arm_stub_hash_entry *stub_entry;
11240 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 11241
11242 /* Need to refetch the addend, reconstruct the top three bits,
11243 and squish the two 11 bit pieces together. */
11244 if (globals->use_rel)
11245 {
11246 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 11247 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 11248 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11249 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11250 bfd_vma lower = (lower_insn & 0x07ff);
11251
a00a1f35
MS		 11252 upper |= J1 << 6;
11253 upper |= J2 << 7;
11254 upper |= (!S) << 8;
c19d1205
ZW		 11255 upper -= 0x0100; /* Sign extend. */
11256
11257 addend = (upper << 12) | (lower << 1);
11258 signed_addend = addend;
11259 }
11260
bd97cb95 11261 /* Handle calls via the PLT. */
34e77a92 11262 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 11263 {
11264 value = (splt->output_section->vma
11265 + splt->output_offset
34e77a92 11266 + plt_offset);
bd97cb95
DJ		 11267 /* Target the Thumb stub before the ARM PLT entry. */
11268 value -= PLT_THUMB_STUB_SIZE;
11269 *unresolved_reloc_p = FALSE;
11270 }
11271
c5423981
TG		 11272 hash = (struct elf32_arm_link_hash_entry *)h;
11273
11274 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 11275 st_type, &branch_type,
11276 hash, value, sym_sec,
11277 input_bfd, sym_name);
c5423981
TG		 11278 if (stub_type != arm_stub_none)
11279 {
11280 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 11281 sym_sec, h,
11282 rel, globals,
11283 stub_type);
c5423981
TG		 11284 if (stub_entry != NULL)
11285 {
07d6d2b8
AM		 11286 value = (stub_entry->stub_offset
11287 + stub_entry->stub_sec->output_offset
11288 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 11289 }
11290 }
c19d1205 11291
99059e56 11292 relocation = value + signed_addend;
c19d1205
ZW		 11293 relocation -= (input_section->output_section->vma
11294 + input_section->output_offset
11295 + rel->r_offset);
a00a1f35 11296 signed_check = (bfd_signed_vma) relocation;
c19d1205 11297
c19d1205
ZW		 11298 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11299 overflow = TRUE;
11300
11301 /* Put RELOCATION back into the insn. */
11302 {
11303 bfd_vma S = (relocation & 0x00100000) >> 20;
11304 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11305 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11306 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11307 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11308
a00a1f35 11309 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 11310 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11311 }
11312
11313 /* Put the relocated value back in the object file: */
11314 bfd_put_16 (input_bfd, upper_insn, hit_data);
11315 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11316
11317 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11318 }
11319
11320 case R_ARM_THM_JUMP11:
11321 case R_ARM_THM_JUMP8:
11322 case R_ARM_THM_JUMP6:
51c5503b
NC		 11323 /* Thumb B (branch) instruction). */
11324 {
6cf9e9fe 11325 bfd_signed_vma relocation;
51c5503b
NC		 11326 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11327 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11328 bfd_signed_vma signed_check;
11329
c19d1205
ZW		 11330 /* CZB cannot jump backward. */
11331 if (r_type == R_ARM_THM_JUMP6)
11332 reloc_signed_min = 0;
11333
4e7fd91e 11334 if (globals->use_rel)
6cf9e9fe 11335 {
4e7fd91e
PB		 11336 /* Need to refetch addend. */
11337 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
11338 if (addend & ((howto->src_mask + 1) >> 1))
11339 {
11340 signed_addend = -1;
11341 signed_addend &= ~ howto->src_mask;
11342 signed_addend |= addend;
11343 }
11344 else
11345 signed_addend = addend;
11346 /* The value in the insn has been right shifted. We need to
11347 undo this, so that we can perform the address calculation
11348 in terms of bytes. */
11349 signed_addend <<= howto->rightshift;
6cf9e9fe 11350 }
6cf9e9fe 11351 relocation = value + signed_addend;
51c5503b
NC		 11352
11353 relocation -= (input_section->output_section->vma
11354 + input_section->output_offset
11355 + rel->r_offset);
11356
6cf9e9fe
NC		 11357 relocation >>= howto->rightshift;
11358 signed_check = relocation;
c19d1205
ZW		 11359
11360 if (r_type == R_ARM_THM_JUMP6)
11361 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11362 else
11363 relocation &= howto->dst_mask;
51c5503b 11364 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11365
51c5503b
NC		 11366 bfd_put_16 (input_bfd, relocation, hit_data);
11367
11368 /* Assumes two's complement. */
11369 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11370 return bfd_reloc_overflow;
11371
11372 return bfd_reloc_ok;
11373 }
cedb70c5 11374
8375c36b
PB		 11375 case R_ARM_ALU_PCREL7_0:
11376 case R_ARM_ALU_PCREL15_8:
11377 case R_ARM_ALU_PCREL23_15:
11378 {
11379 bfd_vma insn;
11380 bfd_vma relocation;
11381
11382 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11383 if (globals->use_rel)
11384 {
11385 /* Extract the addend. */
11386 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11387 signed_addend = addend;
11388 }
8375c36b
PB		 11389 relocation = value + signed_addend;
11390
11391 relocation -= (input_section->output_section->vma
11392 + input_section->output_offset
11393 + rel->r_offset);
11394 insn = (insn & ~0xfff)
11395 | ((howto->bitpos << 7) & 0xf00)
11396 | ((relocation >> howto->bitpos) & 0xff);
11397 bfd_put_32 (input_bfd, value, hit_data);
11398 }
11399 return bfd_reloc_ok;
11400
252b5132
RH		 11401 case R_ARM_GNU_VTINHERIT:
11402 case R_ARM_GNU_VTENTRY:
11403 return bfd_reloc_ok;
11404
c19d1205 11405 case R_ARM_GOTOFF32:
252b5132 11406 /* Relocation is relative to the start of the
99059e56 11407 global offset table. */
252b5132
RH		 11408
11409 BFD_ASSERT (sgot != NULL);
11410 if (sgot == NULL)
99059e56 11411 return bfd_reloc_notsupported;
9a5aca8c 11412
cedb70c5 11413 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11414 address by one, so that attempts to call the function pointer will
11415 correctly interpret it as Thumb code. */
35fc36a8 11416 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11417 value += 1;
11418
252b5132 11419 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11420 calculation. We always want the start of .got. If we
11421 define _GLOBAL_OFFSET_TABLE in a different way, as is
11422 permitted by the ABI, we might have to change this
11423 calculation. */
252b5132 11424 value -= sgot->output_section->vma;
f21f3fe0 11425 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11426 contents, rel->r_offset, value,
00a97672 11427 rel->r_addend);
252b5132
RH		 11428
11429 case R_ARM_GOTPC:
a7c10850 11430 /* Use global offset table as symbol value. */
252b5132 11431 BFD_ASSERT (sgot != NULL);
f21f3fe0 11432
252b5132 11433 if (sgot == NULL)
99059e56 11434 return bfd_reloc_notsupported;
252b5132 11435
0945cdfd 11436 *unresolved_reloc_p = FALSE;
252b5132 11437 value = sgot->output_section->vma;
f21f3fe0 11438 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11439 contents, rel->r_offset, value,
00a97672 11440 rel->r_addend);
f21f3fe0 11441
252b5132 11442 case R_ARM_GOT32:
eb043451 11443 case R_ARM_GOT_PREL:
252b5132 11444 /* Relocation is to the entry for this symbol in the
99059e56 11445 global offset table. */
252b5132
RH		 11446 if (sgot == NULL)
11447 return bfd_reloc_notsupported;
f21f3fe0 11448
34e77a92
RS		 11449 if (dynreloc_st_type == STT_GNU_IFUNC
11450 && plt_offset != (bfd_vma) -1
11451 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11452 {
11453 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11454 symbol, and the relocation resolves directly to the runtime
11455 target rather than to the .iplt entry. This means that any
11456 .got entry would be the same value as the .igot.plt entry,
11457 so there's no point creating both. */
11458 sgot = globals->root.igotplt;
11459 value = sgot->output_offset + gotplt_offset;
11460 }
11461 else if (h != NULL)
252b5132
RH		 11462 {
11463 bfd_vma off;
f21f3fe0 11464
252b5132
RH		 11465 off = h->got.offset;
11466 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11467 if ((off & 1) != 0)
252b5132 11468 {
b436d854
RS		 11469 /* We have already processsed one GOT relocation against
11470 this symbol. */
11471 off &= ~1;
11472 if (globals->root.dynamic_sections_created
11473 && !SYMBOL_REFERENCES_LOCAL (info, h))
11474 *unresolved_reloc_p = FALSE;
11475 }
11476 else
11477 {
11478 Elf_Internal_Rela outrel;
e8b09b87 11479 int isrofixup = 0;
b436d854 11480
e8b09b87
CL		 11481 if (((h->dynindx != -1) || globals->fdpic_p)
11482 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11483 {
11484 /* If the symbol doesn't resolve locally in a static
11485 object, we have an undefined reference. If the
11486 symbol doesn't resolve locally in a dynamic object,
11487 it should be resolved by the dynamic linker. */
11488 if (globals->root.dynamic_sections_created)
11489 {
11490 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11491 *unresolved_reloc_p = FALSE;
11492 }
11493 else
11494 outrel.r_info = 0;
11495 outrel.r_addend = 0;
11496 }
252b5132
RH		 11497 else
11498 {
34e77a92 11499 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11500 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11501 else if (bfd_link_pic (info)
11502 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11503 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11504 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11505 else
2376f038
EB		 11506 {
11507 outrel.r_info = 0;
11508 if (globals->fdpic_p)
11509 isrofixup = 1;
11510 }
34e77a92 11511 outrel.r_addend = dynreloc_value;
b436d854 11512 }
ee29b9fb 11513
b436d854
RS		 11514 /* The GOT entry is initialized to zero by default.
11515 See if we should install a different value. */
11516 if (outrel.r_addend != 0
2376f038 11517 && (globals->use_rel || outrel.r_info == 0))
b436d854
RS		 11518 {
11519 bfd_put_32 (output_bfd, outrel.r_addend,
11520 sgot->contents + off);
11521 outrel.r_addend = 0;
252b5132 11522 }
f21f3fe0 11523
2376f038
EB		 11524 if (isrofixup)
11525 arm_elf_add_rofixup (output_bfd,
11526 elf32_arm_hash_table(info)->srofixup,
11527 sgot->output_section->vma
11528 + sgot->output_offset + off);
11529
11530 else if (outrel.r_info != 0)
b436d854
RS		 11531 {
11532 outrel.r_offset = (sgot->output_section->vma
11533 + sgot->output_offset
11534 + off);
11535 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11536 }
2376f038 11537
b436d854
RS		 11538 h->got.offset |= 1;
11539 }
252b5132
RH		 11540 value = sgot->output_offset + off;
11541 }
11542 else
11543 {
11544 bfd_vma off;
f21f3fe0 11545
5025eb7c
AO		 11546 BFD_ASSERT (local_got_offsets != NULL
11547 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11548
252b5132 11549 off = local_got_offsets[r_symndx];
f21f3fe0 11550
252b5132
RH		 11551 /* The offset must always be a multiple of 4. We use the
11552 least significant bit to record whether we have already
9b485d32 11553 generated the necessary reloc. */
252b5132
RH		 11554 if ((off & 1) != 0)
11555 off &= ~1;
11556 else
11557 {
2376f038
EB		 11558 Elf_Internal_Rela outrel;
11559 int isrofixup = 0;
f21f3fe0 11560
2376f038
EB		 11561 if (dynreloc_st_type == STT_GNU_IFUNC)
11562 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11563 else if (bfd_link_pic (info))
11564 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11565 else
252b5132 11566 {
2376f038
EB		 11567 outrel.r_info = 0;
11568 if (globals->fdpic_p)
11569 isrofixup = 1;
11570 }
11571
11572 /* The GOT entry is initialized to zero by default.
11573 See if we should install a different value. */
11574 if (globals->use_rel || outrel.r_info == 0)
11575 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
11576
11577 if (isrofixup)
11578 arm_elf_add_rofixup (output_bfd,
11579 globals->srofixup,
11580 sgot->output_section->vma
11581 + sgot->output_offset + off);
f21f3fe0 11582
2376f038
EB		 11583 else if (outrel.r_info != 0)
11584 {
34e77a92 11585 outrel.r_addend = addend + dynreloc_value;
252b5132 11586 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11587 + sgot->output_offset
252b5132 11588 + off);
47beaa6a 11589 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11590 }
f21f3fe0 11591
252b5132
RH		 11592 local_got_offsets[r_symndx] |= 1;
11593 }
f21f3fe0 11594
252b5132
RH		 11595 value = sgot->output_offset + off;
11596 }
eb043451
PB		 11597 if (r_type != R_ARM_GOT32)
11598 value += sgot->output_section->vma;
9a5aca8c 11599
f21f3fe0 11600 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11601 contents, rel->r_offset, value,
00a97672 11602 rel->r_addend);
f21f3fe0 11603
ba93b8ac
DJ		 11604 case R_ARM_TLS_LDO32:
11605 value = value - dtpoff_base (info);
11606
11607 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11608 contents, rel->r_offset, value,
11609 rel->r_addend);
ba93b8ac
DJ		 11610
11611 case R_ARM_TLS_LDM32:
5c5a4843 11612 case R_ARM_TLS_LDM32_FDPIC:
ba93b8ac
DJ		 11613 {
11614 bfd_vma off;
11615
362d30a1 11616 if (sgot == NULL)
ba93b8ac
DJ		 11617 abort ();
11618
11619 off = globals->tls_ldm_got.offset;
11620
11621 if ((off & 1) != 0)
11622 off &= ~1;
11623 else
11624 {
11625 /* If we don't know the module number, create a relocation
11626 for it. */
0e1862bb 11627 if (bfd_link_pic (info))
ba93b8ac
DJ		 11628 {
11629 Elf_Internal_Rela outrel;
ba93b8ac 11630
362d30a1 11631 if (srelgot == NULL)
ba93b8ac
DJ		 11632 abort ();
11633
00a97672 11634 outrel.r_addend = 0;
362d30a1
RS		 11635 outrel.r_offset = (sgot->output_section->vma
11636 + sgot->output_offset + off);
ba93b8ac
DJ		 11637 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11638
00a97672
RS		 11639 if (globals->use_rel)
11640 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11641 sgot->contents + off);
ba93b8ac 11642
47beaa6a 11643 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11644 }
11645 else
362d30a1 11646 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11647
11648 globals->tls_ldm_got.offset |= 1;
11649 }
11650
5c5a4843 11651 if (r_type == R_ARM_TLS_LDM32_FDPIC)
e8b09b87
CL		 11652 {
11653 bfd_put_32(output_bfd,
11654 globals->root.sgot->output_offset + off,
11655 contents + rel->r_offset);
11656
11657 return bfd_reloc_ok;
11658 }
11659 else
11660 {
11661 value = sgot->output_section->vma + sgot->output_offset + off
11662 - (input_section->output_section->vma
11663 + input_section->output_offset + rel->r_offset);
ba93b8ac 11664
e8b09b87
CL		 11665 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11666 contents, rel->r_offset, value,
11667 rel->r_addend);
11668 }
ba93b8ac
DJ		 11669 }
11670
0855e32b
NS		 11671 case R_ARM_TLS_CALL:
11672 case R_ARM_THM_TLS_CALL:
ba93b8ac 11673 case R_ARM_TLS_GD32:
5c5a4843 11674 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 11675 case R_ARM_TLS_IE32:
5c5a4843 11676 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 11677 case R_ARM_TLS_GOTDESC:
11678 case R_ARM_TLS_DESCSEQ:
11679 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11680 {
0855e32b
NS		 11681 bfd_vma off, offplt;
11682 int indx = 0;
ba93b8ac
DJ		 11683 char tls_type;
11684
0855e32b 11685 BFD_ASSERT (sgot != NULL);
ba93b8ac 11686
ba93b8ac
DJ		 11687 if (h != NULL)
11688 {
11689 bfd_boolean dyn;
11690 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11691 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11692 bfd_link_pic (info),
11693 h)
11694 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11695 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11696 {
11697 *unresolved_reloc_p = FALSE;
11698 indx = h->dynindx;
11699 }
11700 off = h->got.offset;
0855e32b 11701 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11702 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11703 }
11704 else
11705 {
0855e32b 11706 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11707 off = local_got_offsets[r_symndx];
0855e32b 11708 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11709 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11710 }
11711
0855e32b 11712 /* Linker relaxations happens from one of the
b38cadfb 11713 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11714 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11715 tls_type = GOT_TLS_IE;
0855e32b
NS		 11716
11717 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11718
11719 if ((off & 1) != 0)
11720 off &= ~1;
11721 else
11722 {
11723 bfd_boolean need_relocs = FALSE;
11724 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11725 int cur_off = off;
11726
11727 /* The GOT entries have not been initialized yet. Do it
11728 now, and emit any relocations. If both an IE GOT and a
11729 GD GOT are necessary, we emit the GD first. */
11730
0e1862bb 11731 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac 11732 && (h == NULL
95b03e4a
L		 11733 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11734 && !resolved_to_zero)
ba93b8ac
DJ		 11735 || h->root.type != bfd_link_hash_undefweak))
11736 {
11737 need_relocs = TRUE;
0855e32b 11738 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11739 }
11740
0855e32b
NS		 11741 if (tls_type & GOT_TLS_GDESC)
11742 {
47beaa6a
RS		 11743 bfd_byte *loc;
11744
0855e32b
NS		 11745 /* We should have relaxed, unless this is an undefined
11746 weak symbol. */
11747 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11748 || bfd_link_pic (info));
0855e32b 11749 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11750 <= globals->root.sgotplt->size);
0855e32b
NS		 11751
11752 outrel.r_addend = 0;
11753 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11754 + globals->root.sgotplt->output_offset
11755 + offplt
11756 + globals->sgotplt_jump_table_size);
b38cadfb 11757
0855e32b
NS		 11758 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11759 sreloc = globals->root.srelplt;
11760 loc = sreloc->contents;
11761 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11762 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11763 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11764
11765 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11766
11767 /* For globals, the first word in the relocation gets
11768 the relocation index and the top bit set, or zero,
11769 if we're binding now. For locals, it gets the
11770 symbol's offset in the tls section. */
99059e56 11771 bfd_put_32 (output_bfd,
0855e32b
NS		 11772 !h ? value - elf_hash_table (info)->tls_sec->vma
11773 : info->flags & DF_BIND_NOW ? 0
11774 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11775 globals->root.sgotplt->contents + offplt
11776 + globals->sgotplt_jump_table_size);
11777
0855e32b 11778 /* Second word in the relocation is always zero. */
99059e56 11779 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11780 globals->root.sgotplt->contents + offplt
11781 + globals->sgotplt_jump_table_size + 4);
0855e32b 11782 }
ba93b8ac
DJ		 11783 if (tls_type & GOT_TLS_GD)
11784 {
11785 if (need_relocs)
11786 {
00a97672 11787 outrel.r_addend = 0;
362d30a1
RS		 11788 outrel.r_offset = (sgot->output_section->vma
11789 + sgot->output_offset
00a97672 11790 + cur_off);
ba93b8ac 11791 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11792
00a97672
RS		 11793 if (globals->use_rel)
11794 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11795 sgot->contents + cur_off);
00a97672 11796
47beaa6a 11797 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11798
11799 if (indx == 0)
11800 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11801 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11802 else
11803 {
00a97672 11804 outrel.r_addend = 0;
ba93b8ac
DJ		 11805 outrel.r_info = ELF32_R_INFO (indx,
11806 R_ARM_TLS_DTPOFF32);
11807 outrel.r_offset += 4;
00a97672
RS		 11808
11809 if (globals->use_rel)
11810 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11811 sgot->contents + cur_off + 4);
00a97672 11812
47beaa6a
RS		 11813 elf32_arm_add_dynreloc (output_bfd, info,
11814 srelgot, &outrel);
ba93b8ac
DJ		 11815 }
11816 }
11817 else
11818 {
11819 /* If we are not emitting relocations for a
11820 general dynamic reference, then we must be in a
11821 static link or an executable link with the
11822 symbol binding locally. Mark it as belonging
11823 to module 1, the executable. */
11824 bfd_put_32 (output_bfd, 1,
362d30a1 11825 sgot->contents + cur_off);
ba93b8ac 11826 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11827 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11828 }
11829
11830 cur_off += 8;
11831 }
11832
11833 if (tls_type & GOT_TLS_IE)
11834 {
11835 if (need_relocs)
11836 {
00a97672
RS		 11837 if (indx == 0)
11838 outrel.r_addend = value - dtpoff_base (info);
11839 else
11840 outrel.r_addend = 0;
362d30a1
RS		 11841 outrel.r_offset = (sgot->output_section->vma
11842 + sgot->output_offset
ba93b8ac
DJ		 11843 + cur_off);
11844 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11845
00a97672
RS		 11846 if (globals->use_rel)
11847 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11848 sgot->contents + cur_off);
ba93b8ac 11849
47beaa6a 11850 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11851 }
11852 else
11853 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11854 sgot->contents + cur_off);
ba93b8ac
DJ		 11855 cur_off += 4;
11856 }
11857
11858 if (h != NULL)
11859 h->got.offset |= 1;
11860 else
11861 local_got_offsets[r_symndx] |= 1;
11862 }
11863
5c5a4843 11864 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
ba93b8ac 11865 off += 8;
0855e32b
NS		 11866 else if (tls_type & GOT_TLS_GDESC)
11867 off = offplt;
11868
11869 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11870 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11871 {
11872 bfd_signed_vma offset;
12352d3f
PB		 11873 /* TLS stubs are arm mode. The original symbol is a
11874 data object, so branch_type is bogus. */
11875 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11876 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11877 = arm_type_of_stub (info, input_section, rel,
11878 st_type, &branch_type,
0855e32b
NS		 11879 (struct elf32_arm_link_hash_entry *)h,
11880 globals->tls_trampoline, globals->root.splt,
11881 input_bfd, sym_name);
11882
11883 if (stub_type != arm_stub_none)
11884 {
11885 struct elf32_arm_stub_hash_entry *stub_entry
11886 = elf32_arm_get_stub_entry
11887 (input_section, globals->root.splt, 0, rel,
11888 globals, stub_type);
11889 offset = (stub_entry->stub_offset
11890 + stub_entry->stub_sec->output_offset
11891 + stub_entry->stub_sec->output_section->vma);
11892 }
11893 else
11894 offset = (globals->root.splt->output_section->vma
11895 + globals->root.splt->output_offset
11896 + globals->tls_trampoline);
11897
11898 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11899 {
11900 unsigned long inst;
b38cadfb
NC		 11901
11902 offset -= (input_section->output_section->vma
11903 + input_section->output_offset
11904 + rel->r_offset + 8);
0855e32b
NS		 11905
11906 inst = offset >> 2;
11907 inst &= 0x00ffffff;
11908 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11909 }
11910 else
11911 {
11912 /* Thumb blx encodes the offset in a complicated
11913 fashion. */
11914 unsigned upper_insn, lower_insn;
11915 unsigned neg;
11916
b38cadfb
NC		 11917 offset -= (input_section->output_section->vma
11918 + input_section->output_offset
0855e32b 11919 + rel->r_offset + 4);
b38cadfb 11920
12352d3f
PB		 11921 if (stub_type != arm_stub_none
11922 && arm_stub_is_thumb (stub_type))
11923 {
11924 lower_insn = 0xd000;
11925 }
11926 else
11927 {
11928 lower_insn = 0xc000;
6a631e86 11929 /* Round up the offset to a word boundary. */
12352d3f
PB		 11930 offset = (offset + 2) & ~2;
11931 }
11932
0855e32b
NS		 11933 neg = offset < 0;
11934 upper_insn = (0xf000
11935 | ((offset >> 12) & 0x3ff)
11936 | (neg << 10));
12352d3f 11937 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11938 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11939 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11940 bfd_put_16 (input_bfd, upper_insn, hit_data);
11941 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11942 return bfd_reloc_ok;
11943 }
11944 }
11945 /* These relocations needs special care, as besides the fact
11946 they point somewhere in .gotplt, the addend must be
11947 adjusted accordingly depending on the type of instruction
6a631e86 11948 we refer to. */
0855e32b
NS		 11949 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11950 {
11951 unsigned long data, insn;
11952 unsigned thumb;
b38cadfb 11953
0855e32b
NS		 11954 data = bfd_get_32 (input_bfd, hit_data);
11955 thumb = data & 1;
11956 data &= ~1u;
b38cadfb 11957
0855e32b
NS		 11958 if (thumb)
11959 {
11960 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11961 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11962 insn = (insn << 16)
11963 | bfd_get_16 (input_bfd,
11964 contents + rel->r_offset - data + 2);
11965 if ((insn & 0xf800c000) == 0xf000c000)
11966 /* bl/blx */
11967 value = -6;
11968 else if ((insn & 0xffffff00) == 0x4400)
11969 /* add */
11970 value = -5;
11971 else
11972 {
4eca0228 11973 _bfd_error_handler
695344c0 11974 /* xgettext:c-format */
2dcf00ce 11975 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 11976 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 11977 "referenced by TLS_GOTDESC"),
11978 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 11979 "Thumb", insn);
0855e32b
NS		 11980 return bfd_reloc_notsupported;
11981 }
11982 }
11983 else
11984 {
11985 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11986
11987 switch (insn >> 24)
11988 {
11989 case 0xeb: /* bl */
11990 case 0xfa: /* blx */
11991 value = -4;
11992 break;
11993
11994 case 0xe0: /* add */
11995 value = -8;
11996 break;
b38cadfb 11997
0855e32b 11998 default:
4eca0228 11999 _bfd_error_handler
695344c0 12000 /* xgettext:c-format */
2dcf00ce 12001 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12002 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12003 "referenced by TLS_GOTDESC"),
12004 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12005 "ARM", insn);
0855e32b
NS		 12006 return bfd_reloc_notsupported;
12007 }
12008 }
b38cadfb 12009
0855e32b
NS		 12010 value += ((globals->root.sgotplt->output_section->vma
12011 + globals->root.sgotplt->output_offset + off)
12012 - (input_section->output_section->vma
12013 + input_section->output_offset
12014 + rel->r_offset)
12015 + globals->sgotplt_jump_table_size);
12016 }
12017 else
12018 value = ((globals->root.sgot->output_section->vma
12019 + globals->root.sgot->output_offset + off)
12020 - (input_section->output_section->vma
12021 + input_section->output_offset + rel->r_offset));
ba93b8ac 12022
5c5a4843
CL		 12023 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
12024 r_type == R_ARM_TLS_IE32_FDPIC))
e8b09b87
CL		 12025 {
12026 /* For FDPIC relocations, resolve to the offset of the GOT
12027 entry from the start of GOT. */
12028 bfd_put_32(output_bfd,
12029 globals->root.sgot->output_offset + off,
12030 contents + rel->r_offset);
12031
12032 return bfd_reloc_ok;
12033 }
12034 else
12035 {
12036 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12037 contents, rel->r_offset, value,
12038 rel->r_addend);
12039 }
ba93b8ac
DJ		 12040 }
12041
12042 case R_ARM_TLS_LE32:
3cbc1e5e 12043 if (bfd_link_dll (info))
ba93b8ac 12044 {
4eca0228 12045 _bfd_error_handler
695344c0 12046 /* xgettext:c-format */
2dcf00ce
AM		 12047 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12048 "in shared object"),
12049 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 12050 return bfd_reloc_notsupported;
ba93b8ac
DJ		 12051 }
12052 else
12053 value = tpoff (info, value);
906e58ca 12054
ba93b8ac 12055 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 12056 contents, rel->r_offset, value,
12057 rel->r_addend);
ba93b8ac 12058
319850b4
JB		 12059 case R_ARM_V4BX:
12060 if (globals->fix_v4bx)
845b51d6
PB		 12061 {
12062 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 12063
845b51d6
PB		 12064 /* Ensure that we have a BX instruction. */
12065 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 12066
845b51d6
PB		 12067 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12068 {
12069 /* Branch to veneer. */
12070 bfd_vma glue_addr;
12071 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12072 glue_addr -= input_section->output_section->vma
12073 + input_section->output_offset
12074 + rel->r_offset + 8;
12075 insn = (insn & 0xf0000000) | 0x0a000000
12076 | ((glue_addr >> 2) & 0x00ffffff);
12077 }
12078 else
12079 {
12080 /* Preserve Rm (lowest four bits) and the condition code
12081 (highest four bits). Other bits encode MOV PC,Rm. */
12082 insn = (insn & 0xf000000f) | 0x01a0f000;
12083 }
319850b4 12084
845b51d6
PB		 12085 bfd_put_32 (input_bfd, insn, hit_data);
12086 }
319850b4
JB		 12087 return bfd_reloc_ok;
12088
b6895b4f
PB		 12089 case R_ARM_MOVW_ABS_NC:
12090 case R_ARM_MOVT_ABS:
12091 case R_ARM_MOVW_PREL_NC:
12092 case R_ARM_MOVT_PREL:
92f5d02b
MS		 12093 /* Until we properly support segment-base-relative addressing then
12094 we assume the segment base to be zero, as for the group relocations.
12095 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12096 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12097 case R_ARM_MOVW_BREL_NC:
12098 case R_ARM_MOVW_BREL:
12099 case R_ARM_MOVT_BREL:
b6895b4f
PB		 12100 {
12101 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12102
12103 if (globals->use_rel)
12104 {
12105 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 12106 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12107 }
92f5d02b 12108
b6895b4f 12109 value += signed_addend;
b6895b4f
PB		 12110
12111 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12112 value -= (input_section->output_section->vma
12113 + input_section->output_offset + rel->r_offset);
12114
92f5d02b 12115 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 12116 return bfd_reloc_overflow;
92f5d02b 12117
35fc36a8 12118 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12119 value |= 1;
12120
12121 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 12122 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 12123 value >>= 16;
12124
12125 insn &= 0xfff0f000;
12126 insn |= value & 0xfff;
12127 insn |= (value & 0xf000) << 4;
12128 bfd_put_32 (input_bfd, insn, hit_data);
12129 }
12130 return bfd_reloc_ok;
12131
12132 case R_ARM_THM_MOVW_ABS_NC:
12133 case R_ARM_THM_MOVT_ABS:
12134 case R_ARM_THM_MOVW_PREL_NC:
12135 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 12136 /* Until we properly support segment-base-relative addressing then
12137 we assume the segment base to be zero, as for the above relocations.
12138 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12139 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12140 as R_ARM_THM_MOVT_ABS. */
12141 case R_ARM_THM_MOVW_BREL_NC:
12142 case R_ARM_THM_MOVW_BREL:
12143 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 12144 {
12145 bfd_vma insn;
906e58ca 12146
b6895b4f
PB		 12147 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12148 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12149
12150 if (globals->use_rel)
12151 {
12152 addend = ((insn >> 4) & 0xf000)
12153 | ((insn >> 15) & 0x0800)
12154 | ((insn >> 4) & 0x0700)
07d6d2b8 12155 | (insn & 0x00ff);
39623e12 12156 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12157 }
92f5d02b 12158
b6895b4f 12159 value += signed_addend;
b6895b4f
PB		 12160
12161 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12162 value -= (input_section->output_section->vma
12163 + input_section->output_offset + rel->r_offset);
12164
92f5d02b 12165 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 12166 return bfd_reloc_overflow;
92f5d02b 12167
35fc36a8 12168 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12169 value |= 1;
12170
12171 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 12172 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 12173 value >>= 16;
12174
12175 insn &= 0xfbf08f00;
12176 insn |= (value & 0xf000) << 4;
12177 insn |= (value & 0x0800) << 15;
12178 insn |= (value & 0x0700) << 4;
12179 insn |= (value & 0x00ff);
12180
12181 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12182 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12183 }
12184 return bfd_reloc_ok;
12185
4962c51a
MS		 12186 case R_ARM_ALU_PC_G0_NC:
12187 case R_ARM_ALU_PC_G1_NC:
12188 case R_ARM_ALU_PC_G0:
12189 case R_ARM_ALU_PC_G1:
12190 case R_ARM_ALU_PC_G2:
12191 case R_ARM_ALU_SB_G0_NC:
12192 case R_ARM_ALU_SB_G1_NC:
12193 case R_ARM_ALU_SB_G0:
12194 case R_ARM_ALU_SB_G1:
12195 case R_ARM_ALU_SB_G2:
12196 {
12197 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12198 bfd_vma pc = input_section->output_section->vma
4962c51a 12199 + input_section->output_offset + rel->r_offset;
31a91d61 12200 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12201 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 12202 bfd_vma residual;
12203 bfd_vma g_n;
4962c51a 12204 bfd_signed_vma signed_value;
99059e56
RM		 12205 int group = 0;
12206
12207 /* Determine which group of bits to select. */
12208 switch (r_type)
12209 {
12210 case R_ARM_ALU_PC_G0_NC:
12211 case R_ARM_ALU_PC_G0:
12212 case R_ARM_ALU_SB_G0_NC:
12213 case R_ARM_ALU_SB_G0:
12214 group = 0;
12215 break;
12216
12217 case R_ARM_ALU_PC_G1_NC:
12218 case R_ARM_ALU_PC_G1:
12219 case R_ARM_ALU_SB_G1_NC:
12220 case R_ARM_ALU_SB_G1:
12221 group = 1;
12222 break;
12223
12224 case R_ARM_ALU_PC_G2:
12225 case R_ARM_ALU_SB_G2:
12226 group = 2;
12227 break;
12228
12229 default:
12230 abort ();
12231 }
12232
12233 /* If REL, extract the addend from the insn. If RELA, it will
12234 have already been fetched for us. */
4962c51a 12235 if (globals->use_rel)
99059e56
RM		 12236 {
12237 int negative;
12238 bfd_vma constant = insn & 0xff;
12239 bfd_vma rotation = (insn & 0xf00) >> 8;
12240
12241 if (rotation == 0)
12242 signed_addend = constant;
12243 else
12244 {
12245 /* Compensate for the fact that in the instruction, the
12246 rotation is stored in multiples of 2 bits. */
12247 rotation *= 2;
12248
12249 /* Rotate "constant" right by "rotation" bits. */
12250 signed_addend = (constant >> rotation) |
12251 (constant << (8 * sizeof (bfd_vma) - rotation));
12252 }
12253
12254 /* Determine if the instruction is an ADD or a SUB.
12255 (For REL, this determines the sign of the addend.) */
12256 negative = identify_add_or_sub (insn);
12257 if (negative == 0)
12258 {
4eca0228 12259 _bfd_error_handler
695344c0 12260 /* xgettext:c-format */
90b6238f 12261 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 12262 "are allowed for ALU group relocations"),
12263 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 12264 return bfd_reloc_overflow;
12265 }
12266
12267 signed_addend *= negative;
12268 }
4962c51a
MS		 12269
12270 /* Compute the value (X) to go in the place. */
99059e56
RM		 12271 if (r_type == R_ARM_ALU_PC_G0_NC
12272 || r_type == R_ARM_ALU_PC_G1_NC
12273 || r_type == R_ARM_ALU_PC_G0
12274 || r_type == R_ARM_ALU_PC_G1
12275 || r_type == R_ARM_ALU_PC_G2)
12276 /* PC relative. */
12277 signed_value = value - pc + signed_addend;
12278 else
12279 /* Section base relative. */
12280 signed_value = value - sb + signed_addend;
12281
12282 /* If the target symbol is a Thumb function, then set the
12283 Thumb bit in the address. */
35fc36a8 12284 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 12285 signed_value |= 1;
12286
99059e56
RM		 12287 /* Calculate the value of the relevant G_n, in encoded
12288 constant-with-rotation format. */
b6518b38
NC		 12289 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12290 group, &residual);
99059e56
RM		 12291
12292 /* Check for overflow if required. */
12293 if ((r_type == R_ARM_ALU_PC_G0
12294 || r_type == R_ARM_ALU_PC_G1
12295 || r_type == R_ARM_ALU_PC_G2
12296 || r_type == R_ARM_ALU_SB_G0
12297 || r_type == R_ARM_ALU_SB_G1
12298 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12299 {
4eca0228 12300 _bfd_error_handler
695344c0 12301 /* xgettext:c-format */
90b6238f 12302 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12303 "splitting %#" PRIx64 " for group relocation %s"),
12304 input_bfd, input_section, (uint64_t) rel->r_offset,
12305 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12306 howto->name);
99059e56
RM		 12307 return bfd_reloc_overflow;
12308 }
12309
12310 /* Mask out the value and the ADD/SUB part of the opcode; take care
12311 not to destroy the S bit. */
12312 insn &= 0xff1ff000;
12313
12314 /* Set the opcode according to whether the value to go in the
12315 place is negative. */
12316 if (signed_value < 0)
12317 insn |= 1 << 22;
12318 else
12319 insn |= 1 << 23;
12320
12321 /* Encode the offset. */
12322 insn |= g_n;
4962c51a
MS		 12323
12324 bfd_put_32 (input_bfd, insn, hit_data);
12325 }
12326 return bfd_reloc_ok;
12327
12328 case R_ARM_LDR_PC_G0:
12329 case R_ARM_LDR_PC_G1:
12330 case R_ARM_LDR_PC_G2:
12331 case R_ARM_LDR_SB_G0:
12332 case R_ARM_LDR_SB_G1:
12333 case R_ARM_LDR_SB_G2:
12334 {
12335 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12336 bfd_vma pc = input_section->output_section->vma
4962c51a 12337 + input_section->output_offset + rel->r_offset;
31a91d61 12338 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12339 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12340 bfd_vma residual;
4962c51a 12341 bfd_signed_vma signed_value;
99059e56
RM		 12342 int group = 0;
12343
12344 /* Determine which groups of bits to calculate. */
12345 switch (r_type)
12346 {
12347 case R_ARM_LDR_PC_G0:
12348 case R_ARM_LDR_SB_G0:
12349 group = 0;
12350 break;
12351
12352 case R_ARM_LDR_PC_G1:
12353 case R_ARM_LDR_SB_G1:
12354 group = 1;
12355 break;
12356
12357 case R_ARM_LDR_PC_G2:
12358 case R_ARM_LDR_SB_G2:
12359 group = 2;
12360 break;
12361
12362 default:
12363 abort ();
12364 }
12365
12366 /* If REL, extract the addend from the insn. If RELA, it will
12367 have already been fetched for us. */
4962c51a 12368 if (globals->use_rel)
99059e56
RM		 12369 {
12370 int negative = (insn & (1 << 23)) ? 1 : -1;
12371 signed_addend = negative * (insn & 0xfff);
12372 }
4962c51a
MS		 12373
12374 /* Compute the value (X) to go in the place. */
99059e56
RM		 12375 if (r_type == R_ARM_LDR_PC_G0
12376 || r_type == R_ARM_LDR_PC_G1
12377 || r_type == R_ARM_LDR_PC_G2)
12378 /* PC relative. */
12379 signed_value = value - pc + signed_addend;
12380 else
12381 /* Section base relative. */
12382 signed_value = value - sb + signed_addend;
12383
12384 /* Calculate the value of the relevant G_{n-1} to obtain
12385 the residual at that stage. */
b6518b38
NC		 12386 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12387 group - 1, &residual);
99059e56
RM		 12388
12389 /* Check for overflow. */
12390 if (residual >= 0x1000)
12391 {
4eca0228 12392 _bfd_error_handler
695344c0 12393 /* xgettext:c-format */
90b6238f 12394 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12395 "splitting %#" PRIx64 " for group relocation %s"),
12396 input_bfd, input_section, (uint64_t) rel->r_offset,
12397 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12398 howto->name);
99059e56
RM		 12399 return bfd_reloc_overflow;
12400 }
12401
12402 /* Mask out the value and U bit. */
12403 insn &= 0xff7ff000;
12404
12405 /* Set the U bit if the value to go in the place is non-negative. */
12406 if (signed_value >= 0)
12407 insn |= 1 << 23;
12408
12409 /* Encode the offset. */
12410 insn |= residual;
4962c51a
MS		 12411
12412 bfd_put_32 (input_bfd, insn, hit_data);
12413 }
12414 return bfd_reloc_ok;
12415
12416 case R_ARM_LDRS_PC_G0:
12417 case R_ARM_LDRS_PC_G1:
12418 case R_ARM_LDRS_PC_G2:
12419 case R_ARM_LDRS_SB_G0:
12420 case R_ARM_LDRS_SB_G1:
12421 case R_ARM_LDRS_SB_G2:
12422 {
12423 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12424 bfd_vma pc = input_section->output_section->vma
4962c51a 12425 + input_section->output_offset + rel->r_offset;
31a91d61 12426 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12427 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12428 bfd_vma residual;
4962c51a 12429 bfd_signed_vma signed_value;
99059e56
RM		 12430 int group = 0;
12431
12432 /* Determine which groups of bits to calculate. */
12433 switch (r_type)
12434 {
12435 case R_ARM_LDRS_PC_G0:
12436 case R_ARM_LDRS_SB_G0:
12437 group = 0;
12438 break;
12439
12440 case R_ARM_LDRS_PC_G1:
12441 case R_ARM_LDRS_SB_G1:
12442 group = 1;
12443 break;
12444
12445 case R_ARM_LDRS_PC_G2:
12446 case R_ARM_LDRS_SB_G2:
12447 group = 2;
12448 break;
12449
12450 default:
12451 abort ();
12452 }
12453
12454 /* If REL, extract the addend from the insn. If RELA, it will
12455 have already been fetched for us. */
4962c51a 12456 if (globals->use_rel)
99059e56
RM		 12457 {
12458 int negative = (insn & (1 << 23)) ? 1 : -1;
12459 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12460 }
4962c51a
MS		 12461
12462 /* Compute the value (X) to go in the place. */
99059e56
RM		 12463 if (r_type == R_ARM_LDRS_PC_G0
12464 || r_type == R_ARM_LDRS_PC_G1
12465 || r_type == R_ARM_LDRS_PC_G2)
12466 /* PC relative. */
12467 signed_value = value - pc + signed_addend;
12468 else
12469 /* Section base relative. */
12470 signed_value = value - sb + signed_addend;
12471
12472 /* Calculate the value of the relevant G_{n-1} to obtain
12473 the residual at that stage. */
b6518b38
NC		 12474 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12475 group - 1, &residual);
99059e56
RM		 12476
12477 /* Check for overflow. */
12478 if (residual >= 0x100)
12479 {
4eca0228 12480 _bfd_error_handler
695344c0 12481 /* xgettext:c-format */
90b6238f 12482 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12483 "splitting %#" PRIx64 " for group relocation %s"),
12484 input_bfd, input_section, (uint64_t) rel->r_offset,
12485 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12486 howto->name);
99059e56
RM		 12487 return bfd_reloc_overflow;
12488 }
12489
12490 /* Mask out the value and U bit. */
12491 insn &= 0xff7ff0f0;
12492
12493 /* Set the U bit if the value to go in the place is non-negative. */
12494 if (signed_value >= 0)
12495 insn |= 1 << 23;
12496
12497 /* Encode the offset. */
12498 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12499
12500 bfd_put_32 (input_bfd, insn, hit_data);
12501 }
12502 return bfd_reloc_ok;
12503
12504 case R_ARM_LDC_PC_G0:
12505 case R_ARM_LDC_PC_G1:
12506 case R_ARM_LDC_PC_G2:
12507 case R_ARM_LDC_SB_G0:
12508 case R_ARM_LDC_SB_G1:
12509 case R_ARM_LDC_SB_G2:
12510 {
12511 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12512 bfd_vma pc = input_section->output_section->vma
4962c51a 12513 + input_section->output_offset + rel->r_offset;
31a91d61 12514 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12515 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12516 bfd_vma residual;
4962c51a 12517 bfd_signed_vma signed_value;
99059e56
RM		 12518 int group = 0;
12519
12520 /* Determine which groups of bits to calculate. */
12521 switch (r_type)
12522 {
12523 case R_ARM_LDC_PC_G0:
12524 case R_ARM_LDC_SB_G0:
12525 group = 0;
12526 break;
12527
12528 case R_ARM_LDC_PC_G1:
12529 case R_ARM_LDC_SB_G1:
12530 group = 1;
12531 break;
12532
12533 case R_ARM_LDC_PC_G2:
12534 case R_ARM_LDC_SB_G2:
12535 group = 2;
12536 break;
12537
12538 default:
12539 abort ();
12540 }
12541
12542 /* If REL, extract the addend from the insn. If RELA, it will
12543 have already been fetched for us. */
4962c51a 12544 if (globals->use_rel)
99059e56
RM		 12545 {
12546 int negative = (insn & (1 << 23)) ? 1 : -1;
12547 signed_addend = negative * ((insn & 0xff) << 2);
12548 }
4962c51a
MS		 12549
12550 /* Compute the value (X) to go in the place. */
99059e56
RM		 12551 if (r_type == R_ARM_LDC_PC_G0
12552 || r_type == R_ARM_LDC_PC_G1
12553 || r_type == R_ARM_LDC_PC_G2)
12554 /* PC relative. */
12555 signed_value = value - pc + signed_addend;
12556 else
12557 /* Section base relative. */
12558 signed_value = value - sb + signed_addend;
12559
12560 /* Calculate the value of the relevant G_{n-1} to obtain
12561 the residual at that stage. */
b6518b38
NC		 12562 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12563 group - 1, &residual);
99059e56
RM		 12564
12565 /* Check for overflow. (The absolute value to go in the place must be
12566 divisible by four and, after having been divided by four, must
12567 fit in eight bits.) */
12568 if ((residual & 0x3) != 0 || residual >= 0x400)
12569 {
4eca0228 12570 _bfd_error_handler
695344c0 12571 /* xgettext:c-format */
90b6238f 12572 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12573 "splitting %#" PRIx64 " for group relocation %s"),
12574 input_bfd, input_section, (uint64_t) rel->r_offset,
12575 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12576 howto->name);
99059e56
RM		 12577 return bfd_reloc_overflow;
12578 }
12579
12580 /* Mask out the value and U bit. */
12581 insn &= 0xff7fff00;
12582
12583 /* Set the U bit if the value to go in the place is non-negative. */
12584 if (signed_value >= 0)
12585 insn |= 1 << 23;
12586
12587 /* Encode the offset. */
12588 insn |= residual >> 2;
4962c51a
MS		 12589
12590 bfd_put_32 (input_bfd, insn, hit_data);
12591 }
12592 return bfd_reloc_ok;
12593
72d98d16
MG		 12594 case R_ARM_THM_ALU_ABS_G0_NC:
12595 case R_ARM_THM_ALU_ABS_G1_NC:
12596 case R_ARM_THM_ALU_ABS_G2_NC:
12597 case R_ARM_THM_ALU_ABS_G3_NC:
12598 {
12599 const int shift_array[4] = {0, 8, 16, 24};
12600 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12601 bfd_vma addr = value;
12602 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12603
12604 /* Compute address. */
12605 if (globals->use_rel)
12606 signed_addend = insn & 0xff;
12607 addr += signed_addend;
12608 if (branch_type == ST_BRANCH_TO_THUMB)
12609 addr |= 1;
12610 /* Clean imm8 insn. */
12611 insn &= 0xff00;
12612 /* And update with correct part of address. */
12613 insn |= (addr >> shift) & 0xff;
12614 /* Update insn. */
12615 bfd_put_16 (input_bfd, insn, hit_data);
12616 }
12617
12618 *unresolved_reloc_p = FALSE;
12619 return bfd_reloc_ok;
12620
e8b09b87
CL		 12621 case R_ARM_GOTOFFFUNCDESC:
12622 {
4b24dd1a 12623 if (h == NULL)
e8b09b87
CL		 12624 {
12625 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12626 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12627 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12628 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12629 bfd_vma seg = -1;
12630
12631 if (bfd_link_pic(info) && dynindx == 0)
12632 abort();
12633
12634 /* Resolve relocation. */
12635 bfd_put_32(output_bfd, (offset + sgot->output_offset)
12636 , contents + rel->r_offset);
12637 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12638 not done yet. */
12639 arm_elf_fill_funcdesc(output_bfd, info,
12640 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12641 dynindx, offset, addr, dynreloc_value, seg);
12642 }
12643 else
12644 {
12645 int dynindx;
12646 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12647 bfd_vma addr;
12648 bfd_vma seg = -1;
12649
12650 /* For static binaries, sym_sec can be null. */
12651 if (sym_sec)
12652 {
12653 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12654 addr = dynreloc_value - sym_sec->output_section->vma;
12655 }
12656 else
12657 {
12658 dynindx = 0;
12659 addr = 0;
12660 }
12661
12662 if (bfd_link_pic(info) && dynindx == 0)
12663 abort();
12664
12665 /* This case cannot occur since funcdesc is allocated by
12666 the dynamic loader so we cannot resolve the relocation. */
12667 if (h->dynindx != -1)
12668 abort();
12669
12670 /* Resolve relocation. */
12671 bfd_put_32(output_bfd, (offset + sgot->output_offset),
12672 contents + rel->r_offset);
12673 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12674 arm_elf_fill_funcdesc(output_bfd, info,
12675 &eh->fdpic_cnts.funcdesc_offset,
12676 dynindx, offset, addr, dynreloc_value, seg);
12677 }
12678 }
12679 *unresolved_reloc_p = FALSE;
12680 return bfd_reloc_ok;
12681
12682 case R_ARM_GOTFUNCDESC:
12683 {
4b24dd1a 12684 if (h != NULL)
e8b09b87
CL		 12685 {
12686 Elf_Internal_Rela outrel;
12687
12688 /* Resolve relocation. */
12689 bfd_put_32(output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12690 + sgot->output_offset),
12691 contents + rel->r_offset);
12692 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12693 if(h->dynindx == -1)
12694 {
12695 int dynindx;
12696 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12697 bfd_vma addr;
12698 bfd_vma seg = -1;
12699
12700 /* For static binaries sym_sec can be null. */
12701 if (sym_sec)
12702 {
12703 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12704 addr = dynreloc_value - sym_sec->output_section->vma;
12705 }
12706 else
12707 {
12708 dynindx = 0;
12709 addr = 0;
12710 }
12711
12712 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12713 arm_elf_fill_funcdesc(output_bfd, info,
12714 &eh->fdpic_cnts.funcdesc_offset,
12715 dynindx, offset, addr, dynreloc_value, seg);
12716 }
12717
12718 /* Add a dynamic relocation on GOT entry if not already done. */
12719 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12720 {
12721 if (h->dynindx == -1)
12722 {
12723 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12724 if (h->root.type == bfd_link_hash_undefweak)
12725 bfd_put_32(output_bfd, 0, sgot->contents
12726 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12727 else
12728 bfd_put_32(output_bfd, sgot->output_section->vma
12729 + sgot->output_offset
12730 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12731 sgot->contents
12732 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12733 }
12734 else
12735 {
12736 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12737 }
12738 outrel.r_offset = sgot->output_section->vma
12739 + sgot->output_offset
12740 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12741 outrel.r_addend = 0;
12742 if (h->dynindx == -1 && !bfd_link_pic(info))
12743 if (h->root.type == bfd_link_hash_undefweak)
4b24dd1a 12744 arm_elf_add_rofixup(output_bfd, globals->srofixup, -1);
e8b09b87 12745 else
4b24dd1a
AM		 12746 arm_elf_add_rofixup(output_bfd, globals->srofixup,
12747 outrel.r_offset);
e8b09b87
CL		 12748 else
12749 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12750 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12751 }
12752 }
12753 else
12754 {
12755 /* Such relocation on static function should not have been
12756 emitted by the compiler. */
12757 abort();
12758 }
12759 }
12760 *unresolved_reloc_p = FALSE;
12761 return bfd_reloc_ok;
12762
12763 case R_ARM_FUNCDESC:
12764 {
4b24dd1a 12765 if (h == NULL)
e8b09b87
CL		 12766 {
12767 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12768 Elf_Internal_Rela outrel;
12769 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12770 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12771 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12772 bfd_vma seg = -1;
12773
12774 if (bfd_link_pic(info) && dynindx == 0)
12775 abort();
12776
12777 /* Replace static FUNCDESC relocation with a
12778 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12779 executable. */
12780 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12781 outrel.r_offset = input_section->output_section->vma
12782 + input_section->output_offset + rel->r_offset;
12783 outrel.r_addend = 0;
12784 if (bfd_link_pic(info))
12785 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12786 else
12787 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12788
12789 bfd_put_32 (input_bfd, sgot->output_section->vma
12790 + sgot->output_offset + offset, hit_data);
12791
12792 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12793 arm_elf_fill_funcdesc(output_bfd, info,
12794 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12795 dynindx, offset, addr, dynreloc_value, seg);
12796 }
12797 else
12798 {
12799 if (h->dynindx == -1)
12800 {
12801 int dynindx;
12802 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12803 bfd_vma addr;
12804 bfd_vma seg = -1;
12805 Elf_Internal_Rela outrel;
12806
12807 /* For static binaries sym_sec can be null. */
12808 if (sym_sec)
12809 {
12810 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12811 addr = dynreloc_value - sym_sec->output_section->vma;
12812 }
12813 else
12814 {
12815 dynindx = 0;
12816 addr = 0;
12817 }
12818
12819 if (bfd_link_pic(info) && dynindx == 0)
12820 abort();
12821
12822 /* Replace static FUNCDESC relocation with a
12823 R_ARM_RELATIVE dynamic relocation. */
12824 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12825 outrel.r_offset = input_section->output_section->vma
12826 + input_section->output_offset + rel->r_offset;
12827 outrel.r_addend = 0;
12828 if (bfd_link_pic(info))
12829 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12830 else
12831 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12832
12833 bfd_put_32 (input_bfd, sgot->output_section->vma
12834 + sgot->output_offset + offset, hit_data);
12835
12836 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12837 arm_elf_fill_funcdesc(output_bfd, info,
12838 &eh->fdpic_cnts.funcdesc_offset,
12839 dynindx, offset, addr, dynreloc_value, seg);
12840 }
12841 else
12842 {
12843 Elf_Internal_Rela outrel;
12844
12845 /* Add a dynamic relocation. */
12846 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12847 outrel.r_offset = input_section->output_section->vma
12848 + input_section->output_offset + rel->r_offset;
12849 outrel.r_addend = 0;
12850 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12851 }
12852 }
12853 }
12854 *unresolved_reloc_p = FALSE;
12855 return bfd_reloc_ok;
12856
252b5132
RH		 12857 default:
12858 return bfd_reloc_notsupported;
12859 }
12860}
12861
98c1d4aa
NC		 12862/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12863static void
07d6d2b8
AM		 12864arm_add_to_rel (bfd * abfd,
12865 bfd_byte * address,
57e8b36a 12866 reloc_howto_type * howto,
07d6d2b8 12867 bfd_signed_vma increment)
98c1d4aa 12868{
98c1d4aa
NC		 12869 bfd_signed_vma addend;
12870
bd97cb95
DJ		 12871 if (howto->type == R_ARM_THM_CALL
12872 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 12873 {
9a5aca8c
AM		 12874 int upper_insn, lower_insn;
12875 int upper, lower;
98c1d4aa 12876
9a5aca8c
AM		 12877 upper_insn = bfd_get_16 (abfd, address);
12878 lower_insn = bfd_get_16 (abfd, address + 2);
12879 upper = upper_insn & 0x7ff;
12880 lower = lower_insn & 0x7ff;
12881
12882 addend = (upper << 12) | (lower << 1);
ddda4409 12883 addend += increment;
9a5aca8c 12884 addend >>= 1;
98c1d4aa 12885
9a5aca8c
AM		 12886 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
12887 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
12888
dc810e39
AM		 12889 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
12890 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 12891 }
12892 else
12893 {
07d6d2b8 12894 bfd_vma contents;
9a5aca8c
AM		 12895
12896 contents = bfd_get_32 (abfd, address);
12897
12898 /* Get the (signed) value from the instruction. */
12899 addend = contents & howto->src_mask;
12900 if (addend & ((howto->src_mask + 1) >> 1))
12901 {
12902 bfd_signed_vma mask;
12903
12904 mask = -1;
12905 mask &= ~ howto->src_mask;
12906 addend |= mask;
12907 }
12908
12909 /* Add in the increment, (which is a byte value). */
12910 switch (howto->type)
12911 {
12912 default:
12913 addend += increment;
12914 break;
12915
12916 case R_ARM_PC24:
c6596c5e 12917 case R_ARM_PLT32:
5b5bb741
PB		 12918 case R_ARM_CALL:
12919 case R_ARM_JUMP24:
9a5aca8c 12920 addend <<= howto->size;
dc810e39 12921 addend += increment;
9a5aca8c
AM		 12922
12923 /* Should we check for overflow here ? */
12924
12925 /* Drop any undesired bits. */
12926 addend >>= howto->rightshift;
12927 break;
12928 }
12929
12930 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
12931
12932 bfd_put_32 (abfd, contents, address);
ddda4409 12933 }
98c1d4aa 12934}
252b5132 12935
ba93b8ac
DJ		 12936#define IS_ARM_TLS_RELOC(R_TYPE) \
12937 ((R_TYPE) == R_ARM_TLS_GD32 \
5c5a4843 12938 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
ba93b8ac
DJ		 12939 || (R_TYPE) == R_ARM_TLS_LDO32 \
12940 || (R_TYPE) == R_ARM_TLS_LDM32 \
5c5a4843 12941 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
ba93b8ac
DJ		 12942 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12943 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12944 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12945 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b 12946 || (R_TYPE) == R_ARM_TLS_IE32 \
5c5a4843 12947 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
0855e32b
NS		 12948 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12949
12950/* Specific set of relocations for the gnu tls dialect. */
12951#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12952 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12953 || (R_TYPE) == R_ARM_TLS_CALL \
12954 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12955 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12956 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 12957
252b5132 12958/* Relocate an ARM ELF section. */
906e58ca 12959
b34976b6 12960static bfd_boolean
07d6d2b8 12961elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 12962 struct bfd_link_info * info,
07d6d2b8
AM		 12963 bfd * input_bfd,
12964 asection * input_section,
12965 bfd_byte * contents,
12966 Elf_Internal_Rela * relocs,
12967 Elf_Internal_Sym * local_syms,
12968 asection ** local_sections)
252b5132 12969{
b34976b6
AM		 12970 Elf_Internal_Shdr *symtab_hdr;
12971 struct elf_link_hash_entry **sym_hashes;
12972 Elf_Internal_Rela *rel;
12973 Elf_Internal_Rela *relend;
12974 const char *name;
b32d3aa2 12975 struct elf32_arm_link_hash_table * globals;
252b5132 12976
4e7fd91e 12977 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 12978 if (globals == NULL)
12979 return FALSE;
b491616a 12980
0ffa91dd 12981 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 12982 sym_hashes = elf_sym_hashes (input_bfd);
12983
12984 rel = relocs;
12985 relend = relocs + input_section->reloc_count;
12986 for (; rel < relend; rel++)
12987 {
07d6d2b8
AM		 12988 int r_type;
12989 reloc_howto_type * howto;
12990 unsigned long r_symndx;
12991 Elf_Internal_Sym * sym;
12992 asection * sec;
252b5132 12993 struct elf_link_hash_entry * h;
07d6d2b8
AM		 12994 bfd_vma relocation;
12995 bfd_reloc_status_type r;
12996 arelent bfd_reloc;
12997 char sym_type;
12998 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 12999 char *error_message = NULL;
f21f3fe0 13000
252b5132 13001 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 13002 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 13003 r_type = arm_real_reloc_type (globals, r_type);
252b5132 13004
ba96a88f 13005 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 13006 || r_type == R_ARM_GNU_VTINHERIT)
13007 continue;
252b5132 13008
47aeb64c
NC		 13009 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
13010
13011 if (howto == NULL)
13012 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 13013
252b5132
RH		 13014 h = NULL;
13015 sym = NULL;
13016 sec = NULL;
9b485d32 13017
252b5132
RH		 13018 if (r_symndx < symtab_hdr->sh_info)
13019 {
13020 sym = local_syms + r_symndx;
ba93b8ac 13021 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 13022 sec = local_sections[r_symndx];
ffcb4889
NS		 13023
13024 /* An object file might have a reference to a local
13025 undefined symbol. This is a daft object file, but we
13026 should at least do something about it. V4BX & NONE
13027 relocations do not use the symbol and are explicitly
77b4f08f
TS		 13028 allowed to use the undefined symbol, so allow those.
13029 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 13030 if (r_type != R_ARM_V4BX
13031 && r_type != R_ARM_NONE
77b4f08f 13032 && r_symndx != STN_UNDEF
ffcb4889
NS		 13033 && bfd_is_und_section (sec)
13034 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 13035 (*info->callbacks->undefined_symbol)
13036 (info, bfd_elf_string_from_elf_section
13037 (input_bfd, symtab_hdr->sh_link, sym->st_name),
13038 input_bfd, input_section,
13039 rel->r_offset, TRUE);
b38cadfb 13040
4e7fd91e 13041 if (globals->use_rel)
f8df10f4 13042 {
4e7fd91e
PB		 13043 relocation = (sec->output_section->vma
13044 + sec->output_offset
13045 + sym->st_value);
0e1862bb 13046 if (!bfd_link_relocatable (info)
ab96bf03
AM		 13047 && (sec->flags & SEC_MERGE)
13048 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 13049 {
4e7fd91e
PB		 13050 asection *msec;
13051 bfd_vma addend, value;
13052
39623e12 13053 switch (r_type)
4e7fd91e 13054 {
39623e12
PB		 13055 case R_ARM_MOVW_ABS_NC:
13056 case R_ARM_MOVT_ABS:
13057 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13058 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13059 addend = (addend ^ 0x8000) - 0x8000;
13060 break;
f8df10f4 13061
39623e12
PB		 13062 case R_ARM_THM_MOVW_ABS_NC:
13063 case R_ARM_THM_MOVT_ABS:
13064 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13065 << 16;
13066 value |= bfd_get_16 (input_bfd,
13067 contents + rel->r_offset + 2);
13068 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13069 | ((value & 0x04000000) >> 15);
13070 addend = (addend ^ 0x8000) - 0x8000;
13071 break;
f8df10f4 13072
39623e12
PB		 13073 default:
13074 if (howto->rightshift
13075 || (howto->src_mask & (howto->src_mask + 1)))
13076 {
4eca0228 13077 _bfd_error_handler
695344c0 13078 /* xgettext:c-format */
2dcf00ce
AM		 13079 (_("%pB(%pA+%#" PRIx64 "): "
13080 "%s relocation against SEC_MERGE section"),
39623e12 13081 input_bfd, input_section,
2dcf00ce 13082 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 13083 return FALSE;
13084 }
13085
13086 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13087
13088 /* Get the (signed) value from the instruction. */
13089 addend = value & howto->src_mask;
13090 if (addend & ((howto->src_mask + 1) >> 1))
13091 {
13092 bfd_signed_vma mask;
13093
13094 mask = -1;
13095 mask &= ~ howto->src_mask;
13096 addend |= mask;
13097 }
13098 break;
4e7fd91e 13099 }
39623e12 13100
4e7fd91e
PB		 13101 msec = sec;
13102 addend =
13103 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13104 - relocation;
13105 addend += msec->output_section->vma + msec->output_offset;
39623e12 13106
cc643b88 13107 /* Cases here must match those in the preceding
39623e12
PB		 13108 switch statement. */
13109 switch (r_type)
13110 {
13111 case R_ARM_MOVW_ABS_NC:
13112 case R_ARM_MOVT_ABS:
13113 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13114 | (addend & 0xfff);
13115 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13116 break;
13117
13118 case R_ARM_THM_MOVW_ABS_NC:
13119 case R_ARM_THM_MOVT_ABS:
13120 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13121 | (addend & 0xff) | ((addend & 0x0800) << 15);
13122 bfd_put_16 (input_bfd, value >> 16,
13123 contents + rel->r_offset);
13124 bfd_put_16 (input_bfd, value,
13125 contents + rel->r_offset + 2);
13126 break;
13127
13128 default:
13129 value = (value & ~ howto->dst_mask)
13130 | (addend & howto->dst_mask);
13131 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13132 break;
13133 }
f8df10f4 13134 }
f8df10f4 13135 }
4e7fd91e
PB		 13136 else
13137 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 13138 }
13139 else
13140 {
62d887d4 13141 bfd_boolean warned, ignored;
560e09e9 13142
b2a8e766
AM		 13143 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13144 r_symndx, symtab_hdr, sym_hashes,
13145 h, sec, relocation,
62d887d4 13146 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 13147
13148 sym_type = h->type;
252b5132
RH		 13149 }
13150
dbaa2011 13151 if (sec != NULL && discarded_section (sec))
e4067dbb 13152 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 13153 rel, 1, relend, howto, 0, contents);
ab96bf03 13154
0e1862bb 13155 if (bfd_link_relocatable (info))
ab96bf03
AM		 13156 {
13157 /* This is a relocatable link. We don't have to change
13158 anything, unless the reloc is against a section symbol,
13159 in which case we have to adjust according to where the
13160 section symbol winds up in the output section. */
13161 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13162 {
13163 if (globals->use_rel)
13164 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13165 howto, (bfd_signed_vma) sec->output_offset);
13166 else
13167 rel->r_addend += sec->output_offset;
13168 }
13169 continue;
13170 }
13171
252b5132
RH		 13172 if (h != NULL)
13173 name = h->root.root.string;
13174 else
13175 {
13176 name = (bfd_elf_string_from_elf_section
13177 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13178 if (name == NULL || *name == '\0')
13179 name = bfd_section_name (input_bfd, sec);
13180 }
f21f3fe0 13181
cf35638d 13182 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 13183 && r_type != R_ARM_NONE
13184 && (h == NULL
13185 || h->root.type == bfd_link_hash_defined
13186 || h->root.type == bfd_link_hash_defweak)
13187 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13188 {
4eca0228 13189 _bfd_error_handler
ba93b8ac 13190 ((sym_type == STT_TLS
695344c0 13191 /* xgettext:c-format */
2dcf00ce 13192 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 13193 /* xgettext:c-format */
2dcf00ce 13194 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 13195 input_bfd,
13196 input_section,
2dcf00ce 13197 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 13198 howto->name,
13199 name);
13200 }
13201
0855e32b 13202 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 13203 done, i.e., the relaxation produced the final output we want,
13204 and we won't let anybody mess with it. Also, we have to do
13205 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 13206 both in relaxed and non-relaxed cases. */
39d911fc
TP		 13207 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13208 || (IS_ARM_TLS_GNU_RELOC (r_type)
13209 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13210 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13211 & GOT_TLS_GDESC)))
13212 {
13213 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13214 contents, rel, h == NULL);
13215 /* This may have been marked unresolved because it came from
13216 a shared library. But we've just dealt with that. */
13217 unresolved_reloc = 0;
13218 }
13219 else
13220 r = bfd_reloc_continue;
b38cadfb 13221
39d911fc
TP		 13222 if (r == bfd_reloc_continue)
13223 {
13224 unsigned char branch_type =
13225 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13226 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13227
13228 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13229 input_section, contents, rel,
13230 relocation, info, sec, name,
13231 sym_type, branch_type, h,
13232 &unresolved_reloc,
13233 &error_message);
13234 }
0945cdfd
DJ		 13235
13236 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13237 because such sections are not SEC_ALLOC and thus ld.so will
13238 not process them. */
13239 if (unresolved_reloc
99059e56
RM		 13240 && !((input_section->flags & SEC_DEBUGGING) != 0
13241 && h->def_dynamic)
1d5316ab
AM		 13242 && _bfd_elf_section_offset (output_bfd, info, input_section,
13243 rel->r_offset) != (bfd_vma) -1)
0945cdfd 13244 {
4eca0228 13245 _bfd_error_handler
695344c0 13246 /* xgettext:c-format */
2dcf00ce
AM		 13247 (_("%pB(%pA+%#" PRIx64 "): "
13248 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 13249 input_bfd,
13250 input_section,
2dcf00ce 13251 (uint64_t) rel->r_offset,
843fe662
L		 13252 howto->name,
13253 h->root.root.string);
0945cdfd
DJ		 13254 return FALSE;
13255 }
252b5132
RH		 13256
13257 if (r != bfd_reloc_ok)
13258 {
252b5132
RH		 13259 switch (r)
13260 {
13261 case bfd_reloc_overflow:
cf919dfd
PB		 13262 /* If the overflowing reloc was to an undefined symbol,
13263 we have already printed one error message and there
13264 is no point complaining again. */
1a72702b
AM		 13265 if (!h || h->root.type != bfd_link_hash_undefined)
13266 (*info->callbacks->reloc_overflow)
13267 (info, (h ? &h->root : NULL), name, howto->name,
13268 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13269 break;
13270
13271 case bfd_reloc_undefined:
1a72702b
AM		 13272 (*info->callbacks->undefined_symbol)
13273 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 13274 break;
13275
13276 case bfd_reloc_outofrange:
f2a9dd69 13277 error_message = _("out of range");
252b5132
RH		 13278 goto common_error;
13279
13280 case bfd_reloc_notsupported:
f2a9dd69 13281 error_message = _("unsupported relocation");
252b5132
RH		 13282 goto common_error;
13283
13284 case bfd_reloc_dangerous:
f2a9dd69 13285 /* error_message should already be set. */
252b5132
RH		 13286 goto common_error;
13287
13288 default:
f2a9dd69 13289 error_message = _("unknown error");
8029a119 13290 /* Fall through. */
252b5132
RH		 13291
13292 common_error:
f2a9dd69 13293 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 13294 (*info->callbacks->reloc_dangerous)
13295 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13296 break;
13297 }
13298 }
13299 }
13300
b34976b6 13301 return TRUE;
252b5132
RH		 13302}
13303
91d6fa6a 13304/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 13305 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 13306 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 13307 maintaining that condition). */
13308
13309static void
13310add_unwind_table_edit (arm_unwind_table_edit **head,
13311 arm_unwind_table_edit **tail,
13312 arm_unwind_edit_type type,
13313 asection *linked_section,
91d6fa6a 13314 unsigned int tindex)
2468f9c9 13315{
21d799b5
NC		 13316 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13317 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 13318
2468f9c9
PB		 13319 new_edit->type = type;
13320 new_edit->linked_section = linked_section;
91d6fa6a 13321 new_edit->index = tindex;
b38cadfb 13322
91d6fa6a 13323 if (tindex > 0)
2468f9c9
PB		 13324 {
13325 new_edit->next = NULL;
13326
13327 if (*tail)
13328 (*tail)->next = new_edit;
13329
13330 (*tail) = new_edit;
13331
13332 if (!*head)
13333 (*head) = new_edit;
13334 }
13335 else
13336 {
13337 new_edit->next = *head;
13338
13339 if (!*tail)
13340 *tail = new_edit;
13341
13342 *head = new_edit;
13343 }
13344}
13345
13346static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13347
13348/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13349static void
13350adjust_exidx_size(asection *exidx_sec, int adjust)
13351{
13352 asection *out_sec;
13353
13354 if (!exidx_sec->rawsize)
13355 exidx_sec->rawsize = exidx_sec->size;
13356
13357 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
13358 out_sec = exidx_sec->output_section;
13359 /* Adjust size of output section. */
13360 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
13361}
13362
13363/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13364static void
13365insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
13366{
13367 struct _arm_elf_section_data *exidx_arm_data;
13368
13369 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13370 add_unwind_table_edit (
13371 &exidx_arm_data->u.exidx.unwind_edit_list,
13372 &exidx_arm_data->u.exidx.unwind_edit_tail,
13373 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13374
491d01d3
YU		 13375 exidx_arm_data->additional_reloc_count++;
13376
2468f9c9
PB		 13377 adjust_exidx_size(exidx_sec, 8);
13378}
13379
13380/* Scan .ARM.exidx tables, and create a list describing edits which should be
13381 made to those tables, such that:
b38cadfb 13382
2468f9c9
PB		 13383 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13384 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 13385 codes which have been inlined into the index).
2468f9c9 13386
85fdf906
AH		 13387 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13388
2468f9c9 13389 The edits are applied when the tables are written
b38cadfb 13390 (in elf32_arm_write_section). */
2468f9c9
PB		 13391
13392bfd_boolean
13393elf32_arm_fix_exidx_coverage (asection **text_section_order,
13394 unsigned int num_text_sections,
85fdf906
AH		 13395 struct bfd_link_info *info,
13396 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 13397{
13398 bfd *inp;
13399 unsigned int last_second_word = 0, i;
13400 asection *last_exidx_sec = NULL;
13401 asection *last_text_sec = NULL;
13402 int last_unwind_type = -1;
13403
13404 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13405 text sections. */
c72f2fb2 13406 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 13407 {
13408 asection *sec;
b38cadfb 13409
2468f9c9 13410 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 13411 {
2468f9c9
PB		 13412 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13413 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 13414
dec9d5df 13415 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 13416 continue;
b38cadfb 13417
2468f9c9
PB		 13418 if (elf_sec->linked_to)
13419 {
13420 Elf_Internal_Shdr *linked_hdr
99059e56 13421 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 13422 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 13423 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 13424
13425 if (linked_sec_arm_data == NULL)
99059e56 13426 continue;
2468f9c9
PB		 13427
13428 /* Link this .ARM.exidx section back from the text section it
99059e56 13429 describes. */
2468f9c9
PB		 13430 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13431 }
13432 }
13433 }
13434
13435 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13436 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 13437 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 13438
13439 for (i = 0; i < num_text_sections; i++)
13440 {
13441 asection *sec = text_section_order[i];
13442 asection *exidx_sec;
13443 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13444 struct _arm_elf_section_data *exidx_arm_data;
13445 bfd_byte *contents = NULL;
13446 int deleted_exidx_bytes = 0;
13447 bfd_vma j;
13448 arm_unwind_table_edit *unwind_edit_head = NULL;
13449 arm_unwind_table_edit *unwind_edit_tail = NULL;
13450 Elf_Internal_Shdr *hdr;
13451 bfd *ibfd;
13452
13453 if (arm_data == NULL)
99059e56 13454 continue;
2468f9c9
PB		 13455
13456 exidx_sec = arm_data->u.text.arm_exidx_sec;
13457 if (exidx_sec == NULL)
13458 {
13459 /* Section has no unwind data. */
13460 if (last_unwind_type == 0 || !last_exidx_sec)
13461 continue;
13462
13463 /* Ignore zero sized sections. */
13464 if (sec->size == 0)
13465 continue;
13466
13467 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13468 last_unwind_type = 0;
13469 continue;
13470 }
13471
22a8f80e
PB		 13472 /* Skip /DISCARD/ sections. */
13473 if (bfd_is_abs_section (exidx_sec->output_section))
13474 continue;
13475
2468f9c9
PB		 13476 hdr = &elf_section_data (exidx_sec)->this_hdr;
13477 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 13478 continue;
b38cadfb 13479
2468f9c9
PB		 13480 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13481 if (exidx_arm_data == NULL)
99059e56 13482 continue;
b38cadfb 13483
2468f9c9 13484 ibfd = exidx_sec->owner;
b38cadfb 13485
2468f9c9
PB		 13486 if (hdr->contents != NULL)
13487 contents = hdr->contents;
13488 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13489 /* An error? */
13490 continue;
13491
ac06903d
YU		 13492 if (last_unwind_type > 0)
13493 {
13494 unsigned int first_word = bfd_get_32 (ibfd, contents);
13495 /* Add cantunwind if first unwind item does not match section
13496 start. */
13497 if (first_word != sec->vma)
13498 {
13499 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13500 last_unwind_type = 0;
13501 }
13502 }
13503
2468f9c9
PB		 13504 for (j = 0; j < hdr->sh_size; j += 8)
13505 {
13506 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13507 int unwind_type;
13508 int elide = 0;
13509
13510 /* An EXIDX_CANTUNWIND entry. */
13511 if (second_word == 1)
13512 {
13513 if (last_unwind_type == 0)
13514 elide = 1;
13515 unwind_type = 0;
13516 }
13517 /* Inlined unwinding data. Merge if equal to previous. */
13518 else if ((second_word & 0x80000000) != 0)
13519 {
85fdf906
AH		 13520 if (merge_exidx_entries
13521 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 13522 elide = 1;
13523 unwind_type = 1;
13524 last_second_word = second_word;
13525 }
13526 /* Normal table entry. In theory we could merge these too,
13527 but duplicate entries are likely to be much less common. */
13528 else
13529 unwind_type = 2;
13530
491d01d3 13531 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 13532 {
13533 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13534 DELETE_EXIDX_ENTRY, NULL, j / 8);
13535
13536 deleted_exidx_bytes += 8;
13537 }
13538
13539 last_unwind_type = unwind_type;
13540 }
13541
13542 /* Free contents if we allocated it ourselves. */
13543 if (contents != hdr->contents)
99059e56 13544 free (contents);
2468f9c9
PB		 13545
13546 /* Record edits to be applied later (in elf32_arm_write_section). */
13547 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13548 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 13549
2468f9c9
PB		 13550 if (deleted_exidx_bytes > 0)
13551 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
13552
13553 last_exidx_sec = exidx_sec;
13554 last_text_sec = sec;
13555 }
13556
13557 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 13558 if (!bfd_link_relocatable (info) && last_exidx_sec
13559 && last_unwind_type != 0)
2468f9c9
PB		 13560 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13561
13562 return TRUE;
13563}
13564
3e6b1042
DJ		 13565static bfd_boolean
13566elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13567 bfd *ibfd, const char *name)
13568{
13569 asection *sec, *osec;
13570
3d4d4302 13571 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 13572 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13573 return TRUE;
13574
13575 osec = sec->output_section;
13576 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13577 return TRUE;
13578
13579 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13580 sec->output_offset, sec->size))
13581 return FALSE;
13582
13583 return TRUE;
13584}
13585
13586static bfd_boolean
13587elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13588{
13589 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 13590 asection *sec, *osec;
3e6b1042 13591
4dfe6ac6
NC		 13592 if (globals == NULL)
13593 return FALSE;
13594
3e6b1042
DJ		 13595 /* Invoke the regular ELF backend linker to do all the work. */
13596 if (!bfd_elf_final_link (abfd, info))
13597 return FALSE;
13598
fe33d2fa
CL		 13599 /* Process stub sections (eg BE8 encoding, ...). */
13600 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 13601 unsigned int i;
cdb21a0a
NS		 13602 for (i=0; i<htab->top_id; i++)
13603 {
13604 sec = htab->stub_group[i].stub_sec;
13605 /* Only process it once, in its link_sec slot. */
13606 if (sec && i == htab->stub_group[i].link_sec->id)
13607 {
13608 osec = sec->output_section;
13609 elf32_arm_write_section (abfd, info, sec, sec->contents);
13610 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13611 sec->output_offset, sec->size))
13612 return FALSE;
13613 }
fe33d2fa 13614 }
fe33d2fa 13615
3e6b1042
DJ		 13616 /* Write out any glue sections now that we have created all the
13617 stubs. */
13618 if (globals->bfd_of_glue_owner != NULL)
13619 {
13620 if (! elf32_arm_output_glue_section (info, abfd,
13621 globals->bfd_of_glue_owner,
13622 ARM2THUMB_GLUE_SECTION_NAME))
13623 return FALSE;
13624
13625 if (! elf32_arm_output_glue_section (info, abfd,
13626 globals->bfd_of_glue_owner,
13627 THUMB2ARM_GLUE_SECTION_NAME))
13628 return FALSE;
13629
13630 if (! elf32_arm_output_glue_section (info, abfd,
13631 globals->bfd_of_glue_owner,
13632 VFP11_ERRATUM_VENEER_SECTION_NAME))
13633 return FALSE;
13634
a504d23a
LA		 13635 if (! elf32_arm_output_glue_section (info, abfd,
13636 globals->bfd_of_glue_owner,
13637 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13638 return FALSE;
13639
3e6b1042
DJ		 13640 if (! elf32_arm_output_glue_section (info, abfd,
13641 globals->bfd_of_glue_owner,
13642 ARM_BX_GLUE_SECTION_NAME))
13643 return FALSE;
13644 }
13645
13646 return TRUE;
13647}
13648
5968a7b8
NC		 13649/* Return a best guess for the machine number based on the attributes. */
13650
13651static unsigned int
13652bfd_arm_get_mach_from_attributes (bfd * abfd)
13653{
13654 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13655
13656 switch (arch)
13657 {
c0c468d5 13658 case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
5968a7b8
NC		 13659 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13660 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13661 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13662
13663 case TAG_CPU_ARCH_V5TE:
13664 {
13665 char * name;
13666
13667 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13668 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13669
13670 if (name)
13671 {
13672 if (strcmp (name, "IWMMXT2") == 0)
13673 return bfd_mach_arm_iWMMXt2;
13674
13675 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13676 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13677
13678 if (strcmp (name, "XSCALE") == 0)
13679 {
13680 int wmmx;
13681
13682 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13683 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13684 switch (wmmx)
13685 {
13686 case 1: return bfd_mach_arm_iWMMXt;
13687 case 2: return bfd_mach_arm_iWMMXt2;
13688 default: return bfd_mach_arm_XScale;
13689 }
13690 }
5968a7b8
NC		 13691 }
13692
13693 return bfd_mach_arm_5TE;
13694 }
13695
c0c468d5
TP		 13696 case TAG_CPU_ARCH_V5TEJ:
13697 return bfd_mach_arm_5TEJ;
13698 case TAG_CPU_ARCH_V6:
13699 return bfd_mach_arm_6;
13700 case TAG_CPU_ARCH_V6KZ:
13701 return bfd_mach_arm_6KZ;
13702 case TAG_CPU_ARCH_V6T2:
13703 return bfd_mach_arm_6T2;
13704 case TAG_CPU_ARCH_V6K:
13705 return bfd_mach_arm_6K;
13706 case TAG_CPU_ARCH_V7:
13707 return bfd_mach_arm_7;
13708 case TAG_CPU_ARCH_V6_M:
13709 return bfd_mach_arm_6M;
13710 case TAG_CPU_ARCH_V6S_M:
13711 return bfd_mach_arm_6SM;
13712 case TAG_CPU_ARCH_V7E_M:
13713 return bfd_mach_arm_7EM;
13714 case TAG_CPU_ARCH_V8:
13715 return bfd_mach_arm_8;
13716 case TAG_CPU_ARCH_V8R:
13717 return bfd_mach_arm_8R;
13718 case TAG_CPU_ARCH_V8M_BASE:
13719 return bfd_mach_arm_8M_BASE;
13720 case TAG_CPU_ARCH_V8M_MAIN:
13721 return bfd_mach_arm_8M_MAIN;
13722
5968a7b8 13723 default:
c0c468d5
TP		 13724 /* Force entry to be added for any new known Tag_CPU_arch value. */
13725 BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
13726
13727 /* Unknown Tag_CPU_arch value. */
5968a7b8
NC		 13728 return bfd_mach_arm_unknown;
13729 }
13730}
13731
c178919b
NC		 13732/* Set the right machine number. */
13733
13734static bfd_boolean
57e8b36a 13735elf32_arm_object_p (bfd *abfd)
c178919b 13736{
5a6c6817 13737 unsigned int mach;
57e8b36a 13738
5a6c6817 13739 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13740
5968a7b8
NC		 13741 if (mach == bfd_mach_arm_unknown)
13742 {
13743 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13744 mach = bfd_mach_arm_ep9312;
13745 else
13746 mach = bfd_arm_get_mach_from_attributes (abfd);
13747 }
c178919b 13748
5968a7b8 13749 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13750 return TRUE;
13751}
13752
fc830a83 13753/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13754
b34976b6 13755static bfd_boolean
57e8b36a 13756elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13757{
13758 if (elf_flags_init (abfd)
13759 && elf_elfheader (abfd)->e_flags != flags)
13760 {
fc830a83
NC		 13761 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13762 {
fd2ec330 13763 if (flags & EF_ARM_INTERWORK)
4eca0228 13764 _bfd_error_handler
90b6238f 13765 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13766 abfd);
fc830a83 13767 else
d003868e 13768 _bfd_error_handler
90b6238f 13769 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13770 abfd);
fc830a83 13771 }
252b5132
RH		 13772 }
13773 else
13774 {
13775 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13776 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13777 }
13778
b34976b6 13779 return TRUE;
252b5132
RH		 13780}
13781
fc830a83 13782/* Copy backend specific data from one object module to another. */
9b485d32 13783
b34976b6 13784static bfd_boolean
57e8b36a 13785elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13786{
13787 flagword in_flags;
13788 flagword out_flags;
13789
0ffa91dd 13790 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13791 return TRUE;
252b5132 13792
fc830a83 13793 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13794 out_flags = elf_elfheader (obfd)->e_flags;
13795
fc830a83
NC		 13796 if (elf_flags_init (obfd)
13797 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13798 && in_flags != out_flags)
252b5132 13799 {
252b5132 13800 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13801 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13802 return FALSE;
252b5132
RH		 13803
13804 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13805 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13806 return FALSE;
252b5132
RH		 13807
13808 /* If the src and dest have different interworking flags
99059e56 13809 then turn off the interworking bit. */
fd2ec330 13810 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13811 {
fd2ec330 13812 if (out_flags & EF_ARM_INTERWORK)
d003868e 13813 _bfd_error_handler
90b6238f 13814 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 13815 obfd, ibfd);
252b5132 13816
fd2ec330 13817 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13818 }
1006ba19
PB		 13819
13820 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13821 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13822 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13823 }
13824
13825 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13826 elf_flags_init (obfd) = TRUE;
252b5132 13827
e2349352 13828 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13829}
13830
13831/* Values for Tag_ABI_PCS_R9_use. */
13832enum
13833{
13834 AEABI_R9_V6,
13835 AEABI_R9_SB,
13836 AEABI_R9_TLS,
13837 AEABI_R9_unused
13838};
13839
13840/* Values for Tag_ABI_PCS_RW_data. */
13841enum
13842{
13843 AEABI_PCS_RW_data_absolute,
13844 AEABI_PCS_RW_data_PCrel,
13845 AEABI_PCS_RW_data_SBrel,
13846 AEABI_PCS_RW_data_unused
13847};
13848
13849/* Values for Tag_ABI_enum_size. */
13850enum
13851{
13852 AEABI_enum_unused,
13853 AEABI_enum_short,
13854 AEABI_enum_wide,
13855 AEABI_enum_forced_wide
13856};
13857
104d59d1
JM		 13858/* Determine whether an object attribute tag takes an integer, a
13859 string or both. */
906e58ca 13860
104d59d1
JM		 13861static int
13862elf32_arm_obj_attrs_arg_type (int tag)
13863{
13864 if (tag == Tag_compatibility)
3483fe2e 13865 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 13866 else if (tag == Tag_nodefaults)
3483fe2e
AS		 13867 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
13868 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
13869 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 13870 else if (tag < 32)
3483fe2e 13871 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 13872 else
3483fe2e 13873 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 13874}
13875
5aa6ff7c
AS		 13876/* The ABI defines that Tag_conformance should be emitted first, and that
13877 Tag_nodefaults should be second (if either is defined). This sets those
13878 two positions, and bumps up the position of all the remaining tags to
13879 compensate. */
13880static int
13881elf32_arm_obj_attrs_order (int num)
13882{
3de4a297 13883 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 13884 return Tag_conformance;
3de4a297 13885 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 13886 return Tag_nodefaults;
13887 if ((num - 2) < Tag_nodefaults)
13888 return num - 2;
13889 if ((num - 1) < Tag_conformance)
13890 return num - 1;
13891 return num;
13892}
13893
e8b36cd1
JM		 13894/* Attribute numbers >=64 (mod 128) can be safely ignored. */
13895static bfd_boolean
13896elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
13897{
13898 if ((tag & 127) < 64)
13899 {
13900 _bfd_error_handler
90b6238f 13901 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 13902 abfd, tag);
13903 bfd_set_error (bfd_error_bad_value);
13904 return FALSE;
13905 }
13906 else
13907 {
13908 _bfd_error_handler
90b6238f 13909 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 13910 abfd, tag);
13911 return TRUE;
13912 }
13913}
13914
91e22acd
AS		 13915/* Read the architecture from the Tag_also_compatible_with attribute, if any.
13916 Returns -1 if no architecture could be read. */
13917
13918static int
13919get_secondary_compatible_arch (bfd *abfd)
13920{
13921 obj_attribute *attr =
13922 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
13923
13924 /* Note: the tag and its argument below are uleb128 values, though
13925 currently-defined values fit in one byte for each. */
13926 if (attr->s
13927 && attr->s[0] == Tag_CPU_arch
13928 && (attr->s[1] & 128) != 128
13929 && attr->s[2] == 0)
13930 return attr->s[1];
13931
13932 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13933 return -1;
13934}
13935
13936/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13937 The tag is removed if ARCH is -1. */
13938
8e79c3df 13939static void
91e22acd 13940set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 13941{
91e22acd
AS		 13942 obj_attribute *attr =
13943 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 13944
91e22acd
AS		 13945 if (arch == -1)
13946 {
13947 attr->s = NULL;
13948 return;
8e79c3df 13949 }
91e22acd
AS		 13950
13951 /* Note: the tag and its argument below are uleb128 values, though
13952 currently-defined values fit in one byte for each. */
13953 if (!attr->s)
21d799b5 13954 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 13955 attr->s[0] = Tag_CPU_arch;
13956 attr->s[1] = arch;
13957 attr->s[2] = '\0';
8e79c3df
CM		 13958}
13959
91e22acd
AS		 13960/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13961 into account. */
13962
13963static int
13964tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
13965 int newtag, int secondary_compat)
8e79c3df 13966{
91e22acd
AS		 13967#define T(X) TAG_CPU_ARCH_##X
13968 int tagl, tagh, result;
13969 const int v6t2[] =
13970 {
13971 T(V6T2), /* PRE_V4. */
13972 T(V6T2), /* V4. */
13973 T(V6T2), /* V4T. */
13974 T(V6T2), /* V5T. */
13975 T(V6T2), /* V5TE. */
13976 T(V6T2), /* V5TEJ. */
13977 T(V6T2), /* V6. */
13978 T(V7), /* V6KZ. */
13979 T(V6T2) /* V6T2. */
13980 };
13981 const int v6k[] =
13982 {
13983 T(V6K), /* PRE_V4. */
13984 T(V6K), /* V4. */
13985 T(V6K), /* V4T. */
13986 T(V6K), /* V5T. */
13987 T(V6K), /* V5TE. */
13988 T(V6K), /* V5TEJ. */
13989 T(V6K), /* V6. */
13990 T(V6KZ), /* V6KZ. */
13991 T(V7), /* V6T2. */
13992 T(V6K) /* V6K. */
13993 };
13994 const int v7[] =
13995 {
13996 T(V7), /* PRE_V4. */
13997 T(V7), /* V4. */
13998 T(V7), /* V4T. */
13999 T(V7), /* V5T. */
14000 T(V7), /* V5TE. */
14001 T(V7), /* V5TEJ. */
14002 T(V7), /* V6. */
14003 T(V7), /* V6KZ. */
14004 T(V7), /* V6T2. */
14005 T(V7), /* V6K. */
14006 T(V7) /* V7. */
14007 };
14008 const int v6_m[] =
14009 {
07d6d2b8
AM		 14010 -1, /* PRE_V4. */
14011 -1, /* V4. */
91e22acd
AS		 14012 T(V6K), /* V4T. */
14013 T(V6K), /* V5T. */
14014 T(V6K), /* V5TE. */
14015 T(V6K), /* V5TEJ. */
14016 T(V6K), /* V6. */
14017 T(V6KZ), /* V6KZ. */
14018 T(V7), /* V6T2. */
14019 T(V6K), /* V6K. */
14020 T(V7), /* V7. */
14021 T(V6_M) /* V6_M. */
14022 };
14023 const int v6s_m[] =
14024 {
07d6d2b8
AM		 14025 -1, /* PRE_V4. */
14026 -1, /* V4. */
91e22acd
AS		 14027 T(V6K), /* V4T. */
14028 T(V6K), /* V5T. */
14029 T(V6K), /* V5TE. */
14030 T(V6K), /* V5TEJ. */
14031 T(V6K), /* V6. */
14032 T(V6KZ), /* V6KZ. */
14033 T(V7), /* V6T2. */
14034 T(V6K), /* V6K. */
14035 T(V7), /* V7. */
14036 T(V6S_M), /* V6_M. */
14037 T(V6S_M) /* V6S_M. */
14038 };
9e3c6df6
PB		 14039 const int v7e_m[] =
14040 {
07d6d2b8
AM		 14041 -1, /* PRE_V4. */
14042 -1, /* V4. */
9e3c6df6
PB		 14043 T(V7E_M), /* V4T. */
14044 T(V7E_M), /* V5T. */
14045 T(V7E_M), /* V5TE. */
14046 T(V7E_M), /* V5TEJ. */
14047 T(V7E_M), /* V6. */
14048 T(V7E_M), /* V6KZ. */
14049 T(V7E_M), /* V6T2. */
14050 T(V7E_M), /* V6K. */
14051 T(V7E_M), /* V7. */
14052 T(V7E_M), /* V6_M. */
14053 T(V7E_M), /* V6S_M. */
14054 T(V7E_M) /* V7E_M. */
14055 };
bca38921
MGD		 14056 const int v8[] =
14057 {
14058 T(V8), /* PRE_V4. */
14059 T(V8), /* V4. */
14060 T(V8), /* V4T. */
14061 T(V8), /* V5T. */
14062 T(V8), /* V5TE. */
14063 T(V8), /* V5TEJ. */
14064 T(V8), /* V6. */
14065 T(V8), /* V6KZ. */
14066 T(V8), /* V6T2. */
14067 T(V8), /* V6K. */
14068 T(V8), /* V7. */
14069 T(V8), /* V6_M. */
14070 T(V8), /* V6S_M. */
14071 T(V8), /* V7E_M. */
14072 T(V8) /* V8. */
14073 };
bff0500d
TP		 14074 const int v8r[] =
14075 {
14076 T(V8R), /* PRE_V4. */
14077 T(V8R), /* V4. */
14078 T(V8R), /* V4T. */
14079 T(V8R), /* V5T. */
14080 T(V8R), /* V5TE. */
14081 T(V8R), /* V5TEJ. */
14082 T(V8R), /* V6. */
14083 T(V8R), /* V6KZ. */
14084 T(V8R), /* V6T2. */
14085 T(V8R), /* V6K. */
14086 T(V8R), /* V7. */
14087 T(V8R), /* V6_M. */
14088 T(V8R), /* V6S_M. */
14089 T(V8R), /* V7E_M. */
14090 T(V8), /* V8. */
14091 T(V8R), /* V8R. */
14092 };
2fd158eb
TP		 14093 const int v8m_baseline[] =
14094 {
14095 -1, /* PRE_V4. */
14096 -1, /* V4. */
14097 -1, /* V4T. */
14098 -1, /* V5T. */
14099 -1, /* V5TE. */
14100 -1, /* V5TEJ. */
14101 -1, /* V6. */
14102 -1, /* V6KZ. */
14103 -1, /* V6T2. */
14104 -1, /* V6K. */
14105 -1, /* V7. */
14106 T(V8M_BASE), /* V6_M. */
14107 T(V8M_BASE), /* V6S_M. */
14108 -1, /* V7E_M. */
14109 -1, /* V8. */
bff0500d 14110 -1, /* V8R. */
2fd158eb
TP		 14111 T(V8M_BASE) /* V8-M BASELINE. */
14112 };
14113 const int v8m_mainline[] =
14114 {
14115 -1, /* PRE_V4. */
14116 -1, /* V4. */
14117 -1, /* V4T. */
14118 -1, /* V5T. */
14119 -1, /* V5TE. */
14120 -1, /* V5TEJ. */
14121 -1, /* V6. */
14122 -1, /* V6KZ. */
14123 -1, /* V6T2. */
14124 -1, /* V6K. */
14125 T(V8M_MAIN), /* V7. */
14126 T(V8M_MAIN), /* V6_M. */
14127 T(V8M_MAIN), /* V6S_M. */
14128 T(V8M_MAIN), /* V7E_M. */
14129 -1, /* V8. */
bff0500d 14130 -1, /* V8R. */
2fd158eb
TP		 14131 T(V8M_MAIN), /* V8-M BASELINE. */
14132 T(V8M_MAIN) /* V8-M MAINLINE. */
14133 };
91e22acd
AS		 14134 const int v4t_plus_v6_m[] =
14135 {
14136 -1, /* PRE_V4. */
14137 -1, /* V4. */
14138 T(V4T), /* V4T. */
14139 T(V5T), /* V5T. */
14140 T(V5TE), /* V5TE. */
14141 T(V5TEJ), /* V5TEJ. */
14142 T(V6), /* V6. */
14143 T(V6KZ), /* V6KZ. */
14144 T(V6T2), /* V6T2. */
14145 T(V6K), /* V6K. */
14146 T(V7), /* V7. */
14147 T(V6_M), /* V6_M. */
14148 T(V6S_M), /* V6S_M. */
9e3c6df6 14149 T(V7E_M), /* V7E_M. */
bca38921 14150 T(V8), /* V8. */
bff0500d 14151 -1, /* V8R. */
2fd158eb
TP		 14152 T(V8M_BASE), /* V8-M BASELINE. */
14153 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 14154 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14155 };
14156 const int *comb[] =
14157 {
14158 v6t2,
14159 v6k,
14160 v7,
14161 v6_m,
14162 v6s_m,
9e3c6df6 14163 v7e_m,
bca38921 14164 v8,
bff0500d 14165 v8r,
2fd158eb
TP		 14166 v8m_baseline,
14167 v8m_mainline,
91e22acd
AS		 14168 /* Pseudo-architecture. */
14169 v4t_plus_v6_m
14170 };
14171
14172 /* Check we've not got a higher architecture than we know about. */
14173
9e3c6df6 14174 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 14175 {
90b6238f 14176 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 14177 return -1;
14178 }
14179
14180 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14181
14182 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14183 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14184 oldtag = T(V4T_PLUS_V6_M);
14185
14186 /* And override the new tag if we have a Tag_also_compatible_with on the
14187 input. */
14188
14189 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14190 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14191 newtag = T(V4T_PLUS_V6_M);
14192
14193 tagl = (oldtag < newtag) ? oldtag : newtag;
14194 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14195
14196 /* Architectures before V6KZ add features monotonically. */
14197 if (tagh <= TAG_CPU_ARCH_V6KZ)
14198 return result;
14199
4ed7ed8d 14200 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 14201
14202 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14203 as the canonical version. */
14204 if (result == T(V4T_PLUS_V6_M))
14205 {
14206 result = T(V4T);
14207 *secondary_compat_out = T(V6_M);
14208 }
14209 else
14210 *secondary_compat_out = -1;
14211
14212 if (result == -1)
14213 {
90b6238f 14214 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 14215 ibfd, oldtag, newtag);
14216 return -1;
14217 }
14218
14219 return result;
14220#undef T
8e79c3df
CM		 14221}
14222
ac56ee8f
MGD		 14223/* Query attributes object to see if integer divide instructions may be
14224 present in an object. */
14225static bfd_boolean
14226elf32_arm_attributes_accept_div (const obj_attribute *attr)
14227{
14228 int arch = attr[Tag_CPU_arch].i;
14229 int profile = attr[Tag_CPU_arch_profile].i;
14230
14231 switch (attr[Tag_DIV_use].i)
14232 {
14233 case 0:
14234 /* Integer divide allowed if instruction contained in archetecture. */
14235 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14236 return TRUE;
14237 else if (arch >= TAG_CPU_ARCH_V7E_M)
14238 return TRUE;
14239 else
14240 return FALSE;
14241
14242 case 1:
14243 /* Integer divide explicitly prohibited. */
14244 return FALSE;
14245
14246 default:
14247 /* Unrecognised case - treat as allowing divide everywhere. */
14248 case 2:
14249 /* Integer divide allowed in ARM state. */
14250 return TRUE;
14251 }
14252}
14253
14254/* Query attributes object to see if integer divide instructions are
14255 forbidden to be in the object. This is not the inverse of
14256 elf32_arm_attributes_accept_div. */
14257static bfd_boolean
14258elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14259{
14260 return attr[Tag_DIV_use].i == 1;
14261}
14262
ee065d83
PB		 14263/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14264 are conflicting attributes. */
906e58ca 14265
ee065d83 14266static bfd_boolean
50e03d47 14267elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 14268{
50e03d47 14269 bfd *obfd = info->output_bfd;
104d59d1
JM		 14270 obj_attribute *in_attr;
14271 obj_attribute *out_attr;
ee065d83
PB		 14272 /* Some tags have 0 = don't care, 1 = strong requirement,
14273 2 = weak requirement. */
91e22acd 14274 static const int order_021[3] = {0, 2, 1};
ee065d83 14275 int i;
91e22acd 14276 bfd_boolean result = TRUE;
9274e9de 14277 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 14278
3e6b1042
DJ		 14279 /* Skip the linker stubs file. This preserves previous behavior
14280 of accepting unknown attributes in the first input file - but
14281 is that a bug? */
14282 if (ibfd->flags & BFD_LINKER_CREATED)
14283 return TRUE;
14284
9274e9de
TG		 14285 /* Skip any input that hasn't attribute section.
14286 This enables to link object files without attribute section with
14287 any others. */
14288 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14289 return TRUE;
14290
104d59d1 14291 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 14292 {
14293 /* This is the first object. Copy the attributes. */
104d59d1 14294 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 14295
cd21e546
MGD		 14296 out_attr = elf_known_obj_attributes_proc (obfd);
14297
004ae526
PB		 14298 /* Use the Tag_null value to indicate the attributes have been
14299 initialized. */
cd21e546 14300 out_attr[0].i = 1;
004ae526 14301
cd21e546
MGD		 14302 /* We do not output objects with Tag_MPextension_use_legacy - we move
14303 the attribute's value to Tag_MPextension_use. */
14304 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14305 {
14306 if (out_attr[Tag_MPextension_use].i != 0
14307 && out_attr[Tag_MPextension_use_legacy].i
99059e56 14308 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 14309 {
14310 _bfd_error_handler
871b3ab2 14311 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 14312 "Tag_MPextension_use attributes"), ibfd);
14313 result = FALSE;
14314 }
14315
14316 out_attr[Tag_MPextension_use] =
14317 out_attr[Tag_MPextension_use_legacy];
14318 out_attr[Tag_MPextension_use_legacy].type = 0;
14319 out_attr[Tag_MPextension_use_legacy].i = 0;
14320 }
14321
14322 return result;
ee065d83
PB		 14323 }
14324
104d59d1
JM		 14325 in_attr = elf_known_obj_attributes_proc (ibfd);
14326 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 14327 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14328 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14329 {
5c294fee
TG		 14330 /* Ignore mismatches if the object doesn't use floating point or is
14331 floating point ABI independent. */
14332 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14333 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14334 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 14335 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 14336 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14337 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 14338 {
14339 _bfd_error_handler
871b3ab2 14340 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 14341 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14342 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 14343 result = FALSE;
ee065d83
PB		 14344 }
14345 }
14346
3de4a297 14347 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 14348 {
14349 /* Merge this attribute with existing attributes. */
14350 switch (i)
14351 {
14352 case Tag_CPU_raw_name:
14353 case Tag_CPU_name:
6a631e86 14354 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 14355 break;
14356
14357 case Tag_ABI_optimization_goals:
14358 case Tag_ABI_FP_optimization_goals:
14359 /* Use the first value seen. */
14360 break;
14361
14362 case Tag_CPU_arch:
91e22acd
AS		 14363 {
14364 int secondary_compat = -1, secondary_compat_out = -1;
14365 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 14366 int arch_attr;
14367 static const char *name_table[] =
14368 {
91e22acd
AS		 14369 /* These aren't real CPU names, but we can't guess
14370 that from the architecture version alone. */
14371 "Pre v4",
14372 "ARM v4",
14373 "ARM v4T",
14374 "ARM v5T",
14375 "ARM v5TE",
14376 "ARM v5TEJ",
14377 "ARM v6",
14378 "ARM v6KZ",
14379 "ARM v6T2",
14380 "ARM v6K",
14381 "ARM v7",
14382 "ARM v6-M",
bca38921 14383 "ARM v6S-M",
2fd158eb
TP		 14384 "ARM v8",
14385 "",
14386 "ARM v8-M.baseline",
14387 "ARM v8-M.mainline",
91e22acd
AS		 14388 };
14389
14390 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14391 secondary_compat = get_secondary_compatible_arch (ibfd);
14392 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 14393 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14394 &secondary_compat_out,
14395 in_attr[i].i,
14396 secondary_compat);
14397
14398 /* Return with error if failed to merge. */
14399 if (arch_attr == -1)
14400 return FALSE;
14401
14402 out_attr[i].i = arch_attr;
14403
91e22acd
AS		 14404 set_secondary_compatible_arch (obfd, secondary_compat_out);
14405
14406 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14407 if (out_attr[i].i == saved_out_attr)
14408 ; /* Leave the names alone. */
14409 else if (out_attr[i].i == in_attr[i].i)
14410 {
14411 /* The output architecture has been changed to match the
14412 input architecture. Use the input names. */
14413 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14414 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14415 : NULL;
14416 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14417 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14418 : NULL;
14419 }
14420 else
14421 {
14422 out_attr[Tag_CPU_name].s = NULL;
14423 out_attr[Tag_CPU_raw_name].s = NULL;
14424 }
14425
14426 /* If we still don't have a value for Tag_CPU_name,
14427 make one up now. Tag_CPU_raw_name remains blank. */
14428 if (out_attr[Tag_CPU_name].s == NULL
14429 && out_attr[i].i < ARRAY_SIZE (name_table))
14430 out_attr[Tag_CPU_name].s =
14431 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14432 }
14433 break;
14434
ee065d83
PB		 14435 case Tag_ARM_ISA_use:
14436 case Tag_THUMB_ISA_use:
ee065d83 14437 case Tag_WMMX_arch:
91e22acd
AS		 14438 case Tag_Advanced_SIMD_arch:
14439 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 14440 case Tag_ABI_FP_rounding:
ee065d83
PB		 14441 case Tag_ABI_FP_exceptions:
14442 case Tag_ABI_FP_user_exceptions:
14443 case Tag_ABI_FP_number_model:
75375b3e 14444 case Tag_FP_HP_extension:
91e22acd
AS		 14445 case Tag_CPU_unaligned_access:
14446 case Tag_T2EE_use:
91e22acd 14447 case Tag_MPextension_use:
ee065d83
PB		 14448 /* Use the largest value specified. */
14449 if (in_attr[i].i > out_attr[i].i)
14450 out_attr[i].i = in_attr[i].i;
14451 break;
14452
75375b3e 14453 case Tag_ABI_align_preserved:
91e22acd
AS		 14454 case Tag_ABI_PCS_RO_data:
14455 /* Use the smallest value specified. */
14456 if (in_attr[i].i < out_attr[i].i)
14457 out_attr[i].i = in_attr[i].i;
14458 break;
14459
75375b3e 14460 case Tag_ABI_align_needed:
91e22acd 14461 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 14462 && (in_attr[Tag_ABI_align_preserved].i == 0
14463 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 14464 {
91e22acd
AS		 14465 /* This error message should be enabled once all non-conformant
14466 binaries in the toolchain have had the attributes set
14467 properly.
ee065d83 14468 _bfd_error_handler
871b3ab2 14469 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 14470 obfd, ibfd);
14471 result = FALSE; */
ee065d83 14472 }
91e22acd
AS		 14473 /* Fall through. */
14474 case Tag_ABI_FP_denormal:
14475 case Tag_ABI_PCS_GOT_use:
14476 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14477 value if greater than 2 (for future-proofing). */
14478 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14479 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14480 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 14481 out_attr[i].i = in_attr[i].i;
14482 break;
91e22acd 14483
75375b3e
MGD		 14484 case Tag_Virtualization_use:
14485 /* The virtualization tag effectively stores two bits of
14486 information: the intended use of TrustZone (in bit 0), and the
14487 intended use of Virtualization (in bit 1). */
14488 if (out_attr[i].i == 0)
14489 out_attr[i].i = in_attr[i].i;
14490 else if (in_attr[i].i != 0
14491 && in_attr[i].i != out_attr[i].i)
14492 {
14493 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14494 out_attr[i].i = 3;
14495 else
14496 {
14497 _bfd_error_handler
871b3ab2
AM		 14498 (_("error: %pB: unable to merge virtualization attributes "
14499 "with %pB"),
75375b3e
MGD		 14500 obfd, ibfd);
14501 result = FALSE;
14502 }
14503 }
14504 break;
91e22acd
AS		 14505
14506 case Tag_CPU_arch_profile:
14507 if (out_attr[i].i != in_attr[i].i)
14508 {
14509 /* 0 will merge with anything.
14510 'A' and 'S' merge to 'A'.
14511 'R' and 'S' merge to 'R'.
99059e56 14512 'M' and 'A|R|S' is an error. */
91e22acd
AS		 14513 if (out_attr[i].i == 0
14514 || (out_attr[i].i == 'S'
14515 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14516 out_attr[i].i = in_attr[i].i;
14517 else if (in_attr[i].i == 0
14518 || (in_attr[i].i == 'S'
14519 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 14520 ; /* Do nothing. */
91e22acd
AS		 14521 else
14522 {
14523 _bfd_error_handler
90b6238f 14524 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 14525 ibfd,
14526 in_attr[i].i ? in_attr[i].i : '0',
14527 out_attr[i].i ? out_attr[i].i : '0');
14528 result = FALSE;
14529 }
14530 }
14531 break;
15afaa63
TP		 14532
14533 case Tag_DSP_extension:
14534 /* No need to change output value if any of:
14535 - pre (<=) ARMv5T input architecture (do not have DSP)
14536 - M input profile not ARMv7E-M and do not have DSP. */
14537 if (in_attr[Tag_CPU_arch].i <= 3
14538 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14539 && in_attr[Tag_CPU_arch].i != 13
14540 && in_attr[i].i == 0))
14541 ; /* Do nothing. */
14542 /* Output value should be 0 if DSP part of architecture, ie.
14543 - post (>=) ARMv5te architecture output
14544 - A, R or S profile output or ARMv7E-M output architecture. */
14545 else if (out_attr[Tag_CPU_arch].i >= 4
14546 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14547 || out_attr[Tag_CPU_arch_profile].i == 'R'
14548 || out_attr[Tag_CPU_arch_profile].i == 'S'
14549 || out_attr[Tag_CPU_arch].i == 13))
14550 out_attr[i].i = 0;
14551 /* Otherwise, DSP instructions are added and not part of output
14552 architecture. */
14553 else
14554 out_attr[i].i = 1;
14555 break;
14556
75375b3e 14557 case Tag_FP_arch:
62f3b8c8 14558 {
4547cb56
NC		 14559 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14560 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14561 when it's 0. It might mean absence of FP hardware if
99654aaf 14562 Tag_FP_arch is zero. */
4547cb56 14563
a715796b 14564#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 14565 static const struct
14566 {
14567 int ver;
14568 int regs;
bca38921 14569 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 14570 {
14571 {0, 0},
14572 {1, 16},
14573 {2, 16},
14574 {3, 32},
14575 {3, 16},
14576 {4, 32},
bca38921 14577 {4, 16},
a715796b
TG		 14578 {8, 32},
14579 {8, 16}
62f3b8c8
PB		 14580 };
14581 int ver;
14582 int regs;
14583 int newval;
14584
4547cb56
NC		 14585 /* If the output has no requirement about FP hardware,
14586 follow the requirement of the input. */
14587 if (out_attr[i].i == 0)
14588 {
4ec192e6
RE		 14589 /* This assert is still reasonable, we shouldn't
14590 produce the suspicious build attribute
14591 combination (See below for in_attr). */
4547cb56
NC		 14592 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14593 out_attr[i].i = in_attr[i].i;
14594 out_attr[Tag_ABI_HardFP_use].i
14595 = in_attr[Tag_ABI_HardFP_use].i;
14596 break;
14597 }
14598 /* If the input has no requirement about FP hardware, do
14599 nothing. */
14600 else if (in_attr[i].i == 0)
14601 {
4ec192e6
RE		 14602 /* We used to assert that Tag_ABI_HardFP_use was
14603 zero here, but we should never assert when
14604 consuming an object file that has suspicious
14605 build attributes. The single precision variant
14606 of 'no FP architecture' is still 'no FP
14607 architecture', so we just ignore the tag in this
14608 case. */
4547cb56
NC		 14609 break;
14610 }
14611
14612 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 14613 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 14614
14615 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14616 do nothing. */
14617 if (in_attr[Tag_ABI_HardFP_use].i == 0
14618 && out_attr[Tag_ABI_HardFP_use].i == 0)
14619 ;
14620 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 14621 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 14622 else if (in_attr[Tag_ABI_HardFP_use].i
14623 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 14624 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 14625
14626 /* Now we can handle Tag_FP_arch. */
14627
bca38921
MGD		 14628 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14629 pick the biggest. */
14630 if (in_attr[i].i >= VFP_VERSION_COUNT
14631 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 14632 {
14633 out_attr[i] = in_attr[i];
14634 break;
14635 }
14636 /* The output uses the superset of input features
14637 (ISA version) and registers. */
14638 ver = vfp_versions[in_attr[i].i].ver;
14639 if (ver < vfp_versions[out_attr[i].i].ver)
14640 ver = vfp_versions[out_attr[i].i].ver;
14641 regs = vfp_versions[in_attr[i].i].regs;
14642 if (regs < vfp_versions[out_attr[i].i].regs)
14643 regs = vfp_versions[out_attr[i].i].regs;
14644 /* This assumes all possible supersets are also a valid
99059e56 14645 options. */
bca38921 14646 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 14647 {
14648 if (regs == vfp_versions[newval].regs
14649 && ver == vfp_versions[newval].ver)
14650 break;
14651 }
14652 out_attr[i].i = newval;
14653 }
b1cc4aeb 14654 break;
ee065d83
PB		 14655 case Tag_PCS_config:
14656 if (out_attr[i].i == 0)
14657 out_attr[i].i = in_attr[i].i;
b6009aca 14658 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14659 {
14660 /* It's sometimes ok to mix different configs, so this is only
99059e56 14661 a warning. */
ee065d83 14662 _bfd_error_handler
90b6238f 14663 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14664 }
14665 break;
14666 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14667 if (in_attr[i].i != out_attr[i].i
14668 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14669 && in_attr[i].i != AEABI_R9_unused)
14670 {
14671 _bfd_error_handler
90b6238f 14672 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14673 result = FALSE;
ee065d83
PB		 14674 }
14675 if (out_attr[i].i == AEABI_R9_unused)
14676 out_attr[i].i = in_attr[i].i;
14677 break;
14678 case Tag_ABI_PCS_RW_data:
14679 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14680 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14681 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14682 {
14683 _bfd_error_handler
871b3ab2 14684 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14685 ibfd);
91e22acd 14686 result = FALSE;
ee065d83
PB		 14687 }
14688 /* Use the smallest value specified. */
14689 if (in_attr[i].i < out_attr[i].i)
14690 out_attr[i].i = in_attr[i].i;
14691 break;
ee065d83 14692 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14693 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14694 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14695 {
14696 _bfd_error_handler
871b3ab2 14697 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14698 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14699 }
a9dc9481 14700 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14701 out_attr[i].i = in_attr[i].i;
14702 break;
ee065d83
PB		 14703 case Tag_ABI_enum_size:
14704 if (in_attr[i].i != AEABI_enum_unused)
14705 {
14706 if (out_attr[i].i == AEABI_enum_unused
14707 || out_attr[i].i == AEABI_enum_forced_wide)
14708 {
14709 /* The existing object is compatible with anything.
14710 Use whatever requirements the new object has. */
14711 out_attr[i].i = in_attr[i].i;
14712 }
14713 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14714 && out_attr[i].i != in_attr[i].i
0ffa91dd 14715 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14716 {
91e22acd 14717 static const char *aeabi_enum_names[] =
bf21ed78 14718 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14719 const char *in_name =
14720 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14721 ? aeabi_enum_names[in_attr[i].i]
14722 : "<unknown>";
14723 const char *out_name =
14724 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14725 ? aeabi_enum_names[out_attr[i].i]
14726 : "<unknown>";
ee065d83 14727 _bfd_error_handler
871b3ab2 14728 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14729 ibfd, in_name, out_name);
ee065d83
PB		 14730 }
14731 }
14732 break;
14733 case Tag_ABI_VFP_args:
14734 /* Aready done. */
14735 break;
14736 case Tag_ABI_WMMX_args:
14737 if (in_attr[i].i != out_attr[i].i)
14738 {
14739 _bfd_error_handler
871b3ab2 14740 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14741 ibfd, obfd);
91e22acd 14742 result = FALSE;
ee065d83
PB		 14743 }
14744 break;
7b86a9fa
AS		 14745 case Tag_compatibility:
14746 /* Merged in target-independent code. */
14747 break;
91e22acd 14748 case Tag_ABI_HardFP_use:
4547cb56 14749 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14750 break;
14751 case Tag_ABI_FP_16bit_format:
14752 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14753 {
14754 if (in_attr[i].i != out_attr[i].i)
14755 {
14756 _bfd_error_handler
871b3ab2 14757 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 14758 ibfd, obfd);
14759 result = FALSE;
14760 }
14761 }
14762 if (in_attr[i].i != 0)
14763 out_attr[i].i = in_attr[i].i;
14764 break;
7b86a9fa 14765
cd21e546 14766 case Tag_DIV_use:
ac56ee8f
MGD		 14767 /* A value of zero on input means that the divide instruction may
14768 be used if available in the base architecture as specified via
14769 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14770 the user did not want divide instructions. A value of 2
14771 explicitly means that divide instructions were allowed in ARM
14772 and Thumb state. */
14773 if (in_attr[i].i == out_attr[i].i)
14774 /* Do nothing. */ ;
14775 else if (elf32_arm_attributes_forbid_div (in_attr)
14776 && !elf32_arm_attributes_accept_div (out_attr))
14777 out_attr[i].i = 1;
14778 else if (elf32_arm_attributes_forbid_div (out_attr)
14779 && elf32_arm_attributes_accept_div (in_attr))
14780 out_attr[i].i = in_attr[i].i;
14781 else if (in_attr[i].i == 2)
14782 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14783 break;
14784
14785 case Tag_MPextension_use_legacy:
14786 /* We don't output objects with Tag_MPextension_use_legacy - we
14787 move the value to Tag_MPextension_use. */
14788 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14789 {
14790 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14791 {
14792 _bfd_error_handler
871b3ab2 14793 (_("%pB has both the current and legacy "
b38cadfb 14794 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14795 ibfd);
14796 result = FALSE;
14797 }
14798 }
14799
14800 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14801 out_attr[Tag_MPextension_use] = in_attr[i];
14802
14803 break;
14804
91e22acd 14805 case Tag_nodefaults:
2d0bb761
AS		 14806 /* This tag is set if it exists, but the value is unused (and is
14807 typically zero). We don't actually need to do anything here -
14808 the merge happens automatically when the type flags are merged
14809 below. */
91e22acd
AS		 14810 break;
14811 case Tag_also_compatible_with:
14812 /* Already done in Tag_CPU_arch. */
14813 break;
14814 case Tag_conformance:
14815 /* Keep the attribute if it matches. Throw it away otherwise.
14816 No attribute means no claim to conform. */
14817 if (!in_attr[i].s || !out_attr[i].s
14818 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
14819 out_attr[i].s = NULL;
14820 break;
3cfad14c 14821
91e22acd 14822 default:
e8b36cd1
JM		 14823 result
14824 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 14825 }
14826
14827 /* If out_attr was copied from in_attr then it won't have a type yet. */
14828 if (in_attr[i].type && !out_attr[i].type)
14829 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 14830 }
14831
104d59d1 14832 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 14833 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 14834 return FALSE;
ee065d83 14835
104d59d1 14836 /* Check for any attributes not known on ARM. */
e8b36cd1 14837 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 14838
91e22acd 14839 return result;
252b5132
RH		 14840}
14841
3a4a14e9
PB		 14842
14843/* Return TRUE if the two EABI versions are incompatible. */
14844
14845static bfd_boolean
14846elf32_arm_versions_compatible (unsigned iver, unsigned over)
14847{
14848 /* v4 and v5 are the same spec before and after it was released,
14849 so allow mixing them. */
14850 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
14851 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
14852 return TRUE;
14853
14854 return (iver == over);
14855}
14856
252b5132
RH		 14857/* Merge backend specific data from an object file to the output
14858 object file when linking. */
9b485d32 14859
b34976b6 14860static bfd_boolean
50e03d47 14861elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 14862
9b485d32
NC		 14863/* Display the flags field. */
14864
b34976b6 14865static bfd_boolean
57e8b36a 14866elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 14867{
fc830a83
NC		 14868 FILE * file = (FILE *) ptr;
14869 unsigned long flags;
252b5132
RH		 14870
14871 BFD_ASSERT (abfd != NULL && ptr != NULL);
14872
14873 /* Print normal ELF private data. */
14874 _bfd_elf_print_private_bfd_data (abfd, ptr);
14875
fc830a83 14876 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 14877 /* Ignore init flag - it may not be set, despite the flags field
14878 containing valid data. */
252b5132 14879
9b485d32 14880 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 14881
fc830a83
NC		 14882 switch (EF_ARM_EABI_VERSION (flags))
14883 {
14884 case EF_ARM_EABI_UNKNOWN:
4cc11e76 14885 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 14886 official ARM ELF extended ABI. Hence they are only decoded if
14887 the EABI version is not set. */
fd2ec330 14888 if (flags & EF_ARM_INTERWORK)
9b485d32 14889 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 14890
fd2ec330 14891 if (flags & EF_ARM_APCS_26)
6c571f00 14892 fprintf (file, " [APCS-26]");
fc830a83 14893 else
6c571f00 14894 fprintf (file, " [APCS-32]");
9a5aca8c 14895
96a846ea
RE		 14896 if (flags & EF_ARM_VFP_FLOAT)
14897 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 14898 else if (flags & EF_ARM_MAVERICK_FLOAT)
14899 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 14900 else
14901 fprintf (file, _(" [FPA float format]"));
14902
fd2ec330 14903 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 14904 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 14905
fd2ec330 14906 if (flags & EF_ARM_PIC)
9b485d32 14907 fprintf (file, _(" [position independent]"));
fc830a83 14908
fd2ec330 14909 if (flags & EF_ARM_NEW_ABI)
9b485d32 14910 fprintf (file, _(" [new ABI]"));
9a5aca8c 14911
fd2ec330 14912 if (flags & EF_ARM_OLD_ABI)
9b485d32 14913 fprintf (file, _(" [old ABI]"));
9a5aca8c 14914
fd2ec330 14915 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 14916 fprintf (file, _(" [software FP]"));
9a5aca8c 14917
96a846ea
RE		 14918 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
14919 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 14920 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
14921 | EF_ARM_MAVERICK_FLOAT);
fc830a83 14922 break;
9a5aca8c 14923
fc830a83 14924 case EF_ARM_EABI_VER1:
9b485d32 14925 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 14926
fc830a83 14927 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 14928 fprintf (file, _(" [sorted symbol table]"));
fc830a83 14929 else
9b485d32 14930 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 14931
fc830a83
NC		 14932 flags &= ~ EF_ARM_SYMSARESORTED;
14933 break;
9a5aca8c 14934
fd2ec330
PB		 14935 case EF_ARM_EABI_VER2:
14936 fprintf (file, _(" [Version2 EABI]"));
14937
14938 if (flags & EF_ARM_SYMSARESORTED)
14939 fprintf (file, _(" [sorted symbol table]"));
14940 else
14941 fprintf (file, _(" [unsorted symbol table]"));
14942
14943 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
14944 fprintf (file, _(" [dynamic symbols use segment index]"));
14945
14946 if (flags & EF_ARM_MAPSYMSFIRST)
14947 fprintf (file, _(" [mapping symbols precede others]"));
14948
99e4ae17 14949 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 14950 | EF_ARM_MAPSYMSFIRST);
14951 break;
14952
d507cf36
PB		 14953 case EF_ARM_EABI_VER3:
14954 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 14955 break;
14956
14957 case EF_ARM_EABI_VER4:
14958 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 14959 goto eabi;
d507cf36 14960
3a4a14e9
PB		 14961 case EF_ARM_EABI_VER5:
14962 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 14963
14964 if (flags & EF_ARM_ABI_FLOAT_SOFT)
14965 fprintf (file, _(" [soft-float ABI]"));
14966
14967 if (flags & EF_ARM_ABI_FLOAT_HARD)
14968 fprintf (file, _(" [hard-float ABI]"));
14969
14970 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
14971
3a4a14e9 14972 eabi:
d507cf36
PB		 14973 if (flags & EF_ARM_BE8)
14974 fprintf (file, _(" [BE8]"));
14975
14976 if (flags & EF_ARM_LE8)
14977 fprintf (file, _(" [LE8]"));
14978
14979 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
14980 break;
14981
fc830a83 14982 default:
9b485d32 14983 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 14984 break;
14985 }
252b5132 14986
fc830a83 14987 flags &= ~ EF_ARM_EABIMASK;
252b5132 14988
fc830a83 14989 if (flags & EF_ARM_RELEXEC)
9b485d32 14990 fprintf (file, _(" [relocatable executable]"));
252b5132 14991
18a20338
CL		 14992 if (flags & EF_ARM_PIC)
14993 fprintf (file, _(" [position independent]"));
14994
14995 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
14996 fprintf (file, _(" [FDPIC ABI supplement]"));
14997
14998 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 14999
15000 if (flags)
9b485d32 15001 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 15002
252b5132
RH		 15003 fputc ('\n', file);
15004
b34976b6 15005 return TRUE;
252b5132
RH		 15006}
15007
15008static int
57e8b36a 15009elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 15010{
2f0ca46a
NC		 15011 switch (ELF_ST_TYPE (elf_sym->st_info))
15012 {
15013 case STT_ARM_TFUNC:
15014 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 15015
2f0ca46a
NC		 15016 case STT_ARM_16BIT:
15017 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15018 This allows us to distinguish between data used by Thumb instructions
15019 and non-data (which is probably code) inside Thumb regions of an
15020 executable. */
1a0eb693 15021 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 15022 return ELF_ST_TYPE (elf_sym->st_info);
15023 break;
9a5aca8c 15024
ce855c42
NC		 15025 default:
15026 break;
2f0ca46a
NC		 15027 }
15028
15029 return type;
252b5132 15030}
f21f3fe0 15031
252b5132 15032static asection *
07adf181
AM		 15033elf32_arm_gc_mark_hook (asection *sec,
15034 struct bfd_link_info *info,
15035 Elf_Internal_Rela *rel,
15036 struct elf_link_hash_entry *h,
15037 Elf_Internal_Sym *sym)
252b5132
RH		 15038{
15039 if (h != NULL)
07adf181 15040 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 15041 {
15042 case R_ARM_GNU_VTINHERIT:
15043 case R_ARM_GNU_VTENTRY:
07adf181
AM		 15044 return NULL;
15045 }
9ad5cbcf 15046
07adf181 15047 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 15048}
15049
780a67af
NC		 15050/* Look through the relocs for a section during the first phase. */
15051
b34976b6 15052static bfd_boolean
57e8b36a
NC		 15053elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
15054 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 15055{
b34976b6
AM		 15056 Elf_Internal_Shdr *symtab_hdr;
15057 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 15058 const Elf_Internal_Rela *rel;
15059 const Elf_Internal_Rela *rel_end;
15060 bfd *dynobj;
5e681ec4 15061 asection *sreloc;
5e681ec4 15062 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 15063 bfd_boolean call_reloc_p;
15064 bfd_boolean may_become_dynamic_p;
15065 bfd_boolean may_need_local_target_p;
ce98a316 15066 unsigned long nsyms;
9a5aca8c 15067
0e1862bb 15068 if (bfd_link_relocatable (info))
b34976b6 15069 return TRUE;
9a5aca8c 15070
0ffa91dd
NC		 15071 BFD_ASSERT (is_arm_elf (abfd));
15072
5e681ec4 15073 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15074 if (htab == NULL)
15075 return FALSE;
15076
5e681ec4 15077 sreloc = NULL;
9a5aca8c 15078
67687978
PB		 15079 /* Create dynamic sections for relocatable executables so that we can
15080 copy relocations. */
15081 if (htab->root.is_relocatable_executable
15082 && ! htab->root.dynamic_sections_created)
15083 {
15084 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15085 return FALSE;
15086 }
15087
cbc704f3
RS		 15088 if (htab->root.dynobj == NULL)
15089 htab->root.dynobj = abfd;
34e77a92
RS		 15090 if (!create_ifunc_sections (info))
15091 return FALSE;
cbc704f3
RS		 15092
15093 dynobj = htab->root.dynobj;
15094
0ffa91dd 15095 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 15096 sym_hashes = elf_sym_hashes (abfd);
ce98a316 15097 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 15098
252b5132
RH		 15099 rel_end = relocs + sec->reloc_count;
15100 for (rel = relocs; rel < rel_end; rel++)
15101 {
34e77a92 15102 Elf_Internal_Sym *isym;
252b5132 15103 struct elf_link_hash_entry *h;
b7693d02 15104 struct elf32_arm_link_hash_entry *eh;
d42c267e 15105 unsigned int r_symndx;
eb043451 15106 int r_type;
9a5aca8c 15107
252b5132 15108 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 15109 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 15110 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 15111
ce98a316
NC		 15112 if (r_symndx >= nsyms
15113 /* PR 9934: It is possible to have relocations that do not
15114 refer to symbols, thus it is also possible to have an
15115 object file containing relocations but no symbol table. */
cf35638d 15116 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 15117 {
871b3ab2 15118 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 15119 r_symndx);
ba93b8ac
DJ		 15120 return FALSE;
15121 }
15122
34e77a92
RS		 15123 h = NULL;
15124 isym = NULL;
15125 if (nsyms > 0)
973a3492 15126 {
34e77a92
RS		 15127 if (r_symndx < symtab_hdr->sh_info)
15128 {
15129 /* A local symbol. */
15130 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
15131 abfd, r_symndx);
15132 if (isym == NULL)
15133 return FALSE;
15134 }
15135 else
15136 {
15137 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15138 while (h->root.type == bfd_link_hash_indirect
15139 || h->root.type == bfd_link_hash_warning)
15140 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15141 }
973a3492 15142 }
9a5aca8c 15143
b7693d02
DJ		 15144 eh = (struct elf32_arm_link_hash_entry *) h;
15145
f6e32f6d
RS		 15146 call_reloc_p = FALSE;
15147 may_become_dynamic_p = FALSE;
15148 may_need_local_target_p = FALSE;
15149
0855e32b
NS		 15150 /* Could be done earlier, if h were already available. */
15151 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 15152 switch (r_type)
99059e56 15153 {
e8b09b87
CL		 15154 case R_ARM_GOTOFFFUNCDESC:
15155 {
15156 if (h == NULL)
15157 {
15158 if (!elf32_arm_allocate_local_sym_info (abfd))
15159 return FALSE;
15160 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].gotofffuncdesc_cnt += 1;
15161 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15162 }
15163 else
15164 {
15165 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15166 }
15167 }
15168 break;
15169
15170 case R_ARM_GOTFUNCDESC:
15171 {
15172 if (h == NULL)
15173 {
15174 /* Such a relocation is not supposed to be generated
15175 by gcc on a static function. */
15176 /* Anyway if needed it could be handled. */
15177 abort();
15178 }
15179 else
15180 {
15181 eh->fdpic_cnts.gotfuncdesc_cnt++;
15182 }
15183 }
15184 break;
15185
15186 case R_ARM_FUNCDESC:
15187 {
15188 if (h == NULL)
15189 {
15190 if (!elf32_arm_allocate_local_sym_info (abfd))
15191 return FALSE;
15192 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_cnt += 1;
15193 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15194 }
15195 else
15196 {
15197 eh->fdpic_cnts.funcdesc_cnt++;
15198 }
15199 }
15200 break;
15201
5e681ec4 15202 case R_ARM_GOT32:
eb043451 15203 case R_ARM_GOT_PREL:
ba93b8ac 15204 case R_ARM_TLS_GD32:
5c5a4843 15205 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 15206 case R_ARM_TLS_IE32:
5c5a4843 15207 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 15208 case R_ARM_TLS_GOTDESC:
15209 case R_ARM_TLS_DESCSEQ:
15210 case R_ARM_THM_TLS_DESCSEQ:
15211 case R_ARM_TLS_CALL:
15212 case R_ARM_THM_TLS_CALL:
5e681ec4 15213 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 15214 {
15215 int tls_type, old_tls_type;
5e681ec4 15216
ba93b8ac
DJ		 15217 switch (r_type)
15218 {
15219 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
5c5a4843 15220 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
b38cadfb 15221
ba93b8ac 15222 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
5c5a4843 15223 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
b38cadfb 15224
0855e32b
NS		 15225 case R_ARM_TLS_GOTDESC:
15226 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15227 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15228 tls_type = GOT_TLS_GDESC; break;
b38cadfb 15229
ba93b8ac
DJ		 15230 default: tls_type = GOT_NORMAL; break;
15231 }
252b5132 15232
0e1862bb 15233 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 15234 info->flags |= DF_STATIC_TLS;
15235
ba93b8ac
DJ		 15236 if (h != NULL)
15237 {
15238 h->got.refcount++;
15239 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15240 }
15241 else
15242 {
ba93b8ac 15243 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 15244 if (!elf32_arm_allocate_local_sym_info (abfd))
15245 return FALSE;
15246 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 15247 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15248 }
15249
0855e32b 15250 /* If a variable is accessed with both tls methods, two
99059e56 15251 slots may be created. */
0855e32b
NS		 15252 if (GOT_TLS_GD_ANY_P (old_tls_type)
15253 && GOT_TLS_GD_ANY_P (tls_type))
15254 tls_type |= old_tls_type;
15255
15256 /* We will already have issued an error message if there
15257 is a TLS/non-TLS mismatch, based on the symbol
15258 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 15259 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15260 && tls_type != GOT_NORMAL)
15261 tls_type |= old_tls_type;
15262
0855e32b 15263 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 15264 method, we're able to relax. Turn off the GDESC flag,
15265 without messing up with any other kind of tls types
6a631e86 15266 that may be involved. */
0855e32b
NS		 15267 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15268 tls_type &= ~GOT_TLS_GDESC;
15269
ba93b8ac
DJ		 15270 if (old_tls_type != tls_type)
15271 {
15272 if (h != NULL)
15273 elf32_arm_hash_entry (h)->tls_type = tls_type;
15274 else
15275 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15276 }
15277 }
8029a119 15278 /* Fall through. */
ba93b8ac
DJ		 15279
15280 case R_ARM_TLS_LDM32:
5c5a4843
CL		 15281 case R_ARM_TLS_LDM32_FDPIC:
15282 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
ba93b8ac 15283 htab->tls_ldm_got.refcount++;
8029a119 15284 /* Fall through. */
252b5132 15285
c19d1205 15286 case R_ARM_GOTOFF32:
5e681ec4 15287 case R_ARM_GOTPC:
cbc704f3
RS		 15288 if (htab->root.sgot == NULL
15289 && !create_got_section (htab->root.dynobj, info))
15290 return FALSE;
252b5132
RH		 15291 break;
15292
252b5132 15293 case R_ARM_PC24:
7359ea65 15294 case R_ARM_PLT32:
5b5bb741
PB		 15295 case R_ARM_CALL:
15296 case R_ARM_JUMP24:
eb043451 15297 case R_ARM_PREL31:
c19d1205 15298 case R_ARM_THM_CALL:
bd97cb95
DJ		 15299 case R_ARM_THM_JUMP24:
15300 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 15301 call_reloc_p = TRUE;
15302 may_need_local_target_p = TRUE;
15303 break;
15304
15305 case R_ARM_ABS12:
15306 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15307 ldr __GOTT_INDEX__ offsets. */
15308 if (!htab->vxworks_p)
15309 {
15310 may_need_local_target_p = TRUE;
15311 break;
15312 }
aebf9be7 15313 else goto jump_over;
9eaff861 15314
f6e32f6d 15315 /* Fall through. */
39623e12 15316
96c23d59
JM		 15317 case R_ARM_MOVW_ABS_NC:
15318 case R_ARM_MOVT_ABS:
15319 case R_ARM_THM_MOVW_ABS_NC:
15320 case R_ARM_THM_MOVT_ABS:
0e1862bb 15321 if (bfd_link_pic (info))
96c23d59 15322 {
4eca0228 15323 _bfd_error_handler
871b3ab2 15324 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 15325 abfd, elf32_arm_howto_table_1[r_type].name,
15326 (h) ? h->root.root.string : "a local symbol");
15327 bfd_set_error (bfd_error_bad_value);
15328 return FALSE;
15329 }
15330
15331 /* Fall through. */
39623e12
PB		 15332 case R_ARM_ABS32:
15333 case R_ARM_ABS32_NOI:
aebf9be7 15334 jump_over:
0e1862bb 15335 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 15336 {
15337 h->pointer_equality_needed = 1;
15338 }
15339 /* Fall through. */
39623e12
PB		 15340 case R_ARM_REL32:
15341 case R_ARM_REL32_NOI:
b6895b4f
PB		 15342 case R_ARM_MOVW_PREL_NC:
15343 case R_ARM_MOVT_PREL:
b6895b4f
PB		 15344 case R_ARM_THM_MOVW_PREL_NC:
15345 case R_ARM_THM_MOVT_PREL:
39623e12 15346
b7693d02 15347 /* Should the interworking branches be listed here? */
e8b09b87
CL		 15348 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15349 || htab->fdpic_p)
34e77a92
RS		 15350 && (sec->flags & SEC_ALLOC) != 0)
15351 {
15352 if (h == NULL
469a3493 15353 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 15354 {
15355 /* In shared libraries and relocatable executables,
15356 we treat local relative references as calls;
15357 see the related SYMBOL_CALLS_LOCAL code in
15358 allocate_dynrelocs. */
15359 call_reloc_p = TRUE;
15360 may_need_local_target_p = TRUE;
15361 }
15362 else
15363 /* We are creating a shared library or relocatable
15364 executable, and this is a reloc against a global symbol,
15365 or a non-PC-relative reloc against a local symbol.
15366 We may need to copy the reloc into the output. */
15367 may_become_dynamic_p = TRUE;
15368 }
f6e32f6d
RS		 15369 else
15370 may_need_local_target_p = TRUE;
252b5132
RH		 15371 break;
15372
99059e56
RM		 15373 /* This relocation describes the C++ object vtable hierarchy.
15374 Reconstruct it for later use during GC. */
15375 case R_ARM_GNU_VTINHERIT:
15376 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15377 return FALSE;
15378 break;
15379
15380 /* This relocation describes which C++ vtable entries are actually
15381 used. Record for later use during GC. */
15382 case R_ARM_GNU_VTENTRY:
a0ea3a14 15383 if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
99059e56
RM		 15384 return FALSE;
15385 break;
15386 }
f6e32f6d
RS		 15387
15388 if (h != NULL)
15389 {
15390 if (call_reloc_p)
15391 /* We may need a .plt entry if the function this reloc
15392 refers to is in a different object, regardless of the
15393 symbol's type. We can't tell for sure yet, because
15394 something later might force the symbol local. */
15395 h->needs_plt = 1;
15396 else if (may_need_local_target_p)
15397 /* If this reloc is in a read-only section, we might
15398 need a copy reloc. We can't check reliably at this
15399 stage whether the section is read-only, as input
15400 sections have not yet been mapped to output sections.
15401 Tentatively set the flag for now, and correct in
15402 adjust_dynamic_symbol. */
15403 h->non_got_ref = 1;
15404 }
15405
34e77a92
RS		 15406 if (may_need_local_target_p
15407 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 15408 {
34e77a92
RS		 15409 union gotplt_union *root_plt;
15410 struct arm_plt_info *arm_plt;
15411 struct arm_local_iplt_info *local_iplt;
15412
15413 if (h != NULL)
15414 {
15415 root_plt = &h->plt;
15416 arm_plt = &eh->plt;
15417 }
15418 else
15419 {
15420 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15421 if (local_iplt == NULL)
15422 return FALSE;
15423 root_plt = &local_iplt->root;
15424 arm_plt = &local_iplt->arm;
15425 }
15426
f6e32f6d
RS		 15427 /* If the symbol is a function that doesn't bind locally,
15428 this relocation will need a PLT entry. */
a8c887dd
NC		 15429 if (root_plt->refcount != -1)
15430 root_plt->refcount += 1;
34e77a92
RS		 15431
15432 if (!call_reloc_p)
15433 arm_plt->noncall_refcount++;
f6e32f6d
RS		 15434
15435 /* It's too early to use htab->use_blx here, so we have to
15436 record possible blx references separately from
15437 relocs that definitely need a thumb stub. */
15438
15439 if (r_type == R_ARM_THM_CALL)
34e77a92 15440 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 15441
15442 if (r_type == R_ARM_THM_JUMP24
15443 || r_type == R_ARM_THM_JUMP19)
34e77a92 15444 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 15445 }
15446
15447 if (may_become_dynamic_p)
15448 {
15449 struct elf_dyn_relocs *p, **head;
15450
15451 /* Create a reloc section in dynobj. */
15452 if (sreloc == NULL)
15453 {
15454 sreloc = _bfd_elf_make_dynamic_reloc_section
15455 (sec, dynobj, 2, abfd, ! htab->use_rel);
15456
15457 if (sreloc == NULL)
15458 return FALSE;
15459
15460 /* BPABI objects never have dynamic relocations mapped. */
15461 if (htab->symbian_p)
15462 {
15463 flagword flags;
15464
15465 flags = bfd_get_section_flags (dynobj, sreloc);
15466 flags &= ~(SEC_LOAD | SEC_ALLOC);
15467 bfd_set_section_flags (dynobj, sreloc, flags);
15468 }
15469 }
15470
15471 /* If this is a global symbol, count the number of
15472 relocations we need for this symbol. */
15473 if (h != NULL)
15474 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
15475 else
15476 {
34e77a92
RS		 15477 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15478 if (head == NULL)
f6e32f6d 15479 return FALSE;
f6e32f6d
RS		 15480 }
15481
15482 p = *head;
15483 if (p == NULL || p->sec != sec)
15484 {
15485 bfd_size_type amt = sizeof *p;
15486
15487 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15488 if (p == NULL)
15489 return FALSE;
15490 p->next = *head;
15491 *head = p;
15492 p->sec = sec;
15493 p->count = 0;
15494 p->pc_count = 0;
15495 }
15496
469a3493 15497 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 15498 p->pc_count += 1;
15499 p->count += 1;
e8b09b87
CL		 15500 if (h == NULL && htab->fdpic_p && !bfd_link_pic(info)
15501 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI) {
15502 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15503 that will become rofixup. */
15504 /* This is due to the fact that we suppose all will become rofixup. */
15505 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15506 _bfd_error_handler
15507 (_("FDPIC does not yet support %s relocation"
15508 " to become dynamic for executable"),
15509 elf32_arm_howto_table_1[r_type].name);
15510 abort();
15511 }
f6e32f6d 15512 }
252b5132 15513 }
f21f3fe0 15514
b34976b6 15515 return TRUE;
252b5132
RH		 15516}
15517
9eaff861
AO		 15518static void
15519elf32_arm_update_relocs (asection *o,
15520 struct bfd_elf_section_reloc_data *reldata)
15521{
15522 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15523 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15524 const struct elf_backend_data *bed;
15525 _arm_elf_section_data *eado;
15526 struct bfd_link_order *p;
15527 bfd_byte *erela_head, *erela;
15528 Elf_Internal_Rela *irela_head, *irela;
15529 Elf_Internal_Shdr *rel_hdr;
15530 bfd *abfd;
15531 unsigned int count;
15532
15533 eado = get_arm_elf_section_data (o);
15534
15535 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15536 return;
15537
15538 abfd = o->owner;
15539 bed = get_elf_backend_data (abfd);
15540 rel_hdr = reldata->hdr;
15541
15542 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15543 {
15544 swap_in = bed->s->swap_reloc_in;
15545 swap_out = bed->s->swap_reloc_out;
15546 }
15547 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15548 {
15549 swap_in = bed->s->swap_reloca_in;
15550 swap_out = bed->s->swap_reloca_out;
15551 }
15552 else
15553 abort ();
15554
15555 erela_head = rel_hdr->contents;
15556 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15557 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15558
15559 erela = erela_head;
15560 irela = irela_head;
15561 count = 0;
15562
15563 for (p = o->map_head.link_order; p; p = p->next)
15564 {
15565 if (p->type == bfd_section_reloc_link_order
15566 || p->type == bfd_symbol_reloc_link_order)
15567 {
15568 (*swap_in) (abfd, erela, irela);
15569 erela += rel_hdr->sh_entsize;
15570 irela++;
15571 count++;
15572 }
15573 else if (p->type == bfd_indirect_link_order)
15574 {
15575 struct bfd_elf_section_reloc_data *input_reldata;
15576 arm_unwind_table_edit *edit_list, *edit_tail;
15577 _arm_elf_section_data *eadi;
15578 bfd_size_type j;
15579 bfd_vma offset;
15580 asection *i;
15581
15582 i = p->u.indirect.section;
15583
15584 eadi = get_arm_elf_section_data (i);
15585 edit_list = eadi->u.exidx.unwind_edit_list;
15586 edit_tail = eadi->u.exidx.unwind_edit_tail;
15587 offset = o->vma + i->output_offset;
15588
15589 if (eadi->elf.rel.hdr &&
15590 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15591 input_reldata = &eadi->elf.rel;
15592 else if (eadi->elf.rela.hdr &&
15593 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15594 input_reldata = &eadi->elf.rela;
15595 else
15596 abort ();
15597
15598 if (edit_list)
15599 {
15600 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15601 {
15602 arm_unwind_table_edit *edit_node, *edit_next;
15603 bfd_vma bias;
c48182bf 15604 bfd_vma reloc_index;
9eaff861
AO		 15605
15606 (*swap_in) (abfd, erela, irela);
c48182bf 15607 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 15608
15609 bias = 0;
15610 edit_node = edit_list;
15611 for (edit_next = edit_list;
c48182bf 15612 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 15613 edit_next = edit_node->next)
15614 {
15615 bias++;
15616 edit_node = edit_next;
15617 }
15618
15619 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 15620 || edit_node->index != reloc_index)
9eaff861
AO		 15621 {
15622 irela->r_offset -= bias * 8;
15623 irela++;
15624 count++;
15625 }
15626
15627 erela += rel_hdr->sh_entsize;
15628 }
15629
15630 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15631 {
15632 /* New relocation entity. */
15633 asection *text_sec = edit_tail->linked_section;
15634 asection *text_out = text_sec->output_section;
15635 bfd_vma exidx_offset = offset + i->size - 8;
15636
15637 irela->r_addend = 0;
15638 irela->r_offset = exidx_offset;
15639 irela->r_info = ELF32_R_INFO
15640 (text_out->target_index, R_ARM_PREL31);
15641 irela++;
15642 count++;
15643 }
15644 }
15645 else
15646 {
15647 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15648 {
15649 (*swap_in) (abfd, erela, irela);
15650 erela += rel_hdr->sh_entsize;
15651 irela++;
15652 }
15653
15654 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15655 }
15656 }
15657 }
15658
15659 reldata->count = count;
15660 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15661
15662 erela = erela_head;
15663 irela = irela_head;
15664 while (count > 0)
15665 {
15666 (*swap_out) (abfd, irela, erela);
15667 erela += rel_hdr->sh_entsize;
15668 irela++;
15669 count--;
15670 }
15671
15672 free (irela_head);
15673
15674 /* Hashes are no longer valid. */
15675 free (reldata->hashes);
15676 reldata->hashes = NULL;
15677}
15678
6a5bb875 15679/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15680 required if the corresponding code section is marked. Similarly, ARMv8-M
15681 secure entry functions can only be referenced by SG veneers which are
15682 created after the GC process. They need to be marked in case they reside in
15683 their own section (as would be the case if code was compiled with
15684 -ffunction-sections). */
6a5bb875
PB		 15685
15686static bfd_boolean
906e58ca
NC		 15687elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15688 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15689{
15690 bfd *sub;
15691 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15692 asection *cmse_sec;
15693 obj_attribute *out_attr;
15694 Elf_Internal_Shdr *symtab_hdr;
15695 unsigned i, sym_count, ext_start;
15696 const struct elf_backend_data *bed;
15697 struct elf_link_hash_entry **sym_hashes;
15698 struct elf32_arm_link_hash_entry *cmse_hash;
15699 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 15700
7f6ab9f8
AM		 15701 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15702
4ba2ef8f
TP		 15703 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15704 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15705 && out_attr[Tag_CPU_arch_profile].i == 'M';
15706
6a5bb875
PB		 15707 /* Marking EH data may cause additional code sections to be marked,
15708 requiring multiple passes. */
15709 again = TRUE;
15710 while (again)
15711 {
15712 again = FALSE;
c72f2fb2 15713 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15714 {
15715 asection *o;
15716
0ffa91dd 15717 if (! is_arm_elf (sub))
6a5bb875
PB		 15718 continue;
15719
15720 elf_shdrp = elf_elfsections (sub);
15721 for (o = sub->sections; o != NULL; o = o->next)
15722 {
15723 Elf_Internal_Shdr *hdr;
0ffa91dd 15724
6a5bb875 15725 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15726 if (hdr->sh_type == SHT_ARM_EXIDX
15727 && hdr->sh_link
15728 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15729 && !o->gc_mark
15730 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15731 {
15732 again = TRUE;
15733 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15734 return FALSE;
15735 }
15736 }
4ba2ef8f
TP		 15737
15738 /* Mark section holding ARMv8-M secure entry functions. We mark all
15739 of them so no need for a second browsing. */
15740 if (is_v8m && first_bfd_browse)
15741 {
15742 sym_hashes = elf_sym_hashes (sub);
15743 bed = get_elf_backend_data (sub);
15744 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15745 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15746 ext_start = symtab_hdr->sh_info;
15747
15748 /* Scan symbols. */
15749 for (i = ext_start; i < sym_count; i++)
15750 {
15751 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15752
15753 /* Assume it is a special symbol. If not, cmse_scan will
15754 warn about it and user can do something about it. */
15755 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
15756 {
15757 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15758 if (!cmse_sec->gc_mark
15759 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f
TP		 15760 return FALSE;
15761 }
15762 }
15763 }
6a5bb875 15764 }
4ba2ef8f 15765 first_bfd_browse = FALSE;
6a5bb875
PB		 15766 }
15767
15768 return TRUE;
15769}
15770
3c9458e9
NC		 15771/* Treat mapping symbols as special target symbols. */
15772
15773static bfd_boolean
15774elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
15775{
b0796911
PB		 15776 return bfd_is_arm_special_symbol_name (sym->name,
15777 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 15778}
15779
0367ecfb
NC		 15780/* This is a copy of elf_find_function() from elf.c except that
15781 ARM mapping symbols are ignored when looking for function names
15782 and STT_ARM_TFUNC is considered to a function type. */
252b5132 15783
0367ecfb 15784static bfd_boolean
07d6d2b8 15785arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 15786 asymbol ** symbols,
fb167eb2 15787 asection * section,
07d6d2b8 15788 bfd_vma offset,
0367ecfb
NC		 15789 const char ** filename_ptr,
15790 const char ** functionname_ptr)
15791{
15792 const char * filename = NULL;
15793 asymbol * func = NULL;
15794 bfd_vma low_func = 0;
15795 asymbol ** p;
252b5132
RH		 15796
15797 for (p = symbols; *p != NULL; p++)
15798 {
15799 elf_symbol_type *q;
15800
15801 q = (elf_symbol_type *) *p;
15802
252b5132
RH		 15803 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
15804 {
15805 default:
15806 break;
15807 case STT_FILE:
15808 filename = bfd_asymbol_name (&q->symbol);
15809 break;
252b5132
RH		 15810 case STT_FUNC:
15811 case STT_ARM_TFUNC:
9d2da7ca 15812 case STT_NOTYPE:
b0796911 15813 /* Skip mapping symbols. */
0367ecfb 15814 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 15815 && bfd_is_arm_special_symbol_name (q->symbol.name,
15816 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 15817 continue;
15818 /* Fall through. */
6b40fcba 15819 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 15820 && q->symbol.value >= low_func
15821 && q->symbol.value <= offset)
15822 {
15823 func = (asymbol *) q;
15824 low_func = q->symbol.value;
15825 }
15826 break;
15827 }
15828 }
15829
15830 if (func == NULL)
b34976b6 15831 return FALSE;
252b5132 15832
0367ecfb
NC		 15833 if (filename_ptr)
15834 *filename_ptr = filename;
15835 if (functionname_ptr)
15836 *functionname_ptr = bfd_asymbol_name (func);
15837
15838 return TRUE;
906e58ca 15839}
0367ecfb
NC		 15840
15841
15842/* Find the nearest line to a particular section and offset, for error
15843 reporting. This code is a duplicate of the code in elf.c, except
15844 that it uses arm_elf_find_function. */
15845
15846static bfd_boolean
07d6d2b8
AM		 15847elf32_arm_find_nearest_line (bfd * abfd,
15848 asymbol ** symbols,
15849 asection * section,
15850 bfd_vma offset,
0367ecfb
NC		 15851 const char ** filename_ptr,
15852 const char ** functionname_ptr,
fb167eb2
AM		 15853 unsigned int * line_ptr,
15854 unsigned int * discriminator_ptr)
0367ecfb
NC		 15855{
15856 bfd_boolean found = FALSE;
15857
fb167eb2 15858 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 15859 filename_ptr, functionname_ptr,
fb167eb2
AM		 15860 line_ptr, discriminator_ptr,
15861 dwarf_debug_sections, 0,
0367ecfb
NC		 15862 & elf_tdata (abfd)->dwarf2_find_line_info))
15863 {
15864 if (!*functionname_ptr)
fb167eb2 15865 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15866 *filename_ptr ? NULL : filename_ptr,
15867 functionname_ptr);
f21f3fe0 15868
0367ecfb
NC		 15869 return TRUE;
15870 }
15871
fb167eb2
AM		 15872 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15873 uses DWARF1. */
15874
0367ecfb
NC		 15875 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
15876 & found, filename_ptr,
15877 functionname_ptr, line_ptr,
15878 & elf_tdata (abfd)->line_info))
15879 return FALSE;
15880
15881 if (found && (*functionname_ptr || *line_ptr))
15882 return TRUE;
15883
15884 if (symbols == NULL)
15885 return FALSE;
15886
fb167eb2 15887 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15888 filename_ptr, functionname_ptr))
15889 return FALSE;
15890
15891 *line_ptr = 0;
b34976b6 15892 return TRUE;
252b5132
RH		 15893}
15894
4ab527b0 15895static bfd_boolean
07d6d2b8 15896elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 15897 const char ** filename_ptr,
15898 const char ** functionname_ptr,
15899 unsigned int * line_ptr)
15900{
15901 bfd_boolean found;
15902 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
15903 functionname_ptr, line_ptr,
15904 & elf_tdata (abfd)->dwarf2_find_line_info);
15905 return found;
15906}
15907
63c1f59d
AM		 15908/* Find dynamic relocs for H that apply to read-only sections. */
15909
15910static asection *
15911readonly_dynrelocs (struct elf_link_hash_entry *h)
15912{
15913 struct elf_dyn_relocs *p;
15914
15915 for (p = elf32_arm_hash_entry (h)->dyn_relocs; p != NULL; p = p->next)
15916 {
15917 asection *s = p->sec->output_section;
15918
15919 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15920 return p->sec;
15921 }
15922 return NULL;
15923}
15924
252b5132
RH		 15925/* Adjust a symbol defined by a dynamic object and referenced by a
15926 regular object. The current definition is in some section of the
15927 dynamic object, but we're not including those sections. We have to
15928 change the definition to something the rest of the link can
15929 understand. */
15930
b34976b6 15931static bfd_boolean
57e8b36a
NC		 15932elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
15933 struct elf_link_hash_entry * h)
252b5132
RH		 15934{
15935 bfd * dynobj;
5474d94f 15936 asection *s, *srel;
b7693d02 15937 struct elf32_arm_link_hash_entry * eh;
67687978 15938 struct elf32_arm_link_hash_table *globals;
252b5132 15939
67687978 15940 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15941 if (globals == NULL)
15942 return FALSE;
15943
252b5132
RH		 15944 dynobj = elf_hash_table (info)->dynobj;
15945
15946 /* Make sure we know what is going on here. */
15947 BFD_ASSERT (dynobj != NULL
f5385ebf 15948 && (h->needs_plt
34e77a92 15949 || h->type == STT_GNU_IFUNC
60d67dc8 15950 || h->is_weakalias
f5385ebf
AM		 15951 || (h->def_dynamic
15952 && h->ref_regular
15953 && !h->def_regular)));
252b5132 15954
b7693d02
DJ		 15955 eh = (struct elf32_arm_link_hash_entry *) h;
15956
252b5132
RH		 15957 /* If this is a function, put it in the procedure linkage table. We
15958 will fill in the contents of the procedure linkage table later,
15959 when we know the address of the .got section. */
34e77a92 15960 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 15961 {
34e77a92
RS		 15962 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
15963 symbol binds locally. */
5e681ec4 15964 if (h->plt.refcount <= 0
34e77a92
RS		 15965 || (h->type != STT_GNU_IFUNC
15966 && (SYMBOL_CALLS_LOCAL (info, h)
15967 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15968 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 15969 {
15970 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 15971 file, but the symbol was never referred to by a dynamic
15972 object, or if all references were garbage collected. In
15973 such a case, we don't actually need to build a procedure
15974 linkage table, and we can just do a PC24 reloc instead. */
15975 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15976 eh->plt.thumb_refcount = 0;
15977 eh->plt.maybe_thumb_refcount = 0;
15978 eh->plt.noncall_refcount = 0;
f5385ebf 15979 h->needs_plt = 0;
252b5132
RH		 15980 }
15981
b34976b6 15982 return TRUE;
252b5132 15983 }
5e681ec4 15984 else
b7693d02
DJ		 15985 {
15986 /* It's possible that we incorrectly decided a .plt reloc was
15987 needed for an R_ARM_PC24 or similar reloc to a non-function sym
15988 in check_relocs. We can't decide accurately between function
15989 and non-function syms in check-relocs; Objects loaded later in
15990 the link may change h->type. So fix it now. */
15991 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15992 eh->plt.thumb_refcount = 0;
15993 eh->plt.maybe_thumb_refcount = 0;
15994 eh->plt.noncall_refcount = 0;
b7693d02 15995 }
252b5132
RH		 15996
15997 /* If this is a weak symbol, and there is a real definition, the
15998 processor independent code will have arranged for us to see the
15999 real definition first, and we can just use the same value. */
60d67dc8 16000 if (h->is_weakalias)
252b5132 16001 {
60d67dc8
AM		 16002 struct elf_link_hash_entry *def = weakdef (h);
16003 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
16004 h->root.u.def.section = def->root.u.def.section;
16005 h->root.u.def.value = def->root.u.def.value;
b34976b6 16006 return TRUE;
252b5132
RH		 16007 }
16008
ba93b8ac
DJ		 16009 /* If there are no non-GOT references, we do not need a copy
16010 relocation. */
16011 if (!h->non_got_ref)
16012 return TRUE;
16013
252b5132
RH		 16014 /* This is a reference to a symbol defined by a dynamic object which
16015 is not a function. */
16016
16017 /* If we are creating a shared library, we must presume that the
16018 only references to the symbol are via the global offset table.
16019 For such cases we need not do anything here; the relocations will
67687978
PB		 16020 be handled correctly by relocate_section. Relocatable executables
16021 can reference data in shared objects directly, so we don't need to
16022 do anything here. */
0e1862bb 16023 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 16024 return TRUE;
252b5132
RH		 16025
16026 /* We must allocate the symbol in our .dynbss section, which will
16027 become part of the .bss section of the executable. There will be
16028 an entry for this symbol in the .dynsym section. The dynamic
16029 object will contain position independent code, so all references
16030 from the dynamic object to this symbol will go through the global
16031 offset table. The dynamic linker will use the .dynsym entry to
16032 determine the address it must put in the global offset table, so
16033 both the dynamic object and the regular object will refer to the
16034 same memory location for the variable. */
5522f910
NC		 16035 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16036 linker to copy the initial value out of the dynamic object and into
16037 the runtime process image. We need to remember the offset into the
00a97672 16038 .rel(a).bss section we are going to use. */
5474d94f
AM		 16039 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
16040 {
16041 s = globals->root.sdynrelro;
16042 srel = globals->root.sreldynrelro;
16043 }
16044 else
16045 {
16046 s = globals->root.sdynbss;
16047 srel = globals->root.srelbss;
16048 }
5522f910
NC		 16049 if (info->nocopyreloc == 0
16050 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 16051 && h->size != 0)
252b5132 16052 {
47beaa6a 16053 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 16054 h->needs_copy = 1;
252b5132
RH		 16055 }
16056
6cabe1ea 16057 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 16058}
16059
5e681ec4
PB		 16060/* Allocate space in .plt, .got and associated reloc sections for
16061 dynamic relocs. */
16062
16063static bfd_boolean
47beaa6a 16064allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 16065{
16066 struct bfd_link_info *info;
16067 struct elf32_arm_link_hash_table *htab;
16068 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 16069 struct elf_dyn_relocs *p;
5e681ec4
PB		 16070
16071 if (h->root.type == bfd_link_hash_indirect)
16072 return TRUE;
16073
e6a6bb22
AM		 16074 eh = (struct elf32_arm_link_hash_entry *) h;
16075
5e681ec4
PB		 16076 info = (struct bfd_link_info *) inf;
16077 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16078 if (htab == NULL)
16079 return FALSE;
5e681ec4 16080
34e77a92 16081 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 16082 && h->plt.refcount > 0)
16083 {
16084 /* Make sure this symbol is output as a dynamic symbol.
16085 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16086 if (h->dynindx == -1 && !h->forced_local
16087 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16088 {
c152c796 16089 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16090 return FALSE;
16091 }
16092
34e77a92
RS		 16093 /* If the call in the PLT entry binds locally, the associated
16094 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16095 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16096 than the .plt section. */
16097 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16098 {
16099 eh->is_iplt = 1;
16100 if (eh->plt.noncall_refcount == 0
16101 && SYMBOL_REFERENCES_LOCAL (info, h))
16102 /* All non-call references can be resolved directly.
16103 This means that they can (and in some cases, must)
16104 resolve directly to the run-time target, rather than
16105 to the PLT. That in turns means that any .got entry
16106 would be equal to the .igot.plt entry, so there's
16107 no point having both. */
16108 h->got.refcount = 0;
16109 }
16110
0e1862bb 16111 if (bfd_link_pic (info)
34e77a92 16112 || eh->is_iplt
7359ea65 16113 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 16114 {
34e77a92 16115 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 16116
5e681ec4
PB		 16117 /* If this symbol is not defined in a regular file, and we are
16118 not generating a shared library, then set the symbol to this
16119 location in the .plt. This is required to make function
16120 pointers compare as equal between the normal executable and
16121 the shared library. */
0e1862bb 16122 if (! bfd_link_pic (info)
f5385ebf 16123 && !h->def_regular)
5e681ec4 16124 {
34e77a92 16125 h->root.u.def.section = htab->root.splt;
5e681ec4 16126 h->root.u.def.value = h->plt.offset;
5e681ec4 16127
67d74e43
DJ		 16128 /* Make sure the function is not marked as Thumb, in case
16129 it is the target of an ABS32 relocation, which will
16130 point to the PLT entry. */
39d911fc 16131 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 16132 }
022f8312 16133
00a97672
RS		 16134 /* VxWorks executables have a second set of relocations for
16135 each PLT entry. They go in a separate relocation section,
16136 which is processed by the kernel loader. */
0e1862bb 16137 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 16138 {
16139 /* There is a relocation for the initial PLT entry:
16140 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16141 if (h->plt.offset == htab->plt_header_size)
47beaa6a 16142 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 16143
16144 /* There are two extra relocations for each subsequent
16145 PLT entry: an R_ARM_32 relocation for the GOT entry,
16146 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 16147 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 16148 }
5e681ec4
PB		 16149 }
16150 else
16151 {
16152 h->plt.offset = (bfd_vma) -1;
f5385ebf 16153 h->needs_plt = 0;
5e681ec4
PB		 16154 }
16155 }
16156 else
16157 {
16158 h->plt.offset = (bfd_vma) -1;
f5385ebf 16159 h->needs_plt = 0;
5e681ec4
PB		 16160 }
16161
0855e32b
NS		 16162 eh = (struct elf32_arm_link_hash_entry *) h;
16163 eh->tlsdesc_got = (bfd_vma) -1;
16164
5e681ec4
PB		 16165 if (h->got.refcount > 0)
16166 {
16167 asection *s;
16168 bfd_boolean dyn;
ba93b8ac
DJ		 16169 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16170 int indx;
5e681ec4
PB		 16171
16172 /* Make sure this symbol is output as a dynamic symbol.
16173 Undefined weak syms won't yet be marked as dynamic. */
e8b09b87 16174 if (htab->root.dynamic_sections_created && h->dynindx == -1 && !h->forced_local
6c699715 16175 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16176 {
c152c796 16177 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16178 return FALSE;
16179 }
16180
e5a52504
MM		 16181 if (!htab->symbian_p)
16182 {
362d30a1 16183 s = htab->root.sgot;
e5a52504 16184 h->got.offset = s->size;
ba93b8ac
DJ		 16185
16186 if (tls_type == GOT_UNKNOWN)
16187 abort ();
16188
16189 if (tls_type == GOT_NORMAL)
16190 /* Non-TLS symbols need one GOT slot. */
16191 s->size += 4;
16192 else
16193 {
99059e56
RM		 16194 if (tls_type & GOT_TLS_GDESC)
16195 {
0855e32b 16196 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 16197 eh->tlsdesc_got
0855e32b
NS		 16198 = (htab->root.sgotplt->size
16199 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 16200 htab->root.sgotplt->size += 8;
16201 h->got.offset = (bfd_vma) -2;
34e77a92 16202 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16203 reloc in the middle of .got.plt. */
99059e56
RM		 16204 htab->num_tls_desc++;
16205 }
0855e32b 16206
ba93b8ac 16207 if (tls_type & GOT_TLS_GD)
0855e32b 16208 {
5c5a4843
CL		 16209 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16210 consecutive GOT slots. If the symbol is both GD
16211 and GDESC, got.offset may have been
16212 overwritten. */
0855e32b
NS		 16213 h->got.offset = s->size;
16214 s->size += 8;
16215 }
16216
ba93b8ac 16217 if (tls_type & GOT_TLS_IE)
5c5a4843
CL		 16218 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16219 slot. */
ba93b8ac
DJ		 16220 s->size += 4;
16221 }
16222
e5a52504 16223 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 16224
16225 indx = 0;
0e1862bb
L		 16226 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
16227 bfd_link_pic (info),
16228 h)
16229 && (!bfd_link_pic (info)
ba93b8ac
DJ		 16230 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16231 indx = h->dynindx;
16232
16233 if (tls_type != GOT_NORMAL
0e1862bb 16234 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 16235 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16236 || h->root.type != bfd_link_hash_undefweak))
16237 {
16238 if (tls_type & GOT_TLS_IE)
47beaa6a 16239 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16240
16241 if (tls_type & GOT_TLS_GD)
47beaa6a 16242 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16243
b38cadfb 16244 if (tls_type & GOT_TLS_GDESC)
0855e32b 16245 {
47beaa6a 16246 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 16247 /* GDESC needs a trampoline to jump to. */
16248 htab->tls_trampoline = -1;
16249 }
16250
16251 /* Only GD needs it. GDESC just emits one relocation per
16252 2 entries. */
b38cadfb 16253 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 16254 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16255 }
e8b09b87
CL		 16256 else if (((indx != -1) || htab->fdpic_p)
16257 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 16258 {
16259 if (htab->root.dynamic_sections_created)
16260 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16261 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16262 }
34e77a92
RS		 16263 else if (h->type == STT_GNU_IFUNC
16264 && eh->plt.noncall_refcount == 0)
16265 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16266 they all resolve dynamically instead. Reserve room for the
16267 GOT entry's R_ARM_IRELATIVE relocation. */
16268 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 16269 else if (bfd_link_pic (info)
16270 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16271 || h->root.type != bfd_link_hash_undefweak))
b436d854 16272 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 16273 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16274 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16275 /* Reserve room for rofixup for FDPIC executable. */
16276 /* TLS relocs do not need space since they are completely
16277 resolved. */
16278 htab->srofixup->size += 4;
e5a52504 16279 }
5e681ec4
PB		 16280 }
16281 else
16282 h->got.offset = (bfd_vma) -1;
16283
e8b09b87
CL		 16284 /* FDPIC support. */
16285 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16286 {
16287 /* Symbol musn't be exported. */
16288 if (h->dynindx != -1)
16289 abort();
16290
16291 /* We only allocate one function descriptor with its associated relocation. */
16292 if (eh->fdpic_cnts.funcdesc_offset == -1)
16293 {
16294 asection *s = htab->root.sgot;
16295
16296 eh->fdpic_cnts.funcdesc_offset = s->size;
16297 s->size += 8;
16298 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16299 if (bfd_link_pic(info))
16300 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16301 else
16302 htab->srofixup->size += 8;
16303 }
16304 }
16305
16306 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16307 {
16308 asection *s = htab->root.sgot;
16309
16310 if (htab->root.dynamic_sections_created && h->dynindx == -1
16311 && !h->forced_local)
16312 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16313 return FALSE;
16314
16315 if (h->dynindx == -1)
16316 {
16317 /* We only allocate one function descriptor with its associated relocation. q */
16318 if (eh->fdpic_cnts.funcdesc_offset == -1)
16319 {
16320
16321 eh->fdpic_cnts.funcdesc_offset = s->size;
16322 s->size += 8;
16323 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16324 if (bfd_link_pic(info))
16325 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16326 else
16327 htab->srofixup->size += 8;
16328 }
16329 }
16330
16331 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16332 R_ARM_RELATIVE/rofixup relocation on it. */
16333 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16334 s->size += 4;
16335 if (h->dynindx == -1 && !bfd_link_pic(info))
4b24dd1a 16336 htab->srofixup->size += 4;
e8b09b87 16337 else
4b24dd1a 16338 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16339 }
16340
16341 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16342 {
16343 if (htab->root.dynamic_sections_created && h->dynindx == -1
16344 && !h->forced_local)
16345 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16346 return FALSE;
16347
16348 if (h->dynindx == -1)
16349 {
16350 /* We only allocate one function descriptor with its associated relocation. */
16351 if (eh->fdpic_cnts.funcdesc_offset == -1)
16352 {
16353 asection *s = htab->root.sgot;
16354
16355 eh->fdpic_cnts.funcdesc_offset = s->size;
16356 s->size += 8;
16357 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16358 if (bfd_link_pic(info))
16359 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16360 else
16361 htab->srofixup->size += 8;
16362 }
16363 }
16364 if (h->dynindx == -1 && !bfd_link_pic(info))
16365 {
16366 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16367 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16368 }
16369 else
16370 {
16371 /* Will need one dynamic reloc per reference. will be either
16372 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16373 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16374 eh->fdpic_cnts.funcdesc_cnt);
16375 }
16376 }
16377
a4fd1a8e
PB		 16378 /* Allocate stubs for exported Thumb functions on v4t. */
16379 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 16380 && h->def_regular
39d911fc 16381 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 16382 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16383 {
16384 struct elf_link_hash_entry * th;
16385 struct bfd_link_hash_entry * bh;
16386 struct elf_link_hash_entry * myh;
16387 char name[1024];
16388 asection *s;
16389 bh = NULL;
16390 /* Create a new symbol to regist the real location of the function. */
16391 s = h->root.u.def.section;
906e58ca 16392 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 16393 _bfd_generic_link_add_one_symbol (info, s->owner,
16394 name, BSF_GLOBAL, s,
16395 h->root.u.def.value,
16396 NULL, TRUE, FALSE, &bh);
16397
16398 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 16399 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 16400 myh->forced_local = 1;
39d911fc 16401 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 16402 eh->export_glue = myh;
16403 th = record_arm_to_thumb_glue (info, h);
16404 /* Point the symbol at the stub. */
16405 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 16406 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 16407 h->root.u.def.section = th->root.u.def.section;
16408 h->root.u.def.value = th->root.u.def.value & ~1;
16409 }
16410
0bdcacaf 16411 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 16412 return TRUE;
16413
16414 /* In the shared -Bsymbolic case, discard space allocated for
16415 dynamic pc-relative relocs against symbols which turn out to be
16416 defined in regular objects. For the normal shared case, discard
16417 space for pc-relative relocs that have become local due to symbol
16418 visibility changes. */
16419
e8b09b87 16420 if (bfd_link_pic (info) || htab->root.is_relocatable_executable || htab->fdpic_p)
5e681ec4 16421 {
469a3493
RM		 16422 /* Relocs that use pc_count are PC-relative forms, which will appear
16423 on something like ".long foo - ." or "movw REG, foo - .". We want
16424 calls to protected symbols to resolve directly to the function
16425 rather than going via the plt. If people want function pointer
16426 comparisons to work as expected then they should avoid writing
16427 assembly like ".long foo - .". */
ba93b8ac
DJ		 16428 if (SYMBOL_CALLS_LOCAL (info, h))
16429 {
0bdcacaf 16430 struct elf_dyn_relocs **pp;
ba93b8ac 16431
0bdcacaf 16432 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 16433 {
16434 p->count -= p->pc_count;
16435 p->pc_count = 0;
16436 if (p->count == 0)
16437 *pp = p->next;
16438 else
16439 pp = &p->next;
16440 }
16441 }
16442
4dfe6ac6 16443 if (htab->vxworks_p)
3348747a 16444 {
0bdcacaf 16445 struct elf_dyn_relocs **pp;
3348747a 16446
0bdcacaf 16447 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 16448 {
0bdcacaf 16449 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 16450 *pp = p->next;
16451 else
16452 pp = &p->next;
16453 }
16454 }
16455
ba93b8ac 16456 /* Also discard relocs on undefined weak syms with non-default
99059e56 16457 visibility. */
0bdcacaf 16458 if (eh->dyn_relocs != NULL
5e681ec4 16459 && h->root.type == bfd_link_hash_undefweak)
22d606e9 16460 {
95b03e4a
L		 16461 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16462 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
0bdcacaf 16463 eh->dyn_relocs = NULL;
22d606e9
AM		 16464
16465 /* Make sure undefined weak symbols are output as a dynamic
16466 symbol in PIEs. */
e8b09b87 16467 else if (htab->root.dynamic_sections_created && h->dynindx == -1
22d606e9
AM		 16468 && !h->forced_local)
16469 {
16470 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16471 return FALSE;
16472 }
16473 }
16474
67687978
PB		 16475 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16476 && h->root.type == bfd_link_hash_new)
16477 {
16478 /* Output absolute symbols so that we can create relocations
16479 against them. For normal symbols we output a relocation
16480 against the section that contains them. */
16481 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16482 return FALSE;
16483 }
16484
5e681ec4
PB		 16485 }
16486 else
16487 {
16488 /* For the non-shared case, discard space for relocs against
16489 symbols which turn out to need copy relocs or are not
16490 dynamic. */
16491
f5385ebf
AM		 16492 if (!h->non_got_ref
16493 && ((h->def_dynamic
16494 && !h->def_regular)
5e681ec4
PB		 16495 || (htab->root.dynamic_sections_created
16496 && (h->root.type == bfd_link_hash_undefweak
16497 || h->root.type == bfd_link_hash_undefined))))
16498 {
16499 /* Make sure this symbol is output as a dynamic symbol.
16500 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16501 if (h->dynindx == -1 && !h->forced_local
16502 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16503 {
c152c796 16504 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16505 return FALSE;
16506 }
16507
16508 /* If that succeeded, we know we'll be keeping all the
16509 relocs. */
16510 if (h->dynindx != -1)
16511 goto keep;
16512 }
16513
0bdcacaf 16514 eh->dyn_relocs = NULL;
5e681ec4
PB		 16515
16516 keep: ;
16517 }
16518
16519 /* Finally, allocate space. */
0bdcacaf 16520 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 16521 {
0bdcacaf 16522 asection *sreloc = elf_section_data (p->sec)->sreloc;
e8b09b87 16523
34e77a92
RS		 16524 if (h->type == STT_GNU_IFUNC
16525 && eh->plt.noncall_refcount == 0
16526 && SYMBOL_REFERENCES_LOCAL (info, h))
16527 elf32_arm_allocate_irelocs (info, sreloc, p->count);
e8b09b87
CL		 16528 else if (h->dynindx != -1 && (!bfd_link_pic(info) || !info->symbolic || !h->def_regular))
16529 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16530 else if (htab->fdpic_p && !bfd_link_pic(info))
16531 htab->srofixup->size += 4 * p->count;
34e77a92
RS		 16532 else
16533 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 16534 }
16535
16536 return TRUE;
16537}
16538
63c1f59d
AM		 16539/* Set DF_TEXTREL if we find any dynamic relocs that apply to
16540 read-only sections. */
08d1f311
DJ		 16541
16542static bfd_boolean
63c1f59d 16543maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p)
08d1f311 16544{
63c1f59d 16545 asection *sec;
08d1f311 16546
63c1f59d
AM		 16547 if (h->root.type == bfd_link_hash_indirect)
16548 return TRUE;
08d1f311 16549
63c1f59d
AM		 16550 sec = readonly_dynrelocs (h);
16551 if (sec != NULL)
16552 {
16553 struct bfd_link_info *info = (struct bfd_link_info *) info_p;
08d1f311 16554
63c1f59d
AM		 16555 info->flags |= DF_TEXTREL;
16556 info->callbacks->minfo
c1c8c1ef 16557 (_("%pB: dynamic relocation against `%pT' in read-only section `%pA'\n"),
63c1f59d 16558 sec->owner, h->root.root.string, sec);
08d1f311 16559
63c1f59d
AM		 16560 /* Not an error, just cut short the traversal. */
16561 return FALSE;
08d1f311 16562 }
cb10292c 16563
08d1f311
DJ		 16564 return TRUE;
16565}
16566
d504ffc8
DJ		 16567void
16568bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16569 int byteswap_code)
16570{
16571 struct elf32_arm_link_hash_table *globals;
16572
16573 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16574 if (globals == NULL)
16575 return;
16576
d504ffc8
DJ		 16577 globals->byteswap_code = byteswap_code;
16578}
16579
252b5132
RH		 16580/* Set the sizes of the dynamic sections. */
16581
b34976b6 16582static bfd_boolean
57e8b36a
NC		 16583elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16584 struct bfd_link_info * info)
252b5132
RH		 16585{
16586 bfd * dynobj;
16587 asection * s;
b34976b6
AM		 16588 bfd_boolean plt;
16589 bfd_boolean relocs;
5e681ec4
PB		 16590 bfd *ibfd;
16591 struct elf32_arm_link_hash_table *htab;
252b5132 16592
5e681ec4 16593 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16594 if (htab == NULL)
16595 return FALSE;
16596
252b5132
RH		 16597 dynobj = elf_hash_table (info)->dynobj;
16598 BFD_ASSERT (dynobj != NULL);
39b41c9c 16599 check_use_blx (htab);
252b5132
RH		 16600
16601 if (elf_hash_table (info)->dynamic_sections_created)
16602 {
16603 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 16604 if (bfd_link_executable (info) && !info->nointerp)
252b5132 16605 {
3d4d4302 16606 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 16607 BFD_ASSERT (s != NULL);
eea6121a 16608 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 16609 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16610 }
16611 }
5e681ec4
PB		 16612
16613 /* Set up .got offsets for local syms, and space for local dynamic
16614 relocs. */
c72f2fb2 16615 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 16616 {
5e681ec4
PB		 16617 bfd_signed_vma *local_got;
16618 bfd_signed_vma *end_local_got;
34e77a92 16619 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 16620 char *local_tls_type;
0855e32b 16621 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 16622 bfd_size_type locsymcount;
16623 Elf_Internal_Shdr *symtab_hdr;
16624 asection *srel;
4dfe6ac6 16625 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 16626 unsigned int symndx;
e8b09b87 16627 struct fdpic_local *local_fdpic_cnts;
5e681ec4 16628
0ffa91dd 16629 if (! is_arm_elf (ibfd))
5e681ec4
PB		 16630 continue;
16631
16632 for (s = ibfd->sections; s != NULL; s = s->next)
16633 {
0bdcacaf 16634 struct elf_dyn_relocs *p;
5e681ec4 16635
0bdcacaf 16636 for (p = (struct elf_dyn_relocs *)
99059e56 16637 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 16638 {
0bdcacaf
RS		 16639 if (!bfd_is_abs_section (p->sec)
16640 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 16641 {
16642 /* Input section has been discarded, either because
16643 it is a copy of a linkonce section or due to
16644 linker script /DISCARD/, so we'll be discarding
16645 the relocs too. */
16646 }
3348747a 16647 else if (is_vxworks
0bdcacaf 16648 && strcmp (p->sec->output_section->name,
3348747a
NS		 16649 ".tls_vars") == 0)
16650 {
16651 /* Relocations in vxworks .tls_vars sections are
16652 handled specially by the loader. */
16653 }
5e681ec4
PB		 16654 else if (p->count != 0)
16655 {
0bdcacaf 16656 srel = elf_section_data (p->sec)->sreloc;
e8b09b87
CL		 16657 if (htab->fdpic_p && !bfd_link_pic(info))
16658 htab->srofixup->size += 4 * p->count;
16659 else
16660 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 16661 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 16662 info->flags |= DF_TEXTREL;
16663 }
16664 }
16665 }
16666
16667 local_got = elf_local_got_refcounts (ibfd);
16668 if (!local_got)
16669 continue;
16670
0ffa91dd 16671 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 16672 locsymcount = symtab_hdr->sh_info;
16673 end_local_got = local_got + locsymcount;
34e77a92 16674 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 16675 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 16676 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
e8b09b87 16677 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
34e77a92 16678 symndx = 0;
362d30a1
RS		 16679 s = htab->root.sgot;
16680 srel = htab->root.srelgot;
0855e32b 16681 for (; local_got < end_local_got;
34e77a92 16682 ++local_got, ++local_iplt_ptr, ++local_tls_type,
e8b09b87 16683 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
5e681ec4 16684 {
0855e32b 16685 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92 16686 local_iplt = *local_iplt_ptr;
e8b09b87
CL		 16687
16688 /* FDPIC support. */
16689 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16690 {
16691 if (local_fdpic_cnts->funcdesc_offset == -1)
16692 {
16693 local_fdpic_cnts->funcdesc_offset = s->size;
16694 s->size += 8;
16695
16696 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16697 if (bfd_link_pic(info))
16698 elf32_arm_allocate_dynrelocs (info, srel, 1);
16699 else
16700 htab->srofixup->size += 8;
16701 }
16702 }
16703
16704 if (local_fdpic_cnts->funcdesc_cnt > 0)
16705 {
16706 if (local_fdpic_cnts->funcdesc_offset == -1)
16707 {
16708 local_fdpic_cnts->funcdesc_offset = s->size;
16709 s->size += 8;
16710
16711 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16712 if (bfd_link_pic(info))
16713 elf32_arm_allocate_dynrelocs (info, srel, 1);
16714 else
16715 htab->srofixup->size += 8;
16716 }
16717
16718 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16719 if (bfd_link_pic(info))
16720 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16721 else
16722 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16723 }
16724
34e77a92
RS		 16725 if (local_iplt != NULL)
16726 {
16727 struct elf_dyn_relocs *p;
16728
16729 if (local_iplt->root.refcount > 0)
16730 {
16731 elf32_arm_allocate_plt_entry (info, TRUE,
16732 &local_iplt->root,
16733 &local_iplt->arm);
16734 if (local_iplt->arm.noncall_refcount == 0)
16735 /* All references to the PLT are calls, so all
16736 non-call references can resolve directly to the
16737 run-time target. This means that the .got entry
16738 would be the same as the .igot.plt entry, so there's
16739 no point creating both. */
16740 *local_got = 0;
16741 }
16742 else
16743 {
16744 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
16745 local_iplt->root.offset = (bfd_vma) -1;
16746 }
16747
16748 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
16749 {
16750 asection *psrel;
16751
16752 psrel = elf_section_data (p->sec)->sreloc;
16753 if (local_iplt->arm.noncall_refcount == 0)
16754 elf32_arm_allocate_irelocs (info, psrel, p->count);
16755 else
16756 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
16757 }
16758 }
5e681ec4
PB		 16759 if (*local_got > 0)
16760 {
34e77a92
RS		 16761 Elf_Internal_Sym *isym;
16762
eea6121a 16763 *local_got = s->size;
ba93b8ac
DJ		 16764 if (*local_tls_type & GOT_TLS_GD)
16765 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16766 s->size += 8;
0855e32b
NS		 16767 if (*local_tls_type & GOT_TLS_GDESC)
16768 {
16769 *local_tlsdesc_gotent = htab->root.sgotplt->size
16770 - elf32_arm_compute_jump_table_size (htab);
16771 htab->root.sgotplt->size += 8;
16772 *local_got = (bfd_vma) -2;
34e77a92 16773 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16774 reloc in the middle of .got.plt. */
99059e56 16775 htab->num_tls_desc++;
0855e32b 16776 }
ba93b8ac
DJ		 16777 if (*local_tls_type & GOT_TLS_IE)
16778 s->size += 4;
ba93b8ac 16779
0855e32b
NS		 16780 if (*local_tls_type & GOT_NORMAL)
16781 {
16782 /* If the symbol is both GD and GDESC, *local_got
16783 may have been overwritten. */
16784 *local_got = s->size;
16785 s->size += 4;
16786 }
16787
34e77a92
RS		 16788 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
16789 if (isym == NULL)
16790 return FALSE;
16791
16792 /* If all references to an STT_GNU_IFUNC PLT are calls,
16793 then all non-call references, including this GOT entry,
16794 resolve directly to the run-time target. */
16795 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
16796 && (local_iplt == NULL
16797 || local_iplt->arm.noncall_refcount == 0))
16798 elf32_arm_allocate_irelocs (info, srel, 1);
e8b09b87 16799 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
0855e32b 16800 {
e8b09b87 16801 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
3064e1ff 16802 elf32_arm_allocate_dynrelocs (info, srel, 1);
e8b09b87
CL		 16803 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
16804 htab->srofixup->size += 4;
99059e56 16805
e8b09b87
CL		 16806 if ((bfd_link_pic (info) || htab->fdpic_p)
16807 && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 16808 {
16809 elf32_arm_allocate_dynrelocs (info,
16810 htab->root.srelplt, 1);
16811 htab->tls_trampoline = -1;
16812 }
0855e32b 16813 }
5e681ec4
PB		 16814 }
16815 else
16816 *local_got = (bfd_vma) -1;
16817 }
252b5132
RH		 16818 }
16819
ba93b8ac
DJ		 16820 if (htab->tls_ldm_got.refcount > 0)
16821 {
16822 /* Allocate two GOT entries and one dynamic relocation (if necessary)
5c5a4843 16823 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
362d30a1
RS		 16824 htab->tls_ldm_got.offset = htab->root.sgot->size;
16825 htab->root.sgot->size += 8;
0e1862bb 16826 if (bfd_link_pic (info))
47beaa6a 16827 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16828 }
16829 else
16830 htab->tls_ldm_got.offset = -1;
16831
e8b09b87
CL		 16832 /* At the very end of the .rofixup section is a pointer to the GOT,
16833 reserve space for it. */
16834 if (htab->fdpic_p && htab->srofixup != NULL)
16835 htab->srofixup->size += 4;
16836
5e681ec4
PB		 16837 /* Allocate global sym .plt and .got entries, and space for global
16838 sym dynamic relocs. */
47beaa6a 16839 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 16840
d504ffc8 16841 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 16842 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 16843 {
0ffa91dd 16844 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 16845 continue;
16846
c7b8f16e
JB		 16847 /* Initialise mapping tables for code/data. */
16848 bfd_elf32_arm_init_maps (ibfd);
906e58ca 16849
c7b8f16e 16850 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 16851 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
16852 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 16853 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 16854 }
d504ffc8 16855
3e6b1042
DJ		 16856 /* Allocate space for the glue sections now that we've sized them. */
16857 bfd_elf32_arm_allocate_interworking_sections (info);
16858
0855e32b
NS		 16859 /* For every jump slot reserved in the sgotplt, reloc_count is
16860 incremented. However, when we reserve space for TLS descriptors,
16861 it's not incremented, so in order to compute the space reserved
16862 for them, it suffices to multiply the reloc count by the jump
16863 slot size. */
16864 if (htab->root.srelplt)
16865 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
16866
16867 if (htab->tls_trampoline)
16868 {
16869 if (htab->root.splt->size == 0)
16870 htab->root.splt->size += htab->plt_header_size;
b38cadfb 16871
0855e32b
NS		 16872 htab->tls_trampoline = htab->root.splt->size;
16873 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 16874
0855e32b 16875 /* If we're not using lazy TLS relocations, don't generate the
99059e56 16876 PLT and GOT entries they require. */
0855e32b
NS		 16877 if (!(info->flags & DF_BIND_NOW))
16878 {
16879 htab->dt_tlsdesc_got = htab->root.sgot->size;
16880 htab->root.sgot->size += 4;
16881
16882 htab->dt_tlsdesc_plt = htab->root.splt->size;
16883 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
16884 }
16885 }
16886
252b5132
RH		 16887 /* The check_relocs and adjust_dynamic_symbol entry points have
16888 determined the sizes of the various dynamic sections. Allocate
16889 memory for them. */
b34976b6
AM		 16890 plt = FALSE;
16891 relocs = FALSE;
252b5132
RH		 16892 for (s = dynobj->sections; s != NULL; s = s->next)
16893 {
16894 const char * name;
252b5132
RH		 16895
16896 if ((s->flags & SEC_LINKER_CREATED) == 0)
16897 continue;
16898
16899 /* It's OK to base decisions on the section name, because none
16900 of the dynobj section names depend upon the input files. */
16901 name = bfd_get_section_name (dynobj, s);
16902
34e77a92 16903 if (s == htab->root.splt)
252b5132 16904 {
c456f082
AM		 16905 /* Remember whether there is a PLT. */
16906 plt = s->size != 0;
252b5132 16907 }
0112cd26 16908 else if (CONST_STRNEQ (name, ".rel"))
252b5132 16909 {
c456f082 16910 if (s->size != 0)
252b5132 16911 {
252b5132 16912 /* Remember whether there are any reloc sections other
00a97672 16913 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 16914 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 16915 relocs = TRUE;
252b5132
RH		 16916
16917 /* We use the reloc_count field as a counter if we need
16918 to copy relocs into the output file. */
16919 s->reloc_count = 0;
16920 }
16921 }
34e77a92
RS		 16922 else if (s != htab->root.sgot
16923 && s != htab->root.sgotplt
16924 && s != htab->root.iplt
16925 && s != htab->root.igotplt
5474d94f 16926 && s != htab->root.sdynbss
e8b09b87
CL		 16927 && s != htab->root.sdynrelro
16928 && s != htab->srofixup)
252b5132
RH		 16929 {
16930 /* It's not one of our sections, so don't allocate space. */
16931 continue;
16932 }
16933
c456f082 16934 if (s->size == 0)
252b5132 16935 {
c456f082 16936 /* If we don't need this section, strip it from the
00a97672
RS		 16937 output file. This is mostly to handle .rel(a).bss and
16938 .rel(a).plt. We must create both sections in
c456f082
AM		 16939 create_dynamic_sections, because they must be created
16940 before the linker maps input sections to output
16941 sections. The linker does that before
16942 adjust_dynamic_symbol is called, and it is that
16943 function which decides whether anything needs to go
16944 into these sections. */
8423293d 16945 s->flags |= SEC_EXCLUDE;
252b5132
RH		 16946 continue;
16947 }
16948
c456f082
AM		 16949 if ((s->flags & SEC_HAS_CONTENTS) == 0)
16950 continue;
16951
252b5132 16952 /* Allocate memory for the section contents. */
21d799b5 16953 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 16954 if (s->contents == NULL)
b34976b6 16955 return FALSE;
252b5132
RH		 16956 }
16957
16958 if (elf_hash_table (info)->dynamic_sections_created)
16959 {
16960 /* Add some entries to the .dynamic section. We fill in the
16961 values later, in elf32_arm_finish_dynamic_sections, but we
16962 must add the entries now so that we get the correct size for
16963 the .dynamic section. The DT_DEBUG entry is filled in by the
16964 dynamic linker and used by the debugger. */
dc810e39 16965#define add_dynamic_entry(TAG, VAL) \
5a580b3a 16966 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 16967
0e1862bb 16968 if (bfd_link_executable (info))
252b5132 16969 {
dc810e39 16970 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 16971 return FALSE;
252b5132
RH		 16972 }
16973
16974 if (plt)
16975 {
dc810e39
AM		 16976 if ( !add_dynamic_entry (DT_PLTGOT, 0)
16977 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 16978 || !add_dynamic_entry (DT_PLTREL,
16979 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 16980 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 16981 return FALSE;
0855e32b 16982
5025eb7c
AO		 16983 if (htab->dt_tlsdesc_plt
16984 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
16985 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 16986 return FALSE;
252b5132
RH		 16987 }
16988
16989 if (relocs)
16990 {
00a97672
RS		 16991 if (htab->use_rel)
16992 {
16993 if (!add_dynamic_entry (DT_REL, 0)
16994 || !add_dynamic_entry (DT_RELSZ, 0)
16995 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
16996 return FALSE;
16997 }
16998 else
16999 {
17000 if (!add_dynamic_entry (DT_RELA, 0)
17001 || !add_dynamic_entry (DT_RELASZ, 0)
17002 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
17003 return FALSE;
17004 }
252b5132
RH		 17005 }
17006
08d1f311
DJ		 17007 /* If any dynamic relocs apply to a read-only section,
17008 then we need a DT_TEXTREL entry. */
17009 if ((info->flags & DF_TEXTREL) == 0)
63c1f59d 17010 elf_link_hash_traverse (&htab->root, maybe_set_textrel, info);
08d1f311 17011
99e4ae17 17012 if ((info->flags & DF_TEXTREL) != 0)
252b5132 17013 {
dc810e39 17014 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 17015 return FALSE;
252b5132 17016 }
7a2b07ff
NS		 17017 if (htab->vxworks_p
17018 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
17019 return FALSE;
252b5132 17020 }
8532796c 17021#undef add_dynamic_entry
252b5132 17022
b34976b6 17023 return TRUE;
252b5132
RH		 17024}
17025
0855e32b
NS		 17026/* Size sections even though they're not dynamic. We use it to setup
17027 _TLS_MODULE_BASE_, if needed. */
17028
17029static bfd_boolean
17030elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 17031 struct bfd_link_info *info)
0855e32b
NS		 17032{
17033 asection *tls_sec;
cb10292c
CL		 17034 struct elf32_arm_link_hash_table *htab;
17035
17036 htab = elf32_arm_hash_table (info);
0855e32b 17037
0e1862bb 17038 if (bfd_link_relocatable (info))
0855e32b
NS		 17039 return TRUE;
17040
17041 tls_sec = elf_hash_table (info)->tls_sec;
17042
17043 if (tls_sec)
17044 {
17045 struct elf_link_hash_entry *tlsbase;
17046
17047 tlsbase = elf_link_hash_lookup
17048 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
17049
17050 if (tlsbase)
99059e56
RM		 17051 {
17052 struct bfd_link_hash_entry *bh = NULL;
0855e32b 17053 const struct elf_backend_data *bed
99059e56 17054 = get_elf_backend_data (output_bfd);
0855e32b 17055
99059e56 17056 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 17057 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
17058 tls_sec, 0, NULL, FALSE,
17059 bed->collect, &bh)))
17060 return FALSE;
b38cadfb 17061
99059e56
RM		 17062 tlsbase->type = STT_TLS;
17063 tlsbase = (struct elf_link_hash_entry *)bh;
17064 tlsbase->def_regular = 1;
17065 tlsbase->other = STV_HIDDEN;
17066 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 17067 }
17068 }
cb10292c
CL		 17069
17070 if (htab->fdpic_p && !bfd_link_relocatable (info)
17071 && !bfd_elf_stack_segment_size (output_bfd, info,
17072 "__stacksize", DEFAULT_STACK_SIZE))
17073 return FALSE;
17074
0855e32b
NS		 17075 return TRUE;
17076}
17077
252b5132
RH		 17078/* Finish up dynamic symbol handling. We set the contents of various
17079 dynamic sections here. */
17080
b34976b6 17081static bfd_boolean
906e58ca
NC		 17082elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17083 struct bfd_link_info * info,
17084 struct elf_link_hash_entry * h,
17085 Elf_Internal_Sym * sym)
252b5132 17086{
e5a52504 17087 struct elf32_arm_link_hash_table *htab;
b7693d02 17088 struct elf32_arm_link_hash_entry *eh;
252b5132 17089
e5a52504 17090 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17091 if (htab == NULL)
17092 return FALSE;
17093
b7693d02 17094 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 17095
17096 if (h->plt.offset != (bfd_vma) -1)
17097 {
34e77a92 17098 if (!eh->is_iplt)
e5a52504 17099 {
34e77a92 17100 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 17101 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17102 h->dynindx, 0))
17103 return FALSE;
e5a52504 17104 }
57e8b36a 17105
f5385ebf 17106 if (!h->def_regular)
252b5132
RH		 17107 {
17108 /* Mark the symbol as undefined, rather than as defined in
3a635617 17109 the .plt section. */
252b5132 17110 sym->st_shndx = SHN_UNDEF;
3a635617 17111 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 17112 Otherwise, the PLT entry would provide a definition for
17113 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 17114 and so the symbol would never be NULL. Leave the value if
17115 there were any relocations where pointer equality matters
17116 (this is a clue for the dynamic linker, to make function
17117 pointer comparisons work between an application and shared
17118 library). */
97323ad1 17119 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 17120 sym->st_value = 0;
252b5132 17121 }
34e77a92
RS		 17122 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17123 {
17124 /* At least one non-call relocation references this .iplt entry,
17125 so the .iplt entry is the function's canonical address. */
17126 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 17127 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 17128 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17129 (output_bfd, htab->root.iplt->output_section));
17130 sym->st_value = (h->plt.offset
17131 + htab->root.iplt->output_section->vma
17132 + htab->root.iplt->output_offset);
17133 }
252b5132
RH		 17134 }
17135
f5385ebf 17136 if (h->needs_copy)
252b5132
RH		 17137 {
17138 asection * s;
947216bf 17139 Elf_Internal_Rela rel;
252b5132
RH		 17140
17141 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 17142 BFD_ASSERT (h->dynindx != -1
17143 && (h->root.type == bfd_link_hash_defined
17144 || h->root.type == bfd_link_hash_defweak));
17145
00a97672 17146 rel.r_addend = 0;
252b5132
RH		 17147 rel.r_offset = (h->root.u.def.value
17148 + h->root.u.def.section->output_section->vma
17149 + h->root.u.def.section->output_offset);
17150 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 17151 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 17152 s = htab->root.sreldynrelro;
17153 else
17154 s = htab->root.srelbss;
47beaa6a 17155 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 17156 }
17157
00a97672 17158 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
fac7bd64
CL		 17159 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17160 it is relative to the ".got" section. */
9637f6ef 17161 if (h == htab->root.hdynamic
fac7bd64 17162 || (!htab->fdpic_p && !htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 17163 sym->st_shndx = SHN_ABS;
17164
b34976b6 17165 return TRUE;
252b5132
RH		 17166}
17167
0855e32b
NS		 17168static void
17169arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17170 void *contents,
17171 const unsigned long *template, unsigned count)
17172{
17173 unsigned ix;
b38cadfb 17174
0855e32b
NS		 17175 for (ix = 0; ix != count; ix++)
17176 {
17177 unsigned long insn = template[ix];
17178
17179 /* Emit mov pc,rx if bx is not permitted. */
17180 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17181 insn = (insn & 0xf000000f) | 0x01a0f000;
17182 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17183 }
17184}
17185
99059e56
RM		 17186/* Install the special first PLT entry for elf32-arm-nacl. Unlike
17187 other variants, NaCl needs this entry in a static executable's
17188 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17189 zero. For .iplt really only the last bundle is useful, and .iplt
17190 could have a shorter first entry, with each individual PLT entry's
17191 relative branch calculated differently so it targets the last
17192 bundle instead of the instruction before it (labelled .Lplt_tail
17193 above). But it's simpler to keep the size and layout of PLT0
17194 consistent with the dynamic case, at the cost of some dead code at
17195 the start of .iplt and the one dead store to the stack at the start
17196 of .Lplt_tail. */
17197static void
17198arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17199 asection *plt, bfd_vma got_displacement)
17200{
17201 unsigned int i;
17202
17203 put_arm_insn (htab, output_bfd,
17204 elf32_arm_nacl_plt0_entry[0]
17205 | arm_movw_immediate (got_displacement),
17206 plt->contents + 0);
17207 put_arm_insn (htab, output_bfd,
17208 elf32_arm_nacl_plt0_entry[1]
17209 | arm_movt_immediate (got_displacement),
17210 plt->contents + 4);
17211
17212 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17213 put_arm_insn (htab, output_bfd,
17214 elf32_arm_nacl_plt0_entry[i],
17215 plt->contents + (i * 4));
17216}
17217
252b5132
RH		 17218/* Finish up the dynamic sections. */
17219
b34976b6 17220static bfd_boolean
57e8b36a 17221elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 17222{
17223 bfd * dynobj;
17224 asection * sgot;
17225 asection * sdyn;
4dfe6ac6
NC		 17226 struct elf32_arm_link_hash_table *htab;
17227
17228 htab = elf32_arm_hash_table (info);
17229 if (htab == NULL)
17230 return FALSE;
252b5132
RH		 17231
17232 dynobj = elf_hash_table (info)->dynobj;
17233
362d30a1 17234 sgot = htab->root.sgotplt;
894891db
NC		 17235 /* A broken linker script might have discarded the dynamic sections.
17236 Catch this here so that we do not seg-fault later on. */
17237 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17238 return FALSE;
3d4d4302 17239 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 17240
17241 if (elf_hash_table (info)->dynamic_sections_created)
17242 {
17243 asection *splt;
17244 Elf32_External_Dyn *dyncon, *dynconend;
17245
362d30a1 17246 splt = htab->root.splt;
24a1ba0f 17247 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 17248 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 17249
17250 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 17251 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 17252
252b5132
RH		 17253 for (; dyncon < dynconend; dyncon++)
17254 {
17255 Elf_Internal_Dyn dyn;
17256 const char * name;
17257 asection * s;
17258
17259 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17260
17261 switch (dyn.d_tag)
17262 {
229fcec5
MM		 17263 unsigned int type;
17264
252b5132 17265 default:
7a2b07ff
NS		 17266 if (htab->vxworks_p
17267 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17268 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 17269 break;
17270
229fcec5
MM		 17271 case DT_HASH:
17272 name = ".hash";
17273 goto get_vma_if_bpabi;
17274 case DT_STRTAB:
17275 name = ".dynstr";
17276 goto get_vma_if_bpabi;
17277 case DT_SYMTAB:
17278 name = ".dynsym";
17279 goto get_vma_if_bpabi;
c0042f5d
MM		 17280 case DT_VERSYM:
17281 name = ".gnu.version";
17282 goto get_vma_if_bpabi;
17283 case DT_VERDEF:
17284 name = ".gnu.version_d";
17285 goto get_vma_if_bpabi;
17286 case DT_VERNEED:
17287 name = ".gnu.version_r";
17288 goto get_vma_if_bpabi;
17289
252b5132 17290 case DT_PLTGOT:
4ade44b7 17291 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 17292 goto get_vma;
17293 case DT_JMPREL:
00a97672 17294 name = RELOC_SECTION (htab, ".plt");
252b5132 17295 get_vma:
4ade44b7 17296 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 17297 if (s == NULL)
17298 {
4eca0228 17299 _bfd_error_handler
4ade44b7 17300 (_("could not find section %s"), name);
05456594
NC		 17301 bfd_set_error (bfd_error_invalid_operation);
17302 return FALSE;
17303 }
229fcec5 17304 if (!htab->symbian_p)
4ade44b7 17305 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 17306 else
17307 /* In the BPABI, tags in the PT_DYNAMIC section point
17308 at the file offset, not the memory address, for the
17309 convenience of the post linker. */
4ade44b7 17310 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 17311 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17312 break;
17313
229fcec5
MM		 17314 get_vma_if_bpabi:
17315 if (htab->symbian_p)
17316 goto get_vma;
17317 break;
17318
252b5132 17319 case DT_PLTRELSZ:
362d30a1 17320 s = htab->root.srelplt;
252b5132 17321 BFD_ASSERT (s != NULL);
eea6121a 17322 dyn.d_un.d_val = s->size;
252b5132
RH		 17323 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17324 break;
906e58ca 17325
252b5132 17326 case DT_RELSZ:
00a97672 17327 case DT_RELASZ:
229fcec5
MM		 17328 case DT_REL:
17329 case DT_RELA:
229fcec5
MM		 17330 /* In the BPABI, the DT_REL tag must point at the file
17331 offset, not the VMA, of the first relocation
17332 section. So, we use code similar to that in
17333 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 17334 relocation section, since relocation sections are
17335 never allocated under the BPABI. PLT relocs are also
17336 included. */
229fcec5
MM		 17337 if (htab->symbian_p)
17338 {
17339 unsigned int i;
17340 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
17341 ? SHT_REL : SHT_RELA);
17342 dyn.d_un.d_val = 0;
17343 for (i = 1; i < elf_numsections (output_bfd); i++)
17344 {
906e58ca 17345 Elf_Internal_Shdr *hdr
229fcec5
MM		 17346 = elf_elfsections (output_bfd)[i];
17347 if (hdr->sh_type == type)
17348 {
906e58ca 17349 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 17350 || dyn.d_tag == DT_RELASZ)
17351 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 17352 else if ((ufile_ptr) hdr->sh_offset
17353 <= dyn.d_un.d_val - 1)
229fcec5
MM		 17354 dyn.d_un.d_val = hdr->sh_offset;
17355 }
17356 }
17357 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17358 }
252b5132 17359 break;
88f7bcd5 17360
0855e32b 17361 case DT_TLSDESC_PLT:
99059e56 17362 s = htab->root.splt;
0855e32b
NS		 17363 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
17364 + htab->dt_tlsdesc_plt);
17365 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17366 break;
17367
17368 case DT_TLSDESC_GOT:
99059e56 17369 s = htab->root.sgot;
0855e32b 17370 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 17371 + htab->dt_tlsdesc_got);
0855e32b
NS		 17372 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17373 break;
17374
88f7bcd5
NC		 17375 /* Set the bottom bit of DT_INIT/FINI if the
17376 corresponding function is Thumb. */
17377 case DT_INIT:
17378 name = info->init_function;
17379 goto get_sym;
17380 case DT_FINI:
17381 name = info->fini_function;
17382 get_sym:
17383 /* If it wasn't set by elf_bfd_final_link
4cc11e76 17384 then there is nothing to adjust. */
88f7bcd5
NC		 17385 if (dyn.d_un.d_val != 0)
17386 {
17387 struct elf_link_hash_entry * eh;
17388
17389 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 17390 FALSE, FALSE, TRUE);
39d911fc
TP		 17391 if (eh != NULL
17392 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17393 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 17394 {
17395 dyn.d_un.d_val |= 1;
b34976b6 17396 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 17397 }
17398 }
17399 break;
252b5132
RH		 17400 }
17401 }
17402
24a1ba0f 17403 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 17404 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 17405 {
00a97672
RS		 17406 const bfd_vma *plt0_entry;
17407 bfd_vma got_address, plt_address, got_displacement;
17408
17409 /* Calculate the addresses of the GOT and PLT. */
17410 got_address = sgot->output_section->vma + sgot->output_offset;
17411 plt_address = splt->output_section->vma + splt->output_offset;
17412
17413 if (htab->vxworks_p)
17414 {
17415 /* The VxWorks GOT is relocated by the dynamic linker.
17416 Therefore, we must emit relocations rather than simply
17417 computing the values now. */
17418 Elf_Internal_Rela rel;
17419
17420 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 17421 put_arm_insn (htab, output_bfd, plt0_entry[0],
17422 splt->contents + 0);
17423 put_arm_insn (htab, output_bfd, plt0_entry[1],
17424 splt->contents + 4);
17425 put_arm_insn (htab, output_bfd, plt0_entry[2],
17426 splt->contents + 8);
00a97672
RS		 17427 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17428
8029a119 17429 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 17430 rel.r_offset = plt_address + 12;
17431 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17432 rel.r_addend = 0;
17433 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17434 htab->srelplt2->contents);
17435 }
b38cadfb 17436 else if (htab->nacl_p)
99059e56
RM		 17437 arm_nacl_put_plt0 (htab, output_bfd, splt,
17438 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 17439 else if (using_thumb_only (htab))
17440 {
17441 got_displacement = got_address - (plt_address + 12);
17442
17443 plt0_entry = elf32_thumb2_plt0_entry;
17444 put_arm_insn (htab, output_bfd, plt0_entry[0],
17445 splt->contents + 0);
17446 put_arm_insn (htab, output_bfd, plt0_entry[1],
17447 splt->contents + 4);
17448 put_arm_insn (htab, output_bfd, plt0_entry[2],
17449 splt->contents + 8);
17450
17451 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17452 }
00a97672
RS		 17453 else
17454 {
17455 got_displacement = got_address - (plt_address + 16);
17456
17457 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 17458 put_arm_insn (htab, output_bfd, plt0_entry[0],
17459 splt->contents + 0);
17460 put_arm_insn (htab, output_bfd, plt0_entry[1],
17461 splt->contents + 4);
17462 put_arm_insn (htab, output_bfd, plt0_entry[2],
17463 splt->contents + 8);
17464 put_arm_insn (htab, output_bfd, plt0_entry[3],
17465 splt->contents + 12);
5e681ec4 17466
5e681ec4 17467#ifdef FOUR_WORD_PLT
00a97672
RS		 17468 /* The displacement value goes in the otherwise-unused
17469 last word of the second entry. */
17470 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 17471#else
00a97672 17472 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 17473#endif
00a97672 17474 }
f7a74f8c 17475 }
252b5132
RH		 17476
17477 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17478 really seem like the right value. */
74541ad4
AM		 17479 if (splt->output_section->owner == output_bfd)
17480 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 17481
0855e32b
NS		 17482 if (htab->dt_tlsdesc_plt)
17483 {
17484 bfd_vma got_address
17485 = sgot->output_section->vma + sgot->output_offset;
17486 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17487 + htab->root.sgot->output_offset);
17488 bfd_vma plt_address
17489 = splt->output_section->vma + splt->output_offset;
17490
b38cadfb 17491 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17492 splt->contents + htab->dt_tlsdesc_plt,
17493 dl_tlsdesc_lazy_trampoline, 6);
17494
17495 bfd_put_32 (output_bfd,
17496 gotplt_address + htab->dt_tlsdesc_got
17497 - (plt_address + htab->dt_tlsdesc_plt)
17498 - dl_tlsdesc_lazy_trampoline[6],
17499 splt->contents + htab->dt_tlsdesc_plt + 24);
17500 bfd_put_32 (output_bfd,
17501 got_address - (plt_address + htab->dt_tlsdesc_plt)
17502 - dl_tlsdesc_lazy_trampoline[7],
17503 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
17504 }
17505
17506 if (htab->tls_trampoline)
17507 {
b38cadfb 17508 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17509 splt->contents + htab->tls_trampoline,
17510 tls_trampoline, 3);
17511#ifdef FOUR_WORD_PLT
17512 bfd_put_32 (output_bfd, 0x00000000,
17513 splt->contents + htab->tls_trampoline + 12);
b38cadfb 17514#endif
0855e32b
NS		 17515 }
17516
0e1862bb
L		 17517 if (htab->vxworks_p
17518 && !bfd_link_pic (info)
17519 && htab->root.splt->size > 0)
00a97672
RS		 17520 {
17521 /* Correct the .rel(a).plt.unloaded relocations. They will have
17522 incorrect symbol indexes. */
17523 int num_plts;
eed62c48 17524 unsigned char *p;
00a97672 17525
362d30a1 17526 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 17527 / htab->plt_entry_size);
17528 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17529
17530 for (; num_plts; num_plts--)
17531 {
17532 Elf_Internal_Rela rel;
17533
17534 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17535 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17536 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17537 p += RELOC_SIZE (htab);
17538
17539 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17540 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17541 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17542 p += RELOC_SIZE (htab);
17543 }
17544 }
252b5132
RH		 17545 }
17546
99059e56
RM		 17547 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
17548 /* NaCl uses a special first entry in .iplt too. */
17549 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17550
252b5132 17551 /* Fill in the first three entries in the global offset table. */
229fcec5 17552 if (sgot)
252b5132 17553 {
229fcec5
MM		 17554 if (sgot->size > 0)
17555 {
17556 if (sdyn == NULL)
17557 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17558 else
17559 bfd_put_32 (output_bfd,
17560 sdyn->output_section->vma + sdyn->output_offset,
17561 sgot->contents);
17562 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17563 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17564 }
252b5132 17565
229fcec5
MM		 17566 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17567 }
252b5132 17568
e8b09b87
CL		 17569 /* At the very end of the .rofixup section is a pointer to the GOT. */
17570 if (htab->fdpic_p && htab->srofixup != NULL)
17571 {
17572 struct elf_link_hash_entry *hgot = htab->root.hgot;
17573
17574 bfd_vma got_value = hgot->root.u.def.value
17575 + hgot->root.u.def.section->output_section->vma
17576 + hgot->root.u.def.section->output_offset;
17577
17578 arm_elf_add_rofixup(output_bfd, htab->srofixup, got_value);
17579
17580 /* Make sure we allocated and generated the same number of fixups. */
17581 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17582 }
17583
b34976b6 17584 return TRUE;
252b5132
RH		 17585}
17586
ba96a88f 17587static void
57e8b36a 17588elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 17589{
9b485d32 17590 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 17591 struct elf32_arm_link_hash_table *globals;
ac4c9b04 17592 struct elf_segment_map *m;
ba96a88f
NC		 17593
17594 i_ehdrp = elf_elfheader (abfd);
17595
94a3258f
PB		 17596 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17597 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
17598 else
7394f108 17599 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 17600 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 17601
93204d3a
PB		 17602 if (link_info)
17603 {
17604 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 17605 if (globals != NULL && globals->byteswap_code)
93204d3a 17606 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 17607
17608 if (globals->fdpic_p)
17609 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 17610 }
3bfcb652
NC		 17611
17612 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17613 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17614 {
17615 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 17616 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 17617 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17618 else
17619 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17620 }
ac4c9b04
MG		 17621
17622 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 17623 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 17624 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17625 {
17626 unsigned int j;
17627
17628 if (m->count == 0)
17629 continue;
17630 for (j = 0; j < m->count; j++)
17631 {
f0728ee3 17632 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 17633 break;
17634 }
17635 if (j == m->count)
17636 {
17637 m->p_flags = PF_X;
17638 m->p_flags_valid = 1;
17639 }
17640 }
ba96a88f
NC		 17641}
17642
99e4ae17 17643static enum elf_reloc_type_class
7e612e98
AM		 17644elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17645 const asection *rel_sec ATTRIBUTE_UNUSED,
17646 const Elf_Internal_Rela *rela)
99e4ae17 17647{
f51e552e 17648 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 17649 {
17650 case R_ARM_RELATIVE:
17651 return reloc_class_relative;
17652 case R_ARM_JUMP_SLOT:
17653 return reloc_class_plt;
17654 case R_ARM_COPY:
17655 return reloc_class_copy;
109575d7
JW		 17656 case R_ARM_IRELATIVE:
17657 return reloc_class_ifunc;
99e4ae17
AJ		 17658 default:
17659 return reloc_class_normal;
17660 }
17661}
17662
e489d0ae 17663static void
57e8b36a 17664elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 17665{
5a6c6817 17666 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 17667}
17668
40a18ebd
NC		 17669/* Return TRUE if this is an unwinding table entry. */
17670
17671static bfd_boolean
17672is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17673{
0112cd26
NC		 17674 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
17675 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 17676}
17677
17678
17679/* Set the type and flags for an ARM section. We do this by
17680 the section name, which is a hack, but ought to work. */
17681
17682static bfd_boolean
17683elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17684{
17685 const char * name;
17686
17687 name = bfd_get_section_name (abfd, sec);
17688
17689 if (is_arm_elf_unwind_section_name (abfd, name))
17690 {
17691 hdr->sh_type = SHT_ARM_EXIDX;
17692 hdr->sh_flags |= SHF_LINK_ORDER;
17693 }
ac4c9b04 17694
f0728ee3
AV		 17695 if (sec->flags & SEC_ELF_PURECODE)
17696 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 17697
40a18ebd
NC		 17698 return TRUE;
17699}
17700
6dc132d9
L		 17701/* Handle an ARM specific section when reading an object file. This is
17702 called when bfd_section_from_shdr finds a section with an unknown
17703 type. */
40a18ebd
NC		 17704
17705static bfd_boolean
17706elf32_arm_section_from_shdr (bfd *abfd,
17707 Elf_Internal_Shdr * hdr,
6dc132d9
L		 17708 const char *name,
17709 int shindex)
40a18ebd
NC		 17710{
17711 /* There ought to be a place to keep ELF backend specific flags, but
17712 at the moment there isn't one. We just keep track of the
17713 sections by their name, instead. Fortunately, the ABI gives
17714 names for all the ARM specific sections, so we will probably get
17715 away with this. */
17716 switch (hdr->sh_type)
17717 {
17718 case SHT_ARM_EXIDX:
0951f019
RE		 17719 case SHT_ARM_PREEMPTMAP:
17720 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 17721 break;
17722
17723 default:
17724 return FALSE;
17725 }
17726
6dc132d9 17727 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 17728 return FALSE;
17729
17730 return TRUE;
17731}
e489d0ae 17732
44444f50
NC		 17733static _arm_elf_section_data *
17734get_arm_elf_section_data (asection * sec)
17735{
47b2e99c
JZ		 17736 if (sec && sec->owner && is_arm_elf (sec->owner))
17737 return elf32_arm_section_data (sec);
44444f50
NC		 17738 else
17739 return NULL;
8e3de13a
NC		 17740}
17741
4e617b1e
PB		 17742typedef struct
17743{
57402f1e 17744 void *flaginfo;
4e617b1e 17745 struct bfd_link_info *info;
91a5743d
PB		 17746 asection *sec;
17747 int sec_shndx;
6e0b88f1
AM		 17748 int (*func) (void *, const char *, Elf_Internal_Sym *,
17749 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 17750} output_arch_syminfo;
17751
17752enum map_symbol_type
17753{
17754 ARM_MAP_ARM,
17755 ARM_MAP_THUMB,
17756 ARM_MAP_DATA
17757};
17758
17759
7413f23f 17760/* Output a single mapping symbol. */
4e617b1e
PB		 17761
17762static bfd_boolean
7413f23f
DJ		 17763elf32_arm_output_map_sym (output_arch_syminfo *osi,
17764 enum map_symbol_type type,
17765 bfd_vma offset)
4e617b1e
PB		 17766{
17767 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 17768 Elf_Internal_Sym sym;
17769
91a5743d
PB		 17770 sym.st_value = osi->sec->output_section->vma
17771 + osi->sec->output_offset
17772 + offset;
4e617b1e
PB		 17773 sym.st_size = 0;
17774 sym.st_other = 0;
17775 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 17776 sym.st_shndx = osi->sec_shndx;
35fc36a8 17777 sym.st_target_internal = 0;
fe33d2fa 17778 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 17779 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 17780}
17781
34e77a92
RS		 17782/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17783 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 17784
17785static bfd_boolean
34e77a92
RS		 17786elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
17787 bfd_boolean is_iplt_entry_p,
17788 union gotplt_union *root_plt,
17789 struct arm_plt_info *arm_plt)
4e617b1e 17790{
4e617b1e 17791 struct elf32_arm_link_hash_table *htab;
34e77a92 17792 bfd_vma addr, plt_header_size;
4e617b1e 17793
34e77a92 17794 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 17795 return TRUE;
17796
4dfe6ac6
NC		 17797 htab = elf32_arm_hash_table (osi->info);
17798 if (htab == NULL)
17799 return FALSE;
17800
34e77a92
RS		 17801 if (is_iplt_entry_p)
17802 {
17803 osi->sec = htab->root.iplt;
17804 plt_header_size = 0;
17805 }
17806 else
17807 {
17808 osi->sec = htab->root.splt;
17809 plt_header_size = htab->plt_header_size;
17810 }
17811 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
17812 (osi->info->output_bfd, osi->sec->output_section));
17813
17814 addr = root_plt->offset & -2;
4e617b1e
PB		 17815 if (htab->symbian_p)
17816 {
7413f23f 17817 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17818 return FALSE;
7413f23f 17819 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 17820 return FALSE;
17821 }
17822 else if (htab->vxworks_p)
17823 {
7413f23f 17824 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17825 return FALSE;
7413f23f 17826 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 17827 return FALSE;
7413f23f 17828 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 17829 return FALSE;
7413f23f 17830 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 17831 return FALSE;
17832 }
b38cadfb
NC		 17833 else if (htab->nacl_p)
17834 {
17835 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
17836 return FALSE;
17837 }
7801f98f
CL		 17838 else if (htab->fdpic_p)
17839 {
59029f57
CL		 17840 enum map_symbol_type type = using_thumb_only(htab)
17841 ? ARM_MAP_THUMB
17842 : ARM_MAP_ARM;
17843
7801f98f 17844 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
4b24dd1a
AM		 17845 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
17846 return FALSE;
59029f57 17847 if (!elf32_arm_output_map_sym (osi, type, addr))
4b24dd1a 17848 return FALSE;
7801f98f 17849 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
4b24dd1a 17850 return FALSE;
7801f98f 17851 if (htab->plt_entry_size == 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry))
4b24dd1a
AM		 17852 if (!elf32_arm_output_map_sym (osi, type, addr + 24))
17853 return FALSE;
7801f98f 17854 }
eed94f8f
NC		 17855 else if (using_thumb_only (htab))
17856 {
17857 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
17858 return FALSE;
6a631e86 17859 }
4e617b1e
PB		 17860 else
17861 {
34e77a92 17862 bfd_boolean thumb_stub_p;
bd97cb95 17863
34e77a92
RS		 17864 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
17865 if (thumb_stub_p)
4e617b1e 17866 {
7413f23f 17867 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 17868 return FALSE;
17869 }
17870#ifdef FOUR_WORD_PLT
7413f23f 17871 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17872 return FALSE;
7413f23f 17873 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 17874 return FALSE;
17875#else
906e58ca 17876 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 17877 so only need to output a mapping symbol for the first PLT entry and
17878 entries with thumb thunks. */
34e77a92 17879 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 17880 {
7413f23f 17881 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 17882 return FALSE;
17883 }
17884#endif
17885 }
17886
17887 return TRUE;
17888}
17889
34e77a92
RS		 17890/* Output mapping symbols for PLT entries associated with H. */
17891
17892static bfd_boolean
17893elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
17894{
17895 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
17896 struct elf32_arm_link_hash_entry *eh;
17897
17898 if (h->root.type == bfd_link_hash_indirect)
17899 return TRUE;
17900
17901 if (h->root.type == bfd_link_hash_warning)
17902 /* When warning symbols are created, they **replace** the "real"
17903 entry in the hash table, thus we never get to see the real
17904 symbol in a hash traversal. So look at it now. */
17905 h = (struct elf_link_hash_entry *) h->root.u.i.link;
17906
17907 eh = (struct elf32_arm_link_hash_entry *) h;
17908 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
17909 &h->plt, &eh->plt);
17910}
17911
4f4faa4d
TP		 17912/* Bind a veneered symbol to its veneer identified by its hash entry
17913 STUB_ENTRY. The veneered location thus loose its symbol. */
17914
17915static void
17916arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
17917{
17918 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
17919
17920 BFD_ASSERT (hash);
17921 hash->root.root.u.def.section = stub_entry->stub_sec;
17922 hash->root.root.u.def.value = stub_entry->stub_offset;
17923 hash->root.size = stub_entry->stub_size;
17924}
17925
7413f23f
DJ		 17926/* Output a single local symbol for a generated stub. */
17927
17928static bfd_boolean
17929elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
17930 bfd_vma offset, bfd_vma size)
17931{
7413f23f
DJ		 17932 Elf_Internal_Sym sym;
17933
7413f23f
DJ		 17934 sym.st_value = osi->sec->output_section->vma
17935 + osi->sec->output_offset
17936 + offset;
17937 sym.st_size = size;
17938 sym.st_other = 0;
17939 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
17940 sym.st_shndx = osi->sec_shndx;
35fc36a8 17941 sym.st_target_internal = 0;
57402f1e 17942 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 17943}
4e617b1e 17944
da5938a2 17945static bfd_boolean
8029a119
NC		 17946arm_map_one_stub (struct bfd_hash_entry * gen_entry,
17947 void * in_arg)
da5938a2
NC		 17948{
17949 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 17950 asection *stub_sec;
17951 bfd_vma addr;
7413f23f 17952 char *stub_name;
9a008db3 17953 output_arch_syminfo *osi;
d3ce72d0 17954 const insn_sequence *template_sequence;
461a49ca
DJ		 17955 enum stub_insn_type prev_type;
17956 int size;
17957 int i;
17958 enum map_symbol_type sym_type;
da5938a2
NC		 17959
17960 /* Massage our args to the form they really have. */
17961 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 17962 osi = (output_arch_syminfo *) in_arg;
da5938a2 17963
da5938a2
NC		 17964 stub_sec = stub_entry->stub_sec;
17965
17966 /* Ensure this stub is attached to the current section being
7413f23f 17967 processed. */
da5938a2
NC		 17968 if (stub_sec != osi->sec)
17969 return TRUE;
17970
7413f23f 17971 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 17972 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 17973
17974 if (arm_stub_sym_claimed (stub_entry->stub_type))
17975 arm_stub_claim_sym (stub_entry);
17976 else
7413f23f 17977 {
4f4faa4d
TP		 17978 stub_name = stub_entry->output_name;
17979 switch (template_sequence[0].type)
17980 {
17981 case ARM_TYPE:
17982 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
17983 stub_entry->stub_size))
17984 return FALSE;
17985 break;
17986 case THUMB16_TYPE:
17987 case THUMB32_TYPE:
17988 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
17989 stub_entry->stub_size))
17990 return FALSE;
17991 break;
17992 default:
17993 BFD_FAIL ();
17994 return 0;
17995 }
7413f23f 17996 }
da5938a2 17997
461a49ca
DJ		 17998 prev_type = DATA_TYPE;
17999 size = 0;
18000 for (i = 0; i < stub_entry->stub_template_size; i++)
18001 {
d3ce72d0 18002 switch (template_sequence[i].type)
461a49ca
DJ		 18003 {
18004 case ARM_TYPE:
18005 sym_type = ARM_MAP_ARM;
18006 break;
18007
18008 case THUMB16_TYPE:
48229727 18009 case THUMB32_TYPE:
461a49ca
DJ		 18010 sym_type = ARM_MAP_THUMB;
18011 break;
18012
18013 case DATA_TYPE:
18014 sym_type = ARM_MAP_DATA;
18015 break;
18016
18017 default:
18018 BFD_FAIL ();
4e31c731 18019 return FALSE;
461a49ca
DJ		 18020 }
18021
d3ce72d0 18022 if (template_sequence[i].type != prev_type)
461a49ca 18023 {
d3ce72d0 18024 prev_type = template_sequence[i].type;
461a49ca
DJ		 18025 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
18026 return FALSE;
18027 }
18028
d3ce72d0 18029 switch (template_sequence[i].type)
461a49ca
DJ		 18030 {
18031 case ARM_TYPE:
48229727 18032 case THUMB32_TYPE:
461a49ca
DJ		 18033 size += 4;
18034 break;
18035
18036 case THUMB16_TYPE:
18037 size += 2;
18038 break;
18039
18040 case DATA_TYPE:
18041 size += 4;
18042 break;
18043
18044 default:
18045 BFD_FAIL ();
4e31c731 18046 return FALSE;
461a49ca
DJ		 18047 }
18048 }
18049
da5938a2
NC		 18050 return TRUE;
18051}
18052
33811162
DG		 18053/* Output mapping symbols for linker generated sections,
18054 and for those data-only sections that do not have a
18055 $d. */
4e617b1e
PB		 18056
18057static bfd_boolean
18058elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 18059 struct bfd_link_info *info,
57402f1e 18060 void *flaginfo,
6e0b88f1
AM		 18061 int (*func) (void *, const char *,
18062 Elf_Internal_Sym *,
18063 asection *,
18064 struct elf_link_hash_entry *))
4e617b1e
PB		 18065{
18066 output_arch_syminfo osi;
18067 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 18068 bfd_vma offset;
18069 bfd_size_type size;
33811162 18070 bfd *input_bfd;
4e617b1e
PB		 18071
18072 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 18073 if (htab == NULL)
18074 return FALSE;
18075
906e58ca 18076 check_use_blx (htab);
91a5743d 18077
57402f1e 18078 osi.flaginfo = flaginfo;
4e617b1e
PB		 18079 osi.info = info;
18080 osi.func = func;
906e58ca 18081
33811162
DG		 18082 /* Add a $d mapping symbol to data-only sections that
18083 don't have any mapping symbol. This may result in (harmless) redundant
18084 mapping symbols. */
18085 for (input_bfd = info->input_bfds;
18086 input_bfd != NULL;
c72f2fb2 18087 input_bfd = input_bfd->link.next)
33811162
DG		 18088 {
18089 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18090 for (osi.sec = input_bfd->sections;
18091 osi.sec != NULL;
18092 osi.sec = osi.sec->next)
18093 {
18094 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 18095 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18096 != 0)
33811162
DG		 18097 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18098 == SEC_HAS_CONTENTS
18099 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 18100 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 18101 && osi.sec->size > 0
18102 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 18103 {
18104 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18105 (output_bfd, osi.sec->output_section);
18106 if (osi.sec_shndx != (int)SHN_BAD)
18107 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18108 }
18109 }
18110 }
18111
91a5743d
PB		 18112 /* ARM->Thumb glue. */
18113 if (htab->arm_glue_size > 0)
18114 {
3d4d4302
AM		 18115 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18116 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 18117
18118 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18119 (output_bfd, osi.sec->output_section);
0e1862bb 18120 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 18121 || htab->pic_veneer)
18122 size = ARM2THUMB_PIC_GLUE_SIZE;
18123 else if (htab->use_blx)
18124 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18125 else
18126 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 18127
91a5743d
PB		 18128 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18129 {
7413f23f
DJ		 18130 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18131 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 18132 }
18133 }
18134
18135 /* Thumb->ARM glue. */
18136 if (htab->thumb_glue_size > 0)
18137 {
3d4d4302
AM		 18138 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18139 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 18140
18141 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18142 (output_bfd, osi.sec->output_section);
18143 size = THUMB2ARM_GLUE_SIZE;
18144
18145 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18146 {
7413f23f
DJ		 18147 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18148 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 18149 }
18150 }
18151
845b51d6
PB		 18152 /* ARMv4 BX veneers. */
18153 if (htab->bx_glue_size > 0)
18154 {
3d4d4302
AM		 18155 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18156 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 18157
18158 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18159 (output_bfd, osi.sec->output_section);
18160
7413f23f 18161 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 18162 }
18163
8029a119
NC		 18164 /* Long calls stubs. */
18165 if (htab->stub_bfd && htab->stub_bfd->sections)
18166 {
da5938a2 18167 asection* stub_sec;
8029a119 18168
da5938a2
NC		 18169 for (stub_sec = htab->stub_bfd->sections;
18170 stub_sec != NULL;
8029a119
NC		 18171 stub_sec = stub_sec->next)
18172 {
18173 /* Ignore non-stub sections. */
18174 if (!strstr (stub_sec->name, STUB_SUFFIX))
18175 continue;
da5938a2 18176
8029a119 18177 osi.sec = stub_sec;
da5938a2 18178
8029a119
NC		 18179 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18180 (output_bfd, osi.sec->output_section);
da5938a2 18181
8029a119
NC		 18182 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18183 }
18184 }
da5938a2 18185
91a5743d 18186 /* Finally, output mapping symbols for the PLT. */
34e77a92 18187 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 18188 {
34e77a92
RS		 18189 osi.sec = htab->root.splt;
18190 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18191 (output_bfd, osi.sec->output_section));
18192
18193 /* Output mapping symbols for the plt header. SymbianOS does not have a
18194 plt header. */
18195 if (htab->vxworks_p)
18196 {
18197 /* VxWorks shared libraries have no PLT header. */
0e1862bb 18198 if (!bfd_link_pic (info))
34e77a92
RS		 18199 {
18200 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18201 return FALSE;
18202 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18203 return FALSE;
18204 }
18205 }
b38cadfb
NC		 18206 else if (htab->nacl_p)
18207 {
18208 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18209 return FALSE;
18210 }
59029f57 18211 else if (using_thumb_only (htab) && !htab->fdpic_p)
eed94f8f
NC		 18212 {
18213 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18214 return FALSE;
18215 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18216 return FALSE;
18217 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18218 return FALSE;
18219 }
e8b09b87 18220 else if (!htab->symbian_p && !htab->fdpic_p)
4e617b1e 18221 {
7413f23f 18222 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 18223 return FALSE;
34e77a92
RS		 18224#ifndef FOUR_WORD_PLT
18225 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 18226 return FALSE;
34e77a92 18227#endif
4e617b1e
PB		 18228 }
18229 }
99059e56
RM		 18230 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
18231 {
18232 /* NaCl uses a special first entry in .iplt too. */
18233 osi.sec = htab->root.iplt;
18234 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18235 (output_bfd, osi.sec->output_section));
18236 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18237 return FALSE;
18238 }
34e77a92
RS		 18239 if ((htab->root.splt && htab->root.splt->size > 0)
18240 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 18241 {
34e77a92
RS		 18242 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18243 for (input_bfd = info->input_bfds;
18244 input_bfd != NULL;
c72f2fb2 18245 input_bfd = input_bfd->link.next)
34e77a92
RS		 18246 {
18247 struct arm_local_iplt_info **local_iplt;
18248 unsigned int i, num_syms;
4e617b1e 18249
34e77a92
RS		 18250 local_iplt = elf32_arm_local_iplt (input_bfd);
18251 if (local_iplt != NULL)
18252 {
18253 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18254 for (i = 0; i < num_syms; i++)
18255 if (local_iplt[i] != NULL
18256 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
18257 &local_iplt[i]->root,
18258 &local_iplt[i]->arm))
18259 return FALSE;
18260 }
18261 }
18262 }
0855e32b
NS		 18263 if (htab->dt_tlsdesc_plt != 0)
18264 {
18265 /* Mapping symbols for the lazy tls trampoline. */
18266 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
18267 return FALSE;
b38cadfb 18268
0855e32b
NS		 18269 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18270 htab->dt_tlsdesc_plt + 24))
18271 return FALSE;
18272 }
18273 if (htab->tls_trampoline != 0)
18274 {
18275 /* Mapping symbols for the tls trampoline. */
18276 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18277 return FALSE;
18278#ifdef FOUR_WORD_PLT
18279 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18280 htab->tls_trampoline + 12))
18281 return FALSE;
b38cadfb 18282#endif
0855e32b 18283 }
b38cadfb 18284
4e617b1e
PB		 18285 return TRUE;
18286}
18287
54ddd295
TP		 18288/* Filter normal symbols of CMSE entry functions of ABFD to include in
18289 the import library. All SYMCOUNT symbols of ABFD can be examined
18290 from their pointers in SYMS. Pointers of symbols to keep should be
18291 stored continuously at the beginning of that array.
18292
18293 Returns the number of symbols to keep. */
18294
18295static unsigned int
18296elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18297 struct bfd_link_info *info,
18298 asymbol **syms, long symcount)
18299{
18300 size_t maxnamelen;
18301 char *cmse_name;
18302 long src_count, dst_count = 0;
18303 struct elf32_arm_link_hash_table *htab;
18304
18305 htab = elf32_arm_hash_table (info);
18306 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18307 symcount = 0;
18308
18309 maxnamelen = 128;
18310 cmse_name = (char *) bfd_malloc (maxnamelen);
18311 for (src_count = 0; src_count < symcount; src_count++)
18312 {
18313 struct elf32_arm_link_hash_entry *cmse_hash;
18314 asymbol *sym;
18315 flagword flags;
18316 char *name;
18317 size_t namelen;
18318
18319 sym = syms[src_count];
18320 flags = sym->flags;
18321 name = (char *) bfd_asymbol_name (sym);
18322
18323 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18324 continue;
18325 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18326 continue;
18327
18328 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18329 if (namelen > maxnamelen)
18330 {
18331 cmse_name = (char *)
18332 bfd_realloc (cmse_name, namelen);
18333 maxnamelen = namelen;
18334 }
18335 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18336 cmse_hash = (struct elf32_arm_link_hash_entry *)
18337 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
18338
18339 if (!cmse_hash
18340 || (cmse_hash->root.root.type != bfd_link_hash_defined
18341 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18342 || cmse_hash->root.type != STT_FUNC)
18343 continue;
18344
18345 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
18346 continue;
18347
18348 syms[dst_count++] = sym;
18349 }
18350 free (cmse_name);
18351
18352 syms[dst_count] = NULL;
18353
18354 return dst_count;
18355}
18356
18357/* Filter symbols of ABFD to include in the import library. All
18358 SYMCOUNT symbols of ABFD can be examined from their pointers in
18359 SYMS. Pointers of symbols to keep should be stored continuously at
18360 the beginning of that array.
18361
18362 Returns the number of symbols to keep. */
18363
18364static unsigned int
18365elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18366 struct bfd_link_info *info,
18367 asymbol **syms, long symcount)
18368{
18369 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18370
046734ff
TP		 18371 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18372 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18373 library to be a relocatable object file. */
18374 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 18375 if (globals->cmse_implib)
18376 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18377 else
18378 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18379}
18380
e489d0ae
PB		 18381/* Allocate target specific section data. */
18382
18383static bfd_boolean
18384elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18385{
f592407e
AM		 18386 if (!sec->used_by_bfd)
18387 {
18388 _arm_elf_section_data *sdata;
18389 bfd_size_type amt = sizeof (*sdata);
e489d0ae 18390
21d799b5 18391 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 18392 if (sdata == NULL)
18393 return FALSE;
18394 sec->used_by_bfd = sdata;
18395 }
e489d0ae
PB		 18396
18397 return _bfd_elf_new_section_hook (abfd, sec);
18398}
18399
18400
18401/* Used to order a list of mapping symbols by address. */
18402
18403static int
18404elf32_arm_compare_mapping (const void * a, const void * b)
18405{
7f6a71ff
JM		 18406 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18407 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18408
18409 if (amap->vma > bmap->vma)
18410 return 1;
18411 else if (amap->vma < bmap->vma)
18412 return -1;
18413 else if (amap->type > bmap->type)
18414 /* Ensure results do not depend on the host qsort for objects with
18415 multiple mapping symbols at the same address by sorting on type
18416 after vma. */
18417 return 1;
18418 else if (amap->type < bmap->type)
18419 return -1;
18420 else
18421 return 0;
e489d0ae
PB		 18422}
18423
2468f9c9
PB		 18424/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18425
18426static unsigned long
18427offset_prel31 (unsigned long addr, bfd_vma offset)
18428{
18429 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18430}
18431
18432/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18433 relocations. */
18434
18435static void
18436copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18437{
18438 unsigned long first_word = bfd_get_32 (output_bfd, from);
18439 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 18440
2468f9c9
PB		 18441 /* High bit of first word is supposed to be zero. */
18442 if ((first_word & 0x80000000ul) == 0)
18443 first_word = offset_prel31 (first_word, offset);
b38cadfb 18444
2468f9c9
PB		 18445 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18446 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18447 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18448 second_word = offset_prel31 (second_word, offset);
b38cadfb 18449
2468f9c9
PB		 18450 bfd_put_32 (output_bfd, first_word, to);
18451 bfd_put_32 (output_bfd, second_word, to + 4);
18452}
e489d0ae 18453
48229727
JB		 18454/* Data for make_branch_to_a8_stub(). */
18455
b38cadfb
NC		 18456struct a8_branch_to_stub_data
18457{
48229727
JB		 18458 asection *writing_section;
18459 bfd_byte *contents;
18460};
18461
18462
18463/* Helper to insert branches to Cortex-A8 erratum stubs in the right
18464 places for a particular section. */
18465
18466static bfd_boolean
18467make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 18468 void *in_arg)
48229727
JB		 18469{
18470 struct elf32_arm_stub_hash_entry *stub_entry;
18471 struct a8_branch_to_stub_data *data;
18472 bfd_byte *contents;
18473 unsigned long branch_insn;
18474 bfd_vma veneered_insn_loc, veneer_entry_loc;
18475 bfd_signed_vma branch_offset;
18476 bfd *abfd;
8d9d9490 18477 unsigned int loc;
48229727
JB		 18478
18479 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18480 data = (struct a8_branch_to_stub_data *) in_arg;
18481
18482 if (stub_entry->target_section != data->writing_section
4563a860 18483 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 18484 return TRUE;
18485
18486 contents = data->contents;
18487
8d9d9490
TP		 18488 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18489 generated when both source and target are in the same section. */
48229727
JB		 18490 veneered_insn_loc = stub_entry->target_section->output_section->vma
18491 + stub_entry->target_section->output_offset
8d9d9490 18492 + stub_entry->source_value;
48229727
JB		 18493
18494 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18495 + stub_entry->stub_sec->output_offset
18496 + stub_entry->stub_offset;
18497
18498 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18499 veneered_insn_loc &= ~3u;
18500
18501 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18502
18503 abfd = stub_entry->target_section->owner;
8d9d9490 18504 loc = stub_entry->source_value;
48229727
JB		 18505
18506 /* We attempt to avoid this condition by setting stubs_always_after_branch
18507 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18508 This check is just to be on the safe side... */
18509 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18510 {
871b3ab2 18511 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 18512 "allocated in unsafe location"), abfd);
48229727
JB		 18513 return FALSE;
18514 }
18515
18516 switch (stub_entry->stub_type)
18517 {
18518 case arm_stub_a8_veneer_b:
18519 case arm_stub_a8_veneer_b_cond:
18520 branch_insn = 0xf0009000;
18521 goto jump24;
18522
18523 case arm_stub_a8_veneer_blx:
18524 branch_insn = 0xf000e800;
18525 goto jump24;
18526
18527 case arm_stub_a8_veneer_bl:
18528 {
18529 unsigned int i1, j1, i2, j2, s;
18530
18531 branch_insn = 0xf000d000;
18532
18533 jump24:
18534 if (branch_offset < -16777216 || branch_offset > 16777214)
18535 {
18536 /* There's not much we can do apart from complain if this
18537 happens. */
871b3ab2 18538 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 18539 "of range (input file too large)"), abfd);
48229727
JB		 18540 return FALSE;
18541 }
18542
18543 /* i1 = not(j1 eor s), so:
18544 not i1 = j1 eor s
18545 j1 = (not i1) eor s. */
18546
18547 branch_insn |= (branch_offset >> 1) & 0x7ff;
18548 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18549 i2 = (branch_offset >> 22) & 1;
18550 i1 = (branch_offset >> 23) & 1;
18551 s = (branch_offset >> 24) & 1;
18552 j1 = (!i1) ^ s;
18553 j2 = (!i2) ^ s;
18554 branch_insn |= j2 << 11;
18555 branch_insn |= j1 << 13;
18556 branch_insn |= s << 26;
18557 }
18558 break;
18559
18560 default:
18561 BFD_FAIL ();
18562 return FALSE;
18563 }
18564
8d9d9490
TP		 18565 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18566 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 18567
18568 return TRUE;
18569}
18570
a504d23a
LA		 18571/* Beginning of stm32l4xx work-around. */
18572
18573/* Functions encoding instructions necessary for the emission of the
18574 fix-stm32l4xx-629360.
18575 Encoding is extracted from the
18576 ARM (C) Architecture Reference Manual
18577 ARMv7-A and ARMv7-R edition
18578 ARM DDI 0406C.b (ID072512). */
18579
18580static inline bfd_vma
82188b29 18581create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 18582{
18583 /* A8.8.18 B (A8-334)
18584 B target_address (Encoding T4). */
18585 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18586 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18587 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18588
a504d23a
LA		 18589 int s = ((branch_offset & 0x1000000) >> 24);
18590 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18591 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18592
18593 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18594 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18595
18596 bfd_vma patched_inst = 0xf0009000
18597 | s << 26 /* S. */
18598 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18599 | j1 << 13 /* J1. */
18600 | j2 << 11 /* J2. */
18601 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18602
18603 return patched_inst;
18604}
18605
18606static inline bfd_vma
18607create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18608{
18609 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18610 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18611 bfd_vma patched_inst = 0xe8900000
18612 | (/*W=*/wback << 21)
18613 | (base_reg << 16)
18614 | (reg_mask & 0x0000ffff);
18615
18616 return patched_inst;
18617}
18618
18619static inline bfd_vma
18620create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18621{
18622 /* A8.8.60 LDMDB/LDMEA (A8-402)
18623 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18624 bfd_vma patched_inst = 0xe9100000
18625 | (/*W=*/wback << 21)
18626 | (base_reg << 16)
18627 | (reg_mask & 0x0000ffff);
18628
18629 return patched_inst;
18630}
18631
18632static inline bfd_vma
18633create_instruction_mov (int target_reg, int source_reg)
18634{
18635 /* A8.8.103 MOV (register) (A8-486)
18636 MOV Rd, Rm (Encoding T1). */
18637 bfd_vma patched_inst = 0x4600
18638 | (target_reg & 0x7)
18639 | ((target_reg & 0x8) >> 3) << 7
18640 | (source_reg << 3);
18641
18642 return patched_inst;
18643}
18644
18645static inline bfd_vma
18646create_instruction_sub (int target_reg, int source_reg, int value)
18647{
18648 /* A8.8.221 SUB (immediate) (A8-708)
18649 SUB Rd, Rn, #value (Encoding T3). */
18650 bfd_vma patched_inst = 0xf1a00000
18651 | (target_reg << 8)
18652 | (source_reg << 16)
18653 | (/*S=*/0 << 20)
18654 | ((value & 0x800) >> 11) << 26
18655 | ((value & 0x700) >> 8) << 12
18656 | (value & 0x0ff);
18657
18658 return patched_inst;
18659}
18660
18661static inline bfd_vma
9239bbd3 18662create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 18663 int first_reg)
18664{
18665 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18666 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18667 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 18668 | (/*W=*/wback << 21)
18669 | (base_reg << 16)
9239bbd3
CM		 18670 | (num_words & 0x000000ff)
18671 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 18672 | (first_reg & 0x00000001) << 22;
18673
18674 return patched_inst;
18675}
18676
18677static inline bfd_vma
9239bbd3
CM		 18678create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18679 int first_reg)
a504d23a
LA		 18680{
18681 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18682 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18683 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 18684 | (base_reg << 16)
9239bbd3
CM		 18685 | (num_words & 0x000000ff)
18686 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 18687 | (first_reg & 0x00000001) << 22;
18688
18689 return patched_inst;
18690}
18691
18692static inline bfd_vma
18693create_instruction_udf_w (int value)
18694{
18695 /* A8.8.247 UDF (A8-758)
18696 Undefined (Encoding T2). */
18697 bfd_vma patched_inst = 0xf7f0a000
18698 | (value & 0x00000fff)
18699 | (value & 0x000f0000) << 16;
18700
18701 return patched_inst;
18702}
18703
18704static inline bfd_vma
18705create_instruction_udf (int value)
18706{
18707 /* A8.8.247 UDF (A8-758)
18708 Undefined (Encoding T1). */
18709 bfd_vma patched_inst = 0xde00
18710 | (value & 0xff);
18711
18712 return patched_inst;
18713}
18714
18715/* Functions writing an instruction in memory, returning the next
18716 memory position to write to. */
18717
18718static inline bfd_byte *
18719push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18720 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18721{
18722 put_thumb2_insn (htab, output_bfd, insn, pt);
18723 return pt + 4;
18724}
18725
18726static inline bfd_byte *
18727push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
18728 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18729{
18730 put_thumb_insn (htab, output_bfd, insn, pt);
18731 return pt + 2;
18732}
18733
18734/* Function filling up a region in memory with T1 and T2 UDFs taking
18735 care of alignment. */
18736
18737static bfd_byte *
18738stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 18739 bfd * output_bfd,
18740 const bfd_byte * const base_stub_contents,
18741 bfd_byte * const from_stub_contents,
18742 const bfd_byte * const end_stub_contents)
a504d23a
LA		 18743{
18744 bfd_byte *current_stub_contents = from_stub_contents;
18745
18746 /* Fill the remaining of the stub with deterministic contents : UDF
18747 instructions.
18748 Check if realignment is needed on modulo 4 frontier using T1, to
18749 further use T2. */
18750 if ((current_stub_contents < end_stub_contents)
18751 && !((current_stub_contents - base_stub_contents) % 2)
18752 && ((current_stub_contents - base_stub_contents) % 4))
18753 current_stub_contents =
18754 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18755 create_instruction_udf (0));
18756
18757 for (; current_stub_contents < end_stub_contents;)
18758 current_stub_contents =
18759 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18760 create_instruction_udf_w (0));
18761
18762 return current_stub_contents;
18763}
18764
18765/* Functions writing the stream of instructions equivalent to the
18766 derived sequence for ldmia, ldmdb, vldm respectively. */
18767
18768static void
18769stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
18770 bfd * output_bfd,
18771 const insn32 initial_insn,
18772 const bfd_byte *const initial_insn_addr,
18773 bfd_byte *const base_stub_contents)
18774{
18775 int wback = (initial_insn & 0x00200000) >> 21;
18776 int ri, rn = (initial_insn & 0x000F0000) >> 16;
18777 int insn_all_registers = initial_insn & 0x0000ffff;
18778 int insn_low_registers, insn_high_registers;
18779 int usable_register_mask;
b25e998d 18780 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18781 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18782 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
18783 bfd_byte *current_stub_contents = base_stub_contents;
18784
18785 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
18786
18787 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18788 smaller than 8 registers load sequences that do not cause the
18789 hardware issue. */
18790 if (nb_registers <= 8)
18791 {
18792 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18793 current_stub_contents =
18794 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18795 initial_insn);
18796
18797 /* B initial_insn_addr+4. */
18798 if (!restore_pc)
18799 current_stub_contents =
18800 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18801 create_instruction_branch_absolute
82188b29 18802 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18803
18804 /* Fill the remaining of the stub with deterministic contents. */
18805 current_stub_contents =
18806 stm32l4xx_fill_stub_udf (htab, output_bfd,
18807 base_stub_contents, current_stub_contents,
18808 base_stub_contents +
18809 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18810
18811 return;
18812 }
18813
18814 /* - reg_list[13] == 0. */
18815 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
18816
18817 /* - reg_list[14] & reg_list[15] != 1. */
18818 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18819
18820 /* - if (wback==1) reg_list[rn] == 0. */
18821 BFD_ASSERT (!wback || !restore_rn);
18822
18823 /* - nb_registers > 8. */
b25e998d 18824 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 18825
18826 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18827
18828 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
18829 - One with the 7 lowest registers (register mask 0x007F)
18830 This LDM will finally contain between 2 and 7 registers
18831 - One with the 7 highest registers (register mask 0xDF80)
18832 This ldm will finally contain between 2 and 7 registers. */
18833 insn_low_registers = insn_all_registers & 0x007F;
18834 insn_high_registers = insn_all_registers & 0xDF80;
18835
18836 /* A spare register may be needed during this veneer to temporarily
18837 handle the base register. This register will be restored with the
18838 last LDM operation.
18839 The usable register may be any general purpose register (that
18840 excludes PC, SP, LR : register mask is 0x1FFF). */
18841 usable_register_mask = 0x1FFF;
18842
18843 /* Generate the stub function. */
18844 if (wback)
18845 {
18846 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
18847 current_stub_contents =
18848 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18849 create_instruction_ldmia
18850 (rn, /*wback=*/1, insn_low_registers));
18851
18852 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
18853 current_stub_contents =
18854 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18855 create_instruction_ldmia
18856 (rn, /*wback=*/1, insn_high_registers));
18857 if (!restore_pc)
18858 {
18859 /* B initial_insn_addr+4. */
18860 current_stub_contents =
18861 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18862 create_instruction_branch_absolute
82188b29 18863 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18864 }
18865 }
18866 else /* if (!wback). */
18867 {
18868 ri = rn;
18869
18870 /* If Rn is not part of the high-register-list, move it there. */
18871 if (!(insn_high_registers & (1 << rn)))
18872 {
18873 /* Choose a Ri in the high-register-list that will be restored. */
18874 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18875
18876 /* MOV Ri, Rn. */
18877 current_stub_contents =
18878 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18879 create_instruction_mov (ri, rn));
18880 }
18881
18882 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18883 current_stub_contents =
18884 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18885 create_instruction_ldmia
18886 (ri, /*wback=*/1, insn_low_registers));
18887
18888 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18889 current_stub_contents =
18890 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18891 create_instruction_ldmia
18892 (ri, /*wback=*/0, insn_high_registers));
18893
18894 if (!restore_pc)
18895 {
18896 /* B initial_insn_addr+4. */
18897 current_stub_contents =
18898 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18899 create_instruction_branch_absolute
82188b29 18900 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18901 }
18902 }
18903
18904 /* Fill the remaining of the stub with deterministic contents. */
18905 current_stub_contents =
18906 stm32l4xx_fill_stub_udf (htab, output_bfd,
18907 base_stub_contents, current_stub_contents,
18908 base_stub_contents +
18909 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18910}
18911
18912static void
18913stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
18914 bfd * output_bfd,
18915 const insn32 initial_insn,
18916 const bfd_byte *const initial_insn_addr,
18917 bfd_byte *const base_stub_contents)
18918{
18919 int wback = (initial_insn & 0x00200000) >> 21;
18920 int ri, rn = (initial_insn & 0x000f0000) >> 16;
18921 int insn_all_registers = initial_insn & 0x0000ffff;
18922 int insn_low_registers, insn_high_registers;
18923 int usable_register_mask;
18924 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18925 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 18926 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18927 bfd_byte *current_stub_contents = base_stub_contents;
18928
18929 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
18930
18931 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18932 smaller than 8 registers load sequences that do not cause the
18933 hardware issue. */
18934 if (nb_registers <= 8)
18935 {
18936 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18937 current_stub_contents =
18938 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18939 initial_insn);
18940
18941 /* B initial_insn_addr+4. */
18942 current_stub_contents =
18943 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18944 create_instruction_branch_absolute
82188b29 18945 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18946
18947 /* Fill the remaining of the stub with deterministic contents. */
18948 current_stub_contents =
18949 stm32l4xx_fill_stub_udf (htab, output_bfd,
18950 base_stub_contents, current_stub_contents,
18951 base_stub_contents +
18952 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18953
18954 return;
18955 }
18956
18957 /* - reg_list[13] == 0. */
18958 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
18959
18960 /* - reg_list[14] & reg_list[15] != 1. */
18961 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18962
18963 /* - if (wback==1) reg_list[rn] == 0. */
18964 BFD_ASSERT (!wback || !restore_rn);
18965
18966 /* - nb_registers > 8. */
b25e998d 18967 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 18968
18969 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18970
18971 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
18972 - One with the 7 lowest registers (register mask 0x007F)
18973 This LDM will finally contain between 2 and 7 registers
18974 - One with the 7 highest registers (register mask 0xDF80)
18975 This ldm will finally contain between 2 and 7 registers. */
18976 insn_low_registers = insn_all_registers & 0x007F;
18977 insn_high_registers = insn_all_registers & 0xDF80;
18978
18979 /* A spare register may be needed during this veneer to temporarily
18980 handle the base register. This register will be restored with
18981 the last LDM operation.
18982 The usable register may be any general purpose register (that excludes
18983 PC, SP, LR : register mask is 0x1FFF). */
18984 usable_register_mask = 0x1FFF;
18985
18986 /* Generate the stub function. */
18987 if (!wback && !restore_pc && !restore_rn)
18988 {
18989 /* Choose a Ri in the low-register-list that will be restored. */
18990 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18991
18992 /* MOV Ri, Rn. */
18993 current_stub_contents =
18994 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18995 create_instruction_mov (ri, rn));
18996
18997 /* LDMDB Ri!, {R-high-register-list}. */
18998 current_stub_contents =
18999 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19000 create_instruction_ldmdb
19001 (ri, /*wback=*/1, insn_high_registers));
19002
19003 /* LDMDB Ri, {R-low-register-list}. */
19004 current_stub_contents =
19005 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19006 create_instruction_ldmdb
19007 (ri, /*wback=*/0, insn_low_registers));
19008
19009 /* B initial_insn_addr+4. */
19010 current_stub_contents =
19011 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19012 create_instruction_branch_absolute
82188b29 19013 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19014 }
19015 else if (wback && !restore_pc && !restore_rn)
19016 {
19017 /* LDMDB Rn!, {R-high-register-list}. */
19018 current_stub_contents =
19019 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19020 create_instruction_ldmdb
19021 (rn, /*wback=*/1, insn_high_registers));
19022
19023 /* LDMDB Rn!, {R-low-register-list}. */
19024 current_stub_contents =
19025 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19026 create_instruction_ldmdb
19027 (rn, /*wback=*/1, insn_low_registers));
19028
19029 /* B initial_insn_addr+4. */
19030 current_stub_contents =
19031 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19032 create_instruction_branch_absolute
82188b29 19033 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19034 }
19035 else if (!wback && restore_pc && !restore_rn)
19036 {
19037 /* Choose a Ri in the high-register-list that will be restored. */
19038 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19039
19040 /* SUB Ri, Rn, #(4*nb_registers). */
19041 current_stub_contents =
19042 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19043 create_instruction_sub (ri, rn, (4 * nb_registers)));
19044
19045 /* LDMIA Ri!, {R-low-register-list}. */
19046 current_stub_contents =
19047 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19048 create_instruction_ldmia
19049 (ri, /*wback=*/1, insn_low_registers));
19050
19051 /* LDMIA Ri, {R-high-register-list}. */
19052 current_stub_contents =
19053 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19054 create_instruction_ldmia
19055 (ri, /*wback=*/0, insn_high_registers));
19056 }
19057 else if (wback && restore_pc && !restore_rn)
19058 {
19059 /* Choose a Ri in the high-register-list that will be restored. */
19060 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19061
19062 /* SUB Rn, Rn, #(4*nb_registers) */
19063 current_stub_contents =
19064 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19065 create_instruction_sub (rn, rn, (4 * nb_registers)));
19066
19067 /* MOV Ri, Rn. */
19068 current_stub_contents =
19069 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19070 create_instruction_mov (ri, rn));
19071
19072 /* LDMIA Ri!, {R-low-register-list}. */
19073 current_stub_contents =
19074 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19075 create_instruction_ldmia
19076 (ri, /*wback=*/1, insn_low_registers));
19077
19078 /* LDMIA Ri, {R-high-register-list}. */
19079 current_stub_contents =
19080 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19081 create_instruction_ldmia
19082 (ri, /*wback=*/0, insn_high_registers));
19083 }
19084 else if (!wback && !restore_pc && restore_rn)
19085 {
19086 ri = rn;
19087 if (!(insn_low_registers & (1 << rn)))
19088 {
19089 /* Choose a Ri in the low-register-list that will be restored. */
19090 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19091
19092 /* MOV Ri, Rn. */
19093 current_stub_contents =
19094 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19095 create_instruction_mov (ri, rn));
19096 }
19097
19098 /* LDMDB Ri!, {R-high-register-list}. */
19099 current_stub_contents =
19100 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19101 create_instruction_ldmdb
19102 (ri, /*wback=*/1, insn_high_registers));
19103
19104 /* LDMDB Ri, {R-low-register-list}. */
19105 current_stub_contents =
19106 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19107 create_instruction_ldmdb
19108 (ri, /*wback=*/0, insn_low_registers));
19109
19110 /* B initial_insn_addr+4. */
19111 current_stub_contents =
19112 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19113 create_instruction_branch_absolute
82188b29 19114 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19115 }
19116 else if (!wback && restore_pc && restore_rn)
19117 {
19118 ri = rn;
19119 if (!(insn_high_registers & (1 << rn)))
19120 {
19121 /* Choose a Ri in the high-register-list that will be restored. */
19122 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19123 }
19124
19125 /* SUB Ri, Rn, #(4*nb_registers). */
19126 current_stub_contents =
19127 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19128 create_instruction_sub (ri, rn, (4 * nb_registers)));
19129
19130 /* LDMIA Ri!, {R-low-register-list}. */
19131 current_stub_contents =
19132 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19133 create_instruction_ldmia
19134 (ri, /*wback=*/1, insn_low_registers));
19135
19136 /* LDMIA Ri, {R-high-register-list}. */
19137 current_stub_contents =
19138 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19139 create_instruction_ldmia
19140 (ri, /*wback=*/0, insn_high_registers));
19141 }
19142 else if (wback && restore_rn)
19143 {
19144 /* The assembler should not have accepted to encode this. */
19145 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19146 "undefined behavior.\n");
19147 }
19148
19149 /* Fill the remaining of the stub with deterministic contents. */
19150 current_stub_contents =
19151 stm32l4xx_fill_stub_udf (htab, output_bfd,
19152 base_stub_contents, current_stub_contents,
19153 base_stub_contents +
19154 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19155
19156}
19157
19158static void
19159stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19160 bfd * output_bfd,
19161 const insn32 initial_insn,
19162 const bfd_byte *const initial_insn_addr,
19163 bfd_byte *const base_stub_contents)
19164{
9239bbd3 19165 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 19166 bfd_byte *current_stub_contents = base_stub_contents;
19167
19168 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19169
19170 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 19171 smaller than 8 words load sequences that do not cause the
a504d23a 19172 hardware issue. */
9239bbd3 19173 if (num_words <= 8)
a504d23a
LA		 19174 {
19175 /* Untouched instruction. */
19176 current_stub_contents =
19177 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19178 initial_insn);
19179
19180 /* B initial_insn_addr+4. */
19181 current_stub_contents =
19182 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19183 create_instruction_branch_absolute
82188b29 19184 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19185 }
19186 else
19187 {
9eaff861 19188 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 19189 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 19190 bfd_boolean is_ia_nobang = /* (IA without !). */
19191 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19192 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
19193 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19194 bfd_boolean is_db_bang = /* (DB with !). */
19195 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 19196 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 19197 /* d = UInt (Vd:D);. */
9239bbd3 19198 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 19199 | (((unsigned int)initial_insn << 9) >> 31);
19200
9239bbd3
CM		 19201 /* Compute the number of 8-words chunks needed to split. */
19202 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 19203 int chunk;
19204
19205 /* The test coverage has been done assuming the following
19206 hypothesis that exactly one of the previous is_ predicates is
19207 true. */
9239bbd3
CM		 19208 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19209 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 19210
9239bbd3 19211 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 19212 cases, then we emit the adjustments:
19213
19214 vldm rx, {...}
19215 -> vldm rx!, {8_words_or_less} for each needed 8_word
19216 -> sub rx, rx, #size (list)
19217
19218 vldm rx!, {...}
19219 -> vldm rx!, {8_words_or_less} for each needed 8_word
19220 This also handles vpop instruction (when rx is sp)
19221
19222 vldmd rx!, {...}
19223 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 19224 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 19225 {
9239bbd3
CM		 19226 bfd_vma new_insn = 0;
19227
a504d23a
LA		 19228 if (is_ia_nobang || is_ia_bang)
19229 {
9239bbd3
CM		 19230 new_insn = create_instruction_vldmia
19231 (base_reg,
19232 is_dp,
19233 /*wback= . */1,
19234 chunks - (chunk + 1) ?
19235 8 : num_words - chunk * 8,
19236 first_reg + chunk * 8);
a504d23a
LA		 19237 }
19238 else if (is_db_bang)
19239 {
9239bbd3
CM		 19240 new_insn = create_instruction_vldmdb
19241 (base_reg,
19242 is_dp,
19243 chunks - (chunk + 1) ?
19244 8 : num_words - chunk * 8,
19245 first_reg + chunk * 8);
a504d23a 19246 }
9239bbd3
CM		 19247
19248 if (new_insn)
19249 current_stub_contents =
19250 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19251 new_insn);
a504d23a
LA		 19252 }
19253
19254 /* Only this case requires the base register compensation
19255 subtract. */
19256 if (is_ia_nobang)
19257 {
19258 current_stub_contents =
19259 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19260 create_instruction_sub
9239bbd3 19261 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 19262 }
19263
19264 /* B initial_insn_addr+4. */
19265 current_stub_contents =
19266 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19267 create_instruction_branch_absolute
82188b29 19268 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19269 }
19270
19271 /* Fill the remaining of the stub with deterministic contents. */
19272 current_stub_contents =
19273 stm32l4xx_fill_stub_udf (htab, output_bfd,
19274 base_stub_contents, current_stub_contents,
19275 base_stub_contents +
19276 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19277}
19278
19279static void
19280stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19281 bfd * output_bfd,
19282 const insn32 wrong_insn,
19283 const bfd_byte *const wrong_insn_addr,
19284 bfd_byte *const stub_contents)
19285{
19286 if (is_thumb2_ldmia (wrong_insn))
19287 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19288 wrong_insn, wrong_insn_addr,
19289 stub_contents);
19290 else if (is_thumb2_ldmdb (wrong_insn))
19291 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19292 wrong_insn, wrong_insn_addr,
19293 stub_contents);
19294 else if (is_thumb2_vldm (wrong_insn))
19295 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19296 wrong_insn, wrong_insn_addr,
19297 stub_contents);
19298}
19299
19300/* End of stm32l4xx work-around. */
19301
19302
e489d0ae
PB		 19303/* Do code byteswapping. Return FALSE afterwards so that the section is
19304 written out as normal. */
19305
19306static bfd_boolean
c7b8f16e 19307elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 19308 struct bfd_link_info *link_info,
19309 asection *sec,
e489d0ae
PB		 19310 bfd_byte *contents)
19311{
48229727 19312 unsigned int mapcount, errcount;
8e3de13a 19313 _arm_elf_section_data *arm_data;
c7b8f16e 19314 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 19315 elf32_arm_section_map *map;
c7b8f16e 19316 elf32_vfp11_erratum_list *errnode;
a504d23a 19317 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 19318 bfd_vma ptr;
19319 bfd_vma end;
c7b8f16e 19320 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 19321 bfd_byte tmp;
48229727 19322 unsigned int i;
57e8b36a 19323
4dfe6ac6
NC		 19324 if (globals == NULL)
19325 return FALSE;
19326
8e3de13a
NC		 19327 /* If this section has not been allocated an _arm_elf_section_data
19328 structure then we cannot record anything. */
19329 arm_data = get_arm_elf_section_data (sec);
19330 if (arm_data == NULL)
19331 return FALSE;
19332
19333 mapcount = arm_data->mapcount;
19334 map = arm_data->map;
c7b8f16e
JB		 19335 errcount = arm_data->erratumcount;
19336
19337 if (errcount != 0)
19338 {
19339 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19340
19341 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 19342 errnode = errnode->next)
19343 {
19344 bfd_vma target = errnode->vma - offset;
19345
19346 switch (errnode->type)
19347 {
19348 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19349 {
19350 bfd_vma branch_to_veneer;
19351 /* Original condition code of instruction, plus bit mask for
19352 ARM B instruction. */
19353 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19354 | 0x0a000000;
c7b8f16e
JB		 19355
19356 /* The instruction is before the label. */
91d6fa6a 19357 target -= 4;
c7b8f16e
JB		 19358
19359 /* Above offset included in -4 below. */
19360 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 19361 - errnode->vma - 4;
c7b8f16e
JB		 19362
19363 if ((signed) branch_to_veneer < -(1 << 25)
19364 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 19365 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19366 "range"), output_bfd);
c7b8f16e 19367
99059e56
RM		 19368 insn |= (branch_to_veneer >> 2) & 0xffffff;
19369 contents[endianflip ^ target] = insn & 0xff;
19370 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19371 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19372 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19373 }
19374 break;
c7b8f16e
JB		 19375
19376 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 19377 {
19378 bfd_vma branch_from_veneer;
19379 unsigned int insn;
c7b8f16e 19380
99059e56
RM		 19381 /* Take size of veneer into account. */
19382 branch_from_veneer = errnode->u.v.branch->vma
19383 - errnode->vma - 12;
c7b8f16e
JB		 19384
19385 if ((signed) branch_from_veneer < -(1 << 25)
19386 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 19387 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19388 "range"), output_bfd);
c7b8f16e 19389
99059e56
RM		 19390 /* Original instruction. */
19391 insn = errnode->u.v.branch->u.b.vfp_insn;
19392 contents[endianflip ^ target] = insn & 0xff;
19393 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19394 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19395 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19396
19397 /* Branch back to insn after original insn. */
19398 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19399 contents[endianflip ^ (target + 4)] = insn & 0xff;
19400 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19401 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19402 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19403 }
19404 break;
c7b8f16e 19405
99059e56
RM		 19406 default:
19407 abort ();
19408 }
19409 }
c7b8f16e 19410 }
e489d0ae 19411
a504d23a
LA		 19412 if (arm_data->stm32l4xx_erratumcount != 0)
19413 {
19414 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19415 stm32l4xx_errnode != 0;
19416 stm32l4xx_errnode = stm32l4xx_errnode->next)
19417 {
19418 bfd_vma target = stm32l4xx_errnode->vma - offset;
19419
19420 switch (stm32l4xx_errnode->type)
19421 {
19422 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19423 {
19424 unsigned int insn;
19425 bfd_vma branch_to_veneer =
19426 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19427
19428 if ((signed) branch_to_veneer < -(1 << 24)
19429 || (signed) branch_to_veneer >= (1 << 24))
19430 {
19431 bfd_vma out_of_range =
19432 ((signed) branch_to_veneer < -(1 << 24)) ?
19433 - branch_to_veneer - (1 << 24) :
19434 ((signed) branch_to_veneer >= (1 << 24)) ?
19435 branch_to_veneer - (1 << 24) : 0;
19436
4eca0228 19437 _bfd_error_handler
2dcf00ce 19438 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 19439 "cannot create STM32L4XX veneer; "
19440 "jump out of range by %" PRId64 " bytes; "
19441 "cannot encode branch instruction"),
a504d23a 19442 output_bfd,
2dcf00ce
AM		 19443 (uint64_t) (stm32l4xx_errnode->vma - 4),
19444 (int64_t) out_of_range);
a504d23a
LA		 19445 continue;
19446 }
19447
19448 insn = create_instruction_branch_absolute
82188b29 19449 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 19450
19451 /* The instruction is before the label. */
19452 target -= 4;
19453
19454 put_thumb2_insn (globals, output_bfd,
19455 (bfd_vma) insn, contents + target);
19456 }
19457 break;
19458
19459 case STM32L4XX_ERRATUM_VENEER:
19460 {
82188b29
NC		 19461 bfd_byte * veneer;
19462 bfd_byte * veneer_r;
a504d23a
LA		 19463 unsigned int insn;
19464
82188b29
NC		 19465 veneer = contents + target;
19466 veneer_r = veneer
19467 + stm32l4xx_errnode->u.b.veneer->vma
19468 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 19469
19470 if ((signed) (veneer_r - veneer -
19471 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19472 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19473 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19474 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19475 || (signed) (veneer_r - veneer) >= (1 << 24))
19476 {
90b6238f
AM		 19477 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19478 "veneer"), output_bfd);
a504d23a
LA		 19479 continue;
19480 }
19481
19482 /* Original instruction. */
19483 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19484
19485 stm32l4xx_create_replacing_stub
19486 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19487 }
19488 break;
19489
19490 default:
19491 abort ();
19492 }
19493 }
19494 }
19495
2468f9c9
PB		 19496 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19497 {
19498 arm_unwind_table_edit *edit_node
99059e56 19499 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 19500 /* Now, sec->size is the size of the section we will write. The original
99059e56 19501 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 19502 markers) was sec->rawsize. (This isn't the case if we perform no
19503 edits, then rawsize will be zero and we should use size). */
21d799b5 19504 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 19505 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19506 unsigned int in_index, out_index;
19507 bfd_vma add_to_offsets = 0;
19508
19509 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 19510 {
2468f9c9
PB		 19511 if (edit_node)
19512 {
19513 unsigned int edit_index = edit_node->index;
b38cadfb 19514
2468f9c9 19515 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 19516 {
2468f9c9
PB		 19517 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19518 contents + in_index * 8, add_to_offsets);
19519 out_index++;
19520 in_index++;
19521 }
19522 else if (in_index == edit_index
19523 || (in_index * 8 >= input_size
19524 && edit_index == UINT_MAX))
99059e56 19525 {
2468f9c9
PB		 19526 switch (edit_node->type)
19527 {
19528 case DELETE_EXIDX_ENTRY:
19529 in_index++;
19530 add_to_offsets += 8;
19531 break;
b38cadfb 19532
2468f9c9
PB		 19533 case INSERT_EXIDX_CANTUNWIND_AT_END:
19534 {
99059e56 19535 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 19536 bfd_vma text_offset = text_sec->output_section->vma
19537 + text_sec->output_offset
19538 + text_sec->size;
19539 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 19540 unsigned long prel31_offset;
2468f9c9
PB		 19541
19542 /* Note: this is meant to be equivalent to an
19543 R_ARM_PREL31 relocation. These synthetic
19544 EXIDX_CANTUNWIND markers are not relocated by the
19545 usual BFD method. */
19546 prel31_offset = (text_offset - exidx_offset)
19547 & 0x7ffffffful;
491d01d3
YU		 19548 if (bfd_link_relocatable (link_info))
19549 {
19550 /* Here relocation for new EXIDX_CANTUNWIND is
19551 created, so there is no need to
19552 adjust offset by hand. */
19553 prel31_offset = text_sec->output_offset
19554 + text_sec->size;
491d01d3 19555 }
2468f9c9
PB		 19556
19557 /* First address we can't unwind. */
19558 bfd_put_32 (output_bfd, prel31_offset,
19559 &edited_contents[out_index * 8]);
19560
19561 /* Code for EXIDX_CANTUNWIND. */
19562 bfd_put_32 (output_bfd, 0x1,
19563 &edited_contents[out_index * 8 + 4]);
19564
19565 out_index++;
19566 add_to_offsets -= 8;
19567 }
19568 break;
19569 }
b38cadfb 19570
2468f9c9
PB		 19571 edit_node = edit_node->next;
19572 }
19573 }
19574 else
19575 {
19576 /* No more edits, copy remaining entries verbatim. */
19577 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19578 contents + in_index * 8, add_to_offsets);
19579 out_index++;
19580 in_index++;
19581 }
19582 }
19583
19584 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19585 bfd_set_section_contents (output_bfd, sec->output_section,
19586 edited_contents,
19587 (file_ptr) sec->output_offset, sec->size);
19588
19589 return TRUE;
19590 }
19591
48229727
JB		 19592 /* Fix code to point to Cortex-A8 erratum stubs. */
19593 if (globals->fix_cortex_a8)
19594 {
19595 struct a8_branch_to_stub_data data;
19596
19597 data.writing_section = sec;
19598 data.contents = contents;
19599
a504d23a
LA		 19600 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19601 & data);
48229727
JB		 19602 }
19603
e489d0ae
PB		 19604 if (mapcount == 0)
19605 return FALSE;
19606
c7b8f16e 19607 if (globals->byteswap_code)
e489d0ae 19608 {
c7b8f16e 19609 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 19610
c7b8f16e
JB		 19611 ptr = map[0].vma;
19612 for (i = 0; i < mapcount; i++)
99059e56
RM		 19613 {
19614 if (i == mapcount - 1)
c7b8f16e 19615 end = sec->size;
99059e56
RM		 19616 else
19617 end = map[i + 1].vma;
e489d0ae 19618
99059e56 19619 switch (map[i].type)
e489d0ae 19620 {
c7b8f16e
JB		 19621 case 'a':
19622 /* Byte swap code words. */
19623 while (ptr + 3 < end)
99059e56
RM		 19624 {
19625 tmp = contents[ptr];
19626 contents[ptr] = contents[ptr + 3];
19627 contents[ptr + 3] = tmp;
19628 tmp = contents[ptr + 1];
19629 contents[ptr + 1] = contents[ptr + 2];
19630 contents[ptr + 2] = tmp;
19631 ptr += 4;
19632 }
c7b8f16e 19633 break;
e489d0ae 19634
c7b8f16e
JB		 19635 case 't':
19636 /* Byte swap code halfwords. */
19637 while (ptr + 1 < end)
99059e56
RM		 19638 {
19639 tmp = contents[ptr];
19640 contents[ptr] = contents[ptr + 1];
19641 contents[ptr + 1] = tmp;
19642 ptr += 2;
19643 }
c7b8f16e
JB		 19644 break;
19645
19646 case 'd':
19647 /* Leave data alone. */
19648 break;
19649 }
99059e56
RM		 19650 ptr = end;
19651 }
e489d0ae 19652 }
8e3de13a 19653
93204d3a 19654 free (map);
47b2e99c 19655 arm_data->mapcount = -1;
c7b8f16e 19656 arm_data->mapsize = 0;
8e3de13a 19657 arm_data->map = NULL;
8e3de13a 19658
e489d0ae
PB		 19659 return FALSE;
19660}
19661
0beaef2b
PB		 19662/* Mangle thumb function symbols as we read them in. */
19663
8384fb8f 19664static bfd_boolean
0beaef2b
PB		 19665elf32_arm_swap_symbol_in (bfd * abfd,
19666 const void *psrc,
19667 const void *pshn,
19668 Elf_Internal_Sym *dst)
19669{
4ba2ef8f
TP		 19670 Elf_Internal_Shdr *symtab_hdr;
19671 const char *name = NULL;
19672
8384fb8f
AM		 19673 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19674 return FALSE;
39d911fc 19675 dst->st_target_internal = 0;
0beaef2b
PB		 19676
19677 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 19678 the address. */
63e1a0fc
PB		 19679 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19680 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 19681 {
63e1a0fc
PB		 19682 if (dst->st_value & 1)
19683 {
19684 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 19685 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19686 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 19687 }
19688 else
39d911fc 19689 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 19690 }
19691 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19692 {
19693 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 19694 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 19695 }
35fc36a8 19696 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 19697 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 19698 else
39d911fc 19699 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 19700
4ba2ef8f
TP		 19701 /* Mark CMSE special symbols. */
19702 symtab_hdr = & elf_symtab_hdr (abfd);
19703 if (symtab_hdr->sh_size)
19704 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
19705 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
19706 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
19707
8384fb8f 19708 return TRUE;
0beaef2b
PB		 19709}
19710
19711
19712/* Mangle thumb function symbols as we write them out. */
19713
19714static void
19715elf32_arm_swap_symbol_out (bfd *abfd,
19716 const Elf_Internal_Sym *src,
19717 void *cdst,
19718 void *shndx)
19719{
19720 Elf_Internal_Sym newsym;
19721
19722 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19723 of the address set, as per the new EABI. We do this unconditionally
19724 because objcopy does not set the elf header flags until after
19725 it writes out the symbol table. */
39d911fc 19726 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 19727 {
19728 newsym = *src;
34e77a92
RS		 19729 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19730 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 19731 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 19732 {
19733 /* Do this only for defined symbols. At link type, the static
19734 linker will simulate the work of dynamic linker of resolving
19735 symbols and will carry over the thumbness of found symbols to
19736 the output symbol table. It's not clear how it happens, but
19737 the thumbness of undefined symbols can well be different at
19738 runtime, and writing '1' for them will be confusing for users
19739 and possibly for dynamic linker itself.
19740 */
19741 newsym.st_value |= 1;
19742 }
906e58ca 19743
0beaef2b
PB		 19744 src = &newsym;
19745 }
19746 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
19747}
19748
b294bdf8
MM		 19749/* Add the PT_ARM_EXIDX program header. */
19750
19751static bfd_boolean
906e58ca 19752elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 19753 struct bfd_link_info *info ATTRIBUTE_UNUSED)
19754{
19755 struct elf_segment_map *m;
19756 asection *sec;
19757
19758 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19759 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19760 {
19761 /* If there is already a PT_ARM_EXIDX header, then we do not
19762 want to add another one. This situation arises when running
19763 "strip"; the input binary already has the header. */
12bd6957 19764 m = elf_seg_map (abfd);
b294bdf8
MM		 19765 while (m && m->p_type != PT_ARM_EXIDX)
19766 m = m->next;
19767 if (!m)
19768 {
21d799b5 19769 m = (struct elf_segment_map *)
99059e56 19770 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 19771 if (m == NULL)
19772 return FALSE;
19773 m->p_type = PT_ARM_EXIDX;
19774 m->count = 1;
19775 m->sections[0] = sec;
19776
12bd6957
AM		 19777 m->next = elf_seg_map (abfd);
19778 elf_seg_map (abfd) = m;
b294bdf8
MM		 19779 }
19780 }
19781
19782 return TRUE;
19783}
19784
19785/* We may add a PT_ARM_EXIDX program header. */
19786
19787static int
a6b96beb
AM		 19788elf32_arm_additional_program_headers (bfd *abfd,
19789 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 19790{
19791 asection *sec;
19792
19793 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19794 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19795 return 1;
19796 else
19797 return 0;
19798}
19799
34e77a92
RS		 19800/* Hook called by the linker routine which adds symbols from an object
19801 file. */
19802
19803static bfd_boolean
19804elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
19805 Elf_Internal_Sym *sym, const char **namep,
19806 flagword *flagsp, asection **secp, bfd_vma *valp)
19807{
c792917c
NC		 19808 if (elf32_arm_hash_table (info) == NULL)
19809 return FALSE;
19810
34e77a92
RS		 19811 if (elf32_arm_hash_table (info)->vxworks_p
19812 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
19813 flagsp, secp, valp))
19814 return FALSE;
19815
19816 return TRUE;
19817}
19818
0beaef2b 19819/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 19820const struct elf_size_info elf32_arm_size_info =
19821{
0beaef2b
PB		 19822 sizeof (Elf32_External_Ehdr),
19823 sizeof (Elf32_External_Phdr),
19824 sizeof (Elf32_External_Shdr),
19825 sizeof (Elf32_External_Rel),
19826 sizeof (Elf32_External_Rela),
19827 sizeof (Elf32_External_Sym),
19828 sizeof (Elf32_External_Dyn),
19829 sizeof (Elf_External_Note),
19830 4,
19831 1,
19832 32, 2,
19833 ELFCLASS32, EV_CURRENT,
19834 bfd_elf32_write_out_phdrs,
19835 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 19836 bfd_elf32_checksum_contents,
0beaef2b
PB		 19837 bfd_elf32_write_relocs,
19838 elf32_arm_swap_symbol_in,
19839 elf32_arm_swap_symbol_out,
19840 bfd_elf32_slurp_reloc_table,
19841 bfd_elf32_slurp_symbol_table,
19842 bfd_elf32_swap_dyn_in,
19843 bfd_elf32_swap_dyn_out,
19844 bfd_elf32_swap_reloc_in,
19845 bfd_elf32_swap_reloc_out,
19846 bfd_elf32_swap_reloca_in,
19847 bfd_elf32_swap_reloca_out
19848};
19849
685e70ae
VK		 19850static bfd_vma
19851read_code32 (const bfd *abfd, const bfd_byte *addr)
19852{
19853 /* V7 BE8 code is always little endian. */
19854 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19855 return bfd_getl32 (addr);
19856
19857 return bfd_get_32 (abfd, addr);
19858}
19859
19860static bfd_vma
19861read_code16 (const bfd *abfd, const bfd_byte *addr)
19862{
19863 /* V7 BE8 code is always little endian. */
19864 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19865 return bfd_getl16 (addr);
19866
19867 return bfd_get_16 (abfd, addr);
19868}
19869
6a631e86
YG		 19870/* Return size of plt0 entry starting at ADDR
19871 or (bfd_vma) -1 if size can not be determined. */
19872
19873static bfd_vma
19874elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
19875{
19876 bfd_vma first_word;
19877 bfd_vma plt0_size;
19878
685e70ae 19879 first_word = read_code32 (abfd, addr);
6a631e86
YG		 19880
19881 if (first_word == elf32_arm_plt0_entry[0])
19882 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
19883 else if (first_word == elf32_thumb2_plt0_entry[0])
19884 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
19885 else
19886 /* We don't yet handle this PLT format. */
19887 return (bfd_vma) -1;
19888
19889 return plt0_size;
19890}
19891
19892/* Return size of plt entry starting at offset OFFSET
19893 of plt section located at address START
19894 or (bfd_vma) -1 if size can not be determined. */
19895
19896static bfd_vma
19897elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
19898{
19899 bfd_vma first_insn;
19900 bfd_vma plt_size = 0;
19901 const bfd_byte *addr = start + offset;
19902
19903 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 19904 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 19905 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
19906
19907 /* Respect Thumb stub if necessary. */
685e70ae 19908 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 19909 {
19910 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
19911 }
19912
19913 /* Strip immediate from first add. */
685e70ae 19914 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 19915
19916#ifdef FOUR_WORD_PLT
19917 if (first_insn == elf32_arm_plt_entry[0])
19918 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
19919#else
19920 if (first_insn == elf32_arm_plt_entry_long[0])
19921 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
19922 else if (first_insn == elf32_arm_plt_entry_short[0])
19923 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
19924#endif
19925 else
19926 /* We don't yet handle this PLT format. */
19927 return (bfd_vma) -1;
19928
19929 return plt_size;
19930}
19931
19932/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19933
19934static long
19935elf32_arm_get_synthetic_symtab (bfd *abfd,
19936 long symcount ATTRIBUTE_UNUSED,
19937 asymbol **syms ATTRIBUTE_UNUSED,
19938 long dynsymcount,
19939 asymbol **dynsyms,
19940 asymbol **ret)
19941{
19942 asection *relplt;
19943 asymbol *s;
19944 arelent *p;
19945 long count, i, n;
19946 size_t size;
19947 Elf_Internal_Shdr *hdr;
19948 char *names;
19949 asection *plt;
19950 bfd_vma offset;
19951 bfd_byte *data;
19952
19953 *ret = NULL;
19954
19955 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
19956 return 0;
19957
19958 if (dynsymcount <= 0)
19959 return 0;
19960
19961 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
19962 if (relplt == NULL)
19963 return 0;
19964
19965 hdr = &elf_section_data (relplt)->this_hdr;
19966 if (hdr->sh_link != elf_dynsymtab (abfd)
19967 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
19968 return 0;
19969
19970 plt = bfd_get_section_by_name (abfd, ".plt");
19971 if (plt == NULL)
19972 return 0;
19973
19974 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
19975 return -1;
19976
19977 data = plt->contents;
19978 if (data == NULL)
19979 {
19980 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
19981 return -1;
19982 bfd_cache_section_contents((asection *) plt, data);
19983 }
19984
19985 count = relplt->size / hdr->sh_entsize;
19986 size = count * sizeof (asymbol);
19987 p = relplt->relocation;
19988 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19989 {
19990 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
19991 if (p->addend != 0)
19992 size += sizeof ("+0x") - 1 + 8;
19993 }
19994
19995 s = *ret = (asymbol *) bfd_malloc (size);
19996 if (s == NULL)
19997 return -1;
19998
19999 offset = elf32_arm_plt0_size (abfd, data);
20000 if (offset == (bfd_vma) -1)
20001 return -1;
20002
20003 names = (char *) (s + count);
20004 p = relplt->relocation;
20005 n = 0;
20006 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20007 {
20008 size_t len;
20009
20010 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
20011 if (plt_size == (bfd_vma) -1)
20012 break;
20013
20014 *s = **p->sym_ptr_ptr;
20015 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20016 we are defining a symbol, ensure one of them is set. */
20017 if ((s->flags & BSF_LOCAL) == 0)
20018 s->flags |= BSF_GLOBAL;
20019 s->flags |= BSF_SYNTHETIC;
20020 s->section = plt;
20021 s->value = offset;
20022 s->name = names;
20023 s->udata.p = NULL;
20024 len = strlen ((*p->sym_ptr_ptr)->name);
20025 memcpy (names, (*p->sym_ptr_ptr)->name, len);
20026 names += len;
20027 if (p->addend != 0)
20028 {
20029 char buf[30], *a;
20030
20031 memcpy (names, "+0x", sizeof ("+0x") - 1);
20032 names += sizeof ("+0x") - 1;
20033 bfd_sprintf_vma (abfd, buf, p->addend);
20034 for (a = buf; *a == '0'; ++a)
20035 ;
20036 len = strlen (a);
20037 memcpy (names, a, len);
20038 names += len;
20039 }
20040 memcpy (names, "@plt", sizeof ("@plt"));
20041 names += sizeof ("@plt");
20042 ++s, ++n;
20043 offset += plt_size;
20044 }
20045
20046 return n;
20047}
20048
ac4c9b04
MG		 20049static bfd_boolean
20050elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
20051{
f0728ee3
AV		 20052 if (hdr->sh_flags & SHF_ARM_PURECODE)
20053 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 20054 return TRUE;
20055}
20056
20057static flagword
20058elf32_arm_lookup_section_flags (char *flag_name)
20059{
f0728ee3
AV		 20060 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
20061 return SHF_ARM_PURECODE;
ac4c9b04
MG		 20062
20063 return SEC_NO_FLAGS;
20064}
20065
491d01d3
YU		 20066static unsigned int
20067elf32_arm_count_additional_relocs (asection *sec)
20068{
20069 struct _arm_elf_section_data *arm_data;
20070 arm_data = get_arm_elf_section_data (sec);
5025eb7c 20071
6342be70 20072 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 20073}
20074
5522f910 20075/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 20076 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 20077 FALSE otherwise. ISECTION is the best guess matching section from the
20078 input bfd IBFD, but it might be NULL. */
20079
20080static bfd_boolean
20081elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20082 bfd *obfd ATTRIBUTE_UNUSED,
20083 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20084 Elf_Internal_Shdr *osection)
20085{
20086 switch (osection->sh_type)
20087 {
20088 case SHT_ARM_EXIDX:
20089 {
20090 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20091 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20092 unsigned i = 0;
20093
20094 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20095 osection->sh_info = 0;
20096
20097 /* The sh_link field must be set to the text section associated with
20098 this index section. Unfortunately the ARM EHABI does not specify
20099 exactly how to determine this association. Our caller does try
20100 to match up OSECTION with its corresponding input section however
20101 so that is a good first guess. */
20102 if (isection != NULL
20103 && osection->bfd_section != NULL
20104 && isection->bfd_section != NULL
20105 && isection->bfd_section->output_section != NULL
20106 && isection->bfd_section->output_section == osection->bfd_section
20107 && iheaders != NULL
20108 && isection->sh_link > 0
20109 && isection->sh_link < elf_numsections (ibfd)
20110 && iheaders[isection->sh_link]->bfd_section != NULL
20111 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20112 )
20113 {
20114 for (i = elf_numsections (obfd); i-- > 0;)
20115 if (oheaders[i]->bfd_section
20116 == iheaders[isection->sh_link]->bfd_section->output_section)
20117 break;
20118 }
9eaff861 20119
5522f910
NC		 20120 if (i == 0)
20121 {
20122 /* Failing that we have to find a matching section ourselves. If
20123 we had the output section name available we could compare that
20124 with input section names. Unfortunately we don't. So instead
20125 we use a simple heuristic and look for the nearest executable
20126 section before this one. */
20127 for (i = elf_numsections (obfd); i-- > 0;)
20128 if (oheaders[i] == osection)
20129 break;
20130 if (i == 0)
20131 break;
20132
20133 while (i-- > 0)
20134 if (oheaders[i]->sh_type == SHT_PROGBITS
20135 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20136 == (SHF_ALLOC | SHF_EXECINSTR))
20137 break;
20138 }
20139
20140 if (i)
20141 {
20142 osection->sh_link = i;
20143 /* If the text section was part of a group
20144 then the index section should be too. */
20145 if (oheaders[i]->sh_flags & SHF_GROUP)
20146 osection->sh_flags |= SHF_GROUP;
20147 return TRUE;
20148 }
20149 }
20150 break;
20151
20152 case SHT_ARM_PREEMPTMAP:
20153 osection->sh_flags = SHF_ALLOC;
20154 break;
20155
20156 case SHT_ARM_ATTRIBUTES:
20157 case SHT_ARM_DEBUGOVERLAY:
20158 case SHT_ARM_OVERLAYSECTION:
20159 default:
20160 break;
20161 }
20162
20163 return FALSE;
20164}
20165
d691934d
NC		 20166/* Returns TRUE if NAME is an ARM mapping symbol.
20167 Traditionally the symbols $a, $d and $t have been used.
20168 The ARM ELF standard also defines $x (for A64 code). It also allows a
20169 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20170 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20171 not support them here. $t.x indicates the start of ThumbEE instructions. */
20172
20173static bfd_boolean
20174is_arm_mapping_symbol (const char * name)
20175{
20176 return name != NULL /* Paranoia. */
20177 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20178 the mapping symbols could have acquired a prefix.
20179 We do not support this here, since such symbols no
20180 longer conform to the ARM ELF ABI. */
20181 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20182 && (name[2] == 0 || name[2] == '.');
20183 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20184 any characters that follow the period are legal characters for the body
20185 of a symbol's name. For now we just assume that this is the case. */
20186}
20187
fca2a38f
NC		 20188/* Make sure that mapping symbols in object files are not removed via the
20189 "strip --strip-unneeded" tool. These symbols are needed in order to
20190 correctly generate interworking veneers, and for byte swapping code
20191 regions. Once an object file has been linked, it is safe to remove the
20192 symbols as they will no longer be needed. */
20193
20194static void
20195elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20196{
20197 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 20198 && sym->section != bfd_abs_section_ptr
d691934d 20199 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 20200 sym->flags |= BSF_KEEP;
20201}
20202
5522f910
NC		 20203#undef elf_backend_copy_special_section_fields
20204#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20205
252b5132 20206#define ELF_ARCH bfd_arch_arm
ae95ffa6 20207#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 20208#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 20209#ifdef __QNXTARGET__
20210#define ELF_MAXPAGESIZE 0x1000
20211#else
7572ca89 20212#define ELF_MAXPAGESIZE 0x10000
d0facd1b 20213#endif
b1342370 20214#define ELF_MINPAGESIZE 0x1000
24718e3b 20215#define ELF_COMMONPAGESIZE 0x1000
252b5132 20216
07d6d2b8 20217#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 20218
99e4ae17
AJ		 20219#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20220#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 20221#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20222#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 20223#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 20224#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 20225#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8
AM		 20226#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
20227#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 20228#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 20229#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 20230#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 20231#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 20232
07d6d2b8
AM		 20233#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20234#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 20235#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 20236#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 20237#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 20238#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 20239#define elf_backend_write_section elf32_arm_write_section
252b5132 20240#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 20241#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 20242#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20243#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20244#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 20245#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 20246#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 20247#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 20248#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 20249#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 20250#define elf_backend_fake_sections elf32_arm_fake_sections
20251#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20252#define elf_backend_final_write_processing elf32_arm_final_write_processing
20253#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 20254#define elf_backend_size_info elf32_arm_size_info
b294bdf8 20255#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 20256#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20257#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 20258#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 20259#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 20260#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 20261#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 20262#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 20263
20264#define elf_backend_can_refcount 1
20265#define elf_backend_can_gc_sections 1
20266#define elf_backend_plt_readonly 1
20267#define elf_backend_want_got_plt 1
20268#define elf_backend_want_plt_sym 0
5474d94f 20269#define elf_backend_want_dynrelro 1
906e58ca
NC		 20270#define elf_backend_may_use_rel_p 1
20271#define elf_backend_may_use_rela_p 0
4e7fd91e 20272#define elf_backend_default_use_rela_p 0
64f52338 20273#define elf_backend_dtrel_excludes_plt 1
252b5132 20274
04f7c78d 20275#define elf_backend_got_header_size 12
b68a20d6 20276#define elf_backend_extern_protected_data 1
04f7c78d 20277
07d6d2b8 20278#undef elf_backend_obj_attrs_vendor
906e58ca 20279#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 20280#undef elf_backend_obj_attrs_section
906e58ca 20281#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 20282#undef elf_backend_obj_attrs_arg_type
906e58ca 20283#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 20284#undef elf_backend_obj_attrs_section_type
104d59d1 20285#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 20286#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 20287#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 20288
07d6d2b8 20289#undef elf_backend_section_flags
ac4c9b04 20290#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 20291#undef elf_backend_lookup_section_flags_hook
20292#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 20293
a2f63b2e
MR		 20294#define elf_backend_linux_prpsinfo32_ugid16 TRUE
20295
252b5132 20296#include "elf32-target.h"
7f266840 20297
b38cadfb
NC		 20298/* Native Client targets. */
20299
20300#undef TARGET_LITTLE_SYM
6d00b590 20301#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 20302#undef TARGET_LITTLE_NAME
20303#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20304#undef TARGET_BIG_SYM
6d00b590 20305#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 20306#undef TARGET_BIG_NAME
20307#define TARGET_BIG_NAME "elf32-bigarm-nacl"
20308
20309/* Like elf32_arm_link_hash_table_create -- but overrides
20310 appropriately for NaCl. */
20311
20312static struct bfd_link_hash_table *
20313elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20314{
20315 struct bfd_link_hash_table *ret;
20316
20317 ret = elf32_arm_link_hash_table_create (abfd);
20318 if (ret)
20319 {
20320 struct elf32_arm_link_hash_table *htab
20321 = (struct elf32_arm_link_hash_table *) ret;
20322
20323 htab->nacl_p = 1;
20324
20325 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20326 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20327 }
20328 return ret;
20329}
20330
20331/* Since NaCl doesn't use the ARM-specific unwind format, we don't
20332 really need to use elf32_arm_modify_segment_map. But we do it
20333 anyway just to reduce gratuitous differences with the stock ARM backend. */
20334
20335static bfd_boolean
20336elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20337{
20338 return (elf32_arm_modify_segment_map (abfd, info)
20339 && nacl_modify_segment_map (abfd, info));
20340}
20341
887badb3
RM		 20342static void
20343elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
20344{
20345 elf32_arm_final_write_processing (abfd, linker);
20346 nacl_final_write_processing (abfd, linker);
20347}
20348
6a631e86
YG		 20349static bfd_vma
20350elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20351 const arelent *rel ATTRIBUTE_UNUSED)
20352{
20353 return plt->vma
20354 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20355 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20356}
887badb3 20357
b38cadfb 20358#undef elf32_bed
6a631e86 20359#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 20360#undef bfd_elf32_bfd_link_hash_table_create
20361#define bfd_elf32_bfd_link_hash_table_create \
20362 elf32_arm_nacl_link_hash_table_create
20363#undef elf_backend_plt_alignment
6a631e86 20364#define elf_backend_plt_alignment 4
b38cadfb
NC		 20365#undef elf_backend_modify_segment_map
20366#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
20367#undef elf_backend_modify_program_headers
20368#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 20369#undef elf_backend_final_write_processing
20370#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 20371#undef bfd_elf32_get_synthetic_symtab
20372#undef elf_backend_plt_sym_val
20373#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 20374#undef elf_backend_copy_special_section_fields
b38cadfb 20375
887badb3
RM		 20376#undef ELF_MINPAGESIZE
20377#undef ELF_COMMONPAGESIZE
20378
b38cadfb
NC		 20379
20380#include "elf32-target.h"
20381
20382/* Reset to defaults. */
20383#undef elf_backend_plt_alignment
20384#undef elf_backend_modify_segment_map
20385#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20386#undef elf_backend_modify_program_headers
887badb3
RM		 20387#undef elf_backend_final_write_processing
20388#define elf_backend_final_write_processing elf32_arm_final_write_processing
20389#undef ELF_MINPAGESIZE
20390#define ELF_MINPAGESIZE 0x1000
20391#undef ELF_COMMONPAGESIZE
20392#define ELF_COMMONPAGESIZE 0x1000
20393
b38cadfb 20394
617a5ada
CL		 20395/* FDPIC Targets. */
20396
20397#undef TARGET_LITTLE_SYM
20398#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20399#undef TARGET_LITTLE_NAME
20400#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20401#undef TARGET_BIG_SYM
20402#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20403#undef TARGET_BIG_NAME
20404#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20405#undef elf_match_priority
20406#define elf_match_priority 128
18a20338
CL		 20407#undef ELF_OSABI
20408#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 20409
20410/* Like elf32_arm_link_hash_table_create -- but overrides
20411 appropriately for FDPIC. */
20412
20413static struct bfd_link_hash_table *
20414elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20415{
20416 struct bfd_link_hash_table *ret;
20417
20418 ret = elf32_arm_link_hash_table_create (abfd);
20419 if (ret)
20420 {
20421 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20422
20423 htab->fdpic_p = 1;
20424 }
20425 return ret;
20426}
20427
e8b09b87
CL		 20428/* We need dynamic symbols for every section, since segments can
20429 relocate independently. */
20430static bfd_boolean
20431elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20432 struct bfd_link_info *info
20433 ATTRIBUTE_UNUSED,
20434 asection *p ATTRIBUTE_UNUSED)
20435{
20436 switch (elf_section_data (p)->this_hdr.sh_type)
20437 {
20438 case SHT_PROGBITS:
20439 case SHT_NOBITS:
20440 /* If sh_type is yet undecided, assume it could be
20441 SHT_PROGBITS/SHT_NOBITS. */
20442 case SHT_NULL:
20443 return FALSE;
20444
20445 /* There shouldn't be section relative relocations
20446 against any other section. */
20447 default:
20448 return TRUE;
20449 }
20450}
20451
617a5ada
CL		 20452#undef elf32_bed
20453#define elf32_bed elf32_arm_fdpic_bed
20454
20455#undef bfd_elf32_bfd_link_hash_table_create
4b24dd1a 20456#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
617a5ada 20457
e8b09b87
CL		 20458#undef elf_backend_omit_section_dynsym
20459#define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20460
617a5ada 20461#include "elf32-target.h"
e8b09b87 20462
617a5ada 20463#undef elf_match_priority
18a20338 20464#undef ELF_OSABI
e8b09b87 20465#undef elf_backend_omit_section_dynsym
617a5ada 20466
906e58ca 20467/* VxWorks Targets. */
4e7fd91e 20468
07d6d2b8
AM		 20469#undef TARGET_LITTLE_SYM
20470#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20471#undef TARGET_LITTLE_NAME
20472#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20473#undef TARGET_BIG_SYM
20474#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20475#undef TARGET_BIG_NAME
20476#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 20477
20478/* Like elf32_arm_link_hash_table_create -- but overrides
20479 appropriately for VxWorks. */
906e58ca 20480
4e7fd91e
PB		 20481static struct bfd_link_hash_table *
20482elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20483{
20484 struct bfd_link_hash_table *ret;
20485
20486 ret = elf32_arm_link_hash_table_create (abfd);
20487 if (ret)
20488 {
20489 struct elf32_arm_link_hash_table *htab
00a97672 20490 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 20491 htab->use_rel = 0;
00a97672 20492 htab->vxworks_p = 1;
4e7fd91e
PB		 20493 }
20494 return ret;
906e58ca 20495}
4e7fd91e 20496
00a97672
RS		 20497static void
20498elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
20499{
20500 elf32_arm_final_write_processing (abfd, linker);
20501 elf_vxworks_final_write_processing (abfd, linker);
20502}
20503
906e58ca 20504#undef elf32_bed
4e7fd91e
PB		 20505#define elf32_bed elf32_arm_vxworks_bed
20506
906e58ca
NC		 20507#undef bfd_elf32_bfd_link_hash_table_create
20508#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 20509#undef elf_backend_final_write_processing
20510#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20511#undef elf_backend_emit_relocs
9eaff861 20512#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 20513
906e58ca 20514#undef elf_backend_may_use_rel_p
00a97672 20515#define elf_backend_may_use_rel_p 0
906e58ca 20516#undef elf_backend_may_use_rela_p
00a97672 20517#define elf_backend_may_use_rela_p 1
906e58ca 20518#undef elf_backend_default_use_rela_p
00a97672 20519#define elf_backend_default_use_rela_p 1
906e58ca 20520#undef elf_backend_want_plt_sym
00a97672 20521#define elf_backend_want_plt_sym 1
906e58ca 20522#undef ELF_MAXPAGESIZE
00a97672 20523#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 20524
20525#include "elf32-target.h"
20526
20527
21d799b5
NC		 20528/* Merge backend specific data from an object file to the output
20529 object file when linking. */
20530
20531static bfd_boolean
50e03d47 20532elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 20533{
50e03d47 20534 bfd *obfd = info->output_bfd;
21d799b5
NC		 20535 flagword out_flags;
20536 flagword in_flags;
20537 bfd_boolean flags_compatible = TRUE;
20538 asection *sec;
20539
cc643b88 20540 /* Check if we have the same endianness. */
50e03d47 20541 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 20542 return FALSE;
20543
20544 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20545 return TRUE;
20546
50e03d47 20547 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 20548 return FALSE;
20549
20550 /* The input BFD must have had its flags initialised. */
20551 /* The following seems bogus to me -- The flags are initialized in
20552 the assembler but I don't think an elf_flags_init field is
20553 written into the object. */
20554 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20555
20556 in_flags = elf_elfheader (ibfd)->e_flags;
20557 out_flags = elf_elfheader (obfd)->e_flags;
20558
20559 /* In theory there is no reason why we couldn't handle this. However
20560 in practice it isn't even close to working and there is no real
20561 reason to want it. */
20562 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20563 && !(ibfd->flags & DYNAMIC)
20564 && (in_flags & EF_ARM_BE8))
20565 {
871b3ab2 20566 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 20567 ibfd);
20568 return FALSE;
20569 }
20570
20571 if (!elf_flags_init (obfd))
20572 {
20573 /* If the input is the default architecture and had the default
20574 flags then do not bother setting the flags for the output
20575 architecture, instead allow future merges to do this. If no
20576 future merges ever set these flags then they will retain their
99059e56
RM		 20577 uninitialised values, which surprise surprise, correspond
20578 to the default values. */
21d799b5
NC		 20579 if (bfd_get_arch_info (ibfd)->the_default
20580 && elf_elfheader (ibfd)->e_flags == 0)
20581 return TRUE;
20582
20583 elf_flags_init (obfd) = TRUE;
20584 elf_elfheader (obfd)->e_flags = in_flags;
20585
20586 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20587 && bfd_get_arch_info (obfd)->the_default)
20588 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20589
20590 return TRUE;
20591 }
20592
20593 /* Determine what should happen if the input ARM architecture
20594 does not match the output ARM architecture. */
20595 if (! bfd_arm_merge_machines (ibfd, obfd))
20596 return FALSE;
20597
20598 /* Identical flags must be compatible. */
20599 if (in_flags == out_flags)
20600 return TRUE;
20601
20602 /* Check to see if the input BFD actually contains any sections. If
20603 not, its flags may not have been initialised either, but it
20604 cannot actually cause any incompatiblity. Do not short-circuit
20605 dynamic objects; their section list may be emptied by
20606 elf_link_add_object_symbols.
20607
20608 Also check to see if there are no code sections in the input.
20609 In this case there is no need to check for code specific flags.
20610 XXX - do we need to worry about floating-point format compatability
20611 in data sections ? */
20612 if (!(ibfd->flags & DYNAMIC))
20613 {
20614 bfd_boolean null_input_bfd = TRUE;
20615 bfd_boolean only_data_sections = TRUE;
20616
20617 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20618 {
20619 /* Ignore synthetic glue sections. */
20620 if (strcmp (sec->name, ".glue_7")
20621 && strcmp (sec->name, ".glue_7t"))
20622 {
20623 if ((bfd_get_section_flags (ibfd, sec)
20624 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20625 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 20626 only_data_sections = FALSE;
21d799b5
NC		 20627
20628 null_input_bfd = FALSE;
20629 break;
20630 }
20631 }
20632
20633 if (null_input_bfd || only_data_sections)
20634 return TRUE;
20635 }
20636
20637 /* Complain about various flag mismatches. */
20638 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20639 EF_ARM_EABI_VERSION (out_flags)))
20640 {
20641 _bfd_error_handler
90b6238f 20642 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 20643 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20644 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 20645 return FALSE;
20646 }
20647
20648 /* Not sure what needs to be checked for EABI versions >= 1. */
20649 /* VxWorks libraries do not use these flags. */
20650 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20651 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20652 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20653 {
20654 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20655 {
20656 _bfd_error_handler
871b3ab2 20657 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 20658 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20659 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 20660 flags_compatible = FALSE;
20661 }
20662
20663 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20664 {
20665 if (in_flags & EF_ARM_APCS_FLOAT)
20666 _bfd_error_handler
871b3ab2 20667 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 20668 ibfd, obfd);
20669 else
20670 _bfd_error_handler
871b3ab2 20671 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 20672 ibfd, obfd);
20673
20674 flags_compatible = FALSE;
20675 }
20676
20677 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20678 {
20679 if (in_flags & EF_ARM_VFP_FLOAT)
20680 _bfd_error_handler
90b6238f
AM		 20681 (_("error: %pB uses %s instructions, whereas %pB does not"),
20682 ibfd, "VFP", obfd);
21d799b5
NC		 20683 else
20684 _bfd_error_handler
90b6238f
AM		 20685 (_("error: %pB uses %s instructions, whereas %pB does not"),
20686 ibfd, "FPA", obfd);
21d799b5
NC		 20687
20688 flags_compatible = FALSE;
20689 }
20690
20691 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20692 {
20693 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20694 _bfd_error_handler
90b6238f
AM		 20695 (_("error: %pB uses %s instructions, whereas %pB does not"),
20696 ibfd, "Maverick", obfd);
21d799b5
NC		 20697 else
20698 _bfd_error_handler
90b6238f
AM		 20699 (_("error: %pB does not use %s instructions, whereas %pB does"),
20700 ibfd, "Maverick", obfd);
21d799b5
NC		 20701
20702 flags_compatible = FALSE;
20703 }
20704
20705#ifdef EF_ARM_SOFT_FLOAT
20706 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20707 {
20708 /* We can allow interworking between code that is VFP format
20709 layout, and uses either soft float or integer regs for
20710 passing floating point arguments and results. We already
20711 know that the APCS_FLOAT flags match; similarly for VFP
20712 flags. */
20713 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20714 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20715 {
20716 if (in_flags & EF_ARM_SOFT_FLOAT)
20717 _bfd_error_handler
871b3ab2 20718 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 20719 ibfd, obfd);
20720 else
20721 _bfd_error_handler
871b3ab2 20722 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 20723 ibfd, obfd);
20724
20725 flags_compatible = FALSE;
20726 }
20727 }
20728#endif
20729
20730 /* Interworking mismatch is only a warning. */
20731 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
20732 {
20733 if (in_flags & EF_ARM_INTERWORK)
20734 {
20735 _bfd_error_handler
90b6238f 20736 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 20737 ibfd, obfd);
20738 }
20739 else
20740 {
20741 _bfd_error_handler
90b6238f 20742 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 20743 ibfd, obfd);
20744 }
20745 }
20746 }
20747
20748 return flags_compatible;
20749}
20750
20751
906e58ca 20752/* Symbian OS Targets. */
7f266840 20753
07d6d2b8
AM		 20754#undef TARGET_LITTLE_SYM
20755#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
20756#undef TARGET_LITTLE_NAME
20757#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
20758#undef TARGET_BIG_SYM
20759#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
20760#undef TARGET_BIG_NAME
20761#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 20762
20763/* Like elf32_arm_link_hash_table_create -- but overrides
20764 appropriately for Symbian OS. */
906e58ca 20765
7f266840
DJ		 20766static struct bfd_link_hash_table *
20767elf32_arm_symbian_link_hash_table_create (bfd *abfd)
20768{
20769 struct bfd_link_hash_table *ret;
20770
20771 ret = elf32_arm_link_hash_table_create (abfd);
20772 if (ret)
20773 {
20774 struct elf32_arm_link_hash_table *htab
20775 = (struct elf32_arm_link_hash_table *)ret;
20776 /* There is no PLT header for Symbian OS. */
20777 htab->plt_header_size = 0;
95720a86
DJ		 20778 /* The PLT entries are each one instruction and one word. */
20779 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 20780 htab->symbian_p = 1;
33bfe774
JB		 20781 /* Symbian uses armv5t or above, so use_blx is always true. */
20782 htab->use_blx = 1;
67687978 20783 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 20784 }
20785 return ret;
906e58ca 20786}
7f266840 20787
b35d266b 20788static const struct bfd_elf_special_section
551b43fd 20789elf32_arm_symbian_special_sections[] =
7f266840 20790{
5cd3778d
MM		 20791 /* In a BPABI executable, the dynamic linking sections do not go in
20792 the loadable read-only segment. The post-linker may wish to
20793 refer to these sections, but they are not part of the final
20794 program image. */
07d6d2b8
AM		 20795 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
20796 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
20797 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
20798 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
20799 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 20800 /* These sections do not need to be writable as the SymbianOS
20801 postlinker will arrange things so that no dynamic relocation is
20802 required. */
07d6d2b8
AM		 20803 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
20804 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 20805 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 20806 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 20807};
20808
c3c76620 20809static void
906e58ca 20810elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 20811 struct bfd_link_info *link_info)
c3c76620
MM		 20812{
20813 /* BPABI objects are never loaded directly by an OS kernel; they are
20814 processed by a postlinker first, into an OS-specific format. If
20815 the D_PAGED bit is set on the file, BFD will align segments on
20816 page boundaries, so that an OS can directly map the file. With
20817 BPABI objects, that just results in wasted space. In addition,
20818 because we clear the D_PAGED bit, map_sections_to_segments will
20819 recognize that the program headers should not be mapped into any
20820 loadable segment. */
20821 abfd->flags &= ~D_PAGED;
906e58ca 20822 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 20823}
7f266840
DJ		 20824
20825static bfd_boolean
906e58ca 20826elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 20827 struct bfd_link_info *info)
7f266840
DJ		 20828{
20829 struct elf_segment_map *m;
20830 asection *dynsec;
20831
7f266840
DJ		 20832 /* BPABI shared libraries and executables should have a PT_DYNAMIC
20833 segment. However, because the .dynamic section is not marked
20834 with SEC_LOAD, the generic ELF code will not create such a
20835 segment. */
20836 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
20837 if (dynsec)
20838 {
12bd6957 20839 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 20840 if (m->p_type == PT_DYNAMIC)
20841 break;
20842
20843 if (m == NULL)
20844 {
20845 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 20846 m->next = elf_seg_map (abfd);
20847 elf_seg_map (abfd) = m;
8ded5a0f 20848 }
7f266840
DJ		 20849 }
20850
b294bdf8
MM		 20851 /* Also call the generic arm routine. */
20852 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 20853}
20854
95720a86
DJ		 20855/* Return address for Ith PLT stub in section PLT, for relocation REL
20856 or (bfd_vma) -1 if it should not be included. */
20857
20858static bfd_vma
20859elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
20860 const arelent *rel ATTRIBUTE_UNUSED)
20861{
20862 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
20863}
20864
8029a119 20865#undef elf32_bed
7f266840
DJ		 20866#define elf32_bed elf32_arm_symbian_bed
20867
20868/* The dynamic sections are not allocated on SymbianOS; the postlinker
20869 will process them and then discard them. */
906e58ca 20870#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 20871#define ELF_DYNAMIC_SEC_FLAGS \
20872 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
20873
9eaff861 20874#undef elf_backend_emit_relocs
c3c76620 20875
906e58ca
NC		 20876#undef bfd_elf32_bfd_link_hash_table_create
20877#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
20878#undef elf_backend_special_sections
07d6d2b8 20879#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 20880#undef elf_backend_begin_write_processing
20881#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
20882#undef elf_backend_final_write_processing
20883#define elf_backend_final_write_processing elf32_arm_final_write_processing
20884
20885#undef elf_backend_modify_segment_map
7f266840
DJ		 20886#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
20887
20888/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 20889#undef elf_backend_got_header_size
7f266840
DJ		 20890#define elf_backend_got_header_size 0
20891
20892/* Similarly, there is no .got.plt section. */
906e58ca 20893#undef elf_backend_want_got_plt
7f266840
DJ		 20894#define elf_backend_want_got_plt 0
20895
906e58ca 20896#undef elf_backend_plt_sym_val
95720a86
DJ		 20897#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
20898
906e58ca 20899#undef elf_backend_may_use_rel_p
00a97672 20900#define elf_backend_may_use_rel_p 1
906e58ca 20901#undef elf_backend_may_use_rela_p
00a97672 20902#define elf_backend_may_use_rela_p 0
906e58ca 20903#undef elf_backend_default_use_rela_p
00a97672 20904#define elf_backend_default_use_rela_p 0
906e58ca 20905#undef elf_backend_want_plt_sym
00a97672 20906#define elf_backend_want_plt_sym 0
64f52338
AM		 20907#undef elf_backend_dtrel_excludes_plt
20908#define elf_backend_dtrel_excludes_plt 0
906e58ca 20909#undef ELF_MAXPAGESIZE
00a97672 20910#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 20911
7f266840 20912#include "elf32-target.h"
GDB Binutils - Deliverables
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