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PR26419, ASAN: mn10300_elf_relax_section elf-m10300.c:3943
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
b3adc24a 2 Copyright (C) 1998-2020 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
00a97672 25#include "libiberty.h"
7f266840
DJ		 26#include "libbfd.h"
27#include "elf-bfd.h"
b38cadfb 28#include "elf-nacl.h"
00a97672 29#include "elf-vxworks.h"
ee065d83 30#include "elf/arm.h"
f37164d7
AM		 31#include "elf32-arm.h"
32#include "cpu-arm.h"
7f266840 33
00a97672
RS		 34/* Return the relocation section associated with NAME. HTAB is the
35 bfd's elf32_arm_link_hash_entry. */
36#define RELOC_SECTION(HTAB, NAME) \
37 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
38
39/* Return size of a relocation entry. HTAB is the bfd's
40 elf32_arm_link_hash_entry. */
41#define RELOC_SIZE(HTAB) \
42 ((HTAB)->use_rel \
43 ? sizeof (Elf32_External_Rel) \
44 : sizeof (Elf32_External_Rela))
45
46/* Return function to swap relocations in. HTAB is the bfd's
47 elf32_arm_link_hash_entry. */
48#define SWAP_RELOC_IN(HTAB) \
49 ((HTAB)->use_rel \
50 ? bfd_elf32_swap_reloc_in \
51 : bfd_elf32_swap_reloca_in)
52
53/* Return function to swap relocations out. HTAB is the bfd's
54 elf32_arm_link_hash_entry. */
55#define SWAP_RELOC_OUT(HTAB) \
56 ((HTAB)->use_rel \
57 ? bfd_elf32_swap_reloc_out \
58 : bfd_elf32_swap_reloca_out)
59
f3185997 60#define elf_info_to_howto NULL
07d6d2b8 61#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 62
63#define ARM_ELF_ABI_VERSION 0
64#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
65
79f08007
YZ		 66/* The Adjusted Place, as defined by AAELF. */
67#define Pa(X) ((X) & 0xfffffffc)
68
3e6b1042
DJ		 69static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
70 struct bfd_link_info *link_info,
71 asection *sec,
72 bfd_byte *contents);
73
7f266840
DJ		 74/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
75 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
76 in that slot. */
77
c19d1205 78static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 79{
8029a119 80 /* No relocation. */
7f266840
DJ		 81 HOWTO (R_ARM_NONE, /* type */
82 0, /* rightshift */
6346d5ca 83 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 84 0, /* bitsize */
85 FALSE, /* pc_relative */
86 0, /* bitpos */
87 complain_overflow_dont,/* complain_on_overflow */
88 bfd_elf_generic_reloc, /* special_function */
89 "R_ARM_NONE", /* name */
90 FALSE, /* partial_inplace */
91 0, /* src_mask */
92 0, /* dst_mask */
93 FALSE), /* pcrel_offset */
94
95 HOWTO (R_ARM_PC24, /* type */
96 2, /* rightshift */
97 2, /* size (0 = byte, 1 = short, 2 = long) */
98 24, /* bitsize */
99 TRUE, /* pc_relative */
100 0, /* bitpos */
101 complain_overflow_signed,/* complain_on_overflow */
102 bfd_elf_generic_reloc, /* special_function */
103 "R_ARM_PC24", /* name */
104 FALSE, /* partial_inplace */
105 0x00ffffff, /* src_mask */
106 0x00ffffff, /* dst_mask */
107 TRUE), /* pcrel_offset */
108
109 /* 32 bit absolute */
110 HOWTO (R_ARM_ABS32, /* type */
111 0, /* rightshift */
112 2, /* size (0 = byte, 1 = short, 2 = long) */
113 32, /* bitsize */
114 FALSE, /* pc_relative */
115 0, /* bitpos */
116 complain_overflow_bitfield,/* complain_on_overflow */
117 bfd_elf_generic_reloc, /* special_function */
118 "R_ARM_ABS32", /* name */
119 FALSE, /* partial_inplace */
120 0xffffffff, /* src_mask */
121 0xffffffff, /* dst_mask */
122 FALSE), /* pcrel_offset */
123
124 /* standard 32bit pc-relative reloc */
125 HOWTO (R_ARM_REL32, /* type */
126 0, /* rightshift */
127 2, /* size (0 = byte, 1 = short, 2 = long) */
128 32, /* bitsize */
129 TRUE, /* pc_relative */
130 0, /* bitpos */
131 complain_overflow_bitfield,/* complain_on_overflow */
132 bfd_elf_generic_reloc, /* special_function */
133 "R_ARM_REL32", /* name */
134 FALSE, /* partial_inplace */
135 0xffffffff, /* src_mask */
136 0xffffffff, /* dst_mask */
137 TRUE), /* pcrel_offset */
138
c19d1205 139 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 140 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 141 0, /* rightshift */
142 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 143 32, /* bitsize */
144 TRUE, /* pc_relative */
7f266840 145 0, /* bitpos */
4962c51a 146 complain_overflow_dont,/* complain_on_overflow */
7f266840 147 bfd_elf_generic_reloc, /* special_function */
4962c51a 148 "R_ARM_LDR_PC_G0", /* name */
7f266840 149 FALSE, /* partial_inplace */
4962c51a
MS		 150 0xffffffff, /* src_mask */
151 0xffffffff, /* dst_mask */
152 TRUE), /* pcrel_offset */
7f266840
DJ		 153
154 /* 16 bit absolute */
155 HOWTO (R_ARM_ABS16, /* type */
156 0, /* rightshift */
157 1, /* size (0 = byte, 1 = short, 2 = long) */
158 16, /* bitsize */
159 FALSE, /* pc_relative */
160 0, /* bitpos */
161 complain_overflow_bitfield,/* complain_on_overflow */
162 bfd_elf_generic_reloc, /* special_function */
163 "R_ARM_ABS16", /* name */
164 FALSE, /* partial_inplace */
165 0x0000ffff, /* src_mask */
166 0x0000ffff, /* dst_mask */
167 FALSE), /* pcrel_offset */
168
169 /* 12 bit absolute */
170 HOWTO (R_ARM_ABS12, /* type */
171 0, /* rightshift */
172 2, /* size (0 = byte, 1 = short, 2 = long) */
173 12, /* bitsize */
174 FALSE, /* pc_relative */
175 0, /* bitpos */
176 complain_overflow_bitfield,/* complain_on_overflow */
177 bfd_elf_generic_reloc, /* special_function */
178 "R_ARM_ABS12", /* name */
179 FALSE, /* partial_inplace */
00a97672
RS		 180 0x00000fff, /* src_mask */
181 0x00000fff, /* dst_mask */
7f266840
DJ		 182 FALSE), /* pcrel_offset */
183
184 HOWTO (R_ARM_THM_ABS5, /* type */
185 6, /* rightshift */
186 1, /* size (0 = byte, 1 = short, 2 = long) */
187 5, /* bitsize */
188 FALSE, /* pc_relative */
189 0, /* bitpos */
190 complain_overflow_bitfield,/* complain_on_overflow */
191 bfd_elf_generic_reloc, /* special_function */
192 "R_ARM_THM_ABS5", /* name */
193 FALSE, /* partial_inplace */
194 0x000007e0, /* src_mask */
195 0x000007e0, /* dst_mask */
196 FALSE), /* pcrel_offset */
197
198 /* 8 bit absolute */
199 HOWTO (R_ARM_ABS8, /* type */
200 0, /* rightshift */
201 0, /* size (0 = byte, 1 = short, 2 = long) */
202 8, /* bitsize */
203 FALSE, /* pc_relative */
204 0, /* bitpos */
205 complain_overflow_bitfield,/* complain_on_overflow */
206 bfd_elf_generic_reloc, /* special_function */
207 "R_ARM_ABS8", /* name */
208 FALSE, /* partial_inplace */
209 0x000000ff, /* src_mask */
210 0x000000ff, /* dst_mask */
211 FALSE), /* pcrel_offset */
212
213 HOWTO (R_ARM_SBREL32, /* type */
214 0, /* rightshift */
215 2, /* size (0 = byte, 1 = short, 2 = long) */
216 32, /* bitsize */
217 FALSE, /* pc_relative */
218 0, /* bitpos */
219 complain_overflow_dont,/* complain_on_overflow */
220 bfd_elf_generic_reloc, /* special_function */
221 "R_ARM_SBREL32", /* name */
222 FALSE, /* partial_inplace */
223 0xffffffff, /* src_mask */
224 0xffffffff, /* dst_mask */
225 FALSE), /* pcrel_offset */
226
c19d1205 227 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 228 1, /* rightshift */
229 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 230 24, /* bitsize */
7f266840
DJ		 231 TRUE, /* pc_relative */
232 0, /* bitpos */
233 complain_overflow_signed,/* complain_on_overflow */
234 bfd_elf_generic_reloc, /* special_function */
c19d1205 235 "R_ARM_THM_CALL", /* name */
7f266840 236 FALSE, /* partial_inplace */
7f6ab9f8
AM		 237 0x07ff2fff, /* src_mask */
238 0x07ff2fff, /* dst_mask */
7f266840
DJ		 239 TRUE), /* pcrel_offset */
240
07d6d2b8 241 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 242 1, /* rightshift */
243 1, /* size (0 = byte, 1 = short, 2 = long) */
244 8, /* bitsize */
245 TRUE, /* pc_relative */
246 0, /* bitpos */
247 complain_overflow_signed,/* complain_on_overflow */
248 bfd_elf_generic_reloc, /* special_function */
249 "R_ARM_THM_PC8", /* name */
250 FALSE, /* partial_inplace */
251 0x000000ff, /* src_mask */
252 0x000000ff, /* dst_mask */
253 TRUE), /* pcrel_offset */
254
c19d1205 255 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 256 1, /* rightshift */
257 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 258 32, /* bitsize */
259 FALSE, /* pc_relative */
7f266840
DJ		 260 0, /* bitpos */
261 complain_overflow_signed,/* complain_on_overflow */
262 bfd_elf_generic_reloc, /* special_function */
c19d1205 263 "R_ARM_BREL_ADJ", /* name */
7f266840 264 FALSE, /* partial_inplace */
c19d1205
ZW		 265 0xffffffff, /* src_mask */
266 0xffffffff, /* dst_mask */
267 FALSE), /* pcrel_offset */
7f266840 268
0855e32b 269 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 270 0, /* rightshift */
0855e32b
NS		 271 2, /* size (0 = byte, 1 = short, 2 = long) */
272 32, /* bitsize */
7f266840
DJ		 273 FALSE, /* pc_relative */
274 0, /* bitpos */
0855e32b 275 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 276 bfd_elf_generic_reloc, /* special_function */
0855e32b 277 "R_ARM_TLS_DESC", /* name */
7f266840 278 FALSE, /* partial_inplace */
0855e32b
NS		 279 0xffffffff, /* src_mask */
280 0xffffffff, /* dst_mask */
7f266840
DJ		 281 FALSE), /* pcrel_offset */
282
283 HOWTO (R_ARM_THM_SWI8, /* type */
284 0, /* rightshift */
285 0, /* size (0 = byte, 1 = short, 2 = long) */
286 0, /* bitsize */
287 FALSE, /* pc_relative */
288 0, /* bitpos */
289 complain_overflow_signed,/* complain_on_overflow */
290 bfd_elf_generic_reloc, /* special_function */
291 "R_ARM_SWI8", /* name */
292 FALSE, /* partial_inplace */
293 0x00000000, /* src_mask */
294 0x00000000, /* dst_mask */
295 FALSE), /* pcrel_offset */
296
297 /* BLX instruction for the ARM. */
298 HOWTO (R_ARM_XPC25, /* type */
299 2, /* rightshift */
300 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 301 24, /* bitsize */
7f266840
DJ		 302 TRUE, /* pc_relative */
303 0, /* bitpos */
304 complain_overflow_signed,/* complain_on_overflow */
305 bfd_elf_generic_reloc, /* special_function */
306 "R_ARM_XPC25", /* name */
307 FALSE, /* partial_inplace */
308 0x00ffffff, /* src_mask */
309 0x00ffffff, /* dst_mask */
310 TRUE), /* pcrel_offset */
311
312 /* BLX instruction for the Thumb. */
313 HOWTO (R_ARM_THM_XPC22, /* type */
314 2, /* rightshift */
315 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 316 24, /* bitsize */
7f266840
DJ		 317 TRUE, /* pc_relative */
318 0, /* bitpos */
319 complain_overflow_signed,/* complain_on_overflow */
320 bfd_elf_generic_reloc, /* special_function */
321 "R_ARM_THM_XPC22", /* name */
322 FALSE, /* partial_inplace */
7f6ab9f8
AM		 323 0x07ff2fff, /* src_mask */
324 0x07ff2fff, /* dst_mask */
7f266840
DJ		 325 TRUE), /* pcrel_offset */
326
ba93b8ac 327 /* Dynamic TLS relocations. */
7f266840 328
ba93b8ac 329 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 330 0, /* rightshift */
331 2, /* size (0 = byte, 1 = short, 2 = long) */
332 32, /* bitsize */
333 FALSE, /* pc_relative */
334 0, /* bitpos */
99059e56
RM		 335 complain_overflow_bitfield,/* complain_on_overflow */
336 bfd_elf_generic_reloc, /* special_function */
337 "R_ARM_TLS_DTPMOD32", /* name */
338 TRUE, /* partial_inplace */
339 0xffffffff, /* src_mask */
340 0xffffffff, /* dst_mask */
07d6d2b8 341 FALSE), /* pcrel_offset */
7f266840 342
ba93b8ac 343 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 344 0, /* rightshift */
345 2, /* size (0 = byte, 1 = short, 2 = long) */
346 32, /* bitsize */
347 FALSE, /* pc_relative */
348 0, /* bitpos */
99059e56
RM		 349 complain_overflow_bitfield,/* complain_on_overflow */
350 bfd_elf_generic_reloc, /* special_function */
351 "R_ARM_TLS_DTPOFF32", /* name */
352 TRUE, /* partial_inplace */
353 0xffffffff, /* src_mask */
354 0xffffffff, /* dst_mask */
07d6d2b8 355 FALSE), /* pcrel_offset */
7f266840 356
ba93b8ac 357 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 358 0, /* rightshift */
359 2, /* size (0 = byte, 1 = short, 2 = long) */
360 32, /* bitsize */
361 FALSE, /* pc_relative */
362 0, /* bitpos */
99059e56
RM		 363 complain_overflow_bitfield,/* complain_on_overflow */
364 bfd_elf_generic_reloc, /* special_function */
365 "R_ARM_TLS_TPOFF32", /* name */
366 TRUE, /* partial_inplace */
367 0xffffffff, /* src_mask */
368 0xffffffff, /* dst_mask */
07d6d2b8 369 FALSE), /* pcrel_offset */
7f266840
DJ		 370
371 /* Relocs used in ARM Linux */
372
373 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 374 0, /* rightshift */
375 2, /* size (0 = byte, 1 = short, 2 = long) */
376 32, /* bitsize */
377 FALSE, /* pc_relative */
378 0, /* bitpos */
99059e56
RM		 379 complain_overflow_bitfield,/* complain_on_overflow */
380 bfd_elf_generic_reloc, /* special_function */
381 "R_ARM_COPY", /* name */
382 TRUE, /* partial_inplace */
383 0xffffffff, /* src_mask */
384 0xffffffff, /* dst_mask */
07d6d2b8 385 FALSE), /* pcrel_offset */
7f266840
DJ		 386
387 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 388 0, /* rightshift */
389 2, /* size (0 = byte, 1 = short, 2 = long) */
390 32, /* bitsize */
391 FALSE, /* pc_relative */
392 0, /* bitpos */
99059e56
RM		 393 complain_overflow_bitfield,/* complain_on_overflow */
394 bfd_elf_generic_reloc, /* special_function */
395 "R_ARM_GLOB_DAT", /* name */
396 TRUE, /* partial_inplace */
397 0xffffffff, /* src_mask */
398 0xffffffff, /* dst_mask */
07d6d2b8 399 FALSE), /* pcrel_offset */
7f266840
DJ		 400
401 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 402 0, /* rightshift */
403 2, /* size (0 = byte, 1 = short, 2 = long) */
404 32, /* bitsize */
405 FALSE, /* pc_relative */
406 0, /* bitpos */
99059e56
RM		 407 complain_overflow_bitfield,/* complain_on_overflow */
408 bfd_elf_generic_reloc, /* special_function */
409 "R_ARM_JUMP_SLOT", /* name */
410 TRUE, /* partial_inplace */
411 0xffffffff, /* src_mask */
412 0xffffffff, /* dst_mask */
07d6d2b8 413 FALSE), /* pcrel_offset */
7f266840
DJ		 414
415 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 416 0, /* rightshift */
417 2, /* size (0 = byte, 1 = short, 2 = long) */
418 32, /* bitsize */
419 FALSE, /* pc_relative */
420 0, /* bitpos */
99059e56
RM		 421 complain_overflow_bitfield,/* complain_on_overflow */
422 bfd_elf_generic_reloc, /* special_function */
423 "R_ARM_RELATIVE", /* name */
424 TRUE, /* partial_inplace */
425 0xffffffff, /* src_mask */
426 0xffffffff, /* dst_mask */
07d6d2b8 427 FALSE), /* pcrel_offset */
7f266840 428
c19d1205 429 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 430 0, /* rightshift */
431 2, /* size (0 = byte, 1 = short, 2 = long) */
432 32, /* bitsize */
433 FALSE, /* pc_relative */
434 0, /* bitpos */
99059e56
RM		 435 complain_overflow_bitfield,/* complain_on_overflow */
436 bfd_elf_generic_reloc, /* special_function */
437 "R_ARM_GOTOFF32", /* name */
438 TRUE, /* partial_inplace */
439 0xffffffff, /* src_mask */
440 0xffffffff, /* dst_mask */
07d6d2b8 441 FALSE), /* pcrel_offset */
7f266840
DJ		 442
443 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 444 0, /* rightshift */
445 2, /* size (0 = byte, 1 = short, 2 = long) */
446 32, /* bitsize */
99059e56 447 TRUE, /* pc_relative */
07d6d2b8 448 0, /* bitpos */
99059e56
RM		 449 complain_overflow_bitfield,/* complain_on_overflow */
450 bfd_elf_generic_reloc, /* special_function */
451 "R_ARM_GOTPC", /* name */
452 TRUE, /* partial_inplace */
453 0xffffffff, /* src_mask */
454 0xffffffff, /* dst_mask */
455 TRUE), /* pcrel_offset */
7f266840
DJ		 456
457 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 458 0, /* rightshift */
459 2, /* size (0 = byte, 1 = short, 2 = long) */
460 32, /* bitsize */
99059e56 461 FALSE, /* pc_relative */
07d6d2b8 462 0, /* bitpos */
99059e56
RM		 463 complain_overflow_bitfield,/* complain_on_overflow */
464 bfd_elf_generic_reloc, /* special_function */
465 "R_ARM_GOT32", /* name */
466 TRUE, /* partial_inplace */
467 0xffffffff, /* src_mask */
468 0xffffffff, /* dst_mask */
469 FALSE), /* pcrel_offset */
7f266840
DJ		 470
471 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 472 2, /* rightshift */
473 2, /* size (0 = byte, 1 = short, 2 = long) */
474 24, /* bitsize */
99059e56 475 TRUE, /* pc_relative */
07d6d2b8 476 0, /* bitpos */
99059e56
RM		 477 complain_overflow_bitfield,/* complain_on_overflow */
478 bfd_elf_generic_reloc, /* special_function */
479 "R_ARM_PLT32", /* name */
480 FALSE, /* partial_inplace */
481 0x00ffffff, /* src_mask */
482 0x00ffffff, /* dst_mask */
483 TRUE), /* pcrel_offset */
7f266840
DJ		 484
485 HOWTO (R_ARM_CALL, /* type */
486 2, /* rightshift */
487 2, /* size (0 = byte, 1 = short, 2 = long) */
488 24, /* bitsize */
489 TRUE, /* pc_relative */
490 0, /* bitpos */
491 complain_overflow_signed,/* complain_on_overflow */
492 bfd_elf_generic_reloc, /* special_function */
493 "R_ARM_CALL", /* name */
494 FALSE, /* partial_inplace */
495 0x00ffffff, /* src_mask */
496 0x00ffffff, /* dst_mask */
497 TRUE), /* pcrel_offset */
498
499 HOWTO (R_ARM_JUMP24, /* type */
500 2, /* rightshift */
501 2, /* size (0 = byte, 1 = short, 2 = long) */
502 24, /* bitsize */
503 TRUE, /* pc_relative */
504 0, /* bitpos */
505 complain_overflow_signed,/* complain_on_overflow */
506 bfd_elf_generic_reloc, /* special_function */
507 "R_ARM_JUMP24", /* name */
508 FALSE, /* partial_inplace */
509 0x00ffffff, /* src_mask */
510 0x00ffffff, /* dst_mask */
511 TRUE), /* pcrel_offset */
512
c19d1205
ZW		 513 HOWTO (R_ARM_THM_JUMP24, /* type */
514 1, /* rightshift */
515 2, /* size (0 = byte, 1 = short, 2 = long) */
516 24, /* bitsize */
517 TRUE, /* pc_relative */
7f266840 518 0, /* bitpos */
c19d1205 519 complain_overflow_signed,/* complain_on_overflow */
7f266840 520 bfd_elf_generic_reloc, /* special_function */
c19d1205 521 "R_ARM_THM_JUMP24", /* name */
7f266840 522 FALSE, /* partial_inplace */
c19d1205
ZW		 523 0x07ff2fff, /* src_mask */
524 0x07ff2fff, /* dst_mask */
525 TRUE), /* pcrel_offset */
7f266840 526
c19d1205 527 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 528 0, /* rightshift */
c19d1205
ZW		 529 2, /* size (0 = byte, 1 = short, 2 = long) */
530 32, /* bitsize */
7f266840
DJ		 531 FALSE, /* pc_relative */
532 0, /* bitpos */
533 complain_overflow_dont,/* complain_on_overflow */
534 bfd_elf_generic_reloc, /* special_function */
c19d1205 535 "R_ARM_BASE_ABS", /* name */
7f266840 536 FALSE, /* partial_inplace */
c19d1205
ZW		 537 0xffffffff, /* src_mask */
538 0xffffffff, /* dst_mask */
7f266840
DJ		 539 FALSE), /* pcrel_offset */
540
541 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
542 0, /* rightshift */
543 2, /* size (0 = byte, 1 = short, 2 = long) */
544 12, /* bitsize */
545 TRUE, /* pc_relative */
546 0, /* bitpos */
547 complain_overflow_dont,/* complain_on_overflow */
548 bfd_elf_generic_reloc, /* special_function */
549 "R_ARM_ALU_PCREL_7_0", /* name */
550 FALSE, /* partial_inplace */
551 0x00000fff, /* src_mask */
552 0x00000fff, /* dst_mask */
553 TRUE), /* pcrel_offset */
554
555 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
556 0, /* rightshift */
557 2, /* size (0 = byte, 1 = short, 2 = long) */
558 12, /* bitsize */
559 TRUE, /* pc_relative */
560 8, /* bitpos */
561 complain_overflow_dont,/* complain_on_overflow */
562 bfd_elf_generic_reloc, /* special_function */
563 "R_ARM_ALU_PCREL_15_8",/* name */
564 FALSE, /* partial_inplace */
565 0x00000fff, /* src_mask */
566 0x00000fff, /* dst_mask */
567 TRUE), /* pcrel_offset */
568
569 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
570 0, /* rightshift */
571 2, /* size (0 = byte, 1 = short, 2 = long) */
572 12, /* bitsize */
573 TRUE, /* pc_relative */
574 16, /* bitpos */
575 complain_overflow_dont,/* complain_on_overflow */
576 bfd_elf_generic_reloc, /* special_function */
577 "R_ARM_ALU_PCREL_23_15",/* name */
578 FALSE, /* partial_inplace */
579 0x00000fff, /* src_mask */
580 0x00000fff, /* dst_mask */
581 TRUE), /* pcrel_offset */
582
583 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
584 0, /* rightshift */
585 2, /* size (0 = byte, 1 = short, 2 = long) */
586 12, /* bitsize */
587 FALSE, /* pc_relative */
588 0, /* bitpos */
589 complain_overflow_dont,/* complain_on_overflow */
590 bfd_elf_generic_reloc, /* special_function */
591 "R_ARM_LDR_SBREL_11_0",/* name */
592 FALSE, /* partial_inplace */
593 0x00000fff, /* src_mask */
594 0x00000fff, /* dst_mask */
595 FALSE), /* pcrel_offset */
596
597 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
598 0, /* rightshift */
599 2, /* size (0 = byte, 1 = short, 2 = long) */
600 8, /* bitsize */
601 FALSE, /* pc_relative */
602 12, /* bitpos */
603 complain_overflow_dont,/* complain_on_overflow */
604 bfd_elf_generic_reloc, /* special_function */
605 "R_ARM_ALU_SBREL_19_12",/* name */
606 FALSE, /* partial_inplace */
607 0x000ff000, /* src_mask */
608 0x000ff000, /* dst_mask */
609 FALSE), /* pcrel_offset */
610
611 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
612 0, /* rightshift */
613 2, /* size (0 = byte, 1 = short, 2 = long) */
614 8, /* bitsize */
615 FALSE, /* pc_relative */
616 20, /* bitpos */
617 complain_overflow_dont,/* complain_on_overflow */
618 bfd_elf_generic_reloc, /* special_function */
619 "R_ARM_ALU_SBREL_27_20",/* name */
620 FALSE, /* partial_inplace */
621 0x0ff00000, /* src_mask */
622 0x0ff00000, /* dst_mask */
623 FALSE), /* pcrel_offset */
624
625 HOWTO (R_ARM_TARGET1, /* type */
626 0, /* rightshift */
627 2, /* size (0 = byte, 1 = short, 2 = long) */
628 32, /* bitsize */
629 FALSE, /* pc_relative */
630 0, /* bitpos */
631 complain_overflow_dont,/* complain_on_overflow */
632 bfd_elf_generic_reloc, /* special_function */
633 "R_ARM_TARGET1", /* name */
634 FALSE, /* partial_inplace */
635 0xffffffff, /* src_mask */
636 0xffffffff, /* dst_mask */
637 FALSE), /* pcrel_offset */
638
639 HOWTO (R_ARM_ROSEGREL32, /* type */
640 0, /* rightshift */
641 2, /* size (0 = byte, 1 = short, 2 = long) */
642 32, /* bitsize */
643 FALSE, /* pc_relative */
644 0, /* bitpos */
645 complain_overflow_dont,/* complain_on_overflow */
646 bfd_elf_generic_reloc, /* special_function */
647 "R_ARM_ROSEGREL32", /* name */
648 FALSE, /* partial_inplace */
649 0xffffffff, /* src_mask */
650 0xffffffff, /* dst_mask */
651 FALSE), /* pcrel_offset */
652
653 HOWTO (R_ARM_V4BX, /* type */
654 0, /* rightshift */
655 2, /* size (0 = byte, 1 = short, 2 = long) */
656 32, /* bitsize */
657 FALSE, /* pc_relative */
658 0, /* bitpos */
659 complain_overflow_dont,/* complain_on_overflow */
660 bfd_elf_generic_reloc, /* special_function */
661 "R_ARM_V4BX", /* name */
662 FALSE, /* partial_inplace */
663 0xffffffff, /* src_mask */
664 0xffffffff, /* dst_mask */
665 FALSE), /* pcrel_offset */
666
667 HOWTO (R_ARM_TARGET2, /* type */
668 0, /* rightshift */
669 2, /* size (0 = byte, 1 = short, 2 = long) */
670 32, /* bitsize */
671 FALSE, /* pc_relative */
672 0, /* bitpos */
673 complain_overflow_signed,/* complain_on_overflow */
674 bfd_elf_generic_reloc, /* special_function */
675 "R_ARM_TARGET2", /* name */
676 FALSE, /* partial_inplace */
677 0xffffffff, /* src_mask */
678 0xffffffff, /* dst_mask */
679 TRUE), /* pcrel_offset */
680
681 HOWTO (R_ARM_PREL31, /* type */
682 0, /* rightshift */
683 2, /* size (0 = byte, 1 = short, 2 = long) */
684 31, /* bitsize */
685 TRUE, /* pc_relative */
686 0, /* bitpos */
687 complain_overflow_signed,/* complain_on_overflow */
688 bfd_elf_generic_reloc, /* special_function */
689 "R_ARM_PREL31", /* name */
690 FALSE, /* partial_inplace */
691 0x7fffffff, /* src_mask */
692 0x7fffffff, /* dst_mask */
693 TRUE), /* pcrel_offset */
c19d1205
ZW		 694
695 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
696 0, /* rightshift */
697 2, /* size (0 = byte, 1 = short, 2 = long) */
698 16, /* bitsize */
699 FALSE, /* pc_relative */
700 0, /* bitpos */
701 complain_overflow_dont,/* complain_on_overflow */
702 bfd_elf_generic_reloc, /* special_function */
703 "R_ARM_MOVW_ABS_NC", /* name */
704 FALSE, /* partial_inplace */
39623e12
PB		 705 0x000f0fff, /* src_mask */
706 0x000f0fff, /* dst_mask */
c19d1205
ZW		 707 FALSE), /* pcrel_offset */
708
709 HOWTO (R_ARM_MOVT_ABS, /* type */
710 0, /* rightshift */
711 2, /* size (0 = byte, 1 = short, 2 = long) */
712 16, /* bitsize */
713 FALSE, /* pc_relative */
714 0, /* bitpos */
715 complain_overflow_bitfield,/* complain_on_overflow */
716 bfd_elf_generic_reloc, /* special_function */
717 "R_ARM_MOVT_ABS", /* name */
718 FALSE, /* partial_inplace */
39623e12
PB		 719 0x000f0fff, /* src_mask */
720 0x000f0fff, /* dst_mask */
c19d1205
ZW		 721 FALSE), /* pcrel_offset */
722
723 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
724 0, /* rightshift */
725 2, /* size (0 = byte, 1 = short, 2 = long) */
726 16, /* bitsize */
727 TRUE, /* pc_relative */
728 0, /* bitpos */
729 complain_overflow_dont,/* complain_on_overflow */
730 bfd_elf_generic_reloc, /* special_function */
731 "R_ARM_MOVW_PREL_NC", /* name */
732 FALSE, /* partial_inplace */
39623e12
PB		 733 0x000f0fff, /* src_mask */
734 0x000f0fff, /* dst_mask */
c19d1205
ZW		 735 TRUE), /* pcrel_offset */
736
737 HOWTO (R_ARM_MOVT_PREL, /* type */
738 0, /* rightshift */
739 2, /* size (0 = byte, 1 = short, 2 = long) */
740 16, /* bitsize */
741 TRUE, /* pc_relative */
742 0, /* bitpos */
743 complain_overflow_bitfield,/* complain_on_overflow */
744 bfd_elf_generic_reloc, /* special_function */
745 "R_ARM_MOVT_PREL", /* name */
746 FALSE, /* partial_inplace */
39623e12
PB		 747 0x000f0fff, /* src_mask */
748 0x000f0fff, /* dst_mask */
c19d1205
ZW		 749 TRUE), /* pcrel_offset */
750
751 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
752 0, /* rightshift */
753 2, /* size (0 = byte, 1 = short, 2 = long) */
754 16, /* bitsize */
755 FALSE, /* pc_relative */
756 0, /* bitpos */
757 complain_overflow_dont,/* complain_on_overflow */
758 bfd_elf_generic_reloc, /* special_function */
759 "R_ARM_THM_MOVW_ABS_NC",/* name */
760 FALSE, /* partial_inplace */
761 0x040f70ff, /* src_mask */
762 0x040f70ff, /* dst_mask */
763 FALSE), /* pcrel_offset */
764
765 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
766 0, /* rightshift */
767 2, /* size (0 = byte, 1 = short, 2 = long) */
768 16, /* bitsize */
769 FALSE, /* pc_relative */
770 0, /* bitpos */
771 complain_overflow_bitfield,/* complain_on_overflow */
772 bfd_elf_generic_reloc, /* special_function */
773 "R_ARM_THM_MOVT_ABS", /* name */
774 FALSE, /* partial_inplace */
775 0x040f70ff, /* src_mask */
776 0x040f70ff, /* dst_mask */
777 FALSE), /* pcrel_offset */
778
779 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
780 0, /* rightshift */
781 2, /* size (0 = byte, 1 = short, 2 = long) */
782 16, /* bitsize */
783 TRUE, /* pc_relative */
784 0, /* bitpos */
785 complain_overflow_dont,/* complain_on_overflow */
786 bfd_elf_generic_reloc, /* special_function */
787 "R_ARM_THM_MOVW_PREL_NC",/* name */
788 FALSE, /* partial_inplace */
789 0x040f70ff, /* src_mask */
790 0x040f70ff, /* dst_mask */
791 TRUE), /* pcrel_offset */
792
793 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
794 0, /* rightshift */
795 2, /* size (0 = byte, 1 = short, 2 = long) */
796 16, /* bitsize */
797 TRUE, /* pc_relative */
798 0, /* bitpos */
799 complain_overflow_bitfield,/* complain_on_overflow */
800 bfd_elf_generic_reloc, /* special_function */
801 "R_ARM_THM_MOVT_PREL", /* name */
802 FALSE, /* partial_inplace */
803 0x040f70ff, /* src_mask */
804 0x040f70ff, /* dst_mask */
805 TRUE), /* pcrel_offset */
806
807 HOWTO (R_ARM_THM_JUMP19, /* type */
808 1, /* rightshift */
809 2, /* size (0 = byte, 1 = short, 2 = long) */
810 19, /* bitsize */
811 TRUE, /* pc_relative */
812 0, /* bitpos */
813 complain_overflow_signed,/* complain_on_overflow */
814 bfd_elf_generic_reloc, /* special_function */
815 "R_ARM_THM_JUMP19", /* name */
816 FALSE, /* partial_inplace */
817 0x043f2fff, /* src_mask */
818 0x043f2fff, /* dst_mask */
819 TRUE), /* pcrel_offset */
820
821 HOWTO (R_ARM_THM_JUMP6, /* type */
822 1, /* rightshift */
823 1, /* size (0 = byte, 1 = short, 2 = long) */
824 6, /* bitsize */
825 TRUE, /* pc_relative */
826 0, /* bitpos */
827 complain_overflow_unsigned,/* complain_on_overflow */
828 bfd_elf_generic_reloc, /* special_function */
829 "R_ARM_THM_JUMP6", /* name */
830 FALSE, /* partial_inplace */
831 0x02f8, /* src_mask */
832 0x02f8, /* dst_mask */
833 TRUE), /* pcrel_offset */
834
835 /* These are declared as 13-bit signed relocations because we can
836 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
837 versa. */
838 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
839 0, /* rightshift */
840 2, /* size (0 = byte, 1 = short, 2 = long) */
841 13, /* bitsize */
842 TRUE, /* pc_relative */
843 0, /* bitpos */
2cab6cc3 844 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 845 bfd_elf_generic_reloc, /* special_function */
846 "R_ARM_THM_ALU_PREL_11_0",/* name */
847 FALSE, /* partial_inplace */
2cab6cc3
MS		 848 0xffffffff, /* src_mask */
849 0xffffffff, /* dst_mask */
c19d1205
ZW		 850 TRUE), /* pcrel_offset */
851
852 HOWTO (R_ARM_THM_PC12, /* type */
853 0, /* rightshift */
854 2, /* size (0 = byte, 1 = short, 2 = long) */
855 13, /* bitsize */
856 TRUE, /* pc_relative */
857 0, /* bitpos */
2cab6cc3 858 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 859 bfd_elf_generic_reloc, /* special_function */
860 "R_ARM_THM_PC12", /* name */
861 FALSE, /* partial_inplace */
2cab6cc3
MS		 862 0xffffffff, /* src_mask */
863 0xffffffff, /* dst_mask */
c19d1205
ZW		 864 TRUE), /* pcrel_offset */
865
866 HOWTO (R_ARM_ABS32_NOI, /* type */
867 0, /* rightshift */
868 2, /* size (0 = byte, 1 = short, 2 = long) */
869 32, /* bitsize */
870 FALSE, /* pc_relative */
871 0, /* bitpos */
872 complain_overflow_dont,/* complain_on_overflow */
873 bfd_elf_generic_reloc, /* special_function */
874 "R_ARM_ABS32_NOI", /* name */
875 FALSE, /* partial_inplace */
876 0xffffffff, /* src_mask */
877 0xffffffff, /* dst_mask */
878 FALSE), /* pcrel_offset */
879
880 HOWTO (R_ARM_REL32_NOI, /* type */
881 0, /* rightshift */
882 2, /* size (0 = byte, 1 = short, 2 = long) */
883 32, /* bitsize */
884 TRUE, /* pc_relative */
885 0, /* bitpos */
886 complain_overflow_dont,/* complain_on_overflow */
887 bfd_elf_generic_reloc, /* special_function */
888 "R_ARM_REL32_NOI", /* name */
889 FALSE, /* partial_inplace */
890 0xffffffff, /* src_mask */
891 0xffffffff, /* dst_mask */
892 FALSE), /* pcrel_offset */
7f266840 893
4962c51a
MS		 894 /* Group relocations. */
895
896 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
897 0, /* rightshift */
898 2, /* size (0 = byte, 1 = short, 2 = long) */
899 32, /* bitsize */
900 TRUE, /* pc_relative */
901 0, /* bitpos */
902 complain_overflow_dont,/* complain_on_overflow */
903 bfd_elf_generic_reloc, /* special_function */
904 "R_ARM_ALU_PC_G0_NC", /* name */
905 FALSE, /* partial_inplace */
906 0xffffffff, /* src_mask */
907 0xffffffff, /* dst_mask */
908 TRUE), /* pcrel_offset */
909
07d6d2b8 910 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 911 0, /* rightshift */
912 2, /* size (0 = byte, 1 = short, 2 = long) */
913 32, /* bitsize */
914 TRUE, /* pc_relative */
915 0, /* bitpos */
916 complain_overflow_dont,/* complain_on_overflow */
917 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 918 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 919 FALSE, /* partial_inplace */
920 0xffffffff, /* src_mask */
921 0xffffffff, /* dst_mask */
922 TRUE), /* pcrel_offset */
923
924 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
925 0, /* rightshift */
926 2, /* size (0 = byte, 1 = short, 2 = long) */
927 32, /* bitsize */
928 TRUE, /* pc_relative */
929 0, /* bitpos */
930 complain_overflow_dont,/* complain_on_overflow */
931 bfd_elf_generic_reloc, /* special_function */
932 "R_ARM_ALU_PC_G1_NC", /* name */
933 FALSE, /* partial_inplace */
934 0xffffffff, /* src_mask */
935 0xffffffff, /* dst_mask */
936 TRUE), /* pcrel_offset */
937
07d6d2b8 938 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 939 0, /* rightshift */
940 2, /* size (0 = byte, 1 = short, 2 = long) */
941 32, /* bitsize */
942 TRUE, /* pc_relative */
943 0, /* bitpos */
944 complain_overflow_dont,/* complain_on_overflow */
945 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 946 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 947 FALSE, /* partial_inplace */
948 0xffffffff, /* src_mask */
949 0xffffffff, /* dst_mask */
950 TRUE), /* pcrel_offset */
951
07d6d2b8 952 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 953 0, /* rightshift */
954 2, /* size (0 = byte, 1 = short, 2 = long) */
955 32, /* bitsize */
956 TRUE, /* pc_relative */
957 0, /* bitpos */
958 complain_overflow_dont,/* complain_on_overflow */
959 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 960 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 961 FALSE, /* partial_inplace */
962 0xffffffff, /* src_mask */
963 0xffffffff, /* dst_mask */
964 TRUE), /* pcrel_offset */
965
07d6d2b8 966 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 967 0, /* rightshift */
968 2, /* size (0 = byte, 1 = short, 2 = long) */
969 32, /* bitsize */
970 TRUE, /* pc_relative */
971 0, /* bitpos */
972 complain_overflow_dont,/* complain_on_overflow */
973 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 974 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 975 FALSE, /* partial_inplace */
976 0xffffffff, /* src_mask */
977 0xffffffff, /* dst_mask */
978 TRUE), /* pcrel_offset */
979
07d6d2b8 980 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 981 0, /* rightshift */
982 2, /* size (0 = byte, 1 = short, 2 = long) */
983 32, /* bitsize */
984 TRUE, /* pc_relative */
985 0, /* bitpos */
986 complain_overflow_dont,/* complain_on_overflow */
987 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 988 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 989 FALSE, /* partial_inplace */
990 0xffffffff, /* src_mask */
991 0xffffffff, /* dst_mask */
992 TRUE), /* pcrel_offset */
993
07d6d2b8 994 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 995 0, /* rightshift */
996 2, /* size (0 = byte, 1 = short, 2 = long) */
997 32, /* bitsize */
998 TRUE, /* pc_relative */
999 0, /* bitpos */
1000 complain_overflow_dont,/* complain_on_overflow */
1001 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1002 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1003 FALSE, /* partial_inplace */
1004 0xffffffff, /* src_mask */
1005 0xffffffff, /* dst_mask */
1006 TRUE), /* pcrel_offset */
1007
07d6d2b8 1008 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1009 0, /* rightshift */
1010 2, /* size (0 = byte, 1 = short, 2 = long) */
1011 32, /* bitsize */
1012 TRUE, /* pc_relative */
1013 0, /* bitpos */
1014 complain_overflow_dont,/* complain_on_overflow */
1015 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1016 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1017 FALSE, /* partial_inplace */
1018 0xffffffff, /* src_mask */
1019 0xffffffff, /* dst_mask */
1020 TRUE), /* pcrel_offset */
1021
07d6d2b8 1022 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1023 0, /* rightshift */
1024 2, /* size (0 = byte, 1 = short, 2 = long) */
1025 32, /* bitsize */
1026 TRUE, /* pc_relative */
1027 0, /* bitpos */
1028 complain_overflow_dont,/* complain_on_overflow */
1029 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1030 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1031 FALSE, /* partial_inplace */
1032 0xffffffff, /* src_mask */
1033 0xffffffff, /* dst_mask */
1034 TRUE), /* pcrel_offset */
1035
07d6d2b8 1036 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1037 0, /* rightshift */
1038 2, /* size (0 = byte, 1 = short, 2 = long) */
1039 32, /* bitsize */
1040 TRUE, /* pc_relative */
1041 0, /* bitpos */
1042 complain_overflow_dont,/* complain_on_overflow */
1043 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1044 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1045 FALSE, /* partial_inplace */
1046 0xffffffff, /* src_mask */
1047 0xffffffff, /* dst_mask */
1048 TRUE), /* pcrel_offset */
1049
07d6d2b8 1050 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1051 0, /* rightshift */
1052 2, /* size (0 = byte, 1 = short, 2 = long) */
1053 32, /* bitsize */
1054 TRUE, /* pc_relative */
1055 0, /* bitpos */
1056 complain_overflow_dont,/* complain_on_overflow */
1057 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1058 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1059 FALSE, /* partial_inplace */
1060 0xffffffff, /* src_mask */
1061 0xffffffff, /* dst_mask */
1062 TRUE), /* pcrel_offset */
1063
07d6d2b8 1064 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1065 0, /* rightshift */
1066 2, /* size (0 = byte, 1 = short, 2 = long) */
1067 32, /* bitsize */
1068 TRUE, /* pc_relative */
1069 0, /* bitpos */
1070 complain_overflow_dont,/* complain_on_overflow */
1071 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1072 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1073 FALSE, /* partial_inplace */
1074 0xffffffff, /* src_mask */
1075 0xffffffff, /* dst_mask */
1076 TRUE), /* pcrel_offset */
1077
07d6d2b8 1078 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1079 0, /* rightshift */
1080 2, /* size (0 = byte, 1 = short, 2 = long) */
1081 32, /* bitsize */
1082 TRUE, /* pc_relative */
1083 0, /* bitpos */
1084 complain_overflow_dont,/* complain_on_overflow */
1085 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1086 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1087 FALSE, /* partial_inplace */
1088 0xffffffff, /* src_mask */
1089 0xffffffff, /* dst_mask */
1090 TRUE), /* pcrel_offset */
1091
07d6d2b8 1092 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1093 0, /* rightshift */
1094 2, /* size (0 = byte, 1 = short, 2 = long) */
1095 32, /* bitsize */
1096 TRUE, /* pc_relative */
1097 0, /* bitpos */
1098 complain_overflow_dont,/* complain_on_overflow */
1099 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1100 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1101 FALSE, /* partial_inplace */
1102 0xffffffff, /* src_mask */
1103 0xffffffff, /* dst_mask */
1104 TRUE), /* pcrel_offset */
1105
07d6d2b8 1106 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1107 0, /* rightshift */
1108 2, /* size (0 = byte, 1 = short, 2 = long) */
1109 32, /* bitsize */
1110 TRUE, /* pc_relative */
1111 0, /* bitpos */
1112 complain_overflow_dont,/* complain_on_overflow */
1113 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1114 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1115 FALSE, /* partial_inplace */
1116 0xffffffff, /* src_mask */
1117 0xffffffff, /* dst_mask */
1118 TRUE), /* pcrel_offset */
1119
07d6d2b8 1120 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1121 0, /* rightshift */
1122 2, /* size (0 = byte, 1 = short, 2 = long) */
1123 32, /* bitsize */
1124 TRUE, /* pc_relative */
1125 0, /* bitpos */
1126 complain_overflow_dont,/* complain_on_overflow */
1127 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1128 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1129 FALSE, /* partial_inplace */
1130 0xffffffff, /* src_mask */
1131 0xffffffff, /* dst_mask */
1132 TRUE), /* pcrel_offset */
1133
07d6d2b8 1134 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1135 0, /* rightshift */
1136 2, /* size (0 = byte, 1 = short, 2 = long) */
1137 32, /* bitsize */
1138 TRUE, /* pc_relative */
1139 0, /* bitpos */
1140 complain_overflow_dont,/* complain_on_overflow */
1141 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1142 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1143 FALSE, /* partial_inplace */
1144 0xffffffff, /* src_mask */
1145 0xffffffff, /* dst_mask */
1146 TRUE), /* pcrel_offset */
1147
07d6d2b8 1148 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1149 0, /* rightshift */
1150 2, /* size (0 = byte, 1 = short, 2 = long) */
1151 32, /* bitsize */
1152 TRUE, /* pc_relative */
1153 0, /* bitpos */
1154 complain_overflow_dont,/* complain_on_overflow */
1155 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1156 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1157 FALSE, /* partial_inplace */
1158 0xffffffff, /* src_mask */
1159 0xffffffff, /* dst_mask */
1160 TRUE), /* pcrel_offset */
1161
07d6d2b8 1162 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1163 0, /* rightshift */
1164 2, /* size (0 = byte, 1 = short, 2 = long) */
1165 32, /* bitsize */
1166 TRUE, /* pc_relative */
1167 0, /* bitpos */
1168 complain_overflow_dont,/* complain_on_overflow */
1169 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1170 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1171 FALSE, /* partial_inplace */
1172 0xffffffff, /* src_mask */
1173 0xffffffff, /* dst_mask */
1174 TRUE), /* pcrel_offset */
1175
07d6d2b8 1176 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1177 0, /* rightshift */
1178 2, /* size (0 = byte, 1 = short, 2 = long) */
1179 32, /* bitsize */
1180 TRUE, /* pc_relative */
1181 0, /* bitpos */
1182 complain_overflow_dont,/* complain_on_overflow */
1183 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1184 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1185 FALSE, /* partial_inplace */
1186 0xffffffff, /* src_mask */
1187 0xffffffff, /* dst_mask */
1188 TRUE), /* pcrel_offset */
1189
07d6d2b8 1190 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1191 0, /* rightshift */
1192 2, /* size (0 = byte, 1 = short, 2 = long) */
1193 32, /* bitsize */
1194 TRUE, /* pc_relative */
1195 0, /* bitpos */
1196 complain_overflow_dont,/* complain_on_overflow */
1197 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1198 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1199 FALSE, /* partial_inplace */
1200 0xffffffff, /* src_mask */
1201 0xffffffff, /* dst_mask */
1202 TRUE), /* pcrel_offset */
1203
07d6d2b8 1204 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1205 0, /* rightshift */
1206 2, /* size (0 = byte, 1 = short, 2 = long) */
1207 32, /* bitsize */
1208 TRUE, /* pc_relative */
1209 0, /* bitpos */
1210 complain_overflow_dont,/* complain_on_overflow */
1211 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1212 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1213 FALSE, /* partial_inplace */
1214 0xffffffff, /* src_mask */
1215 0xffffffff, /* dst_mask */
1216 TRUE), /* pcrel_offset */
1217
07d6d2b8 1218 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1219 0, /* rightshift */
1220 2, /* size (0 = byte, 1 = short, 2 = long) */
1221 32, /* bitsize */
1222 TRUE, /* pc_relative */
1223 0, /* bitpos */
1224 complain_overflow_dont,/* complain_on_overflow */
1225 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1226 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1227 FALSE, /* partial_inplace */
1228 0xffffffff, /* src_mask */
1229 0xffffffff, /* dst_mask */
1230 TRUE), /* pcrel_offset */
1231
07d6d2b8 1232 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1233 0, /* rightshift */
1234 2, /* size (0 = byte, 1 = short, 2 = long) */
1235 32, /* bitsize */
1236 TRUE, /* pc_relative */
1237 0, /* bitpos */
1238 complain_overflow_dont,/* complain_on_overflow */
1239 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1240 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1241 FALSE, /* partial_inplace */
1242 0xffffffff, /* src_mask */
1243 0xffffffff, /* dst_mask */
1244 TRUE), /* pcrel_offset */
1245
07d6d2b8 1246 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1247 0, /* rightshift */
1248 2, /* size (0 = byte, 1 = short, 2 = long) */
1249 32, /* bitsize */
1250 TRUE, /* pc_relative */
1251 0, /* bitpos */
1252 complain_overflow_dont,/* complain_on_overflow */
1253 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1254 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1255 FALSE, /* partial_inplace */
1256 0xffffffff, /* src_mask */
1257 0xffffffff, /* dst_mask */
1258 TRUE), /* pcrel_offset */
1259
07d6d2b8 1260 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1261 0, /* rightshift */
1262 2, /* size (0 = byte, 1 = short, 2 = long) */
1263 32, /* bitsize */
1264 TRUE, /* pc_relative */
1265 0, /* bitpos */
1266 complain_overflow_dont,/* complain_on_overflow */
1267 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1268 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1269 FALSE, /* partial_inplace */
1270 0xffffffff, /* src_mask */
1271 0xffffffff, /* dst_mask */
1272 TRUE), /* pcrel_offset */
1273
1274 /* End of group relocations. */
c19d1205 1275
c19d1205
ZW		 1276 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1277 0, /* rightshift */
1278 2, /* size (0 = byte, 1 = short, 2 = long) */
1279 16, /* bitsize */
1280 FALSE, /* pc_relative */
1281 0, /* bitpos */
1282 complain_overflow_dont,/* complain_on_overflow */
1283 bfd_elf_generic_reloc, /* special_function */
1284 "R_ARM_MOVW_BREL_NC", /* name */
1285 FALSE, /* partial_inplace */
1286 0x0000ffff, /* src_mask */
1287 0x0000ffff, /* dst_mask */
1288 FALSE), /* pcrel_offset */
1289
1290 HOWTO (R_ARM_MOVT_BREL, /* type */
1291 0, /* rightshift */
1292 2, /* size (0 = byte, 1 = short, 2 = long) */
1293 16, /* bitsize */
1294 FALSE, /* pc_relative */
1295 0, /* bitpos */
1296 complain_overflow_bitfield,/* complain_on_overflow */
1297 bfd_elf_generic_reloc, /* special_function */
1298 "R_ARM_MOVT_BREL", /* name */
1299 FALSE, /* partial_inplace */
1300 0x0000ffff, /* src_mask */
1301 0x0000ffff, /* dst_mask */
1302 FALSE), /* pcrel_offset */
1303
1304 HOWTO (R_ARM_MOVW_BREL, /* type */
1305 0, /* rightshift */
1306 2, /* size (0 = byte, 1 = short, 2 = long) */
1307 16, /* bitsize */
1308 FALSE, /* pc_relative */
1309 0, /* bitpos */
1310 complain_overflow_dont,/* complain_on_overflow */
1311 bfd_elf_generic_reloc, /* special_function */
1312 "R_ARM_MOVW_BREL", /* name */
1313 FALSE, /* partial_inplace */
1314 0x0000ffff, /* src_mask */
1315 0x0000ffff, /* dst_mask */
1316 FALSE), /* pcrel_offset */
1317
1318 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1319 0, /* rightshift */
1320 2, /* size (0 = byte, 1 = short, 2 = long) */
1321 16, /* bitsize */
1322 FALSE, /* pc_relative */
1323 0, /* bitpos */
1324 complain_overflow_dont,/* complain_on_overflow */
1325 bfd_elf_generic_reloc, /* special_function */
1326 "R_ARM_THM_MOVW_BREL_NC",/* name */
1327 FALSE, /* partial_inplace */
1328 0x040f70ff, /* src_mask */
1329 0x040f70ff, /* dst_mask */
1330 FALSE), /* pcrel_offset */
1331
1332 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1333 0, /* rightshift */
1334 2, /* size (0 = byte, 1 = short, 2 = long) */
1335 16, /* bitsize */
1336 FALSE, /* pc_relative */
1337 0, /* bitpos */
1338 complain_overflow_bitfield,/* complain_on_overflow */
1339 bfd_elf_generic_reloc, /* special_function */
1340 "R_ARM_THM_MOVT_BREL", /* name */
1341 FALSE, /* partial_inplace */
1342 0x040f70ff, /* src_mask */
1343 0x040f70ff, /* dst_mask */
1344 FALSE), /* pcrel_offset */
1345
1346 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1347 0, /* rightshift */
1348 2, /* size (0 = byte, 1 = short, 2 = long) */
1349 16, /* bitsize */
1350 FALSE, /* pc_relative */
1351 0, /* bitpos */
1352 complain_overflow_dont,/* complain_on_overflow */
1353 bfd_elf_generic_reloc, /* special_function */
1354 "R_ARM_THM_MOVW_BREL", /* name */
1355 FALSE, /* partial_inplace */
1356 0x040f70ff, /* src_mask */
1357 0x040f70ff, /* dst_mask */
1358 FALSE), /* pcrel_offset */
1359
0855e32b
NS		 1360 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1361 0, /* rightshift */
1362 2, /* size (0 = byte, 1 = short, 2 = long) */
1363 32, /* bitsize */
1364 FALSE, /* pc_relative */
1365 0, /* bitpos */
1366 complain_overflow_bitfield,/* complain_on_overflow */
1367 NULL, /* special_function */
1368 "R_ARM_TLS_GOTDESC", /* name */
1369 TRUE, /* partial_inplace */
1370 0xffffffff, /* src_mask */
1371 0xffffffff, /* dst_mask */
1372 FALSE), /* pcrel_offset */
1373
1374 HOWTO (R_ARM_TLS_CALL, /* type */
1375 0, /* rightshift */
1376 2, /* size (0 = byte, 1 = short, 2 = long) */
1377 24, /* bitsize */
1378 FALSE, /* pc_relative */
1379 0, /* bitpos */
1380 complain_overflow_dont,/* complain_on_overflow */
1381 bfd_elf_generic_reloc, /* special_function */
1382 "R_ARM_TLS_CALL", /* name */
1383 FALSE, /* partial_inplace */
1384 0x00ffffff, /* src_mask */
1385 0x00ffffff, /* dst_mask */
1386 FALSE), /* pcrel_offset */
1387
1388 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1389 0, /* rightshift */
1390 2, /* size (0 = byte, 1 = short, 2 = long) */
1391 0, /* bitsize */
1392 FALSE, /* pc_relative */
1393 0, /* bitpos */
1394 complain_overflow_bitfield,/* complain_on_overflow */
1395 bfd_elf_generic_reloc, /* special_function */
1396 "R_ARM_TLS_DESCSEQ", /* name */
1397 FALSE, /* partial_inplace */
1398 0x00000000, /* src_mask */
1399 0x00000000, /* dst_mask */
1400 FALSE), /* pcrel_offset */
1401
1402 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1403 0, /* rightshift */
1404 2, /* size (0 = byte, 1 = short, 2 = long) */
1405 24, /* bitsize */
1406 FALSE, /* pc_relative */
1407 0, /* bitpos */
1408 complain_overflow_dont,/* complain_on_overflow */
1409 bfd_elf_generic_reloc, /* special_function */
1410 "R_ARM_THM_TLS_CALL", /* name */
1411 FALSE, /* partial_inplace */
1412 0x07ff07ff, /* src_mask */
1413 0x07ff07ff, /* dst_mask */
1414 FALSE), /* pcrel_offset */
c19d1205
ZW		 1415
1416 HOWTO (R_ARM_PLT32_ABS, /* type */
1417 0, /* rightshift */
1418 2, /* size (0 = byte, 1 = short, 2 = long) */
1419 32, /* bitsize */
1420 FALSE, /* pc_relative */
1421 0, /* bitpos */
1422 complain_overflow_dont,/* complain_on_overflow */
1423 bfd_elf_generic_reloc, /* special_function */
1424 "R_ARM_PLT32_ABS", /* name */
1425 FALSE, /* partial_inplace */
1426 0xffffffff, /* src_mask */
1427 0xffffffff, /* dst_mask */
1428 FALSE), /* pcrel_offset */
1429
1430 HOWTO (R_ARM_GOT_ABS, /* type */
1431 0, /* rightshift */
1432 2, /* size (0 = byte, 1 = short, 2 = long) */
1433 32, /* bitsize */
1434 FALSE, /* pc_relative */
1435 0, /* bitpos */
1436 complain_overflow_dont,/* complain_on_overflow */
1437 bfd_elf_generic_reloc, /* special_function */
1438 "R_ARM_GOT_ABS", /* name */
1439 FALSE, /* partial_inplace */
1440 0xffffffff, /* src_mask */
1441 0xffffffff, /* dst_mask */
1442 FALSE), /* pcrel_offset */
1443
1444 HOWTO (R_ARM_GOT_PREL, /* type */
1445 0, /* rightshift */
1446 2, /* size (0 = byte, 1 = short, 2 = long) */
1447 32, /* bitsize */
1448 TRUE, /* pc_relative */
1449 0, /* bitpos */
1450 complain_overflow_dont, /* complain_on_overflow */
1451 bfd_elf_generic_reloc, /* special_function */
1452 "R_ARM_GOT_PREL", /* name */
1453 FALSE, /* partial_inplace */
1454 0xffffffff, /* src_mask */
1455 0xffffffff, /* dst_mask */
1456 TRUE), /* pcrel_offset */
1457
1458 HOWTO (R_ARM_GOT_BREL12, /* type */
1459 0, /* rightshift */
1460 2, /* size (0 = byte, 1 = short, 2 = long) */
1461 12, /* bitsize */
1462 FALSE, /* pc_relative */
1463 0, /* bitpos */
1464 complain_overflow_bitfield,/* complain_on_overflow */
1465 bfd_elf_generic_reloc, /* special_function */
1466 "R_ARM_GOT_BREL12", /* name */
1467 FALSE, /* partial_inplace */
1468 0x00000fff, /* src_mask */
1469 0x00000fff, /* dst_mask */
1470 FALSE), /* pcrel_offset */
1471
1472 HOWTO (R_ARM_GOTOFF12, /* type */
1473 0, /* rightshift */
1474 2, /* size (0 = byte, 1 = short, 2 = long) */
1475 12, /* bitsize */
1476 FALSE, /* pc_relative */
1477 0, /* bitpos */
1478 complain_overflow_bitfield,/* complain_on_overflow */
1479 bfd_elf_generic_reloc, /* special_function */
1480 "R_ARM_GOTOFF12", /* name */
1481 FALSE, /* partial_inplace */
1482 0x00000fff, /* src_mask */
1483 0x00000fff, /* dst_mask */
1484 FALSE), /* pcrel_offset */
1485
07d6d2b8 1486 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1487
1488 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1489 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1490 0, /* rightshift */
1491 2, /* size (0 = byte, 1 = short, 2 = long) */
1492 0, /* bitsize */
1493 FALSE, /* pc_relative */
1494 0, /* bitpos */
99059e56 1495 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1496 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1497 "R_ARM_GNU_VTENTRY", /* name */
1498 FALSE, /* partial_inplace */
1499 0, /* src_mask */
1500 0, /* dst_mask */
1501 FALSE), /* pcrel_offset */
c19d1205
ZW		 1502
1503 /* GNU extension to record C++ vtable hierarchy */
1504 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1505 0, /* rightshift */
1506 2, /* size (0 = byte, 1 = short, 2 = long) */
1507 0, /* bitsize */
1508 FALSE, /* pc_relative */
1509 0, /* bitpos */
99059e56 1510 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1511 NULL, /* special_function */
99059e56 1512 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1513 FALSE, /* partial_inplace */
1514 0, /* src_mask */
1515 0, /* dst_mask */
1516 FALSE), /* pcrel_offset */
c19d1205
ZW		 1517
1518 HOWTO (R_ARM_THM_JUMP11, /* type */
1519 1, /* rightshift */
1520 1, /* size (0 = byte, 1 = short, 2 = long) */
1521 11, /* bitsize */
1522 TRUE, /* pc_relative */
1523 0, /* bitpos */
1524 complain_overflow_signed, /* complain_on_overflow */
1525 bfd_elf_generic_reloc, /* special_function */
1526 "R_ARM_THM_JUMP11", /* name */
1527 FALSE, /* partial_inplace */
1528 0x000007ff, /* src_mask */
1529 0x000007ff, /* dst_mask */
1530 TRUE), /* pcrel_offset */
1531
1532 HOWTO (R_ARM_THM_JUMP8, /* type */
1533 1, /* rightshift */
1534 1, /* size (0 = byte, 1 = short, 2 = long) */
1535 8, /* bitsize */
1536 TRUE, /* pc_relative */
1537 0, /* bitpos */
1538 complain_overflow_signed, /* complain_on_overflow */
1539 bfd_elf_generic_reloc, /* special_function */
1540 "R_ARM_THM_JUMP8", /* name */
1541 FALSE, /* partial_inplace */
1542 0x000000ff, /* src_mask */
1543 0x000000ff, /* dst_mask */
1544 TRUE), /* pcrel_offset */
ba93b8ac 1545
c19d1205
ZW		 1546 /* TLS relocations */
1547 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1548 0, /* rightshift */
1549 2, /* size (0 = byte, 1 = short, 2 = long) */
1550 32, /* bitsize */
1551 FALSE, /* pc_relative */
1552 0, /* bitpos */
99059e56
RM		 1553 complain_overflow_bitfield,/* complain_on_overflow */
1554 NULL, /* special_function */
1555 "R_ARM_TLS_GD32", /* name */
1556 TRUE, /* partial_inplace */
1557 0xffffffff, /* src_mask */
1558 0xffffffff, /* dst_mask */
07d6d2b8 1559 FALSE), /* pcrel_offset */
ba93b8ac 1560
ba93b8ac 1561 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1562 0, /* rightshift */
1563 2, /* size (0 = byte, 1 = short, 2 = long) */
1564 32, /* bitsize */
1565 FALSE, /* pc_relative */
1566 0, /* bitpos */
99059e56
RM		 1567 complain_overflow_bitfield,/* complain_on_overflow */
1568 bfd_elf_generic_reloc, /* special_function */
1569 "R_ARM_TLS_LDM32", /* name */
1570 TRUE, /* partial_inplace */
1571 0xffffffff, /* src_mask */
1572 0xffffffff, /* dst_mask */
07d6d2b8 1573 FALSE), /* pcrel_offset */
ba93b8ac 1574
c19d1205 1575 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1576 0, /* rightshift */
1577 2, /* size (0 = byte, 1 = short, 2 = long) */
1578 32, /* bitsize */
1579 FALSE, /* pc_relative */
1580 0, /* bitpos */
99059e56
RM		 1581 complain_overflow_bitfield,/* complain_on_overflow */
1582 bfd_elf_generic_reloc, /* special_function */
1583 "R_ARM_TLS_LDO32", /* name */
1584 TRUE, /* partial_inplace */
1585 0xffffffff, /* src_mask */
1586 0xffffffff, /* dst_mask */
07d6d2b8 1587 FALSE), /* pcrel_offset */
ba93b8ac 1588
ba93b8ac 1589 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1590 0, /* rightshift */
1591 2, /* size (0 = byte, 1 = short, 2 = long) */
1592 32, /* bitsize */
1593 FALSE, /* pc_relative */
1594 0, /* bitpos */
99059e56
RM		 1595 complain_overflow_bitfield,/* complain_on_overflow */
1596 NULL, /* special_function */
1597 "R_ARM_TLS_IE32", /* name */
1598 TRUE, /* partial_inplace */
1599 0xffffffff, /* src_mask */
1600 0xffffffff, /* dst_mask */
07d6d2b8 1601 FALSE), /* pcrel_offset */
7f266840 1602
c19d1205 1603 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1604 0, /* rightshift */
1605 2, /* size (0 = byte, 1 = short, 2 = long) */
1606 32, /* bitsize */
1607 FALSE, /* pc_relative */
1608 0, /* bitpos */
99059e56 1609 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1610 NULL, /* special_function */
99059e56
RM		 1611 "R_ARM_TLS_LE32", /* name */
1612 TRUE, /* partial_inplace */
1613 0xffffffff, /* src_mask */
1614 0xffffffff, /* dst_mask */
07d6d2b8 1615 FALSE), /* pcrel_offset */
7f266840 1616
c19d1205
ZW		 1617 HOWTO (R_ARM_TLS_LDO12, /* type */
1618 0, /* rightshift */
1619 2, /* size (0 = byte, 1 = short, 2 = long) */
1620 12, /* bitsize */
1621 FALSE, /* pc_relative */
7f266840 1622 0, /* bitpos */
c19d1205 1623 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1624 bfd_elf_generic_reloc, /* special_function */
c19d1205 1625 "R_ARM_TLS_LDO12", /* name */
7f266840 1626 FALSE, /* partial_inplace */
c19d1205
ZW		 1627 0x00000fff, /* src_mask */
1628 0x00000fff, /* dst_mask */
1629 FALSE), /* pcrel_offset */
7f266840 1630
c19d1205
ZW		 1631 HOWTO (R_ARM_TLS_LE12, /* type */
1632 0, /* rightshift */
1633 2, /* size (0 = byte, 1 = short, 2 = long) */
1634 12, /* bitsize */
1635 FALSE, /* pc_relative */
7f266840 1636 0, /* bitpos */
c19d1205 1637 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1638 bfd_elf_generic_reloc, /* special_function */
c19d1205 1639 "R_ARM_TLS_LE12", /* name */
7f266840 1640 FALSE, /* partial_inplace */
c19d1205
ZW		 1641 0x00000fff, /* src_mask */
1642 0x00000fff, /* dst_mask */
1643 FALSE), /* pcrel_offset */
7f266840 1644
c19d1205 1645 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1646 0, /* rightshift */
1647 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1648 12, /* bitsize */
1649 FALSE, /* pc_relative */
7f266840 1650 0, /* bitpos */
c19d1205 1651 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1652 bfd_elf_generic_reloc, /* special_function */
c19d1205 1653 "R_ARM_TLS_IE12GP", /* name */
7f266840 1654 FALSE, /* partial_inplace */
c19d1205
ZW		 1655 0x00000fff, /* src_mask */
1656 0x00000fff, /* dst_mask */
1657 FALSE), /* pcrel_offset */
0855e32b 1658
34e77a92 1659 /* 112-127 private relocations. */
0855e32b
NS		 1660 EMPTY_HOWTO (112),
1661 EMPTY_HOWTO (113),
1662 EMPTY_HOWTO (114),
1663 EMPTY_HOWTO (115),
1664 EMPTY_HOWTO (116),
1665 EMPTY_HOWTO (117),
1666 EMPTY_HOWTO (118),
1667 EMPTY_HOWTO (119),
1668 EMPTY_HOWTO (120),
1669 EMPTY_HOWTO (121),
1670 EMPTY_HOWTO (122),
1671 EMPTY_HOWTO (123),
1672 EMPTY_HOWTO (124),
1673 EMPTY_HOWTO (125),
1674 EMPTY_HOWTO (126),
1675 EMPTY_HOWTO (127),
34e77a92
RS		 1676
1677 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1678 EMPTY_HOWTO (128),
1679
1680 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1681 0, /* rightshift */
1682 1, /* size (0 = byte, 1 = short, 2 = long) */
1683 0, /* bitsize */
1684 FALSE, /* pc_relative */
1685 0, /* bitpos */
1686 complain_overflow_bitfield,/* complain_on_overflow */
1687 bfd_elf_generic_reloc, /* special_function */
1688 "R_ARM_THM_TLS_DESCSEQ",/* name */
1689 FALSE, /* partial_inplace */
1690 0x00000000, /* src_mask */
1691 0x00000000, /* dst_mask */
1692 FALSE), /* pcrel_offset */
72d98d16
MG		 1693 EMPTY_HOWTO (130),
1694 EMPTY_HOWTO (131),
1695 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1696 0, /* rightshift. */
1697 1, /* size (0 = byte, 1 = short, 2 = long). */
1698 16, /* bitsize. */
1699 FALSE, /* pc_relative. */
1700 0, /* bitpos. */
1701 complain_overflow_bitfield,/* complain_on_overflow. */
1702 bfd_elf_generic_reloc, /* special_function. */
1703 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1704 FALSE, /* partial_inplace. */
1705 0x00000000, /* src_mask. */
1706 0x00000000, /* dst_mask. */
1707 FALSE), /* pcrel_offset. */
1708 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1709 0, /* rightshift. */
1710 1, /* size (0 = byte, 1 = short, 2 = long). */
1711 16, /* bitsize. */
1712 FALSE, /* pc_relative. */
1713 0, /* bitpos. */
1714 complain_overflow_bitfield,/* complain_on_overflow. */
1715 bfd_elf_generic_reloc, /* special_function. */
1716 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1717 FALSE, /* partial_inplace. */
1718 0x00000000, /* src_mask. */
1719 0x00000000, /* dst_mask. */
1720 FALSE), /* pcrel_offset. */
1721 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1722 0, /* rightshift. */
1723 1, /* size (0 = byte, 1 = short, 2 = long). */
1724 16, /* bitsize. */
1725 FALSE, /* pc_relative. */
1726 0, /* bitpos. */
1727 complain_overflow_bitfield,/* complain_on_overflow. */
1728 bfd_elf_generic_reloc, /* special_function. */
1729 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1730 FALSE, /* partial_inplace. */
1731 0x00000000, /* src_mask. */
1732 0x00000000, /* dst_mask. */
1733 FALSE), /* pcrel_offset. */
1734 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1735 0, /* rightshift. */
1736 1, /* size (0 = byte, 1 = short, 2 = long). */
1737 16, /* bitsize. */
1738 FALSE, /* pc_relative. */
1739 0, /* bitpos. */
1740 complain_overflow_bitfield,/* complain_on_overflow. */
1741 bfd_elf_generic_reloc, /* special_function. */
1742 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1743 FALSE, /* partial_inplace. */
1744 0x00000000, /* src_mask. */
1745 0x00000000, /* dst_mask. */
1746 FALSE), /* pcrel_offset. */
e5d6e09e
AV		 1747 /* Relocations for Armv8.1-M Mainline. */
1748 HOWTO (R_ARM_THM_BF16, /* type. */
1749 0, /* rightshift. */
1750 1, /* size (0 = byte, 1 = short, 2 = long). */
1751 16, /* bitsize. */
1752 TRUE, /* pc_relative. */
1753 0, /* bitpos. */
1754 complain_overflow_dont,/* do not complain_on_overflow. */
1755 bfd_elf_generic_reloc, /* special_function. */
1756 "R_ARM_THM_BF16", /* name. */
1757 FALSE, /* partial_inplace. */
1758 0x001f0ffe, /* src_mask. */
1759 0x001f0ffe, /* dst_mask. */
1760 TRUE), /* pcrel_offset. */
1889da70
AV		 1761 HOWTO (R_ARM_THM_BF12, /* type. */
1762 0, /* rightshift. */
1763 1, /* size (0 = byte, 1 = short, 2 = long). */
1764 12, /* bitsize. */
1765 TRUE, /* pc_relative. */
1766 0, /* bitpos. */
1767 complain_overflow_dont,/* do not complain_on_overflow. */
1768 bfd_elf_generic_reloc, /* special_function. */
1769 "R_ARM_THM_BF12", /* name. */
1770 FALSE, /* partial_inplace. */
1771 0x00010ffe, /* src_mask. */
1772 0x00010ffe, /* dst_mask. */
1773 TRUE), /* pcrel_offset. */
1caf72a5
AV		 1774 HOWTO (R_ARM_THM_BF18, /* type. */
1775 0, /* rightshift. */
1776 1, /* size (0 = byte, 1 = short, 2 = long). */
1777 18, /* bitsize. */
1778 TRUE, /* pc_relative. */
1779 0, /* bitpos. */
1780 complain_overflow_dont,/* do not complain_on_overflow. */
1781 bfd_elf_generic_reloc, /* special_function. */
1782 "R_ARM_THM_BF18", /* name. */
1783 FALSE, /* partial_inplace. */
1784 0x007f0ffe, /* src_mask. */
1785 0x007f0ffe, /* dst_mask. */
1786 TRUE), /* pcrel_offset. */
c19d1205
ZW		 1787};
1788
34e77a92 1789/* 160 onwards: */
5c5a4843 1790static reloc_howto_type elf32_arm_howto_table_2[8] =
34e77a92
RS		 1791{
1792 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1793 0, /* rightshift */
1794 2, /* size (0 = byte, 1 = short, 2 = long) */
1795 32, /* bitsize */
1796 FALSE, /* pc_relative */
1797 0, /* bitpos */
99059e56
RM		 1798 complain_overflow_bitfield,/* complain_on_overflow */
1799 bfd_elf_generic_reloc, /* special_function */
1800 "R_ARM_IRELATIVE", /* name */
1801 TRUE, /* partial_inplace */
1802 0xffffffff, /* src_mask */
1803 0xffffffff, /* dst_mask */
188fd7ae
CL		 1804 FALSE), /* pcrel_offset */
1805 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1806 0, /* rightshift */
1807 2, /* size (0 = byte, 1 = short, 2 = long) */
1808 32, /* bitsize */
1809 FALSE, /* pc_relative */
1810 0, /* bitpos */
1811 complain_overflow_bitfield,/* complain_on_overflow */
1812 bfd_elf_generic_reloc, /* special_function */
1813 "R_ARM_GOTFUNCDESC", /* name */
1814 FALSE, /* partial_inplace */
1815 0, /* src_mask */
1816 0xffffffff, /* dst_mask */
1817 FALSE), /* pcrel_offset */
1818 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1819 0, /* rightshift */
1820 2, /* size (0 = byte, 1 = short, 2 = long) */
1821 32, /* bitsize */
1822 FALSE, /* pc_relative */
1823 0, /* bitpos */
1824 complain_overflow_bitfield,/* complain_on_overflow */
1825 bfd_elf_generic_reloc, /* special_function */
1826 "R_ARM_GOTOFFFUNCDESC",/* name */
1827 FALSE, /* partial_inplace */
1828 0, /* src_mask */
1829 0xffffffff, /* dst_mask */
1830 FALSE), /* pcrel_offset */
1831 HOWTO (R_ARM_FUNCDESC, /* type */
1832 0, /* rightshift */
1833 2, /* size (0 = byte, 1 = short, 2 = long) */
1834 32, /* bitsize */
1835 FALSE, /* pc_relative */
1836 0, /* bitpos */
1837 complain_overflow_bitfield,/* complain_on_overflow */
1838 bfd_elf_generic_reloc, /* special_function */
1839 "R_ARM_FUNCDESC", /* name */
1840 FALSE, /* partial_inplace */
1841 0, /* src_mask */
1842 0xffffffff, /* dst_mask */
1843 FALSE), /* pcrel_offset */
1844 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1845 0, /* rightshift */
1846 2, /* size (0 = byte, 1 = short, 2 = long) */
1847 64, /* bitsize */
1848 FALSE, /* pc_relative */
1849 0, /* bitpos */
1850 complain_overflow_bitfield,/* complain_on_overflow */
1851 bfd_elf_generic_reloc, /* special_function */
1852 "R_ARM_FUNCDESC_VALUE",/* name */
1853 FALSE, /* partial_inplace */
1854 0, /* src_mask */
1855 0xffffffff, /* dst_mask */
1856 FALSE), /* pcrel_offset */
5c5a4843
CL		 1857 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1858 0, /* rightshift */
1859 2, /* size (0 = byte, 1 = short, 2 = long) */
1860 32, /* bitsize */
1861 FALSE, /* pc_relative */
1862 0, /* bitpos */
1863 complain_overflow_bitfield,/* complain_on_overflow */
1864 bfd_elf_generic_reloc, /* special_function */
1865 "R_ARM_TLS_GD32_FDPIC",/* name */
1866 FALSE, /* partial_inplace */
1867 0, /* src_mask */
1868 0xffffffff, /* dst_mask */
1869 FALSE), /* pcrel_offset */
1870 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1871 0, /* rightshift */
1872 2, /* size (0 = byte, 1 = short, 2 = long) */
1873 32, /* bitsize */
1874 FALSE, /* pc_relative */
1875 0, /* bitpos */
1876 complain_overflow_bitfield,/* complain_on_overflow */
1877 bfd_elf_generic_reloc, /* special_function */
1878 "R_ARM_TLS_LDM32_FDPIC",/* name */
1879 FALSE, /* partial_inplace */
1880 0, /* src_mask */
1881 0xffffffff, /* dst_mask */
1882 FALSE), /* pcrel_offset */
1883 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1884 0, /* rightshift */
1885 2, /* size (0 = byte, 1 = short, 2 = long) */
1886 32, /* bitsize */
1887 FALSE, /* pc_relative */
1888 0, /* bitpos */
1889 complain_overflow_bitfield,/* complain_on_overflow */
1890 bfd_elf_generic_reloc, /* special_function */
1891 "R_ARM_TLS_IE32_FDPIC",/* name */
1892 FALSE, /* partial_inplace */
1893 0, /* src_mask */
1894 0xffffffff, /* dst_mask */
1895 FALSE), /* pcrel_offset */
34e77a92 1896};
c19d1205 1897
34e77a92
RS		 1898/* 249-255 extended, currently unused, relocations: */
1899static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1900{
1901 HOWTO (R_ARM_RREL32, /* type */
1902 0, /* rightshift */
1903 0, /* size (0 = byte, 1 = short, 2 = long) */
1904 0, /* bitsize */
1905 FALSE, /* pc_relative */
1906 0, /* bitpos */
1907 complain_overflow_dont,/* complain_on_overflow */
1908 bfd_elf_generic_reloc, /* special_function */
1909 "R_ARM_RREL32", /* name */
1910 FALSE, /* partial_inplace */
1911 0, /* src_mask */
1912 0, /* dst_mask */
1913 FALSE), /* pcrel_offset */
1914
1915 HOWTO (R_ARM_RABS32, /* type */
1916 0, /* rightshift */
1917 0, /* size (0 = byte, 1 = short, 2 = long) */
1918 0, /* bitsize */
1919 FALSE, /* pc_relative */
1920 0, /* bitpos */
1921 complain_overflow_dont,/* complain_on_overflow */
1922 bfd_elf_generic_reloc, /* special_function */
1923 "R_ARM_RABS32", /* name */
1924 FALSE, /* partial_inplace */
1925 0, /* src_mask */
1926 0, /* dst_mask */
1927 FALSE), /* pcrel_offset */
1928
1929 HOWTO (R_ARM_RPC24, /* type */
1930 0, /* rightshift */
1931 0, /* size (0 = byte, 1 = short, 2 = long) */
1932 0, /* bitsize */
1933 FALSE, /* pc_relative */
1934 0, /* bitpos */
1935 complain_overflow_dont,/* complain_on_overflow */
1936 bfd_elf_generic_reloc, /* special_function */
1937 "R_ARM_RPC24", /* name */
1938 FALSE, /* partial_inplace */
1939 0, /* src_mask */
1940 0, /* dst_mask */
1941 FALSE), /* pcrel_offset */
1942
1943 HOWTO (R_ARM_RBASE, /* type */
1944 0, /* rightshift */
1945 0, /* size (0 = byte, 1 = short, 2 = long) */
1946 0, /* bitsize */
1947 FALSE, /* pc_relative */
1948 0, /* bitpos */
1949 complain_overflow_dont,/* complain_on_overflow */
1950 bfd_elf_generic_reloc, /* special_function */
1951 "R_ARM_RBASE", /* name */
1952 FALSE, /* partial_inplace */
1953 0, /* src_mask */
1954 0, /* dst_mask */
1955 FALSE) /* pcrel_offset */
1956};
1957
1958static reloc_howto_type *
1959elf32_arm_howto_from_type (unsigned int r_type)
1960{
906e58ca 1961 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1962 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1963
188fd7ae
CL		 1964 if (r_type >= R_ARM_IRELATIVE
1965 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1966 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1967
c19d1205 1968 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1969 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1970 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1971
c19d1205 1972 return NULL;
7f266840
DJ		 1973}
1974
f3185997
NC		 1975static bfd_boolean
1976elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1977 Elf_Internal_Rela * elf_reloc)
1978{
1979 unsigned int r_type;
1980
1981 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1982 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1983 {
1984 /* xgettext:c-format */
1985 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1986 abfd, r_type);
1987 bfd_set_error (bfd_error_bad_value);
1988 return FALSE;
1989 }
1990 return TRUE;
7f266840
DJ		 1991}
1992
1993struct elf32_arm_reloc_map
1994 {
1995 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1996 unsigned char elf_reloc_val;
7f266840
DJ		 1997 };
1998
1999/* All entries in this list must also be present in elf32_arm_howto_table. */
2000static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
2001 {
07d6d2b8 2002 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 2003 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 2004 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
2005 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 2006 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
2007 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
2008 {BFD_RELOC_32, R_ARM_ABS32},
2009 {BFD_RELOC_32_PCREL, R_ARM_REL32},
2010 {BFD_RELOC_8, R_ARM_ABS8},
2011 {BFD_RELOC_16, R_ARM_ABS16},
2012 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 2013 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 2014 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
2015 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
2016 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
2017 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
2018 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
2019 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 2020 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
2021 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
2022 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
2023 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
2024 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
2025 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
2026 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
2027 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 2028 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
2029 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
2030 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
2031 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 2032 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 2033 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
2034 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
2035 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 2036 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 2037 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 2038 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 2039 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 2040 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
2041 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2042 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2043 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2044 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 2045 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2046 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2047 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2048 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 2049 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2050 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2051 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2052 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
5c5a4843
CL		 2053 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2054 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2055 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
c19d1205
ZW		 2056 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2057 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 2058 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2059 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2060 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2061 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2062 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2063 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2064 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2065 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 2066 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2067 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2068 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2069 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2070 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2071 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2072 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2073 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2074 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2075 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2076 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2077 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2078 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2079 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2080 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2081 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2082 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2083 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2084 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2085 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2086 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2087 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2088 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2089 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2090 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2091 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2092 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2093 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2094 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2095 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2096 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2097 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
e5d6e09e 2098 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
1caf72a5 2099 {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16},
1889da70 2100 {BFD_RELOC_ARM_THUMB_BF13, R_ARM_THM_BF12},
1caf72a5 2101 {BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18}
7f266840
DJ		 2102 };
2103
2104static reloc_howto_type *
f1c71a59
ZW		 2105elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2106 bfd_reloc_code_real_type code)
7f266840
DJ		 2107{
2108 unsigned int i;
8029a119 2109
906e58ca 2110 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2111 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2112 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2113
c19d1205 2114 return NULL;
7f266840
DJ		 2115}
2116
157090f7
AM		 2117static reloc_howto_type *
2118elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2119 const char *r_name)
2120{
2121 unsigned int i;
2122
906e58ca 2123 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2124 if (elf32_arm_howto_table_1[i].name != NULL
2125 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2126 return &elf32_arm_howto_table_1[i];
2127
906e58ca 2128 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2129 if (elf32_arm_howto_table_2[i].name != NULL
2130 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2131 return &elf32_arm_howto_table_2[i];
2132
34e77a92
RS		 2133 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2134 if (elf32_arm_howto_table_3[i].name != NULL
2135 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2136 return &elf32_arm_howto_table_3[i];
2137
157090f7
AM		 2138 return NULL;
2139}
2140
906e58ca
NC		 2141/* Support for core dump NOTE sections. */
2142
7f266840 2143static bfd_boolean
f1c71a59 2144elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2145{
2146 int offset;
2147 size_t size;
2148
2149 switch (note->descsz)
2150 {
2151 default:
2152 return FALSE;
2153
8029a119 2154 case 148: /* Linux/ARM 32-bit. */
7f266840 2155 /* pr_cursig */
228e534f 2156 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2157
2158 /* pr_pid */
228e534f 2159 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2160
2161 /* pr_reg */
2162 offset = 72;
2163 size = 72;
2164
2165 break;
2166 }
2167
2168 /* Make a ".reg/999" section. */
2169 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2170 size, note->descpos + offset);
2171}
2172
2173static bfd_boolean
f1c71a59 2174elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2175{
2176 switch (note->descsz)
2177 {
2178 default:
2179 return FALSE;
2180
8029a119 2181 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2182 elf_tdata (abfd)->core->pid
4395ee08 2183 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2184 elf_tdata (abfd)->core->program
7f266840 2185 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2186 elf_tdata (abfd)->core->command
7f266840
DJ		 2187 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2188 }
2189
2190 /* Note that for some reason, a spurious space is tacked
2191 onto the end of the args in some (at least one anyway)
2192 implementations, so strip it off if it exists. */
7f266840 2193 {
228e534f 2194 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2195 int n = strlen (command);
2196
2197 if (0 < n && command[n - 1] == ' ')
2198 command[n - 1] = '\0';
2199 }
2200
2201 return TRUE;
2202}
2203
1f20dca5
UW		 2204static char *
2205elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2206 int note_type, ...)
2207{
2208 switch (note_type)
2209 {
2210 default:
2211 return NULL;
2212
2213 case NT_PRPSINFO:
2214 {
602f1657 2215 char data[124] ATTRIBUTE_NONSTRING;
1f20dca5
UW		 2216 va_list ap;
2217
2218 va_start (ap, note_type);
2219 memset (data, 0, sizeof (data));
2220 strncpy (data + 28, va_arg (ap, const char *), 16);
be3e27bb 2221#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2222 DIAGNOSTIC_PUSH;
be3e27bb 2223 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
95da9854
L		 2224 -Wstringop-truncation:
2225 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2226 */
95da9854
L		 2227 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2228#endif
1f20dca5 2229 strncpy (data + 44, va_arg (ap, const char *), 80);
be3e27bb 2230#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2231 DIAGNOSTIC_POP;
fe75810f 2232#endif
1f20dca5
UW		 2233 va_end (ap);
2234
2235 return elfcore_write_note (abfd, buf, bufsiz,
2236 "CORE", note_type, data, sizeof (data));
2237 }
2238
2239 case NT_PRSTATUS:
2240 {
2241 char data[148];
2242 va_list ap;
2243 long pid;
2244 int cursig;
2245 const void *greg;
2246
2247 va_start (ap, note_type);
2248 memset (data, 0, sizeof (data));
2249 pid = va_arg (ap, long);
2250 bfd_put_32 (abfd, pid, data + 24);
2251 cursig = va_arg (ap, int);
2252 bfd_put_16 (abfd, cursig, data + 12);
2253 greg = va_arg (ap, const void *);
2254 memcpy (data + 72, greg, 72);
2255 va_end (ap);
2256
2257 return elfcore_write_note (abfd, buf, bufsiz,
2258 "CORE", note_type, data, sizeof (data));
2259 }
2260 }
2261}
2262
07d6d2b8
AM		 2263#define TARGET_LITTLE_SYM arm_elf32_le_vec
2264#define TARGET_LITTLE_NAME "elf32-littlearm"
2265#define TARGET_BIG_SYM arm_elf32_be_vec
2266#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2267
2268#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2269#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2270#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2271
252b5132
RH		 2272typedef unsigned long int insn32;
2273typedef unsigned short int insn16;
2274
3a4a14e9
PB		 2275/* In lieu of proper flags, assume all EABIv4 or later objects are
2276 interworkable. */
57e8b36a 2277#define INTERWORK_FLAG(abfd) \
3a4a14e9 2278 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2279 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2280 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2281
252b5132
RH		 2282/* The linker script knows the section names for placement.
2283 The entry_names are used to do simple name mangling on the stubs.
2284 Given a function name, and its type, the stub can be found. The
9b485d32 2285 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2286#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2287#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2288
2289#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2290#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2291
c7b8f16e
JB		 2292#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2293#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2294
a504d23a
LA		 2295#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2296#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2297
845b51d6
PB		 2298#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2299#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2300
7413f23f
DJ		 2301#define STUB_ENTRY_NAME "__%s_veneer"
2302
4ba2ef8f
TP		 2303#define CMSE_PREFIX "__acle_se_"
2304
4d83e8d9
CL		 2305#define CMSE_STUB_NAME ".gnu.sgstubs"
2306
252b5132
RH		 2307/* The name of the dynamic interpreter. This is put in the .interp
2308 section. */
2309#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2310
cb10292c
CL		 2311/* FDPIC default stack size. */
2312#define DEFAULT_STACK_SIZE 0x8000
2313
0855e32b 2314static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2315{
2316 0xe08e0000, /* add r0, lr, r0 */
2317 0xe5901004, /* ldr r1, [r0,#4] */
2318 0xe12fff11, /* bx r1 */
2319};
0855e32b
NS		 2320
2321static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2322{
2323 0xe52d2004, /* push {r2} */
2324 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2325 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2326 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2327 0xe081100f, /* 2: add r1, pc */
2328 0xe12fff12, /* bx r2 */
2329 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2330 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2331 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2332};
0855e32b 2333
b4e87f2c
TC		 2334/* NOTE: [Thumb nop sequence]
2335 When adding code that transitions from Thumb to Arm the instruction that
2336 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2337 a nop for performance reasons. */
2338
7801f98f
CL		 2339/* ARM FDPIC PLT entry. */
2340/* The last 5 words contain PLT lazy fragment code and data. */
2341static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2342 {
2343 0xe59fc008, /* ldr r12, .L1 */
2344 0xe08cc009, /* add r12, r12, r9 */
2345 0xe59c9004, /* ldr r9, [r12, #4] */
2346 0xe59cf000, /* ldr pc, [r12] */
2347 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2348 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2349 0xe51fc00c, /* ldr r12, [pc, #-12] */
2350 0xe92d1000, /* push {r12} */
2351 0xe599c004, /* ldr r12, [r9, #4] */
2352 0xe599f000, /* ldr pc, [r9] */
2353 };
2354
59029f57
CL		 2355/* Thumb FDPIC PLT entry. */
2356/* The last 5 words contain PLT lazy fragment code and data. */
2357static const bfd_vma elf32_arm_fdpic_thumb_plt_entry [] =
2358 {
2359 0xc00cf8df, /* ldr.w r12, .L1 */
2360 0x0c09eb0c, /* add.w r12, r12, r9 */
2361 0x9004f8dc, /* ldr.w r9, [r12, #4] */
2362 0xf000f8dc, /* ldr.w pc, [r12] */
2363 0x00000000, /* .L1 .word foo(GOTOFFFUNCDESC) */
2364 0x00000000, /* .L2 .word foo(funcdesc_value_reloc_offset) */
2365 0xc008f85f, /* ldr.w r12, .L2 */
2366 0xcd04f84d, /* push {r12} */
2367 0xc004f8d9, /* ldr.w r12, [r9, #4] */
2368 0xf000f8d9, /* ldr.w pc, [r9] */
2369 };
2370
5e681ec4
PB		 2371#ifdef FOUR_WORD_PLT
2372
252b5132
RH		 2373/* The first entry in a procedure linkage table looks like
2374 this. It is set up so that any shared library function that is
59f2c4e7 2375 called before the relocation has been set up calls the dynamic
9b485d32 2376 linker first. */
e5a52504 2377static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2378{
2379 0xe52de004, /* str lr, [sp, #-4]! */
2380 0xe59fe010, /* ldr lr, [pc, #16] */
2381 0xe08fe00e, /* add lr, pc, lr */
2382 0xe5bef008, /* ldr pc, [lr, #8]! */
2383};
5e681ec4
PB		 2384
2385/* Subsequent entries in a procedure linkage table look like
2386 this. */
e5a52504 2387static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2388{
2389 0xe28fc600, /* add ip, pc, #NN */
2390 0xe28cca00, /* add ip, ip, #NN */
2391 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2392 0x00000000, /* unused */
2393};
5e681ec4 2394
eed94f8f 2395#else /* not FOUR_WORD_PLT */
5e681ec4 2396
5e681ec4
PB		 2397/* The first entry in a procedure linkage table looks like
2398 this. It is set up so that any shared library function that is
2399 called before the relocation has been set up calls the dynamic
2400 linker first. */
e5a52504 2401static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2402{
07d6d2b8
AM		 2403 0xe52de004, /* str lr, [sp, #-4]! */
2404 0xe59fe004, /* ldr lr, [pc, #4] */
2405 0xe08fe00e, /* add lr, pc, lr */
2406 0xe5bef008, /* ldr pc, [lr, #8]! */
2407 0x00000000, /* &GOT[0] - . */
b38cadfb 2408};
252b5132 2409
1db37fe6
YG		 2410/* By default subsequent entries in a procedure linkage table look like
2411 this. Offsets that don't fit into 28 bits will cause link error. */
2412static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2413{
2414 0xe28fc600, /* add ip, pc, #0xNN00000 */
2415 0xe28cca00, /* add ip, ip, #0xNN000 */
2416 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2417};
5e681ec4 2418
1db37fe6
YG		 2419/* When explicitly asked, we'll use this "long" entry format
2420 which can cope with arbitrary displacements. */
2421static const bfd_vma elf32_arm_plt_entry_long [] =
2422{
07d6d2b8
AM		 2423 0xe28fc200, /* add ip, pc, #0xN0000000 */
2424 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2425 0xe28cca00, /* add ip, ip, #0xNN000 */
2426 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2427};
2428
2429static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2430
eed94f8f
NC		 2431#endif /* not FOUR_WORD_PLT */
2432
2433/* The first entry in a procedure linkage table looks like this.
2434 It is set up so that any shared library function that is called before the
2435 relocation has been set up calls the dynamic linker first. */
2436static const bfd_vma elf32_thumb2_plt0_entry [] =
2437{
2438 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2439 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2440 0xf8dfb500, /* push {lr} */
2441 0x44fee008, /* ldr.w lr, [pc, #8] */
2442 /* add lr, pc */
eed94f8f 2443 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2444 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2445};
2446
2447/* Subsequent entries in a procedure linkage table for thumb only target
2448 look like this. */
2449static const bfd_vma elf32_thumb2_plt_entry [] =
2450{
2451 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2452 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2453 0x0c00f240, /* movw ip, #0xNNNN */
2454 0x0c00f2c0, /* movt ip, #0xNNNN */
2455 0xf8dc44fc, /* add ip, pc */
15ccbdd7
TC		 2456 0xe7fcf000 /* ldr.w pc, [ip] */
2457 /* b .-4 */
eed94f8f 2458};
252b5132 2459
00a97672
RS		 2460/* The format of the first entry in the procedure linkage table
2461 for a VxWorks executable. */
2462static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2463{
07d6d2b8
AM		 2464 0xe52dc008, /* str ip,[sp,#-8]! */
2465 0xe59fc000, /* ldr ip,[pc] */
2466 0xe59cf008, /* ldr pc,[ip,#8] */
2467 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2468};
00a97672
RS		 2469
2470/* The format of subsequent entries in a VxWorks executable. */
2471static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2472{
07d6d2b8
AM		 2473 0xe59fc000, /* ldr ip,[pc] */
2474 0xe59cf000, /* ldr pc,[ip] */
2475 0x00000000, /* .long @got */
2476 0xe59fc000, /* ldr ip,[pc] */
2477 0xea000000, /* b _PLT */
2478 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2479};
00a97672
RS		 2480
2481/* The format of entries in a VxWorks shared library. */
2482static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2483{
07d6d2b8
AM		 2484 0xe59fc000, /* ldr ip,[pc] */
2485 0xe79cf009, /* ldr pc,[ip,r9] */
2486 0x00000000, /* .long @got */
2487 0xe59fc000, /* ldr ip,[pc] */
2488 0xe599f008, /* ldr pc,[r9,#8] */
2489 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2490};
00a97672 2491
b7693d02
DJ		 2492/* An initial stub used if the PLT entry is referenced from Thumb code. */
2493#define PLT_THUMB_STUB_SIZE 4
2494static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2495{
2496 0x4778, /* bx pc */
b4e87f2c 2497 0xe7fd /* b .-2 */
b38cadfb 2498};
b7693d02 2499
e5a52504
MM		 2500/* The entries in a PLT when using a DLL-based target with multiple
2501 address spaces. */
906e58ca 2502static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2503{
07d6d2b8
AM		 2504 0xe51ff004, /* ldr pc, [pc, #-4] */
2505 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2506};
2507
2508/* The first entry in a procedure linkage table looks like
2509 this. It is set up so that any shared library function that is
2510 called before the relocation has been set up calls the dynamic
2511 linker first. */
2512static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2513{
2514 /* First bundle: */
2515 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2516 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2517 0xe08cc00f, /* add ip, ip, pc */
2518 0xe52dc008, /* str ip, [sp, #-8]! */
2519 /* Second bundle: */
edccdf7c
RM		 2520 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2521 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2522 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2523 0xe12fff1c, /* bx ip */
b38cadfb 2524 /* Third bundle: */
edccdf7c
RM		 2525 0xe320f000, /* nop */
2526 0xe320f000, /* nop */
2527 0xe320f000, /* nop */
b38cadfb
NC		 2528 /* .Lplt_tail: */
2529 0xe50dc004, /* str ip, [sp, #-4] */
2530 /* Fourth bundle: */
edccdf7c
RM		 2531 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2532 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2533 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2534 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2535};
2536#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2537
2538/* Subsequent entries in a procedure linkage table look like this. */
2539static const bfd_vma elf32_arm_nacl_plt_entry [] =
2540{
2541 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2542 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2543 0xe08cc00f, /* add ip, ip, pc */
2544 0xea000000, /* b .Lplt_tail */
2545};
e5a52504 2546
906e58ca
NC		 2547#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2548#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2549#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2550#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2551#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2552#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2553#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2554#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2555
461a49ca 2556enum stub_insn_type
b38cadfb
NC		 2557{
2558 THUMB16_TYPE = 1,
2559 THUMB32_TYPE,
2560 ARM_TYPE,
2561 DATA_TYPE
2562};
461a49ca 2563
48229727
JB		 2564#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2565/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2566 is inserted in arm_build_one_stub(). */
2567#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2568#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2569#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2570#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2571#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2572#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2573#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2574#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2575
2576typedef struct
2577{
07d6d2b8 2578 bfd_vma data;
b38cadfb 2579 enum stub_insn_type type;
07d6d2b8
AM		 2580 unsigned int r_type;
2581 int reloc_addend;
461a49ca
DJ		 2582} insn_sequence;
2583
b4e87f2c
TC		 2584/* See note [Thumb nop sequence] when adding a veneer. */
2585
fea2b4d6
CL		 2586/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2587 to reach the stub if necessary. */
461a49ca 2588static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2589{
07d6d2b8 2590 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2591 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2592};
906e58ca 2593
fea2b4d6
CL		 2594/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2595 available. */
461a49ca 2596static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2597{
07d6d2b8
AM		 2598 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2599 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2600 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2601};
906e58ca 2602
d3626fb0 2603/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2604static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2605{
07d6d2b8
AM		 2606 THUMB16_INSN (0xb401), /* push {r0} */
2607 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2608 THUMB16_INSN (0x4684), /* mov ip, r0 */
2609 THUMB16_INSN (0xbc01), /* pop {r0} */
2610 THUMB16_INSN (0x4760), /* bx ip */
2611 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2612 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2613};
906e58ca 2614
80c135e5
TP		 2615/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2616static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2617{
07d6d2b8 2618 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2619 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2620};
2621
d5a67c02
AV		 2622/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2623 M-profile architectures. */
2624static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2625{
2626 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2627 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2628 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2629};
2630
d3626fb0
CL		 2631/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2632 allowed. */
2633static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2634{
07d6d2b8 2635 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2636 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2637 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2638 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2639 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2640};
d3626fb0 2641
fea2b4d6
CL		 2642/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2643 available. */
461a49ca 2644static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2645{
07d6d2b8 2646 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2647 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8 2648 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2649 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2650};
906e58ca 2651
fea2b4d6
CL		 2652/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2653 one, when the destination is close enough. */
461a49ca 2654static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2655{
07d6d2b8 2656 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2657 THUMB16_INSN (0xe7fd), /* b .-2 */
b38cadfb
NC		 2658 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2659};
c820be07 2660
cf3eccff 2661/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2662 blx to reach the stub if necessary. */
cf3eccff 2663static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2664{
07d6d2b8
AM		 2665 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2666 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2667 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2668};
906e58ca 2669
cf3eccff
DJ		 2670/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2671 blx to reach the stub if necessary. We can not add into pc;
2672 it is not guaranteed to mode switch (different in ARMv6 and
2673 ARMv7). */
2674static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2675{
07d6d2b8
AM		 2676 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2677 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2678 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2679 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2680};
cf3eccff 2681
ebe24dd4
CL		 2682/* V4T ARM -> ARM long branch stub, PIC. */
2683static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2684{
07d6d2b8
AM		 2685 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2686 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2687 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2688 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2689};
ebe24dd4
CL		 2690
2691/* V4T Thumb -> ARM long branch stub, PIC. */
2692static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2693{
07d6d2b8 2694 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2695 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2696 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2697 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2698 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2699};
ebe24dd4 2700
d3626fb0
CL		 2701/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2702 architectures. */
ebe24dd4 2703static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2704{
07d6d2b8
AM		 2705 THUMB16_INSN (0xb401), /* push {r0} */
2706 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2707 THUMB16_INSN (0x46fc), /* mov ip, pc */
2708 THUMB16_INSN (0x4484), /* add ip, r0 */
2709 THUMB16_INSN (0xbc01), /* pop {r0} */
2710 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2711 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2712};
ebe24dd4 2713
d3626fb0
CL		 2714/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2715 allowed. */
2716static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2717{
07d6d2b8 2718 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2719 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2720 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2721 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2722 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2723 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2724};
d3626fb0 2725
0855e32b
NS		 2726/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2727 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2728static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2729{
07d6d2b8
AM		 2730 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2731 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2732 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2733};
2734
2735/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2736 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2737static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2738{
07d6d2b8 2739 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2740 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2741 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2742 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2743 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2744};
2745
7a89b94e
NC		 2746/* NaCl ARM -> ARM long branch stub. */
2747static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2748{
2749 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2750 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2751 ARM_INSN (0xe12fff1c), /* bx ip */
2752 ARM_INSN (0xe320f000), /* nop */
2753 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2754 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2755 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2756 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2757};
2758
2759/* NaCl ARM -> ARM long branch stub, PIC. */
2760static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2761{
2762 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2763 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2764 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2765 ARM_INSN (0xe12fff1c), /* bx ip */
2766 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2767 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2768 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2769 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2770};
2771
4ba2ef8f
TP		 2772/* Stub used for transition to secure state (aka SG veneer). */
2773static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2774{
2775 THUMB32_INSN (0xe97fe97f), /* sg. */
2776 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2777};
2778
7a89b94e 2779
48229727
JB		 2780/* Cortex-A8 erratum-workaround stubs. */
2781
2782/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2783 can't use a conditional branch to reach this stub). */
2784
2785static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2786{
07d6d2b8 2787 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2788 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2789 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2790};
48229727
JB		 2791
2792/* Stub used for b.w and bl.w instructions. */
2793
2794static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2795{
2796 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2797};
48229727
JB		 2798
2799static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2800{
2801 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2802};
48229727
JB		 2803
2804/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2805 instruction (which switches to ARM mode) to point to this stub. Jump to the
2806 real destination using an ARM-mode branch. */
2807
2808static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2809{
2810 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2811};
48229727 2812
9553db3c
NC		 2813/* For each section group there can be a specially created linker section
2814 to hold the stubs for that group. The name of the stub section is based
2815 upon the name of another section within that group with the suffix below
2816 applied.
2817
2818 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2819 create what appeared to be a linker stub section when it actually
2820 contained user code/data. For example, consider this fragment:
b38cadfb 2821
9553db3c
NC		 2822 const char * stubborn_problems[] = { "np" };
2823
2824 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2825 section called:
2826
2827 .data.rel.local.stubborn_problems
2828
2829 This then causes problems in arm32_arm_build_stubs() as it triggers:
2830
2831 // Ignore non-stub sections.
2832 if (!strstr (stub_sec->name, STUB_SUFFIX))
2833 continue;
2834
2835 And so the section would be ignored instead of being processed. Hence
2836 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2837 C identifier. */
2838#define STUB_SUFFIX ".__stub"
906e58ca 2839
738a79f6
CL		 2840/* One entry per long/short branch stub defined above. */
2841#define DEF_STUBS \
2842 DEF_STUB(long_branch_any_any) \
2843 DEF_STUB(long_branch_v4t_arm_thumb) \
2844 DEF_STUB(long_branch_thumb_only) \
2845 DEF_STUB(long_branch_v4t_thumb_thumb) \
2846 DEF_STUB(long_branch_v4t_thumb_arm) \
2847 DEF_STUB(short_branch_v4t_thumb_arm) \
2848 DEF_STUB(long_branch_any_arm_pic) \
2849 DEF_STUB(long_branch_any_thumb_pic) \
2850 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2851 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2852 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2853 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2854 DEF_STUB(long_branch_any_tls_pic) \
2855 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2856 DEF_STUB(long_branch_arm_nacl) \
2857 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2858 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2859 DEF_STUB(a8_veneer_b_cond) \
2860 DEF_STUB(a8_veneer_b) \
2861 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2862 DEF_STUB(a8_veneer_blx) \
2863 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2864 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2865
2866#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2867enum elf32_arm_stub_type
2868{
906e58ca 2869 arm_stub_none,
738a79f6 2870 DEF_STUBS
4f4faa4d 2871 max_stub_type
738a79f6
CL		 2872};
2873#undef DEF_STUB
2874
8d9d9490
TP		 2875/* Note the first a8_veneer type. */
2876const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2877
738a79f6
CL		 2878typedef struct
2879{
d3ce72d0 2880 const insn_sequence* template_sequence;
738a79f6
CL		 2881 int template_size;
2882} stub_def;
2883
2884#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2885static const stub_def stub_definitions[] =
2886{
738a79f6
CL		 2887 {NULL, 0},
2888 DEF_STUBS
906e58ca
NC		 2889};
2890
2891struct elf32_arm_stub_hash_entry
2892{
2893 /* Base hash table entry structure. */
2894 struct bfd_hash_entry root;
2895
2896 /* The stub section. */
2897 asection *stub_sec;
2898
2899 /* Offset within stub_sec of the beginning of this stub. */
2900 bfd_vma stub_offset;
2901
2902 /* Given the symbol's value and its section we can determine its final
2903 value when building the stubs (so the stub knows where to jump). */
2904 bfd_vma target_value;
2905 asection *target_section;
2906
8d9d9490
TP		 2907 /* Same as above but for the source of the branch to the stub. Used for
2908 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2909 such, source section does not need to be recorded since Cortex-A8 erratum
2910 workaround stubs are only generated when both source and target are in the
2911 same section. */
2912 bfd_vma source_value;
48229727
JB		 2913
2914 /* The instruction which caused this stub to be generated (only valid for
2915 Cortex-A8 erratum workaround stubs at present). */
2916 unsigned long orig_insn;
2917
461a49ca 2918 /* The stub type. */
906e58ca 2919 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2920 /* Its encoding size in bytes. */
2921 int stub_size;
2922 /* Its template. */
2923 const insn_sequence *stub_template;
2924 /* The size of the template (number of entries). */
2925 int stub_template_size;
906e58ca
NC		 2926
2927 /* The symbol table entry, if any, that this was derived from. */
2928 struct elf32_arm_link_hash_entry *h;
2929
35fc36a8
RS		 2930 /* Type of branch. */
2931 enum arm_st_branch_type branch_type;
906e58ca
NC		 2932
2933 /* Where this stub is being called from, or, in the case of combined
2934 stub sections, the first input section in the group. */
2935 asection *id_sec;
7413f23f
DJ		 2936
2937 /* The name for the local symbol at the start of this stub. The
2938 stub name in the hash table has to be unique; this does not, so
2939 it can be friendlier. */
2940 char *output_name;
906e58ca
NC		 2941};
2942
e489d0ae
PB		 2943/* Used to build a map of a section. This is required for mixed-endian
2944 code/data. */
2945
2946typedef struct elf32_elf_section_map
2947{
2948 bfd_vma vma;
2949 char type;
2950}
2951elf32_arm_section_map;
2952
c7b8f16e
JB		 2953/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2954
2955typedef enum
2956{
2957 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2958 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2959 VFP11_ERRATUM_ARM_VENEER,
2960 VFP11_ERRATUM_THUMB_VENEER
2961}
2962elf32_vfp11_erratum_type;
2963
2964typedef struct elf32_vfp11_erratum_list
2965{
2966 struct elf32_vfp11_erratum_list *next;
2967 bfd_vma vma;
2968 union
2969 {
2970 struct
2971 {
2972 struct elf32_vfp11_erratum_list *veneer;
2973 unsigned int vfp_insn;
2974 } b;
2975 struct
2976 {
2977 struct elf32_vfp11_erratum_list *branch;
2978 unsigned int id;
2979 } v;
2980 } u;
2981 elf32_vfp11_erratum_type type;
2982}
2983elf32_vfp11_erratum_list;
2984
a504d23a
LA		 2985/* Information about a STM32L4XX erratum veneer, or a branch to such a
2986 veneer. */
2987typedef enum
2988{
2989 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2990 STM32L4XX_ERRATUM_VENEER
2991}
2992elf32_stm32l4xx_erratum_type;
2993
2994typedef struct elf32_stm32l4xx_erratum_list
2995{
2996 struct elf32_stm32l4xx_erratum_list *next;
2997 bfd_vma vma;
2998 union
2999 {
3000 struct
3001 {
3002 struct elf32_stm32l4xx_erratum_list *veneer;
3003 unsigned int insn;
3004 } b;
3005 struct
3006 {
3007 struct elf32_stm32l4xx_erratum_list *branch;
3008 unsigned int id;
3009 } v;
3010 } u;
3011 elf32_stm32l4xx_erratum_type type;
3012}
3013elf32_stm32l4xx_erratum_list;
3014
2468f9c9
PB		 3015typedef enum
3016{
3017 DELETE_EXIDX_ENTRY,
3018 INSERT_EXIDX_CANTUNWIND_AT_END
3019}
3020arm_unwind_edit_type;
3021
3022/* A (sorted) list of edits to apply to an unwind table. */
3023typedef struct arm_unwind_table_edit
3024{
3025 arm_unwind_edit_type type;
3026 /* Note: we sometimes want to insert an unwind entry corresponding to a
3027 section different from the one we're currently writing out, so record the
3028 (text) section this edit relates to here. */
3029 asection *linked_section;
3030 unsigned int index;
3031 struct arm_unwind_table_edit *next;
3032}
3033arm_unwind_table_edit;
3034
8e3de13a 3035typedef struct _arm_elf_section_data
e489d0ae 3036{
2468f9c9 3037 /* Information about mapping symbols. */
e489d0ae 3038 struct bfd_elf_section_data elf;
8e3de13a 3039 unsigned int mapcount;
c7b8f16e 3040 unsigned int mapsize;
e489d0ae 3041 elf32_arm_section_map *map;
2468f9c9 3042 /* Information about CPU errata. */
c7b8f16e
JB		 3043 unsigned int erratumcount;
3044 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 3045 unsigned int stm32l4xx_erratumcount;
3046 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 3047 unsigned int additional_reloc_count;
2468f9c9
PB		 3048 /* Information about unwind tables. */
3049 union
3050 {
3051 /* Unwind info attached to a text section. */
3052 struct
3053 {
3054 asection *arm_exidx_sec;
3055 } text;
3056
3057 /* Unwind info attached to an .ARM.exidx section. */
3058 struct
3059 {
3060 arm_unwind_table_edit *unwind_edit_list;
3061 arm_unwind_table_edit *unwind_edit_tail;
3062 } exidx;
3063 } u;
8e3de13a
NC		 3064}
3065_arm_elf_section_data;
e489d0ae
PB		 3066
3067#define elf32_arm_section_data(sec) \
8e3de13a 3068 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 3069
48229727
JB		 3070/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3071 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3072 so may be created multiple times: we use an array of these entries whilst
3073 relaxing which we can refresh easily, then create stubs for each potentially
3074 erratum-triggering instruction once we've settled on a solution. */
3075
b38cadfb
NC		 3076struct a8_erratum_fix
3077{
48229727
JB		 3078 bfd *input_bfd;
3079 asection *section;
3080 bfd_vma offset;
8d9d9490 3081 bfd_vma target_offset;
48229727
JB		 3082 unsigned long orig_insn;
3083 char *stub_name;
3084 enum elf32_arm_stub_type stub_type;
35fc36a8 3085 enum arm_st_branch_type branch_type;
48229727
JB		 3086};
3087
3088/* A table of relocs applied to branches which might trigger Cortex-A8
3089 erratum. */
3090
b38cadfb
NC		 3091struct a8_erratum_reloc
3092{
48229727
JB		 3093 bfd_vma from;
3094 bfd_vma destination;
92750f34
DJ		 3095 struct elf32_arm_link_hash_entry *hash;
3096 const char *sym_name;
48229727 3097 unsigned int r_type;
35fc36a8 3098 enum arm_st_branch_type branch_type;
48229727
JB		 3099 bfd_boolean non_a8_stub;
3100};
3101
ba93b8ac
DJ		 3102/* The size of the thread control block. */
3103#define TCB_SIZE 8
3104
34e77a92
RS		 3105/* ARM-specific information about a PLT entry, over and above the usual
3106 gotplt_union. */
b38cadfb
NC		 3107struct arm_plt_info
3108{
34e77a92
RS		 3109 /* We reference count Thumb references to a PLT entry separately,
3110 so that we can emit the Thumb trampoline only if needed. */
3111 bfd_signed_vma thumb_refcount;
3112
3113 /* Some references from Thumb code may be eliminated by BL->BLX
3114 conversion, so record them separately. */
3115 bfd_signed_vma maybe_thumb_refcount;
3116
3117 /* How many of the recorded PLT accesses were from non-call relocations.
3118 This information is useful when deciding whether anything takes the
3119 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3120 non-call references to the function should resolve directly to the
3121 real runtime target. */
3122 unsigned int noncall_refcount;
3123
3124 /* Since PLT entries have variable size if the Thumb prologue is
3125 used, we need to record the index into .got.plt instead of
3126 recomputing it from the PLT offset. */
3127 bfd_signed_vma got_offset;
3128};
3129
3130/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 3131struct arm_local_iplt_info
3132{
34e77a92
RS		 3133 /* The information that is usually found in the generic ELF part of
3134 the hash table entry. */
3135 union gotplt_union root;
3136
3137 /* The information that is usually found in the ARM-specific part of
3138 the hash table entry. */
3139 struct arm_plt_info arm;
3140
3141 /* A list of all potential dynamic relocations against this symbol. */
3142 struct elf_dyn_relocs *dyn_relocs;
3143};
3144
e8b09b87
CL		 3145/* Structure to handle FDPIC support for local functions. */
3146struct fdpic_local {
3147 unsigned int funcdesc_cnt;
3148 unsigned int gotofffuncdesc_cnt;
3149 int funcdesc_offset;
3150};
3151
0ffa91dd 3152struct elf_arm_obj_tdata
ba93b8ac
DJ		 3153{
3154 struct elf_obj_tdata root;
3155
3156 /* tls_type for each local got entry. */
3157 char *local_got_tls_type;
ee065d83 3158
0855e32b
NS		 3159 /* GOTPLT entries for TLS descriptors. */
3160 bfd_vma *local_tlsdesc_gotent;
3161
34e77a92
RS		 3162 /* Information for local symbols that need entries in .iplt. */
3163 struct arm_local_iplt_info **local_iplt;
3164
bf21ed78
MS		 3165 /* Zero to warn when linking objects with incompatible enum sizes. */
3166 int no_enum_size_warning;
a9dc9481
JM		 3167
3168 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3169 int no_wchar_size_warning;
e8b09b87
CL		 3170
3171 /* Maintains FDPIC counters and funcdesc info. */
3172 struct fdpic_local *local_fdpic_cnts;
ba93b8ac
DJ		 3173};
3174
0ffa91dd
NC		 3175#define elf_arm_tdata(bfd) \
3176 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3177
0ffa91dd
NC		 3178#define elf32_arm_local_got_tls_type(bfd) \
3179 (elf_arm_tdata (bfd)->local_got_tls_type)
3180
0855e32b
NS		 3181#define elf32_arm_local_tlsdesc_gotent(bfd) \
3182 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3183
34e77a92
RS		 3184#define elf32_arm_local_iplt(bfd) \
3185 (elf_arm_tdata (bfd)->local_iplt)
3186
e8b09b87
CL		 3187#define elf32_arm_local_fdpic_cnts(bfd) \
3188 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3189
0ffa91dd
NC		 3190#define is_arm_elf(bfd) \
3191 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3192 && elf_tdata (bfd) != NULL \
4dfe6ac6 3193 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3194
3195static bfd_boolean
3196elf32_arm_mkobject (bfd *abfd)
3197{
0ffa91dd 3198 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3199 ARM_ELF_DATA);
ba93b8ac
DJ		 3200}
3201
ba93b8ac
DJ		 3202#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3203
e8b09b87
CL		 3204/* Structure to handle FDPIC support for extern functions. */
3205struct fdpic_global {
3206 unsigned int gotofffuncdesc_cnt;
3207 unsigned int gotfuncdesc_cnt;
3208 unsigned int funcdesc_cnt;
3209 int funcdesc_offset;
3210 int gotfuncdesc_offset;
3211};
3212
ba96a88f 3213/* Arm ELF linker hash entry. */
252b5132 3214struct elf32_arm_link_hash_entry
b38cadfb
NC		 3215{
3216 struct elf_link_hash_entry root;
252b5132 3217
b38cadfb
NC		 3218 /* ARM-specific PLT information. */
3219 struct arm_plt_info plt;
ba93b8ac
DJ		 3220
3221#define GOT_UNKNOWN 0
3222#define GOT_NORMAL 1
3223#define GOT_TLS_GD 2
3224#define GOT_TLS_IE 4
0855e32b
NS		 3225#define GOT_TLS_GDESC 8
3226#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3227 unsigned int tls_type : 8;
34e77a92 3228
b38cadfb
NC		 3229 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3230 unsigned int is_iplt : 1;
34e77a92 3231
b38cadfb 3232 unsigned int unused : 23;
a4fd1a8e 3233
b38cadfb
NC		 3234 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3235 starting at the end of the jump table. */
3236 bfd_vma tlsdesc_got;
0855e32b 3237
b38cadfb
NC		 3238 /* The symbol marking the real symbol location for exported thumb
3239 symbols with Arm stubs. */
3240 struct elf_link_hash_entry *export_glue;
906e58ca 3241
b38cadfb 3242 /* A pointer to the most recently used stub hash entry against this
8029a119 3243 symbol. */
b38cadfb 3244 struct elf32_arm_stub_hash_entry *stub_cache;
e8b09b87
CL		 3245
3246 /* Counter for FDPIC relocations against this symbol. */
3247 struct fdpic_global fdpic_cnts;
b38cadfb 3248};
252b5132 3249
252b5132 3250/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3251#define elf32_arm_link_hash_traverse(table, func, info) \
3252 (elf_link_hash_traverse \
3253 (&(table)->root, \
b7693d02 3254 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3255 (info)))
3256
3257/* Get the ARM elf linker hash table from a link_info structure. */
0f55320b
AM		 3258#define elf32_arm_hash_table(p) \
3259 ((is_elf_hash_table ((p)->hash) \
3260 && elf_hash_table_id (elf_hash_table (p)) == ARM_ELF_DATA) \
3261 ? (struct elf32_arm_link_hash_table *) (p)->hash : NULL)
252b5132 3262
906e58ca
NC		 3263#define arm_stub_hash_lookup(table, string, create, copy) \
3264 ((struct elf32_arm_stub_hash_entry *) \
3265 bfd_hash_lookup ((table), (string), (create), (copy)))
3266
21d799b5
NC		 3267/* Array to keep track of which stub sections have been created, and
3268 information on stub grouping. */
3269struct map_stub
3270{
3271 /* This is the section to which stubs in the group will be
3272 attached. */
3273 asection *link_sec;
3274 /* The stub section. */
3275 asection *stub_sec;
3276};
3277
0855e32b
NS		 3278#define elf32_arm_compute_jump_table_size(htab) \
3279 ((htab)->next_tls_desc_index * 4)
3280
9b485d32 3281/* ARM ELF linker hash table. */
252b5132 3282struct elf32_arm_link_hash_table
906e58ca
NC		 3283{
3284 /* The main hash table. */
3285 struct elf_link_hash_table root;
252b5132 3286
906e58ca
NC		 3287 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3288 bfd_size_type thumb_glue_size;
252b5132 3289
906e58ca
NC		 3290 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3291 bfd_size_type arm_glue_size;
252b5132 3292
906e58ca
NC		 3293 /* The size in bytes of section containing the ARMv4 BX veneers. */
3294 bfd_size_type bx_glue_size;
845b51d6 3295
906e58ca
NC		 3296 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3297 veneer has been populated. */
3298 bfd_vma bx_glue_offset[15];
845b51d6 3299
906e58ca
NC		 3300 /* The size in bytes of the section containing glue for VFP11 erratum
3301 veneers. */
3302 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3303
a504d23a
LA		 3304 /* The size in bytes of the section containing glue for STM32L4XX erratum
3305 veneers. */
3306 bfd_size_type stm32l4xx_erratum_glue_size;
3307
48229727
JB		 3308 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3309 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3310 elf32_arm_write_section(). */
3311 struct a8_erratum_fix *a8_erratum_fixes;
3312 unsigned int num_a8_erratum_fixes;
3313
906e58ca
NC		 3314 /* An arbitrary input BFD chosen to hold the glue sections. */
3315 bfd * bfd_of_glue_owner;
ba96a88f 3316
906e58ca
NC		 3317 /* Nonzero to output a BE8 image. */
3318 int byteswap_code;
e489d0ae 3319
906e58ca
NC		 3320 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3321 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3322 int target1_is_rel;
9c504268 3323
906e58ca
NC		 3324 /* The relocation to use for R_ARM_TARGET2 relocations. */
3325 int target2_reloc;
eb043451 3326
906e58ca
NC		 3327 /* 0 = Ignore R_ARM_V4BX.
3328 1 = Convert BX to MOV PC.
3329 2 = Generate v4 interworing stubs. */
3330 int fix_v4bx;
319850b4 3331
48229727
JB		 3332 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3333 int fix_cortex_a8;
3334
2de70689
MGD		 3335 /* Whether we should fix the ARM1176 BLX immediate issue. */
3336 int fix_arm1176;
3337
906e58ca
NC		 3338 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3339 int use_blx;
33bfe774 3340
906e58ca
NC		 3341 /* What sort of code sequences we should look for which may trigger the
3342 VFP11 denorm erratum. */
3343 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3344
906e58ca
NC		 3345 /* Global counter for the number of fixes we have emitted. */
3346 int num_vfp11_fixes;
c7b8f16e 3347
a504d23a
LA		 3348 /* What sort of code sequences we should look for which may trigger the
3349 STM32L4XX erratum. */
3350 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3351
3352 /* Global counter for the number of fixes we have emitted. */
3353 int num_stm32l4xx_fixes;
3354
906e58ca
NC		 3355 /* Nonzero to force PIC branch veneers. */
3356 int pic_veneer;
27e55c4d 3357
906e58ca
NC		 3358 /* The number of bytes in the initial entry in the PLT. */
3359 bfd_size_type plt_header_size;
e5a52504 3360
906e58ca
NC		 3361 /* The number of bytes in the subsequent PLT etries. */
3362 bfd_size_type plt_entry_size;
e5a52504 3363
906e58ca 3364 /* True if the target uses REL relocations. */
f3185997 3365 bfd_boolean use_rel;
4e7fd91e 3366
54ddd295
TP		 3367 /* Nonzero if import library must be a secure gateway import library
3368 as per ARMv8-M Security Extensions. */
3369 int cmse_implib;
3370
0955507f
TP		 3371 /* The import library whose symbols' address must remain stable in
3372 the import library generated. */
3373 bfd *in_implib_bfd;
3374
0855e32b
NS		 3375 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3376 bfd_vma next_tls_desc_index;
3377
3378 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3379 bfd_vma num_tls_desc;
3380
906e58ca
NC		 3381 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3382 asection *srelplt2;
00a97672 3383
0855e32b
NS		 3384 /* Offset in .plt section of tls_arm_trampoline. */
3385 bfd_vma tls_trampoline;
3386
5c5a4843 3387 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
906e58ca
NC		 3388 union
3389 {
3390 bfd_signed_vma refcount;
3391 bfd_vma offset;
3392 } tls_ldm_got;
b7693d02 3393
906e58ca
NC		 3394 /* For convenience in allocate_dynrelocs. */
3395 bfd * obfd;
3396
0855e32b
NS		 3397 /* The amount of space used by the reserved portion of the sgotplt
3398 section, plus whatever space is used by the jump slots. */
3399 bfd_vma sgotplt_jump_table_size;
3400
906e58ca
NC		 3401 /* The stub hash table. */
3402 struct bfd_hash_table stub_hash_table;
3403
3404 /* Linker stub bfd. */
3405 bfd *stub_bfd;
3406
3407 /* Linker call-backs. */
6bde4c52
TP		 3408 asection * (*add_stub_section) (const char *, asection *, asection *,
3409 unsigned int);
906e58ca
NC		 3410 void (*layout_sections_again) (void);
3411
3412 /* Array to keep track of which stub sections have been created, and
3413 information on stub grouping. */
21d799b5 3414 struct map_stub *stub_group;
906e58ca 3415
4ba2ef8f
TP		 3416 /* Input stub section holding secure gateway veneers. */
3417 asection *cmse_stub_sec;
3418
0955507f
TP		 3419 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3420 start to be allocated. */
3421 bfd_vma new_cmse_stub_offset;
3422
fe33d2fa 3423 /* Number of elements in stub_group. */
7292b3ac 3424 unsigned int top_id;
fe33d2fa 3425
906e58ca
NC		 3426 /* Assorted information used by elf32_arm_size_stubs. */
3427 unsigned int bfd_count;
7292b3ac 3428 unsigned int top_index;
906e58ca 3429 asection **input_list;
617a5ada
CL		 3430
3431 /* True if the target system uses FDPIC. */
3432 int fdpic_p;
e8b09b87
CL		 3433
3434 /* Fixup section. Used for FDPIC. */
3435 asection *srofixup;
906e58ca 3436};
252b5132 3437
e8b09b87
CL		 3438/* Add an FDPIC read-only fixup. */
3439static void
3440arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3441{
3442 bfd_vma fixup_offset;
3443
3444 fixup_offset = srofixup->reloc_count++ * 4;
3445 BFD_ASSERT (fixup_offset < srofixup->size);
3446 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3447}
3448
a504d23a
LA		 3449static inline int
3450ctz (unsigned int mask)
3451{
3452#if GCC_VERSION >= 3004
3453 return __builtin_ctz (mask);
3454#else
3455 unsigned int i;
3456
3457 for (i = 0; i < 8 * sizeof (mask); i++)
3458 {
3459 if (mask & 0x1)
3460 break;
3461 mask = (mask >> 1);
3462 }
3463 return i;
3464#endif
3465}
3466
3467static inline int
b25e998d 3468elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3469{
3470#if GCC_VERSION >= 3004
3471 return __builtin_popcount (mask);
3472#else
b25e998d
CG		 3473 unsigned int i;
3474 int sum = 0;
a504d23a
LA		 3475
3476 for (i = 0; i < 8 * sizeof (mask); i++)
3477 {
3478 if (mask & 0x1)
3479 sum++;
3480 mask = (mask >> 1);
3481 }
3482 return sum;
3483#endif
3484}
3485
e8b09b87
CL		 3486static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3487 asection *sreloc, Elf_Internal_Rela *rel);
3488
3489static void
3490arm_elf_fill_funcdesc(bfd *output_bfd,
3491 struct bfd_link_info *info,
3492 int *funcdesc_offset,
3493 int dynindx,
3494 int offset,
3495 bfd_vma addr,
3496 bfd_vma dynreloc_value,
3497 bfd_vma seg)
3498{
3499 if ((*funcdesc_offset & 1) == 0)
3500 {
3501 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3502 asection *sgot = globals->root.sgot;
3503
3504 if (bfd_link_pic(info))
3505 {
3506 asection *srelgot = globals->root.srelgot;
3507 Elf_Internal_Rela outrel;
3508
3509 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3510 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3511 outrel.r_addend = 0;
3512
3513 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3514 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3515 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3516 }
3517 else
3518 {
3519 struct elf_link_hash_entry *hgot = globals->root.hgot;
3520 bfd_vma got_value = hgot->root.u.def.value
3521 + hgot->root.u.def.section->output_section->vma
3522 + hgot->root.u.def.section->output_offset;
3523
3524 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3525 sgot->output_section->vma + sgot->output_offset
3526 + offset);
3527 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3528 sgot->output_section->vma + sgot->output_offset
3529 + offset + 4);
3530 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3531 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3532 }
3533 *funcdesc_offset |= 1;
3534 }
3535}
3536
780a67af
NC		 3537/* Create an entry in an ARM ELF linker hash table. */
3538
3539static struct bfd_hash_entry *
57e8b36a 3540elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3541 struct bfd_hash_table * table,
3542 const char * string)
780a67af
NC		 3543{
3544 struct elf32_arm_link_hash_entry * ret =
3545 (struct elf32_arm_link_hash_entry *) entry;
3546
3547 /* Allocate the structure if it has not already been allocated by a
3548 subclass. */
906e58ca 3549 if (ret == NULL)
21d799b5 3550 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3551 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3552 if (ret == NULL)
780a67af
NC		 3553 return (struct bfd_hash_entry *) ret;
3554
3555 /* Call the allocation method of the superclass. */
3556 ret = ((struct elf32_arm_link_hash_entry *)
3557 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3558 table, string));
57e8b36a 3559 if (ret != NULL)
b7693d02 3560 {
ba93b8ac 3561 ret->tls_type = GOT_UNKNOWN;
0855e32b 3562 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3563 ret->plt.thumb_refcount = 0;
3564 ret->plt.maybe_thumb_refcount = 0;
3565 ret->plt.noncall_refcount = 0;
3566 ret->plt.got_offset = -1;
3567 ret->is_iplt = FALSE;
a4fd1a8e 3568 ret->export_glue = NULL;
906e58ca
NC		 3569
3570 ret->stub_cache = NULL;
e8b09b87
CL		 3571
3572 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3573 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3574 ret->fdpic_cnts.funcdesc_cnt = 0;
3575 ret->fdpic_cnts.funcdesc_offset = -1;
3576 ret->fdpic_cnts.gotfuncdesc_offset = -1;
b7693d02 3577 }
780a67af
NC		 3578
3579 return (struct bfd_hash_entry *) ret;
3580}
3581
34e77a92
RS		 3582/* Ensure that we have allocated bookkeeping structures for ABFD's local
3583 symbols. */
3584
3585static bfd_boolean
3586elf32_arm_allocate_local_sym_info (bfd *abfd)
3587{
3588 if (elf_local_got_refcounts (abfd) == NULL)
3589 {
3590 bfd_size_type num_syms;
3591 bfd_size_type size;
3592 char *data;
3593
3594 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3595 size = num_syms * (sizeof (bfd_signed_vma)
3596 + sizeof (struct arm_local_iplt_info *)
3597 + sizeof (bfd_vma)
e8b09b87
CL		 3598 + sizeof (char)
3599 + sizeof (struct fdpic_local));
34e77a92
RS		 3600 data = bfd_zalloc (abfd, size);
3601 if (data == NULL)
3602 return FALSE;
3603
e8b09b87
CL		 3604 elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
3605 data += num_syms * sizeof (struct fdpic_local);
3606
34e77a92
RS		 3607 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3608 data += num_syms * sizeof (bfd_signed_vma);
3609
3610 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3611 data += num_syms * sizeof (struct arm_local_iplt_info *);
3612
3613 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3614 data += num_syms * sizeof (bfd_vma);
3615
3616 elf32_arm_local_got_tls_type (abfd) = data;
3617 }
3618 return TRUE;
3619}
3620
3621/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3622 to input bfd ABFD. Create the information if it doesn't already exist.
3623 Return null if an allocation fails. */
3624
3625static struct arm_local_iplt_info *
3626elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3627{
3628 struct arm_local_iplt_info **ptr;
3629
3630 if (!elf32_arm_allocate_local_sym_info (abfd))
3631 return NULL;
3632
3633 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3634 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3635 if (*ptr == NULL)
3636 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3637 return *ptr;
3638}
3639
3640/* Try to obtain PLT information for the symbol with index R_SYMNDX
3641 in ABFD's symbol table. If the symbol is global, H points to its
3642 hash table entry, otherwise H is null.
3643
3644 Return true if the symbol does have PLT information. When returning
3645 true, point *ROOT_PLT at the target-independent reference count/offset
3646 union and *ARM_PLT at the ARM-specific information. */
3647
3648static bfd_boolean
4ba2ef8f
TP		 3649elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3650 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3651 unsigned long r_symndx, union gotplt_union **root_plt,
3652 struct arm_plt_info **arm_plt)
3653{
3654 struct arm_local_iplt_info *local_iplt;
3655
4ba2ef8f
TP		 3656 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3657 return FALSE;
3658
34e77a92
RS		 3659 if (h != NULL)
3660 {
3661 *root_plt = &h->root.plt;
3662 *arm_plt = &h->plt;
3663 return TRUE;
3664 }
3665
3666 if (elf32_arm_local_iplt (abfd) == NULL)
3667 return FALSE;
3668
3669 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3670 if (local_iplt == NULL)
3671 return FALSE;
3672
3673 *root_plt = &local_iplt->root;
3674 *arm_plt = &local_iplt->arm;
3675 return TRUE;
3676}
3677
59029f57
CL		 3678static bfd_boolean using_thumb_only (struct elf32_arm_link_hash_table *globals);
3679
34e77a92
RS		 3680/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3681 before it. */
3682
3683static bfd_boolean
3684elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3685 struct arm_plt_info *arm_plt)
3686{
3687 struct elf32_arm_link_hash_table *htab;
3688
3689 htab = elf32_arm_hash_table (info);
59029f57
CL		 3690
3691 return (!using_thumb_only(htab) && (arm_plt->thumb_refcount != 0
3692 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0)));
34e77a92
RS		 3693}
3694
3695/* Return a pointer to the head of the dynamic reloc list that should
3696 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3697 ABFD's symbol table. Return null if an error occurs. */
3698
3699static struct elf_dyn_relocs **
3700elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3701 Elf_Internal_Sym *isym)
3702{
3703 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3704 {
3705 struct arm_local_iplt_info *local_iplt;
3706
3707 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3708 if (local_iplt == NULL)
3709 return NULL;
3710 return &local_iplt->dyn_relocs;
3711 }
3712 else
3713 {
3714 /* Track dynamic relocs needed for local syms too.
3715 We really need local syms available to do this
3716 easily. Oh well. */
3717 asection *s;
3718 void *vpp;
3719
3720 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3721 if (s == NULL)
3722 abort ();
3723
3724 vpp = &elf_section_data (s)->local_dynrel;
3725 return (struct elf_dyn_relocs **) vpp;
3726 }
3727}
3728
906e58ca
NC		 3729/* Initialize an entry in the stub hash table. */
3730
3731static struct bfd_hash_entry *
3732stub_hash_newfunc (struct bfd_hash_entry *entry,
3733 struct bfd_hash_table *table,
3734 const char *string)
3735{
3736 /* Allocate the structure if it has not already been allocated by a
3737 subclass. */
3738 if (entry == NULL)
3739 {
21d799b5 3740 entry = (struct bfd_hash_entry *)
99059e56 3741 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3742 if (entry == NULL)
3743 return entry;
3744 }
3745
3746 /* Call the allocation method of the superclass. */
3747 entry = bfd_hash_newfunc (entry, table, string);
3748 if (entry != NULL)
3749 {
3750 struct elf32_arm_stub_hash_entry *eh;
3751
3752 /* Initialize the local fields. */
3753 eh = (struct elf32_arm_stub_hash_entry *) entry;
3754 eh->stub_sec = NULL;
0955507f 3755 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3756 eh->source_value = 0;
906e58ca
NC		 3757 eh->target_value = 0;
3758 eh->target_section = NULL;
cedfb179 3759 eh->orig_insn = 0;
906e58ca 3760 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3761 eh->stub_size = 0;
3762 eh->stub_template = NULL;
0955507f 3763 eh->stub_template_size = -1;
906e58ca
NC		 3764 eh->h = NULL;
3765 eh->id_sec = NULL;
d8d2f433 3766 eh->output_name = NULL;
906e58ca
NC		 3767 }
3768
3769 return entry;
3770}
3771
00a97672 3772/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3773 shortcuts to them in our hash table. */
3774
3775static bfd_boolean
57e8b36a 3776create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3777{
3778 struct elf32_arm_link_hash_table *htab;
3779
e5a52504 3780 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3781 if (htab == NULL)
3782 return FALSE;
3783
e5a52504 3784 /* BPABI objects never have a GOT, or associated sections. */
90c14f0c 3785 if (htab->root.target_os == is_symbian)
e5a52504
MM		 3786 return TRUE;
3787
5e681ec4
PB		 3788 if (! _bfd_elf_create_got_section (dynobj, info))
3789 return FALSE;
3790
e8b09b87
CL		 3791 /* Also create .rofixup. */
3792 if (htab->fdpic_p)
3793 {
3794 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3795 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3796 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
fd361982
AM		 3797 if (htab->srofixup == NULL
3798 || !bfd_set_section_alignment (htab->srofixup, 2))
e8b09b87
CL		 3799 return FALSE;
3800 }
3801
5e681ec4
PB		 3802 return TRUE;
3803}
3804
34e77a92
RS		 3805/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3806
3807static bfd_boolean
3808create_ifunc_sections (struct bfd_link_info *info)
3809{
3810 struct elf32_arm_link_hash_table *htab;
3811 const struct elf_backend_data *bed;
3812 bfd *dynobj;
3813 asection *s;
3814 flagword flags;
b38cadfb 3815
34e77a92
RS		 3816 htab = elf32_arm_hash_table (info);
3817 dynobj = htab->root.dynobj;
3818 bed = get_elf_backend_data (dynobj);
3819 flags = bed->dynamic_sec_flags;
3820
3821 if (htab->root.iplt == NULL)
3822 {
3d4d4302
AM		 3823 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3824 flags | SEC_READONLY | SEC_CODE);
34e77a92 3825 if (s == NULL
fd361982 3826 || !bfd_set_section_alignment (s, bed->plt_alignment))
34e77a92
RS		 3827 return FALSE;
3828 htab->root.iplt = s;
3829 }
3830
3831 if (htab->root.irelplt == NULL)
3832 {
3d4d4302
AM		 3833 s = bfd_make_section_anyway_with_flags (dynobj,
3834 RELOC_SECTION (htab, ".iplt"),
3835 flags | SEC_READONLY);
34e77a92 3836 if (s == NULL
fd361982 3837 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3838 return FALSE;
3839 htab->root.irelplt = s;
3840 }
3841
3842 if (htab->root.igotplt == NULL)
3843 {
3d4d4302 3844 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92 3845 if (s == NULL
fd361982 3846 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3847 return FALSE;
3848 htab->root.igotplt = s;
3849 }
3850 return TRUE;
3851}
3852
eed94f8f
NC		 3853/* Determine if we're dealing with a Thumb only architecture. */
3854
3855static bfd_boolean
3856using_thumb_only (struct elf32_arm_link_hash_table *globals)
3857{
2fd158eb
TP		 3858 int arch;
3859 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3860 Tag_CPU_arch_profile);
eed94f8f 3861
2fd158eb
TP		 3862 if (profile)
3863 return profile == 'M';
eed94f8f 3864
2fd158eb 3865 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3866
60a019a0 3867 /* Force return logic to be reviewed for each new architecture. */
031254f2 3868 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0 3869
2fd158eb
TP		 3870 if (arch == TAG_CPU_ARCH_V6_M
3871 || arch == TAG_CPU_ARCH_V6S_M
3872 || arch == TAG_CPU_ARCH_V7E_M
3873 || arch == TAG_CPU_ARCH_V8M_BASE
031254f2
AV		 3874 || arch == TAG_CPU_ARCH_V8M_MAIN
3875 || arch == TAG_CPU_ARCH_V8_1M_MAIN)
2fd158eb 3876 return TRUE;
eed94f8f 3877
2fd158eb 3878 return FALSE;
eed94f8f
NC		 3879}
3880
3881/* Determine if we're dealing with a Thumb-2 object. */
3882
3883static bfd_boolean
3884using_thumb2 (struct elf32_arm_link_hash_table *globals)
3885{
60a019a0
TP		 3886 int arch;
3887 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3888 Tag_THUMB_ISA_use);
3889
3890 if (thumb_isa)
3891 return thumb_isa == 2;
3892
3893 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3894
3895 /* Force return logic to be reviewed for each new architecture. */
031254f2 3896 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 3897
3898 return (arch == TAG_CPU_ARCH_V6T2
3899 || arch == TAG_CPU_ARCH_V7
3900 || arch == TAG_CPU_ARCH_V7E_M
3901 || arch == TAG_CPU_ARCH_V8
bff0500d 3902 || arch == TAG_CPU_ARCH_V8R
031254f2
AV		 3903 || arch == TAG_CPU_ARCH_V8M_MAIN
3904 || arch == TAG_CPU_ARCH_V8_1M_MAIN);
eed94f8f
NC		 3905}
3906
5e866f5a
TP		 3907/* Determine whether Thumb-2 BL instruction is available. */
3908
3909static bfd_boolean
3910using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3911{
3912 int arch =
3913 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3914
3915 /* Force return logic to be reviewed for each new architecture. */
031254f2 3916 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
5e866f5a
TP		 3917
3918 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3919 return (arch == TAG_CPU_ARCH_V6T2
3920 || arch >= TAG_CPU_ARCH_V7);
3921}
3922
00a97672
RS		 3923/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3924 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3925 hash table. */
3926
3927static bfd_boolean
57e8b36a 3928elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3929{
3930 struct elf32_arm_link_hash_table *htab;
3931
3932 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3933 if (htab == NULL)
3934 return FALSE;
3935
362d30a1 3936 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3937 return FALSE;
3938
3939 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3940 return FALSE;
3941
90c14f0c 3942 if (htab->root.target_os == is_vxworks)
00a97672
RS		 3943 {
3944 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3945 return FALSE;
3946
0e1862bb 3947 if (bfd_link_pic (info))
00a97672
RS		 3948 {
3949 htab->plt_header_size = 0;
3950 htab->plt_entry_size
3951 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3952 }
3953 else
3954 {
3955 htab->plt_header_size
3956 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3957 htab->plt_entry_size
3958 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3959 }
aebf9be7
NC		 3960
3961 if (elf_elfheader (dynobj))
3962 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3963 }
eed94f8f
NC		 3964 else
3965 {
3966 /* PR ld/16017
3967 Test for thumb only architectures. Note - we cannot just call
3968 using_thumb_only() as the attributes in the output bfd have not been
3969 initialised at this point, so instead we use the input bfd. */
3970 bfd * saved_obfd = htab->obfd;
3971
3972 htab->obfd = dynobj;
3973 if (using_thumb_only (htab))
3974 {
3975 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3976 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3977 }
3978 htab->obfd = saved_obfd;
3979 }
5e681ec4 3980
7801f98f
CL		 3981 if (htab->fdpic_p) {
3982 htab->plt_header_size = 0;
3983 if (info->flags & DF_BIND_NOW)
3984 htab->plt_entry_size = 4 * (ARRAY_SIZE(elf32_arm_fdpic_plt_entry) - 5);
3985 else
3986 htab->plt_entry_size = 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry);
3987 }
3988
362d30a1
RS		 3989 if (!htab->root.splt
3990 || !htab->root.srelplt
9d19e4fd
AM		 3991 || !htab->root.sdynbss
3992 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 3993 abort ();
3994
3995 return TRUE;
3996}
3997
906e58ca
NC		 3998/* Copy the extra info we tack onto an elf_link_hash_entry. */
3999
4000static void
4001elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
4002 struct elf_link_hash_entry *dir,
4003 struct elf_link_hash_entry *ind)
4004{
4005 struct elf32_arm_link_hash_entry *edir, *eind;
4006
4007 edir = (struct elf32_arm_link_hash_entry *) dir;
4008 eind = (struct elf32_arm_link_hash_entry *) ind;
4009
906e58ca
NC		 4010 if (ind->root.type == bfd_link_hash_indirect)
4011 {
4012 /* Copy over PLT info. */
34e77a92
RS		 4013 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
4014 eind->plt.thumb_refcount = 0;
4015 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
4016 eind->plt.maybe_thumb_refcount = 0;
4017 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
4018 eind->plt.noncall_refcount = 0;
4019
e8b09b87
CL		 4020 /* Copy FDPIC counters. */
4021 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
4022 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
4023 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
4024
34e77a92
RS		 4025 /* We should only allocate a function to .iplt once the final
4026 symbol information is known. */
4027 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 4028
4029 if (dir->got.refcount <= 0)
4030 {
4031 edir->tls_type = eind->tls_type;
4032 eind->tls_type = GOT_UNKNOWN;
4033 }
4034 }
4035
4036 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4037}
4038
68faa637
AM		 4039/* Destroy an ARM elf linker hash table. */
4040
4041static void
d495ab0d 4042elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 4043{
4044 struct elf32_arm_link_hash_table *ret
d495ab0d 4045 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 4046
4047 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 4048 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 4049}
4050
906e58ca
NC		 4051/* Create an ARM elf linker hash table. */
4052
4053static struct bfd_link_hash_table *
4054elf32_arm_link_hash_table_create (bfd *abfd)
4055{
4056 struct elf32_arm_link_hash_table *ret;
986f0783 4057 size_t amt = sizeof (struct elf32_arm_link_hash_table);
906e58ca 4058
7bf52ea2 4059 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 4060 if (ret == NULL)
4061 return NULL;
4062
4063 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4064 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 4065 sizeof (struct elf32_arm_link_hash_entry),
4066 ARM_ELF_DATA))
906e58ca
NC		 4067 {
4068 free (ret);
4069 return NULL;
4070 }
4071
906e58ca 4072 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 4073 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 4074#ifdef FOUR_WORD_PLT
4075 ret->plt_header_size = 16;
4076 ret->plt_entry_size = 16;
4077#else
4078 ret->plt_header_size = 20;
1db37fe6 4079 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 4080#endif
f3185997 4081 ret->use_rel = TRUE;
906e58ca 4082 ret->obfd = abfd;
617a5ada 4083 ret->fdpic_p = 0;
906e58ca
NC		 4084
4085 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4086 sizeof (struct elf32_arm_stub_hash_entry)))
4087 {
d495ab0d 4088 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 4089 return NULL;
4090 }
d495ab0d 4091 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 4092
4093 return &ret->root.root;
4094}
4095
cd1dac3d
DG		 4096/* Determine what kind of NOPs are available. */
4097
4098static bfd_boolean
4099arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4100{
4101 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4102 Tag_CPU_arch);
cd1dac3d 4103
60a019a0 4104 /* Force return logic to be reviewed for each new architecture. */
031254f2 4105 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 4106
4107 return (arch == TAG_CPU_ARCH_V6T2
4108 || arch == TAG_CPU_ARCH_V6K
4109 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 4110 || arch == TAG_CPU_ARCH_V8
4111 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 4112}
4113
f4ac8484
DJ		 4114static bfd_boolean
4115arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4116{
4117 switch (stub_type)
4118 {
fea2b4d6 4119 case arm_stub_long_branch_thumb_only:
80c135e5 4120 case arm_stub_long_branch_thumb2_only:
d5a67c02 4121 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 4122 case arm_stub_long_branch_v4t_thumb_arm:
4123 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 4124 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 4125 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 4126 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 4127 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 4128 return TRUE;
4129 case arm_stub_none:
4130 BFD_FAIL ();
4131 return FALSE;
4132 break;
4133 default:
4134 return FALSE;
4135 }
4136}
4137
906e58ca
NC		 4138/* Determine the type of stub needed, if any, for a call. */
4139
4140static enum elf32_arm_stub_type
4141arm_type_of_stub (struct bfd_link_info *info,
4142 asection *input_sec,
4143 const Elf_Internal_Rela *rel,
34e77a92 4144 unsigned char st_type,
35fc36a8 4145 enum arm_st_branch_type *actual_branch_type,
906e58ca 4146 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 4147 bfd_vma destination,
4148 asection *sym_sec,
4149 bfd *input_bfd,
4150 const char *name)
906e58ca
NC		 4151{
4152 bfd_vma location;
4153 bfd_signed_vma branch_offset;
4154 unsigned int r_type;
4155 struct elf32_arm_link_hash_table * globals;
5e866f5a 4156 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 4157 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 4158 int use_plt = 0;
35fc36a8 4159 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 4160 union gotplt_union *root_plt;
4161 struct arm_plt_info *arm_plt;
d5a67c02
AV		 4162 int arch;
4163 int thumb2_movw;
906e58ca 4164
35fc36a8 4165 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 4166 return stub_type;
4167
906e58ca 4168 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4169 if (globals == NULL)
4170 return stub_type;
906e58ca
NC		 4171
4172 thumb_only = using_thumb_only (globals);
906e58ca 4173 thumb2 = using_thumb2 (globals);
5e866f5a 4174 thumb2_bl = using_thumb2_bl (globals);
906e58ca 4175
d5a67c02
AV		 4176 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4177
4178 /* True for architectures that implement the thumb2 movw instruction. */
4179 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4180
906e58ca
NC		 4181 /* Determine where the call point is. */
4182 location = (input_sec->output_offset
4183 + input_sec->output_section->vma
4184 + rel->r_offset);
4185
906e58ca
NC		 4186 r_type = ELF32_R_TYPE (rel->r_info);
4187
39f21624
NC		 4188 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4189 are considering a function call relocation. */
c5423981 4190 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 4191 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 4192 && branch_type == ST_BRANCH_TO_ARM)
4193 branch_type = ST_BRANCH_TO_THUMB;
4194
34e77a92
RS		 4195 /* For TLS call relocs, it is the caller's responsibility to provide
4196 the address of the appropriate trampoline. */
4197 if (r_type != R_ARM_TLS_CALL
4198 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 4199 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4200 ELF32_R_SYM (rel->r_info), &root_plt,
4201 &arm_plt)
34e77a92 4202 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 4203 {
34e77a92 4204 asection *splt;
fe33d2fa 4205
34e77a92
RS		 4206 if (hash == NULL || hash->is_iplt)
4207 splt = globals->root.iplt;
4208 else
4209 splt = globals->root.splt;
4210 if (splt != NULL)
b38cadfb 4211 {
34e77a92
RS		 4212 use_plt = 1;
4213
4214 /* Note when dealing with PLT entries: the main PLT stub is in
4215 ARM mode, so if the branch is in Thumb mode, another
4216 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4217 PLT stub. If a long branch stub is needed, we'll add a
4218 Thumb->Arm one and branch directly to the ARM PLT entry.
4219 Here, we have to check if a pre-PLT Thumb->ARM stub
4220 is needed and if it will be close enough. */
34e77a92
RS		 4221
4222 destination = (splt->output_section->vma
4223 + splt->output_offset
4224 + root_plt->offset);
4225 st_type = STT_FUNC;
2df2751d
CL		 4226
4227 /* Thumb branch/call to PLT: it can become a branch to ARM
4228 or to Thumb. We must perform the same checks and
4229 corrections as in elf32_arm_final_link_relocate. */
4230 if ((r_type == R_ARM_THM_CALL)
4231 || (r_type == R_ARM_THM_JUMP24))
4232 {
4233 if (globals->use_blx
4234 && r_type == R_ARM_THM_CALL
4235 && !thumb_only)
4236 {
4237 /* If the Thumb BLX instruction is available, convert
4238 the BL to a BLX instruction to call the ARM-mode
4239 PLT entry. */
4240 branch_type = ST_BRANCH_TO_ARM;
4241 }
4242 else
4243 {
4244 if (!thumb_only)
4245 /* Target the Thumb stub before the ARM PLT entry. */
4246 destination -= PLT_THUMB_STUB_SIZE;
4247 branch_type = ST_BRANCH_TO_THUMB;
4248 }
4249 }
4250 else
4251 {
4252 branch_type = ST_BRANCH_TO_ARM;
4253 }
34e77a92 4254 }
5fa9e92f 4255 }
34e77a92
RS		 4256 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4257 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4258
fe33d2fa
CL		 4259 branch_offset = (bfd_signed_vma)(destination - location);
4260
0855e32b 4261 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4262 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4263 {
5fa9e92f
CL		 4264 /* Handle cases where:
4265 - this call goes too far (different Thumb/Thumb2 max
99059e56 4266 distance)
155d87d7 4267 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4268 Thumb->Arm branch (not bl). A stub is needed in this case,
4269 but only if this call is not through a PLT entry. Indeed,
695344c0 4270 PLT stubs handle mode switching already. */
5e866f5a 4271 if ((!thumb2_bl
906e58ca
NC		 4272 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4273 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4274 || (thumb2_bl
906e58ca
NC		 4275 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4276 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4277 || (thumb2
4278 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4279 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4280 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4281 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4282 && (((r_type == R_ARM_THM_CALL
4283 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4284 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4285 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4286 && !use_plt))
906e58ca 4287 {
2df2751d
CL		 4288 /* If we need to insert a Thumb-Thumb long branch stub to a
4289 PLT, use one that branches directly to the ARM PLT
4290 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4291 stub, undo this now. */
695344c0
NC		 4292 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4293 {
4294 branch_type = ST_BRANCH_TO_ARM;
4295 branch_offset += PLT_THUMB_STUB_SIZE;
4296 }
2df2751d 4297
35fc36a8 4298 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4299 {
4300 /* Thumb to thumb. */
4301 if (!thumb_only)
4302 {
d5a67c02 4303 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4304 _bfd_error_handler
871b3ab2 4305 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4306 " section with SHF_ARM_PURECODE section"
4307 " attribute is only supported for M-profile"
90b6238f 4308 " targets that implement the movw instruction"),
10463f39 4309 input_bfd, input_sec);
d5a67c02 4310
0e1862bb 4311 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4312 /* PIC stubs. */
155d87d7 4313 ? ((globals->use_blx
9553db3c 4314 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4315 /* V5T and above. Stub starts with ARM code, so
4316 we must be able to switch mode before
4317 reaching it, which is only possible for 'bl'
4318 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4319 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4320 /* On V4T, use Thumb code only. */
d3626fb0 4321 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4322
4323 /* non-PIC stubs. */
155d87d7 4324 : ((globals->use_blx
9553db3c 4325 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4326 /* V5T and above. */
4327 ? arm_stub_long_branch_any_any
4328 /* V4T. */
d3626fb0 4329 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4330 }
4331 else
4332 {
d5a67c02
AV		 4333 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4334 stub_type = arm_stub_long_branch_thumb2_only_pure;
4335 else
4336 {
4337 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4338 _bfd_error_handler
871b3ab2 4339 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4340 " section with SHF_ARM_PURECODE section"
4341 " attribute is only supported for M-profile"
90b6238f 4342 " targets that implement the movw instruction"),
10463f39 4343 input_bfd, input_sec);
d5a67c02
AV		 4344
4345 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4346 /* PIC stub. */
4347 ? arm_stub_long_branch_thumb_only_pic
4348 /* non-PIC stub. */
4349 : (thumb2 ? arm_stub_long_branch_thumb2_only
4350 : arm_stub_long_branch_thumb_only);
4351 }
906e58ca
NC		 4352 }
4353 }
4354 else
4355 {
d5a67c02 4356 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4357 _bfd_error_handler
871b3ab2 4358 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4359 " section with SHF_ARM_PURECODE section"
4360 " attribute is only supported" " for M-profile"
90b6238f 4361 " targets that implement the movw instruction"),
10463f39 4362 input_bfd, input_sec);
d5a67c02 4363
906e58ca 4364 /* Thumb to arm. */
c820be07
NC		 4365 if (sym_sec != NULL
4366 && sym_sec->owner != NULL
4367 && !INTERWORK_FLAG (sym_sec->owner))
4368 {
4eca0228 4369 _bfd_error_handler
90b6238f
AM		 4370 (_("%pB(%s): warning: interworking not enabled;"
4371 " first occurrence: %pB: %s call to %s"),
4372 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4373 }
4374
0855e32b 4375 stub_type =
0e1862bb 4376 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4377 /* PIC stubs. */
0855e32b 4378 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4379 /* TLS PIC stubs. */
0855e32b
NS		 4380 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4381 : arm_stub_long_branch_v4t_thumb_tls_pic)
4382 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4383 /* V5T PIC and above. */
4384 ? arm_stub_long_branch_any_arm_pic
4385 /* V4T PIC stub. */
4386 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4387
4388 /* non-PIC stubs. */
0855e32b 4389 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4390 /* V5T and above. */
4391 ? arm_stub_long_branch_any_any
4392 /* V4T. */
4393 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4394
4395 /* Handle v4t short branches. */
fea2b4d6 4396 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4397 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4398 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4399 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4400 }
4401 }
4402 }
fe33d2fa
CL		 4403 else if (r_type == R_ARM_CALL
4404 || r_type == R_ARM_JUMP24
0855e32b
NS		 4405 || r_type == R_ARM_PLT32
4406 || r_type == R_ARM_TLS_CALL)
906e58ca 4407 {
d5a67c02 4408 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4409 _bfd_error_handler
871b3ab2 4410 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4411 " section with SHF_ARM_PURECODE section"
4412 " attribute is only supported for M-profile"
90b6238f 4413 " targets that implement the movw instruction"),
10463f39 4414 input_bfd, input_sec);
35fc36a8 4415 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4416 {
4417 /* Arm to thumb. */
c820be07
NC		 4418
4419 if (sym_sec != NULL
4420 && sym_sec->owner != NULL
4421 && !INTERWORK_FLAG (sym_sec->owner))
4422 {
4eca0228 4423 _bfd_error_handler
90b6238f
AM		 4424 (_("%pB(%s): warning: interworking not enabled;"
4425 " first occurrence: %pB: %s call to %s"),
4426 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4427 }
4428
4429 /* We have an extra 2-bytes reach because of
4430 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4431 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4432 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4433 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4434 || (r_type == R_ARM_JUMP24)
4435 || (r_type == R_ARM_PLT32))
906e58ca 4436 {
0e1862bb 4437 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4438 /* PIC stubs. */
ebe24dd4
CL		 4439 ? ((globals->use_blx)
4440 /* V5T and above. */
4441 ? arm_stub_long_branch_any_thumb_pic
4442 /* V4T stub. */
4443 : arm_stub_long_branch_v4t_arm_thumb_pic)
4444
c2b4a39d
CL		 4445 /* non-PIC stubs. */
4446 : ((globals->use_blx)
4447 /* V5T and above. */
4448 ? arm_stub_long_branch_any_any
4449 /* V4T. */
4450 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4451 }
4452 }
4453 else
4454 {
4455 /* Arm to arm. */
4456 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4457 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4458 {
0855e32b 4459 stub_type =
0e1862bb 4460 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4461 /* PIC stubs. */
0855e32b 4462 ? (r_type == R_ARM_TLS_CALL
6a631e86 4463 /* TLS PIC Stub. */
0855e32b 4464 ? arm_stub_long_branch_any_tls_pic
90c14f0c 4465 : (globals->root.target_os == is_nacl
7a89b94e
NC		 4466 ? arm_stub_long_branch_arm_nacl_pic
4467 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4468 /* non-PIC stubs. */
90c14f0c 4469 : (globals->root.target_os == is_nacl
7a89b94e
NC		 4470 ? arm_stub_long_branch_arm_nacl
4471 : arm_stub_long_branch_any_any);
906e58ca
NC		 4472 }
4473 }
4474 }
4475
fe33d2fa
CL		 4476 /* If a stub is needed, record the actual destination type. */
4477 if (stub_type != arm_stub_none)
35fc36a8 4478 *actual_branch_type = branch_type;
fe33d2fa 4479
906e58ca
NC		 4480 return stub_type;
4481}
4482
4483/* Build a name for an entry in the stub hash table. */
4484
4485static char *
4486elf32_arm_stub_name (const asection *input_section,
4487 const asection *sym_sec,
4488 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4489 const Elf_Internal_Rela *rel,
4490 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4491{
4492 char *stub_name;
4493 bfd_size_type len;
4494
4495 if (hash)
4496 {
fe33d2fa 4497 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4498 stub_name = (char *) bfd_malloc (len);
906e58ca 4499 if (stub_name != NULL)
fe33d2fa 4500 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4501 input_section->id & 0xffffffff,
4502 hash->root.root.root.string,
fe33d2fa
CL		 4503 (int) rel->r_addend & 0xffffffff,
4504 (int) stub_type);
906e58ca
NC		 4505 }
4506 else
4507 {
fe33d2fa 4508 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4509 stub_name = (char *) bfd_malloc (len);
906e58ca 4510 if (stub_name != NULL)
fe33d2fa 4511 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4512 input_section->id & 0xffffffff,
4513 sym_sec->id & 0xffffffff,
0855e32b
NS		 4514 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4515 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4516 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4517 (int) rel->r_addend & 0xffffffff,
4518 (int) stub_type);
906e58ca
NC		 4519 }
4520
4521 return stub_name;
4522}
4523
4524/* Look up an entry in the stub hash. Stub entries are cached because
4525 creating the stub name takes a bit of time. */
4526
4527static struct elf32_arm_stub_hash_entry *
4528elf32_arm_get_stub_entry (const asection *input_section,
4529 const asection *sym_sec,
4530 struct elf_link_hash_entry *hash,
4531 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4532 struct elf32_arm_link_hash_table *htab,
4533 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4534{
4535 struct elf32_arm_stub_hash_entry *stub_entry;
4536 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4537 const asection *id_sec;
4538
4539 if ((input_section->flags & SEC_CODE) == 0)
4540 return NULL;
4541
4d83e8d9
CL		 4542 /* If the input section is the CMSE stubs one and it needs a long
4543 branch stub to reach it's final destination, give up with an
4544 error message: this is not supported. See PR ld/24709. */
4545 if (!strncmp (input_section->name, CMSE_STUB_NAME, strlen(CMSE_STUB_NAME)))
4546 {
4547 bfd *output_bfd = htab->obfd;
4548 asection *out_sec = bfd_get_section_by_name (output_bfd, CMSE_STUB_NAME);
4549
4550 _bfd_error_handler (_("ERROR: CMSE stub (%s section) too far "
4551 "(%#" PRIx64 ") from destination (%#" PRIx64 ")"),
4552 CMSE_STUB_NAME,
4553 (uint64_t)out_sec->output_section->vma
4554 + out_sec->output_offset,
4555 (uint64_t)sym_sec->output_section->vma
4556 + sym_sec->output_offset
4557 + h->root.root.u.def.value);
4558 /* Exit, rather than leave incompletely processed
4559 relocations. */
4560 xexit(1);
4561 }
4562
906e58ca
NC		 4563 /* If this input section is part of a group of sections sharing one
4564 stub section, then use the id of the first section in the group.
4565 Stub names need to include a section id, as there may well be
4566 more than one stub used to reach say, printf, and we need to
4567 distinguish between them. */
c2abbbeb 4568 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4569 id_sec = htab->stub_group[input_section->id].link_sec;
4570
4571 if (h != NULL && h->stub_cache != NULL
4572 && h->stub_cache->h == h
fe33d2fa
CL		 4573 && h->stub_cache->id_sec == id_sec
4574 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4575 {
4576 stub_entry = h->stub_cache;
4577 }
4578 else
4579 {
4580 char *stub_name;
4581
fe33d2fa 4582 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4583 if (stub_name == NULL)
4584 return NULL;
4585
4586 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4587 stub_name, FALSE, FALSE);
4588 if (h != NULL)
4589 h->stub_cache = stub_entry;
4590
4591 free (stub_name);
4592 }
4593
4594 return stub_entry;
4595}
4596
daa4adae
TP		 4597/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4598 section. */
4599
4600static bfd_boolean
4601arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4602{
4603 if (stub_type >= max_stub_type)
4604 abort (); /* Should be unreachable. */
4605
4ba2ef8f
TP		 4606 switch (stub_type)
4607 {
4608 case arm_stub_cmse_branch_thumb_only:
4609 return TRUE;
4610
4611 default:
4612 return FALSE;
4613 }
4614
4615 abort (); /* Should be unreachable. */
daa4adae
TP		 4616}
4617
4618/* Required alignment (as a power of 2) for the dedicated section holding
4619 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4620 with input sections. */
4621
4622static int
4623arm_dedicated_stub_output_section_required_alignment
4624 (enum elf32_arm_stub_type stub_type)
4625{
4626 if (stub_type >= max_stub_type)
4627 abort (); /* Should be unreachable. */
4628
4ba2ef8f
TP		 4629 switch (stub_type)
4630 {
4631 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4632 boundary. */
4633 case arm_stub_cmse_branch_thumb_only:
4634 return 5;
4635
4636 default:
4637 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4638 return 0;
4639 }
4640
4641 abort (); /* Should be unreachable. */
daa4adae
TP		 4642}
4643
4644/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4645 NULL if veneers of this type are interspersed with input sections. */
4646
4647static const char *
4648arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4649{
4650 if (stub_type >= max_stub_type)
4651 abort (); /* Should be unreachable. */
4652
4ba2ef8f
TP		 4653 switch (stub_type)
4654 {
4655 case arm_stub_cmse_branch_thumb_only:
4d83e8d9 4656 return CMSE_STUB_NAME;
4ba2ef8f
TP		 4657
4658 default:
4659 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4660 return NULL;
4661 }
4662
4663 abort (); /* Should be unreachable. */
daa4adae
TP		 4664}
4665
4666/* If veneers of type STUB_TYPE should go in a dedicated output section,
4667 returns the address of the hash table field in HTAB holding a pointer to the
4668 corresponding input section. Otherwise, returns NULL. */
4669
4670static asection **
4ba2ef8f
TP		 4671arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4672 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4673{
4674 if (stub_type >= max_stub_type)
4675 abort (); /* Should be unreachable. */
4676
4ba2ef8f
TP		 4677 switch (stub_type)
4678 {
4679 case arm_stub_cmse_branch_thumb_only:
4680 return &htab->cmse_stub_sec;
4681
4682 default:
4683 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4684 return NULL;
4685 }
4686
4687 abort (); /* Should be unreachable. */
daa4adae
TP		 4688}
4689
4690/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4691 is the section that branch into veneer and can be NULL if stub should go in
4692 a dedicated output section. Returns a pointer to the stub section, and the
4693 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4694 LINK_SEC_P may be NULL. */
906e58ca 4695
48229727
JB		 4696static asection *
4697elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4698 struct elf32_arm_link_hash_table *htab,
4699 enum elf32_arm_stub_type stub_type)
906e58ca 4700{
daa4adae
TP		 4701 asection *link_sec, *out_sec, **stub_sec_p;
4702 const char *stub_sec_prefix;
4703 bfd_boolean dedicated_output_section =
4704 arm_dedicated_stub_output_section_required (stub_type);
4705 int align;
906e58ca 4706
daa4adae 4707 if (dedicated_output_section)
906e58ca 4708 {
daa4adae
TP		 4709 bfd *output_bfd = htab->obfd;
4710 const char *out_sec_name =
4711 arm_dedicated_stub_output_section_name (stub_type);
4712 link_sec = NULL;
4713 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4714 stub_sec_prefix = out_sec_name;
4715 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4716 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4717 if (out_sec == NULL)
906e58ca 4718 {
90b6238f 4719 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4720 "section %s"), out_sec_name);
daa4adae 4721 return NULL;
906e58ca 4722 }
daa4adae
TP		 4723 }
4724 else
4725 {
c2abbbeb 4726 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4727 link_sec = htab->stub_group[section->id].link_sec;
4728 BFD_ASSERT (link_sec != NULL);
4729 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4730 if (*stub_sec_p == NULL)
4731 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4732 stub_sec_prefix = link_sec->name;
4733 out_sec = link_sec->output_section;
90c14f0c 4734 align = htab->root.target_os == is_nacl ? 4 : 3;
906e58ca 4735 }
b38cadfb 4736
daa4adae
TP		 4737 if (*stub_sec_p == NULL)
4738 {
4739 size_t namelen;
4740 bfd_size_type len;
4741 char *s_name;
4742
4743 namelen = strlen (stub_sec_prefix);
4744 len = namelen + sizeof (STUB_SUFFIX);
4745 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4746 if (s_name == NULL)
4747 return NULL;
4748
4749 memcpy (s_name, stub_sec_prefix, namelen);
4750 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4751 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4752 align);
4753 if (*stub_sec_p == NULL)
4754 return NULL;
4755
4756 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4757 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4758 | SEC_KEEP;
4759 }
4760
4761 if (!dedicated_output_section)
4762 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4763
48229727
JB		 4764 if (link_sec_p)
4765 *link_sec_p = link_sec;
b38cadfb 4766
daa4adae 4767 return *stub_sec_p;
48229727
JB		 4768}
4769
4770/* Add a new stub entry to the stub hash. Not all fields of the new
4771 stub entry are initialised. */
4772
4773static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4774elf32_arm_add_stub (const char *stub_name, asection *section,
4775 struct elf32_arm_link_hash_table *htab,
4776 enum elf32_arm_stub_type stub_type)
48229727
JB		 4777{
4778 asection *link_sec;
4779 asection *stub_sec;
4780 struct elf32_arm_stub_hash_entry *stub_entry;
4781
daa4adae
TP		 4782 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4783 stub_type);
48229727
JB		 4784 if (stub_sec == NULL)
4785 return NULL;
906e58ca
NC		 4786
4787 /* Enter this entry into the linker stub hash table. */
4788 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4789 TRUE, FALSE);
4790 if (stub_entry == NULL)
4791 {
6bde4c52
TP		 4792 if (section == NULL)
4793 section = stub_sec;
871b3ab2 4794 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4795 section->owner, stub_name);
906e58ca
NC		 4796 return NULL;
4797 }
4798
4799 stub_entry->stub_sec = stub_sec;
0955507f 4800 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4801 stub_entry->id_sec = link_sec;
4802
906e58ca
NC		 4803 return stub_entry;
4804}
4805
4806/* Store an Arm insn into an output section not processed by
4807 elf32_arm_write_section. */
4808
4809static void
8029a119
NC		 4810put_arm_insn (struct elf32_arm_link_hash_table * htab,
4811 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4812{
4813 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4814 bfd_putl32 (val, ptr);
4815 else
4816 bfd_putb32 (val, ptr);
4817}
4818
4819/* Store a 16-bit Thumb insn into an output section not processed by
4820 elf32_arm_write_section. */
4821
4822static void
8029a119
NC		 4823put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4824 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4825{
4826 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4827 bfd_putl16 (val, ptr);
4828 else
4829 bfd_putb16 (val, ptr);
4830}
4831
a504d23a
LA		 4832/* Store a Thumb2 insn into an output section not processed by
4833 elf32_arm_write_section. */
4834
4835static void
4836put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4837 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4838{
4839 /* T2 instructions are 16-bit streamed. */
4840 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4841 {
4842 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4843 bfd_putl16 ((val & 0xffff), ptr + 2);
4844 }
4845 else
4846 {
4847 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4848 bfd_putb16 ((val & 0xffff), ptr + 2);
4849 }
4850}
4851
0855e32b
NS		 4852/* If it's possible to change R_TYPE to a more efficient access
4853 model, return the new reloc type. */
4854
4855static unsigned
b38cadfb 4856elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4857 struct elf_link_hash_entry *h)
4858{
4859 int is_local = (h == NULL);
4860
9cb09e33 4861 if (bfd_link_dll (info)
0e1862bb 4862 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4863 return r_type;
4864
b38cadfb 4865 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4866 switch (r_type)
4867 {
4868 case R_ARM_TLS_GOTDESC:
4869 case R_ARM_TLS_CALL:
4870 case R_ARM_THM_TLS_CALL:
4871 case R_ARM_TLS_DESCSEQ:
4872 case R_ARM_THM_TLS_DESCSEQ:
4873 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4874 }
4875
4876 return r_type;
4877}
4878
48229727
JB		 4879static bfd_reloc_status_type elf32_arm_final_link_relocate
4880 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4881 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4882 const char *, unsigned char, enum arm_st_branch_type,
4883 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4884
4563a860
JB		 4885static unsigned int
4886arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4887{
4888 switch (stub_type)
4889 {
4890 case arm_stub_a8_veneer_b_cond:
4891 case arm_stub_a8_veneer_b:
4892 case arm_stub_a8_veneer_bl:
4893 return 2;
4894
4895 case arm_stub_long_branch_any_any:
4896 case arm_stub_long_branch_v4t_arm_thumb:
4897 case arm_stub_long_branch_thumb_only:
80c135e5 4898 case arm_stub_long_branch_thumb2_only:
d5a67c02 4899 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4900 case arm_stub_long_branch_v4t_thumb_thumb:
4901 case arm_stub_long_branch_v4t_thumb_arm:
4902 case arm_stub_short_branch_v4t_thumb_arm:
4903 case arm_stub_long_branch_any_arm_pic:
4904 case arm_stub_long_branch_any_thumb_pic:
4905 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4906 case arm_stub_long_branch_v4t_arm_thumb_pic:
4907 case arm_stub_long_branch_v4t_thumb_arm_pic:
4908 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4909 case arm_stub_long_branch_any_tls_pic:
4910 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4911 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4912 case arm_stub_a8_veneer_blx:
4913 return 4;
b38cadfb 4914
7a89b94e
NC		 4915 case arm_stub_long_branch_arm_nacl:
4916 case arm_stub_long_branch_arm_nacl_pic:
4917 return 16;
4918
4563a860
JB		 4919 default:
4920 abort (); /* Should be unreachable. */
4921 }
4922}
4923
4f4faa4d
TP		 4924/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4925 veneering (TRUE) or have their own symbol (FALSE). */
4926
4927static bfd_boolean
4928arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4929{
4930 if (stub_type >= max_stub_type)
4931 abort (); /* Should be unreachable. */
4932
4ba2ef8f
TP		 4933 switch (stub_type)
4934 {
4935 case arm_stub_cmse_branch_thumb_only:
4936 return TRUE;
4937
4938 default:
4939 return FALSE;
4940 }
4941
4942 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4943}
4944
d7c5bd02
TP		 4945/* Returns the padding needed for the dedicated section used stubs of type
4946 STUB_TYPE. */
4947
4948static int
4949arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4950{
4951 if (stub_type >= max_stub_type)
4952 abort (); /* Should be unreachable. */
4953
4ba2ef8f
TP		 4954 switch (stub_type)
4955 {
4956 case arm_stub_cmse_branch_thumb_only:
4957 return 32;
4958
4959 default:
4960 return 0;
4961 }
4962
4963 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4964}
4965
0955507f
TP		 4966/* If veneers of type STUB_TYPE should go in a dedicated output section,
4967 returns the address of the hash table field in HTAB holding the offset at
4968 which new veneers should be layed out in the stub section. */
4969
4970static bfd_vma*
4971arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4972 enum elf32_arm_stub_type stub_type)
4973{
4974 switch (stub_type)
4975 {
4976 case arm_stub_cmse_branch_thumb_only:
4977 return &htab->new_cmse_stub_offset;
4978
4979 default:
4980 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4981 return NULL;
4982 }
4983}
4984
906e58ca
NC		 4985static bfd_boolean
4986arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4987 void * in_arg)
4988{
7a89b94e 4989#define MAXRELOCS 3
0955507f 4990 bfd_boolean removed_sg_veneer;
906e58ca 4991 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4992 struct elf32_arm_link_hash_table *globals;
906e58ca 4993 struct bfd_link_info *info;
906e58ca
NC		 4994 asection *stub_sec;
4995 bfd *stub_bfd;
906e58ca
NC		 4996 bfd_byte *loc;
4997 bfd_vma sym_value;
4998 int template_size;
4999 int size;
d3ce72d0 5000 const insn_sequence *template_sequence;
906e58ca 5001 int i;
48229727
JB		 5002 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
5003 int stub_reloc_offset[MAXRELOCS] = {0, 0};
5004 int nrelocs = 0;
0955507f 5005 int just_allocated = 0;
906e58ca
NC		 5006
5007 /* Massage our args to the form they really have. */
5008 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5009 info = (struct bfd_link_info *) in_arg;
5010
abf874aa
CL		 5011 /* Fail if the target section could not be assigned to an output
5012 section. The user should fix his linker script. */
5013 if (stub_entry->target_section->output_section == NULL
5014 && info->non_contiguous_regions)
53215f21
CL		 5015 info->callbacks->einfo (_("%F%P: Could not assign '%pA' to an output section. "
5016 "Retry without --enable-non-contiguous-regions.\n"),
5017 stub_entry->target_section);
abf874aa 5018
906e58ca 5019 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5020 if (globals == NULL)
5021 return FALSE;
906e58ca 5022
906e58ca
NC		 5023 stub_sec = stub_entry->stub_sec;
5024
4dfe6ac6 5025 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 5026 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
5027 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 5028 return TRUE;
fe33d2fa 5029
0955507f
TP		 5030 /* Assign a slot at the end of section if none assigned yet. */
5031 if (stub_entry->stub_offset == (bfd_vma) -1)
5032 {
5033 stub_entry->stub_offset = stub_sec->size;
5034 just_allocated = 1;
5035 }
906e58ca
NC		 5036 loc = stub_sec->contents + stub_entry->stub_offset;
5037
5038 stub_bfd = stub_sec->owner;
5039
906e58ca
NC		 5040 /* This is the address of the stub destination. */
5041 sym_value = (stub_entry->target_value
5042 + stub_entry->target_section->output_offset
5043 + stub_entry->target_section->output_section->vma);
5044
d3ce72d0 5045 template_sequence = stub_entry->stub_template;
461a49ca 5046 template_size = stub_entry->stub_template_size;
906e58ca
NC		 5047
5048 size = 0;
461a49ca 5049 for (i = 0; i < template_size; i++)
906e58ca 5050 {
d3ce72d0 5051 switch (template_sequence[i].type)
461a49ca
DJ		 5052 {
5053 case THUMB16_TYPE:
48229727 5054 {
d3ce72d0
NC		 5055 bfd_vma data = (bfd_vma) template_sequence[i].data;
5056 if (template_sequence[i].reloc_addend != 0)
48229727 5057 {
99059e56
RM		 5058 /* We've borrowed the reloc_addend field to mean we should
5059 insert a condition code into this (Thumb-1 branch)
5060 instruction. See THUMB16_BCOND_INSN. */
5061 BFD_ASSERT ((data & 0xff00) == 0xd000);
5062 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 5063 }
fe33d2fa 5064 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 5065 size += 2;
5066 }
461a49ca 5067 break;
906e58ca 5068
48229727 5069 case THUMB32_TYPE:
fe33d2fa
CL		 5070 bfd_put_16 (stub_bfd,
5071 (template_sequence[i].data >> 16) & 0xffff,
5072 loc + size);
5073 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5074 loc + size + 2);
99059e56
RM		 5075 if (template_sequence[i].r_type != R_ARM_NONE)
5076 {
5077 stub_reloc_idx[nrelocs] = i;
5078 stub_reloc_offset[nrelocs++] = size;
5079 }
5080 size += 4;
5081 break;
48229727 5082
461a49ca 5083 case ARM_TYPE:
fe33d2fa
CL		 5084 bfd_put_32 (stub_bfd, template_sequence[i].data,
5085 loc + size);
461a49ca
DJ		 5086 /* Handle cases where the target is encoded within the
5087 instruction. */
d3ce72d0 5088 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 5089 {
48229727
JB		 5090 stub_reloc_idx[nrelocs] = i;
5091 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5092 }
5093 size += 4;
5094 break;
5095
5096 case DATA_TYPE:
d3ce72d0 5097 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 5098 stub_reloc_idx[nrelocs] = i;
5099 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5100 size += 4;
5101 break;
5102
5103 default:
5104 BFD_FAIL ();
5105 return FALSE;
5106 }
906e58ca 5107 }
461a49ca 5108
0955507f
TP		 5109 if (just_allocated)
5110 stub_sec->size += size;
906e58ca 5111
461a49ca
DJ		 5112 /* Stub size has already been computed in arm_size_one_stub. Check
5113 consistency. */
5114 BFD_ASSERT (size == stub_entry->stub_size);
5115
906e58ca 5116 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 5117 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 5118 sym_value |= 1;
5119
0955507f
TP		 5120 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5121 to relocate in each stub. */
5122 removed_sg_veneer =
5123 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5124 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 5125
48229727 5126 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 5127 {
5128 Elf_Internal_Rela rel;
5129 bfd_boolean unresolved_reloc;
5130 char *error_message;
5131 bfd_vma points_to =
5132 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5133
5134 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5135 rel.r_info = ELF32_R_INFO (0,
5136 template_sequence[stub_reloc_idx[i]].r_type);
5137 rel.r_addend = 0;
5138
5139 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5140 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5141 template should refer back to the instruction after the original
5142 branch. We use target_section as Cortex-A8 erratum workaround stubs
5143 are only generated when both source and target are in the same
5144 section. */
5145 points_to = stub_entry->target_section->output_section->vma
5146 + stub_entry->target_section->output_offset
5147 + stub_entry->source_value;
5148
5149 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5150 (template_sequence[stub_reloc_idx[i]].r_type),
5151 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5152 points_to, info, stub_entry->target_section, "", STT_FUNC,
5153 stub_entry->branch_type,
5154 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5155 &error_message);
5156 }
906e58ca
NC		 5157
5158 return TRUE;
48229727 5159#undef MAXRELOCS
906e58ca
NC		 5160}
5161
48229727
JB		 5162/* Calculate the template, template size and instruction size for a stub.
5163 Return value is the instruction size. */
906e58ca 5164
48229727
JB		 5165static unsigned int
5166find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5167 const insn_sequence **stub_template,
5168 int *stub_template_size)
906e58ca 5169{
d3ce72d0 5170 const insn_sequence *template_sequence = NULL;
48229727
JB		 5171 int template_size = 0, i;
5172 unsigned int size;
906e58ca 5173
d3ce72d0 5174 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 5175 if (stub_template)
5176 *stub_template = template_sequence;
5177
48229727 5178 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 5179 if (stub_template_size)
5180 *stub_template_size = template_size;
906e58ca
NC		 5181
5182 size = 0;
461a49ca
DJ		 5183 for (i = 0; i < template_size; i++)
5184 {
d3ce72d0 5185 switch (template_sequence[i].type)
461a49ca
DJ		 5186 {
5187 case THUMB16_TYPE:
5188 size += 2;
5189 break;
5190
5191 case ARM_TYPE:
48229727 5192 case THUMB32_TYPE:
461a49ca
DJ		 5193 case DATA_TYPE:
5194 size += 4;
5195 break;
5196
5197 default:
5198 BFD_FAIL ();
2a229407 5199 return 0;
461a49ca
DJ		 5200 }
5201 }
5202
48229727
JB		 5203 return size;
5204}
5205
5206/* As above, but don't actually build the stub. Just bump offset so
5207 we know stub section sizes. */
5208
5209static bfd_boolean
5210arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 5211 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 5212{
5213 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 5214 const insn_sequence *template_sequence;
48229727
JB		 5215 int template_size, size;
5216
5217 /* Massage our args to the form they really have. */
5218 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 5219
5220 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
5221 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
5222
d3ce72d0 5223 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 5224 &template_size);
5225
0955507f
TP		 5226 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5227 if (stub_entry->stub_template_size)
5228 {
5229 stub_entry->stub_size = size;
5230 stub_entry->stub_template = template_sequence;
5231 stub_entry->stub_template_size = template_size;
5232 }
5233
5234 /* Already accounted for. */
5235 if (stub_entry->stub_offset != (bfd_vma) -1)
5236 return TRUE;
461a49ca 5237
906e58ca
NC		 5238 size = (size + 7) & ~7;
5239 stub_entry->stub_sec->size += size;
461a49ca 5240
906e58ca
NC		 5241 return TRUE;
5242}
5243
5244/* External entry points for sizing and building linker stubs. */
5245
5246/* Set up various things so that we can make a list of input sections
5247 for each output section included in the link. Returns -1 on error,
5248 0 when no stubs will be needed, and 1 on success. */
5249
5250int
5251elf32_arm_setup_section_lists (bfd *output_bfd,
5252 struct bfd_link_info *info)
5253{
5254 bfd *input_bfd;
5255 unsigned int bfd_count;
7292b3ac 5256 unsigned int top_id, top_index;
906e58ca
NC		 5257 asection *section;
5258 asection **input_list, **list;
986f0783 5259 size_t amt;
906e58ca
NC		 5260 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5261
4dfe6ac6
NC		 5262 if (htab == NULL)
5263 return 0;
906e58ca
NC		 5264 if (! is_elf_hash_table (htab))
5265 return 0;
5266
5267 /* Count the number of input BFDs and find the top input section id. */
5268 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5269 input_bfd != NULL;
c72f2fb2 5270 input_bfd = input_bfd->link.next)
906e58ca
NC		 5271 {
5272 bfd_count += 1;
5273 for (section = input_bfd->sections;
5274 section != NULL;
5275 section = section->next)
5276 {
5277 if (top_id < section->id)
5278 top_id = section->id;
5279 }
5280 }
5281 htab->bfd_count = bfd_count;
5282
5283 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5284 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5285 if (htab->stub_group == NULL)
5286 return -1;
fe33d2fa 5287 htab->top_id = top_id;
906e58ca
NC		 5288
5289 /* We can't use output_bfd->section_count here to find the top output
5290 section index as some sections may have been removed, and
5291 _bfd_strip_section_from_output doesn't renumber the indices. */
5292 for (section = output_bfd->sections, top_index = 0;
5293 section != NULL;
5294 section = section->next)
5295 {
5296 if (top_index < section->index)
5297 top_index = section->index;
5298 }
5299
5300 htab->top_index = top_index;
5301 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5302 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5303 htab->input_list = input_list;
5304 if (input_list == NULL)
5305 return -1;
5306
5307 /* For sections we aren't interested in, mark their entries with a
5308 value we can check later. */
5309 list = input_list + top_index;
5310 do
5311 *list = bfd_abs_section_ptr;
5312 while (list-- != input_list);
5313
5314 for (section = output_bfd->sections;
5315 section != NULL;
5316 section = section->next)
5317 {
5318 if ((section->flags & SEC_CODE) != 0)
5319 input_list[section->index] = NULL;
5320 }
5321
5322 return 1;
5323}
5324
5325/* The linker repeatedly calls this function for each input section,
5326 in the order that input sections are linked into output sections.
5327 Build lists of input sections to determine groupings between which
5328 we may insert linker stubs. */
5329
5330void
5331elf32_arm_next_input_section (struct bfd_link_info *info,
5332 asection *isec)
5333{
5334 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5335
4dfe6ac6
NC		 5336 if (htab == NULL)
5337 return;
5338
906e58ca
NC		 5339 if (isec->output_section->index <= htab->top_index)
5340 {
5341 asection **list = htab->input_list + isec->output_section->index;
5342
a7470592 5343 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5344 {
5345 /* Steal the link_sec pointer for our list. */
5346#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5347 /* This happens to make the list in reverse order,
07d72278 5348 which we reverse later. */
906e58ca
NC		 5349 PREV_SEC (isec) = *list;
5350 *list = isec;
5351 }
5352 }
5353}
5354
5355/* See whether we can group stub sections together. Grouping stub
5356 sections may result in fewer stubs. More importantly, we need to
07d72278 5357 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5358 .fini output sections respectively, because glibc splits the
5359 _init and _fini functions into multiple parts. Putting a stub in
5360 the middle of a function is not a good idea. */
5361
5362static void
5363group_sections (struct elf32_arm_link_hash_table *htab,
5364 bfd_size_type stub_group_size,
07d72278 5365 bfd_boolean stubs_always_after_branch)
906e58ca 5366{
07d72278 5367 asection **list = htab->input_list;
906e58ca
NC		 5368
5369 do
5370 {
5371 asection *tail = *list;
07d72278 5372 asection *head;
906e58ca
NC		 5373
5374 if (tail == bfd_abs_section_ptr)
5375 continue;
5376
07d72278
DJ		 5377 /* Reverse the list: we must avoid placing stubs at the
5378 beginning of the section because the beginning of the text
5379 section may be required for an interrupt vector in bare metal
5380 code. */
5381#define NEXT_SEC PREV_SEC
e780aef2
CL		 5382 head = NULL;
5383 while (tail != NULL)
99059e56
RM		 5384 {
5385 /* Pop from tail. */
5386 asection *item = tail;
5387 tail = PREV_SEC (item);
e780aef2 5388
99059e56
RM		 5389 /* Push on head. */
5390 NEXT_SEC (item) = head;
5391 head = item;
5392 }
07d72278
DJ		 5393
5394 while (head != NULL)
906e58ca
NC		 5395 {
5396 asection *curr;
07d72278 5397 asection *next;
e780aef2
CL		 5398 bfd_vma stub_group_start = head->output_offset;
5399 bfd_vma end_of_next;
906e58ca 5400
07d72278 5401 curr = head;
e780aef2 5402 while (NEXT_SEC (curr) != NULL)
8cd931b7 5403 {
e780aef2
CL		 5404 next = NEXT_SEC (curr);
5405 end_of_next = next->output_offset + next->size;
5406 if (end_of_next - stub_group_start >= stub_group_size)
5407 /* End of NEXT is too far from start, so stop. */
8cd931b7 5408 break;
e780aef2
CL		 5409 /* Add NEXT to the group. */
5410 curr = next;
8cd931b7 5411 }
906e58ca 5412
07d72278 5413 /* OK, the size from the start to the start of CURR is less
906e58ca 5414 than stub_group_size and thus can be handled by one stub
07d72278 5415 section. (Or the head section is itself larger than
906e58ca
NC		 5416 stub_group_size, in which case we may be toast.)
5417 We should really be keeping track of the total size of
5418 stubs added here, as stubs contribute to the final output
7fb9f789 5419 section size. */
906e58ca
NC		 5420 do
5421 {
07d72278 5422 next = NEXT_SEC (head);
906e58ca 5423 /* Set up this stub group. */
07d72278 5424 htab->stub_group[head->id].link_sec = curr;
906e58ca 5425 }
07d72278 5426 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5427
5428 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5429 bytes after the stub section can be handled by it too. */
5430 if (!stubs_always_after_branch)
906e58ca 5431 {
e780aef2
CL		 5432 stub_group_start = curr->output_offset + curr->size;
5433
8cd931b7 5434 while (next != NULL)
906e58ca 5435 {
e780aef2
CL		 5436 end_of_next = next->output_offset + next->size;
5437 if (end_of_next - stub_group_start >= stub_group_size)
5438 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5439 break;
e780aef2 5440 /* Add NEXT to the stub group. */
07d72278
DJ		 5441 head = next;
5442 next = NEXT_SEC (head);
5443 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5444 }
5445 }
07d72278 5446 head = next;
906e58ca
NC		 5447 }
5448 }
07d72278 5449 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5450
5451 free (htab->input_list);
5452#undef PREV_SEC
07d72278 5453#undef NEXT_SEC
906e58ca
NC		 5454}
5455
48229727
JB		 5456/* Comparison function for sorting/searching relocations relating to Cortex-A8
5457 erratum fix. */
5458
5459static int
5460a8_reloc_compare (const void *a, const void *b)
5461{
21d799b5
NC		 5462 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5463 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5464
5465 if (ra->from < rb->from)
5466 return -1;
5467 else if (ra->from > rb->from)
5468 return 1;
5469 else
5470 return 0;
5471}
5472
5473static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5474 const char *, char **);
5475
5476/* Helper function to scan code for sequences which might trigger the Cortex-A8
5477 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5478 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5479 otherwise. */
5480
81694485
NC		 5481static bfd_boolean
5482cortex_a8_erratum_scan (bfd *input_bfd,
5483 struct bfd_link_info *info,
48229727
JB		 5484 struct a8_erratum_fix **a8_fixes_p,
5485 unsigned int *num_a8_fixes_p,
5486 unsigned int *a8_fix_table_size_p,
5487 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5488 unsigned int num_a8_relocs,
5489 unsigned prev_num_a8_fixes,
5490 bfd_boolean *stub_changed_p)
48229727
JB		 5491{
5492 asection *section;
5493 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5494 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5495 unsigned int num_a8_fixes = *num_a8_fixes_p;
5496 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5497
4dfe6ac6
NC		 5498 if (htab == NULL)
5499 return FALSE;
5500
48229727
JB		 5501 for (section = input_bfd->sections;
5502 section != NULL;
5503 section = section->next)
5504 {
5505 bfd_byte *contents = NULL;
5506 struct _arm_elf_section_data *sec_data;
5507 unsigned int span;
5508 bfd_vma base_vma;
5509
5510 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5511 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5512 || (section->flags & SEC_EXCLUDE) != 0
5513 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5514 || (section->output_section == bfd_abs_section_ptr))
5515 continue;
48229727
JB		 5516
5517 base_vma = section->output_section->vma + section->output_offset;
5518
5519 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5520 contents = elf_section_data (section)->this_hdr.contents;
48229727 5521 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5522 return TRUE;
48229727
JB		 5523
5524 sec_data = elf32_arm_section_data (section);
5525
5526 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5527 {
5528 unsigned int span_start = sec_data->map[span].vma;
5529 unsigned int span_end = (span == sec_data->mapcount - 1)
5530 ? section->size : sec_data->map[span + 1].vma;
5531 unsigned int i;
5532 char span_type = sec_data->map[span].type;
5533 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5534
5535 if (span_type != 't')
5536 continue;
5537
5538 /* Span is entirely within a single 4KB region: skip scanning. */
5539 if (((base_vma + span_start) & ~0xfff)
48229727 5540 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5541 continue;
5542
5543 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5544
5545 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5546 * The branch target is in the same 4KB region as the
5547 first half of the branch.
5548 * The instruction before the branch is a 32-bit
5549 length non-branch instruction. */
5550 for (i = span_start; i < span_end;)
5551 {
5552 unsigned int insn = bfd_getl16 (&contents[i]);
5553 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5554 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5555
99059e56
RM		 5556 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5557 insn_32bit = TRUE;
48229727
JB		 5558
5559 if (insn_32bit)
99059e56
RM		 5560 {
5561 /* Load the rest of the insn (in manual-friendly order). */
5562 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5563
5564 /* Encoding T4: B<c>.W. */
5565 is_b = (insn & 0xf800d000) == 0xf0009000;
5566 /* Encoding T1: BL<c>.W. */
5567 is_bl = (insn & 0xf800d000) == 0xf000d000;
5568 /* Encoding T2: BLX<c>.W. */
5569 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5570 /* Encoding T3: B<c>.W (not permitted in IT block). */
5571 is_bcc = (insn & 0xf800d000) == 0xf0008000
5572 && (insn & 0x07f00000) != 0x03800000;
5573 }
5574
5575 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5576
99059e56 5577 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5578 && insn_32bit
5579 && is_32bit_branch
5580 && last_was_32bit
5581 && ! last_was_branch)
99059e56
RM		 5582 {
5583 bfd_signed_vma offset = 0;
5584 bfd_boolean force_target_arm = FALSE;
48229727 5585 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5586 bfd_vma target;
5587 enum elf32_arm_stub_type stub_type = arm_stub_none;
5588 struct a8_erratum_reloc key, *found;
5589 bfd_boolean use_plt = FALSE;
48229727 5590
99059e56
RM		 5591 key.from = base_vma + i;
5592 found = (struct a8_erratum_reloc *)
5593 bsearch (&key, a8_relocs, num_a8_relocs,
5594 sizeof (struct a8_erratum_reloc),
5595 &a8_reloc_compare);
48229727
JB		 5596
5597 if (found)
5598 {
5599 char *error_message = NULL;
5600 struct elf_link_hash_entry *entry;
5601
5602 /* We don't care about the error returned from this
99059e56 5603 function, only if there is glue or not. */
48229727
JB		 5604 entry = find_thumb_glue (info, found->sym_name,
5605 &error_message);
5606
5607 if (entry)
5608 found->non_a8_stub = TRUE;
5609
92750f34 5610 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5611 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5612 && found->hash->root.plt.offset != (bfd_vma) -1)
5613 use_plt = TRUE;
5614
5615 if (found->r_type == R_ARM_THM_CALL)
5616 {
35fc36a8
RS		 5617 if (found->branch_type == ST_BRANCH_TO_ARM
5618 || use_plt)
92750f34
DJ		 5619 force_target_arm = TRUE;
5620 else
5621 force_target_thumb = TRUE;
5622 }
48229727
JB		 5623 }
5624
99059e56 5625 /* Check if we have an offending branch instruction. */
48229727
JB		 5626
5627 if (found && found->non_a8_stub)
5628 /* We've already made a stub for this instruction, e.g.
5629 it's a long branch or a Thumb->ARM stub. Assume that
5630 stub will suffice to work around the A8 erratum (see
5631 setting of always_after_branch above). */
5632 ;
99059e56
RM		 5633 else if (is_bcc)
5634 {
5635 offset = (insn & 0x7ff) << 1;
5636 offset |= (insn & 0x3f0000) >> 4;
5637 offset |= (insn & 0x2000) ? 0x40000 : 0;
5638 offset |= (insn & 0x800) ? 0x80000 : 0;
5639 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5640 if (offset & 0x100000)
5641 offset |= ~ ((bfd_signed_vma) 0xfffff);
5642 stub_type = arm_stub_a8_veneer_b_cond;
5643 }
5644 else if (is_b || is_bl || is_blx)
5645 {
5646 int s = (insn & 0x4000000) != 0;
5647 int j1 = (insn & 0x2000) != 0;
5648 int j2 = (insn & 0x800) != 0;
5649 int i1 = !(j1 ^ s);
5650 int i2 = !(j2 ^ s);
5651
5652 offset = (insn & 0x7ff) << 1;
5653 offset |= (insn & 0x3ff0000) >> 4;
5654 offset |= i2 << 22;
5655 offset |= i1 << 23;
5656 offset |= s << 24;
5657 if (offset & 0x1000000)
5658 offset |= ~ ((bfd_signed_vma) 0xffffff);
5659
5660 if (is_blx)
5661 offset &= ~ ((bfd_signed_vma) 3);
5662
5663 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5664 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5665 }
5666
5667 if (stub_type != arm_stub_none)
5668 {
5669 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5670
5671 /* The original instruction is a BL, but the target is
99059e56 5672 an ARM instruction. If we were not making a stub,
48229727
JB		 5673 the BL would have been converted to a BLX. Use the
5674 BLX stub instead in that case. */
5675 if (htab->use_blx && force_target_arm
5676 && stub_type == arm_stub_a8_veneer_bl)
5677 {
5678 stub_type = arm_stub_a8_veneer_blx;
5679 is_blx = TRUE;
5680 is_bl = FALSE;
5681 }
5682 /* Conversely, if the original instruction was
5683 BLX but the target is Thumb mode, use the BL
5684 stub. */
5685 else if (force_target_thumb
5686 && stub_type == arm_stub_a8_veneer_blx)
5687 {
5688 stub_type = arm_stub_a8_veneer_bl;
5689 is_blx = FALSE;
5690 is_bl = TRUE;
5691 }
5692
99059e56
RM		 5693 if (is_blx)
5694 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5695
99059e56
RM		 5696 /* If we found a relocation, use the proper destination,
5697 not the offset in the (unrelocated) instruction.
48229727
JB		 5698 Note this is always done if we switched the stub type
5699 above. */
99059e56
RM		 5700 if (found)
5701 offset =
81694485 5702 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5703
99059e56
RM		 5704 /* If the stub will use a Thumb-mode branch to a
5705 PLT target, redirect it to the preceding Thumb
5706 entry point. */
5707 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5708 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5709
99059e56 5710 target = pc_for_insn + offset;
48229727 5711
99059e56
RM		 5712 /* The BLX stub is ARM-mode code. Adjust the offset to
5713 take the different PC value (+8 instead of +4) into
48229727 5714 account. */
99059e56
RM		 5715 if (stub_type == arm_stub_a8_veneer_blx)
5716 offset += 4;
5717
5718 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5719 {
5720 char *stub_name = NULL;
5721
5722 if (num_a8_fixes == a8_fix_table_size)
5723 {
5724 a8_fix_table_size *= 2;
5725 a8_fixes = (struct a8_erratum_fix *)
5726 bfd_realloc (a8_fixes,
5727 sizeof (struct a8_erratum_fix)
5728 * a8_fix_table_size);
5729 }
48229727 5730
eb7c4339
NS		 5731 if (num_a8_fixes < prev_num_a8_fixes)
5732 {
5733 /* If we're doing a subsequent scan,
5734 check if we've found the same fix as
5735 before, and try and reuse the stub
5736 name. */
5737 stub_name = a8_fixes[num_a8_fixes].stub_name;
5738 if ((a8_fixes[num_a8_fixes].section != section)
5739 || (a8_fixes[num_a8_fixes].offset != i))
5740 {
5741 free (stub_name);
5742 stub_name = NULL;
5743 *stub_changed_p = TRUE;
5744 }
5745 }
5746
5747 if (!stub_name)
5748 {
21d799b5 5749 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5750 if (stub_name != NULL)
5751 sprintf (stub_name, "%x:%x", section->id, i);
5752 }
48229727 5753
99059e56
RM		 5754 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5755 a8_fixes[num_a8_fixes].section = section;
5756 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5757 a8_fixes[num_a8_fixes].target_offset =
5758 target - base_vma;
99059e56
RM		 5759 a8_fixes[num_a8_fixes].orig_insn = insn;
5760 a8_fixes[num_a8_fixes].stub_name = stub_name;
5761 a8_fixes[num_a8_fixes].stub_type = stub_type;
5762 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5763 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5764
99059e56
RM		 5765 num_a8_fixes++;
5766 }
5767 }
5768 }
48229727 5769
99059e56
RM		 5770 i += insn_32bit ? 4 : 2;
5771 last_was_32bit = insn_32bit;
48229727 5772 last_was_branch = is_32bit_branch;
99059e56
RM		 5773 }
5774 }
48229727
JB		 5775
5776 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5777 free (contents);
48229727 5778 }
fe33d2fa 5779
48229727
JB		 5780 *a8_fixes_p = a8_fixes;
5781 *num_a8_fixes_p = num_a8_fixes;
5782 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5783
81694485 5784 return FALSE;
48229727
JB		 5785}
5786
b715f643
TP		 5787/* Create or update a stub entry depending on whether the stub can already be
5788 found in HTAB. The stub is identified by:
5789 - its type STUB_TYPE
5790 - its source branch (note that several can share the same stub) whose
5791 section and relocation (if any) are given by SECTION and IRELA
5792 respectively
5793 - its target symbol whose input section, hash, name, value and branch type
5794 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5795 respectively
5796
5797 If found, the value of the stub's target symbol is updated from SYM_VALUE
5798 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5799 TRUE and the stub entry is initialized.
5800
0955507f
TP		 5801 Returns the stub that was created or updated, or NULL if an error
5802 occurred. */
b715f643 5803
0955507f 5804static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5805elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5806 enum elf32_arm_stub_type stub_type, asection *section,
5807 Elf_Internal_Rela *irela, asection *sym_sec,
5808 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5809 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5810 bfd_boolean *new_stub)
5811{
5812 const asection *id_sec;
5813 char *stub_name;
5814 struct elf32_arm_stub_hash_entry *stub_entry;
5815 unsigned int r_type;
4f4faa4d 5816 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5817
5818 BFD_ASSERT (stub_type != arm_stub_none);
5819 *new_stub = FALSE;
5820
4f4faa4d
TP		 5821 if (sym_claimed)
5822 stub_name = sym_name;
5823 else
5824 {
5825 BFD_ASSERT (irela);
5826 BFD_ASSERT (section);
c2abbbeb 5827 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5828
4f4faa4d
TP		 5829 /* Support for grouping stub sections. */
5830 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5831
4f4faa4d
TP		 5832 /* Get the name of this stub. */
5833 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5834 stub_type);
5835 if (!stub_name)
0955507f 5836 return NULL;
4f4faa4d 5837 }
b715f643
TP		 5838
5839 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5840 FALSE);
5841 /* The proper stub has already been created, just update its value. */
5842 if (stub_entry != NULL)
5843 {
4f4faa4d
TP		 5844 if (!sym_claimed)
5845 free (stub_name);
b715f643 5846 stub_entry->target_value = sym_value;
0955507f 5847 return stub_entry;
b715f643
TP		 5848 }
5849
daa4adae 5850 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5851 if (stub_entry == NULL)
5852 {
4f4faa4d
TP		 5853 if (!sym_claimed)
5854 free (stub_name);
0955507f 5855 return NULL;
b715f643
TP		 5856 }
5857
5858 stub_entry->target_value = sym_value;
5859 stub_entry->target_section = sym_sec;
5860 stub_entry->stub_type = stub_type;
5861 stub_entry->h = hash;
5862 stub_entry->branch_type = branch_type;
5863
4f4faa4d
TP		 5864 if (sym_claimed)
5865 stub_entry->output_name = sym_name;
5866 else
b715f643 5867 {
4f4faa4d
TP		 5868 if (sym_name == NULL)
5869 sym_name = "unnamed";
5870 stub_entry->output_name = (char *)
5871 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5872 + strlen (sym_name));
5873 if (stub_entry->output_name == NULL)
5874 {
5875 free (stub_name);
0955507f 5876 return NULL;
4f4faa4d 5877 }
b715f643 5878
4f4faa4d
TP		 5879 /* For historical reasons, use the existing names for ARM-to-Thumb and
5880 Thumb-to-ARM stubs. */
5881 r_type = ELF32_R_TYPE (irela->r_info);
5882 if ((r_type == (unsigned int) R_ARM_THM_CALL
5883 || r_type == (unsigned int) R_ARM_THM_JUMP24
5884 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5885 && branch_type == ST_BRANCH_TO_ARM)
5886 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5887 else if ((r_type == (unsigned int) R_ARM_CALL
5888 || r_type == (unsigned int) R_ARM_JUMP24)
5889 && branch_type == ST_BRANCH_TO_THUMB)
5890 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5891 else
5892 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5893 }
b715f643
TP		 5894
5895 *new_stub = TRUE;
0955507f 5896 return stub_entry;
b715f643
TP		 5897}
5898
4ba2ef8f
TP		 5899/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5900 gateway veneer to transition from non secure to secure state and create them
5901 accordingly.
5902
5903 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5904 defines the conditions that govern Secure Gateway veneer creation for a
5905 given symbol <SYM> as follows:
5906 - it has function type
5907 - it has non local binding
5908 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5909 same type, binding and value as <SYM> (called normal symbol).
5910 An entry function can handle secure state transition itself in which case
5911 its special symbol would have a different value from the normal symbol.
5912
5913 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5914 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5915 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5916 created.
4ba2ef8f 5917
0955507f 5918 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5919
5920static bfd_boolean
5921cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5922 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5923 int *cmse_stub_created)
4ba2ef8f
TP		 5924{
5925 const struct elf_backend_data *bed;
5926 Elf_Internal_Shdr *symtab_hdr;
5927 unsigned i, j, sym_count, ext_start;
5928 Elf_Internal_Sym *cmse_sym, *local_syms;
5929 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5930 enum arm_st_branch_type branch_type;
5931 char *sym_name, *lsym_name;
5932 bfd_vma sym_value;
5933 asection *section;
0955507f
TP		 5934 struct elf32_arm_stub_hash_entry *stub_entry;
5935 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5936
5937 bed = get_elf_backend_data (input_bfd);
5938 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5939 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5940 ext_start = symtab_hdr->sh_info;
5941 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5942 && out_attr[Tag_CPU_arch_profile].i == 'M');
5943
5944 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5945 if (local_syms == NULL)
5946 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5947 symtab_hdr->sh_info, 0, NULL, NULL,
5948 NULL);
5949 if (symtab_hdr->sh_info && local_syms == NULL)
5950 return FALSE;
5951
5952 /* Scan symbols. */
5953 for (i = 0; i < sym_count; i++)
5954 {
5955 cmse_invalid = FALSE;
5956
5957 if (i < ext_start)
5958 {
5959 cmse_sym = &local_syms[i];
4ba2ef8f
TP		 5960 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5961 symtab_hdr->sh_link,
5962 cmse_sym->st_name);
baf46cd7
AM		 5963 if (!sym_name || !CONST_STRNEQ (sym_name, CMSE_PREFIX))
5964 continue;
5965
4ba2ef8f
TP		 5966 /* Special symbol with local binding. */
5967 cmse_invalid = TRUE;
5968 }
5969 else
5970 {
5971 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5972 sym_name = (char *) cmse_hash->root.root.root.string;
baf46cd7 5973 if (!CONST_STRNEQ (sym_name, CMSE_PREFIX))
4ba2ef8f
TP		 5974 continue;
5975
5976 /* Special symbol has incorrect binding or type. */
5977 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5978 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5979 || cmse_hash->root.type != STT_FUNC)
5980 cmse_invalid = TRUE;
5981 }
5982
5983 if (!is_v8m)
5984 {
90b6238f
AM		 5985 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
5986 "ARMv8-M architecture or later"),
4eca0228 5987 input_bfd, sym_name);
4ba2ef8f
TP		 5988 is_v8m = TRUE; /* Avoid multiple warning. */
5989 ret = FALSE;
5990 }
5991
5992 if (cmse_invalid)
5993 {
90b6238f
AM		 5994 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
5995 " a global or weak function symbol"),
4eca0228 5996 input_bfd, sym_name);
4ba2ef8f
TP		 5997 ret = FALSE;
5998 if (i < ext_start)
5999 continue;
6000 }
6001
6002 sym_name += strlen (CMSE_PREFIX);
6003 hash = (struct elf32_arm_link_hash_entry *)
6004 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6005
6006 /* No associated normal symbol or it is neither global nor weak. */
6007 if (!hash
6008 || (hash->root.root.type != bfd_link_hash_defined
6009 && hash->root.root.type != bfd_link_hash_defweak)
6010 || hash->root.type != STT_FUNC)
6011 {
6012 /* Initialize here to avoid warning about use of possibly
6013 uninitialized variable. */
6014 j = 0;
6015
6016 if (!hash)
6017 {
6018 /* Searching for a normal symbol with local binding. */
6019 for (; j < ext_start; j++)
6020 {
6021 lsym_name =
6022 bfd_elf_string_from_elf_section (input_bfd,
6023 symtab_hdr->sh_link,
6024 local_syms[j].st_name);
6025 if (!strcmp (sym_name, lsym_name))
6026 break;
6027 }
6028 }
6029
6030 if (hash || j < ext_start)
6031 {
4eca0228 6032 _bfd_error_handler
90b6238f
AM		 6033 (_("%pB: invalid standard symbol `%s'; it must be "
6034 "a global or weak function symbol"),
6035 input_bfd, sym_name);
4ba2ef8f
TP		 6036 }
6037 else
4eca0228 6038 _bfd_error_handler
90b6238f 6039 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 6040 ret = FALSE;
6041 if (!hash)
6042 continue;
6043 }
6044
6045 sym_value = hash->root.root.u.def.value;
6046 section = hash->root.root.u.def.section;
6047
6048 if (cmse_hash->root.root.u.def.section != section)
6049 {
4eca0228 6050 _bfd_error_handler
90b6238f 6051 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 6052 input_bfd, sym_name);
6053 ret = FALSE;
6054 }
6055 if (cmse_hash->root.root.u.def.value != sym_value)
6056 continue; /* Ignore: could be an entry function starting with SG. */
6057
6058 /* If this section is a link-once section that will be discarded, then
6059 don't create any stubs. */
6060 if (section->output_section == NULL)
6061 {
4eca0228 6062 _bfd_error_handler
90b6238f 6063 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 6064 continue;
6065 }
6066
6067 if (hash->root.size == 0)
6068 {
4eca0228 6069 _bfd_error_handler
90b6238f 6070 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 6071 ret = FALSE;
6072 }
6073
6074 if (!ret)
6075 continue;
6076 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 6077 stub_entry
4ba2ef8f
TP		 6078 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6079 NULL, NULL, section, hash, sym_name,
6080 sym_value, branch_type, &new_stub);
6081
0955507f 6082 if (stub_entry == NULL)
4ba2ef8f
TP		 6083 ret = FALSE;
6084 else
6085 {
6086 BFD_ASSERT (new_stub);
0955507f 6087 (*cmse_stub_created)++;
4ba2ef8f
TP		 6088 }
6089 }
6090
6091 if (!symtab_hdr->contents)
6092 free (local_syms);
6093 return ret;
6094}
6095
0955507f
TP		 6096/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6097 code entry function, ie can be called from non secure code without using a
6098 veneer. */
6099
6100static bfd_boolean
6101cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6102{
42484486 6103 bfd_byte contents[4];
0955507f
TP		 6104 uint32_t first_insn;
6105 asection *section;
6106 file_ptr offset;
6107 bfd *abfd;
6108
6109 /* Defined symbol of function type. */
6110 if (hash->root.root.type != bfd_link_hash_defined
6111 && hash->root.root.type != bfd_link_hash_defweak)
6112 return FALSE;
6113 if (hash->root.type != STT_FUNC)
6114 return FALSE;
6115
6116 /* Read first instruction. */
6117 section = hash->root.root.u.def.section;
6118 abfd = section->owner;
6119 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 6120 if (!bfd_get_section_contents (abfd, section, contents, offset,
6121 sizeof (contents)))
0955507f
TP		 6122 return FALSE;
6123
42484486
TP		 6124 first_insn = bfd_get_32 (abfd, contents);
6125
6126 /* Starts by SG instruction. */
0955507f
TP		 6127 return first_insn == 0xe97fe97f;
6128}
6129
6130/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6131 secure gateway veneers (ie. the veneers was not in the input import library)
6132 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6133
6134static bfd_boolean
6135arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6136{
6137 struct elf32_arm_stub_hash_entry *stub_entry;
6138 struct bfd_link_info *info;
6139
6140 /* Massage our args to the form they really have. */
6141 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6142 info = (struct bfd_link_info *) gen_info;
6143
6144 if (info->out_implib_bfd)
6145 return TRUE;
6146
6147 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6148 return TRUE;
6149
6150 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 6151 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 6152
6153 return TRUE;
6154}
6155
6156/* Set offset of each secure gateway veneers so that its address remain
6157 identical to the one in the input import library referred by
6158 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6159 (present in input import library but absent from the executable being
6160 linked) or if new veneers appeared and there is no output import library
6161 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6162 number of secure gateway veneers found in the input import library.
6163
6164 The function returns whether an error occurred. If no error occurred,
6165 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6166 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6167 veneer observed set for new veneers to be layed out after. */
6168
6169static bfd_boolean
6170set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6171 struct elf32_arm_link_hash_table *htab,
6172 int *cmse_stub_created)
6173{
6174 long symsize;
6175 char *sym_name;
6176 flagword flags;
6177 long i, symcount;
6178 bfd *in_implib_bfd;
6179 asection *stub_out_sec;
6180 bfd_boolean ret = TRUE;
6181 Elf_Internal_Sym *intsym;
6182 const char *out_sec_name;
6183 bfd_size_type cmse_stub_size;
6184 asymbol **sympp = NULL, *sym;
6185 struct elf32_arm_link_hash_entry *hash;
6186 const insn_sequence *cmse_stub_template;
6187 struct elf32_arm_stub_hash_entry *stub_entry;
6188 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6189 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6190 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6191
6192 /* No input secure gateway import library. */
6193 if (!htab->in_implib_bfd)
6194 return TRUE;
6195
6196 in_implib_bfd = htab->in_implib_bfd;
6197 if (!htab->cmse_implib)
6198 {
871b3ab2 6199 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 6200 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 6201 return FALSE;
6202 }
6203
6204 /* Get symbol table size. */
6205 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6206 if (symsize < 0)
6207 return FALSE;
6208
6209 /* Read in the input secure gateway import library's symbol table. */
9a733151
AM		 6210 sympp = (asymbol **) bfd_malloc (symsize);
6211 if (sympp == NULL)
6212 return FALSE;
6213
0955507f
TP		 6214 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6215 if (symcount < 0)
6216 {
6217 ret = FALSE;
6218 goto free_sym_buf;
6219 }
6220
6221 htab->new_cmse_stub_offset = 0;
6222 cmse_stub_size =
6223 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6224 &cmse_stub_template,
6225 &cmse_stub_template_size);
6226 out_sec_name =
6227 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6228 stub_out_sec =
6229 bfd_get_section_by_name (htab->obfd, out_sec_name);
6230 if (stub_out_sec != NULL)
6231 cmse_stub_sec_vma = stub_out_sec->vma;
6232
6233 /* Set addresses of veneers mentionned in input secure gateway import
6234 library's symbol table. */
6235 for (i = 0; i < symcount; i++)
6236 {
6237 sym = sympp[i];
6238 flags = sym->flags;
6239 sym_name = (char *) bfd_asymbol_name (sym);
6240 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6241
6242 if (sym->section != bfd_abs_section_ptr
6243 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6244 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6245 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6246 != ST_BRANCH_TO_THUMB))
6247 {
90b6238f
AM		 6248 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6249 "symbol should be absolute, global and "
6250 "refer to Thumb functions"),
4eca0228 6251 in_implib_bfd, sym_name);
0955507f
TP		 6252 ret = FALSE;
6253 continue;
6254 }
6255
6256 veneer_value = bfd_asymbol_value (sym);
6257 stub_offset = veneer_value - cmse_stub_sec_vma;
6258 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6259 FALSE, FALSE);
6260 hash = (struct elf32_arm_link_hash_entry *)
6261 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6262
6263 /* Stub entry should have been created by cmse_scan or the symbol be of
6264 a secure function callable from non secure code. */
6265 if (!stub_entry && !hash)
6266 {
6267 bfd_boolean new_stub;
6268
4eca0228 6269 _bfd_error_handler
90b6238f 6270 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6271 hash = (struct elf32_arm_link_hash_entry *)
6272 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6273 stub_entry
6274 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6275 NULL, NULL, bfd_abs_section_ptr, hash,
6276 sym_name, veneer_value,
6277 ST_BRANCH_TO_THUMB, &new_stub);
6278 if (stub_entry == NULL)
6279 ret = FALSE;
6280 else
6281 {
6282 BFD_ASSERT (new_stub);
6283 new_cmse_stubs_created++;
6284 (*cmse_stub_created)++;
6285 }
6286 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6287 stub_entry->stub_offset = stub_offset;
6288 }
6289 /* Symbol found is not callable from non secure code. */
6290 else if (!stub_entry)
6291 {
6292 if (!cmse_entry_fct_p (hash))
6293 {
90b6238f 6294 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6295 sym_name);
0955507f
TP		 6296 ret = FALSE;
6297 }
6298 continue;
6299 }
6300 else
6301 {
6302 /* Only stubs for SG veneers should have been created. */
6303 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6304
6305 /* Check visibility hasn't changed. */
6306 if (!!(flags & BSF_GLOBAL)
6307 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6308 _bfd_error_handler
90b6238f 6309 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6310 sym_name);
6311
6312 stub_entry->stub_offset = stub_offset;
6313 }
6314
6315 /* Size should match that of a SG veneer. */
6316 if (intsym->st_size != cmse_stub_size)
6317 {
90b6238f 6318 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6319 in_implib_bfd, sym_name);
0955507f
TP		 6320 ret = FALSE;
6321 }
6322
6323 /* Previous veneer address is before current SG veneer section. */
6324 if (veneer_value < cmse_stub_sec_vma)
6325 {
6326 /* Avoid offset underflow. */
6327 if (stub_entry)
6328 stub_entry->stub_offset = 0;
6329 stub_offset = 0;
6330 ret = FALSE;
6331 }
6332
6333 /* Complain if stub offset not a multiple of stub size. */
6334 if (stub_offset % cmse_stub_size)
6335 {
4eca0228 6336 _bfd_error_handler
90b6238f
AM		 6337 (_("offset of veneer for entry function `%s' not a multiple of "
6338 "its size"), sym_name);
0955507f
TP		 6339 ret = FALSE;
6340 }
6341
6342 if (!ret)
6343 continue;
6344
6345 new_cmse_stubs_created--;
6346 if (veneer_value < cmse_stub_array_start)
6347 cmse_stub_array_start = veneer_value;
6348 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6349 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6350 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6351 }
6352
6353 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6354 {
6355 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6356 _bfd_error_handler
0955507f
TP		 6357 (_("new entry function(s) introduced but no output import library "
6358 "specified:"));
6359 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6360 }
6361
6362 if (cmse_stub_array_start != cmse_stub_sec_vma)
6363 {
4eca0228 6364 _bfd_error_handler
90b6238f 6365 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6366 out_sec_name);
6367 ret = FALSE;
6368 }
6369
dc1e8a47 6370 free_sym_buf:
0955507f
TP		 6371 free (sympp);
6372 return ret;
6373}
6374
906e58ca
NC		 6375/* Determine and set the size of the stub section for a final link.
6376
6377 The basic idea here is to examine all the relocations looking for
6378 PC-relative calls to a target that is unreachable with a "bl"
6379 instruction. */
6380
6381bfd_boolean
6382elf32_arm_size_stubs (bfd *output_bfd,
6383 bfd *stub_bfd,
6384 struct bfd_link_info *info,
6385 bfd_signed_vma group_size,
7a89b94e 6386 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6387 asection *,
7a89b94e 6388 unsigned int),
906e58ca
NC		 6389 void (*layout_sections_again) (void))
6390{
0955507f 6391 bfd_boolean ret = TRUE;
4ba2ef8f 6392 obj_attribute *out_attr;
0955507f 6393 int cmse_stub_created = 0;
906e58ca 6394 bfd_size_type stub_group_size;
4ba2ef8f 6395 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6396 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6397 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6398 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6399 struct a8_erratum_reloc *a8_relocs = NULL;
6400 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6401
4dfe6ac6
NC		 6402 if (htab == NULL)
6403 return FALSE;
6404
48229727
JB		 6405 if (htab->fix_cortex_a8)
6406 {
21d799b5 6407 a8_fixes = (struct a8_erratum_fix *)
99059e56 6408 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6409 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6410 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6411 }
906e58ca
NC		 6412
6413 /* Propagate mach to stub bfd, because it may not have been
6414 finalized when we created stub_bfd. */
6415 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6416 bfd_get_mach (output_bfd));
6417
6418 /* Stash our params away. */
6419 htab->stub_bfd = stub_bfd;
6420 htab->add_stub_section = add_stub_section;
6421 htab->layout_sections_again = layout_sections_again;
07d72278 6422 stubs_always_after_branch = group_size < 0;
48229727 6423
4ba2ef8f
TP		 6424 out_attr = elf_known_obj_attributes_proc (output_bfd);
6425 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6426
48229727
JB		 6427 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6428 as the first half of a 32-bit branch straddling two 4K pages. This is a
6429 crude way of enforcing that. */
6430 if (htab->fix_cortex_a8)
6431 stubs_always_after_branch = 1;
6432
906e58ca
NC		 6433 if (group_size < 0)
6434 stub_group_size = -group_size;
6435 else
6436 stub_group_size = group_size;
6437
6438 if (stub_group_size == 1)
6439 {
6440 /* Default values. */
6441 /* Thumb branch range is +-4MB has to be used as the default
6442 maximum size (a given section can contain both ARM and Thumb
6443 code, so the worst case has to be taken into account).
6444
6445 This value is 24K less than that, which allows for 2025
6446 12-byte stubs. If we exceed that, then we will fail to link.
6447 The user will have to relink with an explicit group size
6448 option. */
6449 stub_group_size = 4170000;
6450 }
6451
07d72278 6452 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6453
3ae046cc
NS		 6454 /* If we're applying the cortex A8 fix, we need to determine the
6455 program header size now, because we cannot change it later --
6456 that could alter section placements. Notice the A8 erratum fix
6457 ends up requiring the section addresses to remain unchanged
6458 modulo the page size. That's something we cannot represent
6459 inside BFD, and we don't want to force the section alignment to
6460 be the page size. */
6461 if (htab->fix_cortex_a8)
6462 (*htab->layout_sections_again) ();
6463
906e58ca
NC		 6464 while (1)
6465 {
6466 bfd *input_bfd;
6467 unsigned int bfd_indx;
6468 asection *stub_sec;
d7c5bd02 6469 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6470 bfd_boolean stub_changed = FALSE;
6471 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6472
48229727 6473 num_a8_fixes = 0;
906e58ca
NC		 6474 for (input_bfd = info->input_bfds, bfd_indx = 0;
6475 input_bfd != NULL;
c72f2fb2 6476 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6477 {
6478 Elf_Internal_Shdr *symtab_hdr;
6479 asection *section;
6480 Elf_Internal_Sym *local_syms = NULL;
6481
73d5efd7
AM		 6482 if (!is_arm_elf (input_bfd))
6483 continue;
6484 if ((input_bfd->flags & DYNAMIC) != 0
6485 && (elf_sym_hashes (input_bfd) == NULL
6486 || (elf_dyn_lib_class (input_bfd) & DYN_AS_NEEDED) != 0))
99059e56 6487 continue;
adbcc655 6488
48229727
JB		 6489 num_a8_relocs = 0;
6490
906e58ca
NC		 6491 /* We'll need the symbol table in a second. */
6492 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6493 if (symtab_hdr->sh_info == 0)
6494 continue;
6495
4ba2ef8f
TP		 6496 /* Limit scan of symbols to object file whose profile is
6497 Microcontroller to not hinder performance in the general case. */
6498 if (m_profile && first_veneer_scan)
6499 {
6500 struct elf_link_hash_entry **sym_hashes;
6501
6502 sym_hashes = elf_sym_hashes (input_bfd);
6503 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6504 &cmse_stub_created))
4ba2ef8f 6505 goto error_ret_free_local;
0955507f
TP		 6506
6507 if (cmse_stub_created != 0)
6508 stub_changed = TRUE;
4ba2ef8f
TP		 6509 }
6510
906e58ca
NC		 6511 /* Walk over each section attached to the input bfd. */
6512 for (section = input_bfd->sections;
6513 section != NULL;
6514 section = section->next)
6515 {
6516 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6517
6518 /* If there aren't any relocs, then there's nothing more
6519 to do. */
6520 if ((section->flags & SEC_RELOC) == 0
6521 || section->reloc_count == 0
6522 || (section->flags & SEC_CODE) == 0)
6523 continue;
6524
6525 /* If this section is a link-once section that will be
6526 discarded, then don't create any stubs. */
6527 if (section->output_section == NULL
6528 || section->output_section->owner != output_bfd)
6529 continue;
6530
6531 /* Get the relocs. */
6532 internal_relocs
6533 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6534 NULL, info->keep_memory);
6535 if (internal_relocs == NULL)
6536 goto error_ret_free_local;
6537
6538 /* Now examine each relocation. */
6539 irela = internal_relocs;
6540 irelaend = irela + section->reloc_count;
6541 for (; irela < irelaend; irela++)
6542 {
6543 unsigned int r_type, r_indx;
906e58ca
NC		 6544 asection *sym_sec;
6545 bfd_vma sym_value;
6546 bfd_vma destination;
6547 struct elf32_arm_link_hash_entry *hash;
7413f23f 6548 const char *sym_name;
34e77a92 6549 unsigned char st_type;
35fc36a8 6550 enum arm_st_branch_type branch_type;
48229727 6551 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6552
6553 r_type = ELF32_R_TYPE (irela->r_info);
6554 r_indx = ELF32_R_SYM (irela->r_info);
6555
6556 if (r_type >= (unsigned int) R_ARM_max)
6557 {
6558 bfd_set_error (bfd_error_bad_value);
6559 error_ret_free_internal:
6560 if (elf_section_data (section)->relocs == NULL)
6561 free (internal_relocs);
15dd01b1
TP		 6562 /* Fall through. */
6563 error_ret_free_local:
c9594989 6564 if (symtab_hdr->contents != (unsigned char *) local_syms)
15dd01b1
TP		 6565 free (local_syms);
6566 return FALSE;
906e58ca 6567 }
b38cadfb 6568
0855e32b
NS		 6569 hash = NULL;
6570 if (r_indx >= symtab_hdr->sh_info)
6571 hash = elf32_arm_hash_entry
6572 (elf_sym_hashes (input_bfd)
6573 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6574
0855e32b
NS		 6575 /* Only look for stubs on branch instructions, or
6576 non-relaxed TLSCALL */
906e58ca 6577 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6578 && (r_type != (unsigned int) R_ARM_THM_CALL)
6579 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6580 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6581 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6582 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6583 && (r_type != (unsigned int) R_ARM_PLT32)
6584 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6585 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6586 && r_type == elf32_arm_tls_transition
6587 (info, r_type, &hash->root)
6588 && ((hash ? hash->tls_type
6589 : (elf32_arm_local_got_tls_type
6590 (input_bfd)[r_indx]))
6591 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6592 continue;
6593
6594 /* Now determine the call target, its name, value,
6595 section. */
6596 sym_sec = NULL;
6597 sym_value = 0;
6598 destination = 0;
7413f23f 6599 sym_name = NULL;
b38cadfb 6600
0855e32b
NS		 6601 if (r_type == (unsigned int) R_ARM_TLS_CALL
6602 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6603 {
6604 /* A non-relaxed TLS call. The target is the
6605 plt-resident trampoline and nothing to do
6606 with the symbol. */
6607 BFD_ASSERT (htab->tls_trampoline > 0);
6608 sym_sec = htab->root.splt;
6609 sym_value = htab->tls_trampoline;
6610 hash = 0;
34e77a92 6611 st_type = STT_FUNC;
35fc36a8 6612 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6613 }
6614 else if (!hash)
906e58ca
NC		 6615 {
6616 /* It's a local symbol. */
6617 Elf_Internal_Sym *sym;
906e58ca
NC		 6618
6619 if (local_syms == NULL)
6620 {
6621 local_syms
6622 = (Elf_Internal_Sym *) symtab_hdr->contents;
6623 if (local_syms == NULL)
6624 local_syms
6625 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6626 symtab_hdr->sh_info, 0,
6627 NULL, NULL, NULL);
6628 if (local_syms == NULL)
6629 goto error_ret_free_internal;
6630 }
6631
6632 sym = local_syms + r_indx;
f6d250ce
TS		 6633 if (sym->st_shndx == SHN_UNDEF)
6634 sym_sec = bfd_und_section_ptr;
6635 else if (sym->st_shndx == SHN_ABS)
6636 sym_sec = bfd_abs_section_ptr;
6637 else if (sym->st_shndx == SHN_COMMON)
6638 sym_sec = bfd_com_section_ptr;
6639 else
6640 sym_sec =
6641 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6642
ffcb4889
NS		 6643 if (!sym_sec)
6644 /* This is an undefined symbol. It can never
6a631e86 6645 be resolved. */
ffcb4889 6646 continue;
fe33d2fa 6647
906e58ca
NC		 6648 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6649 sym_value = sym->st_value;
6650 destination = (sym_value + irela->r_addend
6651 + sym_sec->output_offset
6652 + sym_sec->output_section->vma);
34e77a92 6653 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6654 branch_type =
6655 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6656 sym_name
6657 = bfd_elf_string_from_elf_section (input_bfd,
6658 symtab_hdr->sh_link,
6659 sym->st_name);
906e58ca
NC		 6660 }
6661 else
6662 {
6663 /* It's an external symbol. */
906e58ca
NC		 6664 while (hash->root.root.type == bfd_link_hash_indirect
6665 || hash->root.root.type == bfd_link_hash_warning)
6666 hash = ((struct elf32_arm_link_hash_entry *)
6667 hash->root.root.u.i.link);
6668
6669 if (hash->root.root.type == bfd_link_hash_defined
6670 || hash->root.root.type == bfd_link_hash_defweak)
6671 {
6672 sym_sec = hash->root.root.u.def.section;
6673 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6674
6675 struct elf32_arm_link_hash_table *globals =
6676 elf32_arm_hash_table (info);
6677
6678 /* For a destination in a shared library,
6679 use the PLT stub as target address to
6680 decide whether a branch stub is
6681 needed. */
4dfe6ac6 6682 if (globals != NULL
362d30a1 6683 && globals->root.splt != NULL
4dfe6ac6 6684 && hash != NULL
022f8312
CL		 6685 && hash->root.plt.offset != (bfd_vma) -1)
6686 {
362d30a1 6687 sym_sec = globals->root.splt;
022f8312
CL		 6688 sym_value = hash->root.plt.offset;
6689 if (sym_sec->output_section != NULL)
6690 destination = (sym_value
6691 + sym_sec->output_offset
6692 + sym_sec->output_section->vma);
6693 }
6694 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6695 destination = (sym_value + irela->r_addend
6696 + sym_sec->output_offset
6697 + sym_sec->output_section->vma);
6698 }
69c5861e
CL		 6699 else if ((hash->root.root.type == bfd_link_hash_undefined)
6700 || (hash->root.root.type == bfd_link_hash_undefweak))
6701 {
6702 /* For a shared library, use the PLT stub as
6703 target address to decide whether a long
6704 branch stub is needed.
6705 For absolute code, they cannot be handled. */
6706 struct elf32_arm_link_hash_table *globals =
6707 elf32_arm_hash_table (info);
6708
4dfe6ac6 6709 if (globals != NULL
362d30a1 6710 && globals->root.splt != NULL
4dfe6ac6 6711 && hash != NULL
69c5861e
CL		 6712 && hash->root.plt.offset != (bfd_vma) -1)
6713 {
362d30a1 6714 sym_sec = globals->root.splt;
69c5861e
CL		 6715 sym_value = hash->root.plt.offset;
6716 if (sym_sec->output_section != NULL)
6717 destination = (sym_value
6718 + sym_sec->output_offset
6719 + sym_sec->output_section->vma);
6720 }
6721 else
6722 continue;
6723 }
906e58ca
NC		 6724 else
6725 {
6726 bfd_set_error (bfd_error_bad_value);
6727 goto error_ret_free_internal;
6728 }
34e77a92 6729 st_type = hash->root.type;
39d911fc
TP		 6730 branch_type =
6731 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6732 sym_name = hash->root.root.root.string;
906e58ca
NC		 6733 }
6734
48229727 6735 do
7413f23f 6736 {
b715f643 6737 bfd_boolean new_stub;
0955507f 6738 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6739
48229727
JB		 6740 /* Determine what (if any) linker stub is needed. */
6741 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6742 st_type, &branch_type,
6743 hash, destination, sym_sec,
48229727
JB		 6744 input_bfd, sym_name);
6745 if (stub_type == arm_stub_none)
6746 break;
6747
48229727
JB		 6748 /* We've either created a stub for this reloc already,
6749 or we are about to. */
0955507f 6750 stub_entry =
b715f643
TP		 6751 elf32_arm_create_stub (htab, stub_type, section, irela,
6752 sym_sec, hash,
6753 (char *) sym_name, sym_value,
6754 branch_type, &new_stub);
7413f23f 6755
0955507f 6756 created_stub = stub_entry != NULL;
b715f643
TP		 6757 if (!created_stub)
6758 goto error_ret_free_internal;
6759 else if (!new_stub)
6760 break;
99059e56 6761 else
b715f643 6762 stub_changed = TRUE;
99059e56
RM		 6763 }
6764 while (0);
6765
6766 /* Look for relocations which might trigger Cortex-A8
6767 erratum. */
6768 if (htab->fix_cortex_a8
6769 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6770 || r_type == (unsigned int) R_ARM_THM_JUMP19
6771 || r_type == (unsigned int) R_ARM_THM_CALL
6772 || r_type == (unsigned int) R_ARM_THM_XPC22))
6773 {
6774 bfd_vma from = section->output_section->vma
6775 + section->output_offset
6776 + irela->r_offset;
6777
6778 if ((from & 0xfff) == 0xffe)
6779 {
6780 /* Found a candidate. Note we haven't checked the
6781 destination is within 4K here: if we do so (and
6782 don't create an entry in a8_relocs) we can't tell
6783 that a branch should have been relocated when
6784 scanning later. */
6785 if (num_a8_relocs == a8_reloc_table_size)
6786 {
6787 a8_reloc_table_size *= 2;
6788 a8_relocs = (struct a8_erratum_reloc *)
6789 bfd_realloc (a8_relocs,
6790 sizeof (struct a8_erratum_reloc)
6791 * a8_reloc_table_size);
6792 }
6793
6794 a8_relocs[num_a8_relocs].from = from;
6795 a8_relocs[num_a8_relocs].destination = destination;
6796 a8_relocs[num_a8_relocs].r_type = r_type;
6797 a8_relocs[num_a8_relocs].branch_type = branch_type;
6798 a8_relocs[num_a8_relocs].sym_name = sym_name;
6799 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6800 a8_relocs[num_a8_relocs].hash = hash;
6801
6802 num_a8_relocs++;
6803 }
6804 }
906e58ca
NC		 6805 }
6806
99059e56
RM		 6807 /* We're done with the internal relocs, free them. */
6808 if (elf_section_data (section)->relocs == NULL)
6809 free (internal_relocs);
6810 }
48229727 6811
99059e56 6812 if (htab->fix_cortex_a8)
48229727 6813 {
99059e56
RM		 6814 /* Sort relocs which might apply to Cortex-A8 erratum. */
6815 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6816 sizeof (struct a8_erratum_reloc),
99059e56 6817 &a8_reloc_compare);
48229727 6818
99059e56
RM		 6819 /* Scan for branches which might trigger Cortex-A8 erratum. */
6820 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6821 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6822 a8_relocs, num_a8_relocs,
6823 prev_num_a8_fixes, &stub_changed)
6824 != 0)
48229727 6825 goto error_ret_free_local;
5e681ec4 6826 }
7f991970
AM		 6827
6828 if (local_syms != NULL
6829 && symtab_hdr->contents != (unsigned char *) local_syms)
6830 {
6831 if (!info->keep_memory)
6832 free (local_syms);
6833 else
6834 symtab_hdr->contents = (unsigned char *) local_syms;
6835 }
5e681ec4
PB		 6836 }
6837
0955507f
TP		 6838 if (first_veneer_scan
6839 && !set_cmse_veneer_addr_from_implib (info, htab,
6840 &cmse_stub_created))
6841 ret = FALSE;
6842
eb7c4339 6843 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6844 stub_changed = TRUE;
48229727 6845
906e58ca
NC		 6846 if (!stub_changed)
6847 break;
5e681ec4 6848
906e58ca
NC		 6849 /* OK, we've added some stubs. Find out the new size of the
6850 stub sections. */
6851 for (stub_sec = htab->stub_bfd->sections;
6852 stub_sec != NULL;
6853 stub_sec = stub_sec->next)
3e6b1042
DJ		 6854 {
6855 /* Ignore non-stub sections. */
6856 if (!strstr (stub_sec->name, STUB_SUFFIX))
6857 continue;
6858
6859 stub_sec->size = 0;
6860 }
b34b2d70 6861
0955507f
TP		 6862 /* Add new SG veneers after those already in the input import
6863 library. */
6864 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6865 stub_type++)
6866 {
6867 bfd_vma *start_offset_p;
6868 asection **stub_sec_p;
6869
6870 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6871 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6872 if (start_offset_p == NULL)
6873 continue;
6874
6875 BFD_ASSERT (stub_sec_p != NULL);
6876 if (*stub_sec_p != NULL)
6877 (*stub_sec_p)->size = *start_offset_p;
6878 }
6879
d7c5bd02 6880 /* Compute stub section size, considering padding. */
906e58ca 6881 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6882 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6883 stub_type++)
6884 {
6885 int size, padding;
6886 asection **stub_sec_p;
6887
6888 padding = arm_dedicated_stub_section_padding (stub_type);
6889 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6890 /* Skip if no stub input section or no stub section padding
6891 required. */
6892 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6893 continue;
6894 /* Stub section padding required but no dedicated section. */
6895 BFD_ASSERT (stub_sec_p);
6896
6897 size = (*stub_sec_p)->size;
6898 size = (size + padding - 1) & ~(padding - 1);
6899 (*stub_sec_p)->size = size;
6900 }
906e58ca 6901
48229727
JB		 6902 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6903 if (htab->fix_cortex_a8)
99059e56
RM		 6904 for (i = 0; i < num_a8_fixes; i++)
6905 {
48229727 6906 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6907 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6908
6909 if (stub_sec == NULL)
7f991970 6910 return FALSE;
48229727 6911
99059e56
RM		 6912 stub_sec->size
6913 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6914 NULL);
6915 }
48229727
JB		 6916
6917
906e58ca
NC		 6918 /* Ask the linker to do its stuff. */
6919 (*htab->layout_sections_again) ();
4ba2ef8f 6920 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6921 }
6922
48229727
JB		 6923 /* Add stubs for Cortex-A8 erratum fixes now. */
6924 if (htab->fix_cortex_a8)
6925 {
6926 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6927 {
6928 struct elf32_arm_stub_hash_entry *stub_entry;
6929 char *stub_name = a8_fixes[i].stub_name;
6930 asection *section = a8_fixes[i].section;
6931 unsigned int section_id = a8_fixes[i].section->id;
6932 asection *link_sec = htab->stub_group[section_id].link_sec;
6933 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6934 const insn_sequence *template_sequence;
6935 int template_size, size = 0;
6936
6937 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6938 TRUE, FALSE);
6939 if (stub_entry == NULL)
6940 {
871b3ab2 6941 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6942 section->owner, stub_name);
99059e56
RM		 6943 return FALSE;
6944 }
6945
6946 stub_entry->stub_sec = stub_sec;
0955507f 6947 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6948 stub_entry->id_sec = link_sec;
6949 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6950 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6951 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6952 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6953 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6954 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6955
99059e56
RM		 6956 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6957 &template_sequence,
6958 &template_size);
48229727 6959
99059e56
RM		 6960 stub_entry->stub_size = size;
6961 stub_entry->stub_template = template_sequence;
6962 stub_entry->stub_template_size = template_size;
6963 }
48229727
JB		 6964
6965 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6966 elf32_arm_write_section(). */
48229727
JB		 6967 htab->a8_erratum_fixes = a8_fixes;
6968 htab->num_a8_erratum_fixes = num_a8_fixes;
6969 }
6970 else
6971 {
6972 htab->a8_erratum_fixes = NULL;
6973 htab->num_a8_erratum_fixes = 0;
6974 }
0955507f 6975 return ret;
5e681ec4
PB		 6976}
6977
906e58ca
NC		 6978/* Build all the stubs associated with the current output file. The
6979 stubs are kept in a hash table attached to the main linker hash
6980 table. We also set up the .plt entries for statically linked PIC
6981 functions here. This function is called via arm_elf_finish in the
6982 linker. */
252b5132 6983
906e58ca
NC		 6984bfd_boolean
6985elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6986{
906e58ca
NC		 6987 asection *stub_sec;
6988 struct bfd_hash_table *table;
0955507f 6989 enum elf32_arm_stub_type stub_type;
906e58ca 6990 struct elf32_arm_link_hash_table *htab;
252b5132 6991
906e58ca 6992 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6993 if (htab == NULL)
6994 return FALSE;
252b5132 6995
906e58ca
NC		 6996 for (stub_sec = htab->stub_bfd->sections;
6997 stub_sec != NULL;
6998 stub_sec = stub_sec->next)
252b5132 6999 {
906e58ca
NC		 7000 bfd_size_type size;
7001
8029a119 7002 /* Ignore non-stub sections. */
906e58ca
NC		 7003 if (!strstr (stub_sec->name, STUB_SUFFIX))
7004 continue;
7005
d7c5bd02 7006 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 7007 must at least be done for stub section requiring padding and for SG
7008 veneers to ensure that a non secure code branching to a removed SG
7009 veneer causes an error. */
906e58ca 7010 size = stub_sec->size;
21d799b5 7011 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 7012 if (stub_sec->contents == NULL && size != 0)
7013 return FALSE;
0955507f 7014
906e58ca 7015 stub_sec->size = 0;
252b5132
RH		 7016 }
7017
0955507f
TP		 7018 /* Add new SG veneers after those already in the input import library. */
7019 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7020 {
7021 bfd_vma *start_offset_p;
7022 asection **stub_sec_p;
7023
7024 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
7025 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
7026 if (start_offset_p == NULL)
7027 continue;
7028
7029 BFD_ASSERT (stub_sec_p != NULL);
7030 if (*stub_sec_p != NULL)
7031 (*stub_sec_p)->size = *start_offset_p;
7032 }
7033
906e58ca
NC		 7034 /* Build the stubs as directed by the stub hash table. */
7035 table = &htab->stub_hash_table;
7036 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 7037 if (htab->fix_cortex_a8)
7038 {
7039 /* Place the cortex a8 stubs last. */
7040 htab->fix_cortex_a8 = -1;
7041 bfd_hash_traverse (table, arm_build_one_stub, info);
7042 }
252b5132 7043
906e58ca 7044 return TRUE;
252b5132
RH		 7045}
7046
9b485d32
NC		 7047/* Locate the Thumb encoded calling stub for NAME. */
7048
252b5132 7049static struct elf_link_hash_entry *
57e8b36a
NC		 7050find_thumb_glue (struct bfd_link_info *link_info,
7051 const char *name,
f2a9dd69 7052 char **error_message)
252b5132
RH		 7053{
7054 char *tmp_name;
7055 struct elf_link_hash_entry *hash;
7056 struct elf32_arm_link_hash_table *hash_table;
7057
7058 /* We need a pointer to the armelf specific hash table. */
7059 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7060 if (hash_table == NULL)
7061 return NULL;
252b5132 7062
21d799b5 7063 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7064 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7065
7066 BFD_ASSERT (tmp_name);
7067
7068 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7069
7070 hash = elf_link_hash_lookup
b34976b6 7071 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7072
b1657152 7073 if (hash == NULL
90b6238f
AM		 7074 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7075 "Thumb", tmp_name, name) == -1)
b1657152 7076 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7077
7078 free (tmp_name);
7079
7080 return hash;
7081}
7082
9b485d32
NC		 7083/* Locate the ARM encoded calling stub for NAME. */
7084
252b5132 7085static struct elf_link_hash_entry *
57e8b36a
NC		 7086find_arm_glue (struct bfd_link_info *link_info,
7087 const char *name,
f2a9dd69 7088 char **error_message)
252b5132
RH		 7089{
7090 char *tmp_name;
7091 struct elf_link_hash_entry *myh;
7092 struct elf32_arm_link_hash_table *hash_table;
7093
7094 /* We need a pointer to the elfarm specific hash table. */
7095 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7096 if (hash_table == NULL)
7097 return NULL;
252b5132 7098
21d799b5 7099 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7100 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7101 BFD_ASSERT (tmp_name);
7102
7103 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7104
7105 myh = elf_link_hash_lookup
b34976b6 7106 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7107
b1657152 7108 if (myh == NULL
90b6238f
AM		 7109 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7110 "ARM", tmp_name, name) == -1)
b1657152 7111 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7112
7113 free (tmp_name);
7114
7115 return myh;
7116}
7117
8f6277f5 7118/* ARM->Thumb glue (static images):
252b5132
RH		 7119
7120 .arm
7121 __func_from_arm:
7122 ldr r12, __func_addr
7123 bx r12
7124 __func_addr:
906e58ca 7125 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 7126
26079076
PB		 7127 (v5t static images)
7128 .arm
7129 __func_from_arm:
7130 ldr pc, __func_addr
7131 __func_addr:
906e58ca 7132 .word func @ behave as if you saw a ARM_32 reloc.
26079076 7133
8f6277f5
PB		 7134 (relocatable images)
7135 .arm
7136 __func_from_arm:
7137 ldr r12, __func_offset
7138 add r12, r12, pc
7139 bx r12
7140 __func_offset:
8029a119 7141 .word func - . */
8f6277f5
PB		 7142
7143#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 7144static const insn32 a2t1_ldr_insn = 0xe59fc000;
7145static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7146static const insn32 a2t3_func_addr_insn = 0x00000001;
7147
26079076
PB		 7148#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7149static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7150static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7151
8f6277f5
PB		 7152#define ARM2THUMB_PIC_GLUE_SIZE 16
7153static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7154static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7155static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7156
07d6d2b8 7157/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 7158
07d6d2b8
AM		 7159 .thumb .thumb
7160 .align 2 .align 2
7161 __func_from_thumb: __func_from_thumb:
7162 bx pc push {r6, lr}
7163 nop ldr r6, __func_addr
7164 .arm mov lr, pc
7165 b func bx r6
99059e56
RM		 7166 .arm
7167 ;; back_to_thumb
7168 ldmia r13! {r6, lr}
7169 bx lr
7170 __func_addr:
07d6d2b8 7171 .word func */
252b5132
RH		 7172
7173#define THUMB2ARM_GLUE_SIZE 8
7174static const insn16 t2a1_bx_pc_insn = 0x4778;
7175static const insn16 t2a2_noop_insn = 0x46c0;
7176static const insn32 t2a3_b_insn = 0xea000000;
7177
c7b8f16e 7178#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 7179#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7180#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 7181
845b51d6
PB		 7182#define ARM_BX_VENEER_SIZE 12
7183static const insn32 armbx1_tst_insn = 0xe3100001;
7184static const insn32 armbx2_moveq_insn = 0x01a0f000;
7185static const insn32 armbx3_bx_insn = 0xe12fff10;
7186
7e392df6 7187#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 7188static void
7189arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 7190{
7191 asection * s;
8029a119 7192 bfd_byte * contents;
252b5132 7193
8029a119 7194 if (size == 0)
3e6b1042
DJ		 7195 {
7196 /* Do not include empty glue sections in the output. */
7197 if (abfd != NULL)
7198 {
3d4d4302 7199 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 7200 if (s != NULL)
7201 s->flags |= SEC_EXCLUDE;
7202 }
7203 return;
7204 }
252b5132 7205
8029a119 7206 BFD_ASSERT (abfd != NULL);
252b5132 7207
3d4d4302 7208 s = bfd_get_linker_section (abfd, name);
8029a119 7209 BFD_ASSERT (s != NULL);
252b5132 7210
b0f4fbf8 7211 contents = (bfd_byte *) bfd_zalloc (abfd, size);
252b5132 7212
8029a119
NC		 7213 BFD_ASSERT (s->size == size);
7214 s->contents = contents;
7215}
906e58ca 7216
8029a119
NC		 7217bfd_boolean
7218bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7219{
7220 struct elf32_arm_link_hash_table * globals;
906e58ca 7221
8029a119
NC		 7222 globals = elf32_arm_hash_table (info);
7223 BFD_ASSERT (globals != NULL);
906e58ca 7224
8029a119
NC		 7225 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7226 globals->arm_glue_size,
7227 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 7228
8029a119
NC		 7229 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7230 globals->thumb_glue_size,
7231 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 7232
8029a119
NC		 7233 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7234 globals->vfp11_erratum_glue_size,
7235 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 7236
a504d23a
LA		 7237 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7238 globals->stm32l4xx_erratum_glue_size,
7239 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7240
8029a119
NC		 7241 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7242 globals->bx_glue_size,
845b51d6
PB		 7243 ARM_BX_GLUE_SECTION_NAME);
7244
b34976b6 7245 return TRUE;
252b5132
RH		 7246}
7247
a4fd1a8e 7248/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7249 returns the symbol identifying the stub. */
7250
a4fd1a8e 7251static struct elf_link_hash_entry *
57e8b36a
NC		 7252record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7253 struct elf_link_hash_entry * h)
252b5132
RH		 7254{
7255 const char * name = h->root.root.string;
63b0f745 7256 asection * s;
252b5132
RH		 7257 char * tmp_name;
7258 struct elf_link_hash_entry * myh;
14a793b2 7259 struct bfd_link_hash_entry * bh;
252b5132 7260 struct elf32_arm_link_hash_table * globals;
dc810e39 7261 bfd_vma val;
2f475487 7262 bfd_size_type size;
252b5132
RH		 7263
7264 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7265 BFD_ASSERT (globals != NULL);
7266 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7267
3d4d4302 7268 s = bfd_get_linker_section
252b5132
RH		 7269 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7270
252b5132
RH		 7271 BFD_ASSERT (s != NULL);
7272
21d799b5 7273 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7274 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7275 BFD_ASSERT (tmp_name);
7276
7277 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7278
7279 myh = elf_link_hash_lookup
b34976b6 7280 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7281
7282 if (myh != NULL)
7283 {
9b485d32 7284 /* We've already seen this guy. */
252b5132 7285 free (tmp_name);
a4fd1a8e 7286 return myh;
252b5132
RH		 7287 }
7288
57e8b36a
NC		 7289 /* The only trick here is using hash_table->arm_glue_size as the value.
7290 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7291 putting it. The +1 on the value marks that the stub has not been
7292 output yet - not that it is a Thumb function. */
14a793b2 7293 bh = NULL;
dc810e39
AM		 7294 val = globals->arm_glue_size + 1;
7295 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7296 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7297 NULL, TRUE, FALSE, &bh);
252b5132 7298
b7693d02
DJ		 7299 myh = (struct elf_link_hash_entry *) bh;
7300 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7301 myh->forced_local = 1;
7302
252b5132
RH		 7303 free (tmp_name);
7304
0e1862bb
L		 7305 if (bfd_link_pic (link_info)
7306 || globals->root.is_relocatable_executable
27e55c4d 7307 || globals->pic_veneer)
2f475487 7308 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7309 else if (globals->use_blx)
7310 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7311 else
2f475487
AM		 7312 size = ARM2THUMB_STATIC_GLUE_SIZE;
7313
7314 s->size += size;
7315 globals->arm_glue_size += size;
252b5132 7316
a4fd1a8e 7317 return myh;
252b5132
RH		 7318}
7319
845b51d6
PB		 7320/* Allocate space for ARMv4 BX veneers. */
7321
7322static void
7323record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7324{
7325 asection * s;
7326 struct elf32_arm_link_hash_table *globals;
7327 char *tmp_name;
7328 struct elf_link_hash_entry *myh;
7329 struct bfd_link_hash_entry *bh;
7330 bfd_vma val;
7331
7332 /* BX PC does not need a veneer. */
7333 if (reg == 15)
7334 return;
7335
7336 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7337 BFD_ASSERT (globals != NULL);
7338 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7339
7340 /* Check if this veneer has already been allocated. */
7341 if (globals->bx_glue_offset[reg])
7342 return;
7343
3d4d4302 7344 s = bfd_get_linker_section
845b51d6
PB		 7345 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7346
7347 BFD_ASSERT (s != NULL);
7348
7349 /* Add symbol for veneer. */
21d799b5
NC		 7350 tmp_name = (char *)
7351 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
845b51d6 7352 BFD_ASSERT (tmp_name);
906e58ca 7353
845b51d6 7354 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7355
845b51d6
PB		 7356 myh = elf_link_hash_lookup
7357 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7358
845b51d6 7359 BFD_ASSERT (myh == NULL);
906e58ca 7360
845b51d6
PB		 7361 bh = NULL;
7362 val = globals->bx_glue_size;
7363 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7364 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7365 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7366
7367 myh = (struct elf_link_hash_entry *) bh;
7368 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7369 myh->forced_local = 1;
7370
7371 s->size += ARM_BX_VENEER_SIZE;
7372 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7373 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7374}
7375
7376
c7b8f16e
JB		 7377/* Add an entry to the code/data map for section SEC. */
7378
7379static void
7380elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7381{
7382 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7383 unsigned int newidx;
906e58ca 7384
c7b8f16e
JB		 7385 if (sec_data->map == NULL)
7386 {
21d799b5 7387 sec_data->map = (elf32_arm_section_map *)
99059e56 7388 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7389 sec_data->mapcount = 0;
7390 sec_data->mapsize = 1;
7391 }
906e58ca 7392
c7b8f16e 7393 newidx = sec_data->mapcount++;
906e58ca 7394
c7b8f16e
JB		 7395 if (sec_data->mapcount > sec_data->mapsize)
7396 {
7397 sec_data->mapsize *= 2;
21d799b5 7398 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7399 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7400 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7401 }
7402
7403 if (sec_data->map)
7404 {
7405 sec_data->map[newidx].vma = vma;
7406 sec_data->map[newidx].type = type;
c7b8f16e 7407 }
c7b8f16e
JB		 7408}
7409
7410
7411/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7412 veneers are handled for now. */
7413
7414static bfd_vma
7415record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7416 elf32_vfp11_erratum_list *branch,
7417 bfd *branch_bfd,
7418 asection *branch_sec,
7419 unsigned int offset)
c7b8f16e
JB		 7420{
7421 asection *s;
7422 struct elf32_arm_link_hash_table *hash_table;
7423 char *tmp_name;
7424 struct elf_link_hash_entry *myh;
7425 struct bfd_link_hash_entry *bh;
7426 bfd_vma val;
7427 struct _arm_elf_section_data *sec_data;
c7b8f16e 7428 elf32_vfp11_erratum_list *newerr;
906e58ca 7429
c7b8f16e 7430 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7431 BFD_ASSERT (hash_table != NULL);
7432 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7433
3d4d4302 7434 s = bfd_get_linker_section
c7b8f16e 7435 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7436
c7b8f16e 7437 sec_data = elf32_arm_section_data (s);
906e58ca 7438
c7b8f16e 7439 BFD_ASSERT (s != NULL);
906e58ca 7440
21d799b5 7441 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7442 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e 7443 BFD_ASSERT (tmp_name);
906e58ca 7444
c7b8f16e
JB		 7445 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7446 hash_table->num_vfp11_fixes);
906e58ca 7447
c7b8f16e
JB		 7448 myh = elf_link_hash_lookup
7449 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7450
c7b8f16e 7451 BFD_ASSERT (myh == NULL);
906e58ca 7452
c7b8f16e
JB		 7453 bh = NULL;
7454 val = hash_table->vfp11_erratum_glue_size;
7455 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7456 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7457 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7458
7459 myh = (struct elf_link_hash_entry *) bh;
7460 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7461 myh->forced_local = 1;
7462
7463 /* Link veneer back to calling location. */
c7e2358a 7464 sec_data->erratumcount += 1;
21d799b5
NC		 7465 newerr = (elf32_vfp11_erratum_list *)
7466 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7467
c7b8f16e
JB		 7468 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7469 newerr->vma = -1;
7470 newerr->u.v.branch = branch;
7471 newerr->u.v.id = hash_table->num_vfp11_fixes;
7472 branch->u.b.veneer = newerr;
7473
7474 newerr->next = sec_data->erratumlist;
7475 sec_data->erratumlist = newerr;
7476
7477 /* A symbol for the return from the veneer. */
7478 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7479 hash_table->num_vfp11_fixes);
7480
7481 myh = elf_link_hash_lookup
7482 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7483
c7b8f16e
JB		 7484 if (myh != NULL)
7485 abort ();
7486
7487 bh = NULL;
7488 val = offset + 4;
7489 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7490 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7491
c7b8f16e
JB		 7492 myh = (struct elf_link_hash_entry *) bh;
7493 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7494 myh->forced_local = 1;
7495
7496 free (tmp_name);
906e58ca 7497
c7b8f16e
JB		 7498 /* Generate a mapping symbol for the veneer section, and explicitly add an
7499 entry for that symbol to the code/data map for the section. */
7500 if (hash_table->vfp11_erratum_glue_size == 0)
7501 {
7502 bh = NULL;
7503 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7504 ever requires this erratum fix. */
c7b8f16e
JB		 7505 _bfd_generic_link_add_one_symbol (link_info,
7506 hash_table->bfd_of_glue_owner, "$a",
7507 BSF_LOCAL, s, 0, NULL,
99059e56 7508 TRUE, FALSE, &bh);
c7b8f16e
JB		 7509
7510 myh = (struct elf_link_hash_entry *) bh;
7511 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7512 myh->forced_local = 1;
906e58ca 7513
c7b8f16e 7514 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7515 BFDs. We must make a note of this generated mapping symbol
7516 ourselves so that code byteswapping works properly in
7517 elf32_arm_write_section. */
c7b8f16e
JB		 7518 elf32_arm_section_map_add (s, 'a', 0);
7519 }
906e58ca 7520
c7b8f16e
JB		 7521 s->size += VFP11_ERRATUM_VENEER_SIZE;
7522 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7523 hash_table->num_vfp11_fixes++;
906e58ca 7524
c7b8f16e
JB		 7525 /* The offset of the veneer. */
7526 return val;
7527}
7528
a504d23a
LA		 7529/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7530 veneers need to be handled because used only in Cortex-M. */
7531
7532static bfd_vma
7533record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7534 elf32_stm32l4xx_erratum_list *branch,
7535 bfd *branch_bfd,
7536 asection *branch_sec,
7537 unsigned int offset,
7538 bfd_size_type veneer_size)
7539{
7540 asection *s;
7541 struct elf32_arm_link_hash_table *hash_table;
7542 char *tmp_name;
7543 struct elf_link_hash_entry *myh;
7544 struct bfd_link_hash_entry *bh;
7545 bfd_vma val;
7546 struct _arm_elf_section_data *sec_data;
7547 elf32_stm32l4xx_erratum_list *newerr;
7548
7549 hash_table = elf32_arm_hash_table (link_info);
7550 BFD_ASSERT (hash_table != NULL);
7551 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7552
7553 s = bfd_get_linker_section
7554 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7555
7556 BFD_ASSERT (s != NULL);
7557
7558 sec_data = elf32_arm_section_data (s);
7559
7560 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7561 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
a504d23a
LA		 7562 BFD_ASSERT (tmp_name);
7563
7564 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7565 hash_table->num_stm32l4xx_fixes);
7566
7567 myh = elf_link_hash_lookup
7568 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7569
7570 BFD_ASSERT (myh == NULL);
7571
7572 bh = NULL;
7573 val = hash_table->stm32l4xx_erratum_glue_size;
7574 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7575 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7576 NULL, TRUE, FALSE, &bh);
7577
7578 myh = (struct elf_link_hash_entry *) bh;
7579 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7580 myh->forced_local = 1;
7581
7582 /* Link veneer back to calling location. */
7583 sec_data->stm32l4xx_erratumcount += 1;
7584 newerr = (elf32_stm32l4xx_erratum_list *)
7585 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7586
7587 newerr->type = STM32L4XX_ERRATUM_VENEER;
7588 newerr->vma = -1;
7589 newerr->u.v.branch = branch;
7590 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7591 branch->u.b.veneer = newerr;
7592
7593 newerr->next = sec_data->stm32l4xx_erratumlist;
7594 sec_data->stm32l4xx_erratumlist = newerr;
7595
7596 /* A symbol for the return from the veneer. */
7597 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7598 hash_table->num_stm32l4xx_fixes);
7599
7600 myh = elf_link_hash_lookup
7601 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7602
7603 if (myh != NULL)
7604 abort ();
7605
7606 bh = NULL;
7607 val = offset + 4;
7608 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7609 branch_sec, val, NULL, TRUE, FALSE, &bh);
7610
7611 myh = (struct elf_link_hash_entry *) bh;
7612 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7613 myh->forced_local = 1;
7614
7615 free (tmp_name);
7616
7617 /* Generate a mapping symbol for the veneer section, and explicitly add an
7618 entry for that symbol to the code/data map for the section. */
7619 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7620 {
7621 bh = NULL;
7622 /* Creates a THUMB symbol since there is no other choice. */
7623 _bfd_generic_link_add_one_symbol (link_info,
7624 hash_table->bfd_of_glue_owner, "$t",
7625 BSF_LOCAL, s, 0, NULL,
7626 TRUE, FALSE, &bh);
7627
7628 myh = (struct elf_link_hash_entry *) bh;
7629 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7630 myh->forced_local = 1;
7631
7632 /* The elf32_arm_init_maps function only cares about symbols from input
7633 BFDs. We must make a note of this generated mapping symbol
7634 ourselves so that code byteswapping works properly in
7635 elf32_arm_write_section. */
7636 elf32_arm_section_map_add (s, 't', 0);
7637 }
7638
7639 s->size += veneer_size;
7640 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7641 hash_table->num_stm32l4xx_fixes++;
7642
7643 /* The offset of the veneer. */
7644 return val;
7645}
7646
8029a119 7647#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7648 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7649 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7650
7651/* Create a fake section for use by the ARM backend of the linker. */
7652
7653static bfd_boolean
7654arm_make_glue_section (bfd * abfd, const char * name)
7655{
7656 asection * sec;
7657
3d4d4302 7658 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7659 if (sec != NULL)
7660 /* Already made. */
7661 return TRUE;
7662
3d4d4302 7663 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7664
7665 if (sec == NULL
fd361982 7666 || !bfd_set_section_alignment (sec, 2))
8029a119
NC		 7667 return FALSE;
7668
7669 /* Set the gc mark to prevent the section from being removed by garbage
7670 collection, despite the fact that no relocs refer to this section. */
7671 sec->gc_mark = 1;
7672
7673 return TRUE;
7674}
7675
1db37fe6
YG		 7676/* Set size of .plt entries. This function is called from the
7677 linker scripts in ld/emultempl/{armelf}.em. */
7678
7679void
7680bfd_elf32_arm_use_long_plt (void)
7681{
7682 elf32_arm_use_long_plt_entry = TRUE;
7683}
7684
8afb0e02
NC		 7685/* Add the glue sections to ABFD. This function is called from the
7686 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7687
b34976b6 7688bfd_boolean
57e8b36a
NC		 7689bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7690 struct bfd_link_info *info)
252b5132 7691{
a504d23a
LA		 7692 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7693 bfd_boolean dostm32l4xx = globals
7694 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7695 bfd_boolean addglue;
7696
8afb0e02
NC		 7697 /* If we are only performing a partial
7698 link do not bother adding the glue. */
0e1862bb 7699 if (bfd_link_relocatable (info))
b34976b6 7700 return TRUE;
252b5132 7701
a504d23a 7702 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7703 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7704 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7705 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7706
7707 if (!dostm32l4xx)
7708 return addglue;
7709
7710 return addglue
7711 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7712}
7713
daa4adae
TP		 7714/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7715 ensures they are not marked for deletion by
7716 strip_excluded_output_sections () when veneers are going to be created
7717 later. Not doing so would trigger assert on empty section size in
7718 lang_size_sections_1 (). */
7719
7720void
7721bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7722{
7723 enum elf32_arm_stub_type stub_type;
7724
7725 /* If we are only performing a partial
7726 link do not bother adding the glue. */
7727 if (bfd_link_relocatable (info))
7728 return;
7729
7730 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7731 {
7732 asection *out_sec;
7733 const char *out_sec_name;
7734
7735 if (!arm_dedicated_stub_output_section_required (stub_type))
7736 continue;
7737
7738 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7739 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7740 if (out_sec != NULL)
7741 out_sec->flags |= SEC_KEEP;
7742 }
7743}
7744
8afb0e02
NC		 7745/* Select a BFD to be used to hold the sections used by the glue code.
7746 This function is called from the linker scripts in ld/emultempl/
8029a119 7747 {armelf/pe}.em. */
8afb0e02 7748
b34976b6 7749bfd_boolean
57e8b36a 7750bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7751{
7752 struct elf32_arm_link_hash_table *globals;
7753
7754 /* If we are only performing a partial link
7755 do not bother getting a bfd to hold the glue. */
0e1862bb 7756 if (bfd_link_relocatable (info))
b34976b6 7757 return TRUE;
8afb0e02 7758
b7693d02
DJ		 7759 /* Make sure we don't attach the glue sections to a dynamic object. */
7760 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7761
8afb0e02 7762 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7763 BFD_ASSERT (globals != NULL);
7764
7765 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7766 return TRUE;
8afb0e02 7767
252b5132
RH		 7768 /* Save the bfd for later use. */
7769 globals->bfd_of_glue_owner = abfd;
cedb70c5 7770
b34976b6 7771 return TRUE;
252b5132
RH		 7772}
7773
906e58ca
NC		 7774static void
7775check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7776{
2de70689
MGD		 7777 int cpu_arch;
7778
b38cadfb 7779 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7780 Tag_CPU_arch);
7781
7782 if (globals->fix_arm1176)
7783 {
7784 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7785 globals->use_blx = 1;
7786 }
7787 else
7788 {
7789 if (cpu_arch > TAG_CPU_ARCH_V4T)
7790 globals->use_blx = 1;
7791 }
39b41c9c
PB		 7792}
7793
b34976b6 7794bfd_boolean
57e8b36a 7795bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7796 struct bfd_link_info *link_info)
252b5132
RH		 7797{
7798 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7799 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7800 Elf_Internal_Rela *irel, *irelend;
7801 bfd_byte *contents = NULL;
252b5132
RH		 7802
7803 asection *sec;
7804 struct elf32_arm_link_hash_table *globals;
7805
7806 /* If we are only performing a partial link do not bother
7807 to construct any glue. */
0e1862bb 7808 if (bfd_link_relocatable (link_info))
b34976b6 7809 return TRUE;
252b5132 7810
39ce1a6a
NC		 7811 /* Here we have a bfd that is to be included on the link. We have a
7812 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7813 globals = elf32_arm_hash_table (link_info);
252b5132 7814 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7815
7816 check_use_blx (globals);
252b5132 7817
d504ffc8 7818 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7819 {
90b6238f 7820 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7821 abfd);
e489d0ae
PB		 7822 return FALSE;
7823 }
f21f3fe0 7824
39ce1a6a
NC		 7825 /* PR 5398: If we have not decided to include any loadable sections in
7826 the output then we will not have a glue owner bfd. This is OK, it
7827 just means that there is nothing else for us to do here. */
7828 if (globals->bfd_of_glue_owner == NULL)
7829 return TRUE;
7830
252b5132
RH		 7831 /* Rummage around all the relocs and map the glue vectors. */
7832 sec = abfd->sections;
7833
7834 if (sec == NULL)
b34976b6 7835 return TRUE;
252b5132
RH		 7836
7837 for (; sec != NULL; sec = sec->next)
7838 {
7839 if (sec->reloc_count == 0)
7840 continue;
7841
2f475487
AM		 7842 if ((sec->flags & SEC_EXCLUDE) != 0)
7843 continue;
7844
0ffa91dd 7845 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7846
9b485d32 7847 /* Load the relocs. */
6cdc0ccc 7848 internal_relocs
906e58ca 7849 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7850
6cdc0ccc
AM		 7851 if (internal_relocs == NULL)
7852 goto error_return;
252b5132 7853
6cdc0ccc
AM		 7854 irelend = internal_relocs + sec->reloc_count;
7855 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7856 {
7857 long r_type;
7858 unsigned long r_index;
252b5132
RH		 7859
7860 struct elf_link_hash_entry *h;
7861
7862 r_type = ELF32_R_TYPE (irel->r_info);
7863 r_index = ELF32_R_SYM (irel->r_info);
7864
9b485d32 7865 /* These are the only relocation types we care about. */
ba96a88f 7866 if ( r_type != R_ARM_PC24
845b51d6 7867 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7868 continue;
7869
7870 /* Get the section contents if we haven't done so already. */
7871 if (contents == NULL)
7872 {
7873 /* Get cached copy if it exists. */
7874 if (elf_section_data (sec)->this_hdr.contents != NULL)
7875 contents = elf_section_data (sec)->this_hdr.contents;
7876 else
7877 {
7878 /* Go get them off disk. */
57e8b36a 7879 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7880 goto error_return;
7881 }
7882 }
7883
845b51d6
PB		 7884 if (r_type == R_ARM_V4BX)
7885 {
7886 int reg;
7887
7888 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7889 record_arm_bx_glue (link_info, reg);
7890 continue;
7891 }
7892
a7c10850 7893 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7894 h = NULL;
7895
9b485d32 7896 /* We don't care about local symbols. */
252b5132
RH		 7897 if (r_index < symtab_hdr->sh_info)
7898 continue;
7899
9b485d32 7900 /* This is an external symbol. */
252b5132
RH		 7901 r_index -= symtab_hdr->sh_info;
7902 h = (struct elf_link_hash_entry *)
7903 elf_sym_hashes (abfd)[r_index];
7904
7905 /* If the relocation is against a static symbol it must be within
7906 the current section and so cannot be a cross ARM/Thumb relocation. */
7907 if (h == NULL)
7908 continue;
7909
d504ffc8
DJ		 7910 /* If the call will go through a PLT entry then we do not need
7911 glue. */
362d30a1 7912 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7913 continue;
7914
252b5132
RH		 7915 switch (r_type)
7916 {
7917 case R_ARM_PC24:
7918 /* This one is a call from arm code. We need to look up
99059e56
RM		 7919 the target of the call. If it is a thumb target, we
7920 insert glue. */
39d911fc
TP		 7921 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7922 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7923 record_arm_to_thumb_glue (link_info, h);
7924 break;
7925
252b5132 7926 default:
c6596c5e 7927 abort ();
252b5132
RH		 7928 }
7929 }
6cdc0ccc 7930
c9594989 7931 if (elf_section_data (sec)->this_hdr.contents != contents)
6cdc0ccc
AM		 7932 free (contents);
7933 contents = NULL;
7934
c9594989 7935 if (elf_section_data (sec)->relocs != internal_relocs)
6cdc0ccc
AM		 7936 free (internal_relocs);
7937 internal_relocs = NULL;
252b5132
RH		 7938 }
7939
b34976b6 7940 return TRUE;
9a5aca8c 7941
dc1e8a47 7942 error_return:
c9594989 7943 if (elf_section_data (sec)->this_hdr.contents != contents)
6cdc0ccc 7944 free (contents);
c9594989 7945 if (elf_section_data (sec)->relocs != internal_relocs)
6cdc0ccc 7946 free (internal_relocs);
9a5aca8c 7947
b34976b6 7948 return FALSE;
252b5132 7949}
7e392df6 7950#endif
252b5132 7951
eb043451 7952
c7b8f16e
JB		 7953/* Initialise maps of ARM/Thumb/data for input BFDs. */
7954
7955void
7956bfd_elf32_arm_init_maps (bfd *abfd)
7957{
7958 Elf_Internal_Sym *isymbuf;
7959 Elf_Internal_Shdr *hdr;
7960 unsigned int i, localsyms;
7961
af1f4419
NC		 7962 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7963 if (! is_arm_elf (abfd))
7964 return;
7965
c7b8f16e
JB		 7966 if ((abfd->flags & DYNAMIC) != 0)
7967 return;
7968
0ffa91dd 7969 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7970 localsyms = hdr->sh_info;
7971
7972 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7973 should contain the number of local symbols, which should come before any
7974 global symbols. Mapping symbols are always local. */
7975 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7976 NULL);
7977
7978 /* No internal symbols read? Skip this BFD. */
7979 if (isymbuf == NULL)
7980 return;
7981
7982 for (i = 0; i < localsyms; i++)
7983 {
7984 Elf_Internal_Sym *isym = &isymbuf[i];
7985 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7986 const char *name;
906e58ca 7987
c7b8f16e 7988 if (sec != NULL
99059e56
RM		 7989 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7990 {
7991 name = bfd_elf_string_from_elf_section (abfd,
7992 hdr->sh_link, isym->st_name);
906e58ca 7993
99059e56 7994 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7995 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7996 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7997 }
c7b8f16e
JB		 7998 }
7999}
8000
8001
48229727
JB		 8002/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8003 say what they wanted. */
8004
8005void
8006bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
8007{
8008 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8009 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8010
4dfe6ac6
NC		 8011 if (globals == NULL)
8012 return;
8013
48229727
JB		 8014 if (globals->fix_cortex_a8 == -1)
8015 {
8016 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8017 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
8018 && (out_attr[Tag_CPU_arch_profile].i == 'A'
8019 || out_attr[Tag_CPU_arch_profile].i == 0))
8020 globals->fix_cortex_a8 = 1;
8021 else
8022 globals->fix_cortex_a8 = 0;
8023 }
8024}
8025
8026
c7b8f16e
JB		 8027void
8028bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
8029{
8030 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 8031 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 8032
4dfe6ac6
NC		 8033 if (globals == NULL)
8034 return;
c7b8f16e
JB		 8035 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8036 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
8037 {
8038 switch (globals->vfp11_fix)
99059e56
RM		 8039 {
8040 case BFD_ARM_VFP11_FIX_DEFAULT:
8041 case BFD_ARM_VFP11_FIX_NONE:
8042 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8043 break;
8044
8045 default:
8046 /* Give a warning, but do as the user requests anyway. */
871b3ab2 8047 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 8048 "workaround is not necessary for target architecture"), obfd);
8049 }
c7b8f16e
JB		 8050 }
8051 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
8052 /* For earlier architectures, we might need the workaround, but do not
8053 enable it by default. If users is running with broken hardware, they
8054 must enable the erratum fix explicitly. */
8055 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8056}
8057
a504d23a
LA		 8058void
8059bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8060{
8061 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8062 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8063
8064 if (globals == NULL)
8065 return;
8066
8067 /* We assume only Cortex-M4 may require the fix. */
8068 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8069 || out_attr[Tag_CPU_arch_profile].i != 'M')
8070 {
8071 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8072 /* Give a warning, but do as the user requests anyway. */
4eca0228 8073 _bfd_error_handler
871b3ab2 8074 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 8075 "workaround is not necessary for target architecture"), obfd);
8076 }
8077}
c7b8f16e 8078
906e58ca
NC		 8079enum bfd_arm_vfp11_pipe
8080{
c7b8f16e
JB		 8081 VFP11_FMAC,
8082 VFP11_LS,
8083 VFP11_DS,
8084 VFP11_BAD
8085};
8086
8087/* Return a VFP register number. This is encoded as RX:X for single-precision
8088 registers, or X:RX for double-precision registers, where RX is the group of
8089 four bits in the instruction encoding and X is the single extension bit.
8090 RX and X fields are specified using their lowest (starting) bit. The return
8091 value is:
8092
8093 0...31: single-precision registers s0...s31
8094 32...63: double-precision registers d0...d31.
906e58ca 8095
c7b8f16e
JB		 8096 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8097 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 8098
c7b8f16e
JB		 8099static unsigned int
8100bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 8101 unsigned int x)
c7b8f16e
JB		 8102{
8103 if (is_double)
8104 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8105 else
8106 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8107}
8108
8109/* Set bits in *WMASK according to a register number REG as encoded by
8110 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8111
8112static void
8113bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8114{
8115 if (reg < 32)
8116 *wmask |= 1 << reg;
8117 else if (reg < 48)
8118 *wmask |= 3 << ((reg - 32) * 2);
8119}
8120
8121/* Return TRUE if WMASK overwrites anything in REGS. */
8122
8123static bfd_boolean
8124bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8125{
8126 int i;
906e58ca 8127
c7b8f16e
JB		 8128 for (i = 0; i < numregs; i++)
8129 {
8130 unsigned int reg = regs[i];
8131
8132 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 8133 return TRUE;
906e58ca 8134
c7b8f16e
JB		 8135 reg -= 32;
8136
8137 if (reg >= 16)
99059e56 8138 continue;
906e58ca 8139
c7b8f16e 8140 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 8141 return TRUE;
c7b8f16e 8142 }
906e58ca 8143
c7b8f16e
JB		 8144 return FALSE;
8145}
8146
8147/* In this function, we're interested in two things: finding input registers
8148 for VFP data-processing instructions, and finding the set of registers which
8149 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8150 hold the written set, so FLDM etc. are easy to deal with (we're only
8151 interested in 32 SP registers or 16 dp registers, due to the VFP version
8152 implemented by the chip in question). DP registers are marked by setting
8153 both SP registers in the write mask). */
8154
8155static enum bfd_arm_vfp11_pipe
8156bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 8157 int *numregs)
c7b8f16e 8158{
91d6fa6a 8159 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 8160 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8161
8162 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8163 {
8164 unsigned int pqrs;
8165 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8166 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8167
8168 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 8169 | ((insn & 0x00300000) >> 19)
8170 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 8171
8172 switch (pqrs)
99059e56
RM		 8173 {
8174 case 0: /* fmac[sd]. */
8175 case 1: /* fnmac[sd]. */
8176 case 2: /* fmsc[sd]. */
8177 case 3: /* fnmsc[sd]. */
8178 vpipe = VFP11_FMAC;
8179 bfd_arm_vfp11_write_mask (destmask, fd);
8180 regs[0] = fd;
8181 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8182 regs[2] = fm;
8183 *numregs = 3;
8184 break;
8185
8186 case 4: /* fmul[sd]. */
8187 case 5: /* fnmul[sd]. */
8188 case 6: /* fadd[sd]. */
8189 case 7: /* fsub[sd]. */
8190 vpipe = VFP11_FMAC;
8191 goto vfp_binop;
8192
8193 case 8: /* fdiv[sd]. */
8194 vpipe = VFP11_DS;
8195 vfp_binop:
8196 bfd_arm_vfp11_write_mask (destmask, fd);
8197 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8198 regs[1] = fm;
8199 *numregs = 2;
8200 break;
8201
8202 case 15: /* extended opcode. */
8203 {
8204 unsigned int extn = ((insn >> 15) & 0x1e)
8205 | ((insn >> 7) & 1);
8206
8207 switch (extn)
8208 {
8209 case 0: /* fcpy[sd]. */
8210 case 1: /* fabs[sd]. */
8211 case 2: /* fneg[sd]. */
8212 case 8: /* fcmp[sd]. */
8213 case 9: /* fcmpe[sd]. */
8214 case 10: /* fcmpz[sd]. */
8215 case 11: /* fcmpez[sd]. */
8216 case 16: /* fuito[sd]. */
8217 case 17: /* fsito[sd]. */
8218 case 24: /* ftoui[sd]. */
8219 case 25: /* ftouiz[sd]. */
8220 case 26: /* ftosi[sd]. */
8221 case 27: /* ftosiz[sd]. */
8222 /* These instructions will not bounce due to underflow. */
8223 *numregs = 0;
8224 vpipe = VFP11_FMAC;
8225 break;
8226
8227 case 3: /* fsqrt[sd]. */
8228 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8229 registers to cause the erratum in previous instructions. */
8230 bfd_arm_vfp11_write_mask (destmask, fd);
8231 vpipe = VFP11_DS;
8232 break;
8233
8234 case 15: /* fcvt{ds,sd}. */
8235 {
8236 int rnum = 0;
8237
8238 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8239
8240 /* Only FCVTSD can underflow. */
99059e56
RM		 8241 if ((insn & 0x100) != 0)
8242 regs[rnum++] = fm;
c7b8f16e 8243
99059e56 8244 *numregs = rnum;
c7b8f16e 8245
99059e56
RM		 8246 vpipe = VFP11_FMAC;
8247 }
8248 break;
c7b8f16e 8249
99059e56
RM		 8250 default:
8251 return VFP11_BAD;
8252 }
8253 }
8254 break;
c7b8f16e 8255
99059e56
RM		 8256 default:
8257 return VFP11_BAD;
8258 }
c7b8f16e
JB		 8259 }
8260 /* Two-register transfer. */
8261 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8262 {
8263 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8264
c7b8f16e
JB		 8265 if ((insn & 0x100000) == 0)
8266 {
99059e56
RM		 8267 if (is_double)
8268 bfd_arm_vfp11_write_mask (destmask, fm);
8269 else
8270 {
8271 bfd_arm_vfp11_write_mask (destmask, fm);
8272 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8273 }
c7b8f16e
JB		 8274 }
8275
91d6fa6a 8276 vpipe = VFP11_LS;
c7b8f16e
JB		 8277 }
8278 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8279 {
8280 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8281 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8282
c7b8f16e 8283 switch (puw)
99059e56
RM		 8284 {
8285 case 0: /* Two-reg transfer. We should catch these above. */
8286 abort ();
906e58ca 8287
99059e56
RM		 8288 case 2: /* fldm[sdx]. */
8289 case 3:
8290 case 5:
8291 {
8292 unsigned int i, offset = insn & 0xff;
c7b8f16e 8293
99059e56
RM		 8294 if (is_double)
8295 offset >>= 1;
c7b8f16e 8296
99059e56
RM		 8297 for (i = fd; i < fd + offset; i++)
8298 bfd_arm_vfp11_write_mask (destmask, i);
8299 }
8300 break;
906e58ca 8301
99059e56
RM		 8302 case 4: /* fld[sd]. */
8303 case 6:
8304 bfd_arm_vfp11_write_mask (destmask, fd);
8305 break;
906e58ca 8306
99059e56
RM		 8307 default:
8308 return VFP11_BAD;
8309 }
c7b8f16e 8310
91d6fa6a 8311 vpipe = VFP11_LS;
c7b8f16e
JB		 8312 }
8313 /* Single-register transfer. Note L==0. */
8314 else if ((insn & 0x0f100e10) == 0x0e000a10)
8315 {
8316 unsigned int opcode = (insn >> 21) & 7;
8317 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8318
8319 switch (opcode)
99059e56
RM		 8320 {
8321 case 0: /* fmsr/fmdlr. */
8322 case 1: /* fmdhr. */
8323 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8324 destination register. I don't know if this is exactly right,
8325 but it is the conservative choice. */
8326 bfd_arm_vfp11_write_mask (destmask, fn);
8327 break;
8328
8329 case 7: /* fmxr. */
8330 break;
8331 }
c7b8f16e 8332
91d6fa6a 8333 vpipe = VFP11_LS;
c7b8f16e
JB		 8334 }
8335
91d6fa6a 8336 return vpipe;
c7b8f16e
JB		 8337}
8338
8339
8340static int elf32_arm_compare_mapping (const void * a, const void * b);
8341
8342
8343/* Look for potentially-troublesome code sequences which might trigger the
8344 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8345 (available from ARM) for details of the erratum. A short version is
8346 described in ld.texinfo. */
8347
8348bfd_boolean
8349bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8350{
8351 asection *sec;
8352 bfd_byte *contents = NULL;
8353 int state = 0;
8354 int regs[3], numregs = 0;
8355 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8356 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8357
4dfe6ac6
NC		 8358 if (globals == NULL)
8359 return FALSE;
8360
c7b8f16e
JB		 8361 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8362 The states transition as follows:
906e58ca 8363
c7b8f16e 8364 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8365 A VFP FMAC-pipeline instruction has been seen. Fill
8366 regs[0]..regs[numregs-1] with its input operands. Remember this
8367 instruction in 'first_fmac'.
c7b8f16e
JB		 8368
8369 1 -> 2
99059e56
RM		 8370 Any instruction, except for a VFP instruction which overwrites
8371 regs[*].
906e58ca 8372
c7b8f16e
JB		 8373 1 -> 3 [ -> 0 ] or
8374 2 -> 3 [ -> 0 ]
99059e56
RM		 8375 A VFP instruction has been seen which overwrites any of regs[*].
8376 We must make a veneer! Reset state to 0 before examining next
8377 instruction.
906e58ca 8378
c7b8f16e 8379 2 -> 0
99059e56
RM		 8380 If we fail to match anything in state 2, reset to state 0 and reset
8381 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8382
8383 If the VFP11 vector mode is in use, there must be at least two unrelated
8384 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8385 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8386
8387 /* If we are only performing a partial link do not bother
8388 to construct any glue. */
0e1862bb 8389 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8390 return TRUE;
8391
0ffa91dd
NC		 8392 /* Skip if this bfd does not correspond to an ELF image. */
8393 if (! is_arm_elf (abfd))
8394 return TRUE;
906e58ca 8395
c7b8f16e
JB		 8396 /* We should have chosen a fix type by the time we get here. */
8397 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8398
8399 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8400 return TRUE;
2e6030b9 8401
33a7ffc2
JM		 8402 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8403 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8404 return TRUE;
8405
c7b8f16e
JB		 8406 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8407 {
8408 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8409 struct _arm_elf_section_data *sec_data;
8410
8411 /* If we don't have executable progbits, we're not interested in this
99059e56 8412 section. Also skip if section is to be excluded. */
c7b8f16e 8413 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8414 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8415 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8416 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8417 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8418 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8419 continue;
c7b8f16e
JB		 8420
8421 sec_data = elf32_arm_section_data (sec);
906e58ca 8422
c7b8f16e 8423 if (sec_data->mapcount == 0)
99059e56 8424 continue;
906e58ca 8425
c7b8f16e
JB		 8426 if (elf_section_data (sec)->this_hdr.contents != NULL)
8427 contents = elf_section_data (sec)->this_hdr.contents;
8428 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8429 goto error_return;
8430
8431 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8432 elf32_arm_compare_mapping);
8433
8434 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8435 {
8436 unsigned int span_start = sec_data->map[span].vma;
8437 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8438 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8439 char span_type = sec_data->map[span].type;
8440
8441 /* FIXME: Only ARM mode is supported at present. We may need to
8442 support Thumb-2 mode also at some point. */
8443 if (span_type != 'a')
8444 continue;
8445
8446 for (i = span_start; i < span_end;)
8447 {
8448 unsigned int next_i = i + 4;
8449 unsigned int insn = bfd_big_endian (abfd)
13c9c485
AM		 8450 ? (((unsigned) contents[i] << 24)
8451 | (contents[i + 1] << 16)
8452 | (contents[i + 2] << 8)
8453 | contents[i + 3])
8454 : (((unsigned) contents[i + 3] << 24)
8455 | (contents[i + 2] << 16)
8456 | (contents[i + 1] << 8)
8457 | contents[i]);
99059e56
RM		 8458 unsigned int writemask = 0;
8459 enum bfd_arm_vfp11_pipe vpipe;
8460
8461 switch (state)
8462 {
8463 case 0:
8464 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8465 &numregs);
8466 /* I'm assuming the VFP11 erratum can trigger with denorm
8467 operands on either the FMAC or the DS pipeline. This might
8468 lead to slightly overenthusiastic veneer insertion. */
8469 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8470 {
8471 state = use_vector ? 1 : 2;
8472 first_fmac = i;
8473 veneer_of_insn = insn;
8474 }
8475 break;
8476
8477 case 1:
8478 {
8479 int other_regs[3], other_numregs;
8480 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8481 other_regs,
99059e56
RM		 8482 &other_numregs);
8483 if (vpipe != VFP11_BAD
8484 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8485 numregs))
99059e56
RM		 8486 state = 3;
8487 else
8488 state = 2;
8489 }
8490 break;
8491
8492 case 2:
8493 {
8494 int other_regs[3], other_numregs;
8495 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8496 other_regs,
99059e56
RM		 8497 &other_numregs);
8498 if (vpipe != VFP11_BAD
8499 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8500 numregs))
99059e56
RM		 8501 state = 3;
8502 else
8503 {
8504 state = 0;
8505 next_i = first_fmac + 4;
8506 }
8507 }
8508 break;
8509
8510 case 3:
8511 abort (); /* Should be unreachable. */
8512 }
8513
8514 if (state == 3)
8515 {
8516 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8517 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8518
8519 elf32_arm_section_data (sec)->erratumcount += 1;
8520
8521 newerr->u.b.vfp_insn = veneer_of_insn;
8522
8523 switch (span_type)
8524 {
8525 case 'a':
8526 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8527 break;
8528
8529 default:
8530 abort ();
8531 }
8532
8533 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8534 first_fmac);
8535
99059e56 8536 newerr->vma = -1;
c7b8f16e 8537
99059e56
RM		 8538 newerr->next = sec_data->erratumlist;
8539 sec_data->erratumlist = newerr;
c7b8f16e 8540
99059e56
RM		 8541 state = 0;
8542 }
c7b8f16e 8543
99059e56
RM		 8544 i = next_i;
8545 }
8546 }
906e58ca 8547
c9594989 8548 if (elf_section_data (sec)->this_hdr.contents != contents)
99059e56 8549 free (contents);
c7b8f16e
JB		 8550 contents = NULL;
8551 }
8552
8553 return TRUE;
8554
dc1e8a47 8555 error_return:
c9594989 8556 if (elf_section_data (sec)->this_hdr.contents != contents)
c7b8f16e 8557 free (contents);
906e58ca 8558
c7b8f16e
JB		 8559 return FALSE;
8560}
8561
8562/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8563 after sections have been laid out, using specially-named symbols. */
8564
8565void
8566bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8567 struct bfd_link_info *link_info)
8568{
8569 asection *sec;
8570 struct elf32_arm_link_hash_table *globals;
8571 char *tmp_name;
906e58ca 8572
0e1862bb 8573 if (bfd_link_relocatable (link_info))
c7b8f16e 8574 return;
2e6030b9
MS		 8575
8576 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8577 if (! is_arm_elf (abfd))
2e6030b9
MS		 8578 return;
8579
c7b8f16e 8580 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8581 if (globals == NULL)
8582 return;
906e58ca 8583
21d799b5 8584 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8585 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
7a0fb7be 8586 BFD_ASSERT (tmp_name);
c7b8f16e
JB		 8587
8588 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8589 {
8590 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8591 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8592
c7b8f16e 8593 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8594 {
8595 struct elf_link_hash_entry *myh;
8596 bfd_vma vma;
8597
8598 switch (errnode->type)
8599 {
8600 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8601 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8602 /* Find veneer symbol. */
8603 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8604 errnode->u.b.veneer->u.v.id);
8605
99059e56
RM		 8606 myh = elf_link_hash_lookup
8607 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8608
a504d23a 8609 if (myh == NULL)
90b6238f
AM		 8610 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8611 abfd, "VFP11", tmp_name);
a504d23a
LA		 8612
8613 vma = myh->root.u.def.section->output_section->vma
8614 + myh->root.u.def.section->output_offset
8615 + myh->root.u.def.value;
8616
8617 errnode->u.b.veneer->vma = vma;
8618 break;
8619
8620 case VFP11_ERRATUM_ARM_VENEER:
8621 case VFP11_ERRATUM_THUMB_VENEER:
8622 /* Find return location. */
8623 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8624 errnode->u.v.id);
8625
8626 myh = elf_link_hash_lookup
8627 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8628
8629 if (myh == NULL)
90b6238f
AM		 8630 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8631 abfd, "VFP11", tmp_name);
a504d23a
LA		 8632
8633 vma = myh->root.u.def.section->output_section->vma
8634 + myh->root.u.def.section->output_offset
8635 + myh->root.u.def.value;
8636
8637 errnode->u.v.branch->vma = vma;
8638 break;
8639
8640 default:
8641 abort ();
8642 }
8643 }
8644 }
8645
8646 free (tmp_name);
8647}
8648
8649/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8650 return locations after sections have been laid out, using
8651 specially-named symbols. */
8652
8653void
8654bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8655 struct bfd_link_info *link_info)
8656{
8657 asection *sec;
8658 struct elf32_arm_link_hash_table *globals;
8659 char *tmp_name;
8660
8661 if (bfd_link_relocatable (link_info))
8662 return;
8663
8664 /* Skip if this bfd does not correspond to an ELF image. */
8665 if (! is_arm_elf (abfd))
8666 return;
8667
8668 globals = elf32_arm_hash_table (link_info);
8669 if (globals == NULL)
8670 return;
8671
8672 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8673 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7a0fb7be 8674 BFD_ASSERT (tmp_name);
a504d23a
LA		 8675
8676 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8677 {
8678 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8679 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8680
8681 for (; errnode != NULL; errnode = errnode->next)
8682 {
8683 struct elf_link_hash_entry *myh;
8684 bfd_vma vma;
8685
8686 switch (errnode->type)
8687 {
8688 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8689 /* Find veneer symbol. */
8690 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8691 errnode->u.b.veneer->u.v.id);
8692
8693 myh = elf_link_hash_lookup
8694 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8695
8696 if (myh == NULL)
90b6238f
AM		 8697 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8698 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8699
8700 vma = myh->root.u.def.section->output_section->vma
8701 + myh->root.u.def.section->output_offset
8702 + myh->root.u.def.value;
8703
8704 errnode->u.b.veneer->vma = vma;
8705 break;
8706
8707 case STM32L4XX_ERRATUM_VENEER:
8708 /* Find return location. */
8709 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8710 errnode->u.v.id);
8711
8712 myh = elf_link_hash_lookup
8713 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8714
8715 if (myh == NULL)
90b6238f
AM		 8716 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8717 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8718
8719 vma = myh->root.u.def.section->output_section->vma
8720 + myh->root.u.def.section->output_offset
8721 + myh->root.u.def.value;
8722
8723 errnode->u.v.branch->vma = vma;
8724 break;
8725
8726 default:
8727 abort ();
8728 }
8729 }
8730 }
8731
8732 free (tmp_name);
8733}
8734
8735static inline bfd_boolean
8736is_thumb2_ldmia (const insn32 insn)
8737{
8738 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8739 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8740 return (insn & 0xffd02000) == 0xe8900000;
8741}
8742
8743static inline bfd_boolean
8744is_thumb2_ldmdb (const insn32 insn)
8745{
8746 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8747 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8748 return (insn & 0xffd02000) == 0xe9100000;
8749}
8750
8751static inline bfd_boolean
8752is_thumb2_vldm (const insn32 insn)
8753{
8754 /* A6.5 Extension register load or store instruction
8755 A7.7.229
9239bbd3
CM		 8756 We look for SP 32-bit and DP 64-bit registers.
8757 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8758 <list> is consecutive 64-bit registers
8759 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8760 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8761 <list> is consecutive 32-bit registers
8762 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8763 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8764 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8765 return
9239bbd3
CM		 8766 (((insn & 0xfe100f00) == 0xec100b00) ||
8767 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8768 && /* (IA without !). */
8769 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8770 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8771 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8772 /* (DB with !). */
8773 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8774}
8775
8776/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8777 VLDM opcode and:
8778 - computes the number and the mode of memory accesses
8779 - decides if the replacement should be done:
8780 . replaces only if > 8-word accesses
8781 . or (testing purposes only) replaces all accesses. */
8782
8783static bfd_boolean
8784stm32l4xx_need_create_replacing_stub (const insn32 insn,
8785 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8786{
9239bbd3 8787 int nb_words = 0;
a504d23a
LA		 8788
8789 /* The field encoding the register list is the same for both LDMIA
8790 and LDMDB encodings. */
8791 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8792 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8793 else if (is_thumb2_vldm (insn))
9239bbd3 8794 nb_words = (insn & 0xff);
a504d23a
LA		 8795
8796 /* DEFAULT mode accounts for the real bug condition situation,
8797 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8798 return
9239bbd3 8799 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8800 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8801}
8802
8803/* Look for potentially-troublesome code sequences which might trigger
8804 the STM STM32L4XX erratum. */
8805
8806bfd_boolean
8807bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8808 struct bfd_link_info *link_info)
8809{
8810 asection *sec;
8811 bfd_byte *contents = NULL;
8812 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8813
8814 if (globals == NULL)
8815 return FALSE;
8816
8817 /* If we are only performing a partial link do not bother
8818 to construct any glue. */
8819 if (bfd_link_relocatable (link_info))
8820 return TRUE;
8821
8822 /* Skip if this bfd does not correspond to an ELF image. */
8823 if (! is_arm_elf (abfd))
8824 return TRUE;
8825
8826 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8827 return TRUE;
8828
8829 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8830 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8831 return TRUE;
8832
8833 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8834 {
8835 unsigned int i, span;
8836 struct _arm_elf_section_data *sec_data;
8837
8838 /* If we don't have executable progbits, we're not interested in this
8839 section. Also skip if section is to be excluded. */
8840 if (elf_section_type (sec) != SHT_PROGBITS
8841 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8842 || (sec->flags & SEC_EXCLUDE) != 0
8843 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8844 || sec->output_section == bfd_abs_section_ptr
8845 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8846 continue;
8847
8848 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8849
a504d23a
LA		 8850 if (sec_data->mapcount == 0)
8851 continue;
c7b8f16e 8852
a504d23a
LA		 8853 if (elf_section_data (sec)->this_hdr.contents != NULL)
8854 contents = elf_section_data (sec)->this_hdr.contents;
8855 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8856 goto error_return;
c7b8f16e 8857
a504d23a
LA		 8858 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8859 elf32_arm_compare_mapping);
c7b8f16e 8860
a504d23a
LA		 8861 for (span = 0; span < sec_data->mapcount; span++)
8862 {
8863 unsigned int span_start = sec_data->map[span].vma;
8864 unsigned int span_end = (span == sec_data->mapcount - 1)
8865 ? sec->size : sec_data->map[span + 1].vma;
8866 char span_type = sec_data->map[span].type;
8867 int itblock_current_pos = 0;
c7b8f16e 8868
a504d23a
LA		 8869 /* Only Thumb2 mode need be supported with this CM4 specific
8870 code, we should not encounter any arm mode eg span_type
8871 != 'a'. */
8872 if (span_type != 't')
8873 continue;
c7b8f16e 8874
a504d23a
LA		 8875 for (i = span_start; i < span_end;)
8876 {
8877 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8878 bfd_boolean insn_32bit = FALSE;
8879 bfd_boolean is_ldm = FALSE;
8880 bfd_boolean is_vldm = FALSE;
8881 bfd_boolean is_not_last_in_it_block = FALSE;
8882
8883 /* The first 16-bits of all 32-bit thumb2 instructions start
8884 with opcode[15..13]=0b111 and the encoded op1 can be anything
8885 except opcode[12..11]!=0b00.
8886 See 32-bit Thumb instruction encoding. */
8887 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8888 insn_32bit = TRUE;
c7b8f16e 8889
a504d23a
LA		 8890 /* Compute the predicate that tells if the instruction
8891 is concerned by the IT block
8892 - Creates an error if there is a ldm that is not
8893 last in the IT block thus cannot be replaced
8894 - Otherwise we can create a branch at the end of the
8895 IT block, it will be controlled naturally by IT
8896 with the proper pseudo-predicate
8897 - So the only interesting predicate is the one that
8898 tells that we are not on the last item of an IT
8899 block. */
8900 if (itblock_current_pos != 0)
8901 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8902
a504d23a
LA		 8903 if (insn_32bit)
8904 {
8905 /* Load the rest of the insn (in manual-friendly order). */
8906 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8907 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8908 is_vldm = is_thumb2_vldm (insn);
8909
8910 /* Veneers are created for (v)ldm depending on
8911 option flags and memory accesses conditions; but
8912 if the instruction is not the last instruction of
8913 an IT block, we cannot create a jump there, so we
8914 bail out. */
5025eb7c
AO		 8915 if ((is_ldm || is_vldm)
8916 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8917 (insn, globals->stm32l4xx_fix))
8918 {
8919 if (is_not_last_in_it_block)
8920 {
4eca0228 8921 _bfd_error_handler
695344c0 8922 /* xgettext:c-format */
871b3ab2 8923 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8924 " in non-last IT block instruction:"
8925 " STM32L4XX veneer cannot be generated; "
8926 "use gcc option -mrestrict-it to generate"
8927 " only one instruction per IT block"),
d42c267e 8928 abfd, sec, i);
a504d23a
LA		 8929 }
8930 else
8931 {
8932 elf32_stm32l4xx_erratum_list *newerr =
8933 (elf32_stm32l4xx_erratum_list *)
8934 bfd_zmalloc
8935 (sizeof (elf32_stm32l4xx_erratum_list));
8936
8937 elf32_arm_section_data (sec)
8938 ->stm32l4xx_erratumcount += 1;
8939 newerr->u.b.insn = insn;
8940 /* We create only thumb branches. */
8941 newerr->type =
8942 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8943 record_stm32l4xx_erratum_veneer
8944 (link_info, newerr, abfd, sec,
8945 i,
8946 is_ldm ?
8947 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8948 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8949 newerr->vma = -1;
8950 newerr->next = sec_data->stm32l4xx_erratumlist;
8951 sec_data->stm32l4xx_erratumlist = newerr;
8952 }
8953 }
8954 }
8955 else
8956 {
8957 /* A7.7.37 IT p208
8958 IT blocks are only encoded in T1
8959 Encoding T1: IT{x{y{z}}} <firstcond>
8960 1 0 1 1 - 1 1 1 1 - firstcond - mask
8961 if mask = '0000' then see 'related encodings'
8962 We don't deal with UNPREDICTABLE, just ignore these.
8963 There can be no nested IT blocks so an IT block
8964 is naturally a new one for which it is worth
8965 computing its size. */
5025eb7c
AO		 8966 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8967 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8968 /* If we have a new IT block we compute its size. */
8969 if (is_newitblock)
8970 {
8971 /* Compute the number of instructions controlled
8972 by the IT block, it will be used to decide
8973 whether we are inside an IT block or not. */
8974 unsigned int mask = insn & 0x000f;
8975 itblock_current_pos = 4 - ctz (mask);
8976 }
8977 }
8978
8979 i += insn_32bit ? 4 : 2;
99059e56
RM		 8980 }
8981 }
a504d23a 8982
c9594989 8983 if (elf_section_data (sec)->this_hdr.contents != contents)
a504d23a
LA		 8984 free (contents);
8985 contents = NULL;
c7b8f16e 8986 }
906e58ca 8987
a504d23a
LA		 8988 return TRUE;
8989
dc1e8a47 8990 error_return:
c9594989 8991 if (elf_section_data (sec)->this_hdr.contents != contents)
a504d23a 8992 free (contents);
c7b8f16e 8993
a504d23a
LA		 8994 return FALSE;
8995}
c7b8f16e 8996
eb043451
PB		 8997/* Set target relocation values needed during linking. */
8998
8999void
68c39892 9000bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 9001 struct bfd_link_info *link_info,
68c39892 9002 struct elf32_arm_params *params)
eb043451
PB		 9003{
9004 struct elf32_arm_link_hash_table *globals;
9005
9006 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9007 if (globals == NULL)
9008 return;
eb043451 9009
68c39892 9010 globals->target1_is_rel = params->target1_is_rel;
29e9b073
CL		 9011 if (globals->fdpic_p)
9012 globals->target2_reloc = R_ARM_GOT32;
9013 else if (strcmp (params->target2_type, "rel") == 0)
eb043451 9014 globals->target2_reloc = R_ARM_REL32;
68c39892 9015 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 9016 globals->target2_reloc = R_ARM_ABS32;
68c39892 9017 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 9018 globals->target2_reloc = R_ARM_GOT_PREL;
9019 else
9020 {
90b6238f 9021 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 9022 params->target2_type);
eb043451 9023 }
68c39892
TP		 9024 globals->fix_v4bx = params->fix_v4bx;
9025 globals->use_blx |= params->use_blx;
9026 globals->vfp11_fix = params->vfp11_denorm_fix;
9027 globals->stm32l4xx_fix = params->stm32l4xx_fix;
e8b09b87
CL		 9028 if (globals->fdpic_p)
9029 globals->pic_veneer = 1;
9030 else
9031 globals->pic_veneer = params->pic_veneer;
68c39892
TP		 9032 globals->fix_cortex_a8 = params->fix_cortex_a8;
9033 globals->fix_arm1176 = params->fix_arm1176;
9034 globals->cmse_implib = params->cmse_implib;
9035 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 9036
0ffa91dd 9037 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 9038 elf_arm_tdata (output_bfd)->no_enum_size_warning
9039 = params->no_enum_size_warning;
9040 elf_arm_tdata (output_bfd)->no_wchar_size_warning
9041 = params->no_wchar_size_warning;
eb043451 9042}
eb043451 9043
12a0a0fd 9044/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 9045
12a0a0fd
PB		 9046static void
9047insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
9048{
9049 bfd_vma upper;
9050 bfd_vma lower;
9051 int reloc_sign;
9052
9053 BFD_ASSERT ((offset & 1) == 0);
9054
9055 upper = bfd_get_16 (abfd, insn);
9056 lower = bfd_get_16 (abfd, insn + 2);
9057 reloc_sign = (offset < 0) ? 1 : 0;
9058 upper = (upper & ~(bfd_vma) 0x7ff)
9059 | ((offset >> 12) & 0x3ff)
9060 | (reloc_sign << 10);
906e58ca 9061 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 9062 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9063 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9064 | ((offset >> 1) & 0x7ff);
9065 bfd_put_16 (abfd, upper, insn);
9066 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 9067}
9068
9b485d32
NC		 9069/* Thumb code calling an ARM function. */
9070
252b5132 9071static int
57e8b36a 9072elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9073 const char * name,
9074 bfd * input_bfd,
9075 bfd * output_bfd,
9076 asection * input_section,
9077 bfd_byte * hit_data,
9078 asection * sym_sec,
9079 bfd_vma offset,
9080 bfd_signed_vma addend,
9081 bfd_vma val,
f2a9dd69 9082 char **error_message)
252b5132 9083{
bcbdc74c 9084 asection * s = 0;
dc810e39 9085 bfd_vma my_offset;
252b5132 9086 long int ret_offset;
bcbdc74c
NC		 9087 struct elf_link_hash_entry * myh;
9088 struct elf32_arm_link_hash_table * globals;
252b5132 9089
f2a9dd69 9090 myh = find_thumb_glue (info, name, error_message);
252b5132 9091 if (myh == NULL)
b34976b6 9092 return FALSE;
252b5132
RH		 9093
9094 globals = elf32_arm_hash_table (info);
252b5132
RH		 9095 BFD_ASSERT (globals != NULL);
9096 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9097
9098 my_offset = myh->root.u.def.value;
9099
3d4d4302
AM		 9100 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9101 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 9102
9103 BFD_ASSERT (s != NULL);
9104 BFD_ASSERT (s->contents != NULL);
9105 BFD_ASSERT (s->output_section != NULL);
9106
9107 if ((my_offset & 0x01) == 0x01)
9108 {
9109 if (sym_sec != NULL
9110 && sym_sec->owner != NULL
9111 && !INTERWORK_FLAG (sym_sec->owner))
9112 {
4eca0228 9113 _bfd_error_handler
90b6238f
AM		 9114 (_("%pB(%s): warning: interworking not enabled;"
9115 " first occurrence: %pB: %s call to %s"),
9116 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 9117
b34976b6 9118 return FALSE;
252b5132
RH		 9119 }
9120
9121 --my_offset;
9122 myh->root.u.def.value = my_offset;
9123
52ab56c2
PB		 9124 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9125 s->contents + my_offset);
252b5132 9126
52ab56c2
PB		 9127 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9128 s->contents + my_offset + 2);
252b5132
RH		 9129
9130 ret_offset =
9b485d32
NC		 9131 /* Address of destination of the stub. */
9132 ((bfd_signed_vma) val)
252b5132 9133 - ((bfd_signed_vma)
57e8b36a
NC		 9134 /* Offset from the start of the current section
9135 to the start of the stubs. */
9b485d32
NC		 9136 (s->output_offset
9137 /* Offset of the start of this stub from the start of the stubs. */
9138 + my_offset
9139 /* Address of the start of the current section. */
9140 + s->output_section->vma)
9141 /* The branch instruction is 4 bytes into the stub. */
9142 + 4
9143 /* ARM branches work from the pc of the instruction + 8. */
9144 + 8);
252b5132 9145
52ab56c2
PB		 9146 put_arm_insn (globals, output_bfd,
9147 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9148 s->contents + my_offset + 4);
252b5132
RH		 9149 }
9150
9151 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9152
427bfd90
NC		 9153 /* Now go back and fix up the original BL insn to point to here. */
9154 ret_offset =
9155 /* Address of where the stub is located. */
9156 (s->output_section->vma + s->output_offset + my_offset)
9157 /* Address of where the BL is located. */
57e8b36a
NC		 9158 - (input_section->output_section->vma + input_section->output_offset
9159 + offset)
427bfd90
NC		 9160 /* Addend in the relocation. */
9161 - addend
9162 /* Biassing for PC-relative addressing. */
9163 - 8;
252b5132 9164
12a0a0fd 9165 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 9166
b34976b6 9167 return TRUE;
252b5132
RH		 9168}
9169
a4fd1a8e 9170/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 9171
a4fd1a8e
PB		 9172static struct elf_link_hash_entry *
9173elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9174 const char * name,
9175 bfd * input_bfd,
9176 bfd * output_bfd,
9177 asection * sym_sec,
9178 bfd_vma val,
9179 asection * s,
9180 char ** error_message)
252b5132 9181{
dc810e39 9182 bfd_vma my_offset;
252b5132 9183 long int ret_offset;
bcbdc74c
NC		 9184 struct elf_link_hash_entry * myh;
9185 struct elf32_arm_link_hash_table * globals;
252b5132 9186
f2a9dd69 9187 myh = find_arm_glue (info, name, error_message);
252b5132 9188 if (myh == NULL)
a4fd1a8e 9189 return NULL;
252b5132
RH		 9190
9191 globals = elf32_arm_hash_table (info);
252b5132
RH		 9192 BFD_ASSERT (globals != NULL);
9193 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9194
9195 my_offset = myh->root.u.def.value;
252b5132
RH		 9196
9197 if ((my_offset & 0x01) == 0x01)
9198 {
9199 if (sym_sec != NULL
9200 && sym_sec->owner != NULL
9201 && !INTERWORK_FLAG (sym_sec->owner))
9202 {
4eca0228 9203 _bfd_error_handler
90b6238f
AM		 9204 (_("%pB(%s): warning: interworking not enabled;"
9205 " first occurrence: %pB: %s call to %s"),
9206 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 9207 }
9b485d32 9208
252b5132
RH		 9209 --my_offset;
9210 myh->root.u.def.value = my_offset;
9211
0e1862bb
L		 9212 if (bfd_link_pic (info)
9213 || globals->root.is_relocatable_executable
27e55c4d 9214 || globals->pic_veneer)
8f6277f5
PB		 9215 {
9216 /* For relocatable objects we can't use absolute addresses,
9217 so construct the address from a relative offset. */
9218 /* TODO: If the offset is small it's probably worth
9219 constructing the address with adds. */
52ab56c2
PB		 9220 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9221 s->contents + my_offset);
9222 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9223 s->contents + my_offset + 4);
9224 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9225 s->contents + my_offset + 8);
8f6277f5
PB		 9226 /* Adjust the offset by 4 for the position of the add,
9227 and 8 for the pipeline offset. */
9228 ret_offset = (val - (s->output_offset
9229 + s->output_section->vma
9230 + my_offset + 12))
9231 | 1;
9232 bfd_put_32 (output_bfd, ret_offset,
9233 s->contents + my_offset + 12);
9234 }
26079076
PB		 9235 else if (globals->use_blx)
9236 {
9237 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9238 s->contents + my_offset);
9239
9240 /* It's a thumb address. Add the low order bit. */
9241 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9242 s->contents + my_offset + 4);
9243 }
8f6277f5
PB		 9244 else
9245 {
52ab56c2
PB		 9246 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9247 s->contents + my_offset);
252b5132 9248
52ab56c2
PB		 9249 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9250 s->contents + my_offset + 4);
252b5132 9251
8f6277f5
PB		 9252 /* It's a thumb address. Add the low order bit. */
9253 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9254 s->contents + my_offset + 8);
8029a119
NC		 9255
9256 my_offset += 12;
8f6277f5 9257 }
252b5132
RH		 9258 }
9259
9260 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9261
a4fd1a8e
PB		 9262 return myh;
9263}
9264
9265/* Arm code calling a Thumb function. */
9266
9267static int
9268elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9269 const char * name,
9270 bfd * input_bfd,
9271 bfd * output_bfd,
9272 asection * input_section,
9273 bfd_byte * hit_data,
9274 asection * sym_sec,
9275 bfd_vma offset,
9276 bfd_signed_vma addend,
9277 bfd_vma val,
f2a9dd69 9278 char **error_message)
a4fd1a8e
PB		 9279{
9280 unsigned long int tmp;
9281 bfd_vma my_offset;
9282 asection * s;
9283 long int ret_offset;
9284 struct elf_link_hash_entry * myh;
9285 struct elf32_arm_link_hash_table * globals;
9286
9287 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9288 BFD_ASSERT (globals != NULL);
9289 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9290
3d4d4302
AM		 9291 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9292 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9293 BFD_ASSERT (s != NULL);
9294 BFD_ASSERT (s->contents != NULL);
9295 BFD_ASSERT (s->output_section != NULL);
9296
9297 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9298 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9299 if (!myh)
9300 return FALSE;
9301
9302 my_offset = myh->root.u.def.value;
252b5132
RH		 9303 tmp = bfd_get_32 (input_bfd, hit_data);
9304 tmp = tmp & 0xFF000000;
9305
9b485d32 9306 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9307 ret_offset = (s->output_offset
9308 + my_offset
9309 + s->output_section->vma
9310 - (input_section->output_offset
9311 + input_section->output_section->vma
9312 + offset + addend)
9313 - 8);
9a5aca8c 9314
252b5132
RH		 9315 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9316
dc810e39 9317 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9318
b34976b6 9319 return TRUE;
252b5132
RH		 9320}
9321
a4fd1a8e
PB		 9322/* Populate Arm stub for an exported Thumb function. */
9323
9324static bfd_boolean
9325elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9326{
9327 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9328 asection * s;
9329 struct elf_link_hash_entry * myh;
9330 struct elf32_arm_link_hash_entry *eh;
9331 struct elf32_arm_link_hash_table * globals;
9332 asection *sec;
9333 bfd_vma val;
f2a9dd69 9334 char *error_message;
a4fd1a8e 9335
906e58ca 9336 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9337 /* Allocate stubs for exported Thumb functions on v4t. */
9338 if (eh->export_glue == NULL)
9339 return TRUE;
9340
9341 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9342 BFD_ASSERT (globals != NULL);
9343 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9344
3d4d4302
AM		 9345 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9346 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9347 BFD_ASSERT (s != NULL);
9348 BFD_ASSERT (s->contents != NULL);
9349 BFD_ASSERT (s->output_section != NULL);
9350
9351 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9352
9353 BFD_ASSERT (sec->output_section != NULL);
9354
a4fd1a8e
PB		 9355 val = eh->export_glue->root.u.def.value + sec->output_offset
9356 + sec->output_section->vma;
8029a119 9357
a4fd1a8e
PB		 9358 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9359 h->root.u.def.section->owner,
f2a9dd69
DJ		 9360 globals->obfd, sec, val, s,
9361 &error_message);
a4fd1a8e
PB		 9362 BFD_ASSERT (myh);
9363 return TRUE;
9364}
9365
845b51d6
PB		 9366/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9367
9368static bfd_vma
9369elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9370{
9371 bfd_byte *p;
9372 bfd_vma glue_addr;
9373 asection *s;
9374 struct elf32_arm_link_hash_table *globals;
9375
9376 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9377 BFD_ASSERT (globals != NULL);
9378 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9379
3d4d4302
AM		 9380 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9381 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9382 BFD_ASSERT (s != NULL);
9383 BFD_ASSERT (s->contents != NULL);
9384 BFD_ASSERT (s->output_section != NULL);
9385
9386 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9387
9388 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9389
9390 if ((globals->bx_glue_offset[reg] & 1) == 0)
9391 {
9392 p = s->contents + glue_addr;
9393 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9394 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9395 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9396 globals->bx_glue_offset[reg] |= 1;
9397 }
9398
9399 return glue_addr + s->output_section->vma + s->output_offset;
9400}
9401
a4fd1a8e
PB		 9402/* Generate Arm stubs for exported Thumb symbols. */
9403static void
906e58ca 9404elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9405 struct bfd_link_info *link_info)
9406{
9407 struct elf32_arm_link_hash_table * globals;
9408
8029a119
NC		 9409 if (link_info == NULL)
9410 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9411 return;
9412
9413 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9414 if (globals == NULL)
9415 return;
9416
84c08195
PB		 9417 /* If blx is available then exported Thumb symbols are OK and there is
9418 nothing to do. */
a4fd1a8e
PB		 9419 if (globals->use_blx)
9420 return;
9421
9422 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9423 link_info);
9424}
9425
47beaa6a
RS		 9426/* Reserve space for COUNT dynamic relocations in relocation selection
9427 SRELOC. */
9428
9429static void
9430elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9431 bfd_size_type count)
9432{
9433 struct elf32_arm_link_hash_table *htab;
9434
9435 htab = elf32_arm_hash_table (info);
9436 BFD_ASSERT (htab->root.dynamic_sections_created);
9437 if (sreloc == NULL)
9438 abort ();
9439 sreloc->size += RELOC_SIZE (htab) * count;
9440}
9441
34e77a92
RS		 9442/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9443 dynamic, the relocations should go in SRELOC, otherwise they should
9444 go in the special .rel.iplt section. */
9445
9446static void
9447elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9448 bfd_size_type count)
9449{
9450 struct elf32_arm_link_hash_table *htab;
9451
9452 htab = elf32_arm_hash_table (info);
9453 if (!htab->root.dynamic_sections_created)
9454 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9455 else
9456 {
9457 BFD_ASSERT (sreloc != NULL);
9458 sreloc->size += RELOC_SIZE (htab) * count;
9459 }
9460}
9461
47beaa6a
RS		 9462/* Add relocation REL to the end of relocation section SRELOC. */
9463
9464static void
9465elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9466 asection *sreloc, Elf_Internal_Rela *rel)
9467{
9468 bfd_byte *loc;
9469 struct elf32_arm_link_hash_table *htab;
9470
9471 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9472 if (!htab->root.dynamic_sections_created
9473 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9474 sreloc = htab->root.irelplt;
47beaa6a
RS		 9475 if (sreloc == NULL)
9476 abort ();
9477 loc = sreloc->contents;
9478 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9479 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9480 abort ();
9481 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9482}
9483
34e77a92
RS		 9484/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9485 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9486 to .plt. */
9487
9488static void
9489elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9490 bfd_boolean is_iplt_entry,
9491 union gotplt_union *root_plt,
9492 struct arm_plt_info *arm_plt)
9493{
9494 struct elf32_arm_link_hash_table *htab;
9495 asection *splt;
9496 asection *sgotplt;
9497
9498 htab = elf32_arm_hash_table (info);
9499
9500 if (is_iplt_entry)
9501 {
9502 splt = htab->root.iplt;
9503 sgotplt = htab->root.igotplt;
9504
99059e56 9505 /* NaCl uses a special first entry in .iplt too. */
90c14f0c 9506 if (htab->root.target_os == is_nacl && splt->size == 0)
99059e56
RM		 9507 splt->size += htab->plt_header_size;
9508
34e77a92
RS		 9509 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9510 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9511 }
9512 else
9513 {
9514 splt = htab->root.splt;
9515 sgotplt = htab->root.sgotplt;
9516
7801f98f
CL		 9517 if (htab->fdpic_p)
9518 {
9519 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9520 /* For lazy binding, relocations will be put into .rel.plt, in
9521 .rel.got otherwise. */
9522 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9523 if (info->flags & DF_BIND_NOW)
9524 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9525 else
9526 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9527 }
9528 else
9529 {
9530 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9531 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9532 }
34e77a92
RS		 9533
9534 /* If this is the first .plt entry, make room for the special
9535 first entry. */
9536 if (splt->size == 0)
9537 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9538
9539 htab->next_tls_desc_index++;
34e77a92
RS		 9540 }
9541
9542 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9543 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9544 splt->size += PLT_THUMB_STUB_SIZE;
9545 root_plt->offset = splt->size;
9546 splt->size += htab->plt_entry_size;
9547
90c14f0c 9548 if (htab->root.target_os != is_symbian)
34e77a92
RS		 9549 {
9550 /* We also need to make an entry in the .got.plt section, which
9551 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9552 if (is_iplt_entry)
9553 arm_plt->got_offset = sgotplt->size;
9554 else
9555 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
7801f98f
CL		 9556 if (htab->fdpic_p)
9557 /* Function descriptor takes 64 bits in GOT. */
4b24dd1a 9558 sgotplt->size += 8;
7801f98f
CL		 9559 else
9560 sgotplt->size += 4;
34e77a92
RS		 9561 }
9562}
9563
b38cadfb
NC		 9564static bfd_vma
9565arm_movw_immediate (bfd_vma value)
9566{
9567 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9568}
9569
9570static bfd_vma
9571arm_movt_immediate (bfd_vma value)
9572{
9573 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9574}
9575
34e77a92
RS		 9576/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9577 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9578 Otherwise, DYNINDX is the index of the symbol in the dynamic
9579 symbol table and SYM_VALUE is undefined.
9580
9581 ROOT_PLT points to the offset of the PLT entry from the start of its
9582 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9583 bookkeeping information.
34e77a92 9584
57460bcf
NC		 9585 Returns FALSE if there was a problem. */
9586
9587static bfd_boolean
34e77a92
RS		 9588elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9589 union gotplt_union *root_plt,
9590 struct arm_plt_info *arm_plt,
9591 int dynindx, bfd_vma sym_value)
9592{
9593 struct elf32_arm_link_hash_table *htab;
9594 asection *sgot;
9595 asection *splt;
9596 asection *srel;
9597 bfd_byte *loc;
9598 bfd_vma plt_index;
9599 Elf_Internal_Rela rel;
9600 bfd_vma plt_header_size;
9601 bfd_vma got_header_size;
9602
9603 htab = elf32_arm_hash_table (info);
9604
9605 /* Pick the appropriate sections and sizes. */
9606 if (dynindx == -1)
9607 {
9608 splt = htab->root.iplt;
9609 sgot = htab->root.igotplt;
9610 srel = htab->root.irelplt;
9611
9612 /* There are no reserved entries in .igot.plt, and no special
9613 first entry in .iplt. */
9614 got_header_size = 0;
9615 plt_header_size = 0;
9616 }
9617 else
9618 {
9619 splt = htab->root.splt;
9620 sgot = htab->root.sgotplt;
9621 srel = htab->root.srelplt;
9622
9623 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9624 plt_header_size = htab->plt_header_size;
9625 }
9626 BFD_ASSERT (splt != NULL && srel != NULL);
9627
9628 /* Fill in the entry in the procedure linkage table. */
90c14f0c 9629 if (htab->root.target_os == is_symbian)
34e77a92
RS		 9630 {
9631 BFD_ASSERT (dynindx >= 0);
9632 put_arm_insn (htab, output_bfd,
9633 elf32_arm_symbian_plt_entry[0],
9634 splt->contents + root_plt->offset);
9635 bfd_put_32 (output_bfd,
9636 elf32_arm_symbian_plt_entry[1],
9637 splt->contents + root_plt->offset + 4);
9638
9639 /* Fill in the entry in the .rel.plt section. */
9640 rel.r_offset = (splt->output_section->vma
9641 + splt->output_offset
9642 + root_plt->offset + 4);
9643 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9644
9645 /* Get the index in the procedure linkage table which
9646 corresponds to this symbol. This is the index of this symbol
9647 in all the symbols for which we are making plt entries. The
9648 first entry in the procedure linkage table is reserved. */
9649 plt_index = ((root_plt->offset - plt_header_size)
9650 / htab->plt_entry_size);
9651 }
9652 else
9653 {
9654 bfd_vma got_offset, got_address, plt_address;
9655 bfd_vma got_displacement, initial_got_entry;
9656 bfd_byte * ptr;
9657
9658 BFD_ASSERT (sgot != NULL);
9659
9660 /* Get the offset into the .(i)got.plt table of the entry that
9661 corresponds to this function. */
9662 got_offset = (arm_plt->got_offset & -2);
9663
9664 /* Get the index in the procedure linkage table which
9665 corresponds to this symbol. This is the index of this symbol
9666 in all the symbols for which we are making plt entries.
9667 After the reserved .got.plt entries, all symbols appear in
9668 the same order as in .plt. */
7801f98f 9669 if (htab->fdpic_p)
4b24dd1a
AM		 9670 /* Function descriptor takes 8 bytes. */
9671 plt_index = (got_offset - got_header_size) / 8;
7801f98f 9672 else
4b24dd1a 9673 plt_index = (got_offset - got_header_size) / 4;
34e77a92
RS		 9674
9675 /* Calculate the address of the GOT entry. */
9676 got_address = (sgot->output_section->vma
9677 + sgot->output_offset
9678 + got_offset);
9679
9680 /* ...and the address of the PLT entry. */
9681 plt_address = (splt->output_section->vma
9682 + splt->output_offset
9683 + root_plt->offset);
9684
9685 ptr = splt->contents + root_plt->offset;
90c14f0c 9686 if (htab->root.target_os == is_vxworks && bfd_link_pic (info))
34e77a92
RS		 9687 {
9688 unsigned int i;
9689 bfd_vma val;
9690
9691 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9692 {
9693 val = elf32_arm_vxworks_shared_plt_entry[i];
9694 if (i == 2)
9695 val |= got_address - sgot->output_section->vma;
9696 if (i == 5)
9697 val |= plt_index * RELOC_SIZE (htab);
9698 if (i == 2 || i == 5)
9699 bfd_put_32 (output_bfd, val, ptr);
9700 else
9701 put_arm_insn (htab, output_bfd, val, ptr);
9702 }
9703 }
90c14f0c 9704 else if (htab->root.target_os == is_vxworks)
34e77a92
RS		 9705 {
9706 unsigned int i;
9707 bfd_vma val;
9708
9709 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9710 {
9711 val = elf32_arm_vxworks_exec_plt_entry[i];
9712 if (i == 2)
9713 val |= got_address;
9714 if (i == 4)
9715 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9716 if (i == 5)
9717 val |= plt_index * RELOC_SIZE (htab);
9718 if (i == 2 || i == 5)
9719 bfd_put_32 (output_bfd, val, ptr);
9720 else
9721 put_arm_insn (htab, output_bfd, val, ptr);
9722 }
9723
9724 loc = (htab->srelplt2->contents
9725 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9726
9727 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9728 referencing the GOT for this PLT entry. */
9729 rel.r_offset = plt_address + 8;
9730 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9731 rel.r_addend = got_offset;
9732 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9733 loc += RELOC_SIZE (htab);
9734
9735 /* Create the R_ARM_ABS32 relocation referencing the
9736 beginning of the PLT for this GOT entry. */
9737 rel.r_offset = got_address;
9738 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9739 rel.r_addend = 0;
9740 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9741 }
90c14f0c 9742 else if (htab->root.target_os == is_nacl)
b38cadfb
NC		 9743 {
9744 /* Calculate the displacement between the PLT slot and the
9745 common tail that's part of the special initial PLT slot. */
6034aab8 9746 int32_t tail_displacement
b38cadfb
NC		 9747 = ((splt->output_section->vma + splt->output_offset
9748 + ARM_NACL_PLT_TAIL_OFFSET)
9749 - (plt_address + htab->plt_entry_size + 4));
9750 BFD_ASSERT ((tail_displacement & 3) == 0);
9751 tail_displacement >>= 2;
9752
9753 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9754 || (-tail_displacement & 0xff000000) == 0);
9755
9756 /* Calculate the displacement between the PLT slot and the entry
9757 in the GOT. The offset accounts for the value produced by
9758 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9759 got_displacement = (got_address
99059e56 9760 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9761
9762 /* NaCl does not support interworking at all. */
9763 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9764
9765 put_arm_insn (htab, output_bfd,
9766 elf32_arm_nacl_plt_entry[0]
9767 | arm_movw_immediate (got_displacement),
9768 ptr + 0);
9769 put_arm_insn (htab, output_bfd,
9770 elf32_arm_nacl_plt_entry[1]
9771 | arm_movt_immediate (got_displacement),
9772 ptr + 4);
9773 put_arm_insn (htab, output_bfd,
9774 elf32_arm_nacl_plt_entry[2],
9775 ptr + 8);
9776 put_arm_insn (htab, output_bfd,
9777 elf32_arm_nacl_plt_entry[3]
9778 | (tail_displacement & 0x00ffffff),
9779 ptr + 12);
9780 }
7801f98f
CL		 9781 else if (htab->fdpic_p)
9782 {
59029f57
CL		 9783 const bfd_vma *plt_entry = using_thumb_only(htab)
9784 ? elf32_arm_fdpic_thumb_plt_entry
9785 : elf32_arm_fdpic_plt_entry;
9786
7801f98f
CL		 9787 /* Fill-up Thumb stub if needed. */
9788 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9789 {
9790 put_thumb_insn (htab, output_bfd,
9791 elf32_arm_plt_thumb_stub[0], ptr - 4);
9792 put_thumb_insn (htab, output_bfd,
9793 elf32_arm_plt_thumb_stub[1], ptr - 2);
9794 }
59029f57
CL		 9795 /* As we are using 32 bit instructions even for the Thumb
9796 version, we have to use 'put_arm_insn' instead of
9797 'put_thumb_insn'. */
9798 put_arm_insn(htab, output_bfd, plt_entry[0], ptr + 0);
9799 put_arm_insn(htab, output_bfd, plt_entry[1], ptr + 4);
9800 put_arm_insn(htab, output_bfd, plt_entry[2], ptr + 8);
9801 put_arm_insn(htab, output_bfd, plt_entry[3], ptr + 12);
7801f98f
CL		 9802 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9803
9804 if (!(info->flags & DF_BIND_NOW))
9805 {
9806 /* funcdesc_value_reloc_offset. */
9807 bfd_put_32 (output_bfd,
9808 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9809 ptr + 20);
59029f57
CL		 9810 put_arm_insn(htab, output_bfd, plt_entry[6], ptr + 24);
9811 put_arm_insn(htab, output_bfd, plt_entry[7], ptr + 28);
9812 put_arm_insn(htab, output_bfd, plt_entry[8], ptr + 32);
9813 put_arm_insn(htab, output_bfd, plt_entry[9], ptr + 36);
7801f98f
CL		 9814 }
9815 }
57460bcf
NC		 9816 else if (using_thumb_only (htab))
9817 {
eed94f8f 9818 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9819 if (!using_thumb2 (htab))
eed94f8f
NC		 9820 {
9821 /* FIXME: We ought to be able to generate thumb-1 PLT
9822 instructions... */
90b6238f 9823 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9824 output_bfd);
9825 return FALSE;
9826 }
57460bcf 9827
eed94f8f
NC		 9828 /* Calculate the displacement between the PLT slot and the entry in
9829 the GOT. The 12-byte offset accounts for the value produced by
9830 adding to pc in the 3rd instruction of the PLT stub. */
9831 got_displacement = got_address - (plt_address + 12);
9832
9833 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9834 instead of 'put_thumb_insn'. */
9835 put_arm_insn (htab, output_bfd,
9836 elf32_thumb2_plt_entry[0]
9837 | ((got_displacement & 0x000000ff) << 16)
9838 | ((got_displacement & 0x00000700) << 20)
9839 | ((got_displacement & 0x00000800) >> 1)
9840 | ((got_displacement & 0x0000f000) >> 12),
9841 ptr + 0);
9842 put_arm_insn (htab, output_bfd,
9843 elf32_thumb2_plt_entry[1]
9844 | ((got_displacement & 0x00ff0000) )
9845 | ((got_displacement & 0x07000000) << 4)
9846 | ((got_displacement & 0x08000000) >> 17)
9847 | ((got_displacement & 0xf0000000) >> 28),
9848 ptr + 4);
9849 put_arm_insn (htab, output_bfd,
9850 elf32_thumb2_plt_entry[2],
9851 ptr + 8);
9852 put_arm_insn (htab, output_bfd,
9853 elf32_thumb2_plt_entry[3],
9854 ptr + 12);
57460bcf 9855 }
34e77a92
RS		 9856 else
9857 {
9858 /* Calculate the displacement between the PLT slot and the
9859 entry in the GOT. The eight-byte offset accounts for the
9860 value produced by adding to pc in the first instruction
9861 of the PLT stub. */
9862 got_displacement = got_address - (plt_address + 8);
9863
34e77a92
RS		 9864 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9865 {
9866 put_thumb_insn (htab, output_bfd,
9867 elf32_arm_plt_thumb_stub[0], ptr - 4);
9868 put_thumb_insn (htab, output_bfd,
9869 elf32_arm_plt_thumb_stub[1], ptr - 2);
9870 }
9871
1db37fe6
YG		 9872 if (!elf32_arm_use_long_plt_entry)
9873 {
9874 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9875
9876 put_arm_insn (htab, output_bfd,
9877 elf32_arm_plt_entry_short[0]
9878 | ((got_displacement & 0x0ff00000) >> 20),
9879 ptr + 0);
9880 put_arm_insn (htab, output_bfd,
9881 elf32_arm_plt_entry_short[1]
9882 | ((got_displacement & 0x000ff000) >> 12),
9883 ptr+ 4);
9884 put_arm_insn (htab, output_bfd,
9885 elf32_arm_plt_entry_short[2]
9886 | (got_displacement & 0x00000fff),
9887 ptr + 8);
34e77a92 9888#ifdef FOUR_WORD_PLT
1db37fe6 9889 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9890#endif
1db37fe6
YG		 9891 }
9892 else
9893 {
9894 put_arm_insn (htab, output_bfd,
9895 elf32_arm_plt_entry_long[0]
9896 | ((got_displacement & 0xf0000000) >> 28),
9897 ptr + 0);
9898 put_arm_insn (htab, output_bfd,
9899 elf32_arm_plt_entry_long[1]
9900 | ((got_displacement & 0x0ff00000) >> 20),
9901 ptr + 4);
9902 put_arm_insn (htab, output_bfd,
9903 elf32_arm_plt_entry_long[2]
9904 | ((got_displacement & 0x000ff000) >> 12),
9905 ptr+ 8);
9906 put_arm_insn (htab, output_bfd,
9907 elf32_arm_plt_entry_long[3]
9908 | (got_displacement & 0x00000fff),
9909 ptr + 12);
9910 }
34e77a92
RS		 9911 }
9912
9913 /* Fill in the entry in the .rel(a).(i)plt section. */
9914 rel.r_offset = got_address;
9915 rel.r_addend = 0;
9916 if (dynindx == -1)
9917 {
9918 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9919 The dynamic linker or static executable then calls SYM_VALUE
9920 to determine the correct run-time value of the .igot.plt entry. */
9921 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9922 initial_got_entry = sym_value;
9923 }
9924 else
9925 {
7801f98f
CL		 9926 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9927 used by PLT entry. */
9928 if (htab->fdpic_p)
9929 {
9930 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
9931 initial_got_entry = 0;
9932 }
9933 else
9934 {
9935 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9936 initial_got_entry = (splt->output_section->vma
9937 + splt->output_offset);
a7618269
TC		 9938
9939 /* PR ld/16017
9940 When thumb only we need to set the LSB for any address that
9941 will be used with an interworking branch instruction. */
9942 if (using_thumb_only (htab))
9943 initial_got_entry |= 1;
7801f98f 9944 }
34e77a92
RS		 9945 }
9946
9947 /* Fill in the entry in the global offset table. */
9948 bfd_put_32 (output_bfd, initial_got_entry,
9949 sgot->contents + got_offset);
7801f98f
CL		 9950
9951 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
9952 {
9953 /* Setup initial funcdesc value. */
9954 /* FIXME: we don't support lazy binding because there is a
9955 race condition between both words getting written and
9956 some other thread attempting to read them. The ARM
9957 architecture does not have an atomic 64 bit load/store
9958 instruction that could be used to prevent it; it is
9959 recommended that threaded FDPIC applications run with the
9960 LD_BIND_NOW environment variable set. */
9961 bfd_put_32(output_bfd, plt_address + 0x18,
9962 sgot->contents + got_offset);
9963 bfd_put_32(output_bfd, -1 /*TODO*/,
9964 sgot->contents + got_offset + 4);
9965 }
34e77a92
RS		 9966 }
9967
aba8c3de
WN		 9968 if (dynindx == -1)
9969 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9970 else
9971 {
7801f98f
CL		 9972 if (htab->fdpic_p)
9973 {
9974 /* For FDPIC we put PLT relocationss into .rel.got when not
9975 lazy binding otherwise we put them in .rel.plt. For now,
9976 we don't support lazy binding so put it in .rel.got. */
9977 if (info->flags & DF_BIND_NOW)
9978 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelgot, &rel);
9979 else
9980 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelplt, &rel);
9981 }
9982 else
9983 {
9984 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9985 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9986 }
aba8c3de 9987 }
57460bcf
NC		 9988
9989 return TRUE;
34e77a92
RS		 9990}
9991
eb043451
PB		 9992/* Some relocations map to different relocations depending on the
9993 target. Return the real relocation. */
8029a119 9994
eb043451
PB		 9995static int
9996arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9997 int r_type)
9998{
9999 switch (r_type)
10000 {
10001 case R_ARM_TARGET1:
10002 if (globals->target1_is_rel)
10003 return R_ARM_REL32;
10004 else
10005 return R_ARM_ABS32;
10006
10007 case R_ARM_TARGET2:
10008 return globals->target2_reloc;
10009
10010 default:
10011 return r_type;
10012 }
10013}
eb043451 10014
ba93b8ac
DJ		 10015/* Return the base VMA address which should be subtracted from real addresses
10016 when resolving @dtpoff relocation.
10017 This is PT_TLS segment p_vaddr. */
10018
10019static bfd_vma
10020dtpoff_base (struct bfd_link_info *info)
10021{
10022 /* If tls_sec is NULL, we should have signalled an error already. */
10023 if (elf_hash_table (info)->tls_sec == NULL)
10024 return 0;
10025 return elf_hash_table (info)->tls_sec->vma;
10026}
10027
10028/* Return the relocation value for @tpoff relocation
10029 if STT_TLS virtual address is ADDRESS. */
10030
10031static bfd_vma
10032tpoff (struct bfd_link_info *info, bfd_vma address)
10033{
10034 struct elf_link_hash_table *htab = elf_hash_table (info);
10035 bfd_vma base;
10036
10037 /* If tls_sec is NULL, we should have signalled an error already. */
10038 if (htab->tls_sec == NULL)
10039 return 0;
10040 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
10041 return address - htab->tls_sec->vma + base;
10042}
10043
00a97672
RS		 10044/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10045 VALUE is the relocation value. */
10046
10047static bfd_reloc_status_type
10048elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
10049{
10050 if (value > 0xfff)
10051 return bfd_reloc_overflow;
10052
10053 value |= bfd_get_32 (abfd, data) & 0xfffff000;
10054 bfd_put_32 (abfd, value, data);
10055 return bfd_reloc_ok;
10056}
10057
0855e32b
NS		 10058/* Handle TLS relaxations. Relaxing is possible for symbols that use
10059 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10060 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10061
10062 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10063 is to then call final_link_relocate. Return other values in the
62672b10
NS		 10064 case of error.
10065
10066 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10067 the pre-relaxed code. It would be nice if the relocs were updated
10068 to match the optimization. */
0855e32b 10069
b38cadfb 10070static bfd_reloc_status_type
0855e32b 10071elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 10072 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 10073 Elf_Internal_Rela *rel, unsigned long is_local)
10074{
10075 unsigned long insn;
b38cadfb 10076
0855e32b
NS		 10077 switch (ELF32_R_TYPE (rel->r_info))
10078 {
10079 default:
10080 return bfd_reloc_notsupported;
b38cadfb 10081
0855e32b
NS		 10082 case R_ARM_TLS_GOTDESC:
10083 if (is_local)
10084 insn = 0;
10085 else
10086 {
10087 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10088 if (insn & 1)
10089 insn -= 5; /* THUMB */
10090 else
10091 insn -= 8; /* ARM */
10092 }
10093 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10094 return bfd_reloc_continue;
10095
10096 case R_ARM_THM_TLS_DESCSEQ:
10097 /* Thumb insn. */
10098 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10099 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10100 {
10101 if (is_local)
10102 /* nop */
10103 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10104 }
10105 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10106 {
10107 if (is_local)
10108 /* nop */
10109 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10110 else
10111 /* ldr rx,[ry] */
10112 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10113 }
10114 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10115 {
10116 if (is_local)
10117 /* nop */
10118 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10119 else
10120 /* mov r0, rx */
10121 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10122 contents + rel->r_offset);
10123 }
10124 else
10125 {
10126 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10127 /* It's a 32 bit instruction, fetch the rest of it for
10128 error generation. */
10129 insn = (insn << 16)
10130 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 10131 _bfd_error_handler
695344c0 10132 /* xgettext:c-format */
2dcf00ce 10133 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10134 "unexpected %s instruction '%#lx' in TLS trampoline"),
10135 input_bfd, input_sec, (uint64_t) rel->r_offset,
10136 "Thumb", insn);
0855e32b
NS		 10137 return bfd_reloc_notsupported;
10138 }
10139 break;
b38cadfb 10140
0855e32b
NS		 10141 case R_ARM_TLS_DESCSEQ:
10142 /* arm insn. */
10143 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10144 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10145 {
10146 if (is_local)
10147 /* mov rx, ry */
10148 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10149 contents + rel->r_offset);
10150 }
10151 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10152 {
10153 if (is_local)
10154 /* nop */
10155 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10156 else
10157 /* ldr rx,[ry] */
10158 bfd_put_32 (input_bfd, insn & 0xfffff000,
10159 contents + rel->r_offset);
10160 }
10161 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10162 {
10163 if (is_local)
10164 /* nop */
10165 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10166 else
10167 /* mov r0, rx */
10168 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10169 contents + rel->r_offset);
10170 }
10171 else
10172 {
4eca0228 10173 _bfd_error_handler
695344c0 10174 /* xgettext:c-format */
2dcf00ce 10175 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10176 "unexpected %s instruction '%#lx' in TLS trampoline"),
10177 input_bfd, input_sec, (uint64_t) rel->r_offset,
10178 "ARM", insn);
0855e32b
NS		 10179 return bfd_reloc_notsupported;
10180 }
10181 break;
10182
10183 case R_ARM_TLS_CALL:
10184 /* GD->IE relaxation, turn the instruction into 'nop' or
10185 'ldr r0, [pc,r0]' */
10186 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10187 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10188 break;
b38cadfb 10189
0855e32b 10190 case R_ARM_THM_TLS_CALL:
6a631e86 10191 /* GD->IE relaxation. */
0855e32b
NS		 10192 if (!is_local)
10193 /* add r0,pc; ldr r0, [r0] */
10194 insn = 0x44786800;
60a019a0 10195 else if (using_thumb2 (globals))
0855e32b
NS		 10196 /* nop.w */
10197 insn = 0xf3af8000;
10198 else
10199 /* nop; nop */
10200 insn = 0xbf00bf00;
b38cadfb 10201
0855e32b
NS		 10202 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10203 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10204 break;
10205 }
10206 return bfd_reloc_ok;
10207}
10208
4962c51a
MS		 10209/* For a given value of n, calculate the value of G_n as required to
10210 deal with group relocations. We return it in the form of an
10211 encoded constant-and-rotation, together with the final residual. If n is
10212 specified as less than zero, then final_residual is filled with the
10213 input value and no further action is performed. */
10214
10215static bfd_vma
10216calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10217{
10218 int current_n;
10219 bfd_vma g_n;
10220 bfd_vma encoded_g_n = 0;
10221 bfd_vma residual = value; /* Also known as Y_n. */
10222
10223 for (current_n = 0; current_n <= n; current_n++)
10224 {
10225 int shift;
10226
10227 /* Calculate which part of the value to mask. */
10228 if (residual == 0)
99059e56 10229 shift = 0;
4962c51a 10230 else
99059e56
RM		 10231 {
10232 int msb;
10233
10234 /* Determine the most significant bit in the residual and
10235 align the resulting value to a 2-bit boundary. */
10236 for (msb = 30; msb >= 0; msb -= 2)
10237 if (residual & (3 << msb))
10238 break;
10239
10240 /* The desired shift is now (msb - 6), or zero, whichever
10241 is the greater. */
10242 shift = msb - 6;
10243 if (shift < 0)
10244 shift = 0;
10245 }
4962c51a
MS		 10246
10247 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10248 g_n = residual & (0xff << shift);
10249 encoded_g_n = (g_n >> shift)
99059e56 10250 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 10251
10252 /* Calculate the residual for the next time around. */
10253 residual &= ~g_n;
10254 }
10255
10256 *final_residual = residual;
10257
10258 return encoded_g_n;
10259}
10260
10261/* Given an ARM instruction, determine whether it is an ADD or a SUB.
10262 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 10263
4962c51a 10264static int
906e58ca 10265identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 10266{
10267 int opcode = insn & 0x1e00000;
10268
10269 if (opcode == 1 << 23) /* ADD */
10270 return 1;
10271
10272 if (opcode == 1 << 22) /* SUB */
10273 return -1;
10274
10275 return 0;
10276}
10277
252b5132 10278/* Perform a relocation as part of a final link. */
9b485d32 10279
252b5132 10280static bfd_reloc_status_type
07d6d2b8
AM		 10281elf32_arm_final_link_relocate (reloc_howto_type * howto,
10282 bfd * input_bfd,
10283 bfd * output_bfd,
10284 asection * input_section,
10285 bfd_byte * contents,
10286 Elf_Internal_Rela * rel,
10287 bfd_vma value,
10288 struct bfd_link_info * info,
10289 asection * sym_sec,
10290 const char * sym_name,
10291 unsigned char st_type,
10292 enum arm_st_branch_type branch_type,
0945cdfd 10293 struct elf_link_hash_entry * h,
07d6d2b8
AM		 10294 bfd_boolean * unresolved_reloc_p,
10295 char ** error_message)
10296{
10297 unsigned long r_type = howto->type;
10298 unsigned long r_symndx;
10299 bfd_byte * hit_data = contents + rel->r_offset;
10300 bfd_vma * local_got_offsets;
10301 bfd_vma * local_tlsdesc_gotents;
10302 asection * sgot;
10303 asection * splt;
10304 asection * sreloc = NULL;
10305 asection * srelgot;
10306 bfd_vma addend;
10307 bfd_signed_vma signed_addend;
10308 unsigned char dynreloc_st_type;
10309 bfd_vma dynreloc_value;
ba96a88f 10310 struct elf32_arm_link_hash_table * globals;
34e77a92 10311 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 10312 union gotplt_union *root_plt;
10313 struct arm_plt_info *arm_plt;
10314 bfd_vma plt_offset;
10315 bfd_vma gotplt_offset;
10316 bfd_boolean has_iplt_entry;
10317 bfd_boolean resolved_to_zero;
f21f3fe0 10318
9c504268 10319 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 10320 if (globals == NULL)
10321 return bfd_reloc_notsupported;
9c504268 10322
0ffa91dd 10323 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 10324 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 10325
10326 /* Some relocation types map to different relocations depending on the
9c504268 10327 target. We pick the right one here. */
eb043451 10328 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 10329
10330 /* It is possible to have linker relaxations on some TLS access
10331 models. Update our information here. */
10332 r_type = elf32_arm_tls_transition (info, r_type, h);
10333
eb043451
PB		 10334 if (r_type != howto->type)
10335 howto = elf32_arm_howto_from_type (r_type);
9c504268 10336
34e77a92 10337 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 10338 sgot = globals->root.sgot;
252b5132 10339 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 10340 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10341
34e77a92
RS		 10342 if (globals->root.dynamic_sections_created)
10343 srelgot = globals->root.srelgot;
10344 else
10345 srelgot = NULL;
10346
252b5132
RH		 10347 r_symndx = ELF32_R_SYM (rel->r_info);
10348
4e7fd91e 10349 if (globals->use_rel)
ba96a88f 10350 {
4e7fd91e
PB		 10351 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
10352
10353 if (addend & ((howto->src_mask + 1) >> 1))
10354 {
10355 signed_addend = -1;
10356 signed_addend &= ~ howto->src_mask;
10357 signed_addend |= addend;
10358 }
10359 else
10360 signed_addend = addend;
ba96a88f
NC		 10361 }
10362 else
4e7fd91e 10363 addend = signed_addend = rel->r_addend;
f21f3fe0 10364
39f21624
NC		 10365 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10366 are resolving a function call relocation. */
10367 if (using_thumb_only (globals)
10368 && (r_type == R_ARM_THM_CALL
10369 || r_type == R_ARM_THM_JUMP24)
10370 && branch_type == ST_BRANCH_TO_ARM)
10371 branch_type = ST_BRANCH_TO_THUMB;
10372
34e77a92
RS		 10373 /* Record the symbol information that should be used in dynamic
10374 relocations. */
10375 dynreloc_st_type = st_type;
10376 dynreloc_value = value;
10377 if (branch_type == ST_BRANCH_TO_THUMB)
10378 dynreloc_value |= 1;
10379
10380 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10381 VALUE appropriately for relocations that we resolve at link time. */
10382 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10383 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10384 &arm_plt)
34e77a92
RS		 10385 && root_plt->offset != (bfd_vma) -1)
10386 {
10387 plt_offset = root_plt->offset;
10388 gotplt_offset = arm_plt->got_offset;
10389
10390 if (h == NULL || eh->is_iplt)
10391 {
10392 has_iplt_entry = TRUE;
10393 splt = globals->root.iplt;
10394
10395 /* Populate .iplt entries here, because not all of them will
10396 be seen by finish_dynamic_symbol. The lower bit is set if
10397 we have already populated the entry. */
10398 if (plt_offset & 1)
10399 plt_offset--;
10400 else
10401 {
57460bcf
NC		 10402 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10403 -1, dynreloc_value))
10404 root_plt->offset |= 1;
10405 else
10406 return bfd_reloc_notsupported;
34e77a92
RS		 10407 }
10408
10409 /* Static relocations always resolve to the .iplt entry. */
10410 st_type = STT_FUNC;
10411 value = (splt->output_section->vma
10412 + splt->output_offset
10413 + plt_offset);
10414 branch_type = ST_BRANCH_TO_ARM;
10415
10416 /* If there are non-call relocations that resolve to the .iplt
10417 entry, then all dynamic ones must too. */
10418 if (arm_plt->noncall_refcount != 0)
10419 {
10420 dynreloc_st_type = st_type;
10421 dynreloc_value = value;
10422 }
10423 }
10424 else
10425 /* We populate the .plt entry in finish_dynamic_symbol. */
10426 splt = globals->root.splt;
10427 }
10428 else
10429 {
10430 splt = NULL;
10431 plt_offset = (bfd_vma) -1;
10432 gotplt_offset = (bfd_vma) -1;
10433 }
10434
95b03e4a
L		 10435 resolved_to_zero = (h != NULL
10436 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10437
252b5132
RH		 10438 switch (r_type)
10439 {
10440 case R_ARM_NONE:
28a094c2
DJ		 10441 /* We don't need to find a value for this symbol. It's just a
10442 marker. */
10443 *unresolved_reloc_p = FALSE;
252b5132
RH		 10444 return bfd_reloc_ok;
10445
00a97672 10446 case R_ARM_ABS12:
90c14f0c 10447 if (globals->root.target_os != is_vxworks)
00a97672 10448 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10449 /* Fall through. */
00a97672 10450
252b5132
RH		 10451 case R_ARM_PC24:
10452 case R_ARM_ABS32:
bb224fc3 10453 case R_ARM_ABS32_NOI:
252b5132 10454 case R_ARM_REL32:
bb224fc3 10455 case R_ARM_REL32_NOI:
5b5bb741
PB		 10456 case R_ARM_CALL:
10457 case R_ARM_JUMP24:
dfc5f959 10458 case R_ARM_XPC25:
eb043451 10459 case R_ARM_PREL31:
7359ea65 10460 case R_ARM_PLT32:
7359ea65
DJ		 10461 /* Handle relocations which should use the PLT entry. ABS32/REL32
10462 will use the symbol's value, which may point to a PLT entry, but we
10463 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10464 branches in this object should go to it, except if the PLT is too
10465 far away, in which case a long branch stub should be inserted. */
bb224fc3 10466 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10467 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10468 && r_type != R_ARM_CALL
10469 && r_type != R_ARM_JUMP24
10470 && r_type != R_ARM_PLT32)
34e77a92 10471 && plt_offset != (bfd_vma) -1)
7359ea65 10472 {
34e77a92
RS		 10473 /* If we've created a .plt section, and assigned a PLT entry
10474 to this function, it must either be a STT_GNU_IFUNC reference
10475 or not be known to bind locally. In other cases, we should
10476 have cleared the PLT entry by now. */
10477 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10478
10479 value = (splt->output_section->vma
10480 + splt->output_offset
34e77a92 10481 + plt_offset);
0945cdfd 10482 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10483 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10484 contents, rel->r_offset, value,
00a97672 10485 rel->r_addend);
7359ea65
DJ		 10486 }
10487
67687978
PB		 10488 /* When generating a shared object or relocatable executable, these
10489 relocations are copied into the output file to be resolved at
10490 run time. */
0e1862bb 10491 if ((bfd_link_pic (info)
e8b09b87
CL		 10492 || globals->root.is_relocatable_executable
10493 || globals->fdpic_p)
7359ea65 10494 && (input_section->flags & SEC_ALLOC)
90c14f0c 10495 && !(globals->root.target_os == is_vxworks
3348747a
NS		 10496 && strcmp (input_section->output_section->name,
10497 ".tls_vars") == 0)
bb224fc3 10498 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10499 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10500 && !(input_bfd == globals->stub_bfd
10501 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10502 && (h == NULL
95b03e4a
L		 10503 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10504 && !resolved_to_zero)
7359ea65
DJ		 10505 || h->root.type != bfd_link_hash_undefweak)
10506 && r_type != R_ARM_PC24
5b5bb741
PB		 10507 && r_type != R_ARM_CALL
10508 && r_type != R_ARM_JUMP24
ee06dc07 10509 && r_type != R_ARM_PREL31
7359ea65 10510 && r_type != R_ARM_PLT32)
252b5132 10511 {
947216bf 10512 Elf_Internal_Rela outrel;
b34976b6 10513 bfd_boolean skip, relocate;
e8b09b87 10514 int isrofixup = 0;
f21f3fe0 10515
52db4ec2
JW		 10516 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10517 && !h->def_regular)
10518 {
10519 char *v = _("shared object");
10520
0e1862bb 10521 if (bfd_link_executable (info))
52db4ec2
JW		 10522 v = _("PIE executable");
10523
4eca0228 10524 _bfd_error_handler
871b3ab2 10525 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10526 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10527 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10528 return bfd_reloc_notsupported;
10529 }
10530
0945cdfd
DJ		 10531 *unresolved_reloc_p = FALSE;
10532
34e77a92 10533 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10534 {
83bac4b0
NC		 10535 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10536 ! globals->use_rel);
f21f3fe0 10537
83bac4b0 10538 if (sreloc == NULL)
252b5132 10539 return bfd_reloc_notsupported;
252b5132 10540 }
f21f3fe0 10541
b34976b6
AM		 10542 skip = FALSE;
10543 relocate = FALSE;
f21f3fe0 10544
00a97672 10545 outrel.r_addend = addend;
c629eae0
JJ		 10546 outrel.r_offset =
10547 _bfd_elf_section_offset (output_bfd, info, input_section,
10548 rel->r_offset);
10549 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10550 skip = TRUE;
0bb2d96a 10551 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10552 skip = TRUE, relocate = TRUE;
252b5132
RH		 10553 outrel.r_offset += (input_section->output_section->vma
10554 + input_section->output_offset);
f21f3fe0 10555
252b5132 10556 if (skip)
0bb2d96a 10557 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10558 else if (h != NULL
10559 && h->dynindx != -1
0e1862bb 10560 && (!bfd_link_pic (info)
1dcb9720
JW		 10561 || !(bfd_link_pie (info)
10562 || SYMBOLIC_BIND (info, h))
f5385ebf 10563 || !h->def_regular))
5e681ec4 10564 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10565 else
10566 {
a16385dc
MM		 10567 int symbol;
10568
5e681ec4 10569 /* This symbol is local, or marked to become local. */
e8b09b87
CL		 10570 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10571 || (globals->fdpic_p && !bfd_link_pic(info)));
90c14f0c 10572 if (globals->root.target_os == is_symbian)
6366ff1e 10573 {
74541ad4
AM		 10574 asection *osec;
10575
6366ff1e
MM		 10576 /* On Symbian OS, the data segment and text segement
10577 can be relocated independently. Therefore, we
10578 must indicate the segment to which this
10579 relocation is relative. The BPABI allows us to
10580 use any symbol in the right segment; we just use
10581 the section symbol as it is convenient. (We
10582 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10583 will not appear in the dynamic symbol table.)
10584
10585 Note that the dynamic linker ignores the section
10586 symbol value, so we don't subtract osec->vma
10587 from the emitted reloc addend. */
10dbd1f3 10588 if (sym_sec)
74541ad4 10589 osec = sym_sec->output_section;
10dbd1f3 10590 else
74541ad4
AM		 10591 osec = input_section->output_section;
10592 symbol = elf_section_data (osec)->dynindx;
10593 if (symbol == 0)
10594 {
10595 struct elf_link_hash_table *htab = elf_hash_table (info);
10596
10597 if ((osec->flags & SEC_READONLY) == 0
10598 && htab->data_index_section != NULL)
10599 osec = htab->data_index_section;
10600 else
10601 osec = htab->text_index_section;
10602 symbol = elf_section_data (osec)->dynindx;
10603 }
6366ff1e
MM		 10604 BFD_ASSERT (symbol != 0);
10605 }
a16385dc
MM		 10606 else
10607 /* On SVR4-ish systems, the dynamic loader cannot
10608 relocate the text and data segments independently,
10609 so the symbol does not matter. */
10610 symbol = 0;
34e77a92
RS		 10611 if (dynreloc_st_type == STT_GNU_IFUNC)
10612 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10613 to the .iplt entry. Instead, every non-call reference
10614 must use an R_ARM_IRELATIVE relocation to obtain the
10615 correct run-time address. */
10616 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
e8b09b87
CL		 10617 else if (globals->fdpic_p && !bfd_link_pic(info))
10618 isrofixup = 1;
34e77a92
RS		 10619 else
10620 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10621 if (globals->use_rel)
10622 relocate = TRUE;
10623 else
34e77a92 10624 outrel.r_addend += dynreloc_value;
252b5132 10625 }
f21f3fe0 10626
e8b09b87
CL		 10627 if (isrofixup)
10628 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
10629 else
10630 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10631
f21f3fe0 10632 /* If this reloc is against an external symbol, we do not want to
252b5132 10633 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10634 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10635 if (! relocate)
10636 return bfd_reloc_ok;
9a5aca8c 10637
f21f3fe0 10638 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10639 contents, rel->r_offset,
10640 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10641 }
10642 else switch (r_type)
10643 {
00a97672
RS		 10644 case R_ARM_ABS12:
10645 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10646
dfc5f959 10647 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10648 case R_ARM_CALL:
10649 case R_ARM_JUMP24:
8029a119 10650 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10651 case R_ARM_PLT32:
906e58ca 10652 {
906e58ca
NC		 10653 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10654
dfc5f959 10655 if (r_type == R_ARM_XPC25)
252b5132 10656 {
dfc5f959
NC		 10657 /* Check for Arm calling Arm function. */
10658 /* FIXME: Should we translate the instruction into a BL
10659 instruction instead ? */
35fc36a8 10660 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10661 _bfd_error_handler
90b6238f
AM		 10662 (_("\%pB: warning: %s BLX instruction targets"
10663 " %s function '%s'"),
10664 input_bfd, "ARM",
10665 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10666 }
155d87d7 10667 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10668 {
10669 /* Check for Arm calling Thumb function. */
35fc36a8 10670 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10671 {
f2a9dd69
DJ		 10672 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10673 output_bfd, input_section,
10674 hit_data, sym_sec, rel->r_offset,
10675 signed_addend, value,
10676 error_message))
10677 return bfd_reloc_ok;
10678 else
10679 return bfd_reloc_dangerous;
dfc5f959 10680 }
252b5132 10681 }
ba96a88f 10682
906e58ca 10683 /* Check if a stub has to be inserted because the
8029a119 10684 destination is too far or we are changing mode. */
155d87d7
CL		 10685 if ( r_type == R_ARM_CALL
10686 || r_type == R_ARM_JUMP24
10687 || r_type == R_ARM_PLT32)
906e58ca 10688 {
fe33d2fa
CL		 10689 enum elf32_arm_stub_type stub_type = arm_stub_none;
10690 struct elf32_arm_link_hash_entry *hash;
10691
10692 hash = (struct elf32_arm_link_hash_entry *) h;
10693 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10694 st_type, &branch_type,
10695 hash, value, sym_sec,
fe33d2fa 10696 input_bfd, sym_name);
5fa9e92f 10697
fe33d2fa 10698 if (stub_type != arm_stub_none)
906e58ca
NC		 10699 {
10700 /* The target is out of reach, so redirect the
10701 branch to the local stub for this function. */
906e58ca
NC		 10702 stub_entry = elf32_arm_get_stub_entry (input_section,
10703 sym_sec, h,
fe33d2fa
CL		 10704 rel, globals,
10705 stub_type);
9cd3e4e5
NC		 10706 {
10707 if (stub_entry != NULL)
10708 value = (stub_entry->stub_offset
10709 + stub_entry->stub_sec->output_offset
10710 + stub_entry->stub_sec->output_section->vma);
10711
10712 if (plt_offset != (bfd_vma) -1)
10713 *unresolved_reloc_p = FALSE;
10714 }
906e58ca 10715 }
fe33d2fa
CL		 10716 else
10717 {
10718 /* If the call goes through a PLT entry, make sure to
10719 check distance to the right destination address. */
34e77a92 10720 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10721 {
10722 value = (splt->output_section->vma
10723 + splt->output_offset
34e77a92 10724 + plt_offset);
fe33d2fa
CL		 10725 *unresolved_reloc_p = FALSE;
10726 /* The PLT entry is in ARM mode, regardless of the
10727 target function. */
35fc36a8 10728 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10729 }
10730 }
906e58ca
NC		 10731 }
10732
dea514f5
PB		 10733 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10734 where:
10735 S is the address of the symbol in the relocation.
10736 P is address of the instruction being relocated.
10737 A is the addend (extracted from the instruction) in bytes.
10738
10739 S is held in 'value'.
10740 P is the base address of the section containing the
10741 instruction plus the offset of the reloc into that
10742 section, ie:
10743 (input_section->output_section->vma +
10744 input_section->output_offset +
10745 rel->r_offset).
10746 A is the addend, converted into bytes, ie:
10747 (signed_addend * 4)
10748
10749 Note: None of these operations have knowledge of the pipeline
10750 size of the processor, thus it is up to the assembler to
10751 encode this information into the addend. */
10752 value -= (input_section->output_section->vma
10753 + input_section->output_offset);
10754 value -= rel->r_offset;
4e7fd91e
PB		 10755 if (globals->use_rel)
10756 value += (signed_addend << howto->size);
10757 else
10758 /* RELA addends do not have to be adjusted by howto->size. */
10759 value += signed_addend;
23080146 10760
dcb5e6e6
NC		 10761 signed_addend = value;
10762 signed_addend >>= howto->rightshift;
9a5aca8c 10763
5ab79981 10764 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10765 the next instruction unless a PLT entry will be created.
77b4f08f 10766 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10767 The jump to the next instruction is optimized as a NOP depending
10768 on the architecture. */
ffcb4889 10769 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10770 && plt_offset == (bfd_vma) -1)
77b4f08f 10771 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10772 {
cd1dac3d
DG		 10773 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10774
10775 if (arch_has_arm_nop (globals))
10776 value |= 0x0320f000;
10777 else
10778 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10779 }
10780 else
59f2c4e7 10781 {
9b485d32 10782 /* Perform a signed range check. */
dcb5e6e6 10783 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10784 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10785 return bfd_reloc_overflow;
9a5aca8c 10786
5ab79981 10787 addend = (value & 2);
39b41c9c 10788
5ab79981
PB		 10789 value = (signed_addend & howto->dst_mask)
10790 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10791
5ab79981
PB		 10792 if (r_type == R_ARM_CALL)
10793 {
155d87d7 10794 /* Set the H bit in the BLX instruction. */
35fc36a8 10795 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10796 {
10797 if (addend)
10798 value |= (1 << 24);
10799 else
10800 value &= ~(bfd_vma)(1 << 24);
10801 }
10802
5ab79981 10803 /* Select the correct instruction (BL or BLX). */
906e58ca 10804 /* Only if we are not handling a BL to a stub. In this
8029a119 10805 case, mode switching is performed by the stub. */
35fc36a8 10806 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10807 value |= (1 << 28);
63e1a0fc 10808 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10809 {
10810 value &= ~(bfd_vma)(1 << 28);
10811 value |= (1 << 24);
10812 }
39b41c9c
PB		 10813 }
10814 }
906e58ca 10815 }
252b5132 10816 break;
f21f3fe0 10817
252b5132
RH		 10818 case R_ARM_ABS32:
10819 value += addend;
35fc36a8 10820 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10821 value |= 1;
10822 break;
f21f3fe0 10823
bb224fc3
MS		 10824 case R_ARM_ABS32_NOI:
10825 value += addend;
10826 break;
10827
252b5132 10828 case R_ARM_REL32:
a8bc6c78 10829 value += addend;
35fc36a8 10830 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10831 value |= 1;
252b5132 10832 value -= (input_section->output_section->vma
62efb346 10833 + input_section->output_offset + rel->r_offset);
252b5132 10834 break;
eb043451 10835
bb224fc3
MS		 10836 case R_ARM_REL32_NOI:
10837 value += addend;
10838 value -= (input_section->output_section->vma
10839 + input_section->output_offset + rel->r_offset);
10840 break;
10841
eb043451
PB		 10842 case R_ARM_PREL31:
10843 value -= (input_section->output_section->vma
10844 + input_section->output_offset + rel->r_offset);
10845 value += signed_addend;
10846 if (! h || h->root.type != bfd_link_hash_undefweak)
10847 {
8029a119 10848 /* Check for overflow. */
eb043451
PB		 10849 if ((value ^ (value >> 1)) & (1 << 30))
10850 return bfd_reloc_overflow;
10851 }
10852 value &= 0x7fffffff;
10853 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10854 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10855 value |= 1;
10856 break;
252b5132 10857 }
f21f3fe0 10858
252b5132
RH		 10859 bfd_put_32 (input_bfd, value, hit_data);
10860 return bfd_reloc_ok;
10861
10862 case R_ARM_ABS8:
fd0fd00c
MJ		 10863 /* PR 16202: Refectch the addend using the correct size. */
10864 if (globals->use_rel)
10865 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10866 value += addend;
4e67d4ca
DG		 10867
10868 /* There is no way to tell whether the user intended to use a signed or
10869 unsigned addend. When checking for overflow we accept either,
10870 as specified by the AAELF. */
10871 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10872 return bfd_reloc_overflow;
10873
10874 bfd_put_8 (input_bfd, value, hit_data);
10875 return bfd_reloc_ok;
10876
10877 case R_ARM_ABS16:
fd0fd00c
MJ		 10878 /* PR 16202: Refectch the addend using the correct size. */
10879 if (globals->use_rel)
10880 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10881 value += addend;
10882
4e67d4ca
DG		 10883 /* See comment for R_ARM_ABS8. */
10884 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10885 return bfd_reloc_overflow;
10886
10887 bfd_put_16 (input_bfd, value, hit_data);
10888 return bfd_reloc_ok;
10889
252b5132 10890 case R_ARM_THM_ABS5:
9b485d32 10891 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10892 if (globals->use_rel)
10893 {
10894 /* Need to refetch addend. */
10895 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10896 /* ??? Need to determine shift amount from operand size. */
10897 addend >>= howto->rightshift;
10898 }
252b5132
RH		 10899 value += addend;
10900
10901 /* ??? Isn't value unsigned? */
10902 if ((long) value > 0x1f || (long) value < -0x10)
10903 return bfd_reloc_overflow;
10904
10905 /* ??? Value needs to be properly shifted into place first. */
10906 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10907 bfd_put_16 (input_bfd, value, hit_data);
10908 return bfd_reloc_ok;
10909
2cab6cc3
MS		 10910 case R_ARM_THM_ALU_PREL_11_0:
10911 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10912 {
10913 bfd_vma insn;
10914 bfd_signed_vma relocation;
10915
10916 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10917 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10918
99059e56
RM		 10919 if (globals->use_rel)
10920 {
10921 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10922 | ((insn & (1 << 26)) >> 15);
10923 if (insn & 0xf00000)
10924 signed_addend = -signed_addend;
10925 }
2cab6cc3
MS		 10926
10927 relocation = value + signed_addend;
79f08007 10928 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10929 + input_section->output_offset
10930 + rel->r_offset);
2cab6cc3 10931
8c65b54f
CS		 10932 /* PR 21523: Use an absolute value. The user of this reloc will
10933 have already selected an ADD or SUB insn appropriately. */
453f8e1e 10934 value = llabs (relocation);
2cab6cc3 10935
99059e56
RM		 10936 if (value >= 0x1000)
10937 return bfd_reloc_overflow;
2cab6cc3 10938
e645cf40
AG		 10939 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10940 if (branch_type == ST_BRANCH_TO_THUMB)
10941 value |= 1;
10942
2cab6cc3 10943 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10944 | ((value & 0x700) << 4)
10945 | ((value & 0x800) << 15);
10946 if (relocation < 0)
10947 insn |= 0xa00000;
2cab6cc3
MS		 10948
10949 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10950 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10951
99059e56 10952 return bfd_reloc_ok;
2cab6cc3
MS		 10953 }
10954
e1ec24c6
NC		 10955 case R_ARM_THM_PC8:
10956 /* PR 10073: This reloc is not generated by the GNU toolchain,
10957 but it is supported for compatibility with third party libraries
10958 generated by other compilers, specifically the ARM/IAR. */
10959 {
10960 bfd_vma insn;
10961 bfd_signed_vma relocation;
10962
10963 insn = bfd_get_16 (input_bfd, hit_data);
10964
99059e56 10965 if (globals->use_rel)
79f08007 10966 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10967
10968 relocation = value + addend;
79f08007 10969 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10970 + input_section->output_offset
10971 + rel->r_offset);
e1ec24c6 10972
b6518b38 10973 value = relocation;
e1ec24c6
NC		 10974
10975 /* We do not check for overflow of this reloc. Although strictly
10976 speaking this is incorrect, it appears to be necessary in order
10977 to work with IAR generated relocs. Since GCC and GAS do not
10978 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10979 a problem for them. */
10980 value &= 0x3fc;
10981
10982 insn = (insn & 0xff00) | (value >> 2);
10983
10984 bfd_put_16 (input_bfd, insn, hit_data);
10985
99059e56 10986 return bfd_reloc_ok;
e1ec24c6
NC		 10987 }
10988
2cab6cc3
MS		 10989 case R_ARM_THM_PC12:
10990 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10991 {
10992 bfd_vma insn;
10993 bfd_signed_vma relocation;
10994
10995 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10996 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10997
99059e56
RM		 10998 if (globals->use_rel)
10999 {
11000 signed_addend = insn & 0xfff;
11001 if (!(insn & (1 << 23)))
11002 signed_addend = -signed_addend;
11003 }
2cab6cc3
MS		 11004
11005 relocation = value + signed_addend;
79f08007 11006 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11007 + input_section->output_offset
11008 + rel->r_offset);
2cab6cc3 11009
b6518b38 11010 value = relocation;
2cab6cc3 11011
99059e56
RM		 11012 if (value >= 0x1000)
11013 return bfd_reloc_overflow;
2cab6cc3
MS		 11014
11015 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 11016 if (relocation >= 0)
11017 insn |= (1 << 23);
2cab6cc3
MS		 11018
11019 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11020 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11021
99059e56 11022 return bfd_reloc_ok;
2cab6cc3
MS		 11023 }
11024
dfc5f959 11025 case R_ARM_THM_XPC22:
c19d1205 11026 case R_ARM_THM_CALL:
bd97cb95 11027 case R_ARM_THM_JUMP24:
dfc5f959 11028 /* Thumb BL (branch long instruction). */
252b5132 11029 {
b34976b6 11030 bfd_vma relocation;
99059e56 11031 bfd_vma reloc_sign;
b34976b6
AM		 11032 bfd_boolean overflow = FALSE;
11033 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11034 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 11035 bfd_signed_vma reloc_signed_max;
11036 bfd_signed_vma reloc_signed_min;
b34976b6 11037 bfd_vma check;
252b5132 11038 bfd_signed_vma signed_check;
e95de063 11039 int bitsize;
cd1dac3d 11040 const int thumb2 = using_thumb2 (globals);
5e866f5a 11041 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 11042
5ab79981 11043 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 11044 the next instruction unless a PLT entry will be created.
11045 The jump to the next instruction is optimized as a NOP.W for
11046 Thumb-2 enabled architectures. */
19540007 11047 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 11048 && plt_offset == (bfd_vma) -1)
5ab79981 11049 {
60a019a0 11050 if (thumb2)
cd1dac3d
DG		 11051 {
11052 bfd_put_16 (input_bfd, 0xf3af, hit_data);
11053 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
11054 }
11055 else
11056 {
11057 bfd_put_16 (input_bfd, 0xe000, hit_data);
11058 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11059 }
5ab79981
PB		 11060 return bfd_reloc_ok;
11061 }
11062
e95de063 11063 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 11064 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 11065 if (globals->use_rel)
11066 {
99059e56
RM		 11067 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11068 bfd_vma upper = upper_insn & 0x3ff;
11069 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 11070 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11071 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 11072 bfd_vma i1 = j1 ^ s ? 0 : 1;
11073 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 11074
99059e56
RM		 11075 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11076 /* Sign extend. */
11077 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 11078
4e7fd91e
PB		 11079 signed_addend = addend;
11080 }
cb1afa5c 11081
dfc5f959
NC		 11082 if (r_type == R_ARM_THM_XPC22)
11083 {
11084 /* Check for Thumb to Thumb call. */
11085 /* FIXME: Should we translate the instruction into a BL
11086 instruction instead ? */
35fc36a8 11087 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 11088 _bfd_error_handler
90b6238f
AM		 11089 (_("%pB: warning: %s BLX instruction targets"
11090 " %s function '%s'"),
11091 input_bfd, "Thumb",
11092 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 11093 }
11094 else
252b5132 11095 {
dfc5f959
NC		 11096 /* If it is not a call to Thumb, assume call to Arm.
11097 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 11098 function call at all, but rather a long jump. Calls through
11099 the PLT do not require stubs. */
34e77a92 11100 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 11101 {
bd97cb95 11102 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11103 {
11104 /* Convert BL to BLX. */
11105 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11106 }
155d87d7
CL		 11107 else if (( r_type != R_ARM_THM_CALL)
11108 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 11109 {
11110 if (elf32_thumb_to_arm_stub
11111 (info, sym_name, input_bfd, output_bfd, input_section,
11112 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11113 error_message))
11114 return bfd_reloc_ok;
11115 else
11116 return bfd_reloc_dangerous;
11117 }
da5938a2 11118 }
35fc36a8
RS		 11119 else if (branch_type == ST_BRANCH_TO_THUMB
11120 && globals->use_blx
bd97cb95 11121 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11122 {
11123 /* Make sure this is a BL. */
11124 lower_insn |= 0x1800;
11125 }
252b5132 11126 }
f21f3fe0 11127
fe33d2fa 11128 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 11129 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 11130 {
11131 /* Check if a stub has to be inserted because the destination
8029a119 11132 is too far. */
fe33d2fa
CL		 11133 struct elf32_arm_stub_hash_entry *stub_entry;
11134 struct elf32_arm_link_hash_entry *hash;
11135
11136 hash = (struct elf32_arm_link_hash_entry *) h;
11137
11138 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 11139 st_type, &branch_type,
11140 hash, value, sym_sec,
fe33d2fa
CL		 11141 input_bfd, sym_name);
11142
11143 if (stub_type != arm_stub_none)
906e58ca
NC		 11144 {
11145 /* The target is out of reach or we are changing modes, so
11146 redirect the branch to the local stub for this
11147 function. */
11148 stub_entry = elf32_arm_get_stub_entry (input_section,
11149 sym_sec, h,
fe33d2fa
CL		 11150 rel, globals,
11151 stub_type);
906e58ca 11152 if (stub_entry != NULL)
9cd3e4e5
NC		 11153 {
11154 value = (stub_entry->stub_offset
11155 + stub_entry->stub_sec->output_offset
11156 + stub_entry->stub_sec->output_section->vma);
11157
11158 if (plt_offset != (bfd_vma) -1)
11159 *unresolved_reloc_p = FALSE;
11160 }
906e58ca 11161
f4ac8484 11162 /* If this call becomes a call to Arm, force BLX. */
155d87d7 11163 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 11164 {
11165 if ((stub_entry
11166 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 11167 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 11168 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11169 }
906e58ca
NC		 11170 }
11171 }
11172
fe33d2fa 11173 /* Handle calls via the PLT. */
34e77a92 11174 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 11175 {
11176 value = (splt->output_section->vma
11177 + splt->output_offset
34e77a92 11178 + plt_offset);
fe33d2fa 11179
eed94f8f
NC		 11180 if (globals->use_blx
11181 && r_type == R_ARM_THM_CALL
11182 && ! using_thumb_only (globals))
fe33d2fa
CL		 11183 {
11184 /* If the Thumb BLX instruction is available, convert
11185 the BL to a BLX instruction to call the ARM-mode
11186 PLT entry. */
11187 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 11188 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 11189 }
11190 else
11191 {
eed94f8f
NC		 11192 if (! using_thumb_only (globals))
11193 /* Target the Thumb stub before the ARM PLT entry. */
11194 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 11195 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 11196 }
11197 *unresolved_reloc_p = FALSE;
11198 }
11199
ba96a88f 11200 relocation = value + signed_addend;
f21f3fe0 11201
252b5132 11202 relocation -= (input_section->output_section->vma
ba96a88f
NC		 11203 + input_section->output_offset
11204 + rel->r_offset);
9a5aca8c 11205
252b5132
RH		 11206 check = relocation >> howto->rightshift;
11207
11208 /* If this is a signed value, the rightshift just dropped
11209 leading 1 bits (assuming twos complement). */
11210 if ((bfd_signed_vma) relocation >= 0)
11211 signed_check = check;
11212 else
11213 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11214
e95de063
MS		 11215 /* Calculate the permissable maximum and minimum values for
11216 this relocation according to whether we're relocating for
11217 Thumb-2 or not. */
11218 bitsize = howto->bitsize;
5e866f5a 11219 if (!thumb2_bl)
e95de063 11220 bitsize -= 2;
f6ebfac0 11221 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 11222 reloc_signed_min = ~reloc_signed_max;
11223
252b5132 11224 /* Assumes two's complement. */
ba96a88f 11225 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 11226 overflow = TRUE;
252b5132 11227
bd97cb95 11228 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 11229 /* For a BLX instruction, make sure that the relocation is rounded up
11230 to a word boundary. This follows the semantics of the instruction
11231 which specifies that bit 1 of the target address will come from bit
11232 1 of the base address. */
11233 relocation = (relocation + 2) & ~ 3;
cb1afa5c 11234
e95de063
MS		 11235 /* Put RELOCATION back into the insn. Assumes two's complement.
11236 We use the Thumb-2 encoding, which is safe even if dealing with
11237 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 11238 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 11239 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 11240 | ((relocation >> 12) & 0x3ff)
11241 | (reloc_sign << 10);
906e58ca 11242 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 11243 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11244 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11245 | ((relocation >> 1) & 0x7ff);
c62e1cc3 11246
252b5132
RH		 11247 /* Put the relocated value back in the object file: */
11248 bfd_put_16 (input_bfd, upper_insn, hit_data);
11249 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11250
11251 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11252 }
11253 break;
11254
c19d1205
ZW		 11255 case R_ARM_THM_JUMP19:
11256 /* Thumb32 conditional branch instruction. */
11257 {
11258 bfd_vma relocation;
11259 bfd_boolean overflow = FALSE;
11260 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11261 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 11262 bfd_signed_vma reloc_signed_max = 0xffffe;
11263 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 11264 bfd_signed_vma signed_check;
07d6d2b8 11265 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 11266 struct elf32_arm_stub_hash_entry *stub_entry;
11267 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 11268
11269 /* Need to refetch the addend, reconstruct the top three bits,
11270 and squish the two 11 bit pieces together. */
11271 if (globals->use_rel)
11272 {
11273 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 11274 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 11275 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11276 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11277 bfd_vma lower = (lower_insn & 0x07ff);
11278
a00a1f35
MS		 11279 upper |= J1 << 6;
11280 upper |= J2 << 7;
11281 upper |= (!S) << 8;
c19d1205
ZW		 11282 upper -= 0x0100; /* Sign extend. */
11283
11284 addend = (upper << 12) | (lower << 1);
11285 signed_addend = addend;
11286 }
11287
bd97cb95 11288 /* Handle calls via the PLT. */
34e77a92 11289 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 11290 {
11291 value = (splt->output_section->vma
11292 + splt->output_offset
34e77a92 11293 + plt_offset);
bd97cb95
DJ		 11294 /* Target the Thumb stub before the ARM PLT entry. */
11295 value -= PLT_THUMB_STUB_SIZE;
11296 *unresolved_reloc_p = FALSE;
11297 }
11298
c5423981
TG		 11299 hash = (struct elf32_arm_link_hash_entry *)h;
11300
11301 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 11302 st_type, &branch_type,
11303 hash, value, sym_sec,
11304 input_bfd, sym_name);
c5423981
TG		 11305 if (stub_type != arm_stub_none)
11306 {
11307 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 11308 sym_sec, h,
11309 rel, globals,
11310 stub_type);
c5423981
TG		 11311 if (stub_entry != NULL)
11312 {
07d6d2b8
AM		 11313 value = (stub_entry->stub_offset
11314 + stub_entry->stub_sec->output_offset
11315 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 11316 }
11317 }
c19d1205 11318
99059e56 11319 relocation = value + signed_addend;
c19d1205
ZW		 11320 relocation -= (input_section->output_section->vma
11321 + input_section->output_offset
11322 + rel->r_offset);
a00a1f35 11323 signed_check = (bfd_signed_vma) relocation;
c19d1205 11324
c19d1205
ZW		 11325 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11326 overflow = TRUE;
11327
11328 /* Put RELOCATION back into the insn. */
11329 {
11330 bfd_vma S = (relocation & 0x00100000) >> 20;
11331 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11332 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11333 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11334 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11335
a00a1f35 11336 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 11337 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11338 }
11339
11340 /* Put the relocated value back in the object file: */
11341 bfd_put_16 (input_bfd, upper_insn, hit_data);
11342 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11343
11344 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11345 }
11346
11347 case R_ARM_THM_JUMP11:
11348 case R_ARM_THM_JUMP8:
11349 case R_ARM_THM_JUMP6:
51c5503b
NC		 11350 /* Thumb B (branch) instruction). */
11351 {
6cf9e9fe 11352 bfd_signed_vma relocation;
51c5503b
NC		 11353 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11354 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11355 bfd_signed_vma signed_check;
11356
c19d1205
ZW		 11357 /* CZB cannot jump backward. */
11358 if (r_type == R_ARM_THM_JUMP6)
11359 reloc_signed_min = 0;
11360
4e7fd91e 11361 if (globals->use_rel)
6cf9e9fe 11362 {
4e7fd91e
PB		 11363 /* Need to refetch addend. */
11364 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
11365 if (addend & ((howto->src_mask + 1) >> 1))
11366 {
11367 signed_addend = -1;
11368 signed_addend &= ~ howto->src_mask;
11369 signed_addend |= addend;
11370 }
11371 else
11372 signed_addend = addend;
11373 /* The value in the insn has been right shifted. We need to
11374 undo this, so that we can perform the address calculation
11375 in terms of bytes. */
11376 signed_addend <<= howto->rightshift;
6cf9e9fe 11377 }
6cf9e9fe 11378 relocation = value + signed_addend;
51c5503b
NC		 11379
11380 relocation -= (input_section->output_section->vma
11381 + input_section->output_offset
11382 + rel->r_offset);
11383
6cf9e9fe
NC		 11384 relocation >>= howto->rightshift;
11385 signed_check = relocation;
c19d1205
ZW		 11386
11387 if (r_type == R_ARM_THM_JUMP6)
11388 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11389 else
11390 relocation &= howto->dst_mask;
51c5503b 11391 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11392
51c5503b
NC		 11393 bfd_put_16 (input_bfd, relocation, hit_data);
11394
11395 /* Assumes two's complement. */
11396 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11397 return bfd_reloc_overflow;
11398
11399 return bfd_reloc_ok;
11400 }
cedb70c5 11401
8375c36b
PB		 11402 case R_ARM_ALU_PCREL7_0:
11403 case R_ARM_ALU_PCREL15_8:
11404 case R_ARM_ALU_PCREL23_15:
11405 {
11406 bfd_vma insn;
11407 bfd_vma relocation;
11408
11409 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11410 if (globals->use_rel)
11411 {
11412 /* Extract the addend. */
11413 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11414 signed_addend = addend;
11415 }
8375c36b
PB		 11416 relocation = value + signed_addend;
11417
11418 relocation -= (input_section->output_section->vma
11419 + input_section->output_offset
11420 + rel->r_offset);
11421 insn = (insn & ~0xfff)
11422 | ((howto->bitpos << 7) & 0xf00)
11423 | ((relocation >> howto->bitpos) & 0xff);
11424 bfd_put_32 (input_bfd, value, hit_data);
11425 }
11426 return bfd_reloc_ok;
11427
252b5132
RH		 11428 case R_ARM_GNU_VTINHERIT:
11429 case R_ARM_GNU_VTENTRY:
11430 return bfd_reloc_ok;
11431
c19d1205 11432 case R_ARM_GOTOFF32:
252b5132 11433 /* Relocation is relative to the start of the
99059e56 11434 global offset table. */
252b5132
RH		 11435
11436 BFD_ASSERT (sgot != NULL);
11437 if (sgot == NULL)
99059e56 11438 return bfd_reloc_notsupported;
9a5aca8c 11439
cedb70c5 11440 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11441 address by one, so that attempts to call the function pointer will
11442 correctly interpret it as Thumb code. */
35fc36a8 11443 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11444 value += 1;
11445
252b5132 11446 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11447 calculation. We always want the start of .got. If we
11448 define _GLOBAL_OFFSET_TABLE in a different way, as is
11449 permitted by the ABI, we might have to change this
11450 calculation. */
252b5132 11451 value -= sgot->output_section->vma;
f21f3fe0 11452 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11453 contents, rel->r_offset, value,
00a97672 11454 rel->r_addend);
252b5132
RH		 11455
11456 case R_ARM_GOTPC:
a7c10850 11457 /* Use global offset table as symbol value. */
252b5132 11458 BFD_ASSERT (sgot != NULL);
f21f3fe0 11459
252b5132 11460 if (sgot == NULL)
99059e56 11461 return bfd_reloc_notsupported;
252b5132 11462
0945cdfd 11463 *unresolved_reloc_p = FALSE;
252b5132 11464 value = sgot->output_section->vma;
f21f3fe0 11465 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11466 contents, rel->r_offset, value,
00a97672 11467 rel->r_addend);
f21f3fe0 11468
252b5132 11469 case R_ARM_GOT32:
eb043451 11470 case R_ARM_GOT_PREL:
252b5132 11471 /* Relocation is to the entry for this symbol in the
99059e56 11472 global offset table. */
252b5132
RH		 11473 if (sgot == NULL)
11474 return bfd_reloc_notsupported;
f21f3fe0 11475
34e77a92
RS		 11476 if (dynreloc_st_type == STT_GNU_IFUNC
11477 && plt_offset != (bfd_vma) -1
11478 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11479 {
11480 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11481 symbol, and the relocation resolves directly to the runtime
11482 target rather than to the .iplt entry. This means that any
11483 .got entry would be the same value as the .igot.plt entry,
11484 so there's no point creating both. */
11485 sgot = globals->root.igotplt;
11486 value = sgot->output_offset + gotplt_offset;
11487 }
11488 else if (h != NULL)
252b5132
RH		 11489 {
11490 bfd_vma off;
f21f3fe0 11491
252b5132
RH		 11492 off = h->got.offset;
11493 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11494 if ((off & 1) != 0)
252b5132 11495 {
b436d854
RS		 11496 /* We have already processsed one GOT relocation against
11497 this symbol. */
11498 off &= ~1;
11499 if (globals->root.dynamic_sections_created
11500 && !SYMBOL_REFERENCES_LOCAL (info, h))
11501 *unresolved_reloc_p = FALSE;
11502 }
11503 else
11504 {
11505 Elf_Internal_Rela outrel;
e8b09b87 11506 int isrofixup = 0;
b436d854 11507
e8b09b87
CL		 11508 if (((h->dynindx != -1) || globals->fdpic_p)
11509 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11510 {
11511 /* If the symbol doesn't resolve locally in a static
11512 object, we have an undefined reference. If the
11513 symbol doesn't resolve locally in a dynamic object,
11514 it should be resolved by the dynamic linker. */
11515 if (globals->root.dynamic_sections_created)
11516 {
11517 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11518 *unresolved_reloc_p = FALSE;
11519 }
11520 else
11521 outrel.r_info = 0;
11522 outrel.r_addend = 0;
11523 }
252b5132
RH		 11524 else
11525 {
34e77a92 11526 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11527 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c 11528 else if (bfd_link_pic (info)
7f026732 11529 && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
99059e56
RM		 11530 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11531 else
2376f038
EB		 11532 {
11533 outrel.r_info = 0;
11534 if (globals->fdpic_p)
11535 isrofixup = 1;
11536 }
34e77a92 11537 outrel.r_addend = dynreloc_value;
b436d854 11538 }
ee29b9fb 11539
b436d854
RS		 11540 /* The GOT entry is initialized to zero by default.
11541 See if we should install a different value. */
11542 if (outrel.r_addend != 0
2376f038 11543 && (globals->use_rel || outrel.r_info == 0))
b436d854
RS		 11544 {
11545 bfd_put_32 (output_bfd, outrel.r_addend,
11546 sgot->contents + off);
11547 outrel.r_addend = 0;
252b5132 11548 }
f21f3fe0 11549
2376f038
EB		 11550 if (isrofixup)
11551 arm_elf_add_rofixup (output_bfd,
11552 elf32_arm_hash_table(info)->srofixup,
11553 sgot->output_section->vma
11554 + sgot->output_offset + off);
11555
11556 else if (outrel.r_info != 0)
b436d854
RS		 11557 {
11558 outrel.r_offset = (sgot->output_section->vma
11559 + sgot->output_offset
11560 + off);
11561 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11562 }
2376f038 11563
b436d854
RS		 11564 h->got.offset |= 1;
11565 }
252b5132
RH		 11566 value = sgot->output_offset + off;
11567 }
11568 else
11569 {
11570 bfd_vma off;
f21f3fe0 11571
5025eb7c
AO		 11572 BFD_ASSERT (local_got_offsets != NULL
11573 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11574
252b5132 11575 off = local_got_offsets[r_symndx];
f21f3fe0 11576
252b5132
RH		 11577 /* The offset must always be a multiple of 4. We use the
11578 least significant bit to record whether we have already
9b485d32 11579 generated the necessary reloc. */
252b5132
RH		 11580 if ((off & 1) != 0)
11581 off &= ~1;
11582 else
11583 {
2376f038
EB		 11584 Elf_Internal_Rela outrel;
11585 int isrofixup = 0;
f21f3fe0 11586
2376f038
EB		 11587 if (dynreloc_st_type == STT_GNU_IFUNC)
11588 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11589 else if (bfd_link_pic (info))
11590 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11591 else
252b5132 11592 {
2376f038
EB		 11593 outrel.r_info = 0;
11594 if (globals->fdpic_p)
11595 isrofixup = 1;
11596 }
11597
11598 /* The GOT entry is initialized to zero by default.
11599 See if we should install a different value. */
11600 if (globals->use_rel || outrel.r_info == 0)
11601 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
11602
11603 if (isrofixup)
11604 arm_elf_add_rofixup (output_bfd,
11605 globals->srofixup,
11606 sgot->output_section->vma
11607 + sgot->output_offset + off);
f21f3fe0 11608
2376f038
EB		 11609 else if (outrel.r_info != 0)
11610 {
34e77a92 11611 outrel.r_addend = addend + dynreloc_value;
252b5132 11612 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11613 + sgot->output_offset
252b5132 11614 + off);
47beaa6a 11615 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11616 }
f21f3fe0 11617
252b5132
RH		 11618 local_got_offsets[r_symndx] |= 1;
11619 }
f21f3fe0 11620
252b5132
RH		 11621 value = sgot->output_offset + off;
11622 }
eb043451
PB		 11623 if (r_type != R_ARM_GOT32)
11624 value += sgot->output_section->vma;
9a5aca8c 11625
f21f3fe0 11626 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11627 contents, rel->r_offset, value,
00a97672 11628 rel->r_addend);
f21f3fe0 11629
ba93b8ac
DJ		 11630 case R_ARM_TLS_LDO32:
11631 value = value - dtpoff_base (info);
11632
11633 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11634 contents, rel->r_offset, value,
11635 rel->r_addend);
ba93b8ac
DJ		 11636
11637 case R_ARM_TLS_LDM32:
5c5a4843 11638 case R_ARM_TLS_LDM32_FDPIC:
ba93b8ac
DJ		 11639 {
11640 bfd_vma off;
11641
362d30a1 11642 if (sgot == NULL)
ba93b8ac
DJ		 11643 abort ();
11644
11645 off = globals->tls_ldm_got.offset;
11646
11647 if ((off & 1) != 0)
11648 off &= ~1;
11649 else
11650 {
11651 /* If we don't know the module number, create a relocation
11652 for it. */
9cb09e33 11653 if (bfd_link_dll (info))
ba93b8ac
DJ		 11654 {
11655 Elf_Internal_Rela outrel;
ba93b8ac 11656
362d30a1 11657 if (srelgot == NULL)
ba93b8ac
DJ		 11658 abort ();
11659
00a97672 11660 outrel.r_addend = 0;
362d30a1
RS		 11661 outrel.r_offset = (sgot->output_section->vma
11662 + sgot->output_offset + off);
ba93b8ac
DJ		 11663 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11664
00a97672
RS		 11665 if (globals->use_rel)
11666 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11667 sgot->contents + off);
ba93b8ac 11668
47beaa6a 11669 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11670 }
11671 else
362d30a1 11672 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11673
11674 globals->tls_ldm_got.offset |= 1;
11675 }
11676
5c5a4843 11677 if (r_type == R_ARM_TLS_LDM32_FDPIC)
e8b09b87
CL		 11678 {
11679 bfd_put_32(output_bfd,
11680 globals->root.sgot->output_offset + off,
11681 contents + rel->r_offset);
11682
11683 return bfd_reloc_ok;
11684 }
11685 else
11686 {
11687 value = sgot->output_section->vma + sgot->output_offset + off
11688 - (input_section->output_section->vma
11689 + input_section->output_offset + rel->r_offset);
ba93b8ac 11690
e8b09b87
CL		 11691 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11692 contents, rel->r_offset, value,
11693 rel->r_addend);
11694 }
ba93b8ac
DJ		 11695 }
11696
0855e32b
NS		 11697 case R_ARM_TLS_CALL:
11698 case R_ARM_THM_TLS_CALL:
ba93b8ac 11699 case R_ARM_TLS_GD32:
5c5a4843 11700 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 11701 case R_ARM_TLS_IE32:
5c5a4843 11702 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 11703 case R_ARM_TLS_GOTDESC:
11704 case R_ARM_TLS_DESCSEQ:
11705 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11706 {
0855e32b
NS		 11707 bfd_vma off, offplt;
11708 int indx = 0;
ba93b8ac
DJ		 11709 char tls_type;
11710
0855e32b 11711 BFD_ASSERT (sgot != NULL);
ba93b8ac 11712
ba93b8ac
DJ		 11713 if (h != NULL)
11714 {
11715 bfd_boolean dyn;
11716 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11717 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11718 bfd_link_pic (info),
11719 h)
11720 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11721 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11722 {
11723 *unresolved_reloc_p = FALSE;
11724 indx = h->dynindx;
11725 }
11726 off = h->got.offset;
0855e32b 11727 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11728 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11729 }
11730 else
11731 {
0855e32b 11732 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11733 off = local_got_offsets[r_symndx];
0855e32b 11734 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11735 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11736 }
11737
0855e32b 11738 /* Linker relaxations happens from one of the
b38cadfb 11739 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11740 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11741 tls_type = GOT_TLS_IE;
0855e32b
NS		 11742
11743 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11744
11745 if ((off & 1) != 0)
11746 off &= ~1;
11747 else
11748 {
11749 bfd_boolean need_relocs = FALSE;
11750 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11751 int cur_off = off;
11752
11753 /* The GOT entries have not been initialized yet. Do it
11754 now, and emit any relocations. If both an IE GOT and a
11755 GD GOT are necessary, we emit the GD first. */
11756
9cb09e33 11757 if ((bfd_link_dll (info) || indx != 0)
ba93b8ac 11758 && (h == NULL
95b03e4a
L		 11759 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11760 && !resolved_to_zero)
ba93b8ac
DJ		 11761 || h->root.type != bfd_link_hash_undefweak))
11762 {
11763 need_relocs = TRUE;
0855e32b 11764 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11765 }
11766
0855e32b
NS		 11767 if (tls_type & GOT_TLS_GDESC)
11768 {
47beaa6a
RS		 11769 bfd_byte *loc;
11770
0855e32b
NS		 11771 /* We should have relaxed, unless this is an undefined
11772 weak symbol. */
11773 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
9cb09e33 11774 || bfd_link_dll (info));
0855e32b 11775 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11776 <= globals->root.sgotplt->size);
0855e32b
NS		 11777
11778 outrel.r_addend = 0;
11779 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11780 + globals->root.sgotplt->output_offset
11781 + offplt
11782 + globals->sgotplt_jump_table_size);
b38cadfb 11783
0855e32b
NS		 11784 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11785 sreloc = globals->root.srelplt;
11786 loc = sreloc->contents;
11787 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11788 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11789 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11790
11791 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11792
11793 /* For globals, the first word in the relocation gets
11794 the relocation index and the top bit set, or zero,
11795 if we're binding now. For locals, it gets the
11796 symbol's offset in the tls section. */
99059e56 11797 bfd_put_32 (output_bfd,
0855e32b
NS		 11798 !h ? value - elf_hash_table (info)->tls_sec->vma
11799 : info->flags & DF_BIND_NOW ? 0
11800 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11801 globals->root.sgotplt->contents + offplt
11802 + globals->sgotplt_jump_table_size);
11803
0855e32b 11804 /* Second word in the relocation is always zero. */
99059e56 11805 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11806 globals->root.sgotplt->contents + offplt
11807 + globals->sgotplt_jump_table_size + 4);
0855e32b 11808 }
ba93b8ac
DJ		 11809 if (tls_type & GOT_TLS_GD)
11810 {
11811 if (need_relocs)
11812 {
00a97672 11813 outrel.r_addend = 0;
362d30a1
RS		 11814 outrel.r_offset = (sgot->output_section->vma
11815 + sgot->output_offset
00a97672 11816 + cur_off);
ba93b8ac 11817 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11818
00a97672
RS		 11819 if (globals->use_rel)
11820 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11821 sgot->contents + cur_off);
00a97672 11822
47beaa6a 11823 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11824
11825 if (indx == 0)
11826 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11827 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11828 else
11829 {
00a97672 11830 outrel.r_addend = 0;
ba93b8ac
DJ		 11831 outrel.r_info = ELF32_R_INFO (indx,
11832 R_ARM_TLS_DTPOFF32);
11833 outrel.r_offset += 4;
00a97672
RS		 11834
11835 if (globals->use_rel)
11836 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11837 sgot->contents + cur_off + 4);
00a97672 11838
47beaa6a
RS		 11839 elf32_arm_add_dynreloc (output_bfd, info,
11840 srelgot, &outrel);
ba93b8ac
DJ		 11841 }
11842 }
11843 else
11844 {
11845 /* If we are not emitting relocations for a
11846 general dynamic reference, then we must be in a
11847 static link or an executable link with the
11848 symbol binding locally. Mark it as belonging
11849 to module 1, the executable. */
11850 bfd_put_32 (output_bfd, 1,
362d30a1 11851 sgot->contents + cur_off);
ba93b8ac 11852 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11853 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11854 }
11855
11856 cur_off += 8;
11857 }
11858
11859 if (tls_type & GOT_TLS_IE)
11860 {
11861 if (need_relocs)
11862 {
00a97672
RS		 11863 if (indx == 0)
11864 outrel.r_addend = value - dtpoff_base (info);
11865 else
11866 outrel.r_addend = 0;
362d30a1
RS		 11867 outrel.r_offset = (sgot->output_section->vma
11868 + sgot->output_offset
ba93b8ac
DJ		 11869 + cur_off);
11870 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11871
00a97672
RS		 11872 if (globals->use_rel)
11873 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11874 sgot->contents + cur_off);
ba93b8ac 11875
47beaa6a 11876 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11877 }
11878 else
11879 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11880 sgot->contents + cur_off);
ba93b8ac
DJ		 11881 cur_off += 4;
11882 }
11883
11884 if (h != NULL)
11885 h->got.offset |= 1;
11886 else
11887 local_got_offsets[r_symndx] |= 1;
11888 }
11889
5c5a4843 11890 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
ba93b8ac 11891 off += 8;
0855e32b
NS		 11892 else if (tls_type & GOT_TLS_GDESC)
11893 off = offplt;
11894
11895 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11896 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11897 {
11898 bfd_signed_vma offset;
12352d3f
PB		 11899 /* TLS stubs are arm mode. The original symbol is a
11900 data object, so branch_type is bogus. */
11901 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11902 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11903 = arm_type_of_stub (info, input_section, rel,
11904 st_type, &branch_type,
0855e32b
NS		 11905 (struct elf32_arm_link_hash_entry *)h,
11906 globals->tls_trampoline, globals->root.splt,
11907 input_bfd, sym_name);
11908
11909 if (stub_type != arm_stub_none)
11910 {
11911 struct elf32_arm_stub_hash_entry *stub_entry
11912 = elf32_arm_get_stub_entry
11913 (input_section, globals->root.splt, 0, rel,
11914 globals, stub_type);
11915 offset = (stub_entry->stub_offset
11916 + stub_entry->stub_sec->output_offset
11917 + stub_entry->stub_sec->output_section->vma);
11918 }
11919 else
11920 offset = (globals->root.splt->output_section->vma
11921 + globals->root.splt->output_offset
11922 + globals->tls_trampoline);
11923
11924 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11925 {
11926 unsigned long inst;
b38cadfb
NC		 11927
11928 offset -= (input_section->output_section->vma
11929 + input_section->output_offset
11930 + rel->r_offset + 8);
0855e32b
NS		 11931
11932 inst = offset >> 2;
11933 inst &= 0x00ffffff;
11934 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11935 }
11936 else
11937 {
11938 /* Thumb blx encodes the offset in a complicated
11939 fashion. */
11940 unsigned upper_insn, lower_insn;
11941 unsigned neg;
11942
b38cadfb
NC		 11943 offset -= (input_section->output_section->vma
11944 + input_section->output_offset
0855e32b 11945 + rel->r_offset + 4);
b38cadfb 11946
12352d3f
PB		 11947 if (stub_type != arm_stub_none
11948 && arm_stub_is_thumb (stub_type))
11949 {
11950 lower_insn = 0xd000;
11951 }
11952 else
11953 {
11954 lower_insn = 0xc000;
6a631e86 11955 /* Round up the offset to a word boundary. */
12352d3f
PB		 11956 offset = (offset + 2) & ~2;
11957 }
11958
0855e32b
NS		 11959 neg = offset < 0;
11960 upper_insn = (0xf000
11961 | ((offset >> 12) & 0x3ff)
11962 | (neg << 10));
12352d3f 11963 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11964 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11965 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11966 bfd_put_16 (input_bfd, upper_insn, hit_data);
11967 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11968 return bfd_reloc_ok;
11969 }
11970 }
11971 /* These relocations needs special care, as besides the fact
11972 they point somewhere in .gotplt, the addend must be
11973 adjusted accordingly depending on the type of instruction
6a631e86 11974 we refer to. */
0855e32b
NS		 11975 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11976 {
11977 unsigned long data, insn;
11978 unsigned thumb;
b38cadfb 11979
b627f562 11980 data = bfd_get_signed_32 (input_bfd, hit_data);
0855e32b 11981 thumb = data & 1;
b627f562 11982 data &= ~1ul;
b38cadfb 11983
0855e32b
NS		 11984 if (thumb)
11985 {
11986 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11987 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11988 insn = (insn << 16)
11989 | bfd_get_16 (input_bfd,
11990 contents + rel->r_offset - data + 2);
11991 if ((insn & 0xf800c000) == 0xf000c000)
11992 /* bl/blx */
11993 value = -6;
11994 else if ((insn & 0xffffff00) == 0x4400)
11995 /* add */
11996 value = -5;
11997 else
11998 {
4eca0228 11999 _bfd_error_handler
695344c0 12000 /* xgettext:c-format */
2dcf00ce 12001 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12002 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12003 "referenced by TLS_GOTDESC"),
12004 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12005 "Thumb", insn);
0855e32b
NS		 12006 return bfd_reloc_notsupported;
12007 }
12008 }
12009 else
12010 {
12011 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
12012
12013 switch (insn >> 24)
12014 {
12015 case 0xeb: /* bl */
12016 case 0xfa: /* blx */
12017 value = -4;
12018 break;
12019
12020 case 0xe0: /* add */
12021 value = -8;
12022 break;
b38cadfb 12023
0855e32b 12024 default:
4eca0228 12025 _bfd_error_handler
695344c0 12026 /* xgettext:c-format */
2dcf00ce 12027 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12028 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12029 "referenced by TLS_GOTDESC"),
12030 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12031 "ARM", insn);
0855e32b
NS		 12032 return bfd_reloc_notsupported;
12033 }
12034 }
b38cadfb 12035
0855e32b
NS		 12036 value += ((globals->root.sgotplt->output_section->vma
12037 + globals->root.sgotplt->output_offset + off)
12038 - (input_section->output_section->vma
12039 + input_section->output_offset
12040 + rel->r_offset)
12041 + globals->sgotplt_jump_table_size);
12042 }
12043 else
12044 value = ((globals->root.sgot->output_section->vma
12045 + globals->root.sgot->output_offset + off)
12046 - (input_section->output_section->vma
12047 + input_section->output_offset + rel->r_offset));
ba93b8ac 12048
5c5a4843
CL		 12049 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
12050 r_type == R_ARM_TLS_IE32_FDPIC))
e8b09b87
CL		 12051 {
12052 /* For FDPIC relocations, resolve to the offset of the GOT
12053 entry from the start of GOT. */
12054 bfd_put_32(output_bfd,
12055 globals->root.sgot->output_offset + off,
12056 contents + rel->r_offset);
12057
12058 return bfd_reloc_ok;
12059 }
12060 else
12061 {
12062 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12063 contents, rel->r_offset, value,
12064 rel->r_addend);
12065 }
ba93b8ac
DJ		 12066 }
12067
12068 case R_ARM_TLS_LE32:
3cbc1e5e 12069 if (bfd_link_dll (info))
ba93b8ac 12070 {
4eca0228 12071 _bfd_error_handler
695344c0 12072 /* xgettext:c-format */
2dcf00ce
AM		 12073 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12074 "in shared object"),
12075 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 12076 return bfd_reloc_notsupported;
ba93b8ac
DJ		 12077 }
12078 else
12079 value = tpoff (info, value);
906e58ca 12080
ba93b8ac 12081 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 12082 contents, rel->r_offset, value,
12083 rel->r_addend);
ba93b8ac 12084
319850b4
JB		 12085 case R_ARM_V4BX:
12086 if (globals->fix_v4bx)
845b51d6
PB		 12087 {
12088 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 12089
845b51d6
PB		 12090 /* Ensure that we have a BX instruction. */
12091 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 12092
845b51d6
PB		 12093 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12094 {
12095 /* Branch to veneer. */
12096 bfd_vma glue_addr;
12097 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12098 glue_addr -= input_section->output_section->vma
12099 + input_section->output_offset
12100 + rel->r_offset + 8;
12101 insn = (insn & 0xf0000000) | 0x0a000000
12102 | ((glue_addr >> 2) & 0x00ffffff);
12103 }
12104 else
12105 {
12106 /* Preserve Rm (lowest four bits) and the condition code
12107 (highest four bits). Other bits encode MOV PC,Rm. */
12108 insn = (insn & 0xf000000f) | 0x01a0f000;
12109 }
319850b4 12110
845b51d6
PB		 12111 bfd_put_32 (input_bfd, insn, hit_data);
12112 }
319850b4
JB		 12113 return bfd_reloc_ok;
12114
b6895b4f
PB		 12115 case R_ARM_MOVW_ABS_NC:
12116 case R_ARM_MOVT_ABS:
12117 case R_ARM_MOVW_PREL_NC:
12118 case R_ARM_MOVT_PREL:
92f5d02b
MS		 12119 /* Until we properly support segment-base-relative addressing then
12120 we assume the segment base to be zero, as for the group relocations.
12121 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12122 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12123 case R_ARM_MOVW_BREL_NC:
12124 case R_ARM_MOVW_BREL:
12125 case R_ARM_MOVT_BREL:
b6895b4f
PB		 12126 {
12127 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12128
12129 if (globals->use_rel)
12130 {
12131 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 12132 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12133 }
92f5d02b 12134
b6895b4f 12135 value += signed_addend;
b6895b4f
PB		 12136
12137 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12138 value -= (input_section->output_section->vma
12139 + input_section->output_offset + rel->r_offset);
12140
92f5d02b 12141 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 12142 return bfd_reloc_overflow;
92f5d02b 12143
35fc36a8 12144 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12145 value |= 1;
12146
12147 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 12148 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 12149 value >>= 16;
12150
12151 insn &= 0xfff0f000;
12152 insn |= value & 0xfff;
12153 insn |= (value & 0xf000) << 4;
12154 bfd_put_32 (input_bfd, insn, hit_data);
12155 }
12156 return bfd_reloc_ok;
12157
12158 case R_ARM_THM_MOVW_ABS_NC:
12159 case R_ARM_THM_MOVT_ABS:
12160 case R_ARM_THM_MOVW_PREL_NC:
12161 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 12162 /* Until we properly support segment-base-relative addressing then
12163 we assume the segment base to be zero, as for the above relocations.
12164 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12165 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12166 as R_ARM_THM_MOVT_ABS. */
12167 case R_ARM_THM_MOVW_BREL_NC:
12168 case R_ARM_THM_MOVW_BREL:
12169 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 12170 {
12171 bfd_vma insn;
906e58ca 12172
b6895b4f
PB		 12173 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12174 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12175
12176 if (globals->use_rel)
12177 {
12178 addend = ((insn >> 4) & 0xf000)
12179 | ((insn >> 15) & 0x0800)
12180 | ((insn >> 4) & 0x0700)
07d6d2b8 12181 | (insn & 0x00ff);
39623e12 12182 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12183 }
92f5d02b 12184
b6895b4f 12185 value += signed_addend;
b6895b4f
PB		 12186
12187 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12188 value -= (input_section->output_section->vma
12189 + input_section->output_offset + rel->r_offset);
12190
92f5d02b 12191 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 12192 return bfd_reloc_overflow;
92f5d02b 12193
35fc36a8 12194 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12195 value |= 1;
12196
12197 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 12198 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 12199 value >>= 16;
12200
12201 insn &= 0xfbf08f00;
12202 insn |= (value & 0xf000) << 4;
12203 insn |= (value & 0x0800) << 15;
12204 insn |= (value & 0x0700) << 4;
12205 insn |= (value & 0x00ff);
12206
12207 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12208 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12209 }
12210 return bfd_reloc_ok;
12211
4962c51a
MS		 12212 case R_ARM_ALU_PC_G0_NC:
12213 case R_ARM_ALU_PC_G1_NC:
12214 case R_ARM_ALU_PC_G0:
12215 case R_ARM_ALU_PC_G1:
12216 case R_ARM_ALU_PC_G2:
12217 case R_ARM_ALU_SB_G0_NC:
12218 case R_ARM_ALU_SB_G1_NC:
12219 case R_ARM_ALU_SB_G0:
12220 case R_ARM_ALU_SB_G1:
12221 case R_ARM_ALU_SB_G2:
12222 {
12223 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12224 bfd_vma pc = input_section->output_section->vma
4962c51a 12225 + input_section->output_offset + rel->r_offset;
31a91d61 12226 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12227 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 12228 bfd_vma residual;
12229 bfd_vma g_n;
4962c51a 12230 bfd_signed_vma signed_value;
99059e56
RM		 12231 int group = 0;
12232
12233 /* Determine which group of bits to select. */
12234 switch (r_type)
12235 {
12236 case R_ARM_ALU_PC_G0_NC:
12237 case R_ARM_ALU_PC_G0:
12238 case R_ARM_ALU_SB_G0_NC:
12239 case R_ARM_ALU_SB_G0:
12240 group = 0;
12241 break;
12242
12243 case R_ARM_ALU_PC_G1_NC:
12244 case R_ARM_ALU_PC_G1:
12245 case R_ARM_ALU_SB_G1_NC:
12246 case R_ARM_ALU_SB_G1:
12247 group = 1;
12248 break;
12249
12250 case R_ARM_ALU_PC_G2:
12251 case R_ARM_ALU_SB_G2:
12252 group = 2;
12253 break;
12254
12255 default:
12256 abort ();
12257 }
12258
12259 /* If REL, extract the addend from the insn. If RELA, it will
12260 have already been fetched for us. */
4962c51a 12261 if (globals->use_rel)
99059e56
RM		 12262 {
12263 int negative;
12264 bfd_vma constant = insn & 0xff;
12265 bfd_vma rotation = (insn & 0xf00) >> 8;
12266
12267 if (rotation == 0)
12268 signed_addend = constant;
12269 else
12270 {
12271 /* Compensate for the fact that in the instruction, the
12272 rotation is stored in multiples of 2 bits. */
12273 rotation *= 2;
12274
12275 /* Rotate "constant" right by "rotation" bits. */
12276 signed_addend = (constant >> rotation) |
12277 (constant << (8 * sizeof (bfd_vma) - rotation));
12278 }
12279
12280 /* Determine if the instruction is an ADD or a SUB.
12281 (For REL, this determines the sign of the addend.) */
12282 negative = identify_add_or_sub (insn);
12283 if (negative == 0)
12284 {
4eca0228 12285 _bfd_error_handler
695344c0 12286 /* xgettext:c-format */
90b6238f 12287 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 12288 "are allowed for ALU group relocations"),
12289 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 12290 return bfd_reloc_overflow;
12291 }
12292
12293 signed_addend *= negative;
12294 }
4962c51a
MS		 12295
12296 /* Compute the value (X) to go in the place. */
99059e56
RM		 12297 if (r_type == R_ARM_ALU_PC_G0_NC
12298 || r_type == R_ARM_ALU_PC_G1_NC
12299 || r_type == R_ARM_ALU_PC_G0
12300 || r_type == R_ARM_ALU_PC_G1
12301 || r_type == R_ARM_ALU_PC_G2)
12302 /* PC relative. */
12303 signed_value = value - pc + signed_addend;
12304 else
12305 /* Section base relative. */
12306 signed_value = value - sb + signed_addend;
12307
12308 /* If the target symbol is a Thumb function, then set the
12309 Thumb bit in the address. */
35fc36a8 12310 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 12311 signed_value |= 1;
12312
99059e56
RM		 12313 /* Calculate the value of the relevant G_n, in encoded
12314 constant-with-rotation format. */
b6518b38
NC		 12315 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12316 group, &residual);
99059e56
RM		 12317
12318 /* Check for overflow if required. */
12319 if ((r_type == R_ARM_ALU_PC_G0
12320 || r_type == R_ARM_ALU_PC_G1
12321 || r_type == R_ARM_ALU_PC_G2
12322 || r_type == R_ARM_ALU_SB_G0
12323 || r_type == R_ARM_ALU_SB_G1
12324 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12325 {
4eca0228 12326 _bfd_error_handler
695344c0 12327 /* xgettext:c-format */
90b6238f 12328 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12329 "splitting %#" PRIx64 " for group relocation %s"),
12330 input_bfd, input_section, (uint64_t) rel->r_offset,
12331 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12332 howto->name);
99059e56
RM		 12333 return bfd_reloc_overflow;
12334 }
12335
12336 /* Mask out the value and the ADD/SUB part of the opcode; take care
12337 not to destroy the S bit. */
12338 insn &= 0xff1ff000;
12339
12340 /* Set the opcode according to whether the value to go in the
12341 place is negative. */
12342 if (signed_value < 0)
12343 insn |= 1 << 22;
12344 else
12345 insn |= 1 << 23;
12346
12347 /* Encode the offset. */
12348 insn |= g_n;
4962c51a
MS		 12349
12350 bfd_put_32 (input_bfd, insn, hit_data);
12351 }
12352 return bfd_reloc_ok;
12353
12354 case R_ARM_LDR_PC_G0:
12355 case R_ARM_LDR_PC_G1:
12356 case R_ARM_LDR_PC_G2:
12357 case R_ARM_LDR_SB_G0:
12358 case R_ARM_LDR_SB_G1:
12359 case R_ARM_LDR_SB_G2:
12360 {
12361 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12362 bfd_vma pc = input_section->output_section->vma
4962c51a 12363 + input_section->output_offset + rel->r_offset;
31a91d61 12364 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12365 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12366 bfd_vma residual;
4962c51a 12367 bfd_signed_vma signed_value;
99059e56
RM		 12368 int group = 0;
12369
12370 /* Determine which groups of bits to calculate. */
12371 switch (r_type)
12372 {
12373 case R_ARM_LDR_PC_G0:
12374 case R_ARM_LDR_SB_G0:
12375 group = 0;
12376 break;
12377
12378 case R_ARM_LDR_PC_G1:
12379 case R_ARM_LDR_SB_G1:
12380 group = 1;
12381 break;
12382
12383 case R_ARM_LDR_PC_G2:
12384 case R_ARM_LDR_SB_G2:
12385 group = 2;
12386 break;
12387
12388 default:
12389 abort ();
12390 }
12391
12392 /* If REL, extract the addend from the insn. If RELA, it will
12393 have already been fetched for us. */
4962c51a 12394 if (globals->use_rel)
99059e56
RM		 12395 {
12396 int negative = (insn & (1 << 23)) ? 1 : -1;
12397 signed_addend = negative * (insn & 0xfff);
12398 }
4962c51a
MS		 12399
12400 /* Compute the value (X) to go in the place. */
99059e56
RM		 12401 if (r_type == R_ARM_LDR_PC_G0
12402 || r_type == R_ARM_LDR_PC_G1
12403 || r_type == R_ARM_LDR_PC_G2)
12404 /* PC relative. */
12405 signed_value = value - pc + signed_addend;
12406 else
12407 /* Section base relative. */
12408 signed_value = value - sb + signed_addend;
12409
12410 /* Calculate the value of the relevant G_{n-1} to obtain
12411 the residual at that stage. */
b6518b38
NC		 12412 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12413 group - 1, &residual);
99059e56
RM		 12414
12415 /* Check for overflow. */
12416 if (residual >= 0x1000)
12417 {
4eca0228 12418 _bfd_error_handler
695344c0 12419 /* xgettext:c-format */
90b6238f 12420 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12421 "splitting %#" PRIx64 " for group relocation %s"),
12422 input_bfd, input_section, (uint64_t) rel->r_offset,
12423 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12424 howto->name);
99059e56
RM		 12425 return bfd_reloc_overflow;
12426 }
12427
12428 /* Mask out the value and U bit. */
12429 insn &= 0xff7ff000;
12430
12431 /* Set the U bit if the value to go in the place is non-negative. */
12432 if (signed_value >= 0)
12433 insn |= 1 << 23;
12434
12435 /* Encode the offset. */
12436 insn |= residual;
4962c51a
MS		 12437
12438 bfd_put_32 (input_bfd, insn, hit_data);
12439 }
12440 return bfd_reloc_ok;
12441
12442 case R_ARM_LDRS_PC_G0:
12443 case R_ARM_LDRS_PC_G1:
12444 case R_ARM_LDRS_PC_G2:
12445 case R_ARM_LDRS_SB_G0:
12446 case R_ARM_LDRS_SB_G1:
12447 case R_ARM_LDRS_SB_G2:
12448 {
12449 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12450 bfd_vma pc = input_section->output_section->vma
4962c51a 12451 + input_section->output_offset + rel->r_offset;
31a91d61 12452 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12453 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12454 bfd_vma residual;
4962c51a 12455 bfd_signed_vma signed_value;
99059e56
RM		 12456 int group = 0;
12457
12458 /* Determine which groups of bits to calculate. */
12459 switch (r_type)
12460 {
12461 case R_ARM_LDRS_PC_G0:
12462 case R_ARM_LDRS_SB_G0:
12463 group = 0;
12464 break;
12465
12466 case R_ARM_LDRS_PC_G1:
12467 case R_ARM_LDRS_SB_G1:
12468 group = 1;
12469 break;
12470
12471 case R_ARM_LDRS_PC_G2:
12472 case R_ARM_LDRS_SB_G2:
12473 group = 2;
12474 break;
12475
12476 default:
12477 abort ();
12478 }
12479
12480 /* If REL, extract the addend from the insn. If RELA, it will
12481 have already been fetched for us. */
4962c51a 12482 if (globals->use_rel)
99059e56
RM		 12483 {
12484 int negative = (insn & (1 << 23)) ? 1 : -1;
12485 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12486 }
4962c51a
MS		 12487
12488 /* Compute the value (X) to go in the place. */
99059e56
RM		 12489 if (r_type == R_ARM_LDRS_PC_G0
12490 || r_type == R_ARM_LDRS_PC_G1
12491 || r_type == R_ARM_LDRS_PC_G2)
12492 /* PC relative. */
12493 signed_value = value - pc + signed_addend;
12494 else
12495 /* Section base relative. */
12496 signed_value = value - sb + signed_addend;
12497
12498 /* Calculate the value of the relevant G_{n-1} to obtain
12499 the residual at that stage. */
b6518b38
NC		 12500 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12501 group - 1, &residual);
99059e56
RM		 12502
12503 /* Check for overflow. */
12504 if (residual >= 0x100)
12505 {
4eca0228 12506 _bfd_error_handler
695344c0 12507 /* xgettext:c-format */
90b6238f 12508 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12509 "splitting %#" PRIx64 " for group relocation %s"),
12510 input_bfd, input_section, (uint64_t) rel->r_offset,
12511 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12512 howto->name);
99059e56
RM		 12513 return bfd_reloc_overflow;
12514 }
12515
12516 /* Mask out the value and U bit. */
12517 insn &= 0xff7ff0f0;
12518
12519 /* Set the U bit if the value to go in the place is non-negative. */
12520 if (signed_value >= 0)
12521 insn |= 1 << 23;
12522
12523 /* Encode the offset. */
12524 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12525
12526 bfd_put_32 (input_bfd, insn, hit_data);
12527 }
12528 return bfd_reloc_ok;
12529
12530 case R_ARM_LDC_PC_G0:
12531 case R_ARM_LDC_PC_G1:
12532 case R_ARM_LDC_PC_G2:
12533 case R_ARM_LDC_SB_G0:
12534 case R_ARM_LDC_SB_G1:
12535 case R_ARM_LDC_SB_G2:
12536 {
12537 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12538 bfd_vma pc = input_section->output_section->vma
4962c51a 12539 + input_section->output_offset + rel->r_offset;
31a91d61 12540 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12541 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12542 bfd_vma residual;
4962c51a 12543 bfd_signed_vma signed_value;
99059e56
RM		 12544 int group = 0;
12545
12546 /* Determine which groups of bits to calculate. */
12547 switch (r_type)
12548 {
12549 case R_ARM_LDC_PC_G0:
12550 case R_ARM_LDC_SB_G0:
12551 group = 0;
12552 break;
12553
12554 case R_ARM_LDC_PC_G1:
12555 case R_ARM_LDC_SB_G1:
12556 group = 1;
12557 break;
12558
12559 case R_ARM_LDC_PC_G2:
12560 case R_ARM_LDC_SB_G2:
12561 group = 2;
12562 break;
12563
12564 default:
12565 abort ();
12566 }
12567
12568 /* If REL, extract the addend from the insn. If RELA, it will
12569 have already been fetched for us. */
4962c51a 12570 if (globals->use_rel)
99059e56
RM		 12571 {
12572 int negative = (insn & (1 << 23)) ? 1 : -1;
12573 signed_addend = negative * ((insn & 0xff) << 2);
12574 }
4962c51a
MS		 12575
12576 /* Compute the value (X) to go in the place. */
99059e56
RM		 12577 if (r_type == R_ARM_LDC_PC_G0
12578 || r_type == R_ARM_LDC_PC_G1
12579 || r_type == R_ARM_LDC_PC_G2)
12580 /* PC relative. */
12581 signed_value = value - pc + signed_addend;
12582 else
12583 /* Section base relative. */
12584 signed_value = value - sb + signed_addend;
12585
12586 /* Calculate the value of the relevant G_{n-1} to obtain
12587 the residual at that stage. */
b6518b38
NC		 12588 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12589 group - 1, &residual);
99059e56
RM		 12590
12591 /* Check for overflow. (The absolute value to go in the place must be
12592 divisible by four and, after having been divided by four, must
12593 fit in eight bits.) */
12594 if ((residual & 0x3) != 0 || residual >= 0x400)
12595 {
4eca0228 12596 _bfd_error_handler
695344c0 12597 /* xgettext:c-format */
90b6238f 12598 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12599 "splitting %#" PRIx64 " for group relocation %s"),
12600 input_bfd, input_section, (uint64_t) rel->r_offset,
12601 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12602 howto->name);
99059e56
RM		 12603 return bfd_reloc_overflow;
12604 }
12605
12606 /* Mask out the value and U bit. */
12607 insn &= 0xff7fff00;
12608
12609 /* Set the U bit if the value to go in the place is non-negative. */
12610 if (signed_value >= 0)
12611 insn |= 1 << 23;
12612
12613 /* Encode the offset. */
12614 insn |= residual >> 2;
4962c51a
MS		 12615
12616 bfd_put_32 (input_bfd, insn, hit_data);
12617 }
12618 return bfd_reloc_ok;
12619
72d98d16
MG		 12620 case R_ARM_THM_ALU_ABS_G0_NC:
12621 case R_ARM_THM_ALU_ABS_G1_NC:
12622 case R_ARM_THM_ALU_ABS_G2_NC:
12623 case R_ARM_THM_ALU_ABS_G3_NC:
12624 {
12625 const int shift_array[4] = {0, 8, 16, 24};
12626 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12627 bfd_vma addr = value;
12628 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12629
12630 /* Compute address. */
12631 if (globals->use_rel)
12632 signed_addend = insn & 0xff;
12633 addr += signed_addend;
12634 if (branch_type == ST_BRANCH_TO_THUMB)
12635 addr |= 1;
12636 /* Clean imm8 insn. */
12637 insn &= 0xff00;
12638 /* And update with correct part of address. */
12639 insn |= (addr >> shift) & 0xff;
12640 /* Update insn. */
12641 bfd_put_16 (input_bfd, insn, hit_data);
12642 }
12643
12644 *unresolved_reloc_p = FALSE;
12645 return bfd_reloc_ok;
12646
e8b09b87
CL		 12647 case R_ARM_GOTOFFFUNCDESC:
12648 {
4b24dd1a 12649 if (h == NULL)
e8b09b87
CL		 12650 {
12651 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12652 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12653 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12654 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12655 bfd_vma seg = -1;
12656
12657 if (bfd_link_pic(info) && dynindx == 0)
12658 abort();
12659
12660 /* Resolve relocation. */
12661 bfd_put_32(output_bfd, (offset + sgot->output_offset)
12662 , contents + rel->r_offset);
12663 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12664 not done yet. */
12665 arm_elf_fill_funcdesc(output_bfd, info,
12666 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12667 dynindx, offset, addr, dynreloc_value, seg);
12668 }
12669 else
12670 {
12671 int dynindx;
12672 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12673 bfd_vma addr;
12674 bfd_vma seg = -1;
12675
12676 /* For static binaries, sym_sec can be null. */
12677 if (sym_sec)
12678 {
12679 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12680 addr = dynreloc_value - sym_sec->output_section->vma;
12681 }
12682 else
12683 {
12684 dynindx = 0;
12685 addr = 0;
12686 }
12687
12688 if (bfd_link_pic(info) && dynindx == 0)
12689 abort();
12690
12691 /* This case cannot occur since funcdesc is allocated by
12692 the dynamic loader so we cannot resolve the relocation. */
12693 if (h->dynindx != -1)
12694 abort();
12695
12696 /* Resolve relocation. */
12697 bfd_put_32(output_bfd, (offset + sgot->output_offset),
12698 contents + rel->r_offset);
12699 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12700 arm_elf_fill_funcdesc(output_bfd, info,
12701 &eh->fdpic_cnts.funcdesc_offset,
12702 dynindx, offset, addr, dynreloc_value, seg);
12703 }
12704 }
12705 *unresolved_reloc_p = FALSE;
12706 return bfd_reloc_ok;
12707
12708 case R_ARM_GOTFUNCDESC:
12709 {
4b24dd1a 12710 if (h != NULL)
e8b09b87
CL		 12711 {
12712 Elf_Internal_Rela outrel;
12713
12714 /* Resolve relocation. */
12715 bfd_put_32(output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12716 + sgot->output_offset),
12717 contents + rel->r_offset);
12718 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12719 if(h->dynindx == -1)
12720 {
12721 int dynindx;
12722 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12723 bfd_vma addr;
12724 bfd_vma seg = -1;
12725
12726 /* For static binaries sym_sec can be null. */
12727 if (sym_sec)
12728 {
12729 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12730 addr = dynreloc_value - sym_sec->output_section->vma;
12731 }
12732 else
12733 {
12734 dynindx = 0;
12735 addr = 0;
12736 }
12737
12738 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12739 arm_elf_fill_funcdesc(output_bfd, info,
12740 &eh->fdpic_cnts.funcdesc_offset,
12741 dynindx, offset, addr, dynreloc_value, seg);
12742 }
12743
12744 /* Add a dynamic relocation on GOT entry if not already done. */
12745 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12746 {
12747 if (h->dynindx == -1)
12748 {
12749 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12750 if (h->root.type == bfd_link_hash_undefweak)
12751 bfd_put_32(output_bfd, 0, sgot->contents
12752 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12753 else
12754 bfd_put_32(output_bfd, sgot->output_section->vma
12755 + sgot->output_offset
12756 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12757 sgot->contents
12758 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12759 }
12760 else
12761 {
12762 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12763 }
12764 outrel.r_offset = sgot->output_section->vma
12765 + sgot->output_offset
12766 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12767 outrel.r_addend = 0;
12768 if (h->dynindx == -1 && !bfd_link_pic(info))
12769 if (h->root.type == bfd_link_hash_undefweak)
4b24dd1a 12770 arm_elf_add_rofixup(output_bfd, globals->srofixup, -1);
e8b09b87 12771 else
4b24dd1a
AM		 12772 arm_elf_add_rofixup(output_bfd, globals->srofixup,
12773 outrel.r_offset);
e8b09b87
CL		 12774 else
12775 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12776 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12777 }
12778 }
12779 else
12780 {
12781 /* Such relocation on static function should not have been
12782 emitted by the compiler. */
12783 abort();
12784 }
12785 }
12786 *unresolved_reloc_p = FALSE;
12787 return bfd_reloc_ok;
12788
12789 case R_ARM_FUNCDESC:
12790 {
4b24dd1a 12791 if (h == NULL)
e8b09b87
CL		 12792 {
12793 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12794 Elf_Internal_Rela outrel;
12795 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12796 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12797 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12798 bfd_vma seg = -1;
12799
12800 if (bfd_link_pic(info) && dynindx == 0)
12801 abort();
12802
12803 /* Replace static FUNCDESC relocation with a
12804 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12805 executable. */
12806 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12807 outrel.r_offset = input_section->output_section->vma
12808 + input_section->output_offset + rel->r_offset;
12809 outrel.r_addend = 0;
12810 if (bfd_link_pic(info))
12811 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12812 else
12813 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12814
12815 bfd_put_32 (input_bfd, sgot->output_section->vma
12816 + sgot->output_offset + offset, hit_data);
12817
12818 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12819 arm_elf_fill_funcdesc(output_bfd, info,
12820 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12821 dynindx, offset, addr, dynreloc_value, seg);
12822 }
12823 else
12824 {
12825 if (h->dynindx == -1)
12826 {
12827 int dynindx;
12828 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12829 bfd_vma addr;
12830 bfd_vma seg = -1;
12831 Elf_Internal_Rela outrel;
12832
12833 /* For static binaries sym_sec can be null. */
12834 if (sym_sec)
12835 {
12836 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12837 addr = dynreloc_value - sym_sec->output_section->vma;
12838 }
12839 else
12840 {
12841 dynindx = 0;
12842 addr = 0;
12843 }
12844
12845 if (bfd_link_pic(info) && dynindx == 0)
12846 abort();
12847
12848 /* Replace static FUNCDESC relocation with a
12849 R_ARM_RELATIVE dynamic relocation. */
12850 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12851 outrel.r_offset = input_section->output_section->vma
12852 + input_section->output_offset + rel->r_offset;
12853 outrel.r_addend = 0;
12854 if (bfd_link_pic(info))
12855 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12856 else
12857 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12858
12859 bfd_put_32 (input_bfd, sgot->output_section->vma
12860 + sgot->output_offset + offset, hit_data);
12861
12862 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12863 arm_elf_fill_funcdesc(output_bfd, info,
12864 &eh->fdpic_cnts.funcdesc_offset,
12865 dynindx, offset, addr, dynreloc_value, seg);
12866 }
12867 else
12868 {
12869 Elf_Internal_Rela outrel;
12870
12871 /* Add a dynamic relocation. */
12872 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12873 outrel.r_offset = input_section->output_section->vma
12874 + input_section->output_offset + rel->r_offset;
12875 outrel.r_addend = 0;
12876 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12877 }
12878 }
12879 }
12880 *unresolved_reloc_p = FALSE;
12881 return bfd_reloc_ok;
12882
e5d6e09e
AV		 12883 case R_ARM_THM_BF16:
12884 {
12885 bfd_vma relocation;
12886 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12887 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12888
12889 if (globals->use_rel)
12890 {
12891 bfd_vma immA = (upper_insn & 0x001f);
12892 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12893 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12894 addend = (immA << 12);
12895 addend |= (immB << 2);
12896 addend |= (immC << 1);
12897 addend |= 1;
12898 /* Sign extend. */
e6f65e75 12899 signed_addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
e5d6e09e
AV		 12900 }
12901
e6f65e75 12902 relocation = value + signed_addend;
e5d6e09e
AV		 12903 relocation -= (input_section->output_section->vma
12904 + input_section->output_offset
12905 + rel->r_offset);
12906
12907 /* Put RELOCATION back into the insn. */
12908 {
12909 bfd_vma immA = (relocation & 0x0001f000) >> 12;
12910 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12911 bfd_vma immC = (relocation & 0x00000002) >> 1;
12912
12913 upper_insn = (upper_insn & 0xffe0) | immA;
12914 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12915 }
12916
12917 /* Put the relocated value back in the object file: */
12918 bfd_put_16 (input_bfd, upper_insn, hit_data);
12919 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12920
12921 return bfd_reloc_ok;
12922 }
12923
1889da70
AV		 12924 case R_ARM_THM_BF12:
12925 {
12926 bfd_vma relocation;
12927 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12928 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12929
12930 if (globals->use_rel)
12931 {
12932 bfd_vma immA = (upper_insn & 0x0001);
12933 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12934 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12935 addend = (immA << 12);
12936 addend |= (immB << 2);
12937 addend |= (immC << 1);
12938 addend |= 1;
12939 /* Sign extend. */
12940 addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
e6f65e75 12941 signed_addend = addend;
1889da70
AV		 12942 }
12943
e6f65e75 12944 relocation = value + signed_addend;
1889da70
AV		 12945 relocation -= (input_section->output_section->vma
12946 + input_section->output_offset
12947 + rel->r_offset);
12948
12949 /* Put RELOCATION back into the insn. */
12950 {
12951 bfd_vma immA = (relocation & 0x00001000) >> 12;
12952 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12953 bfd_vma immC = (relocation & 0x00000002) >> 1;
12954
12955 upper_insn = (upper_insn & 0xfffe) | immA;
12956 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12957 }
12958
12959 /* Put the relocated value back in the object file: */
12960 bfd_put_16 (input_bfd, upper_insn, hit_data);
12961 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12962
12963 return bfd_reloc_ok;
12964 }
12965
1caf72a5
AV		 12966 case R_ARM_THM_BF18:
12967 {
12968 bfd_vma relocation;
12969 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12970 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12971
12972 if (globals->use_rel)
12973 {
12974 bfd_vma immA = (upper_insn & 0x007f);
12975 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12976 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12977 addend = (immA << 12);
12978 addend |= (immB << 2);
12979 addend |= (immC << 1);
12980 addend |= 1;
12981 /* Sign extend. */
12982 addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
e6f65e75 12983 signed_addend = addend;
1caf72a5
AV		 12984 }
12985
e6f65e75 12986 relocation = value + signed_addend;
1caf72a5
AV		 12987 relocation -= (input_section->output_section->vma
12988 + input_section->output_offset
12989 + rel->r_offset);
12990
12991 /* Put RELOCATION back into the insn. */
12992 {
12993 bfd_vma immA = (relocation & 0x0007f000) >> 12;
12994 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12995 bfd_vma immC = (relocation & 0x00000002) >> 1;
12996
12997 upper_insn = (upper_insn & 0xff80) | immA;
12998 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12999 }
13000
13001 /* Put the relocated value back in the object file: */
13002 bfd_put_16 (input_bfd, upper_insn, hit_data);
13003 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13004
13005 return bfd_reloc_ok;
13006 }
13007
252b5132
RH		 13008 default:
13009 return bfd_reloc_notsupported;
13010 }
13011}
13012
98c1d4aa
NC		 13013/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13014static void
07d6d2b8
AM		 13015arm_add_to_rel (bfd * abfd,
13016 bfd_byte * address,
57e8b36a 13017 reloc_howto_type * howto,
07d6d2b8 13018 bfd_signed_vma increment)
98c1d4aa 13019{
98c1d4aa
NC		 13020 bfd_signed_vma addend;
13021
bd97cb95
DJ		 13022 if (howto->type == R_ARM_THM_CALL
13023 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 13024 {
9a5aca8c
AM		 13025 int upper_insn, lower_insn;
13026 int upper, lower;
98c1d4aa 13027
9a5aca8c
AM		 13028 upper_insn = bfd_get_16 (abfd, address);
13029 lower_insn = bfd_get_16 (abfd, address + 2);
13030 upper = upper_insn & 0x7ff;
13031 lower = lower_insn & 0x7ff;
13032
13033 addend = (upper << 12) | (lower << 1);
ddda4409 13034 addend += increment;
9a5aca8c 13035 addend >>= 1;
98c1d4aa 13036
9a5aca8c
AM		 13037 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
13038 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
13039
dc810e39
AM		 13040 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
13041 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 13042 }
13043 else
13044 {
07d6d2b8 13045 bfd_vma contents;
9a5aca8c
AM		 13046
13047 contents = bfd_get_32 (abfd, address);
13048
13049 /* Get the (signed) value from the instruction. */
13050 addend = contents & howto->src_mask;
13051 if (addend & ((howto->src_mask + 1) >> 1))
13052 {
13053 bfd_signed_vma mask;
13054
13055 mask = -1;
13056 mask &= ~ howto->src_mask;
13057 addend |= mask;
13058 }
13059
13060 /* Add in the increment, (which is a byte value). */
13061 switch (howto->type)
13062 {
13063 default:
13064 addend += increment;
13065 break;
13066
13067 case R_ARM_PC24:
c6596c5e 13068 case R_ARM_PLT32:
5b5bb741
PB		 13069 case R_ARM_CALL:
13070 case R_ARM_JUMP24:
9a5aca8c 13071 addend <<= howto->size;
dc810e39 13072 addend += increment;
9a5aca8c
AM		 13073
13074 /* Should we check for overflow here ? */
13075
13076 /* Drop any undesired bits. */
13077 addend >>= howto->rightshift;
13078 break;
13079 }
13080
13081 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
13082
13083 bfd_put_32 (abfd, contents, address);
ddda4409 13084 }
98c1d4aa 13085}
252b5132 13086
ba93b8ac
DJ		 13087#define IS_ARM_TLS_RELOC(R_TYPE) \
13088 ((R_TYPE) == R_ARM_TLS_GD32 \
5c5a4843 13089 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
ba93b8ac
DJ		 13090 || (R_TYPE) == R_ARM_TLS_LDO32 \
13091 || (R_TYPE) == R_ARM_TLS_LDM32 \
5c5a4843 13092 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
ba93b8ac
DJ		 13093 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13094 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13095 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13096 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b 13097 || (R_TYPE) == R_ARM_TLS_IE32 \
5c5a4843 13098 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
0855e32b
NS		 13099 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13100
13101/* Specific set of relocations for the gnu tls dialect. */
13102#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13103 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13104 || (R_TYPE) == R_ARM_TLS_CALL \
13105 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13106 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13107 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 13108
252b5132 13109/* Relocate an ARM ELF section. */
906e58ca 13110
b34976b6 13111static bfd_boolean
07d6d2b8 13112elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 13113 struct bfd_link_info * info,
07d6d2b8
AM		 13114 bfd * input_bfd,
13115 asection * input_section,
13116 bfd_byte * contents,
13117 Elf_Internal_Rela * relocs,
13118 Elf_Internal_Sym * local_syms,
13119 asection ** local_sections)
252b5132 13120{
b34976b6
AM		 13121 Elf_Internal_Shdr *symtab_hdr;
13122 struct elf_link_hash_entry **sym_hashes;
13123 Elf_Internal_Rela *rel;
13124 Elf_Internal_Rela *relend;
13125 const char *name;
b32d3aa2 13126 struct elf32_arm_link_hash_table * globals;
252b5132 13127
4e7fd91e 13128 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13129 if (globals == NULL)
13130 return FALSE;
b491616a 13131
0ffa91dd 13132 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 13133 sym_hashes = elf_sym_hashes (input_bfd);
13134
13135 rel = relocs;
13136 relend = relocs + input_section->reloc_count;
13137 for (; rel < relend; rel++)
13138 {
07d6d2b8
AM		 13139 int r_type;
13140 reloc_howto_type * howto;
13141 unsigned long r_symndx;
13142 Elf_Internal_Sym * sym;
13143 asection * sec;
252b5132 13144 struct elf_link_hash_entry * h;
07d6d2b8
AM		 13145 bfd_vma relocation;
13146 bfd_reloc_status_type r;
13147 arelent bfd_reloc;
13148 char sym_type;
13149 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 13150 char *error_message = NULL;
f21f3fe0 13151
252b5132 13152 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 13153 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 13154 r_type = arm_real_reloc_type (globals, r_type);
252b5132 13155
ba96a88f 13156 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 13157 || r_type == R_ARM_GNU_VTINHERIT)
13158 continue;
252b5132 13159
47aeb64c
NC		 13160 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
13161
13162 if (howto == NULL)
13163 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 13164
252b5132
RH		 13165 h = NULL;
13166 sym = NULL;
13167 sec = NULL;
9b485d32 13168
252b5132
RH		 13169 if (r_symndx < symtab_hdr->sh_info)
13170 {
13171 sym = local_syms + r_symndx;
ba93b8ac 13172 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 13173 sec = local_sections[r_symndx];
ffcb4889
NS		 13174
13175 /* An object file might have a reference to a local
13176 undefined symbol. This is a daft object file, but we
13177 should at least do something about it. V4BX & NONE
13178 relocations do not use the symbol and are explicitly
77b4f08f
TS		 13179 allowed to use the undefined symbol, so allow those.
13180 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 13181 if (r_type != R_ARM_V4BX
13182 && r_type != R_ARM_NONE
77b4f08f 13183 && r_symndx != STN_UNDEF
ffcb4889
NS		 13184 && bfd_is_und_section (sec)
13185 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 13186 (*info->callbacks->undefined_symbol)
13187 (info, bfd_elf_string_from_elf_section
13188 (input_bfd, symtab_hdr->sh_link, sym->st_name),
13189 input_bfd, input_section,
13190 rel->r_offset, TRUE);
b38cadfb 13191
4e7fd91e 13192 if (globals->use_rel)
f8df10f4 13193 {
4e7fd91e
PB		 13194 relocation = (sec->output_section->vma
13195 + sec->output_offset
13196 + sym->st_value);
0e1862bb 13197 if (!bfd_link_relocatable (info)
ab96bf03
AM		 13198 && (sec->flags & SEC_MERGE)
13199 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 13200 {
4e7fd91e
PB		 13201 asection *msec;
13202 bfd_vma addend, value;
13203
39623e12 13204 switch (r_type)
4e7fd91e 13205 {
39623e12
PB		 13206 case R_ARM_MOVW_ABS_NC:
13207 case R_ARM_MOVT_ABS:
13208 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13209 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13210 addend = (addend ^ 0x8000) - 0x8000;
13211 break;
f8df10f4 13212
39623e12
PB		 13213 case R_ARM_THM_MOVW_ABS_NC:
13214 case R_ARM_THM_MOVT_ABS:
13215 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13216 << 16;
13217 value |= bfd_get_16 (input_bfd,
13218 contents + rel->r_offset + 2);
13219 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13220 | ((value & 0x04000000) >> 15);
13221 addend = (addend ^ 0x8000) - 0x8000;
13222 break;
f8df10f4 13223
39623e12
PB		 13224 default:
13225 if (howto->rightshift
13226 || (howto->src_mask & (howto->src_mask + 1)))
13227 {
4eca0228 13228 _bfd_error_handler
695344c0 13229 /* xgettext:c-format */
2dcf00ce
AM		 13230 (_("%pB(%pA+%#" PRIx64 "): "
13231 "%s relocation against SEC_MERGE section"),
39623e12 13232 input_bfd, input_section,
2dcf00ce 13233 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 13234 return FALSE;
13235 }
13236
13237 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13238
13239 /* Get the (signed) value from the instruction. */
13240 addend = value & howto->src_mask;
13241 if (addend & ((howto->src_mask + 1) >> 1))
13242 {
13243 bfd_signed_vma mask;
13244
13245 mask = -1;
13246 mask &= ~ howto->src_mask;
13247 addend |= mask;
13248 }
13249 break;
4e7fd91e 13250 }
39623e12 13251
4e7fd91e
PB		 13252 msec = sec;
13253 addend =
13254 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13255 - relocation;
13256 addend += msec->output_section->vma + msec->output_offset;
39623e12 13257
cc643b88 13258 /* Cases here must match those in the preceding
39623e12
PB		 13259 switch statement. */
13260 switch (r_type)
13261 {
13262 case R_ARM_MOVW_ABS_NC:
13263 case R_ARM_MOVT_ABS:
13264 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13265 | (addend & 0xfff);
13266 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13267 break;
13268
13269 case R_ARM_THM_MOVW_ABS_NC:
13270 case R_ARM_THM_MOVT_ABS:
13271 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13272 | (addend & 0xff) | ((addend & 0x0800) << 15);
13273 bfd_put_16 (input_bfd, value >> 16,
13274 contents + rel->r_offset);
13275 bfd_put_16 (input_bfd, value,
13276 contents + rel->r_offset + 2);
13277 break;
13278
13279 default:
13280 value = (value & ~ howto->dst_mask)
13281 | (addend & howto->dst_mask);
13282 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13283 break;
13284 }
f8df10f4 13285 }
f8df10f4 13286 }
4e7fd91e
PB		 13287 else
13288 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 13289 }
13290 else
13291 {
62d887d4 13292 bfd_boolean warned, ignored;
560e09e9 13293
b2a8e766
AM		 13294 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13295 r_symndx, symtab_hdr, sym_hashes,
13296 h, sec, relocation,
62d887d4 13297 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 13298
13299 sym_type = h->type;
252b5132
RH		 13300 }
13301
dbaa2011 13302 if (sec != NULL && discarded_section (sec))
e4067dbb 13303 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 13304 rel, 1, relend, howto, 0, contents);
ab96bf03 13305
0e1862bb 13306 if (bfd_link_relocatable (info))
ab96bf03
AM		 13307 {
13308 /* This is a relocatable link. We don't have to change
13309 anything, unless the reloc is against a section symbol,
13310 in which case we have to adjust according to where the
13311 section symbol winds up in the output section. */
13312 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13313 {
13314 if (globals->use_rel)
13315 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13316 howto, (bfd_signed_vma) sec->output_offset);
13317 else
13318 rel->r_addend += sec->output_offset;
13319 }
13320 continue;
13321 }
13322
252b5132
RH		 13323 if (h != NULL)
13324 name = h->root.root.string;
13325 else
13326 {
13327 name = (bfd_elf_string_from_elf_section
13328 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13329 if (name == NULL || *name == '\0')
fd361982 13330 name = bfd_section_name (sec);
252b5132 13331 }
f21f3fe0 13332
cf35638d 13333 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 13334 && r_type != R_ARM_NONE
13335 && (h == NULL
13336 || h->root.type == bfd_link_hash_defined
13337 || h->root.type == bfd_link_hash_defweak)
13338 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13339 {
4eca0228 13340 _bfd_error_handler
ba93b8ac 13341 ((sym_type == STT_TLS
695344c0 13342 /* xgettext:c-format */
2dcf00ce 13343 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 13344 /* xgettext:c-format */
2dcf00ce 13345 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 13346 input_bfd,
13347 input_section,
2dcf00ce 13348 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 13349 howto->name,
13350 name);
13351 }
13352
0855e32b 13353 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 13354 done, i.e., the relaxation produced the final output we want,
13355 and we won't let anybody mess with it. Also, we have to do
13356 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 13357 both in relaxed and non-relaxed cases. */
39d911fc
TP		 13358 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13359 || (IS_ARM_TLS_GNU_RELOC (r_type)
13360 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13361 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13362 & GOT_TLS_GDESC)))
13363 {
13364 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13365 contents, rel, h == NULL);
13366 /* This may have been marked unresolved because it came from
13367 a shared library. But we've just dealt with that. */
13368 unresolved_reloc = 0;
13369 }
13370 else
13371 r = bfd_reloc_continue;
b38cadfb 13372
39d911fc
TP		 13373 if (r == bfd_reloc_continue)
13374 {
13375 unsigned char branch_type =
13376 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13377 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13378
13379 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13380 input_section, contents, rel,
13381 relocation, info, sec, name,
13382 sym_type, branch_type, h,
13383 &unresolved_reloc,
13384 &error_message);
13385 }
0945cdfd
DJ		 13386
13387 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13388 because such sections are not SEC_ALLOC and thus ld.so will
13389 not process them. */
13390 if (unresolved_reloc
99059e56
RM		 13391 && !((input_section->flags & SEC_DEBUGGING) != 0
13392 && h->def_dynamic)
1d5316ab
AM		 13393 && _bfd_elf_section_offset (output_bfd, info, input_section,
13394 rel->r_offset) != (bfd_vma) -1)
0945cdfd 13395 {
4eca0228 13396 _bfd_error_handler
695344c0 13397 /* xgettext:c-format */
2dcf00ce
AM		 13398 (_("%pB(%pA+%#" PRIx64 "): "
13399 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 13400 input_bfd,
13401 input_section,
2dcf00ce 13402 (uint64_t) rel->r_offset,
843fe662
L		 13403 howto->name,
13404 h->root.root.string);
0945cdfd
DJ		 13405 return FALSE;
13406 }
252b5132
RH		 13407
13408 if (r != bfd_reloc_ok)
13409 {
252b5132
RH		 13410 switch (r)
13411 {
13412 case bfd_reloc_overflow:
cf919dfd
PB		 13413 /* If the overflowing reloc was to an undefined symbol,
13414 we have already printed one error message and there
13415 is no point complaining again. */
1a72702b
AM		 13416 if (!h || h->root.type != bfd_link_hash_undefined)
13417 (*info->callbacks->reloc_overflow)
13418 (info, (h ? &h->root : NULL), name, howto->name,
13419 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13420 break;
13421
13422 case bfd_reloc_undefined:
1a72702b
AM		 13423 (*info->callbacks->undefined_symbol)
13424 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 13425 break;
13426
13427 case bfd_reloc_outofrange:
f2a9dd69 13428 error_message = _("out of range");
252b5132
RH		 13429 goto common_error;
13430
13431 case bfd_reloc_notsupported:
f2a9dd69 13432 error_message = _("unsupported relocation");
252b5132
RH		 13433 goto common_error;
13434
13435 case bfd_reloc_dangerous:
f2a9dd69 13436 /* error_message should already be set. */
252b5132
RH		 13437 goto common_error;
13438
13439 default:
f2a9dd69 13440 error_message = _("unknown error");
8029a119 13441 /* Fall through. */
252b5132
RH		 13442
13443 common_error:
f2a9dd69 13444 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 13445 (*info->callbacks->reloc_dangerous)
13446 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13447 break;
13448 }
13449 }
13450 }
13451
b34976b6 13452 return TRUE;
252b5132
RH		 13453}
13454
91d6fa6a 13455/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 13456 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 13457 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 13458 maintaining that condition). */
13459
13460static void
13461add_unwind_table_edit (arm_unwind_table_edit **head,
13462 arm_unwind_table_edit **tail,
13463 arm_unwind_edit_type type,
13464 asection *linked_section,
91d6fa6a 13465 unsigned int tindex)
2468f9c9 13466{
21d799b5
NC		 13467 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13468 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 13469
2468f9c9
PB		 13470 new_edit->type = type;
13471 new_edit->linked_section = linked_section;
91d6fa6a 13472 new_edit->index = tindex;
b38cadfb 13473
91d6fa6a 13474 if (tindex > 0)
2468f9c9
PB		 13475 {
13476 new_edit->next = NULL;
13477
13478 if (*tail)
13479 (*tail)->next = new_edit;
13480
13481 (*tail) = new_edit;
13482
13483 if (!*head)
13484 (*head) = new_edit;
13485 }
13486 else
13487 {
13488 new_edit->next = *head;
13489
13490 if (!*tail)
13491 *tail = new_edit;
13492
13493 *head = new_edit;
13494 }
13495}
13496
13497static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13498
13499/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13500static void
13501adjust_exidx_size(asection *exidx_sec, int adjust)
13502{
13503 asection *out_sec;
13504
13505 if (!exidx_sec->rawsize)
13506 exidx_sec->rawsize = exidx_sec->size;
13507
fd361982 13508 bfd_set_section_size (exidx_sec, exidx_sec->size + adjust);
2468f9c9
PB		 13509 out_sec = exidx_sec->output_section;
13510 /* Adjust size of output section. */
fd361982 13511 bfd_set_section_size (out_sec, out_sec->size +adjust);
2468f9c9
PB		 13512}
13513
13514/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13515static void
13516insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
13517{
13518 struct _arm_elf_section_data *exidx_arm_data;
13519
13520 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13521 add_unwind_table_edit (
13522 &exidx_arm_data->u.exidx.unwind_edit_list,
13523 &exidx_arm_data->u.exidx.unwind_edit_tail,
13524 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13525
491d01d3
YU		 13526 exidx_arm_data->additional_reloc_count++;
13527
2468f9c9
PB		 13528 adjust_exidx_size(exidx_sec, 8);
13529}
13530
13531/* Scan .ARM.exidx tables, and create a list describing edits which should be
13532 made to those tables, such that:
b38cadfb 13533
2468f9c9
PB		 13534 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13535 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 13536 codes which have been inlined into the index).
2468f9c9 13537
85fdf906
AH		 13538 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13539
2468f9c9 13540 The edits are applied when the tables are written
b38cadfb 13541 (in elf32_arm_write_section). */
2468f9c9
PB		 13542
13543bfd_boolean
13544elf32_arm_fix_exidx_coverage (asection **text_section_order,
13545 unsigned int num_text_sections,
85fdf906
AH		 13546 struct bfd_link_info *info,
13547 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 13548{
13549 bfd *inp;
13550 unsigned int last_second_word = 0, i;
13551 asection *last_exidx_sec = NULL;
13552 asection *last_text_sec = NULL;
13553 int last_unwind_type = -1;
13554
13555 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13556 text sections. */
c72f2fb2 13557 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 13558 {
13559 asection *sec;
b38cadfb 13560
2468f9c9 13561 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 13562 {
2468f9c9
PB		 13563 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13564 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 13565
dec9d5df 13566 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 13567 continue;
b38cadfb 13568
2468f9c9
PB		 13569 if (elf_sec->linked_to)
13570 {
13571 Elf_Internal_Shdr *linked_hdr
99059e56 13572 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 13573 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 13574 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 13575
13576 if (linked_sec_arm_data == NULL)
99059e56 13577 continue;
2468f9c9
PB		 13578
13579 /* Link this .ARM.exidx section back from the text section it
99059e56 13580 describes. */
2468f9c9
PB		 13581 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13582 }
13583 }
13584 }
13585
13586 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13587 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 13588 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 13589
13590 for (i = 0; i < num_text_sections; i++)
13591 {
13592 asection *sec = text_section_order[i];
13593 asection *exidx_sec;
13594 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13595 struct _arm_elf_section_data *exidx_arm_data;
13596 bfd_byte *contents = NULL;
13597 int deleted_exidx_bytes = 0;
13598 bfd_vma j;
13599 arm_unwind_table_edit *unwind_edit_head = NULL;
13600 arm_unwind_table_edit *unwind_edit_tail = NULL;
13601 Elf_Internal_Shdr *hdr;
13602 bfd *ibfd;
13603
13604 if (arm_data == NULL)
99059e56 13605 continue;
2468f9c9
PB		 13606
13607 exidx_sec = arm_data->u.text.arm_exidx_sec;
13608 if (exidx_sec == NULL)
13609 {
13610 /* Section has no unwind data. */
13611 if (last_unwind_type == 0 || !last_exidx_sec)
13612 continue;
13613
13614 /* Ignore zero sized sections. */
13615 if (sec->size == 0)
13616 continue;
13617
13618 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13619 last_unwind_type = 0;
13620 continue;
13621 }
13622
22a8f80e
PB		 13623 /* Skip /DISCARD/ sections. */
13624 if (bfd_is_abs_section (exidx_sec->output_section))
13625 continue;
13626
2468f9c9
PB		 13627 hdr = &elf_section_data (exidx_sec)->this_hdr;
13628 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 13629 continue;
b38cadfb 13630
2468f9c9
PB		 13631 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13632 if (exidx_arm_data == NULL)
99059e56 13633 continue;
b38cadfb 13634
2468f9c9 13635 ibfd = exidx_sec->owner;
b38cadfb 13636
2468f9c9
PB		 13637 if (hdr->contents != NULL)
13638 contents = hdr->contents;
13639 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13640 /* An error? */
13641 continue;
13642
ac06903d
YU		 13643 if (last_unwind_type > 0)
13644 {
13645 unsigned int first_word = bfd_get_32 (ibfd, contents);
13646 /* Add cantunwind if first unwind item does not match section
13647 start. */
13648 if (first_word != sec->vma)
13649 {
13650 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13651 last_unwind_type = 0;
13652 }
13653 }
13654
2468f9c9
PB		 13655 for (j = 0; j < hdr->sh_size; j += 8)
13656 {
13657 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13658 int unwind_type;
13659 int elide = 0;
13660
13661 /* An EXIDX_CANTUNWIND entry. */
13662 if (second_word == 1)
13663 {
13664 if (last_unwind_type == 0)
13665 elide = 1;
13666 unwind_type = 0;
13667 }
13668 /* Inlined unwinding data. Merge if equal to previous. */
13669 else if ((second_word & 0x80000000) != 0)
13670 {
85fdf906
AH		 13671 if (merge_exidx_entries
13672 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 13673 elide = 1;
13674 unwind_type = 1;
13675 last_second_word = second_word;
13676 }
13677 /* Normal table entry. In theory we could merge these too,
13678 but duplicate entries are likely to be much less common. */
13679 else
13680 unwind_type = 2;
13681
491d01d3 13682 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 13683 {
13684 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13685 DELETE_EXIDX_ENTRY, NULL, j / 8);
13686
13687 deleted_exidx_bytes += 8;
13688 }
13689
13690 last_unwind_type = unwind_type;
13691 }
13692
13693 /* Free contents if we allocated it ourselves. */
13694 if (contents != hdr->contents)
99059e56 13695 free (contents);
2468f9c9
PB		 13696
13697 /* Record edits to be applied later (in elf32_arm_write_section). */
13698 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13699 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 13700
2468f9c9
PB		 13701 if (deleted_exidx_bytes > 0)
13702 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
13703
13704 last_exidx_sec = exidx_sec;
13705 last_text_sec = sec;
13706 }
13707
13708 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 13709 if (!bfd_link_relocatable (info) && last_exidx_sec
13710 && last_unwind_type != 0)
2468f9c9
PB		 13711 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13712
13713 return TRUE;
13714}
13715
3e6b1042
DJ		 13716static bfd_boolean
13717elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13718 bfd *ibfd, const char *name)
13719{
13720 asection *sec, *osec;
13721
3d4d4302 13722 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 13723 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13724 return TRUE;
13725
13726 osec = sec->output_section;
13727 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13728 return TRUE;
13729
13730 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13731 sec->output_offset, sec->size))
13732 return FALSE;
13733
13734 return TRUE;
13735}
13736
13737static bfd_boolean
13738elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13739{
13740 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 13741 asection *sec, *osec;
3e6b1042 13742
4dfe6ac6
NC		 13743 if (globals == NULL)
13744 return FALSE;
13745
3e6b1042
DJ		 13746 /* Invoke the regular ELF backend linker to do all the work. */
13747 if (!bfd_elf_final_link (abfd, info))
13748 return FALSE;
13749
fe33d2fa
CL		 13750 /* Process stub sections (eg BE8 encoding, ...). */
13751 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 13752 unsigned int i;
cdb21a0a
NS		 13753 for (i=0; i<htab->top_id; i++)
13754 {
13755 sec = htab->stub_group[i].stub_sec;
13756 /* Only process it once, in its link_sec slot. */
13757 if (sec && i == htab->stub_group[i].link_sec->id)
13758 {
13759 osec = sec->output_section;
13760 elf32_arm_write_section (abfd, info, sec, sec->contents);
13761 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13762 sec->output_offset, sec->size))
13763 return FALSE;
13764 }
fe33d2fa 13765 }
fe33d2fa 13766
3e6b1042
DJ		 13767 /* Write out any glue sections now that we have created all the
13768 stubs. */
13769 if (globals->bfd_of_glue_owner != NULL)
13770 {
13771 if (! elf32_arm_output_glue_section (info, abfd,
13772 globals->bfd_of_glue_owner,
13773 ARM2THUMB_GLUE_SECTION_NAME))
13774 return FALSE;
13775
13776 if (! elf32_arm_output_glue_section (info, abfd,
13777 globals->bfd_of_glue_owner,
13778 THUMB2ARM_GLUE_SECTION_NAME))
13779 return FALSE;
13780
13781 if (! elf32_arm_output_glue_section (info, abfd,
13782 globals->bfd_of_glue_owner,
13783 VFP11_ERRATUM_VENEER_SECTION_NAME))
13784 return FALSE;
13785
a504d23a
LA		 13786 if (! elf32_arm_output_glue_section (info, abfd,
13787 globals->bfd_of_glue_owner,
13788 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13789 return FALSE;
13790
3e6b1042
DJ		 13791 if (! elf32_arm_output_glue_section (info, abfd,
13792 globals->bfd_of_glue_owner,
13793 ARM_BX_GLUE_SECTION_NAME))
13794 return FALSE;
13795 }
13796
13797 return TRUE;
13798}
13799
5968a7b8
NC		 13800/* Return a best guess for the machine number based on the attributes. */
13801
13802static unsigned int
13803bfd_arm_get_mach_from_attributes (bfd * abfd)
13804{
13805 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13806
13807 switch (arch)
13808 {
c0c468d5 13809 case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
5968a7b8
NC		 13810 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13811 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13812 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13813
13814 case TAG_CPU_ARCH_V5TE:
13815 {
13816 char * name;
13817
13818 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13819 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13820
13821 if (name)
13822 {
13823 if (strcmp (name, "IWMMXT2") == 0)
13824 return bfd_mach_arm_iWMMXt2;
13825
13826 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13827 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13828
13829 if (strcmp (name, "XSCALE") == 0)
13830 {
13831 int wmmx;
13832
13833 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13834 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13835 switch (wmmx)
13836 {
13837 case 1: return bfd_mach_arm_iWMMXt;
13838 case 2: return bfd_mach_arm_iWMMXt2;
13839 default: return bfd_mach_arm_XScale;
13840 }
13841 }
5968a7b8
NC		 13842 }
13843
13844 return bfd_mach_arm_5TE;
13845 }
13846
c0c468d5
TP		 13847 case TAG_CPU_ARCH_V5TEJ:
13848 return bfd_mach_arm_5TEJ;
13849 case TAG_CPU_ARCH_V6:
13850 return bfd_mach_arm_6;
13851 case TAG_CPU_ARCH_V6KZ:
13852 return bfd_mach_arm_6KZ;
13853 case TAG_CPU_ARCH_V6T2:
13854 return bfd_mach_arm_6T2;
13855 case TAG_CPU_ARCH_V6K:
13856 return bfd_mach_arm_6K;
13857 case TAG_CPU_ARCH_V7:
13858 return bfd_mach_arm_7;
13859 case TAG_CPU_ARCH_V6_M:
13860 return bfd_mach_arm_6M;
13861 case TAG_CPU_ARCH_V6S_M:
13862 return bfd_mach_arm_6SM;
13863 case TAG_CPU_ARCH_V7E_M:
13864 return bfd_mach_arm_7EM;
13865 case TAG_CPU_ARCH_V8:
13866 return bfd_mach_arm_8;
13867 case TAG_CPU_ARCH_V8R:
13868 return bfd_mach_arm_8R;
13869 case TAG_CPU_ARCH_V8M_BASE:
13870 return bfd_mach_arm_8M_BASE;
13871 case TAG_CPU_ARCH_V8M_MAIN:
13872 return bfd_mach_arm_8M_MAIN;
031254f2
AV		 13873 case TAG_CPU_ARCH_V8_1M_MAIN:
13874 return bfd_mach_arm_8_1M_MAIN;
c0c468d5 13875
5968a7b8 13876 default:
c0c468d5
TP		 13877 /* Force entry to be added for any new known Tag_CPU_arch value. */
13878 BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
13879
13880 /* Unknown Tag_CPU_arch value. */
5968a7b8
NC		 13881 return bfd_mach_arm_unknown;
13882 }
13883}
13884
c178919b
NC		 13885/* Set the right machine number. */
13886
13887static bfd_boolean
57e8b36a 13888elf32_arm_object_p (bfd *abfd)
c178919b 13889{
5a6c6817 13890 unsigned int mach;
57e8b36a 13891
5a6c6817 13892 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13893
5968a7b8
NC		 13894 if (mach == bfd_mach_arm_unknown)
13895 {
13896 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13897 mach = bfd_mach_arm_ep9312;
13898 else
13899 mach = bfd_arm_get_mach_from_attributes (abfd);
13900 }
c178919b 13901
5968a7b8 13902 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13903 return TRUE;
13904}
13905
fc830a83 13906/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13907
b34976b6 13908static bfd_boolean
57e8b36a 13909elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13910{
13911 if (elf_flags_init (abfd)
13912 && elf_elfheader (abfd)->e_flags != flags)
13913 {
fc830a83
NC		 13914 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13915 {
fd2ec330 13916 if (flags & EF_ARM_INTERWORK)
4eca0228 13917 _bfd_error_handler
90b6238f 13918 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13919 abfd);
fc830a83 13920 else
d003868e 13921 _bfd_error_handler
90b6238f 13922 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13923 abfd);
fc830a83 13924 }
252b5132
RH		 13925 }
13926 else
13927 {
13928 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13929 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13930 }
13931
b34976b6 13932 return TRUE;
252b5132
RH		 13933}
13934
fc830a83 13935/* Copy backend specific data from one object module to another. */
9b485d32 13936
b34976b6 13937static bfd_boolean
57e8b36a 13938elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13939{
13940 flagword in_flags;
13941 flagword out_flags;
13942
0ffa91dd 13943 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13944 return TRUE;
252b5132 13945
fc830a83 13946 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13947 out_flags = elf_elfheader (obfd)->e_flags;
13948
fc830a83
NC		 13949 if (elf_flags_init (obfd)
13950 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13951 && in_flags != out_flags)
252b5132 13952 {
252b5132 13953 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13954 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13955 return FALSE;
252b5132
RH		 13956
13957 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13958 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13959 return FALSE;
252b5132
RH		 13960
13961 /* If the src and dest have different interworking flags
99059e56 13962 then turn off the interworking bit. */
fd2ec330 13963 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13964 {
fd2ec330 13965 if (out_flags & EF_ARM_INTERWORK)
d003868e 13966 _bfd_error_handler
90b6238f 13967 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 13968 obfd, ibfd);
252b5132 13969
fd2ec330 13970 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13971 }
1006ba19
PB		 13972
13973 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13974 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13975 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13976 }
13977
13978 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13979 elf_flags_init (obfd) = TRUE;
252b5132 13980
e2349352 13981 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13982}
13983
13984/* Values for Tag_ABI_PCS_R9_use. */
13985enum
13986{
13987 AEABI_R9_V6,
13988 AEABI_R9_SB,
13989 AEABI_R9_TLS,
13990 AEABI_R9_unused
13991};
13992
13993/* Values for Tag_ABI_PCS_RW_data. */
13994enum
13995{
13996 AEABI_PCS_RW_data_absolute,
13997 AEABI_PCS_RW_data_PCrel,
13998 AEABI_PCS_RW_data_SBrel,
13999 AEABI_PCS_RW_data_unused
14000};
14001
14002/* Values for Tag_ABI_enum_size. */
14003enum
14004{
14005 AEABI_enum_unused,
14006 AEABI_enum_short,
14007 AEABI_enum_wide,
14008 AEABI_enum_forced_wide
14009};
14010
104d59d1
JM		 14011/* Determine whether an object attribute tag takes an integer, a
14012 string or both. */
906e58ca 14013
104d59d1
JM		 14014static int
14015elf32_arm_obj_attrs_arg_type (int tag)
14016{
14017 if (tag == Tag_compatibility)
3483fe2e 14018 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 14019 else if (tag == Tag_nodefaults)
3483fe2e
AS		 14020 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
14021 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
14022 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 14023 else if (tag < 32)
3483fe2e 14024 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 14025 else
3483fe2e 14026 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 14027}
14028
5aa6ff7c
AS		 14029/* The ABI defines that Tag_conformance should be emitted first, and that
14030 Tag_nodefaults should be second (if either is defined). This sets those
14031 two positions, and bumps up the position of all the remaining tags to
14032 compensate. */
14033static int
14034elf32_arm_obj_attrs_order (int num)
14035{
3de4a297 14036 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 14037 return Tag_conformance;
3de4a297 14038 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 14039 return Tag_nodefaults;
14040 if ((num - 2) < Tag_nodefaults)
14041 return num - 2;
14042 if ((num - 1) < Tag_conformance)
14043 return num - 1;
14044 return num;
14045}
14046
e8b36cd1
JM		 14047/* Attribute numbers >=64 (mod 128) can be safely ignored. */
14048static bfd_boolean
14049elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
14050{
14051 if ((tag & 127) < 64)
14052 {
14053 _bfd_error_handler
90b6238f 14054 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 14055 abfd, tag);
14056 bfd_set_error (bfd_error_bad_value);
14057 return FALSE;
14058 }
14059 else
14060 {
14061 _bfd_error_handler
90b6238f 14062 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 14063 abfd, tag);
14064 return TRUE;
14065 }
14066}
14067
91e22acd
AS		 14068/* Read the architecture from the Tag_also_compatible_with attribute, if any.
14069 Returns -1 if no architecture could be read. */
14070
14071static int
14072get_secondary_compatible_arch (bfd *abfd)
14073{
14074 obj_attribute *attr =
14075 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
14076
14077 /* Note: the tag and its argument below are uleb128 values, though
14078 currently-defined values fit in one byte for each. */
14079 if (attr->s
14080 && attr->s[0] == Tag_CPU_arch
14081 && (attr->s[1] & 128) != 128
14082 && attr->s[2] == 0)
14083 return attr->s[1];
14084
14085 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14086 return -1;
14087}
14088
14089/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14090 The tag is removed if ARCH is -1. */
14091
8e79c3df 14092static void
91e22acd 14093set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 14094{
91e22acd
AS		 14095 obj_attribute *attr =
14096 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 14097
91e22acd
AS		 14098 if (arch == -1)
14099 {
14100 attr->s = NULL;
14101 return;
8e79c3df 14102 }
91e22acd
AS		 14103
14104 /* Note: the tag and its argument below are uleb128 values, though
14105 currently-defined values fit in one byte for each. */
14106 if (!attr->s)
21d799b5 14107 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 14108 attr->s[0] = Tag_CPU_arch;
14109 attr->s[1] = arch;
14110 attr->s[2] = '\0';
8e79c3df
CM		 14111}
14112
91e22acd
AS		 14113/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14114 into account. */
14115
14116static int
14117tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
14118 int newtag, int secondary_compat)
8e79c3df 14119{
91e22acd
AS		 14120#define T(X) TAG_CPU_ARCH_##X
14121 int tagl, tagh, result;
14122 const int v6t2[] =
14123 {
14124 T(V6T2), /* PRE_V4. */
14125 T(V6T2), /* V4. */
14126 T(V6T2), /* V4T. */
14127 T(V6T2), /* V5T. */
14128 T(V6T2), /* V5TE. */
14129 T(V6T2), /* V5TEJ. */
14130 T(V6T2), /* V6. */
14131 T(V7), /* V6KZ. */
14132 T(V6T2) /* V6T2. */
14133 };
14134 const int v6k[] =
14135 {
14136 T(V6K), /* PRE_V4. */
14137 T(V6K), /* V4. */
14138 T(V6K), /* V4T. */
14139 T(V6K), /* V5T. */
14140 T(V6K), /* V5TE. */
14141 T(V6K), /* V5TEJ. */
14142 T(V6K), /* V6. */
14143 T(V6KZ), /* V6KZ. */
14144 T(V7), /* V6T2. */
14145 T(V6K) /* V6K. */
14146 };
14147 const int v7[] =
14148 {
14149 T(V7), /* PRE_V4. */
14150 T(V7), /* V4. */
14151 T(V7), /* V4T. */
14152 T(V7), /* V5T. */
14153 T(V7), /* V5TE. */
14154 T(V7), /* V5TEJ. */
14155 T(V7), /* V6. */
14156 T(V7), /* V6KZ. */
14157 T(V7), /* V6T2. */
14158 T(V7), /* V6K. */
14159 T(V7) /* V7. */
14160 };
14161 const int v6_m[] =
14162 {
07d6d2b8
AM		 14163 -1, /* PRE_V4. */
14164 -1, /* V4. */
91e22acd
AS		 14165 T(V6K), /* V4T. */
14166 T(V6K), /* V5T. */
14167 T(V6K), /* V5TE. */
14168 T(V6K), /* V5TEJ. */
14169 T(V6K), /* V6. */
14170 T(V6KZ), /* V6KZ. */
14171 T(V7), /* V6T2. */
14172 T(V6K), /* V6K. */
14173 T(V7), /* V7. */
14174 T(V6_M) /* V6_M. */
14175 };
14176 const int v6s_m[] =
14177 {
07d6d2b8
AM		 14178 -1, /* PRE_V4. */
14179 -1, /* V4. */
91e22acd
AS		 14180 T(V6K), /* V4T. */
14181 T(V6K), /* V5T. */
14182 T(V6K), /* V5TE. */
14183 T(V6K), /* V5TEJ. */
14184 T(V6K), /* V6. */
14185 T(V6KZ), /* V6KZ. */
14186 T(V7), /* V6T2. */
14187 T(V6K), /* V6K. */
14188 T(V7), /* V7. */
14189 T(V6S_M), /* V6_M. */
14190 T(V6S_M) /* V6S_M. */
14191 };
9e3c6df6
PB		 14192 const int v7e_m[] =
14193 {
07d6d2b8
AM		 14194 -1, /* PRE_V4. */
14195 -1, /* V4. */
9e3c6df6
PB		 14196 T(V7E_M), /* V4T. */
14197 T(V7E_M), /* V5T. */
14198 T(V7E_M), /* V5TE. */
14199 T(V7E_M), /* V5TEJ. */
14200 T(V7E_M), /* V6. */
14201 T(V7E_M), /* V6KZ. */
14202 T(V7E_M), /* V6T2. */
14203 T(V7E_M), /* V6K. */
14204 T(V7E_M), /* V7. */
14205 T(V7E_M), /* V6_M. */
14206 T(V7E_M), /* V6S_M. */
14207 T(V7E_M) /* V7E_M. */
14208 };
bca38921
MGD		 14209 const int v8[] =
14210 {
14211 T(V8), /* PRE_V4. */
14212 T(V8), /* V4. */
14213 T(V8), /* V4T. */
14214 T(V8), /* V5T. */
14215 T(V8), /* V5TE. */
14216 T(V8), /* V5TEJ. */
14217 T(V8), /* V6. */
14218 T(V8), /* V6KZ. */
14219 T(V8), /* V6T2. */
14220 T(V8), /* V6K. */
14221 T(V8), /* V7. */
14222 T(V8), /* V6_M. */
14223 T(V8), /* V6S_M. */
14224 T(V8), /* V7E_M. */
14225 T(V8) /* V8. */
14226 };
bff0500d
TP		 14227 const int v8r[] =
14228 {
14229 T(V8R), /* PRE_V4. */
14230 T(V8R), /* V4. */
14231 T(V8R), /* V4T. */
14232 T(V8R), /* V5T. */
14233 T(V8R), /* V5TE. */
14234 T(V8R), /* V5TEJ. */
14235 T(V8R), /* V6. */
14236 T(V8R), /* V6KZ. */
14237 T(V8R), /* V6T2. */
14238 T(V8R), /* V6K. */
14239 T(V8R), /* V7. */
14240 T(V8R), /* V6_M. */
14241 T(V8R), /* V6S_M. */
14242 T(V8R), /* V7E_M. */
14243 T(V8), /* V8. */
14244 T(V8R), /* V8R. */
14245 };
2fd158eb
TP		 14246 const int v8m_baseline[] =
14247 {
14248 -1, /* PRE_V4. */
14249 -1, /* V4. */
14250 -1, /* V4T. */
14251 -1, /* V5T. */
14252 -1, /* V5TE. */
14253 -1, /* V5TEJ. */
14254 -1, /* V6. */
14255 -1, /* V6KZ. */
14256 -1, /* V6T2. */
14257 -1, /* V6K. */
14258 -1, /* V7. */
14259 T(V8M_BASE), /* V6_M. */
14260 T(V8M_BASE), /* V6S_M. */
14261 -1, /* V7E_M. */
14262 -1, /* V8. */
bff0500d 14263 -1, /* V8R. */
2fd158eb
TP		 14264 T(V8M_BASE) /* V8-M BASELINE. */
14265 };
14266 const int v8m_mainline[] =
14267 {
14268 -1, /* PRE_V4. */
14269 -1, /* V4. */
14270 -1, /* V4T. */
14271 -1, /* V5T. */
14272 -1, /* V5TE. */
14273 -1, /* V5TEJ. */
14274 -1, /* V6. */
14275 -1, /* V6KZ. */
14276 -1, /* V6T2. */
14277 -1, /* V6K. */
14278 T(V8M_MAIN), /* V7. */
14279 T(V8M_MAIN), /* V6_M. */
14280 T(V8M_MAIN), /* V6S_M. */
14281 T(V8M_MAIN), /* V7E_M. */
14282 -1, /* V8. */
bff0500d 14283 -1, /* V8R. */
2fd158eb
TP		 14284 T(V8M_MAIN), /* V8-M BASELINE. */
14285 T(V8M_MAIN) /* V8-M MAINLINE. */
14286 };
031254f2
AV		 14287 const int v8_1m_mainline[] =
14288 {
14289 -1, /* PRE_V4. */
14290 -1, /* V4. */
14291 -1, /* V4T. */
14292 -1, /* V5T. */
14293 -1, /* V5TE. */
14294 -1, /* V5TEJ. */
14295 -1, /* V6. */
14296 -1, /* V6KZ. */
14297 -1, /* V6T2. */
14298 -1, /* V6K. */
14299 T(V8_1M_MAIN), /* V7. */
14300 T(V8_1M_MAIN), /* V6_M. */
14301 T(V8_1M_MAIN), /* V6S_M. */
14302 T(V8_1M_MAIN), /* V7E_M. */
14303 -1, /* V8. */
14304 -1, /* V8R. */
14305 T(V8_1M_MAIN), /* V8-M BASELINE. */
14306 T(V8_1M_MAIN), /* V8-M MAINLINE. */
14307 -1, /* Unused (18). */
14308 -1, /* Unused (19). */
14309 -1, /* Unused (20). */
14310 T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
14311 };
91e22acd
AS		 14312 const int v4t_plus_v6_m[] =
14313 {
14314 -1, /* PRE_V4. */
14315 -1, /* V4. */
14316 T(V4T), /* V4T. */
14317 T(V5T), /* V5T. */
14318 T(V5TE), /* V5TE. */
14319 T(V5TEJ), /* V5TEJ. */
14320 T(V6), /* V6. */
14321 T(V6KZ), /* V6KZ. */
14322 T(V6T2), /* V6T2. */
14323 T(V6K), /* V6K. */
14324 T(V7), /* V7. */
14325 T(V6_M), /* V6_M. */
14326 T(V6S_M), /* V6S_M. */
9e3c6df6 14327 T(V7E_M), /* V7E_M. */
bca38921 14328 T(V8), /* V8. */
bff0500d 14329 -1, /* V8R. */
2fd158eb
TP		 14330 T(V8M_BASE), /* V8-M BASELINE. */
14331 T(V8M_MAIN), /* V8-M MAINLINE. */
031254f2
AV		 14332 -1, /* Unused (18). */
14333 -1, /* Unused (19). */
14334 -1, /* Unused (20). */
14335 T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
91e22acd
AS		 14336 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14337 };
14338 const int *comb[] =
14339 {
14340 v6t2,
14341 v6k,
14342 v7,
14343 v6_m,
14344 v6s_m,
9e3c6df6 14345 v7e_m,
bca38921 14346 v8,
bff0500d 14347 v8r,
2fd158eb
TP		 14348 v8m_baseline,
14349 v8m_mainline,
031254f2
AV		 14350 NULL,
14351 NULL,
14352 NULL,
14353 v8_1m_mainline,
91e22acd
AS		 14354 /* Pseudo-architecture. */
14355 v4t_plus_v6_m
14356 };
14357
14358 /* Check we've not got a higher architecture than we know about. */
14359
9e3c6df6 14360 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 14361 {
90b6238f 14362 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 14363 return -1;
14364 }
14365
14366 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14367
14368 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14369 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14370 oldtag = T(V4T_PLUS_V6_M);
14371
14372 /* And override the new tag if we have a Tag_also_compatible_with on the
14373 input. */
14374
14375 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14376 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14377 newtag = T(V4T_PLUS_V6_M);
14378
14379 tagl = (oldtag < newtag) ? oldtag : newtag;
14380 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14381
14382 /* Architectures before V6KZ add features monotonically. */
14383 if (tagh <= TAG_CPU_ARCH_V6KZ)
14384 return result;
14385
4ed7ed8d 14386 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 14387
14388 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14389 as the canonical version. */
14390 if (result == T(V4T_PLUS_V6_M))
14391 {
14392 result = T(V4T);
14393 *secondary_compat_out = T(V6_M);
14394 }
14395 else
14396 *secondary_compat_out = -1;
14397
14398 if (result == -1)
14399 {
90b6238f 14400 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 14401 ibfd, oldtag, newtag);
14402 return -1;
14403 }
14404
14405 return result;
14406#undef T
8e79c3df
CM		 14407}
14408
ac56ee8f
MGD		 14409/* Query attributes object to see if integer divide instructions may be
14410 present in an object. */
14411static bfd_boolean
14412elf32_arm_attributes_accept_div (const obj_attribute *attr)
14413{
14414 int arch = attr[Tag_CPU_arch].i;
14415 int profile = attr[Tag_CPU_arch_profile].i;
14416
14417 switch (attr[Tag_DIV_use].i)
14418 {
14419 case 0:
14420 /* Integer divide allowed if instruction contained in archetecture. */
14421 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14422 return TRUE;
14423 else if (arch >= TAG_CPU_ARCH_V7E_M)
14424 return TRUE;
14425 else
14426 return FALSE;
14427
14428 case 1:
14429 /* Integer divide explicitly prohibited. */
14430 return FALSE;
14431
14432 default:
14433 /* Unrecognised case - treat as allowing divide everywhere. */
14434 case 2:
14435 /* Integer divide allowed in ARM state. */
14436 return TRUE;
14437 }
14438}
14439
14440/* Query attributes object to see if integer divide instructions are
14441 forbidden to be in the object. This is not the inverse of
14442 elf32_arm_attributes_accept_div. */
14443static bfd_boolean
14444elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14445{
14446 return attr[Tag_DIV_use].i == 1;
14447}
14448
ee065d83
PB		 14449/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14450 are conflicting attributes. */
906e58ca 14451
ee065d83 14452static bfd_boolean
50e03d47 14453elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 14454{
50e03d47 14455 bfd *obfd = info->output_bfd;
104d59d1
JM		 14456 obj_attribute *in_attr;
14457 obj_attribute *out_attr;
ee065d83
PB		 14458 /* Some tags have 0 = don't care, 1 = strong requirement,
14459 2 = weak requirement. */
91e22acd 14460 static const int order_021[3] = {0, 2, 1};
ee065d83 14461 int i;
91e22acd 14462 bfd_boolean result = TRUE;
9274e9de 14463 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 14464
3e6b1042
DJ		 14465 /* Skip the linker stubs file. This preserves previous behavior
14466 of accepting unknown attributes in the first input file - but
14467 is that a bug? */
14468 if (ibfd->flags & BFD_LINKER_CREATED)
14469 return TRUE;
14470
9274e9de
TG		 14471 /* Skip any input that hasn't attribute section.
14472 This enables to link object files without attribute section with
14473 any others. */
14474 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14475 return TRUE;
14476
104d59d1 14477 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 14478 {
14479 /* This is the first object. Copy the attributes. */
104d59d1 14480 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 14481
cd21e546
MGD		 14482 out_attr = elf_known_obj_attributes_proc (obfd);
14483
004ae526
PB		 14484 /* Use the Tag_null value to indicate the attributes have been
14485 initialized. */
cd21e546 14486 out_attr[0].i = 1;
004ae526 14487
cd21e546
MGD		 14488 /* We do not output objects with Tag_MPextension_use_legacy - we move
14489 the attribute's value to Tag_MPextension_use. */
14490 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14491 {
14492 if (out_attr[Tag_MPextension_use].i != 0
14493 && out_attr[Tag_MPextension_use_legacy].i
99059e56 14494 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 14495 {
14496 _bfd_error_handler
871b3ab2 14497 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 14498 "Tag_MPextension_use attributes"), ibfd);
14499 result = FALSE;
14500 }
14501
14502 out_attr[Tag_MPextension_use] =
14503 out_attr[Tag_MPextension_use_legacy];
14504 out_attr[Tag_MPextension_use_legacy].type = 0;
14505 out_attr[Tag_MPextension_use_legacy].i = 0;
14506 }
14507
14508 return result;
ee065d83
PB		 14509 }
14510
104d59d1
JM		 14511 in_attr = elf_known_obj_attributes_proc (ibfd);
14512 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 14513 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14514 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14515 {
5c294fee
TG		 14516 /* Ignore mismatches if the object doesn't use floating point or is
14517 floating point ABI independent. */
14518 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14519 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14520 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 14521 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 14522 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14523 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 14524 {
14525 _bfd_error_handler
871b3ab2 14526 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 14527 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14528 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 14529 result = FALSE;
ee065d83
PB		 14530 }
14531 }
14532
3de4a297 14533 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 14534 {
14535 /* Merge this attribute with existing attributes. */
14536 switch (i)
14537 {
14538 case Tag_CPU_raw_name:
14539 case Tag_CPU_name:
6a631e86 14540 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 14541 break;
14542
14543 case Tag_ABI_optimization_goals:
14544 case Tag_ABI_FP_optimization_goals:
14545 /* Use the first value seen. */
14546 break;
14547
14548 case Tag_CPU_arch:
91e22acd
AS		 14549 {
14550 int secondary_compat = -1, secondary_compat_out = -1;
14551 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 14552 int arch_attr;
14553 static const char *name_table[] =
14554 {
91e22acd
AS		 14555 /* These aren't real CPU names, but we can't guess
14556 that from the architecture version alone. */
14557 "Pre v4",
14558 "ARM v4",
14559 "ARM v4T",
14560 "ARM v5T",
14561 "ARM v5TE",
14562 "ARM v5TEJ",
14563 "ARM v6",
14564 "ARM v6KZ",
14565 "ARM v6T2",
14566 "ARM v6K",
14567 "ARM v7",
14568 "ARM v6-M",
bca38921 14569 "ARM v6S-M",
2fd158eb
TP		 14570 "ARM v8",
14571 "",
14572 "ARM v8-M.baseline",
14573 "ARM v8-M.mainline",
91e22acd
AS		 14574 };
14575
14576 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14577 secondary_compat = get_secondary_compatible_arch (ibfd);
14578 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 14579 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14580 &secondary_compat_out,
14581 in_attr[i].i,
14582 secondary_compat);
14583
14584 /* Return with error if failed to merge. */
14585 if (arch_attr == -1)
14586 return FALSE;
14587
14588 out_attr[i].i = arch_attr;
14589
91e22acd
AS		 14590 set_secondary_compatible_arch (obfd, secondary_compat_out);
14591
14592 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14593 if (out_attr[i].i == saved_out_attr)
14594 ; /* Leave the names alone. */
14595 else if (out_attr[i].i == in_attr[i].i)
14596 {
14597 /* The output architecture has been changed to match the
14598 input architecture. Use the input names. */
14599 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14600 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14601 : NULL;
14602 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14603 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14604 : NULL;
14605 }
14606 else
14607 {
14608 out_attr[Tag_CPU_name].s = NULL;
14609 out_attr[Tag_CPU_raw_name].s = NULL;
14610 }
14611
14612 /* If we still don't have a value for Tag_CPU_name,
14613 make one up now. Tag_CPU_raw_name remains blank. */
14614 if (out_attr[Tag_CPU_name].s == NULL
14615 && out_attr[i].i < ARRAY_SIZE (name_table))
14616 out_attr[Tag_CPU_name].s =
14617 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14618 }
14619 break;
14620
ee065d83
PB		 14621 case Tag_ARM_ISA_use:
14622 case Tag_THUMB_ISA_use:
ee065d83 14623 case Tag_WMMX_arch:
91e22acd
AS		 14624 case Tag_Advanced_SIMD_arch:
14625 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 14626 case Tag_ABI_FP_rounding:
ee065d83
PB		 14627 case Tag_ABI_FP_exceptions:
14628 case Tag_ABI_FP_user_exceptions:
14629 case Tag_ABI_FP_number_model:
75375b3e 14630 case Tag_FP_HP_extension:
91e22acd
AS		 14631 case Tag_CPU_unaligned_access:
14632 case Tag_T2EE_use:
91e22acd 14633 case Tag_MPextension_use:
a7ad558c 14634 case Tag_MVE_arch:
ee065d83
PB		 14635 /* Use the largest value specified. */
14636 if (in_attr[i].i > out_attr[i].i)
14637 out_attr[i].i = in_attr[i].i;
14638 break;
14639
75375b3e 14640 case Tag_ABI_align_preserved:
91e22acd
AS		 14641 case Tag_ABI_PCS_RO_data:
14642 /* Use the smallest value specified. */
14643 if (in_attr[i].i < out_attr[i].i)
14644 out_attr[i].i = in_attr[i].i;
14645 break;
14646
75375b3e 14647 case Tag_ABI_align_needed:
91e22acd 14648 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 14649 && (in_attr[Tag_ABI_align_preserved].i == 0
14650 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 14651 {
91e22acd
AS		 14652 /* This error message should be enabled once all non-conformant
14653 binaries in the toolchain have had the attributes set
14654 properly.
ee065d83 14655 _bfd_error_handler
871b3ab2 14656 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 14657 obfd, ibfd);
14658 result = FALSE; */
ee065d83 14659 }
91e22acd
AS		 14660 /* Fall through. */
14661 case Tag_ABI_FP_denormal:
14662 case Tag_ABI_PCS_GOT_use:
14663 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14664 value if greater than 2 (for future-proofing). */
14665 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14666 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14667 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 14668 out_attr[i].i = in_attr[i].i;
14669 break;
91e22acd 14670
75375b3e
MGD		 14671 case Tag_Virtualization_use:
14672 /* The virtualization tag effectively stores two bits of
14673 information: the intended use of TrustZone (in bit 0), and the
14674 intended use of Virtualization (in bit 1). */
14675 if (out_attr[i].i == 0)
14676 out_attr[i].i = in_attr[i].i;
14677 else if (in_attr[i].i != 0
14678 && in_attr[i].i != out_attr[i].i)
14679 {
14680 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14681 out_attr[i].i = 3;
14682 else
14683 {
14684 _bfd_error_handler
871b3ab2
AM		 14685 (_("error: %pB: unable to merge virtualization attributes "
14686 "with %pB"),
75375b3e
MGD		 14687 obfd, ibfd);
14688 result = FALSE;
14689 }
14690 }
14691 break;
91e22acd
AS		 14692
14693 case Tag_CPU_arch_profile:
14694 if (out_attr[i].i != in_attr[i].i)
14695 {
14696 /* 0 will merge with anything.
14697 'A' and 'S' merge to 'A'.
14698 'R' and 'S' merge to 'R'.
99059e56 14699 'M' and 'A|R|S' is an error. */
91e22acd
AS		 14700 if (out_attr[i].i == 0
14701 || (out_attr[i].i == 'S'
14702 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14703 out_attr[i].i = in_attr[i].i;
14704 else if (in_attr[i].i == 0
14705 || (in_attr[i].i == 'S'
14706 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 14707 ; /* Do nothing. */
91e22acd
AS		 14708 else
14709 {
14710 _bfd_error_handler
90b6238f 14711 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 14712 ibfd,
14713 in_attr[i].i ? in_attr[i].i : '0',
14714 out_attr[i].i ? out_attr[i].i : '0');
14715 result = FALSE;
14716 }
14717 }
14718 break;
15afaa63
TP		 14719
14720 case Tag_DSP_extension:
14721 /* No need to change output value if any of:
14722 - pre (<=) ARMv5T input architecture (do not have DSP)
14723 - M input profile not ARMv7E-M and do not have DSP. */
14724 if (in_attr[Tag_CPU_arch].i <= 3
14725 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14726 && in_attr[Tag_CPU_arch].i != 13
14727 && in_attr[i].i == 0))
14728 ; /* Do nothing. */
14729 /* Output value should be 0 if DSP part of architecture, ie.
14730 - post (>=) ARMv5te architecture output
14731 - A, R or S profile output or ARMv7E-M output architecture. */
14732 else if (out_attr[Tag_CPU_arch].i >= 4
14733 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14734 || out_attr[Tag_CPU_arch_profile].i == 'R'
14735 || out_attr[Tag_CPU_arch_profile].i == 'S'
14736 || out_attr[Tag_CPU_arch].i == 13))
14737 out_attr[i].i = 0;
14738 /* Otherwise, DSP instructions are added and not part of output
14739 architecture. */
14740 else
14741 out_attr[i].i = 1;
14742 break;
14743
75375b3e 14744 case Tag_FP_arch:
62f3b8c8 14745 {
4547cb56
NC		 14746 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14747 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14748 when it's 0. It might mean absence of FP hardware if
99654aaf 14749 Tag_FP_arch is zero. */
4547cb56 14750
a715796b 14751#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 14752 static const struct
14753 {
14754 int ver;
14755 int regs;
bca38921 14756 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 14757 {
14758 {0, 0},
14759 {1, 16},
14760 {2, 16},
14761 {3, 32},
14762 {3, 16},
14763 {4, 32},
bca38921 14764 {4, 16},
a715796b
TG		 14765 {8, 32},
14766 {8, 16}
62f3b8c8
PB		 14767 };
14768 int ver;
14769 int regs;
14770 int newval;
14771
4547cb56
NC		 14772 /* If the output has no requirement about FP hardware,
14773 follow the requirement of the input. */
14774 if (out_attr[i].i == 0)
14775 {
4ec192e6
RE		 14776 /* This assert is still reasonable, we shouldn't
14777 produce the suspicious build attribute
14778 combination (See below for in_attr). */
4547cb56
NC		 14779 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14780 out_attr[i].i = in_attr[i].i;
14781 out_attr[Tag_ABI_HardFP_use].i
14782 = in_attr[Tag_ABI_HardFP_use].i;
14783 break;
14784 }
14785 /* If the input has no requirement about FP hardware, do
14786 nothing. */
14787 else if (in_attr[i].i == 0)
14788 {
4ec192e6
RE		 14789 /* We used to assert that Tag_ABI_HardFP_use was
14790 zero here, but we should never assert when
14791 consuming an object file that has suspicious
14792 build attributes. The single precision variant
14793 of 'no FP architecture' is still 'no FP
14794 architecture', so we just ignore the tag in this
14795 case. */
4547cb56
NC		 14796 break;
14797 }
14798
14799 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 14800 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 14801
14802 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14803 do nothing. */
14804 if (in_attr[Tag_ABI_HardFP_use].i == 0
14805 && out_attr[Tag_ABI_HardFP_use].i == 0)
14806 ;
14807 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 14808 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 14809 else if (in_attr[Tag_ABI_HardFP_use].i
14810 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 14811 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 14812
14813 /* Now we can handle Tag_FP_arch. */
14814
bca38921
MGD		 14815 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14816 pick the biggest. */
14817 if (in_attr[i].i >= VFP_VERSION_COUNT
14818 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 14819 {
14820 out_attr[i] = in_attr[i];
14821 break;
14822 }
14823 /* The output uses the superset of input features
14824 (ISA version) and registers. */
14825 ver = vfp_versions[in_attr[i].i].ver;
14826 if (ver < vfp_versions[out_attr[i].i].ver)
14827 ver = vfp_versions[out_attr[i].i].ver;
14828 regs = vfp_versions[in_attr[i].i].regs;
14829 if (regs < vfp_versions[out_attr[i].i].regs)
14830 regs = vfp_versions[out_attr[i].i].regs;
14831 /* This assumes all possible supersets are also a valid
99059e56 14832 options. */
bca38921 14833 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 14834 {
14835 if (regs == vfp_versions[newval].regs
14836 && ver == vfp_versions[newval].ver)
14837 break;
14838 }
14839 out_attr[i].i = newval;
14840 }
b1cc4aeb 14841 break;
ee065d83
PB		 14842 case Tag_PCS_config:
14843 if (out_attr[i].i == 0)
14844 out_attr[i].i = in_attr[i].i;
b6009aca 14845 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14846 {
14847 /* It's sometimes ok to mix different configs, so this is only
99059e56 14848 a warning. */
ee065d83 14849 _bfd_error_handler
90b6238f 14850 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14851 }
14852 break;
14853 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14854 if (in_attr[i].i != out_attr[i].i
14855 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14856 && in_attr[i].i != AEABI_R9_unused)
14857 {
14858 _bfd_error_handler
90b6238f 14859 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14860 result = FALSE;
ee065d83
PB		 14861 }
14862 if (out_attr[i].i == AEABI_R9_unused)
14863 out_attr[i].i = in_attr[i].i;
14864 break;
14865 case Tag_ABI_PCS_RW_data:
14866 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14867 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14868 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14869 {
14870 _bfd_error_handler
871b3ab2 14871 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14872 ibfd);
91e22acd 14873 result = FALSE;
ee065d83
PB		 14874 }
14875 /* Use the smallest value specified. */
14876 if (in_attr[i].i < out_attr[i].i)
14877 out_attr[i].i = in_attr[i].i;
14878 break;
ee065d83 14879 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14880 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14881 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14882 {
14883 _bfd_error_handler
871b3ab2 14884 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14885 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14886 }
a9dc9481 14887 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14888 out_attr[i].i = in_attr[i].i;
14889 break;
ee065d83
PB		 14890 case Tag_ABI_enum_size:
14891 if (in_attr[i].i != AEABI_enum_unused)
14892 {
14893 if (out_attr[i].i == AEABI_enum_unused
14894 || out_attr[i].i == AEABI_enum_forced_wide)
14895 {
14896 /* The existing object is compatible with anything.
14897 Use whatever requirements the new object has. */
14898 out_attr[i].i = in_attr[i].i;
14899 }
14900 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14901 && out_attr[i].i != in_attr[i].i
0ffa91dd 14902 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14903 {
91e22acd 14904 static const char *aeabi_enum_names[] =
bf21ed78 14905 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14906 const char *in_name =
14907 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14908 ? aeabi_enum_names[in_attr[i].i]
14909 : "<unknown>";
14910 const char *out_name =
14911 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14912 ? aeabi_enum_names[out_attr[i].i]
14913 : "<unknown>";
ee065d83 14914 _bfd_error_handler
871b3ab2 14915 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14916 ibfd, in_name, out_name);
ee065d83
PB		 14917 }
14918 }
14919 break;
14920 case Tag_ABI_VFP_args:
14921 /* Aready done. */
14922 break;
14923 case Tag_ABI_WMMX_args:
14924 if (in_attr[i].i != out_attr[i].i)
14925 {
14926 _bfd_error_handler
871b3ab2 14927 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14928 ibfd, obfd);
91e22acd 14929 result = FALSE;
ee065d83
PB		 14930 }
14931 break;
7b86a9fa
AS		 14932 case Tag_compatibility:
14933 /* Merged in target-independent code. */
14934 break;
91e22acd 14935 case Tag_ABI_HardFP_use:
4547cb56 14936 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14937 break;
14938 case Tag_ABI_FP_16bit_format:
14939 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14940 {
14941 if (in_attr[i].i != out_attr[i].i)
14942 {
14943 _bfd_error_handler
871b3ab2 14944 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 14945 ibfd, obfd);
14946 result = FALSE;
14947 }
14948 }
14949 if (in_attr[i].i != 0)
14950 out_attr[i].i = in_attr[i].i;
14951 break;
7b86a9fa 14952
cd21e546 14953 case Tag_DIV_use:
ac56ee8f
MGD		 14954 /* A value of zero on input means that the divide instruction may
14955 be used if available in the base architecture as specified via
14956 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14957 the user did not want divide instructions. A value of 2
14958 explicitly means that divide instructions were allowed in ARM
14959 and Thumb state. */
14960 if (in_attr[i].i == out_attr[i].i)
14961 /* Do nothing. */ ;
14962 else if (elf32_arm_attributes_forbid_div (in_attr)
14963 && !elf32_arm_attributes_accept_div (out_attr))
14964 out_attr[i].i = 1;
14965 else if (elf32_arm_attributes_forbid_div (out_attr)
14966 && elf32_arm_attributes_accept_div (in_attr))
14967 out_attr[i].i = in_attr[i].i;
14968 else if (in_attr[i].i == 2)
14969 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14970 break;
14971
14972 case Tag_MPextension_use_legacy:
14973 /* We don't output objects with Tag_MPextension_use_legacy - we
14974 move the value to Tag_MPextension_use. */
14975 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14976 {
14977 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14978 {
14979 _bfd_error_handler
871b3ab2 14980 (_("%pB has both the current and legacy "
b38cadfb 14981 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14982 ibfd);
14983 result = FALSE;
14984 }
14985 }
14986
14987 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14988 out_attr[Tag_MPextension_use] = in_attr[i];
14989
14990 break;
14991
91e22acd 14992 case Tag_nodefaults:
2d0bb761
AS		 14993 /* This tag is set if it exists, but the value is unused (and is
14994 typically zero). We don't actually need to do anything here -
14995 the merge happens automatically when the type flags are merged
14996 below. */
91e22acd
AS		 14997 break;
14998 case Tag_also_compatible_with:
14999 /* Already done in Tag_CPU_arch. */
15000 break;
15001 case Tag_conformance:
15002 /* Keep the attribute if it matches. Throw it away otherwise.
15003 No attribute means no claim to conform. */
15004 if (!in_attr[i].s || !out_attr[i].s
15005 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
15006 out_attr[i].s = NULL;
15007 break;
3cfad14c 15008
91e22acd 15009 default:
e8b36cd1
JM		 15010 result
15011 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 15012 }
15013
15014 /* If out_attr was copied from in_attr then it won't have a type yet. */
15015 if (in_attr[i].type && !out_attr[i].type)
15016 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 15017 }
15018
104d59d1 15019 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 15020 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 15021 return FALSE;
ee065d83 15022
104d59d1 15023 /* Check for any attributes not known on ARM. */
e8b36cd1 15024 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 15025
91e22acd 15026 return result;
252b5132
RH		 15027}
15028
3a4a14e9
PB		 15029
15030/* Return TRUE if the two EABI versions are incompatible. */
15031
15032static bfd_boolean
15033elf32_arm_versions_compatible (unsigned iver, unsigned over)
15034{
15035 /* v4 and v5 are the same spec before and after it was released,
15036 so allow mixing them. */
15037 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
15038 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
15039 return TRUE;
15040
15041 return (iver == over);
15042}
15043
252b5132
RH		 15044/* Merge backend specific data from an object file to the output
15045 object file when linking. */
9b485d32 15046
b34976b6 15047static bfd_boolean
50e03d47 15048elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 15049
9b485d32
NC		 15050/* Display the flags field. */
15051
b34976b6 15052static bfd_boolean
57e8b36a 15053elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 15054{
fc830a83
NC		 15055 FILE * file = (FILE *) ptr;
15056 unsigned long flags;
252b5132
RH		 15057
15058 BFD_ASSERT (abfd != NULL && ptr != NULL);
15059
15060 /* Print normal ELF private data. */
15061 _bfd_elf_print_private_bfd_data (abfd, ptr);
15062
fc830a83 15063 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 15064 /* Ignore init flag - it may not be set, despite the flags field
15065 containing valid data. */
252b5132 15066
9b485d32 15067 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 15068
fc830a83
NC		 15069 switch (EF_ARM_EABI_VERSION (flags))
15070 {
15071 case EF_ARM_EABI_UNKNOWN:
4cc11e76 15072 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 15073 official ARM ELF extended ABI. Hence they are only decoded if
15074 the EABI version is not set. */
fd2ec330 15075 if (flags & EF_ARM_INTERWORK)
9b485d32 15076 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 15077
fd2ec330 15078 if (flags & EF_ARM_APCS_26)
6c571f00 15079 fprintf (file, " [APCS-26]");
fc830a83 15080 else
6c571f00 15081 fprintf (file, " [APCS-32]");
9a5aca8c 15082
96a846ea
RE		 15083 if (flags & EF_ARM_VFP_FLOAT)
15084 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 15085 else if (flags & EF_ARM_MAVERICK_FLOAT)
15086 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 15087 else
15088 fprintf (file, _(" [FPA float format]"));
15089
fd2ec330 15090 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 15091 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 15092
fd2ec330 15093 if (flags & EF_ARM_PIC)
9b485d32 15094 fprintf (file, _(" [position independent]"));
fc830a83 15095
fd2ec330 15096 if (flags & EF_ARM_NEW_ABI)
9b485d32 15097 fprintf (file, _(" [new ABI]"));
9a5aca8c 15098
fd2ec330 15099 if (flags & EF_ARM_OLD_ABI)
9b485d32 15100 fprintf (file, _(" [old ABI]"));
9a5aca8c 15101
fd2ec330 15102 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 15103 fprintf (file, _(" [software FP]"));
9a5aca8c 15104
96a846ea
RE		 15105 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
15106 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 15107 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
15108 | EF_ARM_MAVERICK_FLOAT);
fc830a83 15109 break;
9a5aca8c 15110
fc830a83 15111 case EF_ARM_EABI_VER1:
9b485d32 15112 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 15113
fc830a83 15114 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 15115 fprintf (file, _(" [sorted symbol table]"));
fc830a83 15116 else
9b485d32 15117 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 15118
fc830a83
NC		 15119 flags &= ~ EF_ARM_SYMSARESORTED;
15120 break;
9a5aca8c 15121
fd2ec330
PB		 15122 case EF_ARM_EABI_VER2:
15123 fprintf (file, _(" [Version2 EABI]"));
15124
15125 if (flags & EF_ARM_SYMSARESORTED)
15126 fprintf (file, _(" [sorted symbol table]"));
15127 else
15128 fprintf (file, _(" [unsorted symbol table]"));
15129
15130 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
15131 fprintf (file, _(" [dynamic symbols use segment index]"));
15132
15133 if (flags & EF_ARM_MAPSYMSFIRST)
15134 fprintf (file, _(" [mapping symbols precede others]"));
15135
99e4ae17 15136 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 15137 | EF_ARM_MAPSYMSFIRST);
15138 break;
15139
d507cf36
PB		 15140 case EF_ARM_EABI_VER3:
15141 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 15142 break;
15143
15144 case EF_ARM_EABI_VER4:
15145 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 15146 goto eabi;
d507cf36 15147
3a4a14e9
PB		 15148 case EF_ARM_EABI_VER5:
15149 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 15150
15151 if (flags & EF_ARM_ABI_FLOAT_SOFT)
15152 fprintf (file, _(" [soft-float ABI]"));
15153
15154 if (flags & EF_ARM_ABI_FLOAT_HARD)
15155 fprintf (file, _(" [hard-float ABI]"));
15156
15157 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
15158
3a4a14e9 15159 eabi:
d507cf36
PB		 15160 if (flags & EF_ARM_BE8)
15161 fprintf (file, _(" [BE8]"));
15162
15163 if (flags & EF_ARM_LE8)
15164 fprintf (file, _(" [LE8]"));
15165
15166 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
15167 break;
15168
fc830a83 15169 default:
9b485d32 15170 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 15171 break;
15172 }
252b5132 15173
fc830a83 15174 flags &= ~ EF_ARM_EABIMASK;
252b5132 15175
fc830a83 15176 if (flags & EF_ARM_RELEXEC)
9b485d32 15177 fprintf (file, _(" [relocatable executable]"));
252b5132 15178
18a20338
CL		 15179 if (flags & EF_ARM_PIC)
15180 fprintf (file, _(" [position independent]"));
15181
15182 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
15183 fprintf (file, _(" [FDPIC ABI supplement]"));
15184
15185 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 15186
15187 if (flags)
9b485d32 15188 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 15189
252b5132
RH		 15190 fputc ('\n', file);
15191
b34976b6 15192 return TRUE;
252b5132
RH		 15193}
15194
15195static int
57e8b36a 15196elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 15197{
2f0ca46a
NC		 15198 switch (ELF_ST_TYPE (elf_sym->st_info))
15199 {
15200 case STT_ARM_TFUNC:
15201 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 15202
2f0ca46a
NC		 15203 case STT_ARM_16BIT:
15204 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15205 This allows us to distinguish between data used by Thumb instructions
15206 and non-data (which is probably code) inside Thumb regions of an
15207 executable. */
1a0eb693 15208 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 15209 return ELF_ST_TYPE (elf_sym->st_info);
15210 break;
9a5aca8c 15211
ce855c42
NC		 15212 default:
15213 break;
2f0ca46a
NC		 15214 }
15215
15216 return type;
252b5132 15217}
f21f3fe0 15218
252b5132 15219static asection *
07adf181
AM		 15220elf32_arm_gc_mark_hook (asection *sec,
15221 struct bfd_link_info *info,
15222 Elf_Internal_Rela *rel,
15223 struct elf_link_hash_entry *h,
15224 Elf_Internal_Sym *sym)
252b5132
RH		 15225{
15226 if (h != NULL)
07adf181 15227 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 15228 {
15229 case R_ARM_GNU_VTINHERIT:
15230 case R_ARM_GNU_VTENTRY:
07adf181
AM		 15231 return NULL;
15232 }
9ad5cbcf 15233
07adf181 15234 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 15235}
15236
780a67af
NC		 15237/* Look through the relocs for a section during the first phase. */
15238
b34976b6 15239static bfd_boolean
57e8b36a
NC		 15240elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
15241 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 15242{
b34976b6
AM		 15243 Elf_Internal_Shdr *symtab_hdr;
15244 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 15245 const Elf_Internal_Rela *rel;
15246 const Elf_Internal_Rela *rel_end;
15247 bfd *dynobj;
5e681ec4 15248 asection *sreloc;
5e681ec4 15249 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 15250 bfd_boolean call_reloc_p;
15251 bfd_boolean may_become_dynamic_p;
15252 bfd_boolean may_need_local_target_p;
ce98a316 15253 unsigned long nsyms;
9a5aca8c 15254
0e1862bb 15255 if (bfd_link_relocatable (info))
b34976b6 15256 return TRUE;
9a5aca8c 15257
0ffa91dd
NC		 15258 BFD_ASSERT (is_arm_elf (abfd));
15259
5e681ec4 15260 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15261 if (htab == NULL)
15262 return FALSE;
15263
5e681ec4 15264 sreloc = NULL;
9a5aca8c 15265
67687978
PB		 15266 /* Create dynamic sections for relocatable executables so that we can
15267 copy relocations. */
15268 if (htab->root.is_relocatable_executable
15269 && ! htab->root.dynamic_sections_created)
15270 {
15271 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15272 return FALSE;
15273 }
15274
cbc704f3
RS		 15275 if (htab->root.dynobj == NULL)
15276 htab->root.dynobj = abfd;
34e77a92
RS		 15277 if (!create_ifunc_sections (info))
15278 return FALSE;
cbc704f3
RS		 15279
15280 dynobj = htab->root.dynobj;
15281
0ffa91dd 15282 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 15283 sym_hashes = elf_sym_hashes (abfd);
ce98a316 15284 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 15285
252b5132
RH		 15286 rel_end = relocs + sec->reloc_count;
15287 for (rel = relocs; rel < rel_end; rel++)
15288 {
34e77a92 15289 Elf_Internal_Sym *isym;
252b5132 15290 struct elf_link_hash_entry *h;
b7693d02 15291 struct elf32_arm_link_hash_entry *eh;
d42c267e 15292 unsigned int r_symndx;
eb043451 15293 int r_type;
9a5aca8c 15294
252b5132 15295 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 15296 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 15297 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 15298
ce98a316
NC		 15299 if (r_symndx >= nsyms
15300 /* PR 9934: It is possible to have relocations that do not
15301 refer to symbols, thus it is also possible to have an
15302 object file containing relocations but no symbol table. */
cf35638d 15303 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 15304 {
871b3ab2 15305 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 15306 r_symndx);
ba93b8ac
DJ		 15307 return FALSE;
15308 }
15309
34e77a92
RS		 15310 h = NULL;
15311 isym = NULL;
15312 if (nsyms > 0)
973a3492 15313 {
34e77a92
RS		 15314 if (r_symndx < symtab_hdr->sh_info)
15315 {
15316 /* A local symbol. */
f1dfbfdb 15317 isym = bfd_sym_from_r_symndx (&htab->root.sym_cache,
34e77a92
RS		 15318 abfd, r_symndx);
15319 if (isym == NULL)
15320 return FALSE;
15321 }
15322 else
15323 {
15324 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15325 while (h->root.type == bfd_link_hash_indirect
15326 || h->root.type == bfd_link_hash_warning)
15327 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15328 }
973a3492 15329 }
9a5aca8c 15330
b7693d02
DJ		 15331 eh = (struct elf32_arm_link_hash_entry *) h;
15332
f6e32f6d
RS		 15333 call_reloc_p = FALSE;
15334 may_become_dynamic_p = FALSE;
15335 may_need_local_target_p = FALSE;
15336
0855e32b
NS		 15337 /* Could be done earlier, if h were already available. */
15338 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 15339 switch (r_type)
99059e56 15340 {
e8b09b87
CL		 15341 case R_ARM_GOTOFFFUNCDESC:
15342 {
15343 if (h == NULL)
15344 {
15345 if (!elf32_arm_allocate_local_sym_info (abfd))
15346 return FALSE;
15347 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].gotofffuncdesc_cnt += 1;
15348 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15349 }
15350 else
15351 {
15352 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15353 }
15354 }
15355 break;
15356
15357 case R_ARM_GOTFUNCDESC:
15358 {
15359 if (h == NULL)
15360 {
15361 /* Such a relocation is not supposed to be generated
15362 by gcc on a static function. */
15363 /* Anyway if needed it could be handled. */
15364 abort();
15365 }
15366 else
15367 {
15368 eh->fdpic_cnts.gotfuncdesc_cnt++;
15369 }
15370 }
15371 break;
15372
15373 case R_ARM_FUNCDESC:
15374 {
15375 if (h == NULL)
15376 {
15377 if (!elf32_arm_allocate_local_sym_info (abfd))
15378 return FALSE;
15379 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_cnt += 1;
15380 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15381 }
15382 else
15383 {
15384 eh->fdpic_cnts.funcdesc_cnt++;
15385 }
15386 }
15387 break;
15388
5e681ec4 15389 case R_ARM_GOT32:
eb043451 15390 case R_ARM_GOT_PREL:
ba93b8ac 15391 case R_ARM_TLS_GD32:
5c5a4843 15392 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 15393 case R_ARM_TLS_IE32:
5c5a4843 15394 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 15395 case R_ARM_TLS_GOTDESC:
15396 case R_ARM_TLS_DESCSEQ:
15397 case R_ARM_THM_TLS_DESCSEQ:
15398 case R_ARM_TLS_CALL:
15399 case R_ARM_THM_TLS_CALL:
5e681ec4 15400 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 15401 {
15402 int tls_type, old_tls_type;
5e681ec4 15403
ba93b8ac
DJ		 15404 switch (r_type)
15405 {
15406 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
5c5a4843 15407 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
b38cadfb 15408
ba93b8ac 15409 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
5c5a4843 15410 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
b38cadfb 15411
0855e32b
NS		 15412 case R_ARM_TLS_GOTDESC:
15413 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15414 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15415 tls_type = GOT_TLS_GDESC; break;
b38cadfb 15416
ba93b8ac
DJ		 15417 default: tls_type = GOT_NORMAL; break;
15418 }
252b5132 15419
0e1862bb 15420 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 15421 info->flags |= DF_STATIC_TLS;
15422
ba93b8ac
DJ		 15423 if (h != NULL)
15424 {
15425 h->got.refcount++;
15426 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15427 }
15428 else
15429 {
ba93b8ac 15430 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 15431 if (!elf32_arm_allocate_local_sym_info (abfd))
15432 return FALSE;
15433 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 15434 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15435 }
15436
0855e32b 15437 /* If a variable is accessed with both tls methods, two
99059e56 15438 slots may be created. */
0855e32b
NS		 15439 if (GOT_TLS_GD_ANY_P (old_tls_type)
15440 && GOT_TLS_GD_ANY_P (tls_type))
15441 tls_type |= old_tls_type;
15442
15443 /* We will already have issued an error message if there
15444 is a TLS/non-TLS mismatch, based on the symbol
15445 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 15446 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15447 && tls_type != GOT_NORMAL)
15448 tls_type |= old_tls_type;
15449
0855e32b 15450 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 15451 method, we're able to relax. Turn off the GDESC flag,
15452 without messing up with any other kind of tls types
6a631e86 15453 that may be involved. */
0855e32b
NS		 15454 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15455 tls_type &= ~GOT_TLS_GDESC;
15456
ba93b8ac
DJ		 15457 if (old_tls_type != tls_type)
15458 {
15459 if (h != NULL)
15460 elf32_arm_hash_entry (h)->tls_type = tls_type;
15461 else
15462 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15463 }
15464 }
8029a119 15465 /* Fall through. */
ba93b8ac
DJ		 15466
15467 case R_ARM_TLS_LDM32:
5c5a4843
CL		 15468 case R_ARM_TLS_LDM32_FDPIC:
15469 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
ba93b8ac 15470 htab->tls_ldm_got.refcount++;
8029a119 15471 /* Fall through. */
252b5132 15472
c19d1205 15473 case R_ARM_GOTOFF32:
5e681ec4 15474 case R_ARM_GOTPC:
cbc704f3
RS		 15475 if (htab->root.sgot == NULL
15476 && !create_got_section (htab->root.dynobj, info))
15477 return FALSE;
252b5132
RH		 15478 break;
15479
252b5132 15480 case R_ARM_PC24:
7359ea65 15481 case R_ARM_PLT32:
5b5bb741
PB		 15482 case R_ARM_CALL:
15483 case R_ARM_JUMP24:
eb043451 15484 case R_ARM_PREL31:
c19d1205 15485 case R_ARM_THM_CALL:
bd97cb95
DJ		 15486 case R_ARM_THM_JUMP24:
15487 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 15488 call_reloc_p = TRUE;
15489 may_need_local_target_p = TRUE;
15490 break;
15491
15492 case R_ARM_ABS12:
15493 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15494 ldr __GOTT_INDEX__ offsets. */
90c14f0c 15495 if (htab->root.target_os != is_vxworks)
f6e32f6d
RS		 15496 {
15497 may_need_local_target_p = TRUE;
15498 break;
15499 }
aebf9be7 15500 else goto jump_over;
9eaff861 15501
f6e32f6d 15502 /* Fall through. */
39623e12 15503
96c23d59
JM		 15504 case R_ARM_MOVW_ABS_NC:
15505 case R_ARM_MOVT_ABS:
15506 case R_ARM_THM_MOVW_ABS_NC:
15507 case R_ARM_THM_MOVT_ABS:
0e1862bb 15508 if (bfd_link_pic (info))
96c23d59 15509 {
4eca0228 15510 _bfd_error_handler
871b3ab2 15511 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 15512 abfd, elf32_arm_howto_table_1[r_type].name,
15513 (h) ? h->root.root.string : "a local symbol");
15514 bfd_set_error (bfd_error_bad_value);
15515 return FALSE;
15516 }
15517
15518 /* Fall through. */
39623e12
PB		 15519 case R_ARM_ABS32:
15520 case R_ARM_ABS32_NOI:
aebf9be7 15521 jump_over:
0e1862bb 15522 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 15523 {
15524 h->pointer_equality_needed = 1;
15525 }
15526 /* Fall through. */
39623e12
PB		 15527 case R_ARM_REL32:
15528 case R_ARM_REL32_NOI:
b6895b4f
PB		 15529 case R_ARM_MOVW_PREL_NC:
15530 case R_ARM_MOVT_PREL:
b6895b4f
PB		 15531 case R_ARM_THM_MOVW_PREL_NC:
15532 case R_ARM_THM_MOVT_PREL:
39623e12 15533
b7693d02 15534 /* Should the interworking branches be listed here? */
e8b09b87
CL		 15535 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15536 || htab->fdpic_p)
34e77a92
RS		 15537 && (sec->flags & SEC_ALLOC) != 0)
15538 {
15539 if (h == NULL
469a3493 15540 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 15541 {
15542 /* In shared libraries and relocatable executables,
15543 we treat local relative references as calls;
15544 see the related SYMBOL_CALLS_LOCAL code in
15545 allocate_dynrelocs. */
15546 call_reloc_p = TRUE;
15547 may_need_local_target_p = TRUE;
15548 }
15549 else
15550 /* We are creating a shared library or relocatable
15551 executable, and this is a reloc against a global symbol,
15552 or a non-PC-relative reloc against a local symbol.
15553 We may need to copy the reloc into the output. */
15554 may_become_dynamic_p = TRUE;
15555 }
f6e32f6d
RS		 15556 else
15557 may_need_local_target_p = TRUE;
252b5132
RH		 15558 break;
15559
99059e56
RM		 15560 /* This relocation describes the C++ object vtable hierarchy.
15561 Reconstruct it for later use during GC. */
15562 case R_ARM_GNU_VTINHERIT:
15563 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15564 return FALSE;
15565 break;
15566
15567 /* This relocation describes which C++ vtable entries are actually
15568 used. Record for later use during GC. */
15569 case R_ARM_GNU_VTENTRY:
a0ea3a14 15570 if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
99059e56
RM		 15571 return FALSE;
15572 break;
15573 }
f6e32f6d
RS		 15574
15575 if (h != NULL)
15576 {
15577 if (call_reloc_p)
15578 /* We may need a .plt entry if the function this reloc
15579 refers to is in a different object, regardless of the
15580 symbol's type. We can't tell for sure yet, because
15581 something later might force the symbol local. */
15582 h->needs_plt = 1;
15583 else if (may_need_local_target_p)
15584 /* If this reloc is in a read-only section, we might
15585 need a copy reloc. We can't check reliably at this
15586 stage whether the section is read-only, as input
15587 sections have not yet been mapped to output sections.
15588 Tentatively set the flag for now, and correct in
15589 adjust_dynamic_symbol. */
15590 h->non_got_ref = 1;
15591 }
15592
34e77a92
RS		 15593 if (may_need_local_target_p
15594 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 15595 {
34e77a92
RS		 15596 union gotplt_union *root_plt;
15597 struct arm_plt_info *arm_plt;
15598 struct arm_local_iplt_info *local_iplt;
15599
15600 if (h != NULL)
15601 {
15602 root_plt = &h->plt;
15603 arm_plt = &eh->plt;
15604 }
15605 else
15606 {
15607 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15608 if (local_iplt == NULL)
15609 return FALSE;
15610 root_plt = &local_iplt->root;
15611 arm_plt = &local_iplt->arm;
15612 }
15613
f6e32f6d
RS		 15614 /* If the symbol is a function that doesn't bind locally,
15615 this relocation will need a PLT entry. */
a8c887dd
NC		 15616 if (root_plt->refcount != -1)
15617 root_plt->refcount += 1;
34e77a92
RS		 15618
15619 if (!call_reloc_p)
15620 arm_plt->noncall_refcount++;
f6e32f6d
RS		 15621
15622 /* It's too early to use htab->use_blx here, so we have to
15623 record possible blx references separately from
15624 relocs that definitely need a thumb stub. */
15625
15626 if (r_type == R_ARM_THM_CALL)
34e77a92 15627 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 15628
15629 if (r_type == R_ARM_THM_JUMP24
15630 || r_type == R_ARM_THM_JUMP19)
34e77a92 15631 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 15632 }
15633
15634 if (may_become_dynamic_p)
15635 {
15636 struct elf_dyn_relocs *p, **head;
15637
15638 /* Create a reloc section in dynobj. */
15639 if (sreloc == NULL)
15640 {
15641 sreloc = _bfd_elf_make_dynamic_reloc_section
15642 (sec, dynobj, 2, abfd, ! htab->use_rel);
15643
15644 if (sreloc == NULL)
15645 return FALSE;
15646
15647 /* BPABI objects never have dynamic relocations mapped. */
90c14f0c 15648 if (htab->root.target_os == is_symbian)
f6e32f6d
RS		 15649 {
15650 flagword flags;
15651
fd361982 15652 flags = bfd_section_flags (sreloc);
f6e32f6d 15653 flags &= ~(SEC_LOAD | SEC_ALLOC);
fd361982 15654 bfd_set_section_flags (sreloc, flags);
f6e32f6d
RS		 15655 }
15656 }
15657
15658 /* If this is a global symbol, count the number of
15659 relocations we need for this symbol. */
15660 if (h != NULL)
190eb1dd 15661 head = &h->dyn_relocs;
f6e32f6d
RS		 15662 else
15663 {
34e77a92
RS		 15664 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15665 if (head == NULL)
f6e32f6d 15666 return FALSE;
f6e32f6d
RS		 15667 }
15668
15669 p = *head;
15670 if (p == NULL || p->sec != sec)
15671 {
986f0783 15672 size_t amt = sizeof *p;
f6e32f6d
RS		 15673
15674 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15675 if (p == NULL)
15676 return FALSE;
15677 p->next = *head;
15678 *head = p;
15679 p->sec = sec;
15680 p->count = 0;
15681 p->pc_count = 0;
15682 }
15683
469a3493 15684 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 15685 p->pc_count += 1;
15686 p->count += 1;
e8b09b87
CL		 15687 if (h == NULL && htab->fdpic_p && !bfd_link_pic(info)
15688 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI) {
15689 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15690 that will become rofixup. */
15691 /* This is due to the fact that we suppose all will become rofixup. */
15692 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15693 _bfd_error_handler
15694 (_("FDPIC does not yet support %s relocation"
15695 " to become dynamic for executable"),
15696 elf32_arm_howto_table_1[r_type].name);
15697 abort();
15698 }
f6e32f6d 15699 }
252b5132 15700 }
f21f3fe0 15701
b34976b6 15702 return TRUE;
252b5132
RH		 15703}
15704
9eaff861
AO		 15705static void
15706elf32_arm_update_relocs (asection *o,
15707 struct bfd_elf_section_reloc_data *reldata)
15708{
15709 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15710 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15711 const struct elf_backend_data *bed;
15712 _arm_elf_section_data *eado;
15713 struct bfd_link_order *p;
15714 bfd_byte *erela_head, *erela;
15715 Elf_Internal_Rela *irela_head, *irela;
15716 Elf_Internal_Shdr *rel_hdr;
15717 bfd *abfd;
15718 unsigned int count;
15719
15720 eado = get_arm_elf_section_data (o);
15721
15722 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15723 return;
15724
15725 abfd = o->owner;
15726 bed = get_elf_backend_data (abfd);
15727 rel_hdr = reldata->hdr;
15728
15729 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15730 {
15731 swap_in = bed->s->swap_reloc_in;
15732 swap_out = bed->s->swap_reloc_out;
15733 }
15734 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15735 {
15736 swap_in = bed->s->swap_reloca_in;
15737 swap_out = bed->s->swap_reloca_out;
15738 }
15739 else
15740 abort ();
15741
15742 erela_head = rel_hdr->contents;
15743 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15744 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15745
15746 erela = erela_head;
15747 irela = irela_head;
15748 count = 0;
15749
15750 for (p = o->map_head.link_order; p; p = p->next)
15751 {
15752 if (p->type == bfd_section_reloc_link_order
15753 || p->type == bfd_symbol_reloc_link_order)
15754 {
15755 (*swap_in) (abfd, erela, irela);
15756 erela += rel_hdr->sh_entsize;
15757 irela++;
15758 count++;
15759 }
15760 else if (p->type == bfd_indirect_link_order)
15761 {
15762 struct bfd_elf_section_reloc_data *input_reldata;
15763 arm_unwind_table_edit *edit_list, *edit_tail;
15764 _arm_elf_section_data *eadi;
15765 bfd_size_type j;
15766 bfd_vma offset;
15767 asection *i;
15768
15769 i = p->u.indirect.section;
15770
15771 eadi = get_arm_elf_section_data (i);
15772 edit_list = eadi->u.exidx.unwind_edit_list;
15773 edit_tail = eadi->u.exidx.unwind_edit_tail;
539300fb 15774 offset = i->output_offset;
9eaff861
AO		 15775
15776 if (eadi->elf.rel.hdr &&
15777 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15778 input_reldata = &eadi->elf.rel;
15779 else if (eadi->elf.rela.hdr &&
15780 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15781 input_reldata = &eadi->elf.rela;
15782 else
15783 abort ();
15784
15785 if (edit_list)
15786 {
15787 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15788 {
15789 arm_unwind_table_edit *edit_node, *edit_next;
15790 bfd_vma bias;
c48182bf 15791 bfd_vma reloc_index;
9eaff861
AO		 15792
15793 (*swap_in) (abfd, erela, irela);
c48182bf 15794 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 15795
15796 bias = 0;
15797 edit_node = edit_list;
15798 for (edit_next = edit_list;
c48182bf 15799 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 15800 edit_next = edit_node->next)
15801 {
15802 bias++;
15803 edit_node = edit_next;
15804 }
15805
15806 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 15807 || edit_node->index != reloc_index)
9eaff861
AO		 15808 {
15809 irela->r_offset -= bias * 8;
15810 irela++;
15811 count++;
15812 }
15813
15814 erela += rel_hdr->sh_entsize;
15815 }
15816
15817 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15818 {
15819 /* New relocation entity. */
15820 asection *text_sec = edit_tail->linked_section;
15821 asection *text_out = text_sec->output_section;
15822 bfd_vma exidx_offset = offset + i->size - 8;
15823
15824 irela->r_addend = 0;
15825 irela->r_offset = exidx_offset;
15826 irela->r_info = ELF32_R_INFO
15827 (text_out->target_index, R_ARM_PREL31);
15828 irela++;
15829 count++;
15830 }
15831 }
15832 else
15833 {
15834 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15835 {
15836 (*swap_in) (abfd, erela, irela);
15837 erela += rel_hdr->sh_entsize;
15838 irela++;
15839 }
15840
15841 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15842 }
15843 }
15844 }
15845
15846 reldata->count = count;
15847 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15848
15849 erela = erela_head;
15850 irela = irela_head;
15851 while (count > 0)
15852 {
15853 (*swap_out) (abfd, irela, erela);
15854 erela += rel_hdr->sh_entsize;
15855 irela++;
15856 count--;
15857 }
15858
15859 free (irela_head);
15860
15861 /* Hashes are no longer valid. */
15862 free (reldata->hashes);
15863 reldata->hashes = NULL;
15864}
15865
6a5bb875 15866/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15867 required if the corresponding code section is marked. Similarly, ARMv8-M
15868 secure entry functions can only be referenced by SG veneers which are
15869 created after the GC process. They need to be marked in case they reside in
15870 their own section (as would be the case if code was compiled with
15871 -ffunction-sections). */
6a5bb875
PB		 15872
15873static bfd_boolean
906e58ca
NC		 15874elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15875 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15876{
15877 bfd *sub;
15878 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15879 asection *cmse_sec;
15880 obj_attribute *out_attr;
15881 Elf_Internal_Shdr *symtab_hdr;
15882 unsigned i, sym_count, ext_start;
15883 const struct elf_backend_data *bed;
15884 struct elf_link_hash_entry **sym_hashes;
15885 struct elf32_arm_link_hash_entry *cmse_hash;
15886 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
bb32413f
SP		 15887 bfd_boolean debug_sec_need_to_be_marked = FALSE;
15888 asection *isec;
6a5bb875 15889
7f6ab9f8
AM		 15890 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15891
4ba2ef8f
TP		 15892 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15893 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15894 && out_attr[Tag_CPU_arch_profile].i == 'M';
15895
6a5bb875
PB		 15896 /* Marking EH data may cause additional code sections to be marked,
15897 requiring multiple passes. */
15898 again = TRUE;
15899 while (again)
15900 {
15901 again = FALSE;
c72f2fb2 15902 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15903 {
15904 asection *o;
15905
0ffa91dd 15906 if (! is_arm_elf (sub))
6a5bb875
PB		 15907 continue;
15908
15909 elf_shdrp = elf_elfsections (sub);
15910 for (o = sub->sections; o != NULL; o = o->next)
15911 {
15912 Elf_Internal_Shdr *hdr;
0ffa91dd 15913
6a5bb875 15914 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15915 if (hdr->sh_type == SHT_ARM_EXIDX
15916 && hdr->sh_link
15917 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15918 && !o->gc_mark
15919 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15920 {
15921 again = TRUE;
15922 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15923 return FALSE;
15924 }
15925 }
4ba2ef8f
TP		 15926
15927 /* Mark section holding ARMv8-M secure entry functions. We mark all
15928 of them so no need for a second browsing. */
15929 if (is_v8m && first_bfd_browse)
15930 {
15931 sym_hashes = elf_sym_hashes (sub);
15932 bed = get_elf_backend_data (sub);
15933 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15934 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15935 ext_start = symtab_hdr->sh_info;
15936
15937 /* Scan symbols. */
15938 for (i = ext_start; i < sym_count; i++)
15939 {
15940 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15941
15942 /* Assume it is a special symbol. If not, cmse_scan will
15943 warn about it and user can do something about it. */
baf46cd7
AM		 15944 if (CONST_STRNEQ (cmse_hash->root.root.root.string,
15945 CMSE_PREFIX))
4ba2ef8f
TP		 15946 {
15947 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15948 if (!cmse_sec->gc_mark
15949 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f 15950 return FALSE;
bb32413f
SP		 15951 /* The debug sections related to these secure entry
15952 functions are marked on enabling below flag. */
15953 debug_sec_need_to_be_marked = TRUE;
4ba2ef8f
TP		 15954 }
15955 }
bb32413f
SP		 15956
15957 if (debug_sec_need_to_be_marked)
15958 {
15959 /* Looping over all the sections of the object file containing
15960 Armv8-M secure entry functions and marking all the debug
15961 sections. */
15962 for (isec = sub->sections; isec != NULL; isec = isec->next)
15963 {
15964 /* If not a debug sections, skip it. */
15965 if (!isec->gc_mark && (isec->flags & SEC_DEBUGGING))
15966 isec->gc_mark = 1 ;
15967 }
15968 debug_sec_need_to_be_marked = FALSE;
15969 }
4ba2ef8f 15970 }
6a5bb875 15971 }
4ba2ef8f 15972 first_bfd_browse = FALSE;
6a5bb875
PB		 15973 }
15974
15975 return TRUE;
15976}
15977
3c9458e9
NC		 15978/* Treat mapping symbols as special target symbols. */
15979
15980static bfd_boolean
15981elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
15982{
b0796911
PB		 15983 return bfd_is_arm_special_symbol_name (sym->name,
15984 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 15985}
15986
e7679060
AM		 15987/* If the ELF symbol SYM might be a function in SEC, return the
15988 function size and set *CODE_OFF to the function's entry point,
15989 otherwise return zero. */
252b5132 15990
e7679060
AM		 15991static bfd_size_type
15992elf32_arm_maybe_function_sym (const asymbol *sym, asection *sec,
15993 bfd_vma *code_off)
15994{
15995 bfd_size_type size;
252b5132 15996
e7679060
AM		 15997 if ((sym->flags & (BSF_SECTION_SYM | BSF_FILE | BSF_OBJECT
15998 | BSF_THREAD_LOCAL | BSF_RELC | BSF_SRELC)) != 0
15999 || sym->section != sec)
16000 return 0;
252b5132 16001
e7679060
AM		 16002 if (!(sym->flags & BSF_SYNTHETIC))
16003 switch (ELF_ST_TYPE (((elf_symbol_type *) sym)->internal_elf_sym.st_info))
16004 {
252b5132
RH		 16005 case STT_FUNC:
16006 case STT_ARM_TFUNC:
9d2da7ca 16007 case STT_NOTYPE:
252b5132 16008 break;
e7679060
AM		 16009 default:
16010 return 0;
16011 }
0367ecfb 16012
e7679060
AM		 16013 if ((sym->flags & BSF_LOCAL)
16014 && bfd_is_arm_special_symbol_name (sym->name,
16015 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
16016 return 0;
0367ecfb 16017
e7679060
AM		 16018 *code_off = sym->value;
16019 size = 0;
16020 if (!(sym->flags & BSF_SYNTHETIC))
16021 size = ((elf_symbol_type *) sym)->internal_elf_sym.st_size;
16022 if (size == 0)
16023 size = 1;
16024 return size;
252b5132
RH		 16025}
16026
4ab527b0 16027static bfd_boolean
07d6d2b8 16028elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 16029 const char ** filename_ptr,
16030 const char ** functionname_ptr,
16031 unsigned int * line_ptr)
16032{
16033 bfd_boolean found;
16034 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
16035 functionname_ptr, line_ptr,
16036 & elf_tdata (abfd)->dwarf2_find_line_info);
16037 return found;
16038}
16039
252b5132
RH		 16040/* Adjust a symbol defined by a dynamic object and referenced by a
16041 regular object. The current definition is in some section of the
16042 dynamic object, but we're not including those sections. We have to
16043 change the definition to something the rest of the link can
16044 understand. */
16045
b34976b6 16046static bfd_boolean
57e8b36a
NC		 16047elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
16048 struct elf_link_hash_entry * h)
252b5132
RH		 16049{
16050 bfd * dynobj;
5474d94f 16051 asection *s, *srel;
b7693d02 16052 struct elf32_arm_link_hash_entry * eh;
67687978 16053 struct elf32_arm_link_hash_table *globals;
252b5132 16054
67687978 16055 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16056 if (globals == NULL)
16057 return FALSE;
16058
252b5132
RH		 16059 dynobj = elf_hash_table (info)->dynobj;
16060
16061 /* Make sure we know what is going on here. */
16062 BFD_ASSERT (dynobj != NULL
f5385ebf 16063 && (h->needs_plt
34e77a92 16064 || h->type == STT_GNU_IFUNC
60d67dc8 16065 || h->is_weakalias
f5385ebf
AM		 16066 || (h->def_dynamic
16067 && h->ref_regular
16068 && !h->def_regular)));
252b5132 16069
b7693d02
DJ		 16070 eh = (struct elf32_arm_link_hash_entry *) h;
16071
252b5132
RH		 16072 /* If this is a function, put it in the procedure linkage table. We
16073 will fill in the contents of the procedure linkage table later,
16074 when we know the address of the .got section. */
34e77a92 16075 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 16076 {
34e77a92
RS		 16077 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16078 symbol binds locally. */
5e681ec4 16079 if (h->plt.refcount <= 0
34e77a92
RS		 16080 || (h->type != STT_GNU_IFUNC
16081 && (SYMBOL_CALLS_LOCAL (info, h)
16082 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16083 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 16084 {
16085 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 16086 file, but the symbol was never referred to by a dynamic
16087 object, or if all references were garbage collected. In
16088 such a case, we don't actually need to build a procedure
16089 linkage table, and we can just do a PC24 reloc instead. */
16090 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16091 eh->plt.thumb_refcount = 0;
16092 eh->plt.maybe_thumb_refcount = 0;
16093 eh->plt.noncall_refcount = 0;
f5385ebf 16094 h->needs_plt = 0;
252b5132
RH		 16095 }
16096
b34976b6 16097 return TRUE;
252b5132 16098 }
5e681ec4 16099 else
b7693d02
DJ		 16100 {
16101 /* It's possible that we incorrectly decided a .plt reloc was
16102 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16103 in check_relocs. We can't decide accurately between function
16104 and non-function syms in check-relocs; Objects loaded later in
16105 the link may change h->type. So fix it now. */
16106 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16107 eh->plt.thumb_refcount = 0;
16108 eh->plt.maybe_thumb_refcount = 0;
16109 eh->plt.noncall_refcount = 0;
b7693d02 16110 }
252b5132
RH		 16111
16112 /* If this is a weak symbol, and there is a real definition, the
16113 processor independent code will have arranged for us to see the
16114 real definition first, and we can just use the same value. */
60d67dc8 16115 if (h->is_weakalias)
252b5132 16116 {
60d67dc8
AM		 16117 struct elf_link_hash_entry *def = weakdef (h);
16118 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
16119 h->root.u.def.section = def->root.u.def.section;
16120 h->root.u.def.value = def->root.u.def.value;
b34976b6 16121 return TRUE;
252b5132
RH		 16122 }
16123
ba93b8ac
DJ		 16124 /* If there are no non-GOT references, we do not need a copy
16125 relocation. */
16126 if (!h->non_got_ref)
16127 return TRUE;
16128
252b5132
RH		 16129 /* This is a reference to a symbol defined by a dynamic object which
16130 is not a function. */
16131
16132 /* If we are creating a shared library, we must presume that the
16133 only references to the symbol are via the global offset table.
16134 For such cases we need not do anything here; the relocations will
67687978
PB		 16135 be handled correctly by relocate_section. Relocatable executables
16136 can reference data in shared objects directly, so we don't need to
16137 do anything here. */
0e1862bb 16138 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 16139 return TRUE;
252b5132
RH		 16140
16141 /* We must allocate the symbol in our .dynbss section, which will
16142 become part of the .bss section of the executable. There will be
16143 an entry for this symbol in the .dynsym section. The dynamic
16144 object will contain position independent code, so all references
16145 from the dynamic object to this symbol will go through the global
16146 offset table. The dynamic linker will use the .dynsym entry to
16147 determine the address it must put in the global offset table, so
16148 both the dynamic object and the regular object will refer to the
16149 same memory location for the variable. */
5522f910
NC		 16150 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16151 linker to copy the initial value out of the dynamic object and into
16152 the runtime process image. We need to remember the offset into the
00a97672 16153 .rel(a).bss section we are going to use. */
5474d94f
AM		 16154 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
16155 {
16156 s = globals->root.sdynrelro;
16157 srel = globals->root.sreldynrelro;
16158 }
16159 else
16160 {
16161 s = globals->root.sdynbss;
16162 srel = globals->root.srelbss;
16163 }
5522f910
NC		 16164 if (info->nocopyreloc == 0
16165 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 16166 && h->size != 0)
252b5132 16167 {
47beaa6a 16168 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 16169 h->needs_copy = 1;
252b5132
RH		 16170 }
16171
6cabe1ea 16172 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 16173}
16174
5e681ec4
PB		 16175/* Allocate space in .plt, .got and associated reloc sections for
16176 dynamic relocs. */
16177
16178static bfd_boolean
47beaa6a 16179allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 16180{
16181 struct bfd_link_info *info;
16182 struct elf32_arm_link_hash_table *htab;
16183 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 16184 struct elf_dyn_relocs *p;
5e681ec4
PB		 16185
16186 if (h->root.type == bfd_link_hash_indirect)
16187 return TRUE;
16188
e6a6bb22
AM		 16189 eh = (struct elf32_arm_link_hash_entry *) h;
16190
5e681ec4
PB		 16191 info = (struct bfd_link_info *) inf;
16192 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16193 if (htab == NULL)
16194 return FALSE;
5e681ec4 16195
34e77a92 16196 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 16197 && h->plt.refcount > 0)
16198 {
16199 /* Make sure this symbol is output as a dynamic symbol.
16200 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16201 if (h->dynindx == -1 && !h->forced_local
16202 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16203 {
c152c796 16204 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16205 return FALSE;
16206 }
16207
34e77a92
RS		 16208 /* If the call in the PLT entry binds locally, the associated
16209 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16210 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16211 than the .plt section. */
16212 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16213 {
16214 eh->is_iplt = 1;
16215 if (eh->plt.noncall_refcount == 0
16216 && SYMBOL_REFERENCES_LOCAL (info, h))
16217 /* All non-call references can be resolved directly.
16218 This means that they can (and in some cases, must)
16219 resolve directly to the run-time target, rather than
16220 to the PLT. That in turns means that any .got entry
16221 would be equal to the .igot.plt entry, so there's
16222 no point having both. */
16223 h->got.refcount = 0;
16224 }
16225
0e1862bb 16226 if (bfd_link_pic (info)
34e77a92 16227 || eh->is_iplt
7359ea65 16228 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 16229 {
34e77a92 16230 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 16231
5e681ec4
PB		 16232 /* If this symbol is not defined in a regular file, and we are
16233 not generating a shared library, then set the symbol to this
16234 location in the .plt. This is required to make function
16235 pointers compare as equal between the normal executable and
16236 the shared library. */
0e1862bb 16237 if (! bfd_link_pic (info)
f5385ebf 16238 && !h->def_regular)
5e681ec4 16239 {
34e77a92 16240 h->root.u.def.section = htab->root.splt;
5e681ec4 16241 h->root.u.def.value = h->plt.offset;
5e681ec4 16242
67d74e43
DJ		 16243 /* Make sure the function is not marked as Thumb, in case
16244 it is the target of an ABS32 relocation, which will
16245 point to the PLT entry. */
39d911fc 16246 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 16247 }
022f8312 16248
00a97672
RS		 16249 /* VxWorks executables have a second set of relocations for
16250 each PLT entry. They go in a separate relocation section,
16251 which is processed by the kernel loader. */
90c14f0c 16252 if (htab->root.target_os == is_vxworks && !bfd_link_pic (info))
00a97672
RS		 16253 {
16254 /* There is a relocation for the initial PLT entry:
16255 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16256 if (h->plt.offset == htab->plt_header_size)
47beaa6a 16257 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 16258
16259 /* There are two extra relocations for each subsequent
16260 PLT entry: an R_ARM_32 relocation for the GOT entry,
16261 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 16262 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 16263 }
5e681ec4
PB		 16264 }
16265 else
16266 {
16267 h->plt.offset = (bfd_vma) -1;
f5385ebf 16268 h->needs_plt = 0;
5e681ec4
PB		 16269 }
16270 }
16271 else
16272 {
16273 h->plt.offset = (bfd_vma) -1;
f5385ebf 16274 h->needs_plt = 0;
5e681ec4
PB		 16275 }
16276
0855e32b
NS		 16277 eh = (struct elf32_arm_link_hash_entry *) h;
16278 eh->tlsdesc_got = (bfd_vma) -1;
16279
5e681ec4
PB		 16280 if (h->got.refcount > 0)
16281 {
16282 asection *s;
16283 bfd_boolean dyn;
ba93b8ac
DJ		 16284 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16285 int indx;
5e681ec4
PB		 16286
16287 /* Make sure this symbol is output as a dynamic symbol.
16288 Undefined weak syms won't yet be marked as dynamic. */
e8b09b87 16289 if (htab->root.dynamic_sections_created && h->dynindx == -1 && !h->forced_local
6c699715 16290 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16291 {
c152c796 16292 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16293 return FALSE;
16294 }
16295
90c14f0c 16296 if (htab->root.target_os != is_symbian)
e5a52504 16297 {
362d30a1 16298 s = htab->root.sgot;
e5a52504 16299 h->got.offset = s->size;
ba93b8ac
DJ		 16300
16301 if (tls_type == GOT_UNKNOWN)
16302 abort ();
16303
16304 if (tls_type == GOT_NORMAL)
16305 /* Non-TLS symbols need one GOT slot. */
16306 s->size += 4;
16307 else
16308 {
99059e56
RM		 16309 if (tls_type & GOT_TLS_GDESC)
16310 {
0855e32b 16311 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 16312 eh->tlsdesc_got
0855e32b
NS		 16313 = (htab->root.sgotplt->size
16314 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 16315 htab->root.sgotplt->size += 8;
16316 h->got.offset = (bfd_vma) -2;
34e77a92 16317 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16318 reloc in the middle of .got.plt. */
99059e56
RM		 16319 htab->num_tls_desc++;
16320 }
0855e32b 16321
ba93b8ac 16322 if (tls_type & GOT_TLS_GD)
0855e32b 16323 {
5c5a4843
CL		 16324 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16325 consecutive GOT slots. If the symbol is both GD
16326 and GDESC, got.offset may have been
16327 overwritten. */
0855e32b
NS		 16328 h->got.offset = s->size;
16329 s->size += 8;
16330 }
16331
ba93b8ac 16332 if (tls_type & GOT_TLS_IE)
5c5a4843
CL		 16333 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16334 slot. */
ba93b8ac
DJ		 16335 s->size += 4;
16336 }
16337
e5a52504 16338 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 16339
16340 indx = 0;
0e1862bb
L		 16341 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
16342 bfd_link_pic (info),
16343 h)
16344 && (!bfd_link_pic (info)
ba93b8ac
DJ		 16345 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16346 indx = h->dynindx;
16347
16348 if (tls_type != GOT_NORMAL
9cb09e33 16349 && (bfd_link_dll (info) || indx != 0)
ba93b8ac
DJ		 16350 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16351 || h->root.type != bfd_link_hash_undefweak))
16352 {
16353 if (tls_type & GOT_TLS_IE)
47beaa6a 16354 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16355
16356 if (tls_type & GOT_TLS_GD)
47beaa6a 16357 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16358
b38cadfb 16359 if (tls_type & GOT_TLS_GDESC)
0855e32b 16360 {
47beaa6a 16361 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 16362 /* GDESC needs a trampoline to jump to. */
16363 htab->tls_trampoline = -1;
16364 }
16365
16366 /* Only GD needs it. GDESC just emits one relocation per
16367 2 entries. */
b38cadfb 16368 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 16369 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16370 }
e8b09b87
CL		 16371 else if (((indx != -1) || htab->fdpic_p)
16372 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 16373 {
16374 if (htab->root.dynamic_sections_created)
16375 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16376 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16377 }
34e77a92
RS		 16378 else if (h->type == STT_GNU_IFUNC
16379 && eh->plt.noncall_refcount == 0)
16380 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16381 they all resolve dynamically instead. Reserve room for the
16382 GOT entry's R_ARM_IRELATIVE relocation. */
16383 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb 16384 else if (bfd_link_pic (info)
7f026732 16385 && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
b436d854 16386 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 16387 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16388 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16389 /* Reserve room for rofixup for FDPIC executable. */
16390 /* TLS relocs do not need space since they are completely
16391 resolved. */
16392 htab->srofixup->size += 4;
e5a52504 16393 }
5e681ec4
PB		 16394 }
16395 else
16396 h->got.offset = (bfd_vma) -1;
16397
e8b09b87
CL		 16398 /* FDPIC support. */
16399 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16400 {
16401 /* Symbol musn't be exported. */
16402 if (h->dynindx != -1)
16403 abort();
16404
16405 /* We only allocate one function descriptor with its associated relocation. */
16406 if (eh->fdpic_cnts.funcdesc_offset == -1)
16407 {
16408 asection *s = htab->root.sgot;
16409
16410 eh->fdpic_cnts.funcdesc_offset = s->size;
16411 s->size += 8;
16412 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16413 if (bfd_link_pic(info))
16414 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16415 else
16416 htab->srofixup->size += 8;
16417 }
16418 }
16419
16420 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16421 {
16422 asection *s = htab->root.sgot;
16423
16424 if (htab->root.dynamic_sections_created && h->dynindx == -1
16425 && !h->forced_local)
16426 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16427 return FALSE;
16428
16429 if (h->dynindx == -1)
16430 {
16431 /* We only allocate one function descriptor with its associated relocation. q */
16432 if (eh->fdpic_cnts.funcdesc_offset == -1)
16433 {
16434
16435 eh->fdpic_cnts.funcdesc_offset = s->size;
16436 s->size += 8;
16437 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16438 if (bfd_link_pic(info))
16439 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16440 else
16441 htab->srofixup->size += 8;
16442 }
16443 }
16444
16445 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16446 R_ARM_RELATIVE/rofixup relocation on it. */
16447 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16448 s->size += 4;
16449 if (h->dynindx == -1 && !bfd_link_pic(info))
4b24dd1a 16450 htab->srofixup->size += 4;
e8b09b87 16451 else
4b24dd1a 16452 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16453 }
16454
16455 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16456 {
16457 if (htab->root.dynamic_sections_created && h->dynindx == -1
16458 && !h->forced_local)
16459 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16460 return FALSE;
16461
16462 if (h->dynindx == -1)
16463 {
16464 /* We only allocate one function descriptor with its associated relocation. */
16465 if (eh->fdpic_cnts.funcdesc_offset == -1)
16466 {
16467 asection *s = htab->root.sgot;
16468
16469 eh->fdpic_cnts.funcdesc_offset = s->size;
16470 s->size += 8;
16471 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16472 if (bfd_link_pic(info))
16473 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16474 else
16475 htab->srofixup->size += 8;
16476 }
16477 }
16478 if (h->dynindx == -1 && !bfd_link_pic(info))
16479 {
16480 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16481 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16482 }
16483 else
16484 {
16485 /* Will need one dynamic reloc per reference. will be either
16486 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16487 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16488 eh->fdpic_cnts.funcdesc_cnt);
16489 }
16490 }
16491
a4fd1a8e
PB		 16492 /* Allocate stubs for exported Thumb functions on v4t. */
16493 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 16494 && h->def_regular
39d911fc 16495 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 16496 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16497 {
16498 struct elf_link_hash_entry * th;
16499 struct bfd_link_hash_entry * bh;
16500 struct elf_link_hash_entry * myh;
16501 char name[1024];
16502 asection *s;
16503 bh = NULL;
16504 /* Create a new symbol to regist the real location of the function. */
16505 s = h->root.u.def.section;
906e58ca 16506 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 16507 _bfd_generic_link_add_one_symbol (info, s->owner,
16508 name, BSF_GLOBAL, s,
16509 h->root.u.def.value,
16510 NULL, TRUE, FALSE, &bh);
16511
16512 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 16513 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 16514 myh->forced_local = 1;
39d911fc 16515 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 16516 eh->export_glue = myh;
16517 th = record_arm_to_thumb_glue (info, h);
16518 /* Point the symbol at the stub. */
16519 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 16520 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 16521 h->root.u.def.section = th->root.u.def.section;
16522 h->root.u.def.value = th->root.u.def.value & ~1;
16523 }
16524
190eb1dd 16525 if (h->dyn_relocs == NULL)
5e681ec4
PB		 16526 return TRUE;
16527
16528 /* In the shared -Bsymbolic case, discard space allocated for
16529 dynamic pc-relative relocs against symbols which turn out to be
16530 defined in regular objects. For the normal shared case, discard
16531 space for pc-relative relocs that have become local due to symbol
16532 visibility changes. */
16533
e8b09b87 16534 if (bfd_link_pic (info) || htab->root.is_relocatable_executable || htab->fdpic_p)
5e681ec4 16535 {
469a3493
RM		 16536 /* Relocs that use pc_count are PC-relative forms, which will appear
16537 on something like ".long foo - ." or "movw REG, foo - .". We want
16538 calls to protected symbols to resolve directly to the function
16539 rather than going via the plt. If people want function pointer
16540 comparisons to work as expected then they should avoid writing
16541 assembly like ".long foo - .". */
ba93b8ac
DJ		 16542 if (SYMBOL_CALLS_LOCAL (info, h))
16543 {
0bdcacaf 16544 struct elf_dyn_relocs **pp;
ba93b8ac 16545
190eb1dd 16546 for (pp = &h->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 16547 {
16548 p->count -= p->pc_count;
16549 p->pc_count = 0;
16550 if (p->count == 0)
16551 *pp = p->next;
16552 else
16553 pp = &p->next;
16554 }
16555 }
16556
90c14f0c 16557 if (htab->root.target_os == is_vxworks)
3348747a 16558 {
0bdcacaf 16559 struct elf_dyn_relocs **pp;
3348747a 16560
190eb1dd 16561 for (pp = &h->dyn_relocs; (p = *pp) != NULL; )
3348747a 16562 {
0bdcacaf 16563 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 16564 *pp = p->next;
16565 else
16566 pp = &p->next;
16567 }
16568 }
16569
ba93b8ac 16570 /* Also discard relocs on undefined weak syms with non-default
99059e56 16571 visibility. */
190eb1dd 16572 if (h->dyn_relocs != NULL
5e681ec4 16573 && h->root.type == bfd_link_hash_undefweak)
22d606e9 16574 {
95b03e4a
L		 16575 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16576 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
190eb1dd 16577 h->dyn_relocs = NULL;
22d606e9
AM		 16578
16579 /* Make sure undefined weak symbols are output as a dynamic
16580 symbol in PIEs. */
e8b09b87 16581 else if (htab->root.dynamic_sections_created && h->dynindx == -1
22d606e9
AM		 16582 && !h->forced_local)
16583 {
16584 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16585 return FALSE;
16586 }
16587 }
16588
67687978
PB		 16589 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16590 && h->root.type == bfd_link_hash_new)
16591 {
16592 /* Output absolute symbols so that we can create relocations
16593 against them. For normal symbols we output a relocation
16594 against the section that contains them. */
16595 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16596 return FALSE;
16597 }
16598
5e681ec4
PB		 16599 }
16600 else
16601 {
16602 /* For the non-shared case, discard space for relocs against
16603 symbols which turn out to need copy relocs or are not
16604 dynamic. */
16605
f5385ebf
AM		 16606 if (!h->non_got_ref
16607 && ((h->def_dynamic
16608 && !h->def_regular)
5e681ec4
PB		 16609 || (htab->root.dynamic_sections_created
16610 && (h->root.type == bfd_link_hash_undefweak
16611 || h->root.type == bfd_link_hash_undefined))))
16612 {
16613 /* Make sure this symbol is output as a dynamic symbol.
16614 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16615 if (h->dynindx == -1 && !h->forced_local
16616 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16617 {
c152c796 16618 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16619 return FALSE;
16620 }
16621
16622 /* If that succeeded, we know we'll be keeping all the
16623 relocs. */
16624 if (h->dynindx != -1)
16625 goto keep;
16626 }
16627
190eb1dd 16628 h->dyn_relocs = NULL;
5e681ec4
PB		 16629
16630 keep: ;
16631 }
16632
16633 /* Finally, allocate space. */
190eb1dd 16634 for (p = h->dyn_relocs; p != NULL; p = p->next)
5e681ec4 16635 {
0bdcacaf 16636 asection *sreloc = elf_section_data (p->sec)->sreloc;
e8b09b87 16637
34e77a92
RS		 16638 if (h->type == STT_GNU_IFUNC
16639 && eh->plt.noncall_refcount == 0
16640 && SYMBOL_REFERENCES_LOCAL (info, h))
16641 elf32_arm_allocate_irelocs (info, sreloc, p->count);
e8b09b87
CL		 16642 else if (h->dynindx != -1 && (!bfd_link_pic(info) || !info->symbolic || !h->def_regular))
16643 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16644 else if (htab->fdpic_p && !bfd_link_pic(info))
16645 htab->srofixup->size += 4 * p->count;
34e77a92
RS		 16646 else
16647 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 16648 }
16649
16650 return TRUE;
16651}
16652
d504ffc8
DJ		 16653void
16654bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16655 int byteswap_code)
16656{
16657 struct elf32_arm_link_hash_table *globals;
16658
16659 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16660 if (globals == NULL)
16661 return;
16662
d504ffc8
DJ		 16663 globals->byteswap_code = byteswap_code;
16664}
16665
252b5132
RH		 16666/* Set the sizes of the dynamic sections. */
16667
b34976b6 16668static bfd_boolean
57e8b36a
NC		 16669elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16670 struct bfd_link_info * info)
252b5132
RH		 16671{
16672 bfd * dynobj;
16673 asection * s;
b34976b6 16674 bfd_boolean relocs;
5e681ec4
PB		 16675 bfd *ibfd;
16676 struct elf32_arm_link_hash_table *htab;
252b5132 16677
5e681ec4 16678 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16679 if (htab == NULL)
16680 return FALSE;
16681
252b5132
RH		 16682 dynobj = elf_hash_table (info)->dynobj;
16683 BFD_ASSERT (dynobj != NULL);
39b41c9c 16684 check_use_blx (htab);
252b5132
RH		 16685
16686 if (elf_hash_table (info)->dynamic_sections_created)
16687 {
16688 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 16689 if (bfd_link_executable (info) && !info->nointerp)
252b5132 16690 {
3d4d4302 16691 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 16692 BFD_ASSERT (s != NULL);
eea6121a 16693 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 16694 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16695 }
16696 }
5e681ec4
PB		 16697
16698 /* Set up .got offsets for local syms, and space for local dynamic
16699 relocs. */
c72f2fb2 16700 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 16701 {
5e681ec4
PB		 16702 bfd_signed_vma *local_got;
16703 bfd_signed_vma *end_local_got;
34e77a92 16704 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 16705 char *local_tls_type;
0855e32b 16706 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 16707 bfd_size_type locsymcount;
16708 Elf_Internal_Shdr *symtab_hdr;
16709 asection *srel;
34e77a92 16710 unsigned int symndx;
e8b09b87 16711 struct fdpic_local *local_fdpic_cnts;
5e681ec4 16712
0ffa91dd 16713 if (! is_arm_elf (ibfd))
5e681ec4
PB		 16714 continue;
16715
16716 for (s = ibfd->sections; s != NULL; s = s->next)
16717 {
0bdcacaf 16718 struct elf_dyn_relocs *p;
5e681ec4 16719
0bdcacaf 16720 for (p = (struct elf_dyn_relocs *)
99059e56 16721 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 16722 {
0bdcacaf
RS		 16723 if (!bfd_is_abs_section (p->sec)
16724 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 16725 {
16726 /* Input section has been discarded, either because
16727 it is a copy of a linkonce section or due to
16728 linker script /DISCARD/, so we'll be discarding
16729 the relocs too. */
16730 }
90c14f0c 16731 else if (htab->root.target_os == is_vxworks
0bdcacaf 16732 && strcmp (p->sec->output_section->name,
3348747a
NS		 16733 ".tls_vars") == 0)
16734 {
16735 /* Relocations in vxworks .tls_vars sections are
16736 handled specially by the loader. */
16737 }
5e681ec4
PB		 16738 else if (p->count != 0)
16739 {
0bdcacaf 16740 srel = elf_section_data (p->sec)->sreloc;
e8b09b87
CL		 16741 if (htab->fdpic_p && !bfd_link_pic(info))
16742 htab->srofixup->size += 4 * p->count;
16743 else
16744 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 16745 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 16746 info->flags |= DF_TEXTREL;
16747 }
16748 }
16749 }
16750
16751 local_got = elf_local_got_refcounts (ibfd);
16752 if (!local_got)
16753 continue;
16754
0ffa91dd 16755 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 16756 locsymcount = symtab_hdr->sh_info;
16757 end_local_got = local_got + locsymcount;
34e77a92 16758 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 16759 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 16760 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
e8b09b87 16761 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
34e77a92 16762 symndx = 0;
362d30a1
RS		 16763 s = htab->root.sgot;
16764 srel = htab->root.srelgot;
0855e32b 16765 for (; local_got < end_local_got;
34e77a92 16766 ++local_got, ++local_iplt_ptr, ++local_tls_type,
e8b09b87 16767 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
5e681ec4 16768 {
0855e32b 16769 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92 16770 local_iplt = *local_iplt_ptr;
e8b09b87
CL		 16771
16772 /* FDPIC support. */
16773 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16774 {
16775 if (local_fdpic_cnts->funcdesc_offset == -1)
16776 {
16777 local_fdpic_cnts->funcdesc_offset = s->size;
16778 s->size += 8;
16779
16780 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16781 if (bfd_link_pic(info))
16782 elf32_arm_allocate_dynrelocs (info, srel, 1);
16783 else
16784 htab->srofixup->size += 8;
16785 }
16786 }
16787
16788 if (local_fdpic_cnts->funcdesc_cnt > 0)
16789 {
16790 if (local_fdpic_cnts->funcdesc_offset == -1)
16791 {
16792 local_fdpic_cnts->funcdesc_offset = s->size;
16793 s->size += 8;
16794
16795 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16796 if (bfd_link_pic(info))
16797 elf32_arm_allocate_dynrelocs (info, srel, 1);
16798 else
16799 htab->srofixup->size += 8;
16800 }
16801
16802 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16803 if (bfd_link_pic(info))
16804 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16805 else
16806 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16807 }
16808
34e77a92
RS		 16809 if (local_iplt != NULL)
16810 {
16811 struct elf_dyn_relocs *p;
16812
16813 if (local_iplt->root.refcount > 0)
16814 {
16815 elf32_arm_allocate_plt_entry (info, TRUE,
16816 &local_iplt->root,
16817 &local_iplt->arm);
16818 if (local_iplt->arm.noncall_refcount == 0)
16819 /* All references to the PLT are calls, so all
16820 non-call references can resolve directly to the
16821 run-time target. This means that the .got entry
16822 would be the same as the .igot.plt entry, so there's
16823 no point creating both. */
16824 *local_got = 0;
16825 }
16826 else
16827 {
16828 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
16829 local_iplt->root.offset = (bfd_vma) -1;
16830 }
16831
16832 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
16833 {
16834 asection *psrel;
16835
16836 psrel = elf_section_data (p->sec)->sreloc;
16837 if (local_iplt->arm.noncall_refcount == 0)
16838 elf32_arm_allocate_irelocs (info, psrel, p->count);
16839 else
16840 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
16841 }
16842 }
5e681ec4
PB		 16843 if (*local_got > 0)
16844 {
34e77a92
RS		 16845 Elf_Internal_Sym *isym;
16846
eea6121a 16847 *local_got = s->size;
ba93b8ac
DJ		 16848 if (*local_tls_type & GOT_TLS_GD)
16849 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16850 s->size += 8;
0855e32b
NS		 16851 if (*local_tls_type & GOT_TLS_GDESC)
16852 {
16853 *local_tlsdesc_gotent = htab->root.sgotplt->size
16854 - elf32_arm_compute_jump_table_size (htab);
16855 htab->root.sgotplt->size += 8;
16856 *local_got = (bfd_vma) -2;
34e77a92 16857 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16858 reloc in the middle of .got.plt. */
99059e56 16859 htab->num_tls_desc++;
0855e32b 16860 }
ba93b8ac
DJ		 16861 if (*local_tls_type & GOT_TLS_IE)
16862 s->size += 4;
ba93b8ac 16863
0855e32b
NS		 16864 if (*local_tls_type & GOT_NORMAL)
16865 {
16866 /* If the symbol is both GD and GDESC, *local_got
16867 may have been overwritten. */
16868 *local_got = s->size;
16869 s->size += 4;
16870 }
16871
f1dfbfdb
L		 16872 isym = bfd_sym_from_r_symndx (&htab->root.sym_cache, ibfd,
16873 symndx);
34e77a92
RS		 16874 if (isym == NULL)
16875 return FALSE;
16876
16877 /* If all references to an STT_GNU_IFUNC PLT are calls,
16878 then all non-call references, including this GOT entry,
16879 resolve directly to the run-time target. */
16880 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
16881 && (local_iplt == NULL
16882 || local_iplt->arm.noncall_refcount == 0))
16883 elf32_arm_allocate_irelocs (info, srel, 1);
e8b09b87 16884 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
0855e32b 16885 {
e8b09b87 16886 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
3064e1ff 16887 elf32_arm_allocate_dynrelocs (info, srel, 1);
e8b09b87
CL		 16888 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
16889 htab->srofixup->size += 4;
99059e56 16890
e8b09b87
CL		 16891 if ((bfd_link_pic (info) || htab->fdpic_p)
16892 && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 16893 {
16894 elf32_arm_allocate_dynrelocs (info,
16895 htab->root.srelplt, 1);
16896 htab->tls_trampoline = -1;
16897 }
0855e32b 16898 }
5e681ec4
PB		 16899 }
16900 else
16901 *local_got = (bfd_vma) -1;
16902 }
252b5132
RH		 16903 }
16904
ba93b8ac
DJ		 16905 if (htab->tls_ldm_got.refcount > 0)
16906 {
16907 /* Allocate two GOT entries and one dynamic relocation (if necessary)
5c5a4843 16908 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
362d30a1
RS		 16909 htab->tls_ldm_got.offset = htab->root.sgot->size;
16910 htab->root.sgot->size += 8;
0e1862bb 16911 if (bfd_link_pic (info))
47beaa6a 16912 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16913 }
16914 else
16915 htab->tls_ldm_got.offset = -1;
16916
e8b09b87
CL		 16917 /* At the very end of the .rofixup section is a pointer to the GOT,
16918 reserve space for it. */
16919 if (htab->fdpic_p && htab->srofixup != NULL)
16920 htab->srofixup->size += 4;
16921
5e681ec4
PB		 16922 /* Allocate global sym .plt and .got entries, and space for global
16923 sym dynamic relocs. */
47beaa6a 16924 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 16925
d504ffc8 16926 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 16927 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 16928 {
0ffa91dd 16929 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 16930 continue;
16931
c7b8f16e
JB		 16932 /* Initialise mapping tables for code/data. */
16933 bfd_elf32_arm_init_maps (ibfd);
906e58ca 16934
c7b8f16e 16935 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 16936 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
16937 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 16938 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 16939 }
d504ffc8 16940
3e6b1042
DJ		 16941 /* Allocate space for the glue sections now that we've sized them. */
16942 bfd_elf32_arm_allocate_interworking_sections (info);
16943
0855e32b
NS		 16944 /* For every jump slot reserved in the sgotplt, reloc_count is
16945 incremented. However, when we reserve space for TLS descriptors,
16946 it's not incremented, so in order to compute the space reserved
16947 for them, it suffices to multiply the reloc count by the jump
16948 slot size. */
16949 if (htab->root.srelplt)
16950 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
16951
16952 if (htab->tls_trampoline)
16953 {
16954 if (htab->root.splt->size == 0)
16955 htab->root.splt->size += htab->plt_header_size;
b38cadfb 16956
0855e32b
NS		 16957 htab->tls_trampoline = htab->root.splt->size;
16958 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 16959
0855e32b 16960 /* If we're not using lazy TLS relocations, don't generate the
99059e56 16961 PLT and GOT entries they require. */
9bcc30e4
L		 16962 if ((info->flags & DF_BIND_NOW))
16963 htab->root.tlsdesc_plt = 0;
16964 else
0855e32b 16965 {
9bcc30e4 16966 htab->root.tlsdesc_got = htab->root.sgot->size;
0855e32b
NS		 16967 htab->root.sgot->size += 4;
16968
9bcc30e4 16969 htab->root.tlsdesc_plt = htab->root.splt->size;
0855e32b
NS		 16970 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
16971 }
16972 }
16973
252b5132
RH		 16974 /* The check_relocs and adjust_dynamic_symbol entry points have
16975 determined the sizes of the various dynamic sections. Allocate
16976 memory for them. */
b34976b6 16977 relocs = FALSE;
252b5132
RH		 16978 for (s = dynobj->sections; s != NULL; s = s->next)
16979 {
16980 const char * name;
252b5132
RH		 16981
16982 if ((s->flags & SEC_LINKER_CREATED) == 0)
16983 continue;
16984
16985 /* It's OK to base decisions on the section name, because none
16986 of the dynobj section names depend upon the input files. */
fd361982 16987 name = bfd_section_name (s);
252b5132 16988
34e77a92 16989 if (s == htab->root.splt)
252b5132 16990 {
c456f082 16991 /* Remember whether there is a PLT. */
3084d7a2 16992 ;
252b5132 16993 }
0112cd26 16994 else if (CONST_STRNEQ (name, ".rel"))
252b5132 16995 {
c456f082 16996 if (s->size != 0)
252b5132 16997 {
252b5132 16998 /* Remember whether there are any reloc sections other
00a97672 16999 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 17000 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 17001 relocs = TRUE;
252b5132
RH		 17002
17003 /* We use the reloc_count field as a counter if we need
17004 to copy relocs into the output file. */
17005 s->reloc_count = 0;
17006 }
17007 }
34e77a92
RS		 17008 else if (s != htab->root.sgot
17009 && s != htab->root.sgotplt
17010 && s != htab->root.iplt
17011 && s != htab->root.igotplt
5474d94f 17012 && s != htab->root.sdynbss
e8b09b87
CL		 17013 && s != htab->root.sdynrelro
17014 && s != htab->srofixup)
252b5132
RH		 17015 {
17016 /* It's not one of our sections, so don't allocate space. */
17017 continue;
17018 }
17019
c456f082 17020 if (s->size == 0)
252b5132 17021 {
c456f082 17022 /* If we don't need this section, strip it from the
00a97672
RS		 17023 output file. This is mostly to handle .rel(a).bss and
17024 .rel(a).plt. We must create both sections in
c456f082
AM		 17025 create_dynamic_sections, because they must be created
17026 before the linker maps input sections to output
17027 sections. The linker does that before
17028 adjust_dynamic_symbol is called, and it is that
17029 function which decides whether anything needs to go
17030 into these sections. */
8423293d 17031 s->flags |= SEC_EXCLUDE;
252b5132
RH		 17032 continue;
17033 }
17034
c456f082
AM		 17035 if ((s->flags & SEC_HAS_CONTENTS) == 0)
17036 continue;
17037
252b5132 17038 /* Allocate memory for the section contents. */
21d799b5 17039 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 17040 if (s->contents == NULL)
b34976b6 17041 return FALSE;
252b5132
RH		 17042 }
17043
3084d7a2
L		 17044 return _bfd_elf_maybe_vxworks_add_dynamic_tags (output_bfd, info,
17045 relocs);
252b5132
RH		 17046}
17047
0855e32b
NS		 17048/* Size sections even though they're not dynamic. We use it to setup
17049 _TLS_MODULE_BASE_, if needed. */
17050
17051static bfd_boolean
17052elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 17053 struct bfd_link_info *info)
0855e32b
NS		 17054{
17055 asection *tls_sec;
cb10292c
CL		 17056 struct elf32_arm_link_hash_table *htab;
17057
17058 htab = elf32_arm_hash_table (info);
0855e32b 17059
0e1862bb 17060 if (bfd_link_relocatable (info))
0855e32b
NS		 17061 return TRUE;
17062
17063 tls_sec = elf_hash_table (info)->tls_sec;
17064
17065 if (tls_sec)
17066 {
17067 struct elf_link_hash_entry *tlsbase;
17068
17069 tlsbase = elf_link_hash_lookup
17070 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
17071
17072 if (tlsbase)
99059e56
RM		 17073 {
17074 struct bfd_link_hash_entry *bh = NULL;
0855e32b 17075 const struct elf_backend_data *bed
99059e56 17076 = get_elf_backend_data (output_bfd);
0855e32b 17077
99059e56 17078 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 17079 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
17080 tls_sec, 0, NULL, FALSE,
17081 bed->collect, &bh)))
17082 return FALSE;
b38cadfb 17083
99059e56
RM		 17084 tlsbase->type = STT_TLS;
17085 tlsbase = (struct elf_link_hash_entry *)bh;
17086 tlsbase->def_regular = 1;
17087 tlsbase->other = STV_HIDDEN;
17088 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 17089 }
17090 }
cb10292c
CL		 17091
17092 if (htab->fdpic_p && !bfd_link_relocatable (info)
17093 && !bfd_elf_stack_segment_size (output_bfd, info,
17094 "__stacksize", DEFAULT_STACK_SIZE))
17095 return FALSE;
17096
0855e32b
NS		 17097 return TRUE;
17098}
17099
252b5132
RH		 17100/* Finish up dynamic symbol handling. We set the contents of various
17101 dynamic sections here. */
17102
b34976b6 17103static bfd_boolean
906e58ca
NC		 17104elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17105 struct bfd_link_info * info,
17106 struct elf_link_hash_entry * h,
17107 Elf_Internal_Sym * sym)
252b5132 17108{
e5a52504 17109 struct elf32_arm_link_hash_table *htab;
b7693d02 17110 struct elf32_arm_link_hash_entry *eh;
252b5132 17111
e5a52504 17112 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17113 if (htab == NULL)
17114 return FALSE;
17115
b7693d02 17116 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 17117
17118 if (h->plt.offset != (bfd_vma) -1)
17119 {
34e77a92 17120 if (!eh->is_iplt)
e5a52504 17121 {
34e77a92 17122 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 17123 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17124 h->dynindx, 0))
17125 return FALSE;
e5a52504 17126 }
57e8b36a 17127
f5385ebf 17128 if (!h->def_regular)
252b5132
RH		 17129 {
17130 /* Mark the symbol as undefined, rather than as defined in
3a635617 17131 the .plt section. */
252b5132 17132 sym->st_shndx = SHN_UNDEF;
3a635617 17133 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 17134 Otherwise, the PLT entry would provide a definition for
17135 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 17136 and so the symbol would never be NULL. Leave the value if
17137 there were any relocations where pointer equality matters
17138 (this is a clue for the dynamic linker, to make function
17139 pointer comparisons work between an application and shared
17140 library). */
97323ad1 17141 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 17142 sym->st_value = 0;
252b5132 17143 }
34e77a92
RS		 17144 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17145 {
17146 /* At least one non-call relocation references this .iplt entry,
17147 so the .iplt entry is the function's canonical address. */
17148 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 17149 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 17150 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17151 (output_bfd, htab->root.iplt->output_section));
17152 sym->st_value = (h->plt.offset
17153 + htab->root.iplt->output_section->vma
17154 + htab->root.iplt->output_offset);
17155 }
252b5132
RH		 17156 }
17157
f5385ebf 17158 if (h->needs_copy)
252b5132
RH		 17159 {
17160 asection * s;
947216bf 17161 Elf_Internal_Rela rel;
252b5132
RH		 17162
17163 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 17164 BFD_ASSERT (h->dynindx != -1
17165 && (h->root.type == bfd_link_hash_defined
17166 || h->root.type == bfd_link_hash_defweak));
17167
00a97672 17168 rel.r_addend = 0;
252b5132
RH		 17169 rel.r_offset = (h->root.u.def.value
17170 + h->root.u.def.section->output_section->vma
17171 + h->root.u.def.section->output_offset);
17172 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 17173 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 17174 s = htab->root.sreldynrelro;
17175 else
17176 s = htab->root.srelbss;
47beaa6a 17177 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 17178 }
17179
00a97672 17180 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
fac7bd64
CL		 17181 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17182 it is relative to the ".got" section. */
9637f6ef 17183 if (h == htab->root.hdynamic
90c14f0c
L		 17184 || (!htab->fdpic_p
17185 && htab->root.target_os != is_vxworks
17186 && h == htab->root.hgot))
252b5132
RH		 17187 sym->st_shndx = SHN_ABS;
17188
b34976b6 17189 return TRUE;
252b5132
RH		 17190}
17191
0855e32b
NS		 17192static void
17193arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17194 void *contents,
17195 const unsigned long *template, unsigned count)
17196{
17197 unsigned ix;
b38cadfb 17198
0855e32b
NS		 17199 for (ix = 0; ix != count; ix++)
17200 {
17201 unsigned long insn = template[ix];
17202
17203 /* Emit mov pc,rx if bx is not permitted. */
17204 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17205 insn = (insn & 0xf000000f) | 0x01a0f000;
17206 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17207 }
17208}
17209
99059e56
RM		 17210/* Install the special first PLT entry for elf32-arm-nacl. Unlike
17211 other variants, NaCl needs this entry in a static executable's
17212 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17213 zero. For .iplt really only the last bundle is useful, and .iplt
17214 could have a shorter first entry, with each individual PLT entry's
17215 relative branch calculated differently so it targets the last
17216 bundle instead of the instruction before it (labelled .Lplt_tail
17217 above). But it's simpler to keep the size and layout of PLT0
17218 consistent with the dynamic case, at the cost of some dead code at
17219 the start of .iplt and the one dead store to the stack at the start
17220 of .Lplt_tail. */
17221static void
17222arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17223 asection *plt, bfd_vma got_displacement)
17224{
17225 unsigned int i;
17226
17227 put_arm_insn (htab, output_bfd,
17228 elf32_arm_nacl_plt0_entry[0]
17229 | arm_movw_immediate (got_displacement),
17230 plt->contents + 0);
17231 put_arm_insn (htab, output_bfd,
17232 elf32_arm_nacl_plt0_entry[1]
17233 | arm_movt_immediate (got_displacement),
17234 plt->contents + 4);
17235
17236 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17237 put_arm_insn (htab, output_bfd,
17238 elf32_arm_nacl_plt0_entry[i],
17239 plt->contents + (i * 4));
17240}
17241
252b5132
RH		 17242/* Finish up the dynamic sections. */
17243
b34976b6 17244static bfd_boolean
57e8b36a 17245elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 17246{
17247 bfd * dynobj;
17248 asection * sgot;
17249 asection * sdyn;
4dfe6ac6
NC		 17250 struct elf32_arm_link_hash_table *htab;
17251
17252 htab = elf32_arm_hash_table (info);
17253 if (htab == NULL)
17254 return FALSE;
252b5132
RH		 17255
17256 dynobj = elf_hash_table (info)->dynobj;
17257
362d30a1 17258 sgot = htab->root.sgotplt;
894891db
NC		 17259 /* A broken linker script might have discarded the dynamic sections.
17260 Catch this here so that we do not seg-fault later on. */
17261 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17262 return FALSE;
3d4d4302 17263 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 17264
17265 if (elf_hash_table (info)->dynamic_sections_created)
17266 {
17267 asection *splt;
17268 Elf32_External_Dyn *dyncon, *dynconend;
17269
362d30a1 17270 splt = htab->root.splt;
24a1ba0f 17271 BFD_ASSERT (splt != NULL && sdyn != NULL);
90c14f0c 17272 BFD_ASSERT (htab->root.target_os == is_symbian || sgot != NULL);
252b5132
RH		 17273
17274 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 17275 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 17276
252b5132
RH		 17277 for (; dyncon < dynconend; dyncon++)
17278 {
17279 Elf_Internal_Dyn dyn;
17280 const char * name;
17281 asection * s;
17282
17283 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17284
17285 switch (dyn.d_tag)
17286 {
229fcec5
MM		 17287 unsigned int type;
17288
252b5132 17289 default:
90c14f0c 17290 if (htab->root.target_os == is_vxworks
7a2b07ff
NS		 17291 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17292 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 17293 break;
17294
229fcec5
MM		 17295 case DT_HASH:
17296 name = ".hash";
17297 goto get_vma_if_bpabi;
17298 case DT_STRTAB:
17299 name = ".dynstr";
17300 goto get_vma_if_bpabi;
17301 case DT_SYMTAB:
17302 name = ".dynsym";
17303 goto get_vma_if_bpabi;
c0042f5d
MM		 17304 case DT_VERSYM:
17305 name = ".gnu.version";
17306 goto get_vma_if_bpabi;
17307 case DT_VERDEF:
17308 name = ".gnu.version_d";
17309 goto get_vma_if_bpabi;
17310 case DT_VERNEED:
17311 name = ".gnu.version_r";
17312 goto get_vma_if_bpabi;
17313
252b5132 17314 case DT_PLTGOT:
90c14f0c
L		 17315 name = (htab->root.target_os == is_symbian
17316 ? ".got" : ".got.plt");
252b5132
RH		 17317 goto get_vma;
17318 case DT_JMPREL:
00a97672 17319 name = RELOC_SECTION (htab, ".plt");
252b5132 17320 get_vma:
4ade44b7 17321 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 17322 if (s == NULL)
17323 {
4eca0228 17324 _bfd_error_handler
4ade44b7 17325 (_("could not find section %s"), name);
05456594
NC		 17326 bfd_set_error (bfd_error_invalid_operation);
17327 return FALSE;
17328 }
90c14f0c 17329 if (htab->root.target_os != is_symbian)
4ade44b7 17330 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 17331 else
17332 /* In the BPABI, tags in the PT_DYNAMIC section point
17333 at the file offset, not the memory address, for the
17334 convenience of the post linker. */
4ade44b7 17335 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 17336 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17337 break;
17338
229fcec5 17339 get_vma_if_bpabi:
90c14f0c 17340 if (htab->root.target_os == is_symbian)
229fcec5
MM		 17341 goto get_vma;
17342 break;
17343
252b5132 17344 case DT_PLTRELSZ:
362d30a1 17345 s = htab->root.srelplt;
252b5132 17346 BFD_ASSERT (s != NULL);
eea6121a 17347 dyn.d_un.d_val = s->size;
252b5132
RH		 17348 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17349 break;
906e58ca 17350
252b5132 17351 case DT_RELSZ:
00a97672 17352 case DT_RELASZ:
229fcec5
MM		 17353 case DT_REL:
17354 case DT_RELA:
229fcec5
MM		 17355 /* In the BPABI, the DT_REL tag must point at the file
17356 offset, not the VMA, of the first relocation
17357 section. So, we use code similar to that in
17358 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 17359 relocation section, since relocation sections are
17360 never allocated under the BPABI. PLT relocs are also
17361 included. */
90c14f0c 17362 if (htab->root.target_os == is_symbian)
229fcec5
MM		 17363 {
17364 unsigned int i;
17365 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
17366 ? SHT_REL : SHT_RELA);
17367 dyn.d_un.d_val = 0;
17368 for (i = 1; i < elf_numsections (output_bfd); i++)
17369 {
906e58ca 17370 Elf_Internal_Shdr *hdr
229fcec5
MM		 17371 = elf_elfsections (output_bfd)[i];
17372 if (hdr->sh_type == type)
17373 {
906e58ca 17374 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 17375 || dyn.d_tag == DT_RELASZ)
17376 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 17377 else if ((ufile_ptr) hdr->sh_offset
17378 <= dyn.d_un.d_val - 1)
229fcec5
MM		 17379 dyn.d_un.d_val = hdr->sh_offset;
17380 }
17381 }
17382 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17383 }
252b5132 17384 break;
88f7bcd5 17385
0855e32b 17386 case DT_TLSDESC_PLT:
99059e56 17387 s = htab->root.splt;
0855e32b 17388 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
9bcc30e4 17389 + htab->root.tlsdesc_plt);
0855e32b
NS		 17390 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17391 break;
17392
17393 case DT_TLSDESC_GOT:
99059e56 17394 s = htab->root.sgot;
0855e32b 17395 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
9bcc30e4 17396 + htab->root.tlsdesc_got);
0855e32b
NS		 17397 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17398 break;
17399
88f7bcd5
NC		 17400 /* Set the bottom bit of DT_INIT/FINI if the
17401 corresponding function is Thumb. */
17402 case DT_INIT:
17403 name = info->init_function;
17404 goto get_sym;
17405 case DT_FINI:
17406 name = info->fini_function;
17407 get_sym:
17408 /* If it wasn't set by elf_bfd_final_link
4cc11e76 17409 then there is nothing to adjust. */
88f7bcd5
NC		 17410 if (dyn.d_un.d_val != 0)
17411 {
17412 struct elf_link_hash_entry * eh;
17413
17414 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 17415 FALSE, FALSE, TRUE);
39d911fc
TP		 17416 if (eh != NULL
17417 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17418 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 17419 {
17420 dyn.d_un.d_val |= 1;
b34976b6 17421 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 17422 }
17423 }
17424 break;
252b5132
RH		 17425 }
17426 }
17427
24a1ba0f 17428 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 17429 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 17430 {
00a97672
RS		 17431 const bfd_vma *plt0_entry;
17432 bfd_vma got_address, plt_address, got_displacement;
17433
17434 /* Calculate the addresses of the GOT and PLT. */
17435 got_address = sgot->output_section->vma + sgot->output_offset;
17436 plt_address = splt->output_section->vma + splt->output_offset;
17437
90c14f0c 17438 if (htab->root.target_os == is_vxworks)
00a97672
RS		 17439 {
17440 /* The VxWorks GOT is relocated by the dynamic linker.
17441 Therefore, we must emit relocations rather than simply
17442 computing the values now. */
17443 Elf_Internal_Rela rel;
17444
17445 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 17446 put_arm_insn (htab, output_bfd, plt0_entry[0],
17447 splt->contents + 0);
17448 put_arm_insn (htab, output_bfd, plt0_entry[1],
17449 splt->contents + 4);
17450 put_arm_insn (htab, output_bfd, plt0_entry[2],
17451 splt->contents + 8);
00a97672
RS		 17452 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17453
8029a119 17454 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 17455 rel.r_offset = plt_address + 12;
17456 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17457 rel.r_addend = 0;
17458 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17459 htab->srelplt2->contents);
17460 }
90c14f0c 17461 else if (htab->root.target_os == is_nacl)
99059e56
RM		 17462 arm_nacl_put_plt0 (htab, output_bfd, splt,
17463 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 17464 else if (using_thumb_only (htab))
17465 {
17466 got_displacement = got_address - (plt_address + 12);
17467
17468 plt0_entry = elf32_thumb2_plt0_entry;
17469 put_arm_insn (htab, output_bfd, plt0_entry[0],
17470 splt->contents + 0);
17471 put_arm_insn (htab, output_bfd, plt0_entry[1],
17472 splt->contents + 4);
17473 put_arm_insn (htab, output_bfd, plt0_entry[2],
17474 splt->contents + 8);
17475
17476 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17477 }
00a97672
RS		 17478 else
17479 {
17480 got_displacement = got_address - (plt_address + 16);
17481
17482 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 17483 put_arm_insn (htab, output_bfd, plt0_entry[0],
17484 splt->contents + 0);
17485 put_arm_insn (htab, output_bfd, plt0_entry[1],
17486 splt->contents + 4);
17487 put_arm_insn (htab, output_bfd, plt0_entry[2],
17488 splt->contents + 8);
17489 put_arm_insn (htab, output_bfd, plt0_entry[3],
17490 splt->contents + 12);
5e681ec4 17491
5e681ec4 17492#ifdef FOUR_WORD_PLT
00a97672
RS		 17493 /* The displacement value goes in the otherwise-unused
17494 last word of the second entry. */
17495 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 17496#else
00a97672 17497 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 17498#endif
00a97672 17499 }
f7a74f8c 17500 }
252b5132
RH		 17501
17502 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17503 really seem like the right value. */
74541ad4
AM		 17504 if (splt->output_section->owner == output_bfd)
17505 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 17506
9bcc30e4 17507 if (htab->root.tlsdesc_plt)
0855e32b
NS		 17508 {
17509 bfd_vma got_address
17510 = sgot->output_section->vma + sgot->output_offset;
17511 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17512 + htab->root.sgot->output_offset);
17513 bfd_vma plt_address
17514 = splt->output_section->vma + splt->output_offset;
17515
b38cadfb 17516 arm_put_trampoline (htab, output_bfd,
9bcc30e4 17517 splt->contents + htab->root.tlsdesc_plt,
0855e32b
NS		 17518 dl_tlsdesc_lazy_trampoline, 6);
17519
17520 bfd_put_32 (output_bfd,
9bcc30e4
L		 17521 gotplt_address + htab->root.tlsdesc_got
17522 - (plt_address + htab->root.tlsdesc_plt)
0855e32b 17523 - dl_tlsdesc_lazy_trampoline[6],
9bcc30e4 17524 splt->contents + htab->root.tlsdesc_plt + 24);
0855e32b 17525 bfd_put_32 (output_bfd,
9bcc30e4 17526 got_address - (plt_address + htab->root.tlsdesc_plt)
0855e32b 17527 - dl_tlsdesc_lazy_trampoline[7],
9bcc30e4 17528 splt->contents + htab->root.tlsdesc_plt + 24 + 4);
0855e32b
NS		 17529 }
17530
17531 if (htab->tls_trampoline)
17532 {
b38cadfb 17533 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17534 splt->contents + htab->tls_trampoline,
17535 tls_trampoline, 3);
17536#ifdef FOUR_WORD_PLT
17537 bfd_put_32 (output_bfd, 0x00000000,
17538 splt->contents + htab->tls_trampoline + 12);
b38cadfb 17539#endif
0855e32b
NS		 17540 }
17541
90c14f0c 17542 if (htab->root.target_os == is_vxworks
0e1862bb
L		 17543 && !bfd_link_pic (info)
17544 && htab->root.splt->size > 0)
00a97672
RS		 17545 {
17546 /* Correct the .rel(a).plt.unloaded relocations. They will have
17547 incorrect symbol indexes. */
17548 int num_plts;
eed62c48 17549 unsigned char *p;
00a97672 17550
362d30a1 17551 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 17552 / htab->plt_entry_size);
17553 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17554
17555 for (; num_plts; num_plts--)
17556 {
17557 Elf_Internal_Rela rel;
17558
17559 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17560 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17561 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17562 p += RELOC_SIZE (htab);
17563
17564 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17565 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17566 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17567 p += RELOC_SIZE (htab);
17568 }
17569 }
252b5132
RH		 17570 }
17571
90c14f0c
L		 17572 if (htab->root.target_os == is_nacl
17573 && htab->root.iplt != NULL
17574 && htab->root.iplt->size > 0)
99059e56
RM		 17575 /* NaCl uses a special first entry in .iplt too. */
17576 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17577
252b5132 17578 /* Fill in the first three entries in the global offset table. */
229fcec5 17579 if (sgot)
252b5132 17580 {
229fcec5
MM		 17581 if (sgot->size > 0)
17582 {
17583 if (sdyn == NULL)
17584 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17585 else
17586 bfd_put_32 (output_bfd,
17587 sdyn->output_section->vma + sdyn->output_offset,
17588 sgot->contents);
17589 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17590 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17591 }
252b5132 17592
229fcec5
MM		 17593 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17594 }
252b5132 17595
e8b09b87
CL		 17596 /* At the very end of the .rofixup section is a pointer to the GOT. */
17597 if (htab->fdpic_p && htab->srofixup != NULL)
17598 {
17599 struct elf_link_hash_entry *hgot = htab->root.hgot;
17600
17601 bfd_vma got_value = hgot->root.u.def.value
17602 + hgot->root.u.def.section->output_section->vma
17603 + hgot->root.u.def.section->output_offset;
17604
17605 arm_elf_add_rofixup(output_bfd, htab->srofixup, got_value);
17606
17607 /* Make sure we allocated and generated the same number of fixups. */
17608 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17609 }
17610
b34976b6 17611 return TRUE;
252b5132
RH		 17612}
17613
ed7e9d0b
AM		 17614static bfd_boolean
17615elf32_arm_init_file_header (bfd *abfd, struct bfd_link_info *link_info)
ba96a88f 17616{
9b485d32 17617 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 17618 struct elf32_arm_link_hash_table *globals;
ac4c9b04 17619 struct elf_segment_map *m;
ba96a88f 17620
ed7e9d0b
AM		 17621 if (!_bfd_elf_init_file_header (abfd, link_info))
17622 return FALSE;
17623
ba96a88f
NC		 17624 i_ehdrp = elf_elfheader (abfd);
17625
94a3258f
PB		 17626 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17627 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
ba96a88f 17628 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 17629
93204d3a
PB		 17630 if (link_info)
17631 {
17632 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 17633 if (globals != NULL && globals->byteswap_code)
93204d3a 17634 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 17635
17636 if (globals->fdpic_p)
17637 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 17638 }
3bfcb652
NC		 17639
17640 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17641 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17642 {
17643 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 17644 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 17645 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17646 else
17647 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17648 }
ac4c9b04
MG		 17649
17650 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 17651 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 17652 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17653 {
17654 unsigned int j;
17655
17656 if (m->count == 0)
17657 continue;
17658 for (j = 0; j < m->count; j++)
17659 {
f0728ee3 17660 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 17661 break;
17662 }
17663 if (j == m->count)
17664 {
17665 m->p_flags = PF_X;
17666 m->p_flags_valid = 1;
17667 }
17668 }
ed7e9d0b 17669 return TRUE;
ba96a88f
NC		 17670}
17671
99e4ae17 17672static enum elf_reloc_type_class
7e612e98
AM		 17673elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17674 const asection *rel_sec ATTRIBUTE_UNUSED,
17675 const Elf_Internal_Rela *rela)
99e4ae17 17676{
f51e552e 17677 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 17678 {
17679 case R_ARM_RELATIVE:
17680 return reloc_class_relative;
17681 case R_ARM_JUMP_SLOT:
17682 return reloc_class_plt;
17683 case R_ARM_COPY:
17684 return reloc_class_copy;
109575d7
JW		 17685 case R_ARM_IRELATIVE:
17686 return reloc_class_ifunc;
99e4ae17
AJ		 17687 default:
17688 return reloc_class_normal;
17689 }
17690}
17691
e489d0ae 17692static void
cc364be6 17693arm_final_write_processing (bfd *abfd)
e16bb312 17694{
5a6c6817 17695 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 17696}
17697
cc364be6
AM		 17698static bfd_boolean
17699elf32_arm_final_write_processing (bfd *abfd)
06f44071 17700{
cc364be6
AM		 17701 arm_final_write_processing (abfd);
17702 return _bfd_elf_final_write_processing (abfd);
06f44071
AM		 17703}
17704
40a18ebd
NC		 17705/* Return TRUE if this is an unwinding table entry. */
17706
17707static bfd_boolean
17708is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17709{
0112cd26
NC		 17710 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
17711 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 17712}
17713
17714
17715/* Set the type and flags for an ARM section. We do this by
17716 the section name, which is a hack, but ought to work. */
17717
17718static bfd_boolean
17719elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17720{
17721 const char * name;
17722
fd361982 17723 name = bfd_section_name (sec);
40a18ebd
NC		 17724
17725 if (is_arm_elf_unwind_section_name (abfd, name))
17726 {
17727 hdr->sh_type = SHT_ARM_EXIDX;
17728 hdr->sh_flags |= SHF_LINK_ORDER;
17729 }
ac4c9b04 17730
f0728ee3
AV		 17731 if (sec->flags & SEC_ELF_PURECODE)
17732 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 17733
40a18ebd
NC		 17734 return TRUE;
17735}
17736
6dc132d9
L		 17737/* Handle an ARM specific section when reading an object file. This is
17738 called when bfd_section_from_shdr finds a section with an unknown
17739 type. */
40a18ebd
NC		 17740
17741static bfd_boolean
17742elf32_arm_section_from_shdr (bfd *abfd,
17743 Elf_Internal_Shdr * hdr,
6dc132d9
L		 17744 const char *name,
17745 int shindex)
40a18ebd
NC		 17746{
17747 /* There ought to be a place to keep ELF backend specific flags, but
17748 at the moment there isn't one. We just keep track of the
17749 sections by their name, instead. Fortunately, the ABI gives
17750 names for all the ARM specific sections, so we will probably get
17751 away with this. */
17752 switch (hdr->sh_type)
17753 {
17754 case SHT_ARM_EXIDX:
0951f019
RE		 17755 case SHT_ARM_PREEMPTMAP:
17756 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 17757 break;
17758
17759 default:
17760 return FALSE;
17761 }
17762
6dc132d9 17763 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 17764 return FALSE;
17765
17766 return TRUE;
17767}
e489d0ae 17768
44444f50
NC		 17769static _arm_elf_section_data *
17770get_arm_elf_section_data (asection * sec)
17771{
47b2e99c
JZ		 17772 if (sec && sec->owner && is_arm_elf (sec->owner))
17773 return elf32_arm_section_data (sec);
44444f50
NC		 17774 else
17775 return NULL;
8e3de13a
NC		 17776}
17777
4e617b1e
PB		 17778typedef struct
17779{
57402f1e 17780 void *flaginfo;
4e617b1e 17781 struct bfd_link_info *info;
91a5743d
PB		 17782 asection *sec;
17783 int sec_shndx;
6e0b88f1
AM		 17784 int (*func) (void *, const char *, Elf_Internal_Sym *,
17785 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 17786} output_arch_syminfo;
17787
17788enum map_symbol_type
17789{
17790 ARM_MAP_ARM,
17791 ARM_MAP_THUMB,
17792 ARM_MAP_DATA
17793};
17794
17795
7413f23f 17796/* Output a single mapping symbol. */
4e617b1e
PB		 17797
17798static bfd_boolean
7413f23f
DJ		 17799elf32_arm_output_map_sym (output_arch_syminfo *osi,
17800 enum map_symbol_type type,
17801 bfd_vma offset)
4e617b1e
PB		 17802{
17803 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 17804 Elf_Internal_Sym sym;
17805
91a5743d
PB		 17806 sym.st_value = osi->sec->output_section->vma
17807 + osi->sec->output_offset
17808 + offset;
4e617b1e
PB		 17809 sym.st_size = 0;
17810 sym.st_other = 0;
17811 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 17812 sym.st_shndx = osi->sec_shndx;
35fc36a8 17813 sym.st_target_internal = 0;
fe33d2fa 17814 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 17815 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 17816}
17817
34e77a92
RS		 17818/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17819 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 17820
17821static bfd_boolean
34e77a92
RS		 17822elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
17823 bfd_boolean is_iplt_entry_p,
17824 union gotplt_union *root_plt,
17825 struct arm_plt_info *arm_plt)
4e617b1e 17826{
4e617b1e 17827 struct elf32_arm_link_hash_table *htab;
34e77a92 17828 bfd_vma addr, plt_header_size;
4e617b1e 17829
34e77a92 17830 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 17831 return TRUE;
17832
4dfe6ac6
NC		 17833 htab = elf32_arm_hash_table (osi->info);
17834 if (htab == NULL)
17835 return FALSE;
17836
34e77a92
RS		 17837 if (is_iplt_entry_p)
17838 {
17839 osi->sec = htab->root.iplt;
17840 plt_header_size = 0;
17841 }
17842 else
17843 {
17844 osi->sec = htab->root.splt;
17845 plt_header_size = htab->plt_header_size;
17846 }
17847 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
17848 (osi->info->output_bfd, osi->sec->output_section));
17849
17850 addr = root_plt->offset & -2;
90c14f0c 17851 if (htab->root.target_os == is_symbian)
4e617b1e 17852 {
7413f23f 17853 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17854 return FALSE;
7413f23f 17855 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 17856 return FALSE;
17857 }
90c14f0c 17858 else if (htab->root.target_os == is_vxworks)
4e617b1e 17859 {
7413f23f 17860 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17861 return FALSE;
7413f23f 17862 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 17863 return FALSE;
7413f23f 17864 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 17865 return FALSE;
7413f23f 17866 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 17867 return FALSE;
17868 }
90c14f0c 17869 else if (htab->root.target_os == is_nacl)
b38cadfb
NC		 17870 {
17871 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
17872 return FALSE;
17873 }
7801f98f
CL		 17874 else if (htab->fdpic_p)
17875 {
59029f57
CL		 17876 enum map_symbol_type type = using_thumb_only(htab)
17877 ? ARM_MAP_THUMB
17878 : ARM_MAP_ARM;
17879
7801f98f 17880 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
4b24dd1a
AM		 17881 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
17882 return FALSE;
59029f57 17883 if (!elf32_arm_output_map_sym (osi, type, addr))
4b24dd1a 17884 return FALSE;
7801f98f 17885 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
4b24dd1a 17886 return FALSE;
7801f98f 17887 if (htab->plt_entry_size == 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry))
4b24dd1a
AM		 17888 if (!elf32_arm_output_map_sym (osi, type, addr + 24))
17889 return FALSE;
7801f98f 17890 }
eed94f8f
NC		 17891 else if (using_thumb_only (htab))
17892 {
17893 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
17894 return FALSE;
6a631e86 17895 }
4e617b1e
PB		 17896 else
17897 {
34e77a92 17898 bfd_boolean thumb_stub_p;
bd97cb95 17899
34e77a92
RS		 17900 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
17901 if (thumb_stub_p)
4e617b1e 17902 {
7413f23f 17903 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 17904 return FALSE;
17905 }
17906#ifdef FOUR_WORD_PLT
7413f23f 17907 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17908 return FALSE;
7413f23f 17909 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 17910 return FALSE;
17911#else
906e58ca 17912 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 17913 so only need to output a mapping symbol for the first PLT entry and
17914 entries with thumb thunks. */
34e77a92 17915 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 17916 {
7413f23f 17917 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 17918 return FALSE;
17919 }
17920#endif
17921 }
17922
17923 return TRUE;
17924}
17925
34e77a92
RS		 17926/* Output mapping symbols for PLT entries associated with H. */
17927
17928static bfd_boolean
17929elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
17930{
17931 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
17932 struct elf32_arm_link_hash_entry *eh;
17933
17934 if (h->root.type == bfd_link_hash_indirect)
17935 return TRUE;
17936
17937 if (h->root.type == bfd_link_hash_warning)
17938 /* When warning symbols are created, they **replace** the "real"
17939 entry in the hash table, thus we never get to see the real
17940 symbol in a hash traversal. So look at it now. */
17941 h = (struct elf_link_hash_entry *) h->root.u.i.link;
17942
17943 eh = (struct elf32_arm_link_hash_entry *) h;
17944 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
17945 &h->plt, &eh->plt);
17946}
17947
4f4faa4d
TP		 17948/* Bind a veneered symbol to its veneer identified by its hash entry
17949 STUB_ENTRY. The veneered location thus loose its symbol. */
17950
17951static void
17952arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
17953{
17954 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
17955
17956 BFD_ASSERT (hash);
17957 hash->root.root.u.def.section = stub_entry->stub_sec;
17958 hash->root.root.u.def.value = stub_entry->stub_offset;
17959 hash->root.size = stub_entry->stub_size;
17960}
17961
7413f23f
DJ		 17962/* Output a single local symbol for a generated stub. */
17963
17964static bfd_boolean
17965elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
17966 bfd_vma offset, bfd_vma size)
17967{
7413f23f
DJ		 17968 Elf_Internal_Sym sym;
17969
7413f23f
DJ		 17970 sym.st_value = osi->sec->output_section->vma
17971 + osi->sec->output_offset
17972 + offset;
17973 sym.st_size = size;
17974 sym.st_other = 0;
17975 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
17976 sym.st_shndx = osi->sec_shndx;
35fc36a8 17977 sym.st_target_internal = 0;
57402f1e 17978 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 17979}
4e617b1e 17980
da5938a2 17981static bfd_boolean
8029a119
NC		 17982arm_map_one_stub (struct bfd_hash_entry * gen_entry,
17983 void * in_arg)
da5938a2
NC		 17984{
17985 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 17986 asection *stub_sec;
17987 bfd_vma addr;
7413f23f 17988 char *stub_name;
9a008db3 17989 output_arch_syminfo *osi;
d3ce72d0 17990 const insn_sequence *template_sequence;
461a49ca
DJ		 17991 enum stub_insn_type prev_type;
17992 int size;
17993 int i;
17994 enum map_symbol_type sym_type;
da5938a2
NC		 17995
17996 /* Massage our args to the form they really have. */
17997 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 17998 osi = (output_arch_syminfo *) in_arg;
da5938a2 17999
da5938a2
NC		 18000 stub_sec = stub_entry->stub_sec;
18001
18002 /* Ensure this stub is attached to the current section being
7413f23f 18003 processed. */
da5938a2
NC		 18004 if (stub_sec != osi->sec)
18005 return TRUE;
18006
7413f23f 18007 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 18008 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 18009
18010 if (arm_stub_sym_claimed (stub_entry->stub_type))
18011 arm_stub_claim_sym (stub_entry);
18012 else
7413f23f 18013 {
4f4faa4d
TP		 18014 stub_name = stub_entry->output_name;
18015 switch (template_sequence[0].type)
18016 {
18017 case ARM_TYPE:
18018 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
18019 stub_entry->stub_size))
18020 return FALSE;
18021 break;
18022 case THUMB16_TYPE:
18023 case THUMB32_TYPE:
18024 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
18025 stub_entry->stub_size))
18026 return FALSE;
18027 break;
18028 default:
18029 BFD_FAIL ();
18030 return 0;
18031 }
7413f23f 18032 }
da5938a2 18033
461a49ca
DJ		 18034 prev_type = DATA_TYPE;
18035 size = 0;
18036 for (i = 0; i < stub_entry->stub_template_size; i++)
18037 {
d3ce72d0 18038 switch (template_sequence[i].type)
461a49ca
DJ		 18039 {
18040 case ARM_TYPE:
18041 sym_type = ARM_MAP_ARM;
18042 break;
18043
18044 case THUMB16_TYPE:
48229727 18045 case THUMB32_TYPE:
461a49ca
DJ		 18046 sym_type = ARM_MAP_THUMB;
18047 break;
18048
18049 case DATA_TYPE:
18050 sym_type = ARM_MAP_DATA;
18051 break;
18052
18053 default:
18054 BFD_FAIL ();
4e31c731 18055 return FALSE;
461a49ca
DJ		 18056 }
18057
d3ce72d0 18058 if (template_sequence[i].type != prev_type)
461a49ca 18059 {
d3ce72d0 18060 prev_type = template_sequence[i].type;
461a49ca
DJ		 18061 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
18062 return FALSE;
18063 }
18064
d3ce72d0 18065 switch (template_sequence[i].type)
461a49ca
DJ		 18066 {
18067 case ARM_TYPE:
48229727 18068 case THUMB32_TYPE:
461a49ca
DJ		 18069 size += 4;
18070 break;
18071
18072 case THUMB16_TYPE:
18073 size += 2;
18074 break;
18075
18076 case DATA_TYPE:
18077 size += 4;
18078 break;
18079
18080 default:
18081 BFD_FAIL ();
4e31c731 18082 return FALSE;
461a49ca
DJ		 18083 }
18084 }
18085
da5938a2
NC		 18086 return TRUE;
18087}
18088
33811162
DG		 18089/* Output mapping symbols for linker generated sections,
18090 and for those data-only sections that do not have a
18091 $d. */
4e617b1e
PB		 18092
18093static bfd_boolean
18094elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 18095 struct bfd_link_info *info,
57402f1e 18096 void *flaginfo,
6e0b88f1
AM		 18097 int (*func) (void *, const char *,
18098 Elf_Internal_Sym *,
18099 asection *,
18100 struct elf_link_hash_entry *))
4e617b1e
PB		 18101{
18102 output_arch_syminfo osi;
18103 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 18104 bfd_vma offset;
18105 bfd_size_type size;
33811162 18106 bfd *input_bfd;
4e617b1e
PB		 18107
18108 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 18109 if (htab == NULL)
18110 return FALSE;
18111
906e58ca 18112 check_use_blx (htab);
91a5743d 18113
57402f1e 18114 osi.flaginfo = flaginfo;
4e617b1e
PB		 18115 osi.info = info;
18116 osi.func = func;
906e58ca 18117
33811162
DG		 18118 /* Add a $d mapping symbol to data-only sections that
18119 don't have any mapping symbol. This may result in (harmless) redundant
18120 mapping symbols. */
18121 for (input_bfd = info->input_bfds;
18122 input_bfd != NULL;
c72f2fb2 18123 input_bfd = input_bfd->link.next)
33811162
DG		 18124 {
18125 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18126 for (osi.sec = input_bfd->sections;
18127 osi.sec != NULL;
18128 osi.sec = osi.sec->next)
18129 {
18130 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 18131 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18132 != 0)
33811162
DG		 18133 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18134 == SEC_HAS_CONTENTS
18135 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 18136 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 18137 && osi.sec->size > 0
18138 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 18139 {
18140 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18141 (output_bfd, osi.sec->output_section);
18142 if (osi.sec_shndx != (int)SHN_BAD)
18143 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18144 }
18145 }
18146 }
18147
91a5743d
PB		 18148 /* ARM->Thumb glue. */
18149 if (htab->arm_glue_size > 0)
18150 {
3d4d4302
AM		 18151 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18152 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 18153
18154 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18155 (output_bfd, osi.sec->output_section);
0e1862bb 18156 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 18157 || htab->pic_veneer)
18158 size = ARM2THUMB_PIC_GLUE_SIZE;
18159 else if (htab->use_blx)
18160 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18161 else
18162 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 18163
91a5743d
PB		 18164 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18165 {
7413f23f
DJ		 18166 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18167 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 18168 }
18169 }
18170
18171 /* Thumb->ARM glue. */
18172 if (htab->thumb_glue_size > 0)
18173 {
3d4d4302
AM		 18174 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18175 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 18176
18177 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18178 (output_bfd, osi.sec->output_section);
18179 size = THUMB2ARM_GLUE_SIZE;
18180
18181 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18182 {
7413f23f
DJ		 18183 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18184 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 18185 }
18186 }
18187
845b51d6
PB		 18188 /* ARMv4 BX veneers. */
18189 if (htab->bx_glue_size > 0)
18190 {
3d4d4302
AM		 18191 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18192 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 18193
18194 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18195 (output_bfd, osi.sec->output_section);
18196
7413f23f 18197 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 18198 }
18199
8029a119
NC		 18200 /* Long calls stubs. */
18201 if (htab->stub_bfd && htab->stub_bfd->sections)
18202 {
da5938a2 18203 asection* stub_sec;
8029a119 18204
da5938a2
NC		 18205 for (stub_sec = htab->stub_bfd->sections;
18206 stub_sec != NULL;
8029a119
NC		 18207 stub_sec = stub_sec->next)
18208 {
18209 /* Ignore non-stub sections. */
18210 if (!strstr (stub_sec->name, STUB_SUFFIX))
18211 continue;
da5938a2 18212
8029a119 18213 osi.sec = stub_sec;
da5938a2 18214
8029a119
NC		 18215 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18216 (output_bfd, osi.sec->output_section);
da5938a2 18217
8029a119
NC		 18218 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18219 }
18220 }
da5938a2 18221
91a5743d 18222 /* Finally, output mapping symbols for the PLT. */
34e77a92 18223 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 18224 {
34e77a92
RS		 18225 osi.sec = htab->root.splt;
18226 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18227 (output_bfd, osi.sec->output_section));
18228
18229 /* Output mapping symbols for the plt header. SymbianOS does not have a
18230 plt header. */
90c14f0c 18231 if (htab->root.target_os == is_vxworks)
34e77a92
RS		 18232 {
18233 /* VxWorks shared libraries have no PLT header. */
0e1862bb 18234 if (!bfd_link_pic (info))
34e77a92
RS		 18235 {
18236 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18237 return FALSE;
18238 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18239 return FALSE;
18240 }
18241 }
90c14f0c 18242 else if (htab->root.target_os == is_nacl)
b38cadfb
NC		 18243 {
18244 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18245 return FALSE;
18246 }
59029f57 18247 else if (using_thumb_only (htab) && !htab->fdpic_p)
eed94f8f
NC		 18248 {
18249 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18250 return FALSE;
18251 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18252 return FALSE;
18253 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18254 return FALSE;
18255 }
90c14f0c 18256 else if (htab->root.target_os != is_symbian && !htab->fdpic_p)
4e617b1e 18257 {
7413f23f 18258 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 18259 return FALSE;
34e77a92
RS		 18260#ifndef FOUR_WORD_PLT
18261 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 18262 return FALSE;
34e77a92 18263#endif
4e617b1e
PB		 18264 }
18265 }
90c14f0c
L		 18266 if (htab->root.target_os == is_nacl
18267 && htab->root.iplt
18268 && htab->root.iplt->size > 0)
99059e56
RM		 18269 {
18270 /* NaCl uses a special first entry in .iplt too. */
18271 osi.sec = htab->root.iplt;
18272 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18273 (output_bfd, osi.sec->output_section));
18274 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18275 return FALSE;
18276 }
34e77a92
RS		 18277 if ((htab->root.splt && htab->root.splt->size > 0)
18278 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 18279 {
34e77a92
RS		 18280 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18281 for (input_bfd = info->input_bfds;
18282 input_bfd != NULL;
c72f2fb2 18283 input_bfd = input_bfd->link.next)
34e77a92
RS		 18284 {
18285 struct arm_local_iplt_info **local_iplt;
18286 unsigned int i, num_syms;
4e617b1e 18287
34e77a92
RS		 18288 local_iplt = elf32_arm_local_iplt (input_bfd);
18289 if (local_iplt != NULL)
18290 {
18291 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18292 for (i = 0; i < num_syms; i++)
18293 if (local_iplt[i] != NULL
18294 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
18295 &local_iplt[i]->root,
18296 &local_iplt[i]->arm))
18297 return FALSE;
18298 }
18299 }
18300 }
9bcc30e4 18301 if (htab->root.tlsdesc_plt != 0)
0855e32b
NS		 18302 {
18303 /* Mapping symbols for the lazy tls trampoline. */
9bcc30e4
L		 18304 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM,
18305 htab->root.tlsdesc_plt))
0855e32b 18306 return FALSE;
b38cadfb 18307
0855e32b 18308 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
9bcc30e4 18309 htab->root.tlsdesc_plt + 24))
0855e32b
NS		 18310 return FALSE;
18311 }
18312 if (htab->tls_trampoline != 0)
18313 {
18314 /* Mapping symbols for the tls trampoline. */
18315 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18316 return FALSE;
18317#ifdef FOUR_WORD_PLT
18318 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18319 htab->tls_trampoline + 12))
18320 return FALSE;
b38cadfb 18321#endif
0855e32b 18322 }
b38cadfb 18323
4e617b1e
PB		 18324 return TRUE;
18325}
18326
54ddd295
TP		 18327/* Filter normal symbols of CMSE entry functions of ABFD to include in
18328 the import library. All SYMCOUNT symbols of ABFD can be examined
18329 from their pointers in SYMS. Pointers of symbols to keep should be
18330 stored continuously at the beginning of that array.
18331
18332 Returns the number of symbols to keep. */
18333
18334static unsigned int
18335elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18336 struct bfd_link_info *info,
18337 asymbol **syms, long symcount)
18338{
18339 size_t maxnamelen;
18340 char *cmse_name;
18341 long src_count, dst_count = 0;
18342 struct elf32_arm_link_hash_table *htab;
18343
18344 htab = elf32_arm_hash_table (info);
18345 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18346 symcount = 0;
18347
18348 maxnamelen = 128;
18349 cmse_name = (char *) bfd_malloc (maxnamelen);
7a0fb7be
NC		 18350 BFD_ASSERT (cmse_name);
18351
54ddd295
TP		 18352 for (src_count = 0; src_count < symcount; src_count++)
18353 {
18354 struct elf32_arm_link_hash_entry *cmse_hash;
18355 asymbol *sym;
18356 flagword flags;
18357 char *name;
18358 size_t namelen;
18359
18360 sym = syms[src_count];
18361 flags = sym->flags;
18362 name = (char *) bfd_asymbol_name (sym);
18363
18364 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18365 continue;
18366 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18367 continue;
18368
18369 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18370 if (namelen > maxnamelen)
18371 {
18372 cmse_name = (char *)
18373 bfd_realloc (cmse_name, namelen);
18374 maxnamelen = namelen;
18375 }
18376 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18377 cmse_hash = (struct elf32_arm_link_hash_entry *)
18378 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
18379
18380 if (!cmse_hash
18381 || (cmse_hash->root.root.type != bfd_link_hash_defined
18382 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18383 || cmse_hash->root.type != STT_FUNC)
18384 continue;
18385
54ddd295
TP		 18386 syms[dst_count++] = sym;
18387 }
18388 free (cmse_name);
18389
18390 syms[dst_count] = NULL;
18391
18392 return dst_count;
18393}
18394
18395/* Filter symbols of ABFD to include in the import library. All
18396 SYMCOUNT symbols of ABFD can be examined from their pointers in
18397 SYMS. Pointers of symbols to keep should be stored continuously at
18398 the beginning of that array.
18399
18400 Returns the number of symbols to keep. */
18401
18402static unsigned int
18403elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18404 struct bfd_link_info *info,
18405 asymbol **syms, long symcount)
18406{
18407 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18408
046734ff
TP		 18409 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18410 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18411 library to be a relocatable object file. */
18412 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 18413 if (globals->cmse_implib)
18414 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18415 else
18416 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18417}
18418
e489d0ae
PB		 18419/* Allocate target specific section data. */
18420
18421static bfd_boolean
18422elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18423{
f592407e
AM		 18424 if (!sec->used_by_bfd)
18425 {
18426 _arm_elf_section_data *sdata;
986f0783 18427 size_t amt = sizeof (*sdata);
e489d0ae 18428
21d799b5 18429 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 18430 if (sdata == NULL)
18431 return FALSE;
18432 sec->used_by_bfd = sdata;
18433 }
e489d0ae
PB		 18434
18435 return _bfd_elf_new_section_hook (abfd, sec);
18436}
18437
18438
18439/* Used to order a list of mapping symbols by address. */
18440
18441static int
18442elf32_arm_compare_mapping (const void * a, const void * b)
18443{
7f6a71ff
JM		 18444 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18445 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18446
18447 if (amap->vma > bmap->vma)
18448 return 1;
18449 else if (amap->vma < bmap->vma)
18450 return -1;
18451 else if (amap->type > bmap->type)
18452 /* Ensure results do not depend on the host qsort for objects with
18453 multiple mapping symbols at the same address by sorting on type
18454 after vma. */
18455 return 1;
18456 else if (amap->type < bmap->type)
18457 return -1;
18458 else
18459 return 0;
e489d0ae
PB		 18460}
18461
2468f9c9
PB		 18462/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18463
18464static unsigned long
18465offset_prel31 (unsigned long addr, bfd_vma offset)
18466{
18467 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18468}
18469
18470/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18471 relocations. */
18472
18473static void
18474copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18475{
18476 unsigned long first_word = bfd_get_32 (output_bfd, from);
18477 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 18478
2468f9c9
PB		 18479 /* High bit of first word is supposed to be zero. */
18480 if ((first_word & 0x80000000ul) == 0)
18481 first_word = offset_prel31 (first_word, offset);
b38cadfb 18482
2468f9c9
PB		 18483 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18484 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18485 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18486 second_word = offset_prel31 (second_word, offset);
b38cadfb 18487
2468f9c9
PB		 18488 bfd_put_32 (output_bfd, first_word, to);
18489 bfd_put_32 (output_bfd, second_word, to + 4);
18490}
e489d0ae 18491
48229727
JB		 18492/* Data for make_branch_to_a8_stub(). */
18493
b38cadfb
NC		 18494struct a8_branch_to_stub_data
18495{
48229727
JB		 18496 asection *writing_section;
18497 bfd_byte *contents;
18498};
18499
18500
18501/* Helper to insert branches to Cortex-A8 erratum stubs in the right
18502 places for a particular section. */
18503
18504static bfd_boolean
18505make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 18506 void *in_arg)
48229727
JB		 18507{
18508 struct elf32_arm_stub_hash_entry *stub_entry;
18509 struct a8_branch_to_stub_data *data;
18510 bfd_byte *contents;
18511 unsigned long branch_insn;
18512 bfd_vma veneered_insn_loc, veneer_entry_loc;
18513 bfd_signed_vma branch_offset;
18514 bfd *abfd;
8d9d9490 18515 unsigned int loc;
48229727
JB		 18516
18517 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18518 data = (struct a8_branch_to_stub_data *) in_arg;
18519
18520 if (stub_entry->target_section != data->writing_section
4563a860 18521 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 18522 return TRUE;
18523
18524 contents = data->contents;
18525
8d9d9490
TP		 18526 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18527 generated when both source and target are in the same section. */
48229727
JB		 18528 veneered_insn_loc = stub_entry->target_section->output_section->vma
18529 + stub_entry->target_section->output_offset
8d9d9490 18530 + stub_entry->source_value;
48229727
JB		 18531
18532 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18533 + stub_entry->stub_sec->output_offset
18534 + stub_entry->stub_offset;
18535
18536 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18537 veneered_insn_loc &= ~3u;
18538
18539 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18540
18541 abfd = stub_entry->target_section->owner;
8d9d9490 18542 loc = stub_entry->source_value;
48229727
JB		 18543
18544 /* We attempt to avoid this condition by setting stubs_always_after_branch
18545 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18546 This check is just to be on the safe side... */
18547 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18548 {
871b3ab2 18549 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 18550 "allocated in unsafe location"), abfd);
48229727
JB		 18551 return FALSE;
18552 }
18553
18554 switch (stub_entry->stub_type)
18555 {
18556 case arm_stub_a8_veneer_b:
18557 case arm_stub_a8_veneer_b_cond:
18558 branch_insn = 0xf0009000;
18559 goto jump24;
18560
18561 case arm_stub_a8_veneer_blx:
18562 branch_insn = 0xf000e800;
18563 goto jump24;
18564
18565 case arm_stub_a8_veneer_bl:
18566 {
18567 unsigned int i1, j1, i2, j2, s;
18568
18569 branch_insn = 0xf000d000;
18570
18571 jump24:
18572 if (branch_offset < -16777216 || branch_offset > 16777214)
18573 {
18574 /* There's not much we can do apart from complain if this
18575 happens. */
871b3ab2 18576 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 18577 "of range (input file too large)"), abfd);
48229727
JB		 18578 return FALSE;
18579 }
18580
18581 /* i1 = not(j1 eor s), so:
18582 not i1 = j1 eor s
18583 j1 = (not i1) eor s. */
18584
18585 branch_insn |= (branch_offset >> 1) & 0x7ff;
18586 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18587 i2 = (branch_offset >> 22) & 1;
18588 i1 = (branch_offset >> 23) & 1;
18589 s = (branch_offset >> 24) & 1;
18590 j1 = (!i1) ^ s;
18591 j2 = (!i2) ^ s;
18592 branch_insn |= j2 << 11;
18593 branch_insn |= j1 << 13;
18594 branch_insn |= s << 26;
18595 }
18596 break;
18597
18598 default:
18599 BFD_FAIL ();
18600 return FALSE;
18601 }
18602
8d9d9490
TP		 18603 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18604 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 18605
18606 return TRUE;
18607}
18608
a504d23a
LA		 18609/* Beginning of stm32l4xx work-around. */
18610
18611/* Functions encoding instructions necessary for the emission of the
18612 fix-stm32l4xx-629360.
18613 Encoding is extracted from the
18614 ARM (C) Architecture Reference Manual
18615 ARMv7-A and ARMv7-R edition
18616 ARM DDI 0406C.b (ID072512). */
18617
18618static inline bfd_vma
82188b29 18619create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 18620{
18621 /* A8.8.18 B (A8-334)
18622 B target_address (Encoding T4). */
18623 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18624 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18625 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18626
a504d23a
LA		 18627 int s = ((branch_offset & 0x1000000) >> 24);
18628 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18629 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18630
18631 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18632 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18633
18634 bfd_vma patched_inst = 0xf0009000
18635 | s << 26 /* S. */
18636 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18637 | j1 << 13 /* J1. */
18638 | j2 << 11 /* J2. */
18639 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18640
18641 return patched_inst;
18642}
18643
18644static inline bfd_vma
18645create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18646{
18647 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18648 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18649 bfd_vma patched_inst = 0xe8900000
18650 | (/*W=*/wback << 21)
18651 | (base_reg << 16)
18652 | (reg_mask & 0x0000ffff);
18653
18654 return patched_inst;
18655}
18656
18657static inline bfd_vma
18658create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18659{
18660 /* A8.8.60 LDMDB/LDMEA (A8-402)
18661 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18662 bfd_vma patched_inst = 0xe9100000
18663 | (/*W=*/wback << 21)
18664 | (base_reg << 16)
18665 | (reg_mask & 0x0000ffff);
18666
18667 return patched_inst;
18668}
18669
18670static inline bfd_vma
18671create_instruction_mov (int target_reg, int source_reg)
18672{
18673 /* A8.8.103 MOV (register) (A8-486)
18674 MOV Rd, Rm (Encoding T1). */
18675 bfd_vma patched_inst = 0x4600
18676 | (target_reg & 0x7)
18677 | ((target_reg & 0x8) >> 3) << 7
18678 | (source_reg << 3);
18679
18680 return patched_inst;
18681}
18682
18683static inline bfd_vma
18684create_instruction_sub (int target_reg, int source_reg, int value)
18685{
18686 /* A8.8.221 SUB (immediate) (A8-708)
18687 SUB Rd, Rn, #value (Encoding T3). */
18688 bfd_vma patched_inst = 0xf1a00000
18689 | (target_reg << 8)
18690 | (source_reg << 16)
18691 | (/*S=*/0 << 20)
18692 | ((value & 0x800) >> 11) << 26
18693 | ((value & 0x700) >> 8) << 12
18694 | (value & 0x0ff);
18695
18696 return patched_inst;
18697}
18698
18699static inline bfd_vma
9239bbd3 18700create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 18701 int first_reg)
18702{
18703 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18704 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18705 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 18706 | (/*W=*/wback << 21)
18707 | (base_reg << 16)
9239bbd3
CM		 18708 | (num_words & 0x000000ff)
18709 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 18710 | (first_reg & 0x00000001) << 22;
18711
18712 return patched_inst;
18713}
18714
18715static inline bfd_vma
9239bbd3
CM		 18716create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18717 int first_reg)
a504d23a
LA		 18718{
18719 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18720 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18721 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 18722 | (base_reg << 16)
9239bbd3
CM		 18723 | (num_words & 0x000000ff)
18724 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 18725 | (first_reg & 0x00000001) << 22;
18726
18727 return patched_inst;
18728}
18729
18730static inline bfd_vma
18731create_instruction_udf_w (int value)
18732{
18733 /* A8.8.247 UDF (A8-758)
18734 Undefined (Encoding T2). */
18735 bfd_vma patched_inst = 0xf7f0a000
18736 | (value & 0x00000fff)
18737 | (value & 0x000f0000) << 16;
18738
18739 return patched_inst;
18740}
18741
18742static inline bfd_vma
18743create_instruction_udf (int value)
18744{
18745 /* A8.8.247 UDF (A8-758)
18746 Undefined (Encoding T1). */
18747 bfd_vma patched_inst = 0xde00
18748 | (value & 0xff);
18749
18750 return patched_inst;
18751}
18752
18753/* Functions writing an instruction in memory, returning the next
18754 memory position to write to. */
18755
18756static inline bfd_byte *
18757push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18758 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18759{
18760 put_thumb2_insn (htab, output_bfd, insn, pt);
18761 return pt + 4;
18762}
18763
18764static inline bfd_byte *
18765push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
18766 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18767{
18768 put_thumb_insn (htab, output_bfd, insn, pt);
18769 return pt + 2;
18770}
18771
18772/* Function filling up a region in memory with T1 and T2 UDFs taking
18773 care of alignment. */
18774
18775static bfd_byte *
18776stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 18777 bfd * output_bfd,
18778 const bfd_byte * const base_stub_contents,
18779 bfd_byte * const from_stub_contents,
18780 const bfd_byte * const end_stub_contents)
a504d23a
LA		 18781{
18782 bfd_byte *current_stub_contents = from_stub_contents;
18783
18784 /* Fill the remaining of the stub with deterministic contents : UDF
18785 instructions.
18786 Check if realignment is needed on modulo 4 frontier using T1, to
18787 further use T2. */
18788 if ((current_stub_contents < end_stub_contents)
18789 && !((current_stub_contents - base_stub_contents) % 2)
18790 && ((current_stub_contents - base_stub_contents) % 4))
18791 current_stub_contents =
18792 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18793 create_instruction_udf (0));
18794
18795 for (; current_stub_contents < end_stub_contents;)
18796 current_stub_contents =
18797 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18798 create_instruction_udf_w (0));
18799
18800 return current_stub_contents;
18801}
18802
18803/* Functions writing the stream of instructions equivalent to the
18804 derived sequence for ldmia, ldmdb, vldm respectively. */
18805
18806static void
18807stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
18808 bfd * output_bfd,
18809 const insn32 initial_insn,
18810 const bfd_byte *const initial_insn_addr,
18811 bfd_byte *const base_stub_contents)
18812{
18813 int wback = (initial_insn & 0x00200000) >> 21;
18814 int ri, rn = (initial_insn & 0x000F0000) >> 16;
18815 int insn_all_registers = initial_insn & 0x0000ffff;
18816 int insn_low_registers, insn_high_registers;
18817 int usable_register_mask;
b25e998d 18818 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18819 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18820 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
18821 bfd_byte *current_stub_contents = base_stub_contents;
18822
18823 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
18824
18825 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18826 smaller than 8 registers load sequences that do not cause the
18827 hardware issue. */
18828 if (nb_registers <= 8)
18829 {
18830 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18831 current_stub_contents =
18832 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18833 initial_insn);
18834
18835 /* B initial_insn_addr+4. */
18836 if (!restore_pc)
18837 current_stub_contents =
18838 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18839 create_instruction_branch_absolute
82188b29 18840 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18841
18842 /* Fill the remaining of the stub with deterministic contents. */
18843 current_stub_contents =
18844 stm32l4xx_fill_stub_udf (htab, output_bfd,
18845 base_stub_contents, current_stub_contents,
18846 base_stub_contents +
18847 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18848
18849 return;
18850 }
18851
18852 /* - reg_list[13] == 0. */
18853 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
18854
18855 /* - reg_list[14] & reg_list[15] != 1. */
18856 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18857
18858 /* - if (wback==1) reg_list[rn] == 0. */
18859 BFD_ASSERT (!wback || !restore_rn);
18860
18861 /* - nb_registers > 8. */
b25e998d 18862 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 18863
18864 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18865
18866 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
18867 - One with the 7 lowest registers (register mask 0x007F)
18868 This LDM will finally contain between 2 and 7 registers
18869 - One with the 7 highest registers (register mask 0xDF80)
18870 This ldm will finally contain between 2 and 7 registers. */
18871 insn_low_registers = insn_all_registers & 0x007F;
18872 insn_high_registers = insn_all_registers & 0xDF80;
18873
18874 /* A spare register may be needed during this veneer to temporarily
18875 handle the base register. This register will be restored with the
18876 last LDM operation.
18877 The usable register may be any general purpose register (that
18878 excludes PC, SP, LR : register mask is 0x1FFF). */
18879 usable_register_mask = 0x1FFF;
18880
18881 /* Generate the stub function. */
18882 if (wback)
18883 {
18884 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
18885 current_stub_contents =
18886 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18887 create_instruction_ldmia
18888 (rn, /*wback=*/1, insn_low_registers));
18889
18890 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
18891 current_stub_contents =
18892 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18893 create_instruction_ldmia
18894 (rn, /*wback=*/1, insn_high_registers));
18895 if (!restore_pc)
18896 {
18897 /* B initial_insn_addr+4. */
18898 current_stub_contents =
18899 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18900 create_instruction_branch_absolute
82188b29 18901 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18902 }
18903 }
18904 else /* if (!wback). */
18905 {
18906 ri = rn;
18907
18908 /* If Rn is not part of the high-register-list, move it there. */
18909 if (!(insn_high_registers & (1 << rn)))
18910 {
18911 /* Choose a Ri in the high-register-list that will be restored. */
18912 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18913
18914 /* MOV Ri, Rn. */
18915 current_stub_contents =
18916 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18917 create_instruction_mov (ri, rn));
18918 }
18919
18920 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18921 current_stub_contents =
18922 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18923 create_instruction_ldmia
18924 (ri, /*wback=*/1, insn_low_registers));
18925
18926 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18927 current_stub_contents =
18928 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18929 create_instruction_ldmia
18930 (ri, /*wback=*/0, insn_high_registers));
18931
18932 if (!restore_pc)
18933 {
18934 /* B initial_insn_addr+4. */
18935 current_stub_contents =
18936 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18937 create_instruction_branch_absolute
82188b29 18938 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18939 }
18940 }
18941
18942 /* Fill the remaining of the stub with deterministic contents. */
18943 current_stub_contents =
18944 stm32l4xx_fill_stub_udf (htab, output_bfd,
18945 base_stub_contents, current_stub_contents,
18946 base_stub_contents +
18947 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18948}
18949
18950static void
18951stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
18952 bfd * output_bfd,
18953 const insn32 initial_insn,
18954 const bfd_byte *const initial_insn_addr,
18955 bfd_byte *const base_stub_contents)
18956{
18957 int wback = (initial_insn & 0x00200000) >> 21;
18958 int ri, rn = (initial_insn & 0x000f0000) >> 16;
18959 int insn_all_registers = initial_insn & 0x0000ffff;
18960 int insn_low_registers, insn_high_registers;
18961 int usable_register_mask;
18962 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18963 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 18964 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18965 bfd_byte *current_stub_contents = base_stub_contents;
18966
18967 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
18968
18969 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18970 smaller than 8 registers load sequences that do not cause the
18971 hardware issue. */
18972 if (nb_registers <= 8)
18973 {
18974 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18975 current_stub_contents =
18976 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18977 initial_insn);
18978
18979 /* B initial_insn_addr+4. */
18980 current_stub_contents =
18981 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18982 create_instruction_branch_absolute
82188b29 18983 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18984
18985 /* Fill the remaining of the stub with deterministic contents. */
18986 current_stub_contents =
18987 stm32l4xx_fill_stub_udf (htab, output_bfd,
18988 base_stub_contents, current_stub_contents,
18989 base_stub_contents +
18990 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18991
18992 return;
18993 }
18994
18995 /* - reg_list[13] == 0. */
18996 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
18997
18998 /* - reg_list[14] & reg_list[15] != 1. */
18999 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19000
19001 /* - if (wback==1) reg_list[rn] == 0. */
19002 BFD_ASSERT (!wback || !restore_rn);
19003
19004 /* - nb_registers > 8. */
b25e998d 19005 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19006
19007 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19008
19009 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19010 - One with the 7 lowest registers (register mask 0x007F)
19011 This LDM will finally contain between 2 and 7 registers
19012 - One with the 7 highest registers (register mask 0xDF80)
19013 This ldm will finally contain between 2 and 7 registers. */
19014 insn_low_registers = insn_all_registers & 0x007F;
19015 insn_high_registers = insn_all_registers & 0xDF80;
19016
19017 /* A spare register may be needed during this veneer to temporarily
19018 handle the base register. This register will be restored with
19019 the last LDM operation.
19020 The usable register may be any general purpose register (that excludes
19021 PC, SP, LR : register mask is 0x1FFF). */
19022 usable_register_mask = 0x1FFF;
19023
19024 /* Generate the stub function. */
19025 if (!wback && !restore_pc && !restore_rn)
19026 {
19027 /* Choose a Ri in the low-register-list that will be restored. */
19028 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19029
19030 /* MOV Ri, Rn. */
19031 current_stub_contents =
19032 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19033 create_instruction_mov (ri, rn));
19034
19035 /* LDMDB Ri!, {R-high-register-list}. */
19036 current_stub_contents =
19037 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19038 create_instruction_ldmdb
19039 (ri, /*wback=*/1, insn_high_registers));
19040
19041 /* LDMDB Ri, {R-low-register-list}. */
19042 current_stub_contents =
19043 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19044 create_instruction_ldmdb
19045 (ri, /*wback=*/0, insn_low_registers));
19046
19047 /* B initial_insn_addr+4. */
19048 current_stub_contents =
19049 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19050 create_instruction_branch_absolute
82188b29 19051 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19052 }
19053 else if (wback && !restore_pc && !restore_rn)
19054 {
19055 /* LDMDB Rn!, {R-high-register-list}. */
19056 current_stub_contents =
19057 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19058 create_instruction_ldmdb
19059 (rn, /*wback=*/1, insn_high_registers));
19060
19061 /* LDMDB Rn!, {R-low-register-list}. */
19062 current_stub_contents =
19063 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19064 create_instruction_ldmdb
19065 (rn, /*wback=*/1, insn_low_registers));
19066
19067 /* B initial_insn_addr+4. */
19068 current_stub_contents =
19069 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19070 create_instruction_branch_absolute
82188b29 19071 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19072 }
19073 else if (!wback && restore_pc && !restore_rn)
19074 {
19075 /* Choose a Ri in the high-register-list that will be restored. */
19076 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19077
19078 /* SUB Ri, Rn, #(4*nb_registers). */
19079 current_stub_contents =
19080 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19081 create_instruction_sub (ri, rn, (4 * nb_registers)));
19082
19083 /* LDMIA Ri!, {R-low-register-list}. */
19084 current_stub_contents =
19085 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19086 create_instruction_ldmia
19087 (ri, /*wback=*/1, insn_low_registers));
19088
19089 /* LDMIA Ri, {R-high-register-list}. */
19090 current_stub_contents =
19091 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19092 create_instruction_ldmia
19093 (ri, /*wback=*/0, insn_high_registers));
19094 }
19095 else if (wback && restore_pc && !restore_rn)
19096 {
19097 /* Choose a Ri in the high-register-list that will be restored. */
19098 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19099
19100 /* SUB Rn, Rn, #(4*nb_registers) */
19101 current_stub_contents =
19102 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19103 create_instruction_sub (rn, rn, (4 * nb_registers)));
19104
19105 /* MOV Ri, Rn. */
19106 current_stub_contents =
19107 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19108 create_instruction_mov (ri, rn));
19109
19110 /* LDMIA Ri!, {R-low-register-list}. */
19111 current_stub_contents =
19112 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19113 create_instruction_ldmia
19114 (ri, /*wback=*/1, insn_low_registers));
19115
19116 /* LDMIA Ri, {R-high-register-list}. */
19117 current_stub_contents =
19118 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19119 create_instruction_ldmia
19120 (ri, /*wback=*/0, insn_high_registers));
19121 }
19122 else if (!wback && !restore_pc && restore_rn)
19123 {
19124 ri = rn;
19125 if (!(insn_low_registers & (1 << rn)))
19126 {
19127 /* Choose a Ri in the low-register-list that will be restored. */
19128 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19129
19130 /* MOV Ri, Rn. */
19131 current_stub_contents =
19132 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19133 create_instruction_mov (ri, rn));
19134 }
19135
19136 /* LDMDB Ri!, {R-high-register-list}. */
19137 current_stub_contents =
19138 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19139 create_instruction_ldmdb
19140 (ri, /*wback=*/1, insn_high_registers));
19141
19142 /* LDMDB Ri, {R-low-register-list}. */
19143 current_stub_contents =
19144 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19145 create_instruction_ldmdb
19146 (ri, /*wback=*/0, insn_low_registers));
19147
19148 /* B initial_insn_addr+4. */
19149 current_stub_contents =
19150 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19151 create_instruction_branch_absolute
82188b29 19152 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19153 }
19154 else if (!wback && restore_pc && restore_rn)
19155 {
19156 ri = rn;
19157 if (!(insn_high_registers & (1 << rn)))
19158 {
19159 /* Choose a Ri in the high-register-list that will be restored. */
19160 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19161 }
19162
19163 /* SUB Ri, Rn, #(4*nb_registers). */
19164 current_stub_contents =
19165 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19166 create_instruction_sub (ri, rn, (4 * nb_registers)));
19167
19168 /* LDMIA Ri!, {R-low-register-list}. */
19169 current_stub_contents =
19170 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19171 create_instruction_ldmia
19172 (ri, /*wback=*/1, insn_low_registers));
19173
19174 /* LDMIA Ri, {R-high-register-list}. */
19175 current_stub_contents =
19176 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19177 create_instruction_ldmia
19178 (ri, /*wback=*/0, insn_high_registers));
19179 }
19180 else if (wback && restore_rn)
19181 {
19182 /* The assembler should not have accepted to encode this. */
19183 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19184 "undefined behavior.\n");
19185 }
19186
19187 /* Fill the remaining of the stub with deterministic contents. */
19188 current_stub_contents =
19189 stm32l4xx_fill_stub_udf (htab, output_bfd,
19190 base_stub_contents, current_stub_contents,
19191 base_stub_contents +
19192 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19193
19194}
19195
19196static void
19197stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19198 bfd * output_bfd,
19199 const insn32 initial_insn,
19200 const bfd_byte *const initial_insn_addr,
19201 bfd_byte *const base_stub_contents)
19202{
13c9c485 19203 int num_words = initial_insn & 0xff;
a504d23a
LA		 19204 bfd_byte *current_stub_contents = base_stub_contents;
19205
19206 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19207
19208 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 19209 smaller than 8 words load sequences that do not cause the
a504d23a 19210 hardware issue. */
9239bbd3 19211 if (num_words <= 8)
a504d23a
LA		 19212 {
19213 /* Untouched instruction. */
19214 current_stub_contents =
19215 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19216 initial_insn);
19217
19218 /* B initial_insn_addr+4. */
19219 current_stub_contents =
19220 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19221 create_instruction_branch_absolute
82188b29 19222 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19223 }
19224 else
19225 {
9eaff861 19226 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 19227 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 19228 bfd_boolean is_ia_nobang = /* (IA without !). */
19229 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19230 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
19231 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19232 bfd_boolean is_db_bang = /* (DB with !). */
19233 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 19234 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 19235 /* d = UInt (Vd:D);. */
9239bbd3 19236 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 19237 | (((unsigned int)initial_insn << 9) >> 31);
19238
9239bbd3
CM		 19239 /* Compute the number of 8-words chunks needed to split. */
19240 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 19241 int chunk;
19242
19243 /* The test coverage has been done assuming the following
19244 hypothesis that exactly one of the previous is_ predicates is
19245 true. */
9239bbd3
CM		 19246 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19247 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 19248
9239bbd3 19249 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 19250 cases, then we emit the adjustments:
19251
19252 vldm rx, {...}
19253 -> vldm rx!, {8_words_or_less} for each needed 8_word
19254 -> sub rx, rx, #size (list)
19255
19256 vldm rx!, {...}
19257 -> vldm rx!, {8_words_or_less} for each needed 8_word
19258 This also handles vpop instruction (when rx is sp)
19259
19260 vldmd rx!, {...}
19261 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 19262 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 19263 {
9239bbd3
CM		 19264 bfd_vma new_insn = 0;
19265
a504d23a
LA		 19266 if (is_ia_nobang || is_ia_bang)
19267 {
9239bbd3
CM		 19268 new_insn = create_instruction_vldmia
19269 (base_reg,
19270 is_dp,
19271 /*wback= . */1,
19272 chunks - (chunk + 1) ?
19273 8 : num_words - chunk * 8,
19274 first_reg + chunk * 8);
a504d23a
LA		 19275 }
19276 else if (is_db_bang)
19277 {
9239bbd3
CM		 19278 new_insn = create_instruction_vldmdb
19279 (base_reg,
19280 is_dp,
19281 chunks - (chunk + 1) ?
19282 8 : num_words - chunk * 8,
19283 first_reg + chunk * 8);
a504d23a 19284 }
9239bbd3
CM		 19285
19286 if (new_insn)
19287 current_stub_contents =
19288 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19289 new_insn);
a504d23a
LA		 19290 }
19291
19292 /* Only this case requires the base register compensation
19293 subtract. */
19294 if (is_ia_nobang)
19295 {
19296 current_stub_contents =
19297 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19298 create_instruction_sub
9239bbd3 19299 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 19300 }
19301
19302 /* B initial_insn_addr+4. */
19303 current_stub_contents =
19304 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19305 create_instruction_branch_absolute
82188b29 19306 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19307 }
19308
19309 /* Fill the remaining of the stub with deterministic contents. */
19310 current_stub_contents =
19311 stm32l4xx_fill_stub_udf (htab, output_bfd,
19312 base_stub_contents, current_stub_contents,
19313 base_stub_contents +
19314 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19315}
19316
19317static void
19318stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19319 bfd * output_bfd,
19320 const insn32 wrong_insn,
19321 const bfd_byte *const wrong_insn_addr,
19322 bfd_byte *const stub_contents)
19323{
19324 if (is_thumb2_ldmia (wrong_insn))
19325 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19326 wrong_insn, wrong_insn_addr,
19327 stub_contents);
19328 else if (is_thumb2_ldmdb (wrong_insn))
19329 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19330 wrong_insn, wrong_insn_addr,
19331 stub_contents);
19332 else if (is_thumb2_vldm (wrong_insn))
19333 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19334 wrong_insn, wrong_insn_addr,
19335 stub_contents);
19336}
19337
19338/* End of stm32l4xx work-around. */
19339
19340
e489d0ae
PB		 19341/* Do code byteswapping. Return FALSE afterwards so that the section is
19342 written out as normal. */
19343
19344static bfd_boolean
c7b8f16e 19345elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 19346 struct bfd_link_info *link_info,
19347 asection *sec,
e489d0ae
PB		 19348 bfd_byte *contents)
19349{
48229727 19350 unsigned int mapcount, errcount;
8e3de13a 19351 _arm_elf_section_data *arm_data;
c7b8f16e 19352 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 19353 elf32_arm_section_map *map;
c7b8f16e 19354 elf32_vfp11_erratum_list *errnode;
a504d23a 19355 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 19356 bfd_vma ptr;
19357 bfd_vma end;
c7b8f16e 19358 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 19359 bfd_byte tmp;
48229727 19360 unsigned int i;
57e8b36a 19361
4dfe6ac6
NC		 19362 if (globals == NULL)
19363 return FALSE;
19364
8e3de13a
NC		 19365 /* If this section has not been allocated an _arm_elf_section_data
19366 structure then we cannot record anything. */
19367 arm_data = get_arm_elf_section_data (sec);
19368 if (arm_data == NULL)
19369 return FALSE;
19370
19371 mapcount = arm_data->mapcount;
19372 map = arm_data->map;
c7b8f16e
JB		 19373 errcount = arm_data->erratumcount;
19374
19375 if (errcount != 0)
19376 {
19377 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19378
19379 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 19380 errnode = errnode->next)
19381 {
19382 bfd_vma target = errnode->vma - offset;
19383
19384 switch (errnode->type)
19385 {
19386 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19387 {
19388 bfd_vma branch_to_veneer;
19389 /* Original condition code of instruction, plus bit mask for
19390 ARM B instruction. */
19391 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19392 | 0x0a000000;
c7b8f16e
JB		 19393
19394 /* The instruction is before the label. */
91d6fa6a 19395 target -= 4;
c7b8f16e
JB		 19396
19397 /* Above offset included in -4 below. */
19398 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 19399 - errnode->vma - 4;
c7b8f16e
JB		 19400
19401 if ((signed) branch_to_veneer < -(1 << 25)
19402 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 19403 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19404 "range"), output_bfd);
c7b8f16e 19405
99059e56
RM		 19406 insn |= (branch_to_veneer >> 2) & 0xffffff;
19407 contents[endianflip ^ target] = insn & 0xff;
19408 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19409 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19410 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19411 }
19412 break;
c7b8f16e
JB		 19413
19414 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 19415 {
19416 bfd_vma branch_from_veneer;
19417 unsigned int insn;
c7b8f16e 19418
99059e56
RM		 19419 /* Take size of veneer into account. */
19420 branch_from_veneer = errnode->u.v.branch->vma
19421 - errnode->vma - 12;
c7b8f16e
JB		 19422
19423 if ((signed) branch_from_veneer < -(1 << 25)
19424 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 19425 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19426 "range"), output_bfd);
c7b8f16e 19427
99059e56
RM		 19428 /* Original instruction. */
19429 insn = errnode->u.v.branch->u.b.vfp_insn;
19430 contents[endianflip ^ target] = insn & 0xff;
19431 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19432 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19433 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19434
19435 /* Branch back to insn after original insn. */
19436 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19437 contents[endianflip ^ (target + 4)] = insn & 0xff;
19438 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19439 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19440 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19441 }
19442 break;
c7b8f16e 19443
99059e56
RM		 19444 default:
19445 abort ();
19446 }
19447 }
c7b8f16e 19448 }
e489d0ae 19449
a504d23a
LA		 19450 if (arm_data->stm32l4xx_erratumcount != 0)
19451 {
19452 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19453 stm32l4xx_errnode != 0;
19454 stm32l4xx_errnode = stm32l4xx_errnode->next)
19455 {
19456 bfd_vma target = stm32l4xx_errnode->vma - offset;
19457
19458 switch (stm32l4xx_errnode->type)
19459 {
19460 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19461 {
19462 unsigned int insn;
19463 bfd_vma branch_to_veneer =
19464 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19465
19466 if ((signed) branch_to_veneer < -(1 << 24)
19467 || (signed) branch_to_veneer >= (1 << 24))
19468 {
19469 bfd_vma out_of_range =
19470 ((signed) branch_to_veneer < -(1 << 24)) ?
19471 - branch_to_veneer - (1 << 24) :
19472 ((signed) branch_to_veneer >= (1 << 24)) ?
19473 branch_to_veneer - (1 << 24) : 0;
19474
4eca0228 19475 _bfd_error_handler
2dcf00ce 19476 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 19477 "cannot create STM32L4XX veneer; "
19478 "jump out of range by %" PRId64 " bytes; "
19479 "cannot encode branch instruction"),
a504d23a 19480 output_bfd,
2dcf00ce
AM		 19481 (uint64_t) (stm32l4xx_errnode->vma - 4),
19482 (int64_t) out_of_range);
a504d23a
LA		 19483 continue;
19484 }
19485
19486 insn = create_instruction_branch_absolute
82188b29 19487 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a 19488
a2699ef2
AM		 19489 /* The instruction is before the label. */
19490 target -= 4;
19491
a504d23a
LA		 19492 put_thumb2_insn (globals, output_bfd,
19493 (bfd_vma) insn, contents + target);
19494 }
19495 break;
19496
19497 case STM32L4XX_ERRATUM_VENEER:
19498 {
82188b29
NC		 19499 bfd_byte * veneer;
19500 bfd_byte * veneer_r;
a504d23a
LA		 19501 unsigned int insn;
19502
82188b29
NC		 19503 veneer = contents + target;
19504 veneer_r = veneer
19505 + stm32l4xx_errnode->u.b.veneer->vma
19506 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 19507
19508 if ((signed) (veneer_r - veneer -
19509 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19510 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19511 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19512 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19513 || (signed) (veneer_r - veneer) >= (1 << 24))
19514 {
90b6238f
AM		 19515 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19516 "veneer"), output_bfd);
a504d23a
LA		 19517 continue;
19518 }
19519
19520 /* Original instruction. */
19521 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19522
19523 stm32l4xx_create_replacing_stub
19524 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19525 }
19526 break;
19527
19528 default:
19529 abort ();
19530 }
19531 }
19532 }
19533
2468f9c9
PB		 19534 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19535 {
19536 arm_unwind_table_edit *edit_node
99059e56 19537 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 19538 /* Now, sec->size is the size of the section we will write. The original
99059e56 19539 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 19540 markers) was sec->rawsize. (This isn't the case if we perform no
19541 edits, then rawsize will be zero and we should use size). */
21d799b5 19542 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 19543 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19544 unsigned int in_index, out_index;
19545 bfd_vma add_to_offsets = 0;
19546
7a0fb7be
NC		 19547 if (edited_contents == NULL)
19548 return FALSE;
2468f9c9 19549 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 19550 {
2468f9c9
PB		 19551 if (edit_node)
19552 {
19553 unsigned int edit_index = edit_node->index;
b38cadfb 19554
2468f9c9 19555 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 19556 {
2468f9c9
PB		 19557 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19558 contents + in_index * 8, add_to_offsets);
19559 out_index++;
19560 in_index++;
19561 }
19562 else if (in_index == edit_index
19563 || (in_index * 8 >= input_size
19564 && edit_index == UINT_MAX))
99059e56 19565 {
2468f9c9
PB		 19566 switch (edit_node->type)
19567 {
19568 case DELETE_EXIDX_ENTRY:
19569 in_index++;
19570 add_to_offsets += 8;
19571 break;
b38cadfb 19572
2468f9c9
PB		 19573 case INSERT_EXIDX_CANTUNWIND_AT_END:
19574 {
99059e56 19575 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 19576 bfd_vma text_offset = text_sec->output_section->vma
19577 + text_sec->output_offset
19578 + text_sec->size;
19579 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 19580 unsigned long prel31_offset;
2468f9c9
PB		 19581
19582 /* Note: this is meant to be equivalent to an
19583 R_ARM_PREL31 relocation. These synthetic
19584 EXIDX_CANTUNWIND markers are not relocated by the
19585 usual BFD method. */
19586 prel31_offset = (text_offset - exidx_offset)
19587 & 0x7ffffffful;
491d01d3
YU		 19588 if (bfd_link_relocatable (link_info))
19589 {
19590 /* Here relocation for new EXIDX_CANTUNWIND is
19591 created, so there is no need to
19592 adjust offset by hand. */
19593 prel31_offset = text_sec->output_offset
19594 + text_sec->size;
491d01d3 19595 }
2468f9c9
PB		 19596
19597 /* First address we can't unwind. */
19598 bfd_put_32 (output_bfd, prel31_offset,
19599 &edited_contents[out_index * 8]);
19600
19601 /* Code for EXIDX_CANTUNWIND. */
19602 bfd_put_32 (output_bfd, 0x1,
19603 &edited_contents[out_index * 8 + 4]);
19604
19605 out_index++;
19606 add_to_offsets -= 8;
19607 }
19608 break;
19609 }
b38cadfb 19610
2468f9c9
PB		 19611 edit_node = edit_node->next;
19612 }
19613 }
19614 else
19615 {
19616 /* No more edits, copy remaining entries verbatim. */
19617 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19618 contents + in_index * 8, add_to_offsets);
19619 out_index++;
19620 in_index++;
19621 }
19622 }
19623
19624 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19625 bfd_set_section_contents (output_bfd, sec->output_section,
19626 edited_contents,
19627 (file_ptr) sec->output_offset, sec->size);
19628
19629 return TRUE;
19630 }
19631
48229727
JB		 19632 /* Fix code to point to Cortex-A8 erratum stubs. */
19633 if (globals->fix_cortex_a8)
19634 {
19635 struct a8_branch_to_stub_data data;
19636
19637 data.writing_section = sec;
19638 data.contents = contents;
19639
a504d23a
LA		 19640 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19641 & data);
48229727
JB		 19642 }
19643
e489d0ae
PB		 19644 if (mapcount == 0)
19645 return FALSE;
19646
c7b8f16e 19647 if (globals->byteswap_code)
e489d0ae 19648 {
c7b8f16e 19649 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 19650
c7b8f16e
JB		 19651 ptr = map[0].vma;
19652 for (i = 0; i < mapcount; i++)
99059e56
RM		 19653 {
19654 if (i == mapcount - 1)
c7b8f16e 19655 end = sec->size;
99059e56
RM		 19656 else
19657 end = map[i + 1].vma;
e489d0ae 19658
99059e56 19659 switch (map[i].type)
e489d0ae 19660 {
c7b8f16e
JB		 19661 case 'a':
19662 /* Byte swap code words. */
19663 while (ptr + 3 < end)
99059e56
RM		 19664 {
19665 tmp = contents[ptr];
19666 contents[ptr] = contents[ptr + 3];
19667 contents[ptr + 3] = tmp;
19668 tmp = contents[ptr + 1];
19669 contents[ptr + 1] = contents[ptr + 2];
19670 contents[ptr + 2] = tmp;
19671 ptr += 4;
19672 }
c7b8f16e 19673 break;
e489d0ae 19674
c7b8f16e
JB		 19675 case 't':
19676 /* Byte swap code halfwords. */
19677 while (ptr + 1 < end)
99059e56
RM		 19678 {
19679 tmp = contents[ptr];
19680 contents[ptr] = contents[ptr + 1];
19681 contents[ptr + 1] = tmp;
19682 ptr += 2;
19683 }
c7b8f16e
JB		 19684 break;
19685
19686 case 'd':
19687 /* Leave data alone. */
19688 break;
19689 }
99059e56
RM		 19690 ptr = end;
19691 }
e489d0ae 19692 }
8e3de13a 19693
93204d3a 19694 free (map);
47b2e99c 19695 arm_data->mapcount = -1;
c7b8f16e 19696 arm_data->mapsize = 0;
8e3de13a 19697 arm_data->map = NULL;
8e3de13a 19698
e489d0ae
PB		 19699 return FALSE;
19700}
19701
0beaef2b
PB		 19702/* Mangle thumb function symbols as we read them in. */
19703
8384fb8f 19704static bfd_boolean
0beaef2b
PB		 19705elf32_arm_swap_symbol_in (bfd * abfd,
19706 const void *psrc,
19707 const void *pshn,
19708 Elf_Internal_Sym *dst)
19709{
8384fb8f
AM		 19710 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19711 return FALSE;
39d911fc 19712 dst->st_target_internal = 0;
0beaef2b
PB		 19713
19714 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 19715 the address. */
63e1a0fc
PB		 19716 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19717 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 19718 {
63e1a0fc
PB		 19719 if (dst->st_value & 1)
19720 {
19721 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 19722 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19723 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 19724 }
19725 else
39d911fc 19726 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 19727 }
19728 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19729 {
19730 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 19731 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 19732 }
35fc36a8 19733 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 19734 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 19735 else
39d911fc 19736 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 19737
8384fb8f 19738 return TRUE;
0beaef2b
PB		 19739}
19740
19741
19742/* Mangle thumb function symbols as we write them out. */
19743
19744static void
19745elf32_arm_swap_symbol_out (bfd *abfd,
19746 const Elf_Internal_Sym *src,
19747 void *cdst,
19748 void *shndx)
19749{
19750 Elf_Internal_Sym newsym;
19751
19752 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19753 of the address set, as per the new EABI. We do this unconditionally
19754 because objcopy does not set the elf header flags until after
19755 it writes out the symbol table. */
39d911fc 19756 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 19757 {
19758 newsym = *src;
34e77a92
RS		 19759 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19760 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 19761 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 19762 {
19763 /* Do this only for defined symbols. At link type, the static
19764 linker will simulate the work of dynamic linker of resolving
19765 symbols and will carry over the thumbness of found symbols to
19766 the output symbol table. It's not clear how it happens, but
19767 the thumbness of undefined symbols can well be different at
19768 runtime, and writing '1' for them will be confusing for users
19769 and possibly for dynamic linker itself.
19770 */
19771 newsym.st_value |= 1;
19772 }
906e58ca 19773
0beaef2b
PB		 19774 src = &newsym;
19775 }
19776 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
19777}
19778
b294bdf8
MM		 19779/* Add the PT_ARM_EXIDX program header. */
19780
19781static bfd_boolean
906e58ca 19782elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 19783 struct bfd_link_info *info ATTRIBUTE_UNUSED)
19784{
19785 struct elf_segment_map *m;
19786 asection *sec;
19787
19788 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19789 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19790 {
19791 /* If there is already a PT_ARM_EXIDX header, then we do not
19792 want to add another one. This situation arises when running
19793 "strip"; the input binary already has the header. */
12bd6957 19794 m = elf_seg_map (abfd);
b294bdf8
MM		 19795 while (m && m->p_type != PT_ARM_EXIDX)
19796 m = m->next;
19797 if (!m)
19798 {
21d799b5 19799 m = (struct elf_segment_map *)
99059e56 19800 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 19801 if (m == NULL)
19802 return FALSE;
19803 m->p_type = PT_ARM_EXIDX;
19804 m->count = 1;
19805 m->sections[0] = sec;
19806
12bd6957
AM		 19807 m->next = elf_seg_map (abfd);
19808 elf_seg_map (abfd) = m;
b294bdf8
MM		 19809 }
19810 }
19811
19812 return TRUE;
19813}
19814
19815/* We may add a PT_ARM_EXIDX program header. */
19816
19817static int
a6b96beb
AM		 19818elf32_arm_additional_program_headers (bfd *abfd,
19819 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 19820{
19821 asection *sec;
19822
19823 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19824 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19825 return 1;
19826 else
19827 return 0;
19828}
19829
34e77a92
RS		 19830/* Hook called by the linker routine which adds symbols from an object
19831 file. */
19832
19833static bfd_boolean
19834elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
19835 Elf_Internal_Sym *sym, const char **namep,
19836 flagword *flagsp, asection **secp, bfd_vma *valp)
19837{
c792917c
NC		 19838 if (elf32_arm_hash_table (info) == NULL)
19839 return FALSE;
19840
90c14f0c 19841 if (elf32_arm_hash_table (info)->root.target_os == is_vxworks
34e77a92
RS		 19842 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
19843 flagsp, secp, valp))
19844 return FALSE;
19845
19846 return TRUE;
19847}
19848
0beaef2b 19849/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 19850const struct elf_size_info elf32_arm_size_info =
19851{
0beaef2b
PB		 19852 sizeof (Elf32_External_Ehdr),
19853 sizeof (Elf32_External_Phdr),
19854 sizeof (Elf32_External_Shdr),
19855 sizeof (Elf32_External_Rel),
19856 sizeof (Elf32_External_Rela),
19857 sizeof (Elf32_External_Sym),
19858 sizeof (Elf32_External_Dyn),
19859 sizeof (Elf_External_Note),
19860 4,
19861 1,
19862 32, 2,
19863 ELFCLASS32, EV_CURRENT,
19864 bfd_elf32_write_out_phdrs,
19865 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 19866 bfd_elf32_checksum_contents,
0beaef2b
PB		 19867 bfd_elf32_write_relocs,
19868 elf32_arm_swap_symbol_in,
19869 elf32_arm_swap_symbol_out,
19870 bfd_elf32_slurp_reloc_table,
19871 bfd_elf32_slurp_symbol_table,
19872 bfd_elf32_swap_dyn_in,
19873 bfd_elf32_swap_dyn_out,
19874 bfd_elf32_swap_reloc_in,
19875 bfd_elf32_swap_reloc_out,
19876 bfd_elf32_swap_reloca_in,
19877 bfd_elf32_swap_reloca_out
19878};
19879
685e70ae
VK		 19880static bfd_vma
19881read_code32 (const bfd *abfd, const bfd_byte *addr)
19882{
19883 /* V7 BE8 code is always little endian. */
19884 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19885 return bfd_getl32 (addr);
19886
19887 return bfd_get_32 (abfd, addr);
19888}
19889
19890static bfd_vma
19891read_code16 (const bfd *abfd, const bfd_byte *addr)
19892{
19893 /* V7 BE8 code is always little endian. */
19894 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19895 return bfd_getl16 (addr);
19896
19897 return bfd_get_16 (abfd, addr);
19898}
19899
6a631e86
YG		 19900/* Return size of plt0 entry starting at ADDR
19901 or (bfd_vma) -1 if size can not be determined. */
19902
19903static bfd_vma
19904elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
19905{
19906 bfd_vma first_word;
19907 bfd_vma plt0_size;
19908
685e70ae 19909 first_word = read_code32 (abfd, addr);
6a631e86
YG		 19910
19911 if (first_word == elf32_arm_plt0_entry[0])
19912 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
19913 else if (first_word == elf32_thumb2_plt0_entry[0])
19914 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
19915 else
19916 /* We don't yet handle this PLT format. */
19917 return (bfd_vma) -1;
19918
19919 return plt0_size;
19920}
19921
19922/* Return size of plt entry starting at offset OFFSET
19923 of plt section located at address START
19924 or (bfd_vma) -1 if size can not be determined. */
19925
19926static bfd_vma
19927elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
19928{
19929 bfd_vma first_insn;
19930 bfd_vma plt_size = 0;
19931 const bfd_byte *addr = start + offset;
19932
19933 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 19934 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 19935 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
19936
19937 /* Respect Thumb stub if necessary. */
685e70ae 19938 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 19939 {
19940 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
19941 }
19942
19943 /* Strip immediate from first add. */
685e70ae 19944 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 19945
19946#ifdef FOUR_WORD_PLT
19947 if (first_insn == elf32_arm_plt_entry[0])
19948 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
19949#else
19950 if (first_insn == elf32_arm_plt_entry_long[0])
19951 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
19952 else if (first_insn == elf32_arm_plt_entry_short[0])
19953 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
19954#endif
19955 else
19956 /* We don't yet handle this PLT format. */
19957 return (bfd_vma) -1;
19958
19959 return plt_size;
19960}
19961
19962/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19963
19964static long
19965elf32_arm_get_synthetic_symtab (bfd *abfd,
19966 long symcount ATTRIBUTE_UNUSED,
19967 asymbol **syms ATTRIBUTE_UNUSED,
19968 long dynsymcount,
19969 asymbol **dynsyms,
19970 asymbol **ret)
19971{
19972 asection *relplt;
19973 asymbol *s;
19974 arelent *p;
19975 long count, i, n;
19976 size_t size;
19977 Elf_Internal_Shdr *hdr;
19978 char *names;
19979 asection *plt;
19980 bfd_vma offset;
19981 bfd_byte *data;
19982
19983 *ret = NULL;
19984
19985 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
19986 return 0;
19987
19988 if (dynsymcount <= 0)
19989 return 0;
19990
19991 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
19992 if (relplt == NULL)
19993 return 0;
19994
19995 hdr = &elf_section_data (relplt)->this_hdr;
19996 if (hdr->sh_link != elf_dynsymtab (abfd)
19997 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
19998 return 0;
19999
20000 plt = bfd_get_section_by_name (abfd, ".plt");
20001 if (plt == NULL)
20002 return 0;
20003
20004 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
20005 return -1;
20006
20007 data = plt->contents;
20008 if (data == NULL)
20009 {
20010 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
20011 return -1;
20012 bfd_cache_section_contents((asection *) plt, data);
20013 }
20014
20015 count = relplt->size / hdr->sh_entsize;
20016 size = count * sizeof (asymbol);
20017 p = relplt->relocation;
20018 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20019 {
20020 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
20021 if (p->addend != 0)
20022 size += sizeof ("+0x") - 1 + 8;
20023 }
20024
20025 s = *ret = (asymbol *) bfd_malloc (size);
20026 if (s == NULL)
20027 return -1;
20028
20029 offset = elf32_arm_plt0_size (abfd, data);
20030 if (offset == (bfd_vma) -1)
20031 return -1;
20032
20033 names = (char *) (s + count);
20034 p = relplt->relocation;
20035 n = 0;
20036 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20037 {
20038 size_t len;
20039
20040 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
20041 if (plt_size == (bfd_vma) -1)
20042 break;
20043
20044 *s = **p->sym_ptr_ptr;
20045 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20046 we are defining a symbol, ensure one of them is set. */
20047 if ((s->flags & BSF_LOCAL) == 0)
20048 s->flags |= BSF_GLOBAL;
20049 s->flags |= BSF_SYNTHETIC;
20050 s->section = plt;
20051 s->value = offset;
20052 s->name = names;
20053 s->udata.p = NULL;
20054 len = strlen ((*p->sym_ptr_ptr)->name);
20055 memcpy (names, (*p->sym_ptr_ptr)->name, len);
20056 names += len;
20057 if (p->addend != 0)
20058 {
20059 char buf[30], *a;
20060
20061 memcpy (names, "+0x", sizeof ("+0x") - 1);
20062 names += sizeof ("+0x") - 1;
20063 bfd_sprintf_vma (abfd, buf, p->addend);
20064 for (a = buf; *a == '0'; ++a)
20065 ;
20066 len = strlen (a);
20067 memcpy (names, a, len);
20068 names += len;
20069 }
20070 memcpy (names, "@plt", sizeof ("@plt"));
20071 names += sizeof ("@plt");
20072 ++s, ++n;
20073 offset += plt_size;
20074 }
20075
20076 return n;
20077}
20078
ac4c9b04 20079static bfd_boolean
8c803a2d 20080elf32_arm_section_flags (const Elf_Internal_Shdr *hdr)
ac4c9b04 20081{
f0728ee3 20082 if (hdr->sh_flags & SHF_ARM_PURECODE)
8c803a2d 20083 hdr->bfd_section->flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 20084 return TRUE;
20085}
20086
20087static flagword
20088elf32_arm_lookup_section_flags (char *flag_name)
20089{
f0728ee3
AV		 20090 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
20091 return SHF_ARM_PURECODE;
ac4c9b04
MG		 20092
20093 return SEC_NO_FLAGS;
20094}
20095
491d01d3
YU		 20096static unsigned int
20097elf32_arm_count_additional_relocs (asection *sec)
20098{
20099 struct _arm_elf_section_data *arm_data;
20100 arm_data = get_arm_elf_section_data (sec);
5025eb7c 20101
6342be70 20102 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 20103}
20104
5522f910 20105/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 20106 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 20107 FALSE otherwise. ISECTION is the best guess matching section from the
20108 input bfd IBFD, but it might be NULL. */
20109
20110static bfd_boolean
20111elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20112 bfd *obfd ATTRIBUTE_UNUSED,
20113 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20114 Elf_Internal_Shdr *osection)
20115{
20116 switch (osection->sh_type)
20117 {
20118 case SHT_ARM_EXIDX:
20119 {
20120 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20121 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20122 unsigned i = 0;
20123
20124 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20125 osection->sh_info = 0;
20126
20127 /* The sh_link field must be set to the text section associated with
20128 this index section. Unfortunately the ARM EHABI does not specify
20129 exactly how to determine this association. Our caller does try
20130 to match up OSECTION with its corresponding input section however
20131 so that is a good first guess. */
20132 if (isection != NULL
20133 && osection->bfd_section != NULL
20134 && isection->bfd_section != NULL
20135 && isection->bfd_section->output_section != NULL
20136 && isection->bfd_section->output_section == osection->bfd_section
20137 && iheaders != NULL
20138 && isection->sh_link > 0
20139 && isection->sh_link < elf_numsections (ibfd)
20140 && iheaders[isection->sh_link]->bfd_section != NULL
20141 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20142 )
20143 {
20144 for (i = elf_numsections (obfd); i-- > 0;)
20145 if (oheaders[i]->bfd_section
20146 == iheaders[isection->sh_link]->bfd_section->output_section)
20147 break;
20148 }
9eaff861 20149
5522f910
NC		 20150 if (i == 0)
20151 {
20152 /* Failing that we have to find a matching section ourselves. If
20153 we had the output section name available we could compare that
20154 with input section names. Unfortunately we don't. So instead
20155 we use a simple heuristic and look for the nearest executable
20156 section before this one. */
20157 for (i = elf_numsections (obfd); i-- > 0;)
20158 if (oheaders[i] == osection)
20159 break;
20160 if (i == 0)
20161 break;
20162
20163 while (i-- > 0)
20164 if (oheaders[i]->sh_type == SHT_PROGBITS
20165 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20166 == (SHF_ALLOC | SHF_EXECINSTR))
20167 break;
20168 }
20169
20170 if (i)
20171 {
20172 osection->sh_link = i;
20173 /* If the text section was part of a group
20174 then the index section should be too. */
20175 if (oheaders[i]->sh_flags & SHF_GROUP)
20176 osection->sh_flags |= SHF_GROUP;
20177 return TRUE;
20178 }
20179 }
20180 break;
20181
20182 case SHT_ARM_PREEMPTMAP:
20183 osection->sh_flags = SHF_ALLOC;
20184 break;
20185
20186 case SHT_ARM_ATTRIBUTES:
20187 case SHT_ARM_DEBUGOVERLAY:
20188 case SHT_ARM_OVERLAYSECTION:
20189 default:
20190 break;
20191 }
20192
20193 return FALSE;
20194}
20195
d691934d
NC		 20196/* Returns TRUE if NAME is an ARM mapping symbol.
20197 Traditionally the symbols $a, $d and $t have been used.
20198 The ARM ELF standard also defines $x (for A64 code). It also allows a
20199 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20200 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20201 not support them here. $t.x indicates the start of ThumbEE instructions. */
20202
20203static bfd_boolean
20204is_arm_mapping_symbol (const char * name)
20205{
20206 return name != NULL /* Paranoia. */
20207 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20208 the mapping symbols could have acquired a prefix.
20209 We do not support this here, since such symbols no
20210 longer conform to the ARM ELF ABI. */
20211 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20212 && (name[2] == 0 || name[2] == '.');
20213 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20214 any characters that follow the period are legal characters for the body
20215 of a symbol's name. For now we just assume that this is the case. */
20216}
20217
fca2a38f
NC		 20218/* Make sure that mapping symbols in object files are not removed via the
20219 "strip --strip-unneeded" tool. These symbols are needed in order to
20220 correctly generate interworking veneers, and for byte swapping code
20221 regions. Once an object file has been linked, it is safe to remove the
20222 symbols as they will no longer be needed. */
20223
20224static void
20225elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20226{
20227 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 20228 && sym->section != bfd_abs_section_ptr
d691934d 20229 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 20230 sym->flags |= BSF_KEEP;
20231}
20232
5522f910
NC		 20233#undef elf_backend_copy_special_section_fields
20234#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20235
252b5132 20236#define ELF_ARCH bfd_arch_arm
ae95ffa6 20237#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 20238#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 20239#ifdef __QNXTARGET__
20240#define ELF_MAXPAGESIZE 0x1000
20241#else
7572ca89 20242#define ELF_MAXPAGESIZE 0x10000
d0facd1b 20243#endif
b1342370 20244#define ELF_MINPAGESIZE 0x1000
24718e3b 20245#define ELF_COMMONPAGESIZE 0x1000
252b5132 20246
07d6d2b8 20247#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 20248
99e4ae17
AJ		 20249#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20250#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 20251#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20252#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 20253#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 20254#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 20255#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8 20256#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 20257#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 20258#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 20259#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 20260#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 20261
07d6d2b8 20262#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
e7679060 20263#define elf_backend_maybe_function_sym elf32_arm_maybe_function_sym
07d6d2b8 20264#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 20265#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 20266#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 20267#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 20268#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 20269#define elf_backend_write_section elf32_arm_write_section
252b5132 20270#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 20271#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 20272#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20273#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20274#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 20275#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 20276#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ed7e9d0b 20277#define elf_backend_init_file_header elf32_arm_init_file_header
99e4ae17 20278#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 20279#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 20280#define elf_backend_fake_sections elf32_arm_fake_sections
20281#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20282#define elf_backend_final_write_processing elf32_arm_final_write_processing
20283#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 20284#define elf_backend_size_info elf32_arm_size_info
b294bdf8 20285#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 20286#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20287#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 20288#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 20289#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 20290#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 20291#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 20292#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 20293
20294#define elf_backend_can_refcount 1
20295#define elf_backend_can_gc_sections 1
20296#define elf_backend_plt_readonly 1
20297#define elf_backend_want_got_plt 1
20298#define elf_backend_want_plt_sym 0
5474d94f 20299#define elf_backend_want_dynrelro 1
906e58ca
NC		 20300#define elf_backend_may_use_rel_p 1
20301#define elf_backend_may_use_rela_p 0
4e7fd91e 20302#define elf_backend_default_use_rela_p 0
64f52338 20303#define elf_backend_dtrel_excludes_plt 1
252b5132 20304
04f7c78d 20305#define elf_backend_got_header_size 12
b68a20d6 20306#define elf_backend_extern_protected_data 1
04f7c78d 20307
07d6d2b8 20308#undef elf_backend_obj_attrs_vendor
906e58ca 20309#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 20310#undef elf_backend_obj_attrs_section
906e58ca 20311#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 20312#undef elf_backend_obj_attrs_arg_type
906e58ca 20313#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 20314#undef elf_backend_obj_attrs_section_type
104d59d1 20315#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 20316#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 20317#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 20318
07d6d2b8 20319#undef elf_backend_section_flags
ac4c9b04 20320#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 20321#undef elf_backend_lookup_section_flags_hook
20322#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 20323
a2f63b2e
MR		 20324#define elf_backend_linux_prpsinfo32_ugid16 TRUE
20325
252b5132 20326#include "elf32-target.h"
7f266840 20327
b38cadfb
NC		 20328/* Native Client targets. */
20329
20330#undef TARGET_LITTLE_SYM
6d00b590 20331#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 20332#undef TARGET_LITTLE_NAME
20333#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20334#undef TARGET_BIG_SYM
6d00b590 20335#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 20336#undef TARGET_BIG_NAME
20337#define TARGET_BIG_NAME "elf32-bigarm-nacl"
20338
20339/* Like elf32_arm_link_hash_table_create -- but overrides
20340 appropriately for NaCl. */
20341
20342static struct bfd_link_hash_table *
20343elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20344{
20345 struct bfd_link_hash_table *ret;
20346
20347 ret = elf32_arm_link_hash_table_create (abfd);
20348 if (ret)
20349 {
20350 struct elf32_arm_link_hash_table *htab
20351 = (struct elf32_arm_link_hash_table *) ret;
20352
b38cadfb
NC		 20353 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20354 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20355 }
20356 return ret;
20357}
20358
20359/* Since NaCl doesn't use the ARM-specific unwind format, we don't
20360 really need to use elf32_arm_modify_segment_map. But we do it
20361 anyway just to reduce gratuitous differences with the stock ARM backend. */
20362
20363static bfd_boolean
20364elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20365{
20366 return (elf32_arm_modify_segment_map (abfd, info)
20367 && nacl_modify_segment_map (abfd, info));
20368}
20369
cc364be6
AM		 20370static bfd_boolean
20371elf32_arm_nacl_final_write_processing (bfd *abfd)
887badb3 20372{
cc364be6
AM		 20373 arm_final_write_processing (abfd);
20374 return nacl_final_write_processing (abfd);
887badb3
RM		 20375}
20376
6a631e86
YG		 20377static bfd_vma
20378elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20379 const arelent *rel ATTRIBUTE_UNUSED)
20380{
20381 return plt->vma
20382 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20383 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20384}
887badb3 20385
b38cadfb 20386#undef elf32_bed
6a631e86 20387#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 20388#undef bfd_elf32_bfd_link_hash_table_create
20389#define bfd_elf32_bfd_link_hash_table_create \
20390 elf32_arm_nacl_link_hash_table_create
20391#undef elf_backend_plt_alignment
6a631e86 20392#define elf_backend_plt_alignment 4
b38cadfb
NC		 20393#undef elf_backend_modify_segment_map
20394#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
6d6c25c8
AM		 20395#undef elf_backend_modify_headers
20396#define elf_backend_modify_headers nacl_modify_headers
887badb3
RM		 20397#undef elf_backend_final_write_processing
20398#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 20399#undef bfd_elf32_get_synthetic_symtab
20400#undef elf_backend_plt_sym_val
20401#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 20402#undef elf_backend_copy_special_section_fields
b38cadfb 20403
887badb3
RM		 20404#undef ELF_MINPAGESIZE
20405#undef ELF_COMMONPAGESIZE
20406
90c14f0c
L		 20407#undef ELF_TARGET_OS
20408#define ELF_TARGET_OS is_nacl
b38cadfb
NC		 20409
20410#include "elf32-target.h"
20411
20412/* Reset to defaults. */
20413#undef elf_backend_plt_alignment
20414#undef elf_backend_modify_segment_map
20415#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
6d6c25c8 20416#undef elf_backend_modify_headers
887badb3
RM		 20417#undef elf_backend_final_write_processing
20418#define elf_backend_final_write_processing elf32_arm_final_write_processing
20419#undef ELF_MINPAGESIZE
20420#define ELF_MINPAGESIZE 0x1000
20421#undef ELF_COMMONPAGESIZE
20422#define ELF_COMMONPAGESIZE 0x1000
20423
b38cadfb 20424
617a5ada
CL		 20425/* FDPIC Targets. */
20426
20427#undef TARGET_LITTLE_SYM
20428#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20429#undef TARGET_LITTLE_NAME
20430#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20431#undef TARGET_BIG_SYM
20432#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20433#undef TARGET_BIG_NAME
20434#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20435#undef elf_match_priority
20436#define elf_match_priority 128
18a20338
CL		 20437#undef ELF_OSABI
20438#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 20439
20440/* Like elf32_arm_link_hash_table_create -- but overrides
20441 appropriately for FDPIC. */
20442
20443static struct bfd_link_hash_table *
20444elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20445{
20446 struct bfd_link_hash_table *ret;
20447
20448 ret = elf32_arm_link_hash_table_create (abfd);
20449 if (ret)
20450 {
20451 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20452
20453 htab->fdpic_p = 1;
20454 }
20455 return ret;
20456}
20457
e8b09b87
CL		 20458/* We need dynamic symbols for every section, since segments can
20459 relocate independently. */
20460static bfd_boolean
20461elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20462 struct bfd_link_info *info
20463 ATTRIBUTE_UNUSED,
20464 asection *p ATTRIBUTE_UNUSED)
20465{
20466 switch (elf_section_data (p)->this_hdr.sh_type)
20467 {
20468 case SHT_PROGBITS:
20469 case SHT_NOBITS:
20470 /* If sh_type is yet undecided, assume it could be
20471 SHT_PROGBITS/SHT_NOBITS. */
20472 case SHT_NULL:
20473 return FALSE;
20474
20475 /* There shouldn't be section relative relocations
20476 against any other section. */
20477 default:
20478 return TRUE;
20479 }
20480}
20481
617a5ada
CL		 20482#undef elf32_bed
20483#define elf32_bed elf32_arm_fdpic_bed
20484
20485#undef bfd_elf32_bfd_link_hash_table_create
4b24dd1a 20486#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
617a5ada 20487
e8b09b87
CL		 20488#undef elf_backend_omit_section_dynsym
20489#define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20490
90c14f0c
L		 20491#undef ELF_TARGET_OS
20492
617a5ada 20493#include "elf32-target.h"
e8b09b87 20494
617a5ada 20495#undef elf_match_priority
18a20338 20496#undef ELF_OSABI
e8b09b87 20497#undef elf_backend_omit_section_dynsym
617a5ada 20498
906e58ca 20499/* VxWorks Targets. */
4e7fd91e 20500
07d6d2b8
AM		 20501#undef TARGET_LITTLE_SYM
20502#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20503#undef TARGET_LITTLE_NAME
20504#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20505#undef TARGET_BIG_SYM
20506#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20507#undef TARGET_BIG_NAME
20508#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 20509
20510/* Like elf32_arm_link_hash_table_create -- but overrides
20511 appropriately for VxWorks. */
906e58ca 20512
4e7fd91e
PB		 20513static struct bfd_link_hash_table *
20514elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20515{
20516 struct bfd_link_hash_table *ret;
20517
20518 ret = elf32_arm_link_hash_table_create (abfd);
20519 if (ret)
20520 {
20521 struct elf32_arm_link_hash_table *htab
00a97672 20522 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e
PB		 20523 htab->use_rel = 0;
20524 }
20525 return ret;
906e58ca 20526}
4e7fd91e 20527
cc364be6
AM		 20528static bfd_boolean
20529elf32_arm_vxworks_final_write_processing (bfd *abfd)
00a97672 20530{
cc364be6
AM		 20531 arm_final_write_processing (abfd);
20532 return elf_vxworks_final_write_processing (abfd);
00a97672
RS		 20533}
20534
906e58ca 20535#undef elf32_bed
4e7fd91e
PB		 20536#define elf32_bed elf32_arm_vxworks_bed
20537
906e58ca
NC		 20538#undef bfd_elf32_bfd_link_hash_table_create
20539#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 20540#undef elf_backend_final_write_processing
20541#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20542#undef elf_backend_emit_relocs
9eaff861 20543#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 20544
906e58ca 20545#undef elf_backend_may_use_rel_p
00a97672 20546#define elf_backend_may_use_rel_p 0
906e58ca 20547#undef elf_backend_may_use_rela_p
00a97672 20548#define elf_backend_may_use_rela_p 1
906e58ca 20549#undef elf_backend_default_use_rela_p
00a97672 20550#define elf_backend_default_use_rela_p 1
906e58ca 20551#undef elf_backend_want_plt_sym
00a97672 20552#define elf_backend_want_plt_sym 1
906e58ca 20553#undef ELF_MAXPAGESIZE
00a97672 20554#define ELF_MAXPAGESIZE 0x1000
90c14f0c
L		 20555#undef ELF_TARGET_OS
20556#define ELF_TARGET_OS is_vxworks
4e7fd91e
PB		 20557
20558#include "elf32-target.h"
20559
20560
21d799b5
NC		 20561/* Merge backend specific data from an object file to the output
20562 object file when linking. */
20563
20564static bfd_boolean
50e03d47 20565elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 20566{
50e03d47 20567 bfd *obfd = info->output_bfd;
21d799b5
NC		 20568 flagword out_flags;
20569 flagword in_flags;
20570 bfd_boolean flags_compatible = TRUE;
20571 asection *sec;
20572
cc643b88 20573 /* Check if we have the same endianness. */
50e03d47 20574 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 20575 return FALSE;
20576
20577 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20578 return TRUE;
20579
50e03d47 20580 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 20581 return FALSE;
20582
20583 /* The input BFD must have had its flags initialised. */
20584 /* The following seems bogus to me -- The flags are initialized in
20585 the assembler but I don't think an elf_flags_init field is
20586 written into the object. */
20587 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20588
20589 in_flags = elf_elfheader (ibfd)->e_flags;
20590 out_flags = elf_elfheader (obfd)->e_flags;
20591
20592 /* In theory there is no reason why we couldn't handle this. However
20593 in practice it isn't even close to working and there is no real
20594 reason to want it. */
20595 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20596 && !(ibfd->flags & DYNAMIC)
20597 && (in_flags & EF_ARM_BE8))
20598 {
871b3ab2 20599 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 20600 ibfd);
20601 return FALSE;
20602 }
20603
20604 if (!elf_flags_init (obfd))
20605 {
20606 /* If the input is the default architecture and had the default
20607 flags then do not bother setting the flags for the output
20608 architecture, instead allow future merges to do this. If no
20609 future merges ever set these flags then they will retain their
99059e56
RM		 20610 uninitialised values, which surprise surprise, correspond
20611 to the default values. */
21d799b5
NC		 20612 if (bfd_get_arch_info (ibfd)->the_default
20613 && elf_elfheader (ibfd)->e_flags == 0)
20614 return TRUE;
20615
20616 elf_flags_init (obfd) = TRUE;
20617 elf_elfheader (obfd)->e_flags = in_flags;
20618
20619 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20620 && bfd_get_arch_info (obfd)->the_default)
20621 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20622
20623 return TRUE;
20624 }
20625
20626 /* Determine what should happen if the input ARM architecture
20627 does not match the output ARM architecture. */
20628 if (! bfd_arm_merge_machines (ibfd, obfd))
20629 return FALSE;
20630
20631 /* Identical flags must be compatible. */
20632 if (in_flags == out_flags)
20633 return TRUE;
20634
20635 /* Check to see if the input BFD actually contains any sections. If
20636 not, its flags may not have been initialised either, but it
20637 cannot actually cause any incompatiblity. Do not short-circuit
20638 dynamic objects; their section list may be emptied by
20639 elf_link_add_object_symbols.
20640
20641 Also check to see if there are no code sections in the input.
20642 In this case there is no need to check for code specific flags.
20643 XXX - do we need to worry about floating-point format compatability
20644 in data sections ? */
20645 if (!(ibfd->flags & DYNAMIC))
20646 {
20647 bfd_boolean null_input_bfd = TRUE;
20648 bfd_boolean only_data_sections = TRUE;
20649
20650 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20651 {
20652 /* Ignore synthetic glue sections. */
20653 if (strcmp (sec->name, ".glue_7")
20654 && strcmp (sec->name, ".glue_7t"))
20655 {
fd361982 20656 if ((bfd_section_flags (sec)
21d799b5
NC		 20657 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20658 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 20659 only_data_sections = FALSE;
21d799b5
NC		 20660
20661 null_input_bfd = FALSE;
20662 break;
20663 }
20664 }
20665
20666 if (null_input_bfd || only_data_sections)
20667 return TRUE;
20668 }
20669
20670 /* Complain about various flag mismatches. */
20671 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20672 EF_ARM_EABI_VERSION (out_flags)))
20673 {
20674 _bfd_error_handler
90b6238f 20675 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 20676 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20677 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 20678 return FALSE;
20679 }
20680
20681 /* Not sure what needs to be checked for EABI versions >= 1. */
20682 /* VxWorks libraries do not use these flags. */
20683 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20684 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20685 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20686 {
20687 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20688 {
20689 _bfd_error_handler
871b3ab2 20690 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 20691 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20692 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 20693 flags_compatible = FALSE;
20694 }
20695
20696 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20697 {
20698 if (in_flags & EF_ARM_APCS_FLOAT)
20699 _bfd_error_handler
871b3ab2 20700 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 20701 ibfd, obfd);
20702 else
20703 _bfd_error_handler
871b3ab2 20704 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 20705 ibfd, obfd);
20706
20707 flags_compatible = FALSE;
20708 }
20709
20710 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20711 {
20712 if (in_flags & EF_ARM_VFP_FLOAT)
20713 _bfd_error_handler
90b6238f
AM		 20714 (_("error: %pB uses %s instructions, whereas %pB does not"),
20715 ibfd, "VFP", obfd);
21d799b5
NC		 20716 else
20717 _bfd_error_handler
90b6238f
AM		 20718 (_("error: %pB uses %s instructions, whereas %pB does not"),
20719 ibfd, "FPA", obfd);
21d799b5
NC		 20720
20721 flags_compatible = FALSE;
20722 }
20723
20724 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20725 {
20726 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20727 _bfd_error_handler
90b6238f
AM		 20728 (_("error: %pB uses %s instructions, whereas %pB does not"),
20729 ibfd, "Maverick", obfd);
21d799b5
NC		 20730 else
20731 _bfd_error_handler
90b6238f
AM		 20732 (_("error: %pB does not use %s instructions, whereas %pB does"),
20733 ibfd, "Maverick", obfd);
21d799b5
NC		 20734
20735 flags_compatible = FALSE;
20736 }
20737
20738#ifdef EF_ARM_SOFT_FLOAT
20739 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20740 {
20741 /* We can allow interworking between code that is VFP format
20742 layout, and uses either soft float or integer regs for
20743 passing floating point arguments and results. We already
20744 know that the APCS_FLOAT flags match; similarly for VFP
20745 flags. */
20746 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20747 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20748 {
20749 if (in_flags & EF_ARM_SOFT_FLOAT)
20750 _bfd_error_handler
871b3ab2 20751 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 20752 ibfd, obfd);
20753 else
20754 _bfd_error_handler
871b3ab2 20755 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 20756 ibfd, obfd);
20757
20758 flags_compatible = FALSE;
20759 }
20760 }
20761#endif
20762
20763 /* Interworking mismatch is only a warning. */
20764 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
20765 {
20766 if (in_flags & EF_ARM_INTERWORK)
20767 {
20768 _bfd_error_handler
90b6238f 20769 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 20770 ibfd, obfd);
20771 }
20772 else
20773 {
20774 _bfd_error_handler
90b6238f 20775 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 20776 ibfd, obfd);
20777 }
20778 }
20779 }
20780
20781 return flags_compatible;
20782}
20783
20784
906e58ca 20785/* Symbian OS Targets. */
7f266840 20786
07d6d2b8
AM		 20787#undef TARGET_LITTLE_SYM
20788#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
20789#undef TARGET_LITTLE_NAME
20790#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
20791#undef TARGET_BIG_SYM
20792#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
20793#undef TARGET_BIG_NAME
20794#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 20795
20796/* Like elf32_arm_link_hash_table_create -- but overrides
20797 appropriately for Symbian OS. */
906e58ca 20798
7f266840
DJ		 20799static struct bfd_link_hash_table *
20800elf32_arm_symbian_link_hash_table_create (bfd *abfd)
20801{
20802 struct bfd_link_hash_table *ret;
20803
20804 ret = elf32_arm_link_hash_table_create (abfd);
20805 if (ret)
20806 {
20807 struct elf32_arm_link_hash_table *htab
20808 = (struct elf32_arm_link_hash_table *)ret;
20809 /* There is no PLT header for Symbian OS. */
20810 htab->plt_header_size = 0;
95720a86
DJ		 20811 /* The PLT entries are each one instruction and one word. */
20812 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
33bfe774
JB		 20813 /* Symbian uses armv5t or above, so use_blx is always true. */
20814 htab->use_blx = 1;
67687978 20815 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 20816 }
20817 return ret;
906e58ca 20818}
7f266840 20819
b35d266b 20820static const struct bfd_elf_special_section
551b43fd 20821elf32_arm_symbian_special_sections[] =
7f266840 20822{
5cd3778d
MM		 20823 /* In a BPABI executable, the dynamic linking sections do not go in
20824 the loadable read-only segment. The post-linker may wish to
20825 refer to these sections, but they are not part of the final
20826 program image. */
07d6d2b8
AM		 20827 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
20828 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
20829 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
20830 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
20831 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 20832 /* These sections do not need to be writable as the SymbianOS
20833 postlinker will arrange things so that no dynamic relocation is
20834 required. */
07d6d2b8
AM		 20835 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
20836 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 20837 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 20838 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 20839};
20840
c3c76620 20841static void
906e58ca 20842elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 20843 struct bfd_link_info *link_info)
c3c76620
MM		 20844{
20845 /* BPABI objects are never loaded directly by an OS kernel; they are
20846 processed by a postlinker first, into an OS-specific format. If
20847 the D_PAGED bit is set on the file, BFD will align segments on
20848 page boundaries, so that an OS can directly map the file. With
20849 BPABI objects, that just results in wasted space. In addition,
20850 because we clear the D_PAGED bit, map_sections_to_segments will
20851 recognize that the program headers should not be mapped into any
20852 loadable segment. */
20853 abfd->flags &= ~D_PAGED;
906e58ca 20854 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 20855}
7f266840
DJ		 20856
20857static bfd_boolean
906e58ca 20858elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 20859 struct bfd_link_info *info)
7f266840
DJ		 20860{
20861 struct elf_segment_map *m;
20862 asection *dynsec;
20863
7f266840
DJ		 20864 /* BPABI shared libraries and executables should have a PT_DYNAMIC
20865 segment. However, because the .dynamic section is not marked
20866 with SEC_LOAD, the generic ELF code will not create such a
20867 segment. */
20868 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
20869 if (dynsec)
20870 {
12bd6957 20871 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 20872 if (m->p_type == PT_DYNAMIC)
20873 break;
20874
20875 if (m == NULL)
20876 {
20877 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 20878 m->next = elf_seg_map (abfd);
20879 elf_seg_map (abfd) = m;
8ded5a0f 20880 }
7f266840
DJ		 20881 }
20882
b294bdf8
MM		 20883 /* Also call the generic arm routine. */
20884 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 20885}
20886
95720a86
DJ		 20887/* Return address for Ith PLT stub in section PLT, for relocation REL
20888 or (bfd_vma) -1 if it should not be included. */
20889
20890static bfd_vma
20891elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
20892 const arelent *rel ATTRIBUTE_UNUSED)
20893{
20894 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
20895}
20896
8029a119 20897#undef elf32_bed
7f266840
DJ		 20898#define elf32_bed elf32_arm_symbian_bed
20899
20900/* The dynamic sections are not allocated on SymbianOS; the postlinker
20901 will process them and then discard them. */
906e58ca 20902#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 20903#define ELF_DYNAMIC_SEC_FLAGS \
20904 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
20905
9eaff861 20906#undef elf_backend_emit_relocs
c3c76620 20907
906e58ca
NC		 20908#undef bfd_elf32_bfd_link_hash_table_create
20909#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
20910#undef elf_backend_special_sections
07d6d2b8 20911#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 20912#undef elf_backend_begin_write_processing
20913#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
20914#undef elf_backend_final_write_processing
20915#define elf_backend_final_write_processing elf32_arm_final_write_processing
20916
20917#undef elf_backend_modify_segment_map
7f266840
DJ		 20918#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
20919
20920/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 20921#undef elf_backend_got_header_size
7f266840
DJ		 20922#define elf_backend_got_header_size 0
20923
20924/* Similarly, there is no .got.plt section. */
906e58ca 20925#undef elf_backend_want_got_plt
7f266840
DJ		 20926#define elf_backend_want_got_plt 0
20927
906e58ca 20928#undef elf_backend_plt_sym_val
95720a86
DJ		 20929#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
20930
906e58ca 20931#undef elf_backend_may_use_rel_p
00a97672 20932#define elf_backend_may_use_rel_p 1
906e58ca 20933#undef elf_backend_may_use_rela_p
00a97672 20934#define elf_backend_may_use_rela_p 0
906e58ca 20935#undef elf_backend_default_use_rela_p
00a97672 20936#define elf_backend_default_use_rela_p 0
906e58ca 20937#undef elf_backend_want_plt_sym
00a97672 20938#define elf_backend_want_plt_sym 0
64f52338
AM		 20939#undef elf_backend_dtrel_excludes_plt
20940#define elf_backend_dtrel_excludes_plt 0
906e58ca 20941#undef ELF_MAXPAGESIZE
00a97672 20942#define ELF_MAXPAGESIZE 0x8000
90c14f0c
L		 20943#undef ELF_TARGET_OS
20944#define ELF_TARGET_OS is_symbian
4e7fd91e 20945
7f266840 20946#include "elf32-target.h"
GDB Binutils - Deliverables
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