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[ARM] FDPIC: Add stack segment
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
219d1afa 2 Copyright (C) 1998-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
f3185997 59#define elf_info_to_howto NULL
07d6d2b8 60#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
07d6d2b8 240 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
99059e56
RM		 334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
07d6d2b8 340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
99059e56
RM		 348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
07d6d2b8 354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
99059e56
RM		 362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
07d6d2b8 368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
99059e56
RM		 378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
07d6d2b8 384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
99059e56
RM		 392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
07d6d2b8 398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
99059e56
RM		 406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
07d6d2b8 412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
99059e56
RM		 420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
07d6d2b8 426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
99059e56
RM		 434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
07d6d2b8 440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
99059e56 446 TRUE, /* pc_relative */
07d6d2b8 447 0, /* bitpos */
99059e56
RM		 448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
99059e56 460 FALSE, /* pc_relative */
07d6d2b8 461 0, /* bitpos */
99059e56
RM		 462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
99059e56 474 TRUE, /* pc_relative */
07d6d2b8 475 0, /* bitpos */
99059e56
RM		 476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
07d6d2b8 909 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 917 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
07d6d2b8 937 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 945 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
07d6d2b8 951 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 959 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
07d6d2b8 965 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 973 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
07d6d2b8 979 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 987 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
07d6d2b8 993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1001 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
07d6d2b8 1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1015 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
07d6d2b8 1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1029 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
07d6d2b8 1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1043 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
07d6d2b8 1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1057 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
07d6d2b8 1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1071 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
07d6d2b8 1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1085 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
07d6d2b8 1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1099 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
07d6d2b8 1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1113 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
07d6d2b8 1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1127 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
07d6d2b8 1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1141 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
07d6d2b8 1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1155 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
07d6d2b8 1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1169 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
07d6d2b8 1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1183 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
07d6d2b8 1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1197 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
07d6d2b8 1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1211 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
07d6d2b8 1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1225 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
07d6d2b8 1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1239 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
07d6d2b8 1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1253 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
07d6d2b8 1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1267 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
07d6d2b8 1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1486
1487 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
99059e56 1494 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
99059e56 1509 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1510 NULL, /* special_function */
99059e56 1511 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
99059e56
RM		 1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
07d6d2b8 1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
99059e56
RM		 1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
07d6d2b8 1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
99059e56
RM		 1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
07d6d2b8 1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
99059e56
RM		 1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
07d6d2b8 1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
99059e56 1608 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
07d6d2b8 1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92 1748/* 160 onwards: */
5c5a4843 1749static reloc_howto_type elf32_arm_howto_table_2[8] =
34e77a92
RS		 1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
99059e56
RM		 1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
188fd7ae
CL		 1763 FALSE), /* pcrel_offset */
1764 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1765 0, /* rightshift */
1766 2, /* size (0 = byte, 1 = short, 2 = long) */
1767 32, /* bitsize */
1768 FALSE, /* pc_relative */
1769 0, /* bitpos */
1770 complain_overflow_bitfield,/* complain_on_overflow */
1771 bfd_elf_generic_reloc, /* special_function */
1772 "R_ARM_GOTFUNCDESC", /* name */
1773 FALSE, /* partial_inplace */
1774 0, /* src_mask */
1775 0xffffffff, /* dst_mask */
1776 FALSE), /* pcrel_offset */
1777 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1778 0, /* rightshift */
1779 2, /* size (0 = byte, 1 = short, 2 = long) */
1780 32, /* bitsize */
1781 FALSE, /* pc_relative */
1782 0, /* bitpos */
1783 complain_overflow_bitfield,/* complain_on_overflow */
1784 bfd_elf_generic_reloc, /* special_function */
1785 "R_ARM_GOTOFFFUNCDESC",/* name */
1786 FALSE, /* partial_inplace */
1787 0, /* src_mask */
1788 0xffffffff, /* dst_mask */
1789 FALSE), /* pcrel_offset */
1790 HOWTO (R_ARM_FUNCDESC, /* type */
1791 0, /* rightshift */
1792 2, /* size (0 = byte, 1 = short, 2 = long) */
1793 32, /* bitsize */
1794 FALSE, /* pc_relative */
1795 0, /* bitpos */
1796 complain_overflow_bitfield,/* complain_on_overflow */
1797 bfd_elf_generic_reloc, /* special_function */
1798 "R_ARM_FUNCDESC", /* name */
1799 FALSE, /* partial_inplace */
1800 0, /* src_mask */
1801 0xffffffff, /* dst_mask */
1802 FALSE), /* pcrel_offset */
1803 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1804 0, /* rightshift */
1805 2, /* size (0 = byte, 1 = short, 2 = long) */
1806 64, /* bitsize */
1807 FALSE, /* pc_relative */
1808 0, /* bitpos */
1809 complain_overflow_bitfield,/* complain_on_overflow */
1810 bfd_elf_generic_reloc, /* special_function */
1811 "R_ARM_FUNCDESC_VALUE",/* name */
1812 FALSE, /* partial_inplace */
1813 0, /* src_mask */
1814 0xffffffff, /* dst_mask */
1815 FALSE), /* pcrel_offset */
5c5a4843
CL		 1816 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1817 0, /* rightshift */
1818 2, /* size (0 = byte, 1 = short, 2 = long) */
1819 32, /* bitsize */
1820 FALSE, /* pc_relative */
1821 0, /* bitpos */
1822 complain_overflow_bitfield,/* complain_on_overflow */
1823 bfd_elf_generic_reloc, /* special_function */
1824 "R_ARM_TLS_GD32_FDPIC",/* name */
1825 FALSE, /* partial_inplace */
1826 0, /* src_mask */
1827 0xffffffff, /* dst_mask */
1828 FALSE), /* pcrel_offset */
1829 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1830 0, /* rightshift */
1831 2, /* size (0 = byte, 1 = short, 2 = long) */
1832 32, /* bitsize */
1833 FALSE, /* pc_relative */
1834 0, /* bitpos */
1835 complain_overflow_bitfield,/* complain_on_overflow */
1836 bfd_elf_generic_reloc, /* special_function */
1837 "R_ARM_TLS_LDM32_FDPIC",/* name */
1838 FALSE, /* partial_inplace */
1839 0, /* src_mask */
1840 0xffffffff, /* dst_mask */
1841 FALSE), /* pcrel_offset */
1842 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1843 0, /* rightshift */
1844 2, /* size (0 = byte, 1 = short, 2 = long) */
1845 32, /* bitsize */
1846 FALSE, /* pc_relative */
1847 0, /* bitpos */
1848 complain_overflow_bitfield,/* complain_on_overflow */
1849 bfd_elf_generic_reloc, /* special_function */
1850 "R_ARM_TLS_IE32_FDPIC",/* name */
1851 FALSE, /* partial_inplace */
1852 0, /* src_mask */
1853 0xffffffff, /* dst_mask */
1854 FALSE), /* pcrel_offset */
34e77a92 1855};
c19d1205 1856
34e77a92
RS		 1857/* 249-255 extended, currently unused, relocations: */
1858static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1859{
1860 HOWTO (R_ARM_RREL32, /* type */
1861 0, /* rightshift */
1862 0, /* size (0 = byte, 1 = short, 2 = long) */
1863 0, /* bitsize */
1864 FALSE, /* pc_relative */
1865 0, /* bitpos */
1866 complain_overflow_dont,/* complain_on_overflow */
1867 bfd_elf_generic_reloc, /* special_function */
1868 "R_ARM_RREL32", /* name */
1869 FALSE, /* partial_inplace */
1870 0, /* src_mask */
1871 0, /* dst_mask */
1872 FALSE), /* pcrel_offset */
1873
1874 HOWTO (R_ARM_RABS32, /* type */
1875 0, /* rightshift */
1876 0, /* size (0 = byte, 1 = short, 2 = long) */
1877 0, /* bitsize */
1878 FALSE, /* pc_relative */
1879 0, /* bitpos */
1880 complain_overflow_dont,/* complain_on_overflow */
1881 bfd_elf_generic_reloc, /* special_function */
1882 "R_ARM_RABS32", /* name */
1883 FALSE, /* partial_inplace */
1884 0, /* src_mask */
1885 0, /* dst_mask */
1886 FALSE), /* pcrel_offset */
1887
1888 HOWTO (R_ARM_RPC24, /* type */
1889 0, /* rightshift */
1890 0, /* size (0 = byte, 1 = short, 2 = long) */
1891 0, /* bitsize */
1892 FALSE, /* pc_relative */
1893 0, /* bitpos */
1894 complain_overflow_dont,/* complain_on_overflow */
1895 bfd_elf_generic_reloc, /* special_function */
1896 "R_ARM_RPC24", /* name */
1897 FALSE, /* partial_inplace */
1898 0, /* src_mask */
1899 0, /* dst_mask */
1900 FALSE), /* pcrel_offset */
1901
1902 HOWTO (R_ARM_RBASE, /* type */
1903 0, /* rightshift */
1904 0, /* size (0 = byte, 1 = short, 2 = long) */
1905 0, /* bitsize */
1906 FALSE, /* pc_relative */
1907 0, /* bitpos */
1908 complain_overflow_dont,/* complain_on_overflow */
1909 bfd_elf_generic_reloc, /* special_function */
1910 "R_ARM_RBASE", /* name */
1911 FALSE, /* partial_inplace */
1912 0, /* src_mask */
1913 0, /* dst_mask */
1914 FALSE) /* pcrel_offset */
1915};
1916
1917static reloc_howto_type *
1918elf32_arm_howto_from_type (unsigned int r_type)
1919{
906e58ca 1920 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1921 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1922
188fd7ae
CL		 1923 if (r_type >= R_ARM_IRELATIVE
1924 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1925 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1926
c19d1205 1927 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1928 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1929 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1930
c19d1205 1931 return NULL;
7f266840
DJ		 1932}
1933
f3185997
NC		 1934static bfd_boolean
1935elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1936 Elf_Internal_Rela * elf_reloc)
1937{
1938 unsigned int r_type;
1939
1940 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1941 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1942 {
1943 /* xgettext:c-format */
1944 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1945 abfd, r_type);
1946 bfd_set_error (bfd_error_bad_value);
1947 return FALSE;
1948 }
1949 return TRUE;
7f266840
DJ		 1950}
1951
1952struct elf32_arm_reloc_map
1953 {
1954 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1955 unsigned char elf_reloc_val;
7f266840
DJ		 1956 };
1957
1958/* All entries in this list must also be present in elf32_arm_howto_table. */
1959static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1960 {
07d6d2b8 1961 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 1962 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1963 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1964 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 1965 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1966 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1967 {BFD_RELOC_32, R_ARM_ABS32},
1968 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1969 {BFD_RELOC_8, R_ARM_ABS8},
1970 {BFD_RELOC_16, R_ARM_ABS16},
1971 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 1972 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1973 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1974 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1975 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1976 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1977 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1978 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 1979 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1980 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1981 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
1982 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
1983 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
1984 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
1985 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1986 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 1987 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1988 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1989 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1990 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 1991 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 1992 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1993 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1994 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 1995 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 1996 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 1997 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 1998 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1999 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
2000 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2001 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2002 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2003 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 2004 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2005 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2006 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2007 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 2008 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2009 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2010 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2011 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
5c5a4843
CL		 2012 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2013 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2014 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
c19d1205
ZW		 2015 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2016 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 2017 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2018 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2019 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2020 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2021 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2022 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2023 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2024 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 2025 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2026 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2027 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2028 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2029 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2030 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2031 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2032 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2033 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2034 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2035 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2036 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2037 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2038 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2039 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2040 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2041 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2042 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2043 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2044 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2045 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2046 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2047 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2048 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2049 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2050 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2051 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2052 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2053 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2054 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2055 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2056 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
2057 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 2058 };
2059
2060static reloc_howto_type *
f1c71a59
ZW		 2061elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2062 bfd_reloc_code_real_type code)
7f266840
DJ		 2063{
2064 unsigned int i;
8029a119 2065
906e58ca 2066 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2067 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2068 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2069
c19d1205 2070 return NULL;
7f266840
DJ		 2071}
2072
157090f7
AM		 2073static reloc_howto_type *
2074elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2075 const char *r_name)
2076{
2077 unsigned int i;
2078
906e58ca 2079 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2080 if (elf32_arm_howto_table_1[i].name != NULL
2081 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2082 return &elf32_arm_howto_table_1[i];
2083
906e58ca 2084 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2085 if (elf32_arm_howto_table_2[i].name != NULL
2086 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2087 return &elf32_arm_howto_table_2[i];
2088
34e77a92
RS		 2089 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2090 if (elf32_arm_howto_table_3[i].name != NULL
2091 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2092 return &elf32_arm_howto_table_3[i];
2093
157090f7
AM		 2094 return NULL;
2095}
2096
906e58ca
NC		 2097/* Support for core dump NOTE sections. */
2098
7f266840 2099static bfd_boolean
f1c71a59 2100elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2101{
2102 int offset;
2103 size_t size;
2104
2105 switch (note->descsz)
2106 {
2107 default:
2108 return FALSE;
2109
8029a119 2110 case 148: /* Linux/ARM 32-bit. */
7f266840 2111 /* pr_cursig */
228e534f 2112 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2113
2114 /* pr_pid */
228e534f 2115 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2116
2117 /* pr_reg */
2118 offset = 72;
2119 size = 72;
2120
2121 break;
2122 }
2123
2124 /* Make a ".reg/999" section. */
2125 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2126 size, note->descpos + offset);
2127}
2128
2129static bfd_boolean
f1c71a59 2130elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2131{
2132 switch (note->descsz)
2133 {
2134 default:
2135 return FALSE;
2136
8029a119 2137 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2138 elf_tdata (abfd)->core->pid
4395ee08 2139 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2140 elf_tdata (abfd)->core->program
7f266840 2141 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2142 elf_tdata (abfd)->core->command
7f266840
DJ		 2143 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2144 }
2145
2146 /* Note that for some reason, a spurious space is tacked
2147 onto the end of the args in some (at least one anyway)
2148 implementations, so strip it off if it exists. */
7f266840 2149 {
228e534f 2150 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2151 int n = strlen (command);
2152
2153 if (0 < n && command[n - 1] == ' ')
2154 command[n - 1] = '\0';
2155 }
2156
2157 return TRUE;
2158}
2159
1f20dca5
UW		 2160static char *
2161elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2162 int note_type, ...)
2163{
2164 switch (note_type)
2165 {
2166 default:
2167 return NULL;
2168
2169 case NT_PRPSINFO:
2170 {
2171 char data[124];
2172 va_list ap;
2173
2174 va_start (ap, note_type);
2175 memset (data, 0, sizeof (data));
2176 strncpy (data + 28, va_arg (ap, const char *), 16);
2177 strncpy (data + 44, va_arg (ap, const char *), 80);
2178 va_end (ap);
2179
2180 return elfcore_write_note (abfd, buf, bufsiz,
2181 "CORE", note_type, data, sizeof (data));
2182 }
2183
2184 case NT_PRSTATUS:
2185 {
2186 char data[148];
2187 va_list ap;
2188 long pid;
2189 int cursig;
2190 const void *greg;
2191
2192 va_start (ap, note_type);
2193 memset (data, 0, sizeof (data));
2194 pid = va_arg (ap, long);
2195 bfd_put_32 (abfd, pid, data + 24);
2196 cursig = va_arg (ap, int);
2197 bfd_put_16 (abfd, cursig, data + 12);
2198 greg = va_arg (ap, const void *);
2199 memcpy (data + 72, greg, 72);
2200 va_end (ap);
2201
2202 return elfcore_write_note (abfd, buf, bufsiz,
2203 "CORE", note_type, data, sizeof (data));
2204 }
2205 }
2206}
2207
07d6d2b8
AM		 2208#define TARGET_LITTLE_SYM arm_elf32_le_vec
2209#define TARGET_LITTLE_NAME "elf32-littlearm"
2210#define TARGET_BIG_SYM arm_elf32_be_vec
2211#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2212
2213#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2214#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2215#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2216
252b5132
RH		 2217typedef unsigned long int insn32;
2218typedef unsigned short int insn16;
2219
3a4a14e9
PB		 2220/* In lieu of proper flags, assume all EABIv4 or later objects are
2221 interworkable. */
57e8b36a 2222#define INTERWORK_FLAG(abfd) \
3a4a14e9 2223 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2224 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2225 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2226
252b5132
RH		 2227/* The linker script knows the section names for placement.
2228 The entry_names are used to do simple name mangling on the stubs.
2229 Given a function name, and its type, the stub can be found. The
9b485d32 2230 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2231#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2232#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2233
2234#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2235#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2236
c7b8f16e
JB		 2237#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2238#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2239
a504d23a
LA		 2240#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2241#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2242
845b51d6
PB		 2243#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2244#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2245
7413f23f
DJ		 2246#define STUB_ENTRY_NAME "__%s_veneer"
2247
4ba2ef8f
TP		 2248#define CMSE_PREFIX "__acle_se_"
2249
252b5132
RH		 2250/* The name of the dynamic interpreter. This is put in the .interp
2251 section. */
2252#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2253
cb10292c
CL		 2254/* FDPIC default stack size. */
2255#define DEFAULT_STACK_SIZE 0x8000
2256
0855e32b 2257static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2258{
2259 0xe08e0000, /* add r0, lr, r0 */
2260 0xe5901004, /* ldr r1, [r0,#4] */
2261 0xe12fff11, /* bx r1 */
2262};
0855e32b
NS		 2263
2264static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2265{
2266 0xe52d2004, /* push {r2} */
2267 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2268 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2269 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2270 0xe081100f, /* 2: add r1, pc */
2271 0xe12fff12, /* bx r2 */
2272 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2273 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2274 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2275};
0855e32b 2276
7801f98f
CL		 2277/* ARM FDPIC PLT entry. */
2278/* The last 5 words contain PLT lazy fragment code and data. */
2279static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2280 {
2281 0xe59fc008, /* ldr r12, .L1 */
2282 0xe08cc009, /* add r12, r12, r9 */
2283 0xe59c9004, /* ldr r9, [r12, #4] */
2284 0xe59cf000, /* ldr pc, [r12] */
2285 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2286 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2287 0xe51fc00c, /* ldr r12, [pc, #-12] */
2288 0xe92d1000, /* push {r12} */
2289 0xe599c004, /* ldr r12, [r9, #4] */
2290 0xe599f000, /* ldr pc, [r9] */
2291 };
2292
5e681ec4
PB		 2293#ifdef FOUR_WORD_PLT
2294
252b5132
RH		 2295/* The first entry in a procedure linkage table looks like
2296 this. It is set up so that any shared library function that is
59f2c4e7 2297 called before the relocation has been set up calls the dynamic
9b485d32 2298 linker first. */
e5a52504 2299static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2300{
2301 0xe52de004, /* str lr, [sp, #-4]! */
2302 0xe59fe010, /* ldr lr, [pc, #16] */
2303 0xe08fe00e, /* add lr, pc, lr */
2304 0xe5bef008, /* ldr pc, [lr, #8]! */
2305};
5e681ec4
PB		 2306
2307/* Subsequent entries in a procedure linkage table look like
2308 this. */
e5a52504 2309static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2310{
2311 0xe28fc600, /* add ip, pc, #NN */
2312 0xe28cca00, /* add ip, ip, #NN */
2313 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2314 0x00000000, /* unused */
2315};
5e681ec4 2316
eed94f8f 2317#else /* not FOUR_WORD_PLT */
5e681ec4 2318
5e681ec4
PB		 2319/* The first entry in a procedure linkage table looks like
2320 this. It is set up so that any shared library function that is
2321 called before the relocation has been set up calls the dynamic
2322 linker first. */
e5a52504 2323static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2324{
07d6d2b8
AM		 2325 0xe52de004, /* str lr, [sp, #-4]! */
2326 0xe59fe004, /* ldr lr, [pc, #4] */
2327 0xe08fe00e, /* add lr, pc, lr */
2328 0xe5bef008, /* ldr pc, [lr, #8]! */
2329 0x00000000, /* &GOT[0] - . */
b38cadfb 2330};
252b5132 2331
1db37fe6
YG		 2332/* By default subsequent entries in a procedure linkage table look like
2333 this. Offsets that don't fit into 28 bits will cause link error. */
2334static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2335{
2336 0xe28fc600, /* add ip, pc, #0xNN00000 */
2337 0xe28cca00, /* add ip, ip, #0xNN000 */
2338 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2339};
5e681ec4 2340
1db37fe6
YG		 2341/* When explicitly asked, we'll use this "long" entry format
2342 which can cope with arbitrary displacements. */
2343static const bfd_vma elf32_arm_plt_entry_long [] =
2344{
07d6d2b8
AM		 2345 0xe28fc200, /* add ip, pc, #0xN0000000 */
2346 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2347 0xe28cca00, /* add ip, ip, #0xNN000 */
2348 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2349};
2350
2351static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2352
eed94f8f
NC		 2353#endif /* not FOUR_WORD_PLT */
2354
2355/* The first entry in a procedure linkage table looks like this.
2356 It is set up so that any shared library function that is called before the
2357 relocation has been set up calls the dynamic linker first. */
2358static const bfd_vma elf32_thumb2_plt0_entry [] =
2359{
2360 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2361 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2362 0xf8dfb500, /* push {lr} */
2363 0x44fee008, /* ldr.w lr, [pc, #8] */
2364 /* add lr, pc */
eed94f8f 2365 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2366 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2367};
2368
2369/* Subsequent entries in a procedure linkage table for thumb only target
2370 look like this. */
2371static const bfd_vma elf32_thumb2_plt_entry [] =
2372{
2373 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2374 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2375 0x0c00f240, /* movw ip, #0xNNNN */
2376 0x0c00f2c0, /* movt ip, #0xNNNN */
2377 0xf8dc44fc, /* add ip, pc */
2378 0xbf00f000 /* ldr.w pc, [ip] */
2379 /* nop */
eed94f8f 2380};
252b5132 2381
00a97672
RS		 2382/* The format of the first entry in the procedure linkage table
2383 for a VxWorks executable. */
2384static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2385{
07d6d2b8
AM		 2386 0xe52dc008, /* str ip,[sp,#-8]! */
2387 0xe59fc000, /* ldr ip,[pc] */
2388 0xe59cf008, /* ldr pc,[ip,#8] */
2389 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2390};
00a97672
RS		 2391
2392/* The format of subsequent entries in a VxWorks executable. */
2393static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2394{
07d6d2b8
AM		 2395 0xe59fc000, /* ldr ip,[pc] */
2396 0xe59cf000, /* ldr pc,[ip] */
2397 0x00000000, /* .long @got */
2398 0xe59fc000, /* ldr ip,[pc] */
2399 0xea000000, /* b _PLT */
2400 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2401};
00a97672
RS		 2402
2403/* The format of entries in a VxWorks shared library. */
2404static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2405{
07d6d2b8
AM		 2406 0xe59fc000, /* ldr ip,[pc] */
2407 0xe79cf009, /* ldr pc,[ip,r9] */
2408 0x00000000, /* .long @got */
2409 0xe59fc000, /* ldr ip,[pc] */
2410 0xe599f008, /* ldr pc,[r9,#8] */
2411 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2412};
00a97672 2413
b7693d02
DJ		 2414/* An initial stub used if the PLT entry is referenced from Thumb code. */
2415#define PLT_THUMB_STUB_SIZE 4
2416static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2417{
2418 0x4778, /* bx pc */
2419 0x46c0 /* nop */
2420};
b7693d02 2421
e5a52504
MM		 2422/* The entries in a PLT when using a DLL-based target with multiple
2423 address spaces. */
906e58ca 2424static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2425{
07d6d2b8
AM		 2426 0xe51ff004, /* ldr pc, [pc, #-4] */
2427 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2428};
2429
2430/* The first entry in a procedure linkage table looks like
2431 this. It is set up so that any shared library function that is
2432 called before the relocation has been set up calls the dynamic
2433 linker first. */
2434static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2435{
2436 /* First bundle: */
2437 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2438 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2439 0xe08cc00f, /* add ip, ip, pc */
2440 0xe52dc008, /* str ip, [sp, #-8]! */
2441 /* Second bundle: */
edccdf7c
RM		 2442 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2443 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2444 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2445 0xe12fff1c, /* bx ip */
b38cadfb 2446 /* Third bundle: */
edccdf7c
RM		 2447 0xe320f000, /* nop */
2448 0xe320f000, /* nop */
2449 0xe320f000, /* nop */
b38cadfb
NC		 2450 /* .Lplt_tail: */
2451 0xe50dc004, /* str ip, [sp, #-4] */
2452 /* Fourth bundle: */
edccdf7c
RM		 2453 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2454 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2455 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2456 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2457};
2458#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2459
2460/* Subsequent entries in a procedure linkage table look like this. */
2461static const bfd_vma elf32_arm_nacl_plt_entry [] =
2462{
2463 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2464 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2465 0xe08cc00f, /* add ip, ip, pc */
2466 0xea000000, /* b .Lplt_tail */
2467};
e5a52504 2468
906e58ca
NC		 2469#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2470#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2471#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2472#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2473#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2474#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2475#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2476#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2477
461a49ca 2478enum stub_insn_type
b38cadfb
NC		 2479{
2480 THUMB16_TYPE = 1,
2481 THUMB32_TYPE,
2482 ARM_TYPE,
2483 DATA_TYPE
2484};
461a49ca 2485
48229727
JB		 2486#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2487/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2488 is inserted in arm_build_one_stub(). */
2489#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2490#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2491#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2492#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2493#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2494#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2495#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2496#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2497
2498typedef struct
2499{
07d6d2b8 2500 bfd_vma data;
b38cadfb 2501 enum stub_insn_type type;
07d6d2b8
AM		 2502 unsigned int r_type;
2503 int reloc_addend;
461a49ca
DJ		 2504} insn_sequence;
2505
fea2b4d6
CL		 2506/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2507 to reach the stub if necessary. */
461a49ca 2508static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2509{
07d6d2b8 2510 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2511 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2512};
906e58ca 2513
fea2b4d6
CL		 2514/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2515 available. */
461a49ca 2516static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2517{
07d6d2b8
AM		 2518 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2519 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2520 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2521};
906e58ca 2522
d3626fb0 2523/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2524static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2525{
07d6d2b8
AM		 2526 THUMB16_INSN (0xb401), /* push {r0} */
2527 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2528 THUMB16_INSN (0x4684), /* mov ip, r0 */
2529 THUMB16_INSN (0xbc01), /* pop {r0} */
2530 THUMB16_INSN (0x4760), /* bx ip */
2531 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2532 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2533};
906e58ca 2534
80c135e5
TP		 2535/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2536static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2537{
07d6d2b8 2538 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2539 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2540};
2541
d5a67c02
AV		 2542/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2543 M-profile architectures. */
2544static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2545{
2546 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2547 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2548 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2549};
2550
d3626fb0
CL		 2551/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2552 allowed. */
2553static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2554{
07d6d2b8
AM		 2555 THUMB16_INSN (0x4778), /* bx pc */
2556 THUMB16_INSN (0x46c0), /* nop */
2557 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2558 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2559 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2560};
d3626fb0 2561
fea2b4d6
CL		 2562/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2563 available. */
461a49ca 2564static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2565{
07d6d2b8
AM		 2566 THUMB16_INSN (0x4778), /* bx pc */
2567 THUMB16_INSN (0x46c0), /* nop */
2568 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2569 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2570};
906e58ca 2571
fea2b4d6
CL		 2572/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2573 one, when the destination is close enough. */
461a49ca 2574static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2575{
07d6d2b8
AM		 2576 THUMB16_INSN (0x4778), /* bx pc */
2577 THUMB16_INSN (0x46c0), /* nop */
b38cadfb
NC		 2578 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2579};
c820be07 2580
cf3eccff 2581/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2582 blx to reach the stub if necessary. */
cf3eccff 2583static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2584{
07d6d2b8
AM		 2585 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2586 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2587 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2588};
906e58ca 2589
cf3eccff
DJ		 2590/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2591 blx to reach the stub if necessary. We can not add into pc;
2592 it is not guaranteed to mode switch (different in ARMv6 and
2593 ARMv7). */
2594static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2595{
07d6d2b8
AM		 2596 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2597 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2598 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2599 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2600};
cf3eccff 2601
ebe24dd4
CL		 2602/* V4T ARM -> ARM long branch stub, PIC. */
2603static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2604{
07d6d2b8
AM		 2605 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2606 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2607 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2608 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2609};
ebe24dd4
CL		 2610
2611/* V4T Thumb -> ARM long branch stub, PIC. */
2612static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2613{
07d6d2b8
AM		 2614 THUMB16_INSN (0x4778), /* bx pc */
2615 THUMB16_INSN (0x46c0), /* nop */
2616 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2617 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2618 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2619};
ebe24dd4 2620
d3626fb0
CL		 2621/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2622 architectures. */
ebe24dd4 2623static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2624{
07d6d2b8
AM		 2625 THUMB16_INSN (0xb401), /* push {r0} */
2626 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2627 THUMB16_INSN (0x46fc), /* mov ip, pc */
2628 THUMB16_INSN (0x4484), /* add ip, r0 */
2629 THUMB16_INSN (0xbc01), /* pop {r0} */
2630 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2631 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2632};
ebe24dd4 2633
d3626fb0
CL		 2634/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2635 allowed. */
2636static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2637{
07d6d2b8
AM		 2638 THUMB16_INSN (0x4778), /* bx pc */
2639 THUMB16_INSN (0x46c0), /* nop */
2640 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2641 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2642 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2643 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2644};
d3626fb0 2645
0855e32b
NS		 2646/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2647 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2648static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2649{
07d6d2b8
AM		 2650 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2651 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2652 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2653};
2654
2655/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2656 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2657static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2658{
07d6d2b8
AM		 2659 THUMB16_INSN (0x4778), /* bx pc */
2660 THUMB16_INSN (0x46c0), /* nop */
2661 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2662 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2663 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2664};
2665
7a89b94e
NC		 2666/* NaCl ARM -> ARM long branch stub. */
2667static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2668{
2669 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2670 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2671 ARM_INSN (0xe12fff1c), /* bx ip */
2672 ARM_INSN (0xe320f000), /* nop */
2673 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2674 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2675 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2676 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2677};
2678
2679/* NaCl ARM -> ARM long branch stub, PIC. */
2680static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2681{
2682 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2683 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2684 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2685 ARM_INSN (0xe12fff1c), /* bx ip */
2686 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2687 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2688 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2689 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2690};
2691
4ba2ef8f
TP		 2692/* Stub used for transition to secure state (aka SG veneer). */
2693static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2694{
2695 THUMB32_INSN (0xe97fe97f), /* sg. */
2696 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2697};
2698
7a89b94e 2699
48229727
JB		 2700/* Cortex-A8 erratum-workaround stubs. */
2701
2702/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2703 can't use a conditional branch to reach this stub). */
2704
2705static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2706{
07d6d2b8 2707 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2708 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2709 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2710};
48229727
JB		 2711
2712/* Stub used for b.w and bl.w instructions. */
2713
2714static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2715{
2716 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2717};
48229727
JB		 2718
2719static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2720{
2721 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2722};
48229727
JB		 2723
2724/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2725 instruction (which switches to ARM mode) to point to this stub. Jump to the
2726 real destination using an ARM-mode branch. */
2727
2728static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2729{
2730 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2731};
48229727 2732
9553db3c
NC		 2733/* For each section group there can be a specially created linker section
2734 to hold the stubs for that group. The name of the stub section is based
2735 upon the name of another section within that group with the suffix below
2736 applied.
2737
2738 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2739 create what appeared to be a linker stub section when it actually
2740 contained user code/data. For example, consider this fragment:
b38cadfb 2741
9553db3c
NC		 2742 const char * stubborn_problems[] = { "np" };
2743
2744 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2745 section called:
2746
2747 .data.rel.local.stubborn_problems
2748
2749 This then causes problems in arm32_arm_build_stubs() as it triggers:
2750
2751 // Ignore non-stub sections.
2752 if (!strstr (stub_sec->name, STUB_SUFFIX))
2753 continue;
2754
2755 And so the section would be ignored instead of being processed. Hence
2756 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2757 C identifier. */
2758#define STUB_SUFFIX ".__stub"
906e58ca 2759
738a79f6
CL		 2760/* One entry per long/short branch stub defined above. */
2761#define DEF_STUBS \
2762 DEF_STUB(long_branch_any_any) \
2763 DEF_STUB(long_branch_v4t_arm_thumb) \
2764 DEF_STUB(long_branch_thumb_only) \
2765 DEF_STUB(long_branch_v4t_thumb_thumb) \
2766 DEF_STUB(long_branch_v4t_thumb_arm) \
2767 DEF_STUB(short_branch_v4t_thumb_arm) \
2768 DEF_STUB(long_branch_any_arm_pic) \
2769 DEF_STUB(long_branch_any_thumb_pic) \
2770 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2771 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2772 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2773 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2774 DEF_STUB(long_branch_any_tls_pic) \
2775 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2776 DEF_STUB(long_branch_arm_nacl) \
2777 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2778 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2779 DEF_STUB(a8_veneer_b_cond) \
2780 DEF_STUB(a8_veneer_b) \
2781 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2782 DEF_STUB(a8_veneer_blx) \
2783 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2784 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2785
2786#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2787enum elf32_arm_stub_type
2788{
906e58ca 2789 arm_stub_none,
738a79f6 2790 DEF_STUBS
4f4faa4d 2791 max_stub_type
738a79f6
CL		 2792};
2793#undef DEF_STUB
2794
8d9d9490
TP		 2795/* Note the first a8_veneer type. */
2796const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2797
738a79f6
CL		 2798typedef struct
2799{
d3ce72d0 2800 const insn_sequence* template_sequence;
738a79f6
CL		 2801 int template_size;
2802} stub_def;
2803
2804#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2805static const stub_def stub_definitions[] =
2806{
738a79f6
CL		 2807 {NULL, 0},
2808 DEF_STUBS
906e58ca
NC		 2809};
2810
2811struct elf32_arm_stub_hash_entry
2812{
2813 /* Base hash table entry structure. */
2814 struct bfd_hash_entry root;
2815
2816 /* The stub section. */
2817 asection *stub_sec;
2818
2819 /* Offset within stub_sec of the beginning of this stub. */
2820 bfd_vma stub_offset;
2821
2822 /* Given the symbol's value and its section we can determine its final
2823 value when building the stubs (so the stub knows where to jump). */
2824 bfd_vma target_value;
2825 asection *target_section;
2826
8d9d9490
TP		 2827 /* Same as above but for the source of the branch to the stub. Used for
2828 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2829 such, source section does not need to be recorded since Cortex-A8 erratum
2830 workaround stubs are only generated when both source and target are in the
2831 same section. */
2832 bfd_vma source_value;
48229727
JB		 2833
2834 /* The instruction which caused this stub to be generated (only valid for
2835 Cortex-A8 erratum workaround stubs at present). */
2836 unsigned long orig_insn;
2837
461a49ca 2838 /* The stub type. */
906e58ca 2839 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2840 /* Its encoding size in bytes. */
2841 int stub_size;
2842 /* Its template. */
2843 const insn_sequence *stub_template;
2844 /* The size of the template (number of entries). */
2845 int stub_template_size;
906e58ca
NC		 2846
2847 /* The symbol table entry, if any, that this was derived from. */
2848 struct elf32_arm_link_hash_entry *h;
2849
35fc36a8
RS		 2850 /* Type of branch. */
2851 enum arm_st_branch_type branch_type;
906e58ca
NC		 2852
2853 /* Where this stub is being called from, or, in the case of combined
2854 stub sections, the first input section in the group. */
2855 asection *id_sec;
7413f23f
DJ		 2856
2857 /* The name for the local symbol at the start of this stub. The
2858 stub name in the hash table has to be unique; this does not, so
2859 it can be friendlier. */
2860 char *output_name;
906e58ca
NC		 2861};
2862
e489d0ae
PB		 2863/* Used to build a map of a section. This is required for mixed-endian
2864 code/data. */
2865
2866typedef struct elf32_elf_section_map
2867{
2868 bfd_vma vma;
2869 char type;
2870}
2871elf32_arm_section_map;
2872
c7b8f16e
JB		 2873/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2874
2875typedef enum
2876{
2877 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2878 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2879 VFP11_ERRATUM_ARM_VENEER,
2880 VFP11_ERRATUM_THUMB_VENEER
2881}
2882elf32_vfp11_erratum_type;
2883
2884typedef struct elf32_vfp11_erratum_list
2885{
2886 struct elf32_vfp11_erratum_list *next;
2887 bfd_vma vma;
2888 union
2889 {
2890 struct
2891 {
2892 struct elf32_vfp11_erratum_list *veneer;
2893 unsigned int vfp_insn;
2894 } b;
2895 struct
2896 {
2897 struct elf32_vfp11_erratum_list *branch;
2898 unsigned int id;
2899 } v;
2900 } u;
2901 elf32_vfp11_erratum_type type;
2902}
2903elf32_vfp11_erratum_list;
2904
a504d23a
LA		 2905/* Information about a STM32L4XX erratum veneer, or a branch to such a
2906 veneer. */
2907typedef enum
2908{
2909 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2910 STM32L4XX_ERRATUM_VENEER
2911}
2912elf32_stm32l4xx_erratum_type;
2913
2914typedef struct elf32_stm32l4xx_erratum_list
2915{
2916 struct elf32_stm32l4xx_erratum_list *next;
2917 bfd_vma vma;
2918 union
2919 {
2920 struct
2921 {
2922 struct elf32_stm32l4xx_erratum_list *veneer;
2923 unsigned int insn;
2924 } b;
2925 struct
2926 {
2927 struct elf32_stm32l4xx_erratum_list *branch;
2928 unsigned int id;
2929 } v;
2930 } u;
2931 elf32_stm32l4xx_erratum_type type;
2932}
2933elf32_stm32l4xx_erratum_list;
2934
2468f9c9
PB		 2935typedef enum
2936{
2937 DELETE_EXIDX_ENTRY,
2938 INSERT_EXIDX_CANTUNWIND_AT_END
2939}
2940arm_unwind_edit_type;
2941
2942/* A (sorted) list of edits to apply to an unwind table. */
2943typedef struct arm_unwind_table_edit
2944{
2945 arm_unwind_edit_type type;
2946 /* Note: we sometimes want to insert an unwind entry corresponding to a
2947 section different from the one we're currently writing out, so record the
2948 (text) section this edit relates to here. */
2949 asection *linked_section;
2950 unsigned int index;
2951 struct arm_unwind_table_edit *next;
2952}
2953arm_unwind_table_edit;
2954
8e3de13a 2955typedef struct _arm_elf_section_data
e489d0ae 2956{
2468f9c9 2957 /* Information about mapping symbols. */
e489d0ae 2958 struct bfd_elf_section_data elf;
8e3de13a 2959 unsigned int mapcount;
c7b8f16e 2960 unsigned int mapsize;
e489d0ae 2961 elf32_arm_section_map *map;
2468f9c9 2962 /* Information about CPU errata. */
c7b8f16e
JB		 2963 unsigned int erratumcount;
2964 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2965 unsigned int stm32l4xx_erratumcount;
2966 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2967 unsigned int additional_reloc_count;
2468f9c9
PB		 2968 /* Information about unwind tables. */
2969 union
2970 {
2971 /* Unwind info attached to a text section. */
2972 struct
2973 {
2974 asection *arm_exidx_sec;
2975 } text;
2976
2977 /* Unwind info attached to an .ARM.exidx section. */
2978 struct
2979 {
2980 arm_unwind_table_edit *unwind_edit_list;
2981 arm_unwind_table_edit *unwind_edit_tail;
2982 } exidx;
2983 } u;
8e3de13a
NC		 2984}
2985_arm_elf_section_data;
e489d0ae
PB		 2986
2987#define elf32_arm_section_data(sec) \
8e3de13a 2988 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2989
48229727
JB		 2990/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2991 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2992 so may be created multiple times: we use an array of these entries whilst
2993 relaxing which we can refresh easily, then create stubs for each potentially
2994 erratum-triggering instruction once we've settled on a solution. */
2995
b38cadfb
NC		 2996struct a8_erratum_fix
2997{
48229727
JB		 2998 bfd *input_bfd;
2999 asection *section;
3000 bfd_vma offset;
8d9d9490 3001 bfd_vma target_offset;
48229727
JB		 3002 unsigned long orig_insn;
3003 char *stub_name;
3004 enum elf32_arm_stub_type stub_type;
35fc36a8 3005 enum arm_st_branch_type branch_type;
48229727
JB		 3006};
3007
3008/* A table of relocs applied to branches which might trigger Cortex-A8
3009 erratum. */
3010
b38cadfb
NC		 3011struct a8_erratum_reloc
3012{
48229727
JB		 3013 bfd_vma from;
3014 bfd_vma destination;
92750f34
DJ		 3015 struct elf32_arm_link_hash_entry *hash;
3016 const char *sym_name;
48229727 3017 unsigned int r_type;
35fc36a8 3018 enum arm_st_branch_type branch_type;
48229727
JB		 3019 bfd_boolean non_a8_stub;
3020};
3021
ba93b8ac
DJ		 3022/* The size of the thread control block. */
3023#define TCB_SIZE 8
3024
34e77a92
RS		 3025/* ARM-specific information about a PLT entry, over and above the usual
3026 gotplt_union. */
b38cadfb
NC		 3027struct arm_plt_info
3028{
34e77a92
RS		 3029 /* We reference count Thumb references to a PLT entry separately,
3030 so that we can emit the Thumb trampoline only if needed. */
3031 bfd_signed_vma thumb_refcount;
3032
3033 /* Some references from Thumb code may be eliminated by BL->BLX
3034 conversion, so record them separately. */
3035 bfd_signed_vma maybe_thumb_refcount;
3036
3037 /* How many of the recorded PLT accesses were from non-call relocations.
3038 This information is useful when deciding whether anything takes the
3039 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3040 non-call references to the function should resolve directly to the
3041 real runtime target. */
3042 unsigned int noncall_refcount;
3043
3044 /* Since PLT entries have variable size if the Thumb prologue is
3045 used, we need to record the index into .got.plt instead of
3046 recomputing it from the PLT offset. */
3047 bfd_signed_vma got_offset;
3048};
3049
3050/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 3051struct arm_local_iplt_info
3052{
34e77a92
RS		 3053 /* The information that is usually found in the generic ELF part of
3054 the hash table entry. */
3055 union gotplt_union root;
3056
3057 /* The information that is usually found in the ARM-specific part of
3058 the hash table entry. */
3059 struct arm_plt_info arm;
3060
3061 /* A list of all potential dynamic relocations against this symbol. */
3062 struct elf_dyn_relocs *dyn_relocs;
3063};
3064
e8b09b87
CL		 3065/* Structure to handle FDPIC support for local functions. */
3066struct fdpic_local {
3067 unsigned int funcdesc_cnt;
3068 unsigned int gotofffuncdesc_cnt;
3069 int funcdesc_offset;
3070};
3071
0ffa91dd 3072struct elf_arm_obj_tdata
ba93b8ac
DJ		 3073{
3074 struct elf_obj_tdata root;
3075
3076 /* tls_type for each local got entry. */
3077 char *local_got_tls_type;
ee065d83 3078
0855e32b
NS		 3079 /* GOTPLT entries for TLS descriptors. */
3080 bfd_vma *local_tlsdesc_gotent;
3081
34e77a92
RS		 3082 /* Information for local symbols that need entries in .iplt. */
3083 struct arm_local_iplt_info **local_iplt;
3084
bf21ed78
MS		 3085 /* Zero to warn when linking objects with incompatible enum sizes. */
3086 int no_enum_size_warning;
a9dc9481
JM		 3087
3088 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3089 int no_wchar_size_warning;
e8b09b87
CL		 3090
3091 /* Maintains FDPIC counters and funcdesc info. */
3092 struct fdpic_local *local_fdpic_cnts;
ba93b8ac
DJ		 3093};
3094
0ffa91dd
NC		 3095#define elf_arm_tdata(bfd) \
3096 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3097
0ffa91dd
NC		 3098#define elf32_arm_local_got_tls_type(bfd) \
3099 (elf_arm_tdata (bfd)->local_got_tls_type)
3100
0855e32b
NS		 3101#define elf32_arm_local_tlsdesc_gotent(bfd) \
3102 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3103
34e77a92
RS		 3104#define elf32_arm_local_iplt(bfd) \
3105 (elf_arm_tdata (bfd)->local_iplt)
3106
e8b09b87
CL		 3107#define elf32_arm_local_fdpic_cnts(bfd) \
3108 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3109
0ffa91dd
NC		 3110#define is_arm_elf(bfd) \
3111 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3112 && elf_tdata (bfd) != NULL \
4dfe6ac6 3113 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3114
3115static bfd_boolean
3116elf32_arm_mkobject (bfd *abfd)
3117{
0ffa91dd 3118 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3119 ARM_ELF_DATA);
ba93b8ac
DJ		 3120}
3121
ba93b8ac
DJ		 3122#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3123
e8b09b87
CL		 3124/* Structure to handle FDPIC support for extern functions. */
3125struct fdpic_global {
3126 unsigned int gotofffuncdesc_cnt;
3127 unsigned int gotfuncdesc_cnt;
3128 unsigned int funcdesc_cnt;
3129 int funcdesc_offset;
3130 int gotfuncdesc_offset;
3131};
3132
ba96a88f 3133/* Arm ELF linker hash entry. */
252b5132 3134struct elf32_arm_link_hash_entry
b38cadfb
NC		 3135{
3136 struct elf_link_hash_entry root;
252b5132 3137
b38cadfb
NC		 3138 /* Track dynamic relocs copied for this symbol. */
3139 struct elf_dyn_relocs *dyn_relocs;
b7693d02 3140
b38cadfb
NC		 3141 /* ARM-specific PLT information. */
3142 struct arm_plt_info plt;
ba93b8ac
DJ		 3143
3144#define GOT_UNKNOWN 0
3145#define GOT_NORMAL 1
3146#define GOT_TLS_GD 2
3147#define GOT_TLS_IE 4
0855e32b
NS		 3148#define GOT_TLS_GDESC 8
3149#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3150 unsigned int tls_type : 8;
34e77a92 3151
b38cadfb
NC		 3152 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3153 unsigned int is_iplt : 1;
34e77a92 3154
b38cadfb 3155 unsigned int unused : 23;
a4fd1a8e 3156
b38cadfb
NC		 3157 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3158 starting at the end of the jump table. */
3159 bfd_vma tlsdesc_got;
0855e32b 3160
b38cadfb
NC		 3161 /* The symbol marking the real symbol location for exported thumb
3162 symbols with Arm stubs. */
3163 struct elf_link_hash_entry *export_glue;
906e58ca 3164
b38cadfb 3165 /* A pointer to the most recently used stub hash entry against this
8029a119 3166 symbol. */
b38cadfb 3167 struct elf32_arm_stub_hash_entry *stub_cache;
e8b09b87
CL		 3168
3169 /* Counter for FDPIC relocations against this symbol. */
3170 struct fdpic_global fdpic_cnts;
b38cadfb 3171};
252b5132 3172
252b5132 3173/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3174#define elf32_arm_link_hash_traverse(table, func, info) \
3175 (elf_link_hash_traverse \
3176 (&(table)->root, \
b7693d02 3177 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3178 (info)))
3179
3180/* Get the ARM elf linker hash table from a link_info structure. */
3181#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3182 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3183 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3184
906e58ca
NC		 3185#define arm_stub_hash_lookup(table, string, create, copy) \
3186 ((struct elf32_arm_stub_hash_entry *) \
3187 bfd_hash_lookup ((table), (string), (create), (copy)))
3188
21d799b5
NC		 3189/* Array to keep track of which stub sections have been created, and
3190 information on stub grouping. */
3191struct map_stub
3192{
3193 /* This is the section to which stubs in the group will be
3194 attached. */
3195 asection *link_sec;
3196 /* The stub section. */
3197 asection *stub_sec;
3198};
3199
0855e32b
NS		 3200#define elf32_arm_compute_jump_table_size(htab) \
3201 ((htab)->next_tls_desc_index * 4)
3202
9b485d32 3203/* ARM ELF linker hash table. */
252b5132 3204struct elf32_arm_link_hash_table
906e58ca
NC		 3205{
3206 /* The main hash table. */
3207 struct elf_link_hash_table root;
252b5132 3208
906e58ca
NC		 3209 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3210 bfd_size_type thumb_glue_size;
252b5132 3211
906e58ca
NC		 3212 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3213 bfd_size_type arm_glue_size;
252b5132 3214
906e58ca
NC		 3215 /* The size in bytes of section containing the ARMv4 BX veneers. */
3216 bfd_size_type bx_glue_size;
845b51d6 3217
906e58ca
NC		 3218 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3219 veneer has been populated. */
3220 bfd_vma bx_glue_offset[15];
845b51d6 3221
906e58ca
NC		 3222 /* The size in bytes of the section containing glue for VFP11 erratum
3223 veneers. */
3224 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3225
a504d23a
LA		 3226 /* The size in bytes of the section containing glue for STM32L4XX erratum
3227 veneers. */
3228 bfd_size_type stm32l4xx_erratum_glue_size;
3229
48229727
JB		 3230 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3231 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3232 elf32_arm_write_section(). */
3233 struct a8_erratum_fix *a8_erratum_fixes;
3234 unsigned int num_a8_erratum_fixes;
3235
906e58ca
NC		 3236 /* An arbitrary input BFD chosen to hold the glue sections. */
3237 bfd * bfd_of_glue_owner;
ba96a88f 3238
906e58ca
NC		 3239 /* Nonzero to output a BE8 image. */
3240 int byteswap_code;
e489d0ae 3241
906e58ca
NC		 3242 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3243 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3244 int target1_is_rel;
9c504268 3245
906e58ca
NC		 3246 /* The relocation to use for R_ARM_TARGET2 relocations. */
3247 int target2_reloc;
eb043451 3248
906e58ca
NC		 3249 /* 0 = Ignore R_ARM_V4BX.
3250 1 = Convert BX to MOV PC.
3251 2 = Generate v4 interworing stubs. */
3252 int fix_v4bx;
319850b4 3253
48229727
JB		 3254 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3255 int fix_cortex_a8;
3256
2de70689
MGD		 3257 /* Whether we should fix the ARM1176 BLX immediate issue. */
3258 int fix_arm1176;
3259
906e58ca
NC		 3260 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3261 int use_blx;
33bfe774 3262
906e58ca
NC		 3263 /* What sort of code sequences we should look for which may trigger the
3264 VFP11 denorm erratum. */
3265 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3266
906e58ca
NC		 3267 /* Global counter for the number of fixes we have emitted. */
3268 int num_vfp11_fixes;
c7b8f16e 3269
a504d23a
LA		 3270 /* What sort of code sequences we should look for which may trigger the
3271 STM32L4XX erratum. */
3272 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3273
3274 /* Global counter for the number of fixes we have emitted. */
3275 int num_stm32l4xx_fixes;
3276
906e58ca
NC		 3277 /* Nonzero to force PIC branch veneers. */
3278 int pic_veneer;
27e55c4d 3279
906e58ca
NC		 3280 /* The number of bytes in the initial entry in the PLT. */
3281 bfd_size_type plt_header_size;
e5a52504 3282
906e58ca
NC		 3283 /* The number of bytes in the subsequent PLT etries. */
3284 bfd_size_type plt_entry_size;
e5a52504 3285
906e58ca
NC		 3286 /* True if the target system is VxWorks. */
3287 int vxworks_p;
00a97672 3288
906e58ca
NC		 3289 /* True if the target system is Symbian OS. */
3290 int symbian_p;
e5a52504 3291
b38cadfb
NC		 3292 /* True if the target system is Native Client. */
3293 int nacl_p;
3294
906e58ca 3295 /* True if the target uses REL relocations. */
f3185997 3296 bfd_boolean use_rel;
4e7fd91e 3297
54ddd295
TP		 3298 /* Nonzero if import library must be a secure gateway import library
3299 as per ARMv8-M Security Extensions. */
3300 int cmse_implib;
3301
0955507f
TP		 3302 /* The import library whose symbols' address must remain stable in
3303 the import library generated. */
3304 bfd *in_implib_bfd;
3305
0855e32b
NS		 3306 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3307 bfd_vma next_tls_desc_index;
3308
3309 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3310 bfd_vma num_tls_desc;
3311
906e58ca
NC		 3312 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3313 asection *srelplt2;
00a97672 3314
0855e32b
NS		 3315 /* The offset into splt of the PLT entry for the TLS descriptor
3316 resolver. Special values are 0, if not necessary (or not found
3317 to be necessary yet), and -1 if needed but not determined
3318 yet. */
3319 bfd_vma dt_tlsdesc_plt;
3320
3321 /* The offset into sgot of the GOT entry used by the PLT entry
3322 above. */
b38cadfb 3323 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3324
3325 /* Offset in .plt section of tls_arm_trampoline. */
3326 bfd_vma tls_trampoline;
3327
5c5a4843 3328 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
906e58ca
NC		 3329 union
3330 {
3331 bfd_signed_vma refcount;
3332 bfd_vma offset;
3333 } tls_ldm_got;
b7693d02 3334
87d72d41
AM		 3335 /* Small local sym cache. */
3336 struct sym_cache sym_cache;
906e58ca
NC		 3337
3338 /* For convenience in allocate_dynrelocs. */
3339 bfd * obfd;
3340
0855e32b
NS		 3341 /* The amount of space used by the reserved portion of the sgotplt
3342 section, plus whatever space is used by the jump slots. */
3343 bfd_vma sgotplt_jump_table_size;
3344
906e58ca
NC		 3345 /* The stub hash table. */
3346 struct bfd_hash_table stub_hash_table;
3347
3348 /* Linker stub bfd. */
3349 bfd *stub_bfd;
3350
3351 /* Linker call-backs. */
6bde4c52
TP		 3352 asection * (*add_stub_section) (const char *, asection *, asection *,
3353 unsigned int);
906e58ca
NC		 3354 void (*layout_sections_again) (void);
3355
3356 /* Array to keep track of which stub sections have been created, and
3357 information on stub grouping. */
21d799b5 3358 struct map_stub *stub_group;
906e58ca 3359
4ba2ef8f
TP		 3360 /* Input stub section holding secure gateway veneers. */
3361 asection *cmse_stub_sec;
3362
0955507f
TP		 3363 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3364 start to be allocated. */
3365 bfd_vma new_cmse_stub_offset;
3366
fe33d2fa 3367 /* Number of elements in stub_group. */
7292b3ac 3368 unsigned int top_id;
fe33d2fa 3369
906e58ca
NC		 3370 /* Assorted information used by elf32_arm_size_stubs. */
3371 unsigned int bfd_count;
7292b3ac 3372 unsigned int top_index;
906e58ca 3373 asection **input_list;
617a5ada
CL		 3374
3375 /* True if the target system uses FDPIC. */
3376 int fdpic_p;
e8b09b87
CL		 3377
3378 /* Fixup section. Used for FDPIC. */
3379 asection *srofixup;
906e58ca 3380};
252b5132 3381
e8b09b87
CL		 3382/* Add an FDPIC read-only fixup. */
3383static void
3384arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3385{
3386 bfd_vma fixup_offset;
3387
3388 fixup_offset = srofixup->reloc_count++ * 4;
3389 BFD_ASSERT (fixup_offset < srofixup->size);
3390 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3391}
3392
a504d23a
LA		 3393static inline int
3394ctz (unsigned int mask)
3395{
3396#if GCC_VERSION >= 3004
3397 return __builtin_ctz (mask);
3398#else
3399 unsigned int i;
3400
3401 for (i = 0; i < 8 * sizeof (mask); i++)
3402 {
3403 if (mask & 0x1)
3404 break;
3405 mask = (mask >> 1);
3406 }
3407 return i;
3408#endif
3409}
3410
3411static inline int
b25e998d 3412elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3413{
3414#if GCC_VERSION >= 3004
3415 return __builtin_popcount (mask);
3416#else
b25e998d
CG		 3417 unsigned int i;
3418 int sum = 0;
a504d23a
LA		 3419
3420 for (i = 0; i < 8 * sizeof (mask); i++)
3421 {
3422 if (mask & 0x1)
3423 sum++;
3424 mask = (mask >> 1);
3425 }
3426 return sum;
3427#endif
3428}
3429
e8b09b87
CL		 3430static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3431 asection *sreloc, Elf_Internal_Rela *rel);
3432
3433static void
3434arm_elf_fill_funcdesc(bfd *output_bfd,
3435 struct bfd_link_info *info,
3436 int *funcdesc_offset,
3437 int dynindx,
3438 int offset,
3439 bfd_vma addr,
3440 bfd_vma dynreloc_value,
3441 bfd_vma seg)
3442{
3443 if ((*funcdesc_offset & 1) == 0)
3444 {
3445 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3446 asection *sgot = globals->root.sgot;
3447
3448 if (bfd_link_pic(info))
3449 {
3450 asection *srelgot = globals->root.srelgot;
3451 Elf_Internal_Rela outrel;
3452
3453 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3454 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3455 outrel.r_addend = 0;
3456
3457 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3458 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3459 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3460 }
3461 else
3462 {
3463 struct elf_link_hash_entry *hgot = globals->root.hgot;
3464 bfd_vma got_value = hgot->root.u.def.value
3465 + hgot->root.u.def.section->output_section->vma
3466 + hgot->root.u.def.section->output_offset;
3467
3468 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3469 sgot->output_section->vma + sgot->output_offset
3470 + offset);
3471 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3472 sgot->output_section->vma + sgot->output_offset
3473 + offset + 4);
3474 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3475 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3476 }
3477 *funcdesc_offset |= 1;
3478 }
3479}
3480
780a67af
NC		 3481/* Create an entry in an ARM ELF linker hash table. */
3482
3483static struct bfd_hash_entry *
57e8b36a 3484elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3485 struct bfd_hash_table * table,
3486 const char * string)
780a67af
NC		 3487{
3488 struct elf32_arm_link_hash_entry * ret =
3489 (struct elf32_arm_link_hash_entry *) entry;
3490
3491 /* Allocate the structure if it has not already been allocated by a
3492 subclass. */
906e58ca 3493 if (ret == NULL)
21d799b5 3494 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3495 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3496 if (ret == NULL)
780a67af
NC		 3497 return (struct bfd_hash_entry *) ret;
3498
3499 /* Call the allocation method of the superclass. */
3500 ret = ((struct elf32_arm_link_hash_entry *)
3501 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3502 table, string));
57e8b36a 3503 if (ret != NULL)
b7693d02 3504 {
0bdcacaf 3505 ret->dyn_relocs = NULL;
ba93b8ac 3506 ret->tls_type = GOT_UNKNOWN;
0855e32b 3507 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3508 ret->plt.thumb_refcount = 0;
3509 ret->plt.maybe_thumb_refcount = 0;
3510 ret->plt.noncall_refcount = 0;
3511 ret->plt.got_offset = -1;
3512 ret->is_iplt = FALSE;
a4fd1a8e 3513 ret->export_glue = NULL;
906e58ca
NC		 3514
3515 ret->stub_cache = NULL;
e8b09b87
CL		 3516
3517 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3518 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3519 ret->fdpic_cnts.funcdesc_cnt = 0;
3520 ret->fdpic_cnts.funcdesc_offset = -1;
3521 ret->fdpic_cnts.gotfuncdesc_offset = -1;
b7693d02 3522 }
780a67af
NC		 3523
3524 return (struct bfd_hash_entry *) ret;
3525}
3526
34e77a92
RS		 3527/* Ensure that we have allocated bookkeeping structures for ABFD's local
3528 symbols. */
3529
3530static bfd_boolean
3531elf32_arm_allocate_local_sym_info (bfd *abfd)
3532{
3533 if (elf_local_got_refcounts (abfd) == NULL)
3534 {
3535 bfd_size_type num_syms;
3536 bfd_size_type size;
3537 char *data;
3538
3539 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3540 size = num_syms * (sizeof (bfd_signed_vma)
3541 + sizeof (struct arm_local_iplt_info *)
3542 + sizeof (bfd_vma)
e8b09b87
CL		 3543 + sizeof (char)
3544 + sizeof (struct fdpic_local));
34e77a92
RS		 3545 data = bfd_zalloc (abfd, size);
3546 if (data == NULL)
3547 return FALSE;
3548
e8b09b87
CL		 3549 elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
3550 data += num_syms * sizeof (struct fdpic_local);
3551
34e77a92
RS		 3552 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3553 data += num_syms * sizeof (bfd_signed_vma);
3554
3555 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3556 data += num_syms * sizeof (struct arm_local_iplt_info *);
3557
3558 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3559 data += num_syms * sizeof (bfd_vma);
3560
3561 elf32_arm_local_got_tls_type (abfd) = data;
3562 }
3563 return TRUE;
3564}
3565
3566/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3567 to input bfd ABFD. Create the information if it doesn't already exist.
3568 Return null if an allocation fails. */
3569
3570static struct arm_local_iplt_info *
3571elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3572{
3573 struct arm_local_iplt_info **ptr;
3574
3575 if (!elf32_arm_allocate_local_sym_info (abfd))
3576 return NULL;
3577
3578 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3579 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3580 if (*ptr == NULL)
3581 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3582 return *ptr;
3583}
3584
3585/* Try to obtain PLT information for the symbol with index R_SYMNDX
3586 in ABFD's symbol table. If the symbol is global, H points to its
3587 hash table entry, otherwise H is null.
3588
3589 Return true if the symbol does have PLT information. When returning
3590 true, point *ROOT_PLT at the target-independent reference count/offset
3591 union and *ARM_PLT at the ARM-specific information. */
3592
3593static bfd_boolean
4ba2ef8f
TP		 3594elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3595 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3596 unsigned long r_symndx, union gotplt_union **root_plt,
3597 struct arm_plt_info **arm_plt)
3598{
3599 struct arm_local_iplt_info *local_iplt;
3600
4ba2ef8f
TP		 3601 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3602 return FALSE;
3603
34e77a92
RS		 3604 if (h != NULL)
3605 {
3606 *root_plt = &h->root.plt;
3607 *arm_plt = &h->plt;
3608 return TRUE;
3609 }
3610
3611 if (elf32_arm_local_iplt (abfd) == NULL)
3612 return FALSE;
3613
3614 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3615 if (local_iplt == NULL)
3616 return FALSE;
3617
3618 *root_plt = &local_iplt->root;
3619 *arm_plt = &local_iplt->arm;
3620 return TRUE;
3621}
3622
3623/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3624 before it. */
3625
3626static bfd_boolean
3627elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3628 struct arm_plt_info *arm_plt)
3629{
3630 struct elf32_arm_link_hash_table *htab;
3631
3632 htab = elf32_arm_hash_table (info);
3633 return (arm_plt->thumb_refcount != 0
3634 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3635}
3636
3637/* Return a pointer to the head of the dynamic reloc list that should
3638 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3639 ABFD's symbol table. Return null if an error occurs. */
3640
3641static struct elf_dyn_relocs **
3642elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3643 Elf_Internal_Sym *isym)
3644{
3645 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3646 {
3647 struct arm_local_iplt_info *local_iplt;
3648
3649 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3650 if (local_iplt == NULL)
3651 return NULL;
3652 return &local_iplt->dyn_relocs;
3653 }
3654 else
3655 {
3656 /* Track dynamic relocs needed for local syms too.
3657 We really need local syms available to do this
3658 easily. Oh well. */
3659 asection *s;
3660 void *vpp;
3661
3662 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3663 if (s == NULL)
3664 abort ();
3665
3666 vpp = &elf_section_data (s)->local_dynrel;
3667 return (struct elf_dyn_relocs **) vpp;
3668 }
3669}
3670
906e58ca
NC		 3671/* Initialize an entry in the stub hash table. */
3672
3673static struct bfd_hash_entry *
3674stub_hash_newfunc (struct bfd_hash_entry *entry,
3675 struct bfd_hash_table *table,
3676 const char *string)
3677{
3678 /* Allocate the structure if it has not already been allocated by a
3679 subclass. */
3680 if (entry == NULL)
3681 {
21d799b5 3682 entry = (struct bfd_hash_entry *)
99059e56 3683 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3684 if (entry == NULL)
3685 return entry;
3686 }
3687
3688 /* Call the allocation method of the superclass. */
3689 entry = bfd_hash_newfunc (entry, table, string);
3690 if (entry != NULL)
3691 {
3692 struct elf32_arm_stub_hash_entry *eh;
3693
3694 /* Initialize the local fields. */
3695 eh = (struct elf32_arm_stub_hash_entry *) entry;
3696 eh->stub_sec = NULL;
0955507f 3697 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3698 eh->source_value = 0;
906e58ca
NC		 3699 eh->target_value = 0;
3700 eh->target_section = NULL;
cedfb179 3701 eh->orig_insn = 0;
906e58ca 3702 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3703 eh->stub_size = 0;
3704 eh->stub_template = NULL;
0955507f 3705 eh->stub_template_size = -1;
906e58ca
NC		 3706 eh->h = NULL;
3707 eh->id_sec = NULL;
d8d2f433 3708 eh->output_name = NULL;
906e58ca
NC		 3709 }
3710
3711 return entry;
3712}
3713
00a97672 3714/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3715 shortcuts to them in our hash table. */
3716
3717static bfd_boolean
57e8b36a 3718create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3719{
3720 struct elf32_arm_link_hash_table *htab;
3721
e5a52504 3722 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3723 if (htab == NULL)
3724 return FALSE;
3725
e5a52504
MM		 3726 /* BPABI objects never have a GOT, or associated sections. */
3727 if (htab->symbian_p)
3728 return TRUE;
3729
5e681ec4
PB		 3730 if (! _bfd_elf_create_got_section (dynobj, info))
3731 return FALSE;
3732
e8b09b87
CL		 3733 /* Also create .rofixup. */
3734 if (htab->fdpic_p)
3735 {
3736 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3737 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3738 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
3739 if (htab->srofixup == NULL || ! bfd_set_section_alignment (dynobj, htab->srofixup, 2))
3740 return FALSE;
3741 }
3742
5e681ec4
PB		 3743 return TRUE;
3744}
3745
34e77a92
RS		 3746/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3747
3748static bfd_boolean
3749create_ifunc_sections (struct bfd_link_info *info)
3750{
3751 struct elf32_arm_link_hash_table *htab;
3752 const struct elf_backend_data *bed;
3753 bfd *dynobj;
3754 asection *s;
3755 flagword flags;
b38cadfb 3756
34e77a92
RS		 3757 htab = elf32_arm_hash_table (info);
3758 dynobj = htab->root.dynobj;
3759 bed = get_elf_backend_data (dynobj);
3760 flags = bed->dynamic_sec_flags;
3761
3762 if (htab->root.iplt == NULL)
3763 {
3d4d4302
AM		 3764 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3765 flags | SEC_READONLY | SEC_CODE);
34e77a92 3766 if (s == NULL
a0f49396 3767 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3768 return FALSE;
3769 htab->root.iplt = s;
3770 }
3771
3772 if (htab->root.irelplt == NULL)
3773 {
3d4d4302
AM		 3774 s = bfd_make_section_anyway_with_flags (dynobj,
3775 RELOC_SECTION (htab, ".iplt"),
3776 flags | SEC_READONLY);
34e77a92 3777 if (s == NULL
a0f49396 3778 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3779 return FALSE;
3780 htab->root.irelplt = s;
3781 }
3782
3783 if (htab->root.igotplt == NULL)
3784 {
3d4d4302 3785 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3786 if (s == NULL
3787 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3788 return FALSE;
3789 htab->root.igotplt = s;
3790 }
3791 return TRUE;
3792}
3793
eed94f8f
NC		 3794/* Determine if we're dealing with a Thumb only architecture. */
3795
3796static bfd_boolean
3797using_thumb_only (struct elf32_arm_link_hash_table *globals)
3798{
2fd158eb
TP		 3799 int arch;
3800 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3801 Tag_CPU_arch_profile);
eed94f8f 3802
2fd158eb
TP		 3803 if (profile)
3804 return profile == 'M';
eed94f8f 3805
2fd158eb 3806 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3807
60a019a0 3808 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3809 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0 3810
2fd158eb
TP		 3811 if (arch == TAG_CPU_ARCH_V6_M
3812 || arch == TAG_CPU_ARCH_V6S_M
3813 || arch == TAG_CPU_ARCH_V7E_M
3814 || arch == TAG_CPU_ARCH_V8M_BASE
3815 || arch == TAG_CPU_ARCH_V8M_MAIN)
3816 return TRUE;
eed94f8f 3817
2fd158eb 3818 return FALSE;
eed94f8f
NC		 3819}
3820
3821/* Determine if we're dealing with a Thumb-2 object. */
3822
3823static bfd_boolean
3824using_thumb2 (struct elf32_arm_link_hash_table *globals)
3825{
60a019a0
TP		 3826 int arch;
3827 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3828 Tag_THUMB_ISA_use);
3829
3830 if (thumb_isa)
3831 return thumb_isa == 2;
3832
3833 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3834
3835 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3836 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0
TP		 3837
3838 return (arch == TAG_CPU_ARCH_V6T2
3839 || arch == TAG_CPU_ARCH_V7
3840 || arch == TAG_CPU_ARCH_V7E_M
3841 || arch == TAG_CPU_ARCH_V8
bff0500d 3842 || arch == TAG_CPU_ARCH_V8R
60a019a0 3843 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3844}
3845
5e866f5a
TP		 3846/* Determine whether Thumb-2 BL instruction is available. */
3847
3848static bfd_boolean
3849using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3850{
3851 int arch =
3852 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3853
3854 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3855 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
5e866f5a
TP		 3856
3857 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3858 return (arch == TAG_CPU_ARCH_V6T2
3859 || arch >= TAG_CPU_ARCH_V7);
3860}
3861
00a97672
RS		 3862/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3863 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3864 hash table. */
3865
3866static bfd_boolean
57e8b36a 3867elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3868{
3869 struct elf32_arm_link_hash_table *htab;
3870
3871 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3872 if (htab == NULL)
3873 return FALSE;
3874
362d30a1 3875 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3876 return FALSE;
3877
3878 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3879 return FALSE;
3880
00a97672
RS		 3881 if (htab->vxworks_p)
3882 {
3883 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3884 return FALSE;
3885
0e1862bb 3886 if (bfd_link_pic (info))
00a97672
RS		 3887 {
3888 htab->plt_header_size = 0;
3889 htab->plt_entry_size
3890 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3891 }
3892 else
3893 {
3894 htab->plt_header_size
3895 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3896 htab->plt_entry_size
3897 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3898 }
aebf9be7
NC		 3899
3900 if (elf_elfheader (dynobj))
3901 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3902 }
eed94f8f
NC		 3903 else
3904 {
3905 /* PR ld/16017
3906 Test for thumb only architectures. Note - we cannot just call
3907 using_thumb_only() as the attributes in the output bfd have not been
3908 initialised at this point, so instead we use the input bfd. */
3909 bfd * saved_obfd = htab->obfd;
3910
3911 htab->obfd = dynobj;
3912 if (using_thumb_only (htab))
3913 {
3914 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3915 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3916 }
3917 htab->obfd = saved_obfd;
3918 }
5e681ec4 3919
7801f98f
CL		 3920 if (htab->fdpic_p) {
3921 htab->plt_header_size = 0;
3922 if (info->flags & DF_BIND_NOW)
3923 htab->plt_entry_size = 4 * (ARRAY_SIZE(elf32_arm_fdpic_plt_entry) - 5);
3924 else
3925 htab->plt_entry_size = 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry);
3926 }
3927
362d30a1
RS		 3928 if (!htab->root.splt
3929 || !htab->root.srelplt
9d19e4fd
AM		 3930 || !htab->root.sdynbss
3931 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 3932 abort ();
3933
3934 return TRUE;
3935}
3936
906e58ca
NC		 3937/* Copy the extra info we tack onto an elf_link_hash_entry. */
3938
3939static void
3940elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3941 struct elf_link_hash_entry *dir,
3942 struct elf_link_hash_entry *ind)
3943{
3944 struct elf32_arm_link_hash_entry *edir, *eind;
3945
3946 edir = (struct elf32_arm_link_hash_entry *) dir;
3947 eind = (struct elf32_arm_link_hash_entry *) ind;
3948
0bdcacaf 3949 if (eind->dyn_relocs != NULL)
906e58ca 3950 {
0bdcacaf 3951 if (edir->dyn_relocs != NULL)
906e58ca 3952 {
0bdcacaf
RS		 3953 struct elf_dyn_relocs **pp;
3954 struct elf_dyn_relocs *p;
906e58ca
NC		 3955
3956 /* Add reloc counts against the indirect sym to the direct sym
3957 list. Merge any entries against the same section. */
0bdcacaf 3958 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3959 {
0bdcacaf 3960 struct elf_dyn_relocs *q;
906e58ca 3961
0bdcacaf
RS		 3962 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3963 if (q->sec == p->sec)
906e58ca
NC		 3964 {
3965 q->pc_count += p->pc_count;
3966 q->count += p->count;
3967 *pp = p->next;
3968 break;
3969 }
3970 if (q == NULL)
3971 pp = &p->next;
3972 }
0bdcacaf 3973 *pp = edir->dyn_relocs;
906e58ca
NC		 3974 }
3975
0bdcacaf
RS		 3976 edir->dyn_relocs = eind->dyn_relocs;
3977 eind->dyn_relocs = NULL;
906e58ca
NC		 3978 }
3979
3980 if (ind->root.type == bfd_link_hash_indirect)
3981 {
3982 /* Copy over PLT info. */
34e77a92
RS		 3983 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3984 eind->plt.thumb_refcount = 0;
3985 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3986 eind->plt.maybe_thumb_refcount = 0;
3987 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3988 eind->plt.noncall_refcount = 0;
3989
e8b09b87
CL		 3990 /* Copy FDPIC counters. */
3991 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
3992 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
3993 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
3994
34e77a92
RS		 3995 /* We should only allocate a function to .iplt once the final
3996 symbol information is known. */
3997 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3998
3999 if (dir->got.refcount <= 0)
4000 {
4001 edir->tls_type = eind->tls_type;
4002 eind->tls_type = GOT_UNKNOWN;
4003 }
4004 }
4005
4006 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4007}
4008
68faa637
AM		 4009/* Destroy an ARM elf linker hash table. */
4010
4011static void
d495ab0d 4012elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 4013{
4014 struct elf32_arm_link_hash_table *ret
d495ab0d 4015 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 4016
4017 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 4018 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 4019}
4020
906e58ca
NC		 4021/* Create an ARM elf linker hash table. */
4022
4023static struct bfd_link_hash_table *
4024elf32_arm_link_hash_table_create (bfd *abfd)
4025{
4026 struct elf32_arm_link_hash_table *ret;
4027 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
4028
7bf52ea2 4029 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 4030 if (ret == NULL)
4031 return NULL;
4032
4033 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4034 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 4035 sizeof (struct elf32_arm_link_hash_entry),
4036 ARM_ELF_DATA))
906e58ca
NC		 4037 {
4038 free (ret);
4039 return NULL;
4040 }
4041
906e58ca 4042 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 4043 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 4044#ifdef FOUR_WORD_PLT
4045 ret->plt_header_size = 16;
4046 ret->plt_entry_size = 16;
4047#else
4048 ret->plt_header_size = 20;
1db37fe6 4049 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 4050#endif
f3185997 4051 ret->use_rel = TRUE;
906e58ca 4052 ret->obfd = abfd;
617a5ada 4053 ret->fdpic_p = 0;
906e58ca
NC		 4054
4055 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4056 sizeof (struct elf32_arm_stub_hash_entry)))
4057 {
d495ab0d 4058 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 4059 return NULL;
4060 }
d495ab0d 4061 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 4062
4063 return &ret->root.root;
4064}
4065
cd1dac3d
DG		 4066/* Determine what kind of NOPs are available. */
4067
4068static bfd_boolean
4069arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4070{
4071 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4072 Tag_CPU_arch);
cd1dac3d 4073
60a019a0 4074 /* Force return logic to be reviewed for each new architecture. */
bff0500d 4075 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0
TP		 4076
4077 return (arch == TAG_CPU_ARCH_V6T2
4078 || arch == TAG_CPU_ARCH_V6K
4079 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 4080 || arch == TAG_CPU_ARCH_V8
4081 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 4082}
4083
f4ac8484
DJ		 4084static bfd_boolean
4085arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4086{
4087 switch (stub_type)
4088 {
fea2b4d6 4089 case arm_stub_long_branch_thumb_only:
80c135e5 4090 case arm_stub_long_branch_thumb2_only:
d5a67c02 4091 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 4092 case arm_stub_long_branch_v4t_thumb_arm:
4093 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 4094 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 4095 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 4096 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 4097 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 4098 return TRUE;
4099 case arm_stub_none:
4100 BFD_FAIL ();
4101 return FALSE;
4102 break;
4103 default:
4104 return FALSE;
4105 }
4106}
4107
906e58ca
NC		 4108/* Determine the type of stub needed, if any, for a call. */
4109
4110static enum elf32_arm_stub_type
4111arm_type_of_stub (struct bfd_link_info *info,
4112 asection *input_sec,
4113 const Elf_Internal_Rela *rel,
34e77a92 4114 unsigned char st_type,
35fc36a8 4115 enum arm_st_branch_type *actual_branch_type,
906e58ca 4116 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 4117 bfd_vma destination,
4118 asection *sym_sec,
4119 bfd *input_bfd,
4120 const char *name)
906e58ca
NC		 4121{
4122 bfd_vma location;
4123 bfd_signed_vma branch_offset;
4124 unsigned int r_type;
4125 struct elf32_arm_link_hash_table * globals;
5e866f5a 4126 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 4127 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 4128 int use_plt = 0;
35fc36a8 4129 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 4130 union gotplt_union *root_plt;
4131 struct arm_plt_info *arm_plt;
d5a67c02
AV		 4132 int arch;
4133 int thumb2_movw;
906e58ca 4134
35fc36a8 4135 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 4136 return stub_type;
4137
906e58ca 4138 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4139 if (globals == NULL)
4140 return stub_type;
906e58ca
NC		 4141
4142 thumb_only = using_thumb_only (globals);
906e58ca 4143 thumb2 = using_thumb2 (globals);
5e866f5a 4144 thumb2_bl = using_thumb2_bl (globals);
906e58ca 4145
d5a67c02
AV		 4146 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4147
4148 /* True for architectures that implement the thumb2 movw instruction. */
4149 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4150
906e58ca
NC		 4151 /* Determine where the call point is. */
4152 location = (input_sec->output_offset
4153 + input_sec->output_section->vma
4154 + rel->r_offset);
4155
906e58ca
NC		 4156 r_type = ELF32_R_TYPE (rel->r_info);
4157
39f21624
NC		 4158 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4159 are considering a function call relocation. */
c5423981 4160 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 4161 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 4162 && branch_type == ST_BRANCH_TO_ARM)
4163 branch_type = ST_BRANCH_TO_THUMB;
4164
34e77a92
RS		 4165 /* For TLS call relocs, it is the caller's responsibility to provide
4166 the address of the appropriate trampoline. */
4167 if (r_type != R_ARM_TLS_CALL
4168 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 4169 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4170 ELF32_R_SYM (rel->r_info), &root_plt,
4171 &arm_plt)
34e77a92 4172 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 4173 {
34e77a92 4174 asection *splt;
fe33d2fa 4175
34e77a92
RS		 4176 if (hash == NULL || hash->is_iplt)
4177 splt = globals->root.iplt;
4178 else
4179 splt = globals->root.splt;
4180 if (splt != NULL)
b38cadfb 4181 {
34e77a92
RS		 4182 use_plt = 1;
4183
4184 /* Note when dealing with PLT entries: the main PLT stub is in
4185 ARM mode, so if the branch is in Thumb mode, another
4186 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4187 PLT stub. If a long branch stub is needed, we'll add a
4188 Thumb->Arm one and branch directly to the ARM PLT entry.
4189 Here, we have to check if a pre-PLT Thumb->ARM stub
4190 is needed and if it will be close enough. */
34e77a92
RS		 4191
4192 destination = (splt->output_section->vma
4193 + splt->output_offset
4194 + root_plt->offset);
4195 st_type = STT_FUNC;
2df2751d
CL		 4196
4197 /* Thumb branch/call to PLT: it can become a branch to ARM
4198 or to Thumb. We must perform the same checks and
4199 corrections as in elf32_arm_final_link_relocate. */
4200 if ((r_type == R_ARM_THM_CALL)
4201 || (r_type == R_ARM_THM_JUMP24))
4202 {
4203 if (globals->use_blx
4204 && r_type == R_ARM_THM_CALL
4205 && !thumb_only)
4206 {
4207 /* If the Thumb BLX instruction is available, convert
4208 the BL to a BLX instruction to call the ARM-mode
4209 PLT entry. */
4210 branch_type = ST_BRANCH_TO_ARM;
4211 }
4212 else
4213 {
4214 if (!thumb_only)
4215 /* Target the Thumb stub before the ARM PLT entry. */
4216 destination -= PLT_THUMB_STUB_SIZE;
4217 branch_type = ST_BRANCH_TO_THUMB;
4218 }
4219 }
4220 else
4221 {
4222 branch_type = ST_BRANCH_TO_ARM;
4223 }
34e77a92 4224 }
5fa9e92f 4225 }
34e77a92
RS		 4226 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4227 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4228
fe33d2fa
CL		 4229 branch_offset = (bfd_signed_vma)(destination - location);
4230
0855e32b 4231 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4232 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4233 {
5fa9e92f
CL		 4234 /* Handle cases where:
4235 - this call goes too far (different Thumb/Thumb2 max
99059e56 4236 distance)
155d87d7 4237 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4238 Thumb->Arm branch (not bl). A stub is needed in this case,
4239 but only if this call is not through a PLT entry. Indeed,
695344c0 4240 PLT stubs handle mode switching already. */
5e866f5a 4241 if ((!thumb2_bl
906e58ca
NC		 4242 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4243 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4244 || (thumb2_bl
906e58ca
NC		 4245 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4246 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4247 || (thumb2
4248 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4249 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4250 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4251 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4252 && (((r_type == R_ARM_THM_CALL
4253 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4254 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4255 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4256 && !use_plt))
906e58ca 4257 {
2df2751d
CL		 4258 /* If we need to insert a Thumb-Thumb long branch stub to a
4259 PLT, use one that branches directly to the ARM PLT
4260 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4261 stub, undo this now. */
695344c0
NC		 4262 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4263 {
4264 branch_type = ST_BRANCH_TO_ARM;
4265 branch_offset += PLT_THUMB_STUB_SIZE;
4266 }
2df2751d 4267
35fc36a8 4268 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4269 {
4270 /* Thumb to thumb. */
4271 if (!thumb_only)
4272 {
d5a67c02 4273 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4274 _bfd_error_handler
871b3ab2 4275 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4276 " section with SHF_ARM_PURECODE section"
4277 " attribute is only supported for M-profile"
90b6238f 4278 " targets that implement the movw instruction"),
10463f39 4279 input_bfd, input_sec);
d5a67c02 4280
0e1862bb 4281 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4282 /* PIC stubs. */
155d87d7 4283 ? ((globals->use_blx
9553db3c 4284 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4285 /* V5T and above. Stub starts with ARM code, so
4286 we must be able to switch mode before
4287 reaching it, which is only possible for 'bl'
4288 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4289 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4290 /* On V4T, use Thumb code only. */
d3626fb0 4291 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4292
4293 /* non-PIC stubs. */
155d87d7 4294 : ((globals->use_blx
9553db3c 4295 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4296 /* V5T and above. */
4297 ? arm_stub_long_branch_any_any
4298 /* V4T. */
d3626fb0 4299 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4300 }
4301 else
4302 {
d5a67c02
AV		 4303 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4304 stub_type = arm_stub_long_branch_thumb2_only_pure;
4305 else
4306 {
4307 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4308 _bfd_error_handler
871b3ab2 4309 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4310 " section with SHF_ARM_PURECODE section"
4311 " attribute is only supported for M-profile"
90b6238f 4312 " targets that implement the movw instruction"),
10463f39 4313 input_bfd, input_sec);
d5a67c02
AV		 4314
4315 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4316 /* PIC stub. */
4317 ? arm_stub_long_branch_thumb_only_pic
4318 /* non-PIC stub. */
4319 : (thumb2 ? arm_stub_long_branch_thumb2_only
4320 : arm_stub_long_branch_thumb_only);
4321 }
906e58ca
NC		 4322 }
4323 }
4324 else
4325 {
d5a67c02 4326 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4327 _bfd_error_handler
871b3ab2 4328 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4329 " section with SHF_ARM_PURECODE section"
4330 " attribute is only supported" " for M-profile"
90b6238f 4331 " targets that implement the movw instruction"),
10463f39 4332 input_bfd, input_sec);
d5a67c02 4333
906e58ca 4334 /* Thumb to arm. */
c820be07
NC		 4335 if (sym_sec != NULL
4336 && sym_sec->owner != NULL
4337 && !INTERWORK_FLAG (sym_sec->owner))
4338 {
4eca0228 4339 _bfd_error_handler
90b6238f
AM		 4340 (_("%pB(%s): warning: interworking not enabled;"
4341 " first occurrence: %pB: %s call to %s"),
4342 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4343 }
4344
0855e32b 4345 stub_type =
0e1862bb 4346 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4347 /* PIC stubs. */
0855e32b 4348 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4349 /* TLS PIC stubs. */
0855e32b
NS		 4350 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4351 : arm_stub_long_branch_v4t_thumb_tls_pic)
4352 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4353 /* V5T PIC and above. */
4354 ? arm_stub_long_branch_any_arm_pic
4355 /* V4T PIC stub. */
4356 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4357
4358 /* non-PIC stubs. */
0855e32b 4359 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4360 /* V5T and above. */
4361 ? arm_stub_long_branch_any_any
4362 /* V4T. */
4363 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4364
4365 /* Handle v4t short branches. */
fea2b4d6 4366 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4367 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4368 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4369 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4370 }
4371 }
4372 }
fe33d2fa
CL		 4373 else if (r_type == R_ARM_CALL
4374 || r_type == R_ARM_JUMP24
0855e32b
NS		 4375 || r_type == R_ARM_PLT32
4376 || r_type == R_ARM_TLS_CALL)
906e58ca 4377 {
d5a67c02 4378 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4379 _bfd_error_handler
871b3ab2 4380 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4381 " section with SHF_ARM_PURECODE section"
4382 " attribute is only supported for M-profile"
90b6238f 4383 " targets that implement the movw instruction"),
10463f39 4384 input_bfd, input_sec);
35fc36a8 4385 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4386 {
4387 /* Arm to thumb. */
c820be07
NC		 4388
4389 if (sym_sec != NULL
4390 && sym_sec->owner != NULL
4391 && !INTERWORK_FLAG (sym_sec->owner))
4392 {
4eca0228 4393 _bfd_error_handler
90b6238f
AM		 4394 (_("%pB(%s): warning: interworking not enabled;"
4395 " first occurrence: %pB: %s call to %s"),
4396 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4397 }
4398
4399 /* We have an extra 2-bytes reach because of
4400 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4401 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4402 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4403 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4404 || (r_type == R_ARM_JUMP24)
4405 || (r_type == R_ARM_PLT32))
906e58ca 4406 {
0e1862bb 4407 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4408 /* PIC stubs. */
ebe24dd4
CL		 4409 ? ((globals->use_blx)
4410 /* V5T and above. */
4411 ? arm_stub_long_branch_any_thumb_pic
4412 /* V4T stub. */
4413 : arm_stub_long_branch_v4t_arm_thumb_pic)
4414
c2b4a39d
CL		 4415 /* non-PIC stubs. */
4416 : ((globals->use_blx)
4417 /* V5T and above. */
4418 ? arm_stub_long_branch_any_any
4419 /* V4T. */
4420 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4421 }
4422 }
4423 else
4424 {
4425 /* Arm to arm. */
4426 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4427 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4428 {
0855e32b 4429 stub_type =
0e1862bb 4430 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4431 /* PIC stubs. */
0855e32b 4432 ? (r_type == R_ARM_TLS_CALL
6a631e86 4433 /* TLS PIC Stub. */
0855e32b 4434 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4435 : (globals->nacl_p
4436 ? arm_stub_long_branch_arm_nacl_pic
4437 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4438 /* non-PIC stubs. */
7a89b94e
NC		 4439 : (globals->nacl_p
4440 ? arm_stub_long_branch_arm_nacl
4441 : arm_stub_long_branch_any_any);
906e58ca
NC		 4442 }
4443 }
4444 }
4445
fe33d2fa
CL		 4446 /* If a stub is needed, record the actual destination type. */
4447 if (stub_type != arm_stub_none)
35fc36a8 4448 *actual_branch_type = branch_type;
fe33d2fa 4449
906e58ca
NC		 4450 return stub_type;
4451}
4452
4453/* Build a name for an entry in the stub hash table. */
4454
4455static char *
4456elf32_arm_stub_name (const asection *input_section,
4457 const asection *sym_sec,
4458 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4459 const Elf_Internal_Rela *rel,
4460 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4461{
4462 char *stub_name;
4463 bfd_size_type len;
4464
4465 if (hash)
4466 {
fe33d2fa 4467 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4468 stub_name = (char *) bfd_malloc (len);
906e58ca 4469 if (stub_name != NULL)
fe33d2fa 4470 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4471 input_section->id & 0xffffffff,
4472 hash->root.root.root.string,
fe33d2fa
CL		 4473 (int) rel->r_addend & 0xffffffff,
4474 (int) stub_type);
906e58ca
NC		 4475 }
4476 else
4477 {
fe33d2fa 4478 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4479 stub_name = (char *) bfd_malloc (len);
906e58ca 4480 if (stub_name != NULL)
fe33d2fa 4481 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4482 input_section->id & 0xffffffff,
4483 sym_sec->id & 0xffffffff,
0855e32b
NS		 4484 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4485 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4486 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4487 (int) rel->r_addend & 0xffffffff,
4488 (int) stub_type);
906e58ca
NC		 4489 }
4490
4491 return stub_name;
4492}
4493
4494/* Look up an entry in the stub hash. Stub entries are cached because
4495 creating the stub name takes a bit of time. */
4496
4497static struct elf32_arm_stub_hash_entry *
4498elf32_arm_get_stub_entry (const asection *input_section,
4499 const asection *sym_sec,
4500 struct elf_link_hash_entry *hash,
4501 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4502 struct elf32_arm_link_hash_table *htab,
4503 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4504{
4505 struct elf32_arm_stub_hash_entry *stub_entry;
4506 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4507 const asection *id_sec;
4508
4509 if ((input_section->flags & SEC_CODE) == 0)
4510 return NULL;
4511
4512 /* If this input section is part of a group of sections sharing one
4513 stub section, then use the id of the first section in the group.
4514 Stub names need to include a section id, as there may well be
4515 more than one stub used to reach say, printf, and we need to
4516 distinguish between them. */
c2abbbeb 4517 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4518 id_sec = htab->stub_group[input_section->id].link_sec;
4519
4520 if (h != NULL && h->stub_cache != NULL
4521 && h->stub_cache->h == h
fe33d2fa
CL		 4522 && h->stub_cache->id_sec == id_sec
4523 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4524 {
4525 stub_entry = h->stub_cache;
4526 }
4527 else
4528 {
4529 char *stub_name;
4530
fe33d2fa 4531 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4532 if (stub_name == NULL)
4533 return NULL;
4534
4535 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4536 stub_name, FALSE, FALSE);
4537 if (h != NULL)
4538 h->stub_cache = stub_entry;
4539
4540 free (stub_name);
4541 }
4542
4543 return stub_entry;
4544}
4545
daa4adae
TP		 4546/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4547 section. */
4548
4549static bfd_boolean
4550arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4551{
4552 if (stub_type >= max_stub_type)
4553 abort (); /* Should be unreachable. */
4554
4ba2ef8f
TP		 4555 switch (stub_type)
4556 {
4557 case arm_stub_cmse_branch_thumb_only:
4558 return TRUE;
4559
4560 default:
4561 return FALSE;
4562 }
4563
4564 abort (); /* Should be unreachable. */
daa4adae
TP		 4565}
4566
4567/* Required alignment (as a power of 2) for the dedicated section holding
4568 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4569 with input sections. */
4570
4571static int
4572arm_dedicated_stub_output_section_required_alignment
4573 (enum elf32_arm_stub_type stub_type)
4574{
4575 if (stub_type >= max_stub_type)
4576 abort (); /* Should be unreachable. */
4577
4ba2ef8f
TP		 4578 switch (stub_type)
4579 {
4580 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4581 boundary. */
4582 case arm_stub_cmse_branch_thumb_only:
4583 return 5;
4584
4585 default:
4586 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4587 return 0;
4588 }
4589
4590 abort (); /* Should be unreachable. */
daa4adae
TP		 4591}
4592
4593/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4594 NULL if veneers of this type are interspersed with input sections. */
4595
4596static const char *
4597arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4598{
4599 if (stub_type >= max_stub_type)
4600 abort (); /* Should be unreachable. */
4601
4ba2ef8f
TP		 4602 switch (stub_type)
4603 {
4604 case arm_stub_cmse_branch_thumb_only:
4605 return ".gnu.sgstubs";
4606
4607 default:
4608 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4609 return NULL;
4610 }
4611
4612 abort (); /* Should be unreachable. */
daa4adae
TP		 4613}
4614
4615/* If veneers of type STUB_TYPE should go in a dedicated output section,
4616 returns the address of the hash table field in HTAB holding a pointer to the
4617 corresponding input section. Otherwise, returns NULL. */
4618
4619static asection **
4ba2ef8f
TP		 4620arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4621 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4622{
4623 if (stub_type >= max_stub_type)
4624 abort (); /* Should be unreachable. */
4625
4ba2ef8f
TP		 4626 switch (stub_type)
4627 {
4628 case arm_stub_cmse_branch_thumb_only:
4629 return &htab->cmse_stub_sec;
4630
4631 default:
4632 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4633 return NULL;
4634 }
4635
4636 abort (); /* Should be unreachable. */
daa4adae
TP		 4637}
4638
4639/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4640 is the section that branch into veneer and can be NULL if stub should go in
4641 a dedicated output section. Returns a pointer to the stub section, and the
4642 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4643 LINK_SEC_P may be NULL. */
906e58ca 4644
48229727
JB		 4645static asection *
4646elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4647 struct elf32_arm_link_hash_table *htab,
4648 enum elf32_arm_stub_type stub_type)
906e58ca 4649{
daa4adae
TP		 4650 asection *link_sec, *out_sec, **stub_sec_p;
4651 const char *stub_sec_prefix;
4652 bfd_boolean dedicated_output_section =
4653 arm_dedicated_stub_output_section_required (stub_type);
4654 int align;
906e58ca 4655
daa4adae 4656 if (dedicated_output_section)
906e58ca 4657 {
daa4adae
TP		 4658 bfd *output_bfd = htab->obfd;
4659 const char *out_sec_name =
4660 arm_dedicated_stub_output_section_name (stub_type);
4661 link_sec = NULL;
4662 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4663 stub_sec_prefix = out_sec_name;
4664 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4665 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4666 if (out_sec == NULL)
906e58ca 4667 {
90b6238f 4668 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4669 "section %s"), out_sec_name);
daa4adae 4670 return NULL;
906e58ca 4671 }
daa4adae
TP		 4672 }
4673 else
4674 {
c2abbbeb 4675 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4676 link_sec = htab->stub_group[section->id].link_sec;
4677 BFD_ASSERT (link_sec != NULL);
4678 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4679 if (*stub_sec_p == NULL)
4680 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4681 stub_sec_prefix = link_sec->name;
4682 out_sec = link_sec->output_section;
4683 align = htab->nacl_p ? 4 : 3;
906e58ca 4684 }
b38cadfb 4685
daa4adae
TP		 4686 if (*stub_sec_p == NULL)
4687 {
4688 size_t namelen;
4689 bfd_size_type len;
4690 char *s_name;
4691
4692 namelen = strlen (stub_sec_prefix);
4693 len = namelen + sizeof (STUB_SUFFIX);
4694 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4695 if (s_name == NULL)
4696 return NULL;
4697
4698 memcpy (s_name, stub_sec_prefix, namelen);
4699 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4700 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4701 align);
4702 if (*stub_sec_p == NULL)
4703 return NULL;
4704
4705 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4706 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4707 | SEC_KEEP;
4708 }
4709
4710 if (!dedicated_output_section)
4711 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4712
48229727
JB		 4713 if (link_sec_p)
4714 *link_sec_p = link_sec;
b38cadfb 4715
daa4adae 4716 return *stub_sec_p;
48229727
JB		 4717}
4718
4719/* Add a new stub entry to the stub hash. Not all fields of the new
4720 stub entry are initialised. */
4721
4722static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4723elf32_arm_add_stub (const char *stub_name, asection *section,
4724 struct elf32_arm_link_hash_table *htab,
4725 enum elf32_arm_stub_type stub_type)
48229727
JB		 4726{
4727 asection *link_sec;
4728 asection *stub_sec;
4729 struct elf32_arm_stub_hash_entry *stub_entry;
4730
daa4adae
TP		 4731 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4732 stub_type);
48229727
JB		 4733 if (stub_sec == NULL)
4734 return NULL;
906e58ca
NC		 4735
4736 /* Enter this entry into the linker stub hash table. */
4737 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4738 TRUE, FALSE);
4739 if (stub_entry == NULL)
4740 {
6bde4c52
TP		 4741 if (section == NULL)
4742 section = stub_sec;
871b3ab2 4743 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4744 section->owner, stub_name);
906e58ca
NC		 4745 return NULL;
4746 }
4747
4748 stub_entry->stub_sec = stub_sec;
0955507f 4749 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4750 stub_entry->id_sec = link_sec;
4751
906e58ca
NC		 4752 return stub_entry;
4753}
4754
4755/* Store an Arm insn into an output section not processed by
4756 elf32_arm_write_section. */
4757
4758static void
8029a119
NC		 4759put_arm_insn (struct elf32_arm_link_hash_table * htab,
4760 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4761{
4762 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4763 bfd_putl32 (val, ptr);
4764 else
4765 bfd_putb32 (val, ptr);
4766}
4767
4768/* Store a 16-bit Thumb insn into an output section not processed by
4769 elf32_arm_write_section. */
4770
4771static void
8029a119
NC		 4772put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4773 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4774{
4775 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4776 bfd_putl16 (val, ptr);
4777 else
4778 bfd_putb16 (val, ptr);
4779}
4780
a504d23a
LA		 4781/* Store a Thumb2 insn into an output section not processed by
4782 elf32_arm_write_section. */
4783
4784static void
4785put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4786 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4787{
4788 /* T2 instructions are 16-bit streamed. */
4789 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4790 {
4791 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4792 bfd_putl16 ((val & 0xffff), ptr + 2);
4793 }
4794 else
4795 {
4796 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4797 bfd_putb16 ((val & 0xffff), ptr + 2);
4798 }
4799}
4800
0855e32b
NS		 4801/* If it's possible to change R_TYPE to a more efficient access
4802 model, return the new reloc type. */
4803
4804static unsigned
b38cadfb 4805elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4806 struct elf_link_hash_entry *h)
4807{
4808 int is_local = (h == NULL);
4809
0e1862bb
L		 4810 if (bfd_link_pic (info)
4811 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4812 return r_type;
4813
b38cadfb 4814 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4815 switch (r_type)
4816 {
4817 case R_ARM_TLS_GOTDESC:
4818 case R_ARM_TLS_CALL:
4819 case R_ARM_THM_TLS_CALL:
4820 case R_ARM_TLS_DESCSEQ:
4821 case R_ARM_THM_TLS_DESCSEQ:
4822 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4823 }
4824
4825 return r_type;
4826}
4827
48229727
JB		 4828static bfd_reloc_status_type elf32_arm_final_link_relocate
4829 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4830 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4831 const char *, unsigned char, enum arm_st_branch_type,
4832 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4833
4563a860
JB		 4834static unsigned int
4835arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4836{
4837 switch (stub_type)
4838 {
4839 case arm_stub_a8_veneer_b_cond:
4840 case arm_stub_a8_veneer_b:
4841 case arm_stub_a8_veneer_bl:
4842 return 2;
4843
4844 case arm_stub_long_branch_any_any:
4845 case arm_stub_long_branch_v4t_arm_thumb:
4846 case arm_stub_long_branch_thumb_only:
80c135e5 4847 case arm_stub_long_branch_thumb2_only:
d5a67c02 4848 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4849 case arm_stub_long_branch_v4t_thumb_thumb:
4850 case arm_stub_long_branch_v4t_thumb_arm:
4851 case arm_stub_short_branch_v4t_thumb_arm:
4852 case arm_stub_long_branch_any_arm_pic:
4853 case arm_stub_long_branch_any_thumb_pic:
4854 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4855 case arm_stub_long_branch_v4t_arm_thumb_pic:
4856 case arm_stub_long_branch_v4t_thumb_arm_pic:
4857 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4858 case arm_stub_long_branch_any_tls_pic:
4859 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4860 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4861 case arm_stub_a8_veneer_blx:
4862 return 4;
b38cadfb 4863
7a89b94e
NC		 4864 case arm_stub_long_branch_arm_nacl:
4865 case arm_stub_long_branch_arm_nacl_pic:
4866 return 16;
4867
4563a860
JB		 4868 default:
4869 abort (); /* Should be unreachable. */
4870 }
4871}
4872
4f4faa4d
TP		 4873/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4874 veneering (TRUE) or have their own symbol (FALSE). */
4875
4876static bfd_boolean
4877arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4878{
4879 if (stub_type >= max_stub_type)
4880 abort (); /* Should be unreachable. */
4881
4ba2ef8f
TP		 4882 switch (stub_type)
4883 {
4884 case arm_stub_cmse_branch_thumb_only:
4885 return TRUE;
4886
4887 default:
4888 return FALSE;
4889 }
4890
4891 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4892}
4893
d7c5bd02
TP		 4894/* Returns the padding needed for the dedicated section used stubs of type
4895 STUB_TYPE. */
4896
4897static int
4898arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4899{
4900 if (stub_type >= max_stub_type)
4901 abort (); /* Should be unreachable. */
4902
4ba2ef8f
TP		 4903 switch (stub_type)
4904 {
4905 case arm_stub_cmse_branch_thumb_only:
4906 return 32;
4907
4908 default:
4909 return 0;
4910 }
4911
4912 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4913}
4914
0955507f
TP		 4915/* If veneers of type STUB_TYPE should go in a dedicated output section,
4916 returns the address of the hash table field in HTAB holding the offset at
4917 which new veneers should be layed out in the stub section. */
4918
4919static bfd_vma*
4920arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4921 enum elf32_arm_stub_type stub_type)
4922{
4923 switch (stub_type)
4924 {
4925 case arm_stub_cmse_branch_thumb_only:
4926 return &htab->new_cmse_stub_offset;
4927
4928 default:
4929 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4930 return NULL;
4931 }
4932}
4933
906e58ca
NC		 4934static bfd_boolean
4935arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4936 void * in_arg)
4937{
7a89b94e 4938#define MAXRELOCS 3
0955507f 4939 bfd_boolean removed_sg_veneer;
906e58ca 4940 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4941 struct elf32_arm_link_hash_table *globals;
906e58ca 4942 struct bfd_link_info *info;
906e58ca
NC		 4943 asection *stub_sec;
4944 bfd *stub_bfd;
906e58ca
NC		 4945 bfd_byte *loc;
4946 bfd_vma sym_value;
4947 int template_size;
4948 int size;
d3ce72d0 4949 const insn_sequence *template_sequence;
906e58ca 4950 int i;
48229727
JB		 4951 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4952 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4953 int nrelocs = 0;
0955507f 4954 int just_allocated = 0;
906e58ca
NC		 4955
4956 /* Massage our args to the form they really have. */
4957 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4958 info = (struct bfd_link_info *) in_arg;
4959
4960 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4961 if (globals == NULL)
4962 return FALSE;
906e58ca 4963
906e58ca
NC		 4964 stub_sec = stub_entry->stub_sec;
4965
4dfe6ac6 4966 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4967 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4968 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4969 return TRUE;
fe33d2fa 4970
0955507f
TP		 4971 /* Assign a slot at the end of section if none assigned yet. */
4972 if (stub_entry->stub_offset == (bfd_vma) -1)
4973 {
4974 stub_entry->stub_offset = stub_sec->size;
4975 just_allocated = 1;
4976 }
906e58ca
NC		 4977 loc = stub_sec->contents + stub_entry->stub_offset;
4978
4979 stub_bfd = stub_sec->owner;
4980
906e58ca
NC		 4981 /* This is the address of the stub destination. */
4982 sym_value = (stub_entry->target_value
4983 + stub_entry->target_section->output_offset
4984 + stub_entry->target_section->output_section->vma);
4985
d3ce72d0 4986 template_sequence = stub_entry->stub_template;
461a49ca 4987 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4988
4989 size = 0;
461a49ca 4990 for (i = 0; i < template_size; i++)
906e58ca 4991 {
d3ce72d0 4992 switch (template_sequence[i].type)
461a49ca
DJ		 4993 {
4994 case THUMB16_TYPE:
48229727 4995 {
d3ce72d0
NC		 4996 bfd_vma data = (bfd_vma) template_sequence[i].data;
4997 if (template_sequence[i].reloc_addend != 0)
48229727 4998 {
99059e56
RM		 4999 /* We've borrowed the reloc_addend field to mean we should
5000 insert a condition code into this (Thumb-1 branch)
5001 instruction. See THUMB16_BCOND_INSN. */
5002 BFD_ASSERT ((data & 0xff00) == 0xd000);
5003 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 5004 }
fe33d2fa 5005 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 5006 size += 2;
5007 }
461a49ca 5008 break;
906e58ca 5009
48229727 5010 case THUMB32_TYPE:
fe33d2fa
CL		 5011 bfd_put_16 (stub_bfd,
5012 (template_sequence[i].data >> 16) & 0xffff,
5013 loc + size);
5014 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5015 loc + size + 2);
99059e56
RM		 5016 if (template_sequence[i].r_type != R_ARM_NONE)
5017 {
5018 stub_reloc_idx[nrelocs] = i;
5019 stub_reloc_offset[nrelocs++] = size;
5020 }
5021 size += 4;
5022 break;
48229727 5023
461a49ca 5024 case ARM_TYPE:
fe33d2fa
CL		 5025 bfd_put_32 (stub_bfd, template_sequence[i].data,
5026 loc + size);
461a49ca
DJ		 5027 /* Handle cases where the target is encoded within the
5028 instruction. */
d3ce72d0 5029 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 5030 {
48229727
JB		 5031 stub_reloc_idx[nrelocs] = i;
5032 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5033 }
5034 size += 4;
5035 break;
5036
5037 case DATA_TYPE:
d3ce72d0 5038 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 5039 stub_reloc_idx[nrelocs] = i;
5040 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5041 size += 4;
5042 break;
5043
5044 default:
5045 BFD_FAIL ();
5046 return FALSE;
5047 }
906e58ca 5048 }
461a49ca 5049
0955507f
TP		 5050 if (just_allocated)
5051 stub_sec->size += size;
906e58ca 5052
461a49ca
DJ		 5053 /* Stub size has already been computed in arm_size_one_stub. Check
5054 consistency. */
5055 BFD_ASSERT (size == stub_entry->stub_size);
5056
906e58ca 5057 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 5058 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 5059 sym_value |= 1;
5060
0955507f
TP		 5061 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5062 to relocate in each stub. */
5063 removed_sg_veneer =
5064 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5065 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 5066
48229727 5067 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 5068 {
5069 Elf_Internal_Rela rel;
5070 bfd_boolean unresolved_reloc;
5071 char *error_message;
5072 bfd_vma points_to =
5073 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5074
5075 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5076 rel.r_info = ELF32_R_INFO (0,
5077 template_sequence[stub_reloc_idx[i]].r_type);
5078 rel.r_addend = 0;
5079
5080 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5081 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5082 template should refer back to the instruction after the original
5083 branch. We use target_section as Cortex-A8 erratum workaround stubs
5084 are only generated when both source and target are in the same
5085 section. */
5086 points_to = stub_entry->target_section->output_section->vma
5087 + stub_entry->target_section->output_offset
5088 + stub_entry->source_value;
5089
5090 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5091 (template_sequence[stub_reloc_idx[i]].r_type),
5092 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5093 points_to, info, stub_entry->target_section, "", STT_FUNC,
5094 stub_entry->branch_type,
5095 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5096 &error_message);
5097 }
906e58ca
NC		 5098
5099 return TRUE;
48229727 5100#undef MAXRELOCS
906e58ca
NC		 5101}
5102
48229727
JB		 5103/* Calculate the template, template size and instruction size for a stub.
5104 Return value is the instruction size. */
906e58ca 5105
48229727
JB		 5106static unsigned int
5107find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5108 const insn_sequence **stub_template,
5109 int *stub_template_size)
906e58ca 5110{
d3ce72d0 5111 const insn_sequence *template_sequence = NULL;
48229727
JB		 5112 int template_size = 0, i;
5113 unsigned int size;
906e58ca 5114
d3ce72d0 5115 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 5116 if (stub_template)
5117 *stub_template = template_sequence;
5118
48229727 5119 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 5120 if (stub_template_size)
5121 *stub_template_size = template_size;
906e58ca
NC		 5122
5123 size = 0;
461a49ca
DJ		 5124 for (i = 0; i < template_size; i++)
5125 {
d3ce72d0 5126 switch (template_sequence[i].type)
461a49ca
DJ		 5127 {
5128 case THUMB16_TYPE:
5129 size += 2;
5130 break;
5131
5132 case ARM_TYPE:
48229727 5133 case THUMB32_TYPE:
461a49ca
DJ		 5134 case DATA_TYPE:
5135 size += 4;
5136 break;
5137
5138 default:
5139 BFD_FAIL ();
2a229407 5140 return 0;
461a49ca
DJ		 5141 }
5142 }
5143
48229727
JB		 5144 return size;
5145}
5146
5147/* As above, but don't actually build the stub. Just bump offset so
5148 we know stub section sizes. */
5149
5150static bfd_boolean
5151arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 5152 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 5153{
5154 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 5155 const insn_sequence *template_sequence;
48229727
JB		 5156 int template_size, size;
5157
5158 /* Massage our args to the form they really have. */
5159 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 5160
5161 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
5162 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
5163
d3ce72d0 5164 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 5165 &template_size);
5166
0955507f
TP		 5167 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5168 if (stub_entry->stub_template_size)
5169 {
5170 stub_entry->stub_size = size;
5171 stub_entry->stub_template = template_sequence;
5172 stub_entry->stub_template_size = template_size;
5173 }
5174
5175 /* Already accounted for. */
5176 if (stub_entry->stub_offset != (bfd_vma) -1)
5177 return TRUE;
461a49ca 5178
906e58ca
NC		 5179 size = (size + 7) & ~7;
5180 stub_entry->stub_sec->size += size;
461a49ca 5181
906e58ca
NC		 5182 return TRUE;
5183}
5184
5185/* External entry points for sizing and building linker stubs. */
5186
5187/* Set up various things so that we can make a list of input sections
5188 for each output section included in the link. Returns -1 on error,
5189 0 when no stubs will be needed, and 1 on success. */
5190
5191int
5192elf32_arm_setup_section_lists (bfd *output_bfd,
5193 struct bfd_link_info *info)
5194{
5195 bfd *input_bfd;
5196 unsigned int bfd_count;
7292b3ac 5197 unsigned int top_id, top_index;
906e58ca
NC		 5198 asection *section;
5199 asection **input_list, **list;
5200 bfd_size_type amt;
5201 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5202
4dfe6ac6
NC		 5203 if (htab == NULL)
5204 return 0;
906e58ca
NC		 5205 if (! is_elf_hash_table (htab))
5206 return 0;
5207
5208 /* Count the number of input BFDs and find the top input section id. */
5209 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5210 input_bfd != NULL;
c72f2fb2 5211 input_bfd = input_bfd->link.next)
906e58ca
NC		 5212 {
5213 bfd_count += 1;
5214 for (section = input_bfd->sections;
5215 section != NULL;
5216 section = section->next)
5217 {
5218 if (top_id < section->id)
5219 top_id = section->id;
5220 }
5221 }
5222 htab->bfd_count = bfd_count;
5223
5224 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5225 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5226 if (htab->stub_group == NULL)
5227 return -1;
fe33d2fa 5228 htab->top_id = top_id;
906e58ca
NC		 5229
5230 /* We can't use output_bfd->section_count here to find the top output
5231 section index as some sections may have been removed, and
5232 _bfd_strip_section_from_output doesn't renumber the indices. */
5233 for (section = output_bfd->sections, top_index = 0;
5234 section != NULL;
5235 section = section->next)
5236 {
5237 if (top_index < section->index)
5238 top_index = section->index;
5239 }
5240
5241 htab->top_index = top_index;
5242 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5243 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5244 htab->input_list = input_list;
5245 if (input_list == NULL)
5246 return -1;
5247
5248 /* For sections we aren't interested in, mark their entries with a
5249 value we can check later. */
5250 list = input_list + top_index;
5251 do
5252 *list = bfd_abs_section_ptr;
5253 while (list-- != input_list);
5254
5255 for (section = output_bfd->sections;
5256 section != NULL;
5257 section = section->next)
5258 {
5259 if ((section->flags & SEC_CODE) != 0)
5260 input_list[section->index] = NULL;
5261 }
5262
5263 return 1;
5264}
5265
5266/* The linker repeatedly calls this function for each input section,
5267 in the order that input sections are linked into output sections.
5268 Build lists of input sections to determine groupings between which
5269 we may insert linker stubs. */
5270
5271void
5272elf32_arm_next_input_section (struct bfd_link_info *info,
5273 asection *isec)
5274{
5275 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5276
4dfe6ac6
NC		 5277 if (htab == NULL)
5278 return;
5279
906e58ca
NC		 5280 if (isec->output_section->index <= htab->top_index)
5281 {
5282 asection **list = htab->input_list + isec->output_section->index;
5283
a7470592 5284 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5285 {
5286 /* Steal the link_sec pointer for our list. */
5287#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5288 /* This happens to make the list in reverse order,
07d72278 5289 which we reverse later. */
906e58ca
NC		 5290 PREV_SEC (isec) = *list;
5291 *list = isec;
5292 }
5293 }
5294}
5295
5296/* See whether we can group stub sections together. Grouping stub
5297 sections may result in fewer stubs. More importantly, we need to
07d72278 5298 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5299 .fini output sections respectively, because glibc splits the
5300 _init and _fini functions into multiple parts. Putting a stub in
5301 the middle of a function is not a good idea. */
5302
5303static void
5304group_sections (struct elf32_arm_link_hash_table *htab,
5305 bfd_size_type stub_group_size,
07d72278 5306 bfd_boolean stubs_always_after_branch)
906e58ca 5307{
07d72278 5308 asection **list = htab->input_list;
906e58ca
NC		 5309
5310 do
5311 {
5312 asection *tail = *list;
07d72278 5313 asection *head;
906e58ca
NC		 5314
5315 if (tail == bfd_abs_section_ptr)
5316 continue;
5317
07d72278
DJ		 5318 /* Reverse the list: we must avoid placing stubs at the
5319 beginning of the section because the beginning of the text
5320 section may be required for an interrupt vector in bare metal
5321 code. */
5322#define NEXT_SEC PREV_SEC
e780aef2
CL		 5323 head = NULL;
5324 while (tail != NULL)
99059e56
RM		 5325 {
5326 /* Pop from tail. */
5327 asection *item = tail;
5328 tail = PREV_SEC (item);
e780aef2 5329
99059e56
RM		 5330 /* Push on head. */
5331 NEXT_SEC (item) = head;
5332 head = item;
5333 }
07d72278
DJ		 5334
5335 while (head != NULL)
906e58ca
NC		 5336 {
5337 asection *curr;
07d72278 5338 asection *next;
e780aef2
CL		 5339 bfd_vma stub_group_start = head->output_offset;
5340 bfd_vma end_of_next;
906e58ca 5341
07d72278 5342 curr = head;
e780aef2 5343 while (NEXT_SEC (curr) != NULL)
8cd931b7 5344 {
e780aef2
CL		 5345 next = NEXT_SEC (curr);
5346 end_of_next = next->output_offset + next->size;
5347 if (end_of_next - stub_group_start >= stub_group_size)
5348 /* End of NEXT is too far from start, so stop. */
8cd931b7 5349 break;
e780aef2
CL		 5350 /* Add NEXT to the group. */
5351 curr = next;
8cd931b7 5352 }
906e58ca 5353
07d72278 5354 /* OK, the size from the start to the start of CURR is less
906e58ca 5355 than stub_group_size and thus can be handled by one stub
07d72278 5356 section. (Or the head section is itself larger than
906e58ca
NC		 5357 stub_group_size, in which case we may be toast.)
5358 We should really be keeping track of the total size of
5359 stubs added here, as stubs contribute to the final output
7fb9f789 5360 section size. */
906e58ca
NC		 5361 do
5362 {
07d72278 5363 next = NEXT_SEC (head);
906e58ca 5364 /* Set up this stub group. */
07d72278 5365 htab->stub_group[head->id].link_sec = curr;
906e58ca 5366 }
07d72278 5367 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5368
5369 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5370 bytes after the stub section can be handled by it too. */
5371 if (!stubs_always_after_branch)
906e58ca 5372 {
e780aef2
CL		 5373 stub_group_start = curr->output_offset + curr->size;
5374
8cd931b7 5375 while (next != NULL)
906e58ca 5376 {
e780aef2
CL		 5377 end_of_next = next->output_offset + next->size;
5378 if (end_of_next - stub_group_start >= stub_group_size)
5379 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5380 break;
e780aef2 5381 /* Add NEXT to the stub group. */
07d72278
DJ		 5382 head = next;
5383 next = NEXT_SEC (head);
5384 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5385 }
5386 }
07d72278 5387 head = next;
906e58ca
NC		 5388 }
5389 }
07d72278 5390 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5391
5392 free (htab->input_list);
5393#undef PREV_SEC
07d72278 5394#undef NEXT_SEC
906e58ca
NC		 5395}
5396
48229727
JB		 5397/* Comparison function for sorting/searching relocations relating to Cortex-A8
5398 erratum fix. */
5399
5400static int
5401a8_reloc_compare (const void *a, const void *b)
5402{
21d799b5
NC		 5403 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5404 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5405
5406 if (ra->from < rb->from)
5407 return -1;
5408 else if (ra->from > rb->from)
5409 return 1;
5410 else
5411 return 0;
5412}
5413
5414static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5415 const char *, char **);
5416
5417/* Helper function to scan code for sequences which might trigger the Cortex-A8
5418 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5419 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5420 otherwise. */
5421
81694485
NC		 5422static bfd_boolean
5423cortex_a8_erratum_scan (bfd *input_bfd,
5424 struct bfd_link_info *info,
48229727
JB		 5425 struct a8_erratum_fix **a8_fixes_p,
5426 unsigned int *num_a8_fixes_p,
5427 unsigned int *a8_fix_table_size_p,
5428 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5429 unsigned int num_a8_relocs,
5430 unsigned prev_num_a8_fixes,
5431 bfd_boolean *stub_changed_p)
48229727
JB		 5432{
5433 asection *section;
5434 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5435 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5436 unsigned int num_a8_fixes = *num_a8_fixes_p;
5437 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5438
4dfe6ac6
NC		 5439 if (htab == NULL)
5440 return FALSE;
5441
48229727
JB		 5442 for (section = input_bfd->sections;
5443 section != NULL;
5444 section = section->next)
5445 {
5446 bfd_byte *contents = NULL;
5447 struct _arm_elf_section_data *sec_data;
5448 unsigned int span;
5449 bfd_vma base_vma;
5450
5451 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5452 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5453 || (section->flags & SEC_EXCLUDE) != 0
5454 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5455 || (section->output_section == bfd_abs_section_ptr))
5456 continue;
48229727
JB		 5457
5458 base_vma = section->output_section->vma + section->output_offset;
5459
5460 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5461 contents = elf_section_data (section)->this_hdr.contents;
48229727 5462 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5463 return TRUE;
48229727
JB		 5464
5465 sec_data = elf32_arm_section_data (section);
5466
5467 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5468 {
5469 unsigned int span_start = sec_data->map[span].vma;
5470 unsigned int span_end = (span == sec_data->mapcount - 1)
5471 ? section->size : sec_data->map[span + 1].vma;
5472 unsigned int i;
5473 char span_type = sec_data->map[span].type;
5474 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5475
5476 if (span_type != 't')
5477 continue;
5478
5479 /* Span is entirely within a single 4KB region: skip scanning. */
5480 if (((base_vma + span_start) & ~0xfff)
48229727 5481 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5482 continue;
5483
5484 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5485
5486 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5487 * The branch target is in the same 4KB region as the
5488 first half of the branch.
5489 * The instruction before the branch is a 32-bit
5490 length non-branch instruction. */
5491 for (i = span_start; i < span_end;)
5492 {
5493 unsigned int insn = bfd_getl16 (&contents[i]);
5494 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5495 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5496
99059e56
RM		 5497 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5498 insn_32bit = TRUE;
48229727
JB		 5499
5500 if (insn_32bit)
99059e56
RM		 5501 {
5502 /* Load the rest of the insn (in manual-friendly order). */
5503 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5504
5505 /* Encoding T4: B<c>.W. */
5506 is_b = (insn & 0xf800d000) == 0xf0009000;
5507 /* Encoding T1: BL<c>.W. */
5508 is_bl = (insn & 0xf800d000) == 0xf000d000;
5509 /* Encoding T2: BLX<c>.W. */
5510 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5511 /* Encoding T3: B<c>.W (not permitted in IT block). */
5512 is_bcc = (insn & 0xf800d000) == 0xf0008000
5513 && (insn & 0x07f00000) != 0x03800000;
5514 }
5515
5516 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5517
99059e56 5518 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5519 && insn_32bit
5520 && is_32bit_branch
5521 && last_was_32bit
5522 && ! last_was_branch)
99059e56
RM		 5523 {
5524 bfd_signed_vma offset = 0;
5525 bfd_boolean force_target_arm = FALSE;
48229727 5526 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5527 bfd_vma target;
5528 enum elf32_arm_stub_type stub_type = arm_stub_none;
5529 struct a8_erratum_reloc key, *found;
5530 bfd_boolean use_plt = FALSE;
48229727 5531
99059e56
RM		 5532 key.from = base_vma + i;
5533 found = (struct a8_erratum_reloc *)
5534 bsearch (&key, a8_relocs, num_a8_relocs,
5535 sizeof (struct a8_erratum_reloc),
5536 &a8_reloc_compare);
48229727
JB		 5537
5538 if (found)
5539 {
5540 char *error_message = NULL;
5541 struct elf_link_hash_entry *entry;
5542
5543 /* We don't care about the error returned from this
99059e56 5544 function, only if there is glue or not. */
48229727
JB		 5545 entry = find_thumb_glue (info, found->sym_name,
5546 &error_message);
5547
5548 if (entry)
5549 found->non_a8_stub = TRUE;
5550
92750f34 5551 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5552 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5553 && found->hash->root.plt.offset != (bfd_vma) -1)
5554 use_plt = TRUE;
5555
5556 if (found->r_type == R_ARM_THM_CALL)
5557 {
35fc36a8
RS		 5558 if (found->branch_type == ST_BRANCH_TO_ARM
5559 || use_plt)
92750f34
DJ		 5560 force_target_arm = TRUE;
5561 else
5562 force_target_thumb = TRUE;
5563 }
48229727
JB		 5564 }
5565
99059e56 5566 /* Check if we have an offending branch instruction. */
48229727
JB		 5567
5568 if (found && found->non_a8_stub)
5569 /* We've already made a stub for this instruction, e.g.
5570 it's a long branch or a Thumb->ARM stub. Assume that
5571 stub will suffice to work around the A8 erratum (see
5572 setting of always_after_branch above). */
5573 ;
99059e56
RM		 5574 else if (is_bcc)
5575 {
5576 offset = (insn & 0x7ff) << 1;
5577 offset |= (insn & 0x3f0000) >> 4;
5578 offset |= (insn & 0x2000) ? 0x40000 : 0;
5579 offset |= (insn & 0x800) ? 0x80000 : 0;
5580 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5581 if (offset & 0x100000)
5582 offset |= ~ ((bfd_signed_vma) 0xfffff);
5583 stub_type = arm_stub_a8_veneer_b_cond;
5584 }
5585 else if (is_b || is_bl || is_blx)
5586 {
5587 int s = (insn & 0x4000000) != 0;
5588 int j1 = (insn & 0x2000) != 0;
5589 int j2 = (insn & 0x800) != 0;
5590 int i1 = !(j1 ^ s);
5591 int i2 = !(j2 ^ s);
5592
5593 offset = (insn & 0x7ff) << 1;
5594 offset |= (insn & 0x3ff0000) >> 4;
5595 offset |= i2 << 22;
5596 offset |= i1 << 23;
5597 offset |= s << 24;
5598 if (offset & 0x1000000)
5599 offset |= ~ ((bfd_signed_vma) 0xffffff);
5600
5601 if (is_blx)
5602 offset &= ~ ((bfd_signed_vma) 3);
5603
5604 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5605 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5606 }
5607
5608 if (stub_type != arm_stub_none)
5609 {
5610 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5611
5612 /* The original instruction is a BL, but the target is
99059e56 5613 an ARM instruction. If we were not making a stub,
48229727
JB		 5614 the BL would have been converted to a BLX. Use the
5615 BLX stub instead in that case. */
5616 if (htab->use_blx && force_target_arm
5617 && stub_type == arm_stub_a8_veneer_bl)
5618 {
5619 stub_type = arm_stub_a8_veneer_blx;
5620 is_blx = TRUE;
5621 is_bl = FALSE;
5622 }
5623 /* Conversely, if the original instruction was
5624 BLX but the target is Thumb mode, use the BL
5625 stub. */
5626 else if (force_target_thumb
5627 && stub_type == arm_stub_a8_veneer_blx)
5628 {
5629 stub_type = arm_stub_a8_veneer_bl;
5630 is_blx = FALSE;
5631 is_bl = TRUE;
5632 }
5633
99059e56
RM		 5634 if (is_blx)
5635 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5636
99059e56
RM		 5637 /* If we found a relocation, use the proper destination,
5638 not the offset in the (unrelocated) instruction.
48229727
JB		 5639 Note this is always done if we switched the stub type
5640 above. */
99059e56
RM		 5641 if (found)
5642 offset =
81694485 5643 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5644
99059e56
RM		 5645 /* If the stub will use a Thumb-mode branch to a
5646 PLT target, redirect it to the preceding Thumb
5647 entry point. */
5648 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5649 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5650
99059e56 5651 target = pc_for_insn + offset;
48229727 5652
99059e56
RM		 5653 /* The BLX stub is ARM-mode code. Adjust the offset to
5654 take the different PC value (+8 instead of +4) into
48229727 5655 account. */
99059e56
RM		 5656 if (stub_type == arm_stub_a8_veneer_blx)
5657 offset += 4;
5658
5659 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5660 {
5661 char *stub_name = NULL;
5662
5663 if (num_a8_fixes == a8_fix_table_size)
5664 {
5665 a8_fix_table_size *= 2;
5666 a8_fixes = (struct a8_erratum_fix *)
5667 bfd_realloc (a8_fixes,
5668 sizeof (struct a8_erratum_fix)
5669 * a8_fix_table_size);
5670 }
48229727 5671
eb7c4339
NS		 5672 if (num_a8_fixes < prev_num_a8_fixes)
5673 {
5674 /* If we're doing a subsequent scan,
5675 check if we've found the same fix as
5676 before, and try and reuse the stub
5677 name. */
5678 stub_name = a8_fixes[num_a8_fixes].stub_name;
5679 if ((a8_fixes[num_a8_fixes].section != section)
5680 || (a8_fixes[num_a8_fixes].offset != i))
5681 {
5682 free (stub_name);
5683 stub_name = NULL;
5684 *stub_changed_p = TRUE;
5685 }
5686 }
5687
5688 if (!stub_name)
5689 {
21d799b5 5690 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5691 if (stub_name != NULL)
5692 sprintf (stub_name, "%x:%x", section->id, i);
5693 }
48229727 5694
99059e56
RM		 5695 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5696 a8_fixes[num_a8_fixes].section = section;
5697 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5698 a8_fixes[num_a8_fixes].target_offset =
5699 target - base_vma;
99059e56
RM		 5700 a8_fixes[num_a8_fixes].orig_insn = insn;
5701 a8_fixes[num_a8_fixes].stub_name = stub_name;
5702 a8_fixes[num_a8_fixes].stub_type = stub_type;
5703 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5704 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5705
99059e56
RM		 5706 num_a8_fixes++;
5707 }
5708 }
5709 }
48229727 5710
99059e56
RM		 5711 i += insn_32bit ? 4 : 2;
5712 last_was_32bit = insn_32bit;
48229727 5713 last_was_branch = is_32bit_branch;
99059e56
RM		 5714 }
5715 }
48229727
JB		 5716
5717 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5718 free (contents);
48229727 5719 }
fe33d2fa 5720
48229727
JB		 5721 *a8_fixes_p = a8_fixes;
5722 *num_a8_fixes_p = num_a8_fixes;
5723 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5724
81694485 5725 return FALSE;
48229727
JB		 5726}
5727
b715f643
TP		 5728/* Create or update a stub entry depending on whether the stub can already be
5729 found in HTAB. The stub is identified by:
5730 - its type STUB_TYPE
5731 - its source branch (note that several can share the same stub) whose
5732 section and relocation (if any) are given by SECTION and IRELA
5733 respectively
5734 - its target symbol whose input section, hash, name, value and branch type
5735 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5736 respectively
5737
5738 If found, the value of the stub's target symbol is updated from SYM_VALUE
5739 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5740 TRUE and the stub entry is initialized.
5741
0955507f
TP		 5742 Returns the stub that was created or updated, or NULL if an error
5743 occurred. */
b715f643 5744
0955507f 5745static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5746elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5747 enum elf32_arm_stub_type stub_type, asection *section,
5748 Elf_Internal_Rela *irela, asection *sym_sec,
5749 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5750 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5751 bfd_boolean *new_stub)
5752{
5753 const asection *id_sec;
5754 char *stub_name;
5755 struct elf32_arm_stub_hash_entry *stub_entry;
5756 unsigned int r_type;
4f4faa4d 5757 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5758
5759 BFD_ASSERT (stub_type != arm_stub_none);
5760 *new_stub = FALSE;
5761
4f4faa4d
TP		 5762 if (sym_claimed)
5763 stub_name = sym_name;
5764 else
5765 {
5766 BFD_ASSERT (irela);
5767 BFD_ASSERT (section);
c2abbbeb 5768 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5769
4f4faa4d
TP		 5770 /* Support for grouping stub sections. */
5771 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5772
4f4faa4d
TP		 5773 /* Get the name of this stub. */
5774 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5775 stub_type);
5776 if (!stub_name)
0955507f 5777 return NULL;
4f4faa4d 5778 }
b715f643
TP		 5779
5780 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5781 FALSE);
5782 /* The proper stub has already been created, just update its value. */
5783 if (stub_entry != NULL)
5784 {
4f4faa4d
TP		 5785 if (!sym_claimed)
5786 free (stub_name);
b715f643 5787 stub_entry->target_value = sym_value;
0955507f 5788 return stub_entry;
b715f643
TP		 5789 }
5790
daa4adae 5791 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5792 if (stub_entry == NULL)
5793 {
4f4faa4d
TP		 5794 if (!sym_claimed)
5795 free (stub_name);
0955507f 5796 return NULL;
b715f643
TP		 5797 }
5798
5799 stub_entry->target_value = sym_value;
5800 stub_entry->target_section = sym_sec;
5801 stub_entry->stub_type = stub_type;
5802 stub_entry->h = hash;
5803 stub_entry->branch_type = branch_type;
5804
4f4faa4d
TP		 5805 if (sym_claimed)
5806 stub_entry->output_name = sym_name;
5807 else
b715f643 5808 {
4f4faa4d
TP		 5809 if (sym_name == NULL)
5810 sym_name = "unnamed";
5811 stub_entry->output_name = (char *)
5812 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5813 + strlen (sym_name));
5814 if (stub_entry->output_name == NULL)
5815 {
5816 free (stub_name);
0955507f 5817 return NULL;
4f4faa4d 5818 }
b715f643 5819
4f4faa4d
TP		 5820 /* For historical reasons, use the existing names for ARM-to-Thumb and
5821 Thumb-to-ARM stubs. */
5822 r_type = ELF32_R_TYPE (irela->r_info);
5823 if ((r_type == (unsigned int) R_ARM_THM_CALL
5824 || r_type == (unsigned int) R_ARM_THM_JUMP24
5825 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5826 && branch_type == ST_BRANCH_TO_ARM)
5827 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5828 else if ((r_type == (unsigned int) R_ARM_CALL
5829 || r_type == (unsigned int) R_ARM_JUMP24)
5830 && branch_type == ST_BRANCH_TO_THUMB)
5831 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5832 else
5833 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5834 }
b715f643
TP		 5835
5836 *new_stub = TRUE;
0955507f 5837 return stub_entry;
b715f643
TP		 5838}
5839
4ba2ef8f
TP		 5840/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5841 gateway veneer to transition from non secure to secure state and create them
5842 accordingly.
5843
5844 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5845 defines the conditions that govern Secure Gateway veneer creation for a
5846 given symbol <SYM> as follows:
5847 - it has function type
5848 - it has non local binding
5849 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5850 same type, binding and value as <SYM> (called normal symbol).
5851 An entry function can handle secure state transition itself in which case
5852 its special symbol would have a different value from the normal symbol.
5853
5854 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5855 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5856 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5857 created.
4ba2ef8f 5858
0955507f 5859 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5860
5861static bfd_boolean
5862cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5863 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5864 int *cmse_stub_created)
4ba2ef8f
TP		 5865{
5866 const struct elf_backend_data *bed;
5867 Elf_Internal_Shdr *symtab_hdr;
5868 unsigned i, j, sym_count, ext_start;
5869 Elf_Internal_Sym *cmse_sym, *local_syms;
5870 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5871 enum arm_st_branch_type branch_type;
5872 char *sym_name, *lsym_name;
5873 bfd_vma sym_value;
5874 asection *section;
0955507f
TP		 5875 struct elf32_arm_stub_hash_entry *stub_entry;
5876 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5877
5878 bed = get_elf_backend_data (input_bfd);
5879 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5880 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5881 ext_start = symtab_hdr->sh_info;
5882 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5883 && out_attr[Tag_CPU_arch_profile].i == 'M');
5884
5885 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5886 if (local_syms == NULL)
5887 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5888 symtab_hdr->sh_info, 0, NULL, NULL,
5889 NULL);
5890 if (symtab_hdr->sh_info && local_syms == NULL)
5891 return FALSE;
5892
5893 /* Scan symbols. */
5894 for (i = 0; i < sym_count; i++)
5895 {
5896 cmse_invalid = FALSE;
5897
5898 if (i < ext_start)
5899 {
5900 cmse_sym = &local_syms[i];
5901 /* Not a special symbol. */
5902 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5903 continue;
5904 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5905 symtab_hdr->sh_link,
5906 cmse_sym->st_name);
5907 /* Special symbol with local binding. */
5908 cmse_invalid = TRUE;
5909 }
5910 else
5911 {
5912 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5913 sym_name = (char *) cmse_hash->root.root.root.string;
5914
5915 /* Not a special symbol. */
5916 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5917 continue;
5918
5919 /* Special symbol has incorrect binding or type. */
5920 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5921 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5922 || cmse_hash->root.type != STT_FUNC)
5923 cmse_invalid = TRUE;
5924 }
5925
5926 if (!is_v8m)
5927 {
90b6238f
AM		 5928 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
5929 "ARMv8-M architecture or later"),
4eca0228 5930 input_bfd, sym_name);
4ba2ef8f
TP		 5931 is_v8m = TRUE; /* Avoid multiple warning. */
5932 ret = FALSE;
5933 }
5934
5935 if (cmse_invalid)
5936 {
90b6238f
AM		 5937 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
5938 " a global or weak function symbol"),
4eca0228 5939 input_bfd, sym_name);
4ba2ef8f
TP		 5940 ret = FALSE;
5941 if (i < ext_start)
5942 continue;
5943 }
5944
5945 sym_name += strlen (CMSE_PREFIX);
5946 hash = (struct elf32_arm_link_hash_entry *)
5947 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5948
5949 /* No associated normal symbol or it is neither global nor weak. */
5950 if (!hash
5951 || (hash->root.root.type != bfd_link_hash_defined
5952 && hash->root.root.type != bfd_link_hash_defweak)
5953 || hash->root.type != STT_FUNC)
5954 {
5955 /* Initialize here to avoid warning about use of possibly
5956 uninitialized variable. */
5957 j = 0;
5958
5959 if (!hash)
5960 {
5961 /* Searching for a normal symbol with local binding. */
5962 for (; j < ext_start; j++)
5963 {
5964 lsym_name =
5965 bfd_elf_string_from_elf_section (input_bfd,
5966 symtab_hdr->sh_link,
5967 local_syms[j].st_name);
5968 if (!strcmp (sym_name, lsym_name))
5969 break;
5970 }
5971 }
5972
5973 if (hash || j < ext_start)
5974 {
4eca0228 5975 _bfd_error_handler
90b6238f
AM		 5976 (_("%pB: invalid standard symbol `%s'; it must be "
5977 "a global or weak function symbol"),
5978 input_bfd, sym_name);
4ba2ef8f
TP		 5979 }
5980 else
4eca0228 5981 _bfd_error_handler
90b6238f 5982 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 5983 ret = FALSE;
5984 if (!hash)
5985 continue;
5986 }
5987
5988 sym_value = hash->root.root.u.def.value;
5989 section = hash->root.root.u.def.section;
5990
5991 if (cmse_hash->root.root.u.def.section != section)
5992 {
4eca0228 5993 _bfd_error_handler
90b6238f 5994 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 5995 input_bfd, sym_name);
5996 ret = FALSE;
5997 }
5998 if (cmse_hash->root.root.u.def.value != sym_value)
5999 continue; /* Ignore: could be an entry function starting with SG. */
6000
6001 /* If this section is a link-once section that will be discarded, then
6002 don't create any stubs. */
6003 if (section->output_section == NULL)
6004 {
4eca0228 6005 _bfd_error_handler
90b6238f 6006 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 6007 continue;
6008 }
6009
6010 if (hash->root.size == 0)
6011 {
4eca0228 6012 _bfd_error_handler
90b6238f 6013 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 6014 ret = FALSE;
6015 }
6016
6017 if (!ret)
6018 continue;
6019 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 6020 stub_entry
4ba2ef8f
TP		 6021 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6022 NULL, NULL, section, hash, sym_name,
6023 sym_value, branch_type, &new_stub);
6024
0955507f 6025 if (stub_entry == NULL)
4ba2ef8f
TP		 6026 ret = FALSE;
6027 else
6028 {
6029 BFD_ASSERT (new_stub);
0955507f 6030 (*cmse_stub_created)++;
4ba2ef8f
TP		 6031 }
6032 }
6033
6034 if (!symtab_hdr->contents)
6035 free (local_syms);
6036 return ret;
6037}
6038
0955507f
TP		 6039/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6040 code entry function, ie can be called from non secure code without using a
6041 veneer. */
6042
6043static bfd_boolean
6044cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6045{
42484486 6046 bfd_byte contents[4];
0955507f
TP		 6047 uint32_t first_insn;
6048 asection *section;
6049 file_ptr offset;
6050 bfd *abfd;
6051
6052 /* Defined symbol of function type. */
6053 if (hash->root.root.type != bfd_link_hash_defined
6054 && hash->root.root.type != bfd_link_hash_defweak)
6055 return FALSE;
6056 if (hash->root.type != STT_FUNC)
6057 return FALSE;
6058
6059 /* Read first instruction. */
6060 section = hash->root.root.u.def.section;
6061 abfd = section->owner;
6062 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 6063 if (!bfd_get_section_contents (abfd, section, contents, offset,
6064 sizeof (contents)))
0955507f
TP		 6065 return FALSE;
6066
42484486
TP		 6067 first_insn = bfd_get_32 (abfd, contents);
6068
6069 /* Starts by SG instruction. */
0955507f
TP		 6070 return first_insn == 0xe97fe97f;
6071}
6072
6073/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6074 secure gateway veneers (ie. the veneers was not in the input import library)
6075 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6076
6077static bfd_boolean
6078arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6079{
6080 struct elf32_arm_stub_hash_entry *stub_entry;
6081 struct bfd_link_info *info;
6082
6083 /* Massage our args to the form they really have. */
6084 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6085 info = (struct bfd_link_info *) gen_info;
6086
6087 if (info->out_implib_bfd)
6088 return TRUE;
6089
6090 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6091 return TRUE;
6092
6093 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 6094 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 6095
6096 return TRUE;
6097}
6098
6099/* Set offset of each secure gateway veneers so that its address remain
6100 identical to the one in the input import library referred by
6101 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6102 (present in input import library but absent from the executable being
6103 linked) or if new veneers appeared and there is no output import library
6104 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6105 number of secure gateway veneers found in the input import library.
6106
6107 The function returns whether an error occurred. If no error occurred,
6108 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6109 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6110 veneer observed set for new veneers to be layed out after. */
6111
6112static bfd_boolean
6113set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6114 struct elf32_arm_link_hash_table *htab,
6115 int *cmse_stub_created)
6116{
6117 long symsize;
6118 char *sym_name;
6119 flagword flags;
6120 long i, symcount;
6121 bfd *in_implib_bfd;
6122 asection *stub_out_sec;
6123 bfd_boolean ret = TRUE;
6124 Elf_Internal_Sym *intsym;
6125 const char *out_sec_name;
6126 bfd_size_type cmse_stub_size;
6127 asymbol **sympp = NULL, *sym;
6128 struct elf32_arm_link_hash_entry *hash;
6129 const insn_sequence *cmse_stub_template;
6130 struct elf32_arm_stub_hash_entry *stub_entry;
6131 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6132 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6133 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6134
6135 /* No input secure gateway import library. */
6136 if (!htab->in_implib_bfd)
6137 return TRUE;
6138
6139 in_implib_bfd = htab->in_implib_bfd;
6140 if (!htab->cmse_implib)
6141 {
871b3ab2 6142 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 6143 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 6144 return FALSE;
6145 }
6146
6147 /* Get symbol table size. */
6148 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6149 if (symsize < 0)
6150 return FALSE;
6151
6152 /* Read in the input secure gateway import library's symbol table. */
6153 sympp = (asymbol **) xmalloc (symsize);
6154 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6155 if (symcount < 0)
6156 {
6157 ret = FALSE;
6158 goto free_sym_buf;
6159 }
6160
6161 htab->new_cmse_stub_offset = 0;
6162 cmse_stub_size =
6163 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6164 &cmse_stub_template,
6165 &cmse_stub_template_size);
6166 out_sec_name =
6167 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6168 stub_out_sec =
6169 bfd_get_section_by_name (htab->obfd, out_sec_name);
6170 if (stub_out_sec != NULL)
6171 cmse_stub_sec_vma = stub_out_sec->vma;
6172
6173 /* Set addresses of veneers mentionned in input secure gateway import
6174 library's symbol table. */
6175 for (i = 0; i < symcount; i++)
6176 {
6177 sym = sympp[i];
6178 flags = sym->flags;
6179 sym_name = (char *) bfd_asymbol_name (sym);
6180 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6181
6182 if (sym->section != bfd_abs_section_ptr
6183 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6184 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6185 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6186 != ST_BRANCH_TO_THUMB))
6187 {
90b6238f
AM		 6188 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6189 "symbol should be absolute, global and "
6190 "refer to Thumb functions"),
4eca0228 6191 in_implib_bfd, sym_name);
0955507f
TP		 6192 ret = FALSE;
6193 continue;
6194 }
6195
6196 veneer_value = bfd_asymbol_value (sym);
6197 stub_offset = veneer_value - cmse_stub_sec_vma;
6198 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6199 FALSE, FALSE);
6200 hash = (struct elf32_arm_link_hash_entry *)
6201 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6202
6203 /* Stub entry should have been created by cmse_scan or the symbol be of
6204 a secure function callable from non secure code. */
6205 if (!stub_entry && !hash)
6206 {
6207 bfd_boolean new_stub;
6208
4eca0228 6209 _bfd_error_handler
90b6238f 6210 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6211 hash = (struct elf32_arm_link_hash_entry *)
6212 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6213 stub_entry
6214 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6215 NULL, NULL, bfd_abs_section_ptr, hash,
6216 sym_name, veneer_value,
6217 ST_BRANCH_TO_THUMB, &new_stub);
6218 if (stub_entry == NULL)
6219 ret = FALSE;
6220 else
6221 {
6222 BFD_ASSERT (new_stub);
6223 new_cmse_stubs_created++;
6224 (*cmse_stub_created)++;
6225 }
6226 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6227 stub_entry->stub_offset = stub_offset;
6228 }
6229 /* Symbol found is not callable from non secure code. */
6230 else if (!stub_entry)
6231 {
6232 if (!cmse_entry_fct_p (hash))
6233 {
90b6238f 6234 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6235 sym_name);
0955507f
TP		 6236 ret = FALSE;
6237 }
6238 continue;
6239 }
6240 else
6241 {
6242 /* Only stubs for SG veneers should have been created. */
6243 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6244
6245 /* Check visibility hasn't changed. */
6246 if (!!(flags & BSF_GLOBAL)
6247 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6248 _bfd_error_handler
90b6238f 6249 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6250 sym_name);
6251
6252 stub_entry->stub_offset = stub_offset;
6253 }
6254
6255 /* Size should match that of a SG veneer. */
6256 if (intsym->st_size != cmse_stub_size)
6257 {
90b6238f 6258 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6259 in_implib_bfd, sym_name);
0955507f
TP		 6260 ret = FALSE;
6261 }
6262
6263 /* Previous veneer address is before current SG veneer section. */
6264 if (veneer_value < cmse_stub_sec_vma)
6265 {
6266 /* Avoid offset underflow. */
6267 if (stub_entry)
6268 stub_entry->stub_offset = 0;
6269 stub_offset = 0;
6270 ret = FALSE;
6271 }
6272
6273 /* Complain if stub offset not a multiple of stub size. */
6274 if (stub_offset % cmse_stub_size)
6275 {
4eca0228 6276 _bfd_error_handler
90b6238f
AM		 6277 (_("offset of veneer for entry function `%s' not a multiple of "
6278 "its size"), sym_name);
0955507f
TP		 6279 ret = FALSE;
6280 }
6281
6282 if (!ret)
6283 continue;
6284
6285 new_cmse_stubs_created--;
6286 if (veneer_value < cmse_stub_array_start)
6287 cmse_stub_array_start = veneer_value;
6288 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6289 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6290 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6291 }
6292
6293 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6294 {
6295 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6296 _bfd_error_handler
0955507f
TP		 6297 (_("new entry function(s) introduced but no output import library "
6298 "specified:"));
6299 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6300 }
6301
6302 if (cmse_stub_array_start != cmse_stub_sec_vma)
6303 {
4eca0228 6304 _bfd_error_handler
90b6238f 6305 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6306 out_sec_name);
6307 ret = FALSE;
6308 }
6309
6310free_sym_buf:
6311 free (sympp);
6312 return ret;
6313}
6314
906e58ca
NC		 6315/* Determine and set the size of the stub section for a final link.
6316
6317 The basic idea here is to examine all the relocations looking for
6318 PC-relative calls to a target that is unreachable with a "bl"
6319 instruction. */
6320
6321bfd_boolean
6322elf32_arm_size_stubs (bfd *output_bfd,
6323 bfd *stub_bfd,
6324 struct bfd_link_info *info,
6325 bfd_signed_vma group_size,
7a89b94e 6326 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6327 asection *,
7a89b94e 6328 unsigned int),
906e58ca
NC		 6329 void (*layout_sections_again) (void))
6330{
0955507f 6331 bfd_boolean ret = TRUE;
4ba2ef8f 6332 obj_attribute *out_attr;
0955507f 6333 int cmse_stub_created = 0;
906e58ca 6334 bfd_size_type stub_group_size;
4ba2ef8f 6335 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6336 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6337 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6338 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6339 struct a8_erratum_reloc *a8_relocs = NULL;
6340 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6341
4dfe6ac6
NC		 6342 if (htab == NULL)
6343 return FALSE;
6344
48229727
JB		 6345 if (htab->fix_cortex_a8)
6346 {
21d799b5 6347 a8_fixes = (struct a8_erratum_fix *)
99059e56 6348 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6349 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6350 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6351 }
906e58ca
NC		 6352
6353 /* Propagate mach to stub bfd, because it may not have been
6354 finalized when we created stub_bfd. */
6355 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6356 bfd_get_mach (output_bfd));
6357
6358 /* Stash our params away. */
6359 htab->stub_bfd = stub_bfd;
6360 htab->add_stub_section = add_stub_section;
6361 htab->layout_sections_again = layout_sections_again;
07d72278 6362 stubs_always_after_branch = group_size < 0;
48229727 6363
4ba2ef8f
TP		 6364 out_attr = elf_known_obj_attributes_proc (output_bfd);
6365 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6366
48229727
JB		 6367 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6368 as the first half of a 32-bit branch straddling two 4K pages. This is a
6369 crude way of enforcing that. */
6370 if (htab->fix_cortex_a8)
6371 stubs_always_after_branch = 1;
6372
906e58ca
NC		 6373 if (group_size < 0)
6374 stub_group_size = -group_size;
6375 else
6376 stub_group_size = group_size;
6377
6378 if (stub_group_size == 1)
6379 {
6380 /* Default values. */
6381 /* Thumb branch range is +-4MB has to be used as the default
6382 maximum size (a given section can contain both ARM and Thumb
6383 code, so the worst case has to be taken into account).
6384
6385 This value is 24K less than that, which allows for 2025
6386 12-byte stubs. If we exceed that, then we will fail to link.
6387 The user will have to relink with an explicit group size
6388 option. */
6389 stub_group_size = 4170000;
6390 }
6391
07d72278 6392 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6393
3ae046cc
NS		 6394 /* If we're applying the cortex A8 fix, we need to determine the
6395 program header size now, because we cannot change it later --
6396 that could alter section placements. Notice the A8 erratum fix
6397 ends up requiring the section addresses to remain unchanged
6398 modulo the page size. That's something we cannot represent
6399 inside BFD, and we don't want to force the section alignment to
6400 be the page size. */
6401 if (htab->fix_cortex_a8)
6402 (*htab->layout_sections_again) ();
6403
906e58ca
NC		 6404 while (1)
6405 {
6406 bfd *input_bfd;
6407 unsigned int bfd_indx;
6408 asection *stub_sec;
d7c5bd02 6409 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6410 bfd_boolean stub_changed = FALSE;
6411 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6412
48229727 6413 num_a8_fixes = 0;
906e58ca
NC		 6414 for (input_bfd = info->input_bfds, bfd_indx = 0;
6415 input_bfd != NULL;
c72f2fb2 6416 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6417 {
6418 Elf_Internal_Shdr *symtab_hdr;
6419 asection *section;
6420 Elf_Internal_Sym *local_syms = NULL;
6421
99059e56
RM		 6422 if (!is_arm_elf (input_bfd))
6423 continue;
adbcc655 6424
48229727
JB		 6425 num_a8_relocs = 0;
6426
906e58ca
NC		 6427 /* We'll need the symbol table in a second. */
6428 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6429 if (symtab_hdr->sh_info == 0)
6430 continue;
6431
4ba2ef8f
TP		 6432 /* Limit scan of symbols to object file whose profile is
6433 Microcontroller to not hinder performance in the general case. */
6434 if (m_profile && first_veneer_scan)
6435 {
6436 struct elf_link_hash_entry **sym_hashes;
6437
6438 sym_hashes = elf_sym_hashes (input_bfd);
6439 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6440 &cmse_stub_created))
4ba2ef8f 6441 goto error_ret_free_local;
0955507f
TP		 6442
6443 if (cmse_stub_created != 0)
6444 stub_changed = TRUE;
4ba2ef8f
TP		 6445 }
6446
906e58ca
NC		 6447 /* Walk over each section attached to the input bfd. */
6448 for (section = input_bfd->sections;
6449 section != NULL;
6450 section = section->next)
6451 {
6452 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6453
6454 /* If there aren't any relocs, then there's nothing more
6455 to do. */
6456 if ((section->flags & SEC_RELOC) == 0
6457 || section->reloc_count == 0
6458 || (section->flags & SEC_CODE) == 0)
6459 continue;
6460
6461 /* If this section is a link-once section that will be
6462 discarded, then don't create any stubs. */
6463 if (section->output_section == NULL
6464 || section->output_section->owner != output_bfd)
6465 continue;
6466
6467 /* Get the relocs. */
6468 internal_relocs
6469 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6470 NULL, info->keep_memory);
6471 if (internal_relocs == NULL)
6472 goto error_ret_free_local;
6473
6474 /* Now examine each relocation. */
6475 irela = internal_relocs;
6476 irelaend = irela + section->reloc_count;
6477 for (; irela < irelaend; irela++)
6478 {
6479 unsigned int r_type, r_indx;
906e58ca
NC		 6480 asection *sym_sec;
6481 bfd_vma sym_value;
6482 bfd_vma destination;
6483 struct elf32_arm_link_hash_entry *hash;
7413f23f 6484 const char *sym_name;
34e77a92 6485 unsigned char st_type;
35fc36a8 6486 enum arm_st_branch_type branch_type;
48229727 6487 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6488
6489 r_type = ELF32_R_TYPE (irela->r_info);
6490 r_indx = ELF32_R_SYM (irela->r_info);
6491
6492 if (r_type >= (unsigned int) R_ARM_max)
6493 {
6494 bfd_set_error (bfd_error_bad_value);
6495 error_ret_free_internal:
6496 if (elf_section_data (section)->relocs == NULL)
6497 free (internal_relocs);
15dd01b1
TP		 6498 /* Fall through. */
6499 error_ret_free_local:
6500 if (local_syms != NULL
6501 && (symtab_hdr->contents
6502 != (unsigned char *) local_syms))
6503 free (local_syms);
6504 return FALSE;
906e58ca 6505 }
b38cadfb 6506
0855e32b
NS		 6507 hash = NULL;
6508 if (r_indx >= symtab_hdr->sh_info)
6509 hash = elf32_arm_hash_entry
6510 (elf_sym_hashes (input_bfd)
6511 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6512
0855e32b
NS		 6513 /* Only look for stubs on branch instructions, or
6514 non-relaxed TLSCALL */
906e58ca 6515 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6516 && (r_type != (unsigned int) R_ARM_THM_CALL)
6517 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6518 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6519 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6520 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6521 && (r_type != (unsigned int) R_ARM_PLT32)
6522 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6523 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6524 && r_type == elf32_arm_tls_transition
6525 (info, r_type, &hash->root)
6526 && ((hash ? hash->tls_type
6527 : (elf32_arm_local_got_tls_type
6528 (input_bfd)[r_indx]))
6529 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6530 continue;
6531
6532 /* Now determine the call target, its name, value,
6533 section. */
6534 sym_sec = NULL;
6535 sym_value = 0;
6536 destination = 0;
7413f23f 6537 sym_name = NULL;
b38cadfb 6538
0855e32b
NS		 6539 if (r_type == (unsigned int) R_ARM_TLS_CALL
6540 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6541 {
6542 /* A non-relaxed TLS call. The target is the
6543 plt-resident trampoline and nothing to do
6544 with the symbol. */
6545 BFD_ASSERT (htab->tls_trampoline > 0);
6546 sym_sec = htab->root.splt;
6547 sym_value = htab->tls_trampoline;
6548 hash = 0;
34e77a92 6549 st_type = STT_FUNC;
35fc36a8 6550 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6551 }
6552 else if (!hash)
906e58ca
NC		 6553 {
6554 /* It's a local symbol. */
6555 Elf_Internal_Sym *sym;
906e58ca
NC		 6556
6557 if (local_syms == NULL)
6558 {
6559 local_syms
6560 = (Elf_Internal_Sym *) symtab_hdr->contents;
6561 if (local_syms == NULL)
6562 local_syms
6563 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6564 symtab_hdr->sh_info, 0,
6565 NULL, NULL, NULL);
6566 if (local_syms == NULL)
6567 goto error_ret_free_internal;
6568 }
6569
6570 sym = local_syms + r_indx;
f6d250ce
TS		 6571 if (sym->st_shndx == SHN_UNDEF)
6572 sym_sec = bfd_und_section_ptr;
6573 else if (sym->st_shndx == SHN_ABS)
6574 sym_sec = bfd_abs_section_ptr;
6575 else if (sym->st_shndx == SHN_COMMON)
6576 sym_sec = bfd_com_section_ptr;
6577 else
6578 sym_sec =
6579 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6580
ffcb4889
NS		 6581 if (!sym_sec)
6582 /* This is an undefined symbol. It can never
6a631e86 6583 be resolved. */
ffcb4889 6584 continue;
fe33d2fa 6585
906e58ca
NC		 6586 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6587 sym_value = sym->st_value;
6588 destination = (sym_value + irela->r_addend
6589 + sym_sec->output_offset
6590 + sym_sec->output_section->vma);
34e77a92 6591 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6592 branch_type =
6593 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6594 sym_name
6595 = bfd_elf_string_from_elf_section (input_bfd,
6596 symtab_hdr->sh_link,
6597 sym->st_name);
906e58ca
NC		 6598 }
6599 else
6600 {
6601 /* It's an external symbol. */
906e58ca
NC		 6602 while (hash->root.root.type == bfd_link_hash_indirect
6603 || hash->root.root.type == bfd_link_hash_warning)
6604 hash = ((struct elf32_arm_link_hash_entry *)
6605 hash->root.root.u.i.link);
6606
6607 if (hash->root.root.type == bfd_link_hash_defined
6608 || hash->root.root.type == bfd_link_hash_defweak)
6609 {
6610 sym_sec = hash->root.root.u.def.section;
6611 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6612
6613 struct elf32_arm_link_hash_table *globals =
6614 elf32_arm_hash_table (info);
6615
6616 /* For a destination in a shared library,
6617 use the PLT stub as target address to
6618 decide whether a branch stub is
6619 needed. */
4dfe6ac6 6620 if (globals != NULL
362d30a1 6621 && globals->root.splt != NULL
4dfe6ac6 6622 && hash != NULL
022f8312
CL		 6623 && hash->root.plt.offset != (bfd_vma) -1)
6624 {
362d30a1 6625 sym_sec = globals->root.splt;
022f8312
CL		 6626 sym_value = hash->root.plt.offset;
6627 if (sym_sec->output_section != NULL)
6628 destination = (sym_value
6629 + sym_sec->output_offset
6630 + sym_sec->output_section->vma);
6631 }
6632 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6633 destination = (sym_value + irela->r_addend
6634 + sym_sec->output_offset
6635 + sym_sec->output_section->vma);
6636 }
69c5861e
CL		 6637 else if ((hash->root.root.type == bfd_link_hash_undefined)
6638 || (hash->root.root.type == bfd_link_hash_undefweak))
6639 {
6640 /* For a shared library, use the PLT stub as
6641 target address to decide whether a long
6642 branch stub is needed.
6643 For absolute code, they cannot be handled. */
6644 struct elf32_arm_link_hash_table *globals =
6645 elf32_arm_hash_table (info);
6646
4dfe6ac6 6647 if (globals != NULL
362d30a1 6648 && globals->root.splt != NULL
4dfe6ac6 6649 && hash != NULL
69c5861e
CL		 6650 && hash->root.plt.offset != (bfd_vma) -1)
6651 {
362d30a1 6652 sym_sec = globals->root.splt;
69c5861e
CL		 6653 sym_value = hash->root.plt.offset;
6654 if (sym_sec->output_section != NULL)
6655 destination = (sym_value
6656 + sym_sec->output_offset
6657 + sym_sec->output_section->vma);
6658 }
6659 else
6660 continue;
6661 }
906e58ca
NC		 6662 else
6663 {
6664 bfd_set_error (bfd_error_bad_value);
6665 goto error_ret_free_internal;
6666 }
34e77a92 6667 st_type = hash->root.type;
39d911fc
TP		 6668 branch_type =
6669 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6670 sym_name = hash->root.root.root.string;
906e58ca
NC		 6671 }
6672
48229727 6673 do
7413f23f 6674 {
b715f643 6675 bfd_boolean new_stub;
0955507f 6676 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6677
48229727
JB		 6678 /* Determine what (if any) linker stub is needed. */
6679 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6680 st_type, &branch_type,
6681 hash, destination, sym_sec,
48229727
JB		 6682 input_bfd, sym_name);
6683 if (stub_type == arm_stub_none)
6684 break;
6685
48229727
JB		 6686 /* We've either created a stub for this reloc already,
6687 or we are about to. */
0955507f 6688 stub_entry =
b715f643
TP		 6689 elf32_arm_create_stub (htab, stub_type, section, irela,
6690 sym_sec, hash,
6691 (char *) sym_name, sym_value,
6692 branch_type, &new_stub);
7413f23f 6693
0955507f 6694 created_stub = stub_entry != NULL;
b715f643
TP		 6695 if (!created_stub)
6696 goto error_ret_free_internal;
6697 else if (!new_stub)
6698 break;
99059e56 6699 else
b715f643 6700 stub_changed = TRUE;
99059e56
RM		 6701 }
6702 while (0);
6703
6704 /* Look for relocations which might trigger Cortex-A8
6705 erratum. */
6706 if (htab->fix_cortex_a8
6707 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6708 || r_type == (unsigned int) R_ARM_THM_JUMP19
6709 || r_type == (unsigned int) R_ARM_THM_CALL
6710 || r_type == (unsigned int) R_ARM_THM_XPC22))
6711 {
6712 bfd_vma from = section->output_section->vma
6713 + section->output_offset
6714 + irela->r_offset;
6715
6716 if ((from & 0xfff) == 0xffe)
6717 {
6718 /* Found a candidate. Note we haven't checked the
6719 destination is within 4K here: if we do so (and
6720 don't create an entry in a8_relocs) we can't tell
6721 that a branch should have been relocated when
6722 scanning later. */
6723 if (num_a8_relocs == a8_reloc_table_size)
6724 {
6725 a8_reloc_table_size *= 2;
6726 a8_relocs = (struct a8_erratum_reloc *)
6727 bfd_realloc (a8_relocs,
6728 sizeof (struct a8_erratum_reloc)
6729 * a8_reloc_table_size);
6730 }
6731
6732 a8_relocs[num_a8_relocs].from = from;
6733 a8_relocs[num_a8_relocs].destination = destination;
6734 a8_relocs[num_a8_relocs].r_type = r_type;
6735 a8_relocs[num_a8_relocs].branch_type = branch_type;
6736 a8_relocs[num_a8_relocs].sym_name = sym_name;
6737 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6738 a8_relocs[num_a8_relocs].hash = hash;
6739
6740 num_a8_relocs++;
6741 }
6742 }
906e58ca
NC		 6743 }
6744
99059e56
RM		 6745 /* We're done with the internal relocs, free them. */
6746 if (elf_section_data (section)->relocs == NULL)
6747 free (internal_relocs);
6748 }
48229727 6749
99059e56 6750 if (htab->fix_cortex_a8)
48229727 6751 {
99059e56
RM		 6752 /* Sort relocs which might apply to Cortex-A8 erratum. */
6753 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6754 sizeof (struct a8_erratum_reloc),
99059e56 6755 &a8_reloc_compare);
48229727 6756
99059e56
RM		 6757 /* Scan for branches which might trigger Cortex-A8 erratum. */
6758 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6759 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6760 a8_relocs, num_a8_relocs,
6761 prev_num_a8_fixes, &stub_changed)
6762 != 0)
48229727 6763 goto error_ret_free_local;
5e681ec4 6764 }
7f991970
AM		 6765
6766 if (local_syms != NULL
6767 && symtab_hdr->contents != (unsigned char *) local_syms)
6768 {
6769 if (!info->keep_memory)
6770 free (local_syms);
6771 else
6772 symtab_hdr->contents = (unsigned char *) local_syms;
6773 }
5e681ec4
PB		 6774 }
6775
0955507f
TP		 6776 if (first_veneer_scan
6777 && !set_cmse_veneer_addr_from_implib (info, htab,
6778 &cmse_stub_created))
6779 ret = FALSE;
6780
eb7c4339 6781 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6782 stub_changed = TRUE;
48229727 6783
906e58ca
NC		 6784 if (!stub_changed)
6785 break;
5e681ec4 6786
906e58ca
NC		 6787 /* OK, we've added some stubs. Find out the new size of the
6788 stub sections. */
6789 for (stub_sec = htab->stub_bfd->sections;
6790 stub_sec != NULL;
6791 stub_sec = stub_sec->next)
3e6b1042
DJ		 6792 {
6793 /* Ignore non-stub sections. */
6794 if (!strstr (stub_sec->name, STUB_SUFFIX))
6795 continue;
6796
6797 stub_sec->size = 0;
6798 }
b34b2d70 6799
0955507f
TP		 6800 /* Add new SG veneers after those already in the input import
6801 library. */
6802 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6803 stub_type++)
6804 {
6805 bfd_vma *start_offset_p;
6806 asection **stub_sec_p;
6807
6808 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6809 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6810 if (start_offset_p == NULL)
6811 continue;
6812
6813 BFD_ASSERT (stub_sec_p != NULL);
6814 if (*stub_sec_p != NULL)
6815 (*stub_sec_p)->size = *start_offset_p;
6816 }
6817
d7c5bd02 6818 /* Compute stub section size, considering padding. */
906e58ca 6819 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6820 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6821 stub_type++)
6822 {
6823 int size, padding;
6824 asection **stub_sec_p;
6825
6826 padding = arm_dedicated_stub_section_padding (stub_type);
6827 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6828 /* Skip if no stub input section or no stub section padding
6829 required. */
6830 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6831 continue;
6832 /* Stub section padding required but no dedicated section. */
6833 BFD_ASSERT (stub_sec_p);
6834
6835 size = (*stub_sec_p)->size;
6836 size = (size + padding - 1) & ~(padding - 1);
6837 (*stub_sec_p)->size = size;
6838 }
906e58ca 6839
48229727
JB		 6840 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6841 if (htab->fix_cortex_a8)
99059e56
RM		 6842 for (i = 0; i < num_a8_fixes; i++)
6843 {
48229727 6844 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6845 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6846
6847 if (stub_sec == NULL)
7f991970 6848 return FALSE;
48229727 6849
99059e56
RM		 6850 stub_sec->size
6851 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6852 NULL);
6853 }
48229727
JB		 6854
6855
906e58ca
NC		 6856 /* Ask the linker to do its stuff. */
6857 (*htab->layout_sections_again) ();
4ba2ef8f 6858 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6859 }
6860
48229727
JB		 6861 /* Add stubs for Cortex-A8 erratum fixes now. */
6862 if (htab->fix_cortex_a8)
6863 {
6864 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6865 {
6866 struct elf32_arm_stub_hash_entry *stub_entry;
6867 char *stub_name = a8_fixes[i].stub_name;
6868 asection *section = a8_fixes[i].section;
6869 unsigned int section_id = a8_fixes[i].section->id;
6870 asection *link_sec = htab->stub_group[section_id].link_sec;
6871 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6872 const insn_sequence *template_sequence;
6873 int template_size, size = 0;
6874
6875 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6876 TRUE, FALSE);
6877 if (stub_entry == NULL)
6878 {
871b3ab2 6879 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6880 section->owner, stub_name);
99059e56
RM		 6881 return FALSE;
6882 }
6883
6884 stub_entry->stub_sec = stub_sec;
0955507f 6885 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6886 stub_entry->id_sec = link_sec;
6887 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6888 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6889 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6890 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6891 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6892 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6893
99059e56
RM		 6894 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6895 &template_sequence,
6896 &template_size);
48229727 6897
99059e56
RM		 6898 stub_entry->stub_size = size;
6899 stub_entry->stub_template = template_sequence;
6900 stub_entry->stub_template_size = template_size;
6901 }
48229727
JB		 6902
6903 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6904 elf32_arm_write_section(). */
48229727
JB		 6905 htab->a8_erratum_fixes = a8_fixes;
6906 htab->num_a8_erratum_fixes = num_a8_fixes;
6907 }
6908 else
6909 {
6910 htab->a8_erratum_fixes = NULL;
6911 htab->num_a8_erratum_fixes = 0;
6912 }
0955507f 6913 return ret;
5e681ec4
PB		 6914}
6915
906e58ca
NC		 6916/* Build all the stubs associated with the current output file. The
6917 stubs are kept in a hash table attached to the main linker hash
6918 table. We also set up the .plt entries for statically linked PIC
6919 functions here. This function is called via arm_elf_finish in the
6920 linker. */
252b5132 6921
906e58ca
NC		 6922bfd_boolean
6923elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6924{
906e58ca
NC		 6925 asection *stub_sec;
6926 struct bfd_hash_table *table;
0955507f 6927 enum elf32_arm_stub_type stub_type;
906e58ca 6928 struct elf32_arm_link_hash_table *htab;
252b5132 6929
906e58ca 6930 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6931 if (htab == NULL)
6932 return FALSE;
252b5132 6933
906e58ca
NC		 6934 for (stub_sec = htab->stub_bfd->sections;
6935 stub_sec != NULL;
6936 stub_sec = stub_sec->next)
252b5132 6937 {
906e58ca
NC		 6938 bfd_size_type size;
6939
8029a119 6940 /* Ignore non-stub sections. */
906e58ca
NC		 6941 if (!strstr (stub_sec->name, STUB_SUFFIX))
6942 continue;
6943
d7c5bd02 6944 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 6945 must at least be done for stub section requiring padding and for SG
6946 veneers to ensure that a non secure code branching to a removed SG
6947 veneer causes an error. */
906e58ca 6948 size = stub_sec->size;
21d799b5 6949 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6950 if (stub_sec->contents == NULL && size != 0)
6951 return FALSE;
0955507f 6952
906e58ca 6953 stub_sec->size = 0;
252b5132
RH		 6954 }
6955
0955507f
TP		 6956 /* Add new SG veneers after those already in the input import library. */
6957 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6958 {
6959 bfd_vma *start_offset_p;
6960 asection **stub_sec_p;
6961
6962 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6963 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6964 if (start_offset_p == NULL)
6965 continue;
6966
6967 BFD_ASSERT (stub_sec_p != NULL);
6968 if (*stub_sec_p != NULL)
6969 (*stub_sec_p)->size = *start_offset_p;
6970 }
6971
906e58ca
NC		 6972 /* Build the stubs as directed by the stub hash table. */
6973 table = &htab->stub_hash_table;
6974 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 6975 if (htab->fix_cortex_a8)
6976 {
6977 /* Place the cortex a8 stubs last. */
6978 htab->fix_cortex_a8 = -1;
6979 bfd_hash_traverse (table, arm_build_one_stub, info);
6980 }
252b5132 6981
906e58ca 6982 return TRUE;
252b5132
RH		 6983}
6984
9b485d32
NC		 6985/* Locate the Thumb encoded calling stub for NAME. */
6986
252b5132 6987static struct elf_link_hash_entry *
57e8b36a
NC		 6988find_thumb_glue (struct bfd_link_info *link_info,
6989 const char *name,
f2a9dd69 6990 char **error_message)
252b5132
RH		 6991{
6992 char *tmp_name;
6993 struct elf_link_hash_entry *hash;
6994 struct elf32_arm_link_hash_table *hash_table;
6995
6996 /* We need a pointer to the armelf specific hash table. */
6997 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6998 if (hash_table == NULL)
6999 return NULL;
252b5132 7000
21d799b5 7001 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7002 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7003
7004 BFD_ASSERT (tmp_name);
7005
7006 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7007
7008 hash = elf_link_hash_lookup
b34976b6 7009 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7010
b1657152 7011 if (hash == NULL
90b6238f
AM		 7012 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7013 "Thumb", tmp_name, name) == -1)
b1657152 7014 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7015
7016 free (tmp_name);
7017
7018 return hash;
7019}
7020
9b485d32
NC		 7021/* Locate the ARM encoded calling stub for NAME. */
7022
252b5132 7023static struct elf_link_hash_entry *
57e8b36a
NC		 7024find_arm_glue (struct bfd_link_info *link_info,
7025 const char *name,
f2a9dd69 7026 char **error_message)
252b5132
RH		 7027{
7028 char *tmp_name;
7029 struct elf_link_hash_entry *myh;
7030 struct elf32_arm_link_hash_table *hash_table;
7031
7032 /* We need a pointer to the elfarm specific hash table. */
7033 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7034 if (hash_table == NULL)
7035 return NULL;
252b5132 7036
21d799b5 7037 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7038 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7039
7040 BFD_ASSERT (tmp_name);
7041
7042 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7043
7044 myh = elf_link_hash_lookup
b34976b6 7045 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7046
b1657152 7047 if (myh == NULL
90b6238f
AM		 7048 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7049 "ARM", tmp_name, name) == -1)
b1657152 7050 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7051
7052 free (tmp_name);
7053
7054 return myh;
7055}
7056
8f6277f5 7057/* ARM->Thumb glue (static images):
252b5132
RH		 7058
7059 .arm
7060 __func_from_arm:
7061 ldr r12, __func_addr
7062 bx r12
7063 __func_addr:
906e58ca 7064 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 7065
26079076
PB		 7066 (v5t static images)
7067 .arm
7068 __func_from_arm:
7069 ldr pc, __func_addr
7070 __func_addr:
906e58ca 7071 .word func @ behave as if you saw a ARM_32 reloc.
26079076 7072
8f6277f5
PB		 7073 (relocatable images)
7074 .arm
7075 __func_from_arm:
7076 ldr r12, __func_offset
7077 add r12, r12, pc
7078 bx r12
7079 __func_offset:
8029a119 7080 .word func - . */
8f6277f5
PB		 7081
7082#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 7083static const insn32 a2t1_ldr_insn = 0xe59fc000;
7084static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7085static const insn32 a2t3_func_addr_insn = 0x00000001;
7086
26079076
PB		 7087#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7088static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7089static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7090
8f6277f5
PB		 7091#define ARM2THUMB_PIC_GLUE_SIZE 16
7092static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7093static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7094static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7095
07d6d2b8 7096/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 7097
07d6d2b8
AM		 7098 .thumb .thumb
7099 .align 2 .align 2
7100 __func_from_thumb: __func_from_thumb:
7101 bx pc push {r6, lr}
7102 nop ldr r6, __func_addr
7103 .arm mov lr, pc
7104 b func bx r6
99059e56
RM		 7105 .arm
7106 ;; back_to_thumb
7107 ldmia r13! {r6, lr}
7108 bx lr
7109 __func_addr:
07d6d2b8 7110 .word func */
252b5132
RH		 7111
7112#define THUMB2ARM_GLUE_SIZE 8
7113static const insn16 t2a1_bx_pc_insn = 0x4778;
7114static const insn16 t2a2_noop_insn = 0x46c0;
7115static const insn32 t2a3_b_insn = 0xea000000;
7116
c7b8f16e 7117#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 7118#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7119#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 7120
845b51d6
PB		 7121#define ARM_BX_VENEER_SIZE 12
7122static const insn32 armbx1_tst_insn = 0xe3100001;
7123static const insn32 armbx2_moveq_insn = 0x01a0f000;
7124static const insn32 armbx3_bx_insn = 0xe12fff10;
7125
7e392df6 7126#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 7127static void
7128arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 7129{
7130 asection * s;
8029a119 7131 bfd_byte * contents;
252b5132 7132
8029a119 7133 if (size == 0)
3e6b1042
DJ		 7134 {
7135 /* Do not include empty glue sections in the output. */
7136 if (abfd != NULL)
7137 {
3d4d4302 7138 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 7139 if (s != NULL)
7140 s->flags |= SEC_EXCLUDE;
7141 }
7142 return;
7143 }
252b5132 7144
8029a119 7145 BFD_ASSERT (abfd != NULL);
252b5132 7146
3d4d4302 7147 s = bfd_get_linker_section (abfd, name);
8029a119 7148 BFD_ASSERT (s != NULL);
252b5132 7149
21d799b5 7150 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 7151
8029a119
NC		 7152 BFD_ASSERT (s->size == size);
7153 s->contents = contents;
7154}
906e58ca 7155
8029a119
NC		 7156bfd_boolean
7157bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7158{
7159 struct elf32_arm_link_hash_table * globals;
906e58ca 7160
8029a119
NC		 7161 globals = elf32_arm_hash_table (info);
7162 BFD_ASSERT (globals != NULL);
906e58ca 7163
8029a119
NC		 7164 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7165 globals->arm_glue_size,
7166 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 7167
8029a119
NC		 7168 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7169 globals->thumb_glue_size,
7170 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 7171
8029a119
NC		 7172 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7173 globals->vfp11_erratum_glue_size,
7174 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 7175
a504d23a
LA		 7176 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7177 globals->stm32l4xx_erratum_glue_size,
7178 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7179
8029a119
NC		 7180 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7181 globals->bx_glue_size,
845b51d6
PB		 7182 ARM_BX_GLUE_SECTION_NAME);
7183
b34976b6 7184 return TRUE;
252b5132
RH		 7185}
7186
a4fd1a8e 7187/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7188 returns the symbol identifying the stub. */
7189
a4fd1a8e 7190static struct elf_link_hash_entry *
57e8b36a
NC		 7191record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7192 struct elf_link_hash_entry * h)
252b5132
RH		 7193{
7194 const char * name = h->root.root.string;
63b0f745 7195 asection * s;
252b5132
RH		 7196 char * tmp_name;
7197 struct elf_link_hash_entry * myh;
14a793b2 7198 struct bfd_link_hash_entry * bh;
252b5132 7199 struct elf32_arm_link_hash_table * globals;
dc810e39 7200 bfd_vma val;
2f475487 7201 bfd_size_type size;
252b5132
RH		 7202
7203 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7204 BFD_ASSERT (globals != NULL);
7205 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7206
3d4d4302 7207 s = bfd_get_linker_section
252b5132
RH		 7208 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7209
252b5132
RH		 7210 BFD_ASSERT (s != NULL);
7211
21d799b5 7212 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7213 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7214
7215 BFD_ASSERT (tmp_name);
7216
7217 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7218
7219 myh = elf_link_hash_lookup
b34976b6 7220 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7221
7222 if (myh != NULL)
7223 {
9b485d32 7224 /* We've already seen this guy. */
252b5132 7225 free (tmp_name);
a4fd1a8e 7226 return myh;
252b5132
RH		 7227 }
7228
57e8b36a
NC		 7229 /* The only trick here is using hash_table->arm_glue_size as the value.
7230 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7231 putting it. The +1 on the value marks that the stub has not been
7232 output yet - not that it is a Thumb function. */
14a793b2 7233 bh = NULL;
dc810e39
AM		 7234 val = globals->arm_glue_size + 1;
7235 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7236 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7237 NULL, TRUE, FALSE, &bh);
252b5132 7238
b7693d02
DJ		 7239 myh = (struct elf_link_hash_entry *) bh;
7240 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7241 myh->forced_local = 1;
7242
252b5132
RH		 7243 free (tmp_name);
7244
0e1862bb
L		 7245 if (bfd_link_pic (link_info)
7246 || globals->root.is_relocatable_executable
27e55c4d 7247 || globals->pic_veneer)
2f475487 7248 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7249 else if (globals->use_blx)
7250 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7251 else
2f475487
AM		 7252 size = ARM2THUMB_STATIC_GLUE_SIZE;
7253
7254 s->size += size;
7255 globals->arm_glue_size += size;
252b5132 7256
a4fd1a8e 7257 return myh;
252b5132
RH		 7258}
7259
845b51d6
PB		 7260/* Allocate space for ARMv4 BX veneers. */
7261
7262static void
7263record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7264{
7265 asection * s;
7266 struct elf32_arm_link_hash_table *globals;
7267 char *tmp_name;
7268 struct elf_link_hash_entry *myh;
7269 struct bfd_link_hash_entry *bh;
7270 bfd_vma val;
7271
7272 /* BX PC does not need a veneer. */
7273 if (reg == 15)
7274 return;
7275
7276 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7277 BFD_ASSERT (globals != NULL);
7278 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7279
7280 /* Check if this veneer has already been allocated. */
7281 if (globals->bx_glue_offset[reg])
7282 return;
7283
3d4d4302 7284 s = bfd_get_linker_section
845b51d6
PB		 7285 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7286
7287 BFD_ASSERT (s != NULL);
7288
7289 /* Add symbol for veneer. */
21d799b5
NC		 7290 tmp_name = (char *)
7291 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7292
845b51d6 7293 BFD_ASSERT (tmp_name);
906e58ca 7294
845b51d6 7295 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7296
845b51d6
PB		 7297 myh = elf_link_hash_lookup
7298 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7299
845b51d6 7300 BFD_ASSERT (myh == NULL);
906e58ca 7301
845b51d6
PB		 7302 bh = NULL;
7303 val = globals->bx_glue_size;
7304 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7305 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7306 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7307
7308 myh = (struct elf_link_hash_entry *) bh;
7309 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7310 myh->forced_local = 1;
7311
7312 s->size += ARM_BX_VENEER_SIZE;
7313 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7314 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7315}
7316
7317
c7b8f16e
JB		 7318/* Add an entry to the code/data map for section SEC. */
7319
7320static void
7321elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7322{
7323 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7324 unsigned int newidx;
906e58ca 7325
c7b8f16e
JB		 7326 if (sec_data->map == NULL)
7327 {
21d799b5 7328 sec_data->map = (elf32_arm_section_map *)
99059e56 7329 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7330 sec_data->mapcount = 0;
7331 sec_data->mapsize = 1;
7332 }
906e58ca 7333
c7b8f16e 7334 newidx = sec_data->mapcount++;
906e58ca 7335
c7b8f16e
JB		 7336 if (sec_data->mapcount > sec_data->mapsize)
7337 {
7338 sec_data->mapsize *= 2;
21d799b5 7339 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7340 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7341 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7342 }
7343
7344 if (sec_data->map)
7345 {
7346 sec_data->map[newidx].vma = vma;
7347 sec_data->map[newidx].type = type;
c7b8f16e 7348 }
c7b8f16e
JB		 7349}
7350
7351
7352/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7353 veneers are handled for now. */
7354
7355static bfd_vma
7356record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7357 elf32_vfp11_erratum_list *branch,
7358 bfd *branch_bfd,
7359 asection *branch_sec,
7360 unsigned int offset)
c7b8f16e
JB		 7361{
7362 asection *s;
7363 struct elf32_arm_link_hash_table *hash_table;
7364 char *tmp_name;
7365 struct elf_link_hash_entry *myh;
7366 struct bfd_link_hash_entry *bh;
7367 bfd_vma val;
7368 struct _arm_elf_section_data *sec_data;
c7b8f16e 7369 elf32_vfp11_erratum_list *newerr;
906e58ca 7370
c7b8f16e 7371 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7372 BFD_ASSERT (hash_table != NULL);
7373 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7374
3d4d4302 7375 s = bfd_get_linker_section
c7b8f16e 7376 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7377
c7b8f16e 7378 sec_data = elf32_arm_section_data (s);
906e58ca 7379
c7b8f16e 7380 BFD_ASSERT (s != NULL);
906e58ca 7381
21d799b5 7382 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7383 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7384
c7b8f16e 7385 BFD_ASSERT (tmp_name);
906e58ca 7386
c7b8f16e
JB		 7387 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7388 hash_table->num_vfp11_fixes);
906e58ca 7389
c7b8f16e
JB		 7390 myh = elf_link_hash_lookup
7391 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7392
c7b8f16e 7393 BFD_ASSERT (myh == NULL);
906e58ca 7394
c7b8f16e
JB		 7395 bh = NULL;
7396 val = hash_table->vfp11_erratum_glue_size;
7397 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7398 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7399 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7400
7401 myh = (struct elf_link_hash_entry *) bh;
7402 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7403 myh->forced_local = 1;
7404
7405 /* Link veneer back to calling location. */
c7e2358a 7406 sec_data->erratumcount += 1;
21d799b5
NC		 7407 newerr = (elf32_vfp11_erratum_list *)
7408 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7409
c7b8f16e
JB		 7410 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7411 newerr->vma = -1;
7412 newerr->u.v.branch = branch;
7413 newerr->u.v.id = hash_table->num_vfp11_fixes;
7414 branch->u.b.veneer = newerr;
7415
7416 newerr->next = sec_data->erratumlist;
7417 sec_data->erratumlist = newerr;
7418
7419 /* A symbol for the return from the veneer. */
7420 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7421 hash_table->num_vfp11_fixes);
7422
7423 myh = elf_link_hash_lookup
7424 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7425
c7b8f16e
JB		 7426 if (myh != NULL)
7427 abort ();
7428
7429 bh = NULL;
7430 val = offset + 4;
7431 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7432 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7433
c7b8f16e
JB		 7434 myh = (struct elf_link_hash_entry *) bh;
7435 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7436 myh->forced_local = 1;
7437
7438 free (tmp_name);
906e58ca 7439
c7b8f16e
JB		 7440 /* Generate a mapping symbol for the veneer section, and explicitly add an
7441 entry for that symbol to the code/data map for the section. */
7442 if (hash_table->vfp11_erratum_glue_size == 0)
7443 {
7444 bh = NULL;
7445 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7446 ever requires this erratum fix. */
c7b8f16e
JB		 7447 _bfd_generic_link_add_one_symbol (link_info,
7448 hash_table->bfd_of_glue_owner, "$a",
7449 BSF_LOCAL, s, 0, NULL,
99059e56 7450 TRUE, FALSE, &bh);
c7b8f16e
JB		 7451
7452 myh = (struct elf_link_hash_entry *) bh;
7453 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7454 myh->forced_local = 1;
906e58ca 7455
c7b8f16e 7456 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7457 BFDs. We must make a note of this generated mapping symbol
7458 ourselves so that code byteswapping works properly in
7459 elf32_arm_write_section. */
c7b8f16e
JB		 7460 elf32_arm_section_map_add (s, 'a', 0);
7461 }
906e58ca 7462
c7b8f16e
JB		 7463 s->size += VFP11_ERRATUM_VENEER_SIZE;
7464 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7465 hash_table->num_vfp11_fixes++;
906e58ca 7466
c7b8f16e
JB		 7467 /* The offset of the veneer. */
7468 return val;
7469}
7470
a504d23a
LA		 7471/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7472 veneers need to be handled because used only in Cortex-M. */
7473
7474static bfd_vma
7475record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7476 elf32_stm32l4xx_erratum_list *branch,
7477 bfd *branch_bfd,
7478 asection *branch_sec,
7479 unsigned int offset,
7480 bfd_size_type veneer_size)
7481{
7482 asection *s;
7483 struct elf32_arm_link_hash_table *hash_table;
7484 char *tmp_name;
7485 struct elf_link_hash_entry *myh;
7486 struct bfd_link_hash_entry *bh;
7487 bfd_vma val;
7488 struct _arm_elf_section_data *sec_data;
7489 elf32_stm32l4xx_erratum_list *newerr;
7490
7491 hash_table = elf32_arm_hash_table (link_info);
7492 BFD_ASSERT (hash_table != NULL);
7493 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7494
7495 s = bfd_get_linker_section
7496 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7497
7498 BFD_ASSERT (s != NULL);
7499
7500 sec_data = elf32_arm_section_data (s);
7501
7502 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7503 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7504
7505 BFD_ASSERT (tmp_name);
7506
7507 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7508 hash_table->num_stm32l4xx_fixes);
7509
7510 myh = elf_link_hash_lookup
7511 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7512
7513 BFD_ASSERT (myh == NULL);
7514
7515 bh = NULL;
7516 val = hash_table->stm32l4xx_erratum_glue_size;
7517 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7518 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7519 NULL, TRUE, FALSE, &bh);
7520
7521 myh = (struct elf_link_hash_entry *) bh;
7522 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7523 myh->forced_local = 1;
7524
7525 /* Link veneer back to calling location. */
7526 sec_data->stm32l4xx_erratumcount += 1;
7527 newerr = (elf32_stm32l4xx_erratum_list *)
7528 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7529
7530 newerr->type = STM32L4XX_ERRATUM_VENEER;
7531 newerr->vma = -1;
7532 newerr->u.v.branch = branch;
7533 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7534 branch->u.b.veneer = newerr;
7535
7536 newerr->next = sec_data->stm32l4xx_erratumlist;
7537 sec_data->stm32l4xx_erratumlist = newerr;
7538
7539 /* A symbol for the return from the veneer. */
7540 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7541 hash_table->num_stm32l4xx_fixes);
7542
7543 myh = elf_link_hash_lookup
7544 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7545
7546 if (myh != NULL)
7547 abort ();
7548
7549 bh = NULL;
7550 val = offset + 4;
7551 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7552 branch_sec, val, NULL, TRUE, FALSE, &bh);
7553
7554 myh = (struct elf_link_hash_entry *) bh;
7555 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7556 myh->forced_local = 1;
7557
7558 free (tmp_name);
7559
7560 /* Generate a mapping symbol for the veneer section, and explicitly add an
7561 entry for that symbol to the code/data map for the section. */
7562 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7563 {
7564 bh = NULL;
7565 /* Creates a THUMB symbol since there is no other choice. */
7566 _bfd_generic_link_add_one_symbol (link_info,
7567 hash_table->bfd_of_glue_owner, "$t",
7568 BSF_LOCAL, s, 0, NULL,
7569 TRUE, FALSE, &bh);
7570
7571 myh = (struct elf_link_hash_entry *) bh;
7572 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7573 myh->forced_local = 1;
7574
7575 /* The elf32_arm_init_maps function only cares about symbols from input
7576 BFDs. We must make a note of this generated mapping symbol
7577 ourselves so that code byteswapping works properly in
7578 elf32_arm_write_section. */
7579 elf32_arm_section_map_add (s, 't', 0);
7580 }
7581
7582 s->size += veneer_size;
7583 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7584 hash_table->num_stm32l4xx_fixes++;
7585
7586 /* The offset of the veneer. */
7587 return val;
7588}
7589
8029a119 7590#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7591 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7592 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7593
7594/* Create a fake section for use by the ARM backend of the linker. */
7595
7596static bfd_boolean
7597arm_make_glue_section (bfd * abfd, const char * name)
7598{
7599 asection * sec;
7600
3d4d4302 7601 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7602 if (sec != NULL)
7603 /* Already made. */
7604 return TRUE;
7605
3d4d4302 7606 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7607
7608 if (sec == NULL
7609 || !bfd_set_section_alignment (abfd, sec, 2))
7610 return FALSE;
7611
7612 /* Set the gc mark to prevent the section from being removed by garbage
7613 collection, despite the fact that no relocs refer to this section. */
7614 sec->gc_mark = 1;
7615
7616 return TRUE;
7617}
7618
1db37fe6
YG		 7619/* Set size of .plt entries. This function is called from the
7620 linker scripts in ld/emultempl/{armelf}.em. */
7621
7622void
7623bfd_elf32_arm_use_long_plt (void)
7624{
7625 elf32_arm_use_long_plt_entry = TRUE;
7626}
7627
8afb0e02
NC		 7628/* Add the glue sections to ABFD. This function is called from the
7629 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7630
b34976b6 7631bfd_boolean
57e8b36a
NC		 7632bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7633 struct bfd_link_info *info)
252b5132 7634{
a504d23a
LA		 7635 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7636 bfd_boolean dostm32l4xx = globals
7637 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7638 bfd_boolean addglue;
7639
8afb0e02
NC		 7640 /* If we are only performing a partial
7641 link do not bother adding the glue. */
0e1862bb 7642 if (bfd_link_relocatable (info))
b34976b6 7643 return TRUE;
252b5132 7644
a504d23a 7645 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7646 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7647 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7648 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7649
7650 if (!dostm32l4xx)
7651 return addglue;
7652
7653 return addglue
7654 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7655}
7656
daa4adae
TP		 7657/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7658 ensures they are not marked for deletion by
7659 strip_excluded_output_sections () when veneers are going to be created
7660 later. Not doing so would trigger assert on empty section size in
7661 lang_size_sections_1 (). */
7662
7663void
7664bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7665{
7666 enum elf32_arm_stub_type stub_type;
7667
7668 /* If we are only performing a partial
7669 link do not bother adding the glue. */
7670 if (bfd_link_relocatable (info))
7671 return;
7672
7673 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7674 {
7675 asection *out_sec;
7676 const char *out_sec_name;
7677
7678 if (!arm_dedicated_stub_output_section_required (stub_type))
7679 continue;
7680
7681 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7682 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7683 if (out_sec != NULL)
7684 out_sec->flags |= SEC_KEEP;
7685 }
7686}
7687
8afb0e02
NC		 7688/* Select a BFD to be used to hold the sections used by the glue code.
7689 This function is called from the linker scripts in ld/emultempl/
8029a119 7690 {armelf/pe}.em. */
8afb0e02 7691
b34976b6 7692bfd_boolean
57e8b36a 7693bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7694{
7695 struct elf32_arm_link_hash_table *globals;
7696
7697 /* If we are only performing a partial link
7698 do not bother getting a bfd to hold the glue. */
0e1862bb 7699 if (bfd_link_relocatable (info))
b34976b6 7700 return TRUE;
8afb0e02 7701
b7693d02
DJ		 7702 /* Make sure we don't attach the glue sections to a dynamic object. */
7703 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7704
8afb0e02 7705 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7706 BFD_ASSERT (globals != NULL);
7707
7708 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7709 return TRUE;
8afb0e02 7710
252b5132
RH		 7711 /* Save the bfd for later use. */
7712 globals->bfd_of_glue_owner = abfd;
cedb70c5 7713
b34976b6 7714 return TRUE;
252b5132
RH		 7715}
7716
906e58ca
NC		 7717static void
7718check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7719{
2de70689
MGD		 7720 int cpu_arch;
7721
b38cadfb 7722 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7723 Tag_CPU_arch);
7724
7725 if (globals->fix_arm1176)
7726 {
7727 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7728 globals->use_blx = 1;
7729 }
7730 else
7731 {
7732 if (cpu_arch > TAG_CPU_ARCH_V4T)
7733 globals->use_blx = 1;
7734 }
39b41c9c
PB		 7735}
7736
b34976b6 7737bfd_boolean
57e8b36a 7738bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7739 struct bfd_link_info *link_info)
252b5132
RH		 7740{
7741 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7742 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7743 Elf_Internal_Rela *irel, *irelend;
7744 bfd_byte *contents = NULL;
252b5132
RH		 7745
7746 asection *sec;
7747 struct elf32_arm_link_hash_table *globals;
7748
7749 /* If we are only performing a partial link do not bother
7750 to construct any glue. */
0e1862bb 7751 if (bfd_link_relocatable (link_info))
b34976b6 7752 return TRUE;
252b5132 7753
39ce1a6a
NC		 7754 /* Here we have a bfd that is to be included on the link. We have a
7755 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7756 globals = elf32_arm_hash_table (link_info);
252b5132 7757 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7758
7759 check_use_blx (globals);
252b5132 7760
d504ffc8 7761 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7762 {
90b6238f 7763 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7764 abfd);
e489d0ae
PB		 7765 return FALSE;
7766 }
f21f3fe0 7767
39ce1a6a
NC		 7768 /* PR 5398: If we have not decided to include any loadable sections in
7769 the output then we will not have a glue owner bfd. This is OK, it
7770 just means that there is nothing else for us to do here. */
7771 if (globals->bfd_of_glue_owner == NULL)
7772 return TRUE;
7773
252b5132
RH		 7774 /* Rummage around all the relocs and map the glue vectors. */
7775 sec = abfd->sections;
7776
7777 if (sec == NULL)
b34976b6 7778 return TRUE;
252b5132
RH		 7779
7780 for (; sec != NULL; sec = sec->next)
7781 {
7782 if (sec->reloc_count == 0)
7783 continue;
7784
2f475487
AM		 7785 if ((sec->flags & SEC_EXCLUDE) != 0)
7786 continue;
7787
0ffa91dd 7788 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7789
9b485d32 7790 /* Load the relocs. */
6cdc0ccc 7791 internal_relocs
906e58ca 7792 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7793
6cdc0ccc
AM		 7794 if (internal_relocs == NULL)
7795 goto error_return;
252b5132 7796
6cdc0ccc
AM		 7797 irelend = internal_relocs + sec->reloc_count;
7798 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7799 {
7800 long r_type;
7801 unsigned long r_index;
252b5132
RH		 7802
7803 struct elf_link_hash_entry *h;
7804
7805 r_type = ELF32_R_TYPE (irel->r_info);
7806 r_index = ELF32_R_SYM (irel->r_info);
7807
9b485d32 7808 /* These are the only relocation types we care about. */
ba96a88f 7809 if ( r_type != R_ARM_PC24
845b51d6 7810 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7811 continue;
7812
7813 /* Get the section contents if we haven't done so already. */
7814 if (contents == NULL)
7815 {
7816 /* Get cached copy if it exists. */
7817 if (elf_section_data (sec)->this_hdr.contents != NULL)
7818 contents = elf_section_data (sec)->this_hdr.contents;
7819 else
7820 {
7821 /* Go get them off disk. */
57e8b36a 7822 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7823 goto error_return;
7824 }
7825 }
7826
845b51d6
PB		 7827 if (r_type == R_ARM_V4BX)
7828 {
7829 int reg;
7830
7831 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7832 record_arm_bx_glue (link_info, reg);
7833 continue;
7834 }
7835
a7c10850 7836 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7837 h = NULL;
7838
9b485d32 7839 /* We don't care about local symbols. */
252b5132
RH		 7840 if (r_index < symtab_hdr->sh_info)
7841 continue;
7842
9b485d32 7843 /* This is an external symbol. */
252b5132
RH		 7844 r_index -= symtab_hdr->sh_info;
7845 h = (struct elf_link_hash_entry *)
7846 elf_sym_hashes (abfd)[r_index];
7847
7848 /* If the relocation is against a static symbol it must be within
7849 the current section and so cannot be a cross ARM/Thumb relocation. */
7850 if (h == NULL)
7851 continue;
7852
d504ffc8
DJ		 7853 /* If the call will go through a PLT entry then we do not need
7854 glue. */
362d30a1 7855 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7856 continue;
7857
252b5132
RH		 7858 switch (r_type)
7859 {
7860 case R_ARM_PC24:
7861 /* This one is a call from arm code. We need to look up
99059e56
RM		 7862 the target of the call. If it is a thumb target, we
7863 insert glue. */
39d911fc
TP		 7864 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7865 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7866 record_arm_to_thumb_glue (link_info, h);
7867 break;
7868
252b5132 7869 default:
c6596c5e 7870 abort ();
252b5132
RH		 7871 }
7872 }
6cdc0ccc
AM		 7873
7874 if (contents != NULL
7875 && elf_section_data (sec)->this_hdr.contents != contents)
7876 free (contents);
7877 contents = NULL;
7878
7879 if (internal_relocs != NULL
7880 && elf_section_data (sec)->relocs != internal_relocs)
7881 free (internal_relocs);
7882 internal_relocs = NULL;
252b5132
RH		 7883 }
7884
b34976b6 7885 return TRUE;
9a5aca8c 7886
252b5132 7887error_return:
6cdc0ccc
AM		 7888 if (contents != NULL
7889 && elf_section_data (sec)->this_hdr.contents != contents)
7890 free (contents);
7891 if (internal_relocs != NULL
7892 && elf_section_data (sec)->relocs != internal_relocs)
7893 free (internal_relocs);
9a5aca8c 7894
b34976b6 7895 return FALSE;
252b5132 7896}
7e392df6 7897#endif
252b5132 7898
eb043451 7899
c7b8f16e
JB		 7900/* Initialise maps of ARM/Thumb/data for input BFDs. */
7901
7902void
7903bfd_elf32_arm_init_maps (bfd *abfd)
7904{
7905 Elf_Internal_Sym *isymbuf;
7906 Elf_Internal_Shdr *hdr;
7907 unsigned int i, localsyms;
7908
af1f4419
NC		 7909 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7910 if (! is_arm_elf (abfd))
7911 return;
7912
c7b8f16e
JB		 7913 if ((abfd->flags & DYNAMIC) != 0)
7914 return;
7915
0ffa91dd 7916 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7917 localsyms = hdr->sh_info;
7918
7919 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7920 should contain the number of local symbols, which should come before any
7921 global symbols. Mapping symbols are always local. */
7922 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7923 NULL);
7924
7925 /* No internal symbols read? Skip this BFD. */
7926 if (isymbuf == NULL)
7927 return;
7928
7929 for (i = 0; i < localsyms; i++)
7930 {
7931 Elf_Internal_Sym *isym = &isymbuf[i];
7932 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7933 const char *name;
906e58ca 7934
c7b8f16e 7935 if (sec != NULL
99059e56
RM		 7936 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7937 {
7938 name = bfd_elf_string_from_elf_section (abfd,
7939 hdr->sh_link, isym->st_name);
906e58ca 7940
99059e56 7941 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7942 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7943 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7944 }
c7b8f16e
JB		 7945 }
7946}
7947
7948
48229727
JB		 7949/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7950 say what they wanted. */
7951
7952void
7953bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7954{
7955 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7956 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7957
4dfe6ac6
NC		 7958 if (globals == NULL)
7959 return;
7960
48229727
JB		 7961 if (globals->fix_cortex_a8 == -1)
7962 {
7963 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7964 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7965 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7966 || out_attr[Tag_CPU_arch_profile].i == 0))
7967 globals->fix_cortex_a8 = 1;
7968 else
7969 globals->fix_cortex_a8 = 0;
7970 }
7971}
7972
7973
c7b8f16e
JB		 7974void
7975bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
7976{
7977 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 7978 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 7979
4dfe6ac6
NC		 7980 if (globals == NULL)
7981 return;
c7b8f16e
JB		 7982 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
7983 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
7984 {
7985 switch (globals->vfp11_fix)
99059e56
RM		 7986 {
7987 case BFD_ARM_VFP11_FIX_DEFAULT:
7988 case BFD_ARM_VFP11_FIX_NONE:
7989 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7990 break;
7991
7992 default:
7993 /* Give a warning, but do as the user requests anyway. */
871b3ab2 7994 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 7995 "workaround is not necessary for target architecture"), obfd);
7996 }
c7b8f16e
JB		 7997 }
7998 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
7999 /* For earlier architectures, we might need the workaround, but do not
8000 enable it by default. If users is running with broken hardware, they
8001 must enable the erratum fix explicitly. */
8002 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8003}
8004
a504d23a
LA		 8005void
8006bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8007{
8008 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8009 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8010
8011 if (globals == NULL)
8012 return;
8013
8014 /* We assume only Cortex-M4 may require the fix. */
8015 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8016 || out_attr[Tag_CPU_arch_profile].i != 'M')
8017 {
8018 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8019 /* Give a warning, but do as the user requests anyway. */
4eca0228 8020 _bfd_error_handler
871b3ab2 8021 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 8022 "workaround is not necessary for target architecture"), obfd);
8023 }
8024}
c7b8f16e 8025
906e58ca
NC		 8026enum bfd_arm_vfp11_pipe
8027{
c7b8f16e
JB		 8028 VFP11_FMAC,
8029 VFP11_LS,
8030 VFP11_DS,
8031 VFP11_BAD
8032};
8033
8034/* Return a VFP register number. This is encoded as RX:X for single-precision
8035 registers, or X:RX for double-precision registers, where RX is the group of
8036 four bits in the instruction encoding and X is the single extension bit.
8037 RX and X fields are specified using their lowest (starting) bit. The return
8038 value is:
8039
8040 0...31: single-precision registers s0...s31
8041 32...63: double-precision registers d0...d31.
906e58ca 8042
c7b8f16e
JB		 8043 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8044 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 8045
c7b8f16e
JB		 8046static unsigned int
8047bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 8048 unsigned int x)
c7b8f16e
JB		 8049{
8050 if (is_double)
8051 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8052 else
8053 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8054}
8055
8056/* Set bits in *WMASK according to a register number REG as encoded by
8057 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8058
8059static void
8060bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8061{
8062 if (reg < 32)
8063 *wmask |= 1 << reg;
8064 else if (reg < 48)
8065 *wmask |= 3 << ((reg - 32) * 2);
8066}
8067
8068/* Return TRUE if WMASK overwrites anything in REGS. */
8069
8070static bfd_boolean
8071bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8072{
8073 int i;
906e58ca 8074
c7b8f16e
JB		 8075 for (i = 0; i < numregs; i++)
8076 {
8077 unsigned int reg = regs[i];
8078
8079 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 8080 return TRUE;
906e58ca 8081
c7b8f16e
JB		 8082 reg -= 32;
8083
8084 if (reg >= 16)
99059e56 8085 continue;
906e58ca 8086
c7b8f16e 8087 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 8088 return TRUE;
c7b8f16e 8089 }
906e58ca 8090
c7b8f16e
JB		 8091 return FALSE;
8092}
8093
8094/* In this function, we're interested in two things: finding input registers
8095 for VFP data-processing instructions, and finding the set of registers which
8096 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8097 hold the written set, so FLDM etc. are easy to deal with (we're only
8098 interested in 32 SP registers or 16 dp registers, due to the VFP version
8099 implemented by the chip in question). DP registers are marked by setting
8100 both SP registers in the write mask). */
8101
8102static enum bfd_arm_vfp11_pipe
8103bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 8104 int *numregs)
c7b8f16e 8105{
91d6fa6a 8106 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 8107 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8108
8109 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8110 {
8111 unsigned int pqrs;
8112 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8113 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8114
8115 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 8116 | ((insn & 0x00300000) >> 19)
8117 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 8118
8119 switch (pqrs)
99059e56
RM		 8120 {
8121 case 0: /* fmac[sd]. */
8122 case 1: /* fnmac[sd]. */
8123 case 2: /* fmsc[sd]. */
8124 case 3: /* fnmsc[sd]. */
8125 vpipe = VFP11_FMAC;
8126 bfd_arm_vfp11_write_mask (destmask, fd);
8127 regs[0] = fd;
8128 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8129 regs[2] = fm;
8130 *numregs = 3;
8131 break;
8132
8133 case 4: /* fmul[sd]. */
8134 case 5: /* fnmul[sd]. */
8135 case 6: /* fadd[sd]. */
8136 case 7: /* fsub[sd]. */
8137 vpipe = VFP11_FMAC;
8138 goto vfp_binop;
8139
8140 case 8: /* fdiv[sd]. */
8141 vpipe = VFP11_DS;
8142 vfp_binop:
8143 bfd_arm_vfp11_write_mask (destmask, fd);
8144 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8145 regs[1] = fm;
8146 *numregs = 2;
8147 break;
8148
8149 case 15: /* extended opcode. */
8150 {
8151 unsigned int extn = ((insn >> 15) & 0x1e)
8152 | ((insn >> 7) & 1);
8153
8154 switch (extn)
8155 {
8156 case 0: /* fcpy[sd]. */
8157 case 1: /* fabs[sd]. */
8158 case 2: /* fneg[sd]. */
8159 case 8: /* fcmp[sd]. */
8160 case 9: /* fcmpe[sd]. */
8161 case 10: /* fcmpz[sd]. */
8162 case 11: /* fcmpez[sd]. */
8163 case 16: /* fuito[sd]. */
8164 case 17: /* fsito[sd]. */
8165 case 24: /* ftoui[sd]. */
8166 case 25: /* ftouiz[sd]. */
8167 case 26: /* ftosi[sd]. */
8168 case 27: /* ftosiz[sd]. */
8169 /* These instructions will not bounce due to underflow. */
8170 *numregs = 0;
8171 vpipe = VFP11_FMAC;
8172 break;
8173
8174 case 3: /* fsqrt[sd]. */
8175 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8176 registers to cause the erratum in previous instructions. */
8177 bfd_arm_vfp11_write_mask (destmask, fd);
8178 vpipe = VFP11_DS;
8179 break;
8180
8181 case 15: /* fcvt{ds,sd}. */
8182 {
8183 int rnum = 0;
8184
8185 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8186
8187 /* Only FCVTSD can underflow. */
99059e56
RM		 8188 if ((insn & 0x100) != 0)
8189 regs[rnum++] = fm;
c7b8f16e 8190
99059e56 8191 *numregs = rnum;
c7b8f16e 8192
99059e56
RM		 8193 vpipe = VFP11_FMAC;
8194 }
8195 break;
c7b8f16e 8196
99059e56
RM		 8197 default:
8198 return VFP11_BAD;
8199 }
8200 }
8201 break;
c7b8f16e 8202
99059e56
RM		 8203 default:
8204 return VFP11_BAD;
8205 }
c7b8f16e
JB		 8206 }
8207 /* Two-register transfer. */
8208 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8209 {
8210 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8211
c7b8f16e
JB		 8212 if ((insn & 0x100000) == 0)
8213 {
99059e56
RM		 8214 if (is_double)
8215 bfd_arm_vfp11_write_mask (destmask, fm);
8216 else
8217 {
8218 bfd_arm_vfp11_write_mask (destmask, fm);
8219 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8220 }
c7b8f16e
JB		 8221 }
8222
91d6fa6a 8223 vpipe = VFP11_LS;
c7b8f16e
JB		 8224 }
8225 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8226 {
8227 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8228 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8229
c7b8f16e 8230 switch (puw)
99059e56
RM		 8231 {
8232 case 0: /* Two-reg transfer. We should catch these above. */
8233 abort ();
906e58ca 8234
99059e56
RM		 8235 case 2: /* fldm[sdx]. */
8236 case 3:
8237 case 5:
8238 {
8239 unsigned int i, offset = insn & 0xff;
c7b8f16e 8240
99059e56
RM		 8241 if (is_double)
8242 offset >>= 1;
c7b8f16e 8243
99059e56
RM		 8244 for (i = fd; i < fd + offset; i++)
8245 bfd_arm_vfp11_write_mask (destmask, i);
8246 }
8247 break;
906e58ca 8248
99059e56
RM		 8249 case 4: /* fld[sd]. */
8250 case 6:
8251 bfd_arm_vfp11_write_mask (destmask, fd);
8252 break;
906e58ca 8253
99059e56
RM		 8254 default:
8255 return VFP11_BAD;
8256 }
c7b8f16e 8257
91d6fa6a 8258 vpipe = VFP11_LS;
c7b8f16e
JB		 8259 }
8260 /* Single-register transfer. Note L==0. */
8261 else if ((insn & 0x0f100e10) == 0x0e000a10)
8262 {
8263 unsigned int opcode = (insn >> 21) & 7;
8264 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8265
8266 switch (opcode)
99059e56
RM		 8267 {
8268 case 0: /* fmsr/fmdlr. */
8269 case 1: /* fmdhr. */
8270 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8271 destination register. I don't know if this is exactly right,
8272 but it is the conservative choice. */
8273 bfd_arm_vfp11_write_mask (destmask, fn);
8274 break;
8275
8276 case 7: /* fmxr. */
8277 break;
8278 }
c7b8f16e 8279
91d6fa6a 8280 vpipe = VFP11_LS;
c7b8f16e
JB		 8281 }
8282
91d6fa6a 8283 return vpipe;
c7b8f16e
JB		 8284}
8285
8286
8287static int elf32_arm_compare_mapping (const void * a, const void * b);
8288
8289
8290/* Look for potentially-troublesome code sequences which might trigger the
8291 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8292 (available from ARM) for details of the erratum. A short version is
8293 described in ld.texinfo. */
8294
8295bfd_boolean
8296bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8297{
8298 asection *sec;
8299 bfd_byte *contents = NULL;
8300 int state = 0;
8301 int regs[3], numregs = 0;
8302 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8303 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8304
4dfe6ac6
NC		 8305 if (globals == NULL)
8306 return FALSE;
8307
c7b8f16e
JB		 8308 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8309 The states transition as follows:
906e58ca 8310
c7b8f16e 8311 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8312 A VFP FMAC-pipeline instruction has been seen. Fill
8313 regs[0]..regs[numregs-1] with its input operands. Remember this
8314 instruction in 'first_fmac'.
c7b8f16e
JB		 8315
8316 1 -> 2
99059e56
RM		 8317 Any instruction, except for a VFP instruction which overwrites
8318 regs[*].
906e58ca 8319
c7b8f16e
JB		 8320 1 -> 3 [ -> 0 ] or
8321 2 -> 3 [ -> 0 ]
99059e56
RM		 8322 A VFP instruction has been seen which overwrites any of regs[*].
8323 We must make a veneer! Reset state to 0 before examining next
8324 instruction.
906e58ca 8325
c7b8f16e 8326 2 -> 0
99059e56
RM		 8327 If we fail to match anything in state 2, reset to state 0 and reset
8328 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8329
8330 If the VFP11 vector mode is in use, there must be at least two unrelated
8331 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8332 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8333
8334 /* If we are only performing a partial link do not bother
8335 to construct any glue. */
0e1862bb 8336 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8337 return TRUE;
8338
0ffa91dd
NC		 8339 /* Skip if this bfd does not correspond to an ELF image. */
8340 if (! is_arm_elf (abfd))
8341 return TRUE;
906e58ca 8342
c7b8f16e
JB		 8343 /* We should have chosen a fix type by the time we get here. */
8344 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8345
8346 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8347 return TRUE;
2e6030b9 8348
33a7ffc2
JM		 8349 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8350 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8351 return TRUE;
8352
c7b8f16e
JB		 8353 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8354 {
8355 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8356 struct _arm_elf_section_data *sec_data;
8357
8358 /* If we don't have executable progbits, we're not interested in this
99059e56 8359 section. Also skip if section is to be excluded. */
c7b8f16e 8360 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8361 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8362 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8363 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8364 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8365 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8366 continue;
c7b8f16e
JB		 8367
8368 sec_data = elf32_arm_section_data (sec);
906e58ca 8369
c7b8f16e 8370 if (sec_data->mapcount == 0)
99059e56 8371 continue;
906e58ca 8372
c7b8f16e
JB		 8373 if (elf_section_data (sec)->this_hdr.contents != NULL)
8374 contents = elf_section_data (sec)->this_hdr.contents;
8375 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8376 goto error_return;
8377
8378 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8379 elf32_arm_compare_mapping);
8380
8381 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8382 {
8383 unsigned int span_start = sec_data->map[span].vma;
8384 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8385 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8386 char span_type = sec_data->map[span].type;
8387
8388 /* FIXME: Only ARM mode is supported at present. We may need to
8389 support Thumb-2 mode also at some point. */
8390 if (span_type != 'a')
8391 continue;
8392
8393 for (i = span_start; i < span_end;)
8394 {
8395 unsigned int next_i = i + 4;
8396 unsigned int insn = bfd_big_endian (abfd)
8397 ? (contents[i] << 24)
8398 | (contents[i + 1] << 16)
8399 | (contents[i + 2] << 8)
8400 | contents[i + 3]
8401 : (contents[i + 3] << 24)
8402 | (contents[i + 2] << 16)
8403 | (contents[i + 1] << 8)
8404 | contents[i];
8405 unsigned int writemask = 0;
8406 enum bfd_arm_vfp11_pipe vpipe;
8407
8408 switch (state)
8409 {
8410 case 0:
8411 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8412 &numregs);
8413 /* I'm assuming the VFP11 erratum can trigger with denorm
8414 operands on either the FMAC or the DS pipeline. This might
8415 lead to slightly overenthusiastic veneer insertion. */
8416 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8417 {
8418 state = use_vector ? 1 : 2;
8419 first_fmac = i;
8420 veneer_of_insn = insn;
8421 }
8422 break;
8423
8424 case 1:
8425 {
8426 int other_regs[3], other_numregs;
8427 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8428 other_regs,
99059e56
RM		 8429 &other_numregs);
8430 if (vpipe != VFP11_BAD
8431 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8432 numregs))
99059e56
RM		 8433 state = 3;
8434 else
8435 state = 2;
8436 }
8437 break;
8438
8439 case 2:
8440 {
8441 int other_regs[3], other_numregs;
8442 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8443 other_regs,
99059e56
RM		 8444 &other_numregs);
8445 if (vpipe != VFP11_BAD
8446 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8447 numregs))
99059e56
RM		 8448 state = 3;
8449 else
8450 {
8451 state = 0;
8452 next_i = first_fmac + 4;
8453 }
8454 }
8455 break;
8456
8457 case 3:
8458 abort (); /* Should be unreachable. */
8459 }
8460
8461 if (state == 3)
8462 {
8463 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8464 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8465
8466 elf32_arm_section_data (sec)->erratumcount += 1;
8467
8468 newerr->u.b.vfp_insn = veneer_of_insn;
8469
8470 switch (span_type)
8471 {
8472 case 'a':
8473 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8474 break;
8475
8476 default:
8477 abort ();
8478 }
8479
8480 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8481 first_fmac);
8482
99059e56 8483 newerr->vma = -1;
c7b8f16e 8484
99059e56
RM		 8485 newerr->next = sec_data->erratumlist;
8486 sec_data->erratumlist = newerr;
c7b8f16e 8487
99059e56
RM		 8488 state = 0;
8489 }
c7b8f16e 8490
99059e56
RM		 8491 i = next_i;
8492 }
8493 }
906e58ca 8494
c7b8f16e 8495 if (contents != NULL
99059e56
RM		 8496 && elf_section_data (sec)->this_hdr.contents != contents)
8497 free (contents);
c7b8f16e
JB		 8498 contents = NULL;
8499 }
8500
8501 return TRUE;
8502
8503error_return:
8504 if (contents != NULL
8505 && elf_section_data (sec)->this_hdr.contents != contents)
8506 free (contents);
906e58ca 8507
c7b8f16e
JB		 8508 return FALSE;
8509}
8510
8511/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8512 after sections have been laid out, using specially-named symbols. */
8513
8514void
8515bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8516 struct bfd_link_info *link_info)
8517{
8518 asection *sec;
8519 struct elf32_arm_link_hash_table *globals;
8520 char *tmp_name;
906e58ca 8521
0e1862bb 8522 if (bfd_link_relocatable (link_info))
c7b8f16e 8523 return;
2e6030b9
MS		 8524
8525 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8526 if (! is_arm_elf (abfd))
2e6030b9
MS		 8527 return;
8528
c7b8f16e 8529 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8530 if (globals == NULL)
8531 return;
906e58ca 8532
21d799b5 8533 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8534 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8535
8536 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8537 {
8538 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8539 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8540
c7b8f16e 8541 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8542 {
8543 struct elf_link_hash_entry *myh;
8544 bfd_vma vma;
8545
8546 switch (errnode->type)
8547 {
8548 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8549 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8550 /* Find veneer symbol. */
8551 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8552 errnode->u.b.veneer->u.v.id);
8553
99059e56
RM		 8554 myh = elf_link_hash_lookup
8555 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8556
a504d23a 8557 if (myh == NULL)
90b6238f
AM		 8558 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8559 abfd, "VFP11", tmp_name);
a504d23a
LA		 8560
8561 vma = myh->root.u.def.section->output_section->vma
8562 + myh->root.u.def.section->output_offset
8563 + myh->root.u.def.value;
8564
8565 errnode->u.b.veneer->vma = vma;
8566 break;
8567
8568 case VFP11_ERRATUM_ARM_VENEER:
8569 case VFP11_ERRATUM_THUMB_VENEER:
8570 /* Find return location. */
8571 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8572 errnode->u.v.id);
8573
8574 myh = elf_link_hash_lookup
8575 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8576
8577 if (myh == NULL)
90b6238f
AM		 8578 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8579 abfd, "VFP11", tmp_name);
a504d23a
LA		 8580
8581 vma = myh->root.u.def.section->output_section->vma
8582 + myh->root.u.def.section->output_offset
8583 + myh->root.u.def.value;
8584
8585 errnode->u.v.branch->vma = vma;
8586 break;
8587
8588 default:
8589 abort ();
8590 }
8591 }
8592 }
8593
8594 free (tmp_name);
8595}
8596
8597/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8598 return locations after sections have been laid out, using
8599 specially-named symbols. */
8600
8601void
8602bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8603 struct bfd_link_info *link_info)
8604{
8605 asection *sec;
8606 struct elf32_arm_link_hash_table *globals;
8607 char *tmp_name;
8608
8609 if (bfd_link_relocatable (link_info))
8610 return;
8611
8612 /* Skip if this bfd does not correspond to an ELF image. */
8613 if (! is_arm_elf (abfd))
8614 return;
8615
8616 globals = elf32_arm_hash_table (link_info);
8617 if (globals == NULL)
8618 return;
8619
8620 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8621 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8622
8623 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8624 {
8625 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8626 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8627
8628 for (; errnode != NULL; errnode = errnode->next)
8629 {
8630 struct elf_link_hash_entry *myh;
8631 bfd_vma vma;
8632
8633 switch (errnode->type)
8634 {
8635 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8636 /* Find veneer symbol. */
8637 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8638 errnode->u.b.veneer->u.v.id);
8639
8640 myh = elf_link_hash_lookup
8641 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8642
8643 if (myh == NULL)
90b6238f
AM		 8644 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8645 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8646
8647 vma = myh->root.u.def.section->output_section->vma
8648 + myh->root.u.def.section->output_offset
8649 + myh->root.u.def.value;
8650
8651 errnode->u.b.veneer->vma = vma;
8652 break;
8653
8654 case STM32L4XX_ERRATUM_VENEER:
8655 /* Find return location. */
8656 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8657 errnode->u.v.id);
8658
8659 myh = elf_link_hash_lookup
8660 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8661
8662 if (myh == NULL)
90b6238f
AM		 8663 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8664 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8665
8666 vma = myh->root.u.def.section->output_section->vma
8667 + myh->root.u.def.section->output_offset
8668 + myh->root.u.def.value;
8669
8670 errnode->u.v.branch->vma = vma;
8671 break;
8672
8673 default:
8674 abort ();
8675 }
8676 }
8677 }
8678
8679 free (tmp_name);
8680}
8681
8682static inline bfd_boolean
8683is_thumb2_ldmia (const insn32 insn)
8684{
8685 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8686 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8687 return (insn & 0xffd02000) == 0xe8900000;
8688}
8689
8690static inline bfd_boolean
8691is_thumb2_ldmdb (const insn32 insn)
8692{
8693 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8694 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8695 return (insn & 0xffd02000) == 0xe9100000;
8696}
8697
8698static inline bfd_boolean
8699is_thumb2_vldm (const insn32 insn)
8700{
8701 /* A6.5 Extension register load or store instruction
8702 A7.7.229
9239bbd3
CM		 8703 We look for SP 32-bit and DP 64-bit registers.
8704 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8705 <list> is consecutive 64-bit registers
8706 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8707 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8708 <list> is consecutive 32-bit registers
8709 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8710 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8711 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8712 return
9239bbd3
CM		 8713 (((insn & 0xfe100f00) == 0xec100b00) ||
8714 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8715 && /* (IA without !). */
8716 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8717 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8718 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8719 /* (DB with !). */
8720 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8721}
8722
8723/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8724 VLDM opcode and:
8725 - computes the number and the mode of memory accesses
8726 - decides if the replacement should be done:
8727 . replaces only if > 8-word accesses
8728 . or (testing purposes only) replaces all accesses. */
8729
8730static bfd_boolean
8731stm32l4xx_need_create_replacing_stub (const insn32 insn,
8732 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8733{
9239bbd3 8734 int nb_words = 0;
a504d23a
LA		 8735
8736 /* The field encoding the register list is the same for both LDMIA
8737 and LDMDB encodings. */
8738 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8739 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8740 else if (is_thumb2_vldm (insn))
9239bbd3 8741 nb_words = (insn & 0xff);
a504d23a
LA		 8742
8743 /* DEFAULT mode accounts for the real bug condition situation,
8744 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8745 return
9239bbd3 8746 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8747 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8748}
8749
8750/* Look for potentially-troublesome code sequences which might trigger
8751 the STM STM32L4XX erratum. */
8752
8753bfd_boolean
8754bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8755 struct bfd_link_info *link_info)
8756{
8757 asection *sec;
8758 bfd_byte *contents = NULL;
8759 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8760
8761 if (globals == NULL)
8762 return FALSE;
8763
8764 /* If we are only performing a partial link do not bother
8765 to construct any glue. */
8766 if (bfd_link_relocatable (link_info))
8767 return TRUE;
8768
8769 /* Skip if this bfd does not correspond to an ELF image. */
8770 if (! is_arm_elf (abfd))
8771 return TRUE;
8772
8773 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8774 return TRUE;
8775
8776 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8777 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8778 return TRUE;
8779
8780 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8781 {
8782 unsigned int i, span;
8783 struct _arm_elf_section_data *sec_data;
8784
8785 /* If we don't have executable progbits, we're not interested in this
8786 section. Also skip if section is to be excluded. */
8787 if (elf_section_type (sec) != SHT_PROGBITS
8788 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8789 || (sec->flags & SEC_EXCLUDE) != 0
8790 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8791 || sec->output_section == bfd_abs_section_ptr
8792 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8793 continue;
8794
8795 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8796
a504d23a
LA		 8797 if (sec_data->mapcount == 0)
8798 continue;
c7b8f16e 8799
a504d23a
LA		 8800 if (elf_section_data (sec)->this_hdr.contents != NULL)
8801 contents = elf_section_data (sec)->this_hdr.contents;
8802 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8803 goto error_return;
c7b8f16e 8804
a504d23a
LA		 8805 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8806 elf32_arm_compare_mapping);
c7b8f16e 8807
a504d23a
LA		 8808 for (span = 0; span < sec_data->mapcount; span++)
8809 {
8810 unsigned int span_start = sec_data->map[span].vma;
8811 unsigned int span_end = (span == sec_data->mapcount - 1)
8812 ? sec->size : sec_data->map[span + 1].vma;
8813 char span_type = sec_data->map[span].type;
8814 int itblock_current_pos = 0;
c7b8f16e 8815
a504d23a
LA		 8816 /* Only Thumb2 mode need be supported with this CM4 specific
8817 code, we should not encounter any arm mode eg span_type
8818 != 'a'. */
8819 if (span_type != 't')
8820 continue;
c7b8f16e 8821
a504d23a
LA		 8822 for (i = span_start; i < span_end;)
8823 {
8824 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8825 bfd_boolean insn_32bit = FALSE;
8826 bfd_boolean is_ldm = FALSE;
8827 bfd_boolean is_vldm = FALSE;
8828 bfd_boolean is_not_last_in_it_block = FALSE;
8829
8830 /* The first 16-bits of all 32-bit thumb2 instructions start
8831 with opcode[15..13]=0b111 and the encoded op1 can be anything
8832 except opcode[12..11]!=0b00.
8833 See 32-bit Thumb instruction encoding. */
8834 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8835 insn_32bit = TRUE;
c7b8f16e 8836
a504d23a
LA		 8837 /* Compute the predicate that tells if the instruction
8838 is concerned by the IT block
8839 - Creates an error if there is a ldm that is not
8840 last in the IT block thus cannot be replaced
8841 - Otherwise we can create a branch at the end of the
8842 IT block, it will be controlled naturally by IT
8843 with the proper pseudo-predicate
8844 - So the only interesting predicate is the one that
8845 tells that we are not on the last item of an IT
8846 block. */
8847 if (itblock_current_pos != 0)
8848 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8849
a504d23a
LA		 8850 if (insn_32bit)
8851 {
8852 /* Load the rest of the insn (in manual-friendly order). */
8853 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8854 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8855 is_vldm = is_thumb2_vldm (insn);
8856
8857 /* Veneers are created for (v)ldm depending on
8858 option flags and memory accesses conditions; but
8859 if the instruction is not the last instruction of
8860 an IT block, we cannot create a jump there, so we
8861 bail out. */
5025eb7c
AO		 8862 if ((is_ldm || is_vldm)
8863 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8864 (insn, globals->stm32l4xx_fix))
8865 {
8866 if (is_not_last_in_it_block)
8867 {
4eca0228 8868 _bfd_error_handler
695344c0 8869 /* xgettext:c-format */
871b3ab2 8870 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8871 " in non-last IT block instruction:"
8872 " STM32L4XX veneer cannot be generated; "
8873 "use gcc option -mrestrict-it to generate"
8874 " only one instruction per IT block"),
d42c267e 8875 abfd, sec, i);
a504d23a
LA		 8876 }
8877 else
8878 {
8879 elf32_stm32l4xx_erratum_list *newerr =
8880 (elf32_stm32l4xx_erratum_list *)
8881 bfd_zmalloc
8882 (sizeof (elf32_stm32l4xx_erratum_list));
8883
8884 elf32_arm_section_data (sec)
8885 ->stm32l4xx_erratumcount += 1;
8886 newerr->u.b.insn = insn;
8887 /* We create only thumb branches. */
8888 newerr->type =
8889 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8890 record_stm32l4xx_erratum_veneer
8891 (link_info, newerr, abfd, sec,
8892 i,
8893 is_ldm ?
8894 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8895 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8896 newerr->vma = -1;
8897 newerr->next = sec_data->stm32l4xx_erratumlist;
8898 sec_data->stm32l4xx_erratumlist = newerr;
8899 }
8900 }
8901 }
8902 else
8903 {
8904 /* A7.7.37 IT p208
8905 IT blocks are only encoded in T1
8906 Encoding T1: IT{x{y{z}}} <firstcond>
8907 1 0 1 1 - 1 1 1 1 - firstcond - mask
8908 if mask = '0000' then see 'related encodings'
8909 We don't deal with UNPREDICTABLE, just ignore these.
8910 There can be no nested IT blocks so an IT block
8911 is naturally a new one for which it is worth
8912 computing its size. */
5025eb7c
AO		 8913 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8914 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8915 /* If we have a new IT block we compute its size. */
8916 if (is_newitblock)
8917 {
8918 /* Compute the number of instructions controlled
8919 by the IT block, it will be used to decide
8920 whether we are inside an IT block or not. */
8921 unsigned int mask = insn & 0x000f;
8922 itblock_current_pos = 4 - ctz (mask);
8923 }
8924 }
8925
8926 i += insn_32bit ? 4 : 2;
99059e56
RM		 8927 }
8928 }
a504d23a
LA		 8929
8930 if (contents != NULL
8931 && elf_section_data (sec)->this_hdr.contents != contents)
8932 free (contents);
8933 contents = NULL;
c7b8f16e 8934 }
906e58ca 8935
a504d23a
LA		 8936 return TRUE;
8937
8938error_return:
8939 if (contents != NULL
8940 && elf_section_data (sec)->this_hdr.contents != contents)
8941 free (contents);
c7b8f16e 8942
a504d23a
LA		 8943 return FALSE;
8944}
c7b8f16e 8945
eb043451
PB		 8946/* Set target relocation values needed during linking. */
8947
8948void
68c39892 8949bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 8950 struct bfd_link_info *link_info,
68c39892 8951 struct elf32_arm_params *params)
eb043451
PB		 8952{
8953 struct elf32_arm_link_hash_table *globals;
8954
8955 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8956 if (globals == NULL)
8957 return;
eb043451 8958
68c39892
TP		 8959 globals->target1_is_rel = params->target1_is_rel;
8960 if (strcmp (params->target2_type, "rel") == 0)
eb043451 8961 globals->target2_reloc = R_ARM_REL32;
68c39892 8962 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 8963 globals->target2_reloc = R_ARM_ABS32;
68c39892 8964 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 8965 globals->target2_reloc = R_ARM_GOT_PREL;
8966 else
8967 {
90b6238f 8968 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 8969 params->target2_type);
eb043451 8970 }
68c39892
TP		 8971 globals->fix_v4bx = params->fix_v4bx;
8972 globals->use_blx |= params->use_blx;
8973 globals->vfp11_fix = params->vfp11_denorm_fix;
8974 globals->stm32l4xx_fix = params->stm32l4xx_fix;
e8b09b87
CL		 8975 if (globals->fdpic_p)
8976 globals->pic_veneer = 1;
8977 else
8978 globals->pic_veneer = params->pic_veneer;
68c39892
TP		 8979 globals->fix_cortex_a8 = params->fix_cortex_a8;
8980 globals->fix_arm1176 = params->fix_arm1176;
8981 globals->cmse_implib = params->cmse_implib;
8982 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 8983
0ffa91dd 8984 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 8985 elf_arm_tdata (output_bfd)->no_enum_size_warning
8986 = params->no_enum_size_warning;
8987 elf_arm_tdata (output_bfd)->no_wchar_size_warning
8988 = params->no_wchar_size_warning;
eb043451 8989}
eb043451 8990
12a0a0fd 8991/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 8992
12a0a0fd
PB		 8993static void
8994insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
8995{
8996 bfd_vma upper;
8997 bfd_vma lower;
8998 int reloc_sign;
8999
9000 BFD_ASSERT ((offset & 1) == 0);
9001
9002 upper = bfd_get_16 (abfd, insn);
9003 lower = bfd_get_16 (abfd, insn + 2);
9004 reloc_sign = (offset < 0) ? 1 : 0;
9005 upper = (upper & ~(bfd_vma) 0x7ff)
9006 | ((offset >> 12) & 0x3ff)
9007 | (reloc_sign << 10);
906e58ca 9008 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 9009 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9010 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9011 | ((offset >> 1) & 0x7ff);
9012 bfd_put_16 (abfd, upper, insn);
9013 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 9014}
9015
9b485d32
NC		 9016/* Thumb code calling an ARM function. */
9017
252b5132 9018static int
57e8b36a 9019elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9020 const char * name,
9021 bfd * input_bfd,
9022 bfd * output_bfd,
9023 asection * input_section,
9024 bfd_byte * hit_data,
9025 asection * sym_sec,
9026 bfd_vma offset,
9027 bfd_signed_vma addend,
9028 bfd_vma val,
f2a9dd69 9029 char **error_message)
252b5132 9030{
bcbdc74c 9031 asection * s = 0;
dc810e39 9032 bfd_vma my_offset;
252b5132 9033 long int ret_offset;
bcbdc74c
NC		 9034 struct elf_link_hash_entry * myh;
9035 struct elf32_arm_link_hash_table * globals;
252b5132 9036
f2a9dd69 9037 myh = find_thumb_glue (info, name, error_message);
252b5132 9038 if (myh == NULL)
b34976b6 9039 return FALSE;
252b5132
RH		 9040
9041 globals = elf32_arm_hash_table (info);
252b5132
RH		 9042 BFD_ASSERT (globals != NULL);
9043 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9044
9045 my_offset = myh->root.u.def.value;
9046
3d4d4302
AM		 9047 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9048 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 9049
9050 BFD_ASSERT (s != NULL);
9051 BFD_ASSERT (s->contents != NULL);
9052 BFD_ASSERT (s->output_section != NULL);
9053
9054 if ((my_offset & 0x01) == 0x01)
9055 {
9056 if (sym_sec != NULL
9057 && sym_sec->owner != NULL
9058 && !INTERWORK_FLAG (sym_sec->owner))
9059 {
4eca0228 9060 _bfd_error_handler
90b6238f
AM		 9061 (_("%pB(%s): warning: interworking not enabled;"
9062 " first occurrence: %pB: %s call to %s"),
9063 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 9064
b34976b6 9065 return FALSE;
252b5132
RH		 9066 }
9067
9068 --my_offset;
9069 myh->root.u.def.value = my_offset;
9070
52ab56c2
PB		 9071 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9072 s->contents + my_offset);
252b5132 9073
52ab56c2
PB		 9074 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9075 s->contents + my_offset + 2);
252b5132
RH		 9076
9077 ret_offset =
9b485d32
NC		 9078 /* Address of destination of the stub. */
9079 ((bfd_signed_vma) val)
252b5132 9080 - ((bfd_signed_vma)
57e8b36a
NC		 9081 /* Offset from the start of the current section
9082 to the start of the stubs. */
9b485d32
NC		 9083 (s->output_offset
9084 /* Offset of the start of this stub from the start of the stubs. */
9085 + my_offset
9086 /* Address of the start of the current section. */
9087 + s->output_section->vma)
9088 /* The branch instruction is 4 bytes into the stub. */
9089 + 4
9090 /* ARM branches work from the pc of the instruction + 8. */
9091 + 8);
252b5132 9092
52ab56c2
PB		 9093 put_arm_insn (globals, output_bfd,
9094 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9095 s->contents + my_offset + 4);
252b5132
RH		 9096 }
9097
9098 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9099
427bfd90
NC		 9100 /* Now go back and fix up the original BL insn to point to here. */
9101 ret_offset =
9102 /* Address of where the stub is located. */
9103 (s->output_section->vma + s->output_offset + my_offset)
9104 /* Address of where the BL is located. */
57e8b36a
NC		 9105 - (input_section->output_section->vma + input_section->output_offset
9106 + offset)
427bfd90
NC		 9107 /* Addend in the relocation. */
9108 - addend
9109 /* Biassing for PC-relative addressing. */
9110 - 8;
252b5132 9111
12a0a0fd 9112 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 9113
b34976b6 9114 return TRUE;
252b5132
RH		 9115}
9116
a4fd1a8e 9117/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 9118
a4fd1a8e
PB		 9119static struct elf_link_hash_entry *
9120elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9121 const char * name,
9122 bfd * input_bfd,
9123 bfd * output_bfd,
9124 asection * sym_sec,
9125 bfd_vma val,
9126 asection * s,
9127 char ** error_message)
252b5132 9128{
dc810e39 9129 bfd_vma my_offset;
252b5132 9130 long int ret_offset;
bcbdc74c
NC		 9131 struct elf_link_hash_entry * myh;
9132 struct elf32_arm_link_hash_table * globals;
252b5132 9133
f2a9dd69 9134 myh = find_arm_glue (info, name, error_message);
252b5132 9135 if (myh == NULL)
a4fd1a8e 9136 return NULL;
252b5132
RH		 9137
9138 globals = elf32_arm_hash_table (info);
252b5132
RH		 9139 BFD_ASSERT (globals != NULL);
9140 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9141
9142 my_offset = myh->root.u.def.value;
252b5132
RH		 9143
9144 if ((my_offset & 0x01) == 0x01)
9145 {
9146 if (sym_sec != NULL
9147 && sym_sec->owner != NULL
9148 && !INTERWORK_FLAG (sym_sec->owner))
9149 {
4eca0228 9150 _bfd_error_handler
90b6238f
AM		 9151 (_("%pB(%s): warning: interworking not enabled;"
9152 " first occurrence: %pB: %s call to %s"),
9153 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 9154 }
9b485d32 9155
252b5132
RH		 9156 --my_offset;
9157 myh->root.u.def.value = my_offset;
9158
0e1862bb
L		 9159 if (bfd_link_pic (info)
9160 || globals->root.is_relocatable_executable
27e55c4d 9161 || globals->pic_veneer)
8f6277f5
PB		 9162 {
9163 /* For relocatable objects we can't use absolute addresses,
9164 so construct the address from a relative offset. */
9165 /* TODO: If the offset is small it's probably worth
9166 constructing the address with adds. */
52ab56c2
PB		 9167 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9168 s->contents + my_offset);
9169 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9170 s->contents + my_offset + 4);
9171 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9172 s->contents + my_offset + 8);
8f6277f5
PB		 9173 /* Adjust the offset by 4 for the position of the add,
9174 and 8 for the pipeline offset. */
9175 ret_offset = (val - (s->output_offset
9176 + s->output_section->vma
9177 + my_offset + 12))
9178 | 1;
9179 bfd_put_32 (output_bfd, ret_offset,
9180 s->contents + my_offset + 12);
9181 }
26079076
PB		 9182 else if (globals->use_blx)
9183 {
9184 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9185 s->contents + my_offset);
9186
9187 /* It's a thumb address. Add the low order bit. */
9188 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9189 s->contents + my_offset + 4);
9190 }
8f6277f5
PB		 9191 else
9192 {
52ab56c2
PB		 9193 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9194 s->contents + my_offset);
252b5132 9195
52ab56c2
PB		 9196 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9197 s->contents + my_offset + 4);
252b5132 9198
8f6277f5
PB		 9199 /* It's a thumb address. Add the low order bit. */
9200 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9201 s->contents + my_offset + 8);
8029a119
NC		 9202
9203 my_offset += 12;
8f6277f5 9204 }
252b5132
RH		 9205 }
9206
9207 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9208
a4fd1a8e
PB		 9209 return myh;
9210}
9211
9212/* Arm code calling a Thumb function. */
9213
9214static int
9215elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9216 const char * name,
9217 bfd * input_bfd,
9218 bfd * output_bfd,
9219 asection * input_section,
9220 bfd_byte * hit_data,
9221 asection * sym_sec,
9222 bfd_vma offset,
9223 bfd_signed_vma addend,
9224 bfd_vma val,
f2a9dd69 9225 char **error_message)
a4fd1a8e
PB		 9226{
9227 unsigned long int tmp;
9228 bfd_vma my_offset;
9229 asection * s;
9230 long int ret_offset;
9231 struct elf_link_hash_entry * myh;
9232 struct elf32_arm_link_hash_table * globals;
9233
9234 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9235 BFD_ASSERT (globals != NULL);
9236 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9237
3d4d4302
AM		 9238 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9239 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9240 BFD_ASSERT (s != NULL);
9241 BFD_ASSERT (s->contents != NULL);
9242 BFD_ASSERT (s->output_section != NULL);
9243
9244 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9245 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9246 if (!myh)
9247 return FALSE;
9248
9249 my_offset = myh->root.u.def.value;
252b5132
RH		 9250 tmp = bfd_get_32 (input_bfd, hit_data);
9251 tmp = tmp & 0xFF000000;
9252
9b485d32 9253 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9254 ret_offset = (s->output_offset
9255 + my_offset
9256 + s->output_section->vma
9257 - (input_section->output_offset
9258 + input_section->output_section->vma
9259 + offset + addend)
9260 - 8);
9a5aca8c 9261
252b5132
RH		 9262 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9263
dc810e39 9264 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9265
b34976b6 9266 return TRUE;
252b5132
RH		 9267}
9268
a4fd1a8e
PB		 9269/* Populate Arm stub for an exported Thumb function. */
9270
9271static bfd_boolean
9272elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9273{
9274 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9275 asection * s;
9276 struct elf_link_hash_entry * myh;
9277 struct elf32_arm_link_hash_entry *eh;
9278 struct elf32_arm_link_hash_table * globals;
9279 asection *sec;
9280 bfd_vma val;
f2a9dd69 9281 char *error_message;
a4fd1a8e 9282
906e58ca 9283 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9284 /* Allocate stubs for exported Thumb functions on v4t. */
9285 if (eh->export_glue == NULL)
9286 return TRUE;
9287
9288 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9289 BFD_ASSERT (globals != NULL);
9290 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9291
3d4d4302
AM		 9292 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9293 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9294 BFD_ASSERT (s != NULL);
9295 BFD_ASSERT (s->contents != NULL);
9296 BFD_ASSERT (s->output_section != NULL);
9297
9298 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9299
9300 BFD_ASSERT (sec->output_section != NULL);
9301
a4fd1a8e
PB		 9302 val = eh->export_glue->root.u.def.value + sec->output_offset
9303 + sec->output_section->vma;
8029a119 9304
a4fd1a8e
PB		 9305 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9306 h->root.u.def.section->owner,
f2a9dd69
DJ		 9307 globals->obfd, sec, val, s,
9308 &error_message);
a4fd1a8e
PB		 9309 BFD_ASSERT (myh);
9310 return TRUE;
9311}
9312
845b51d6
PB		 9313/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9314
9315static bfd_vma
9316elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9317{
9318 bfd_byte *p;
9319 bfd_vma glue_addr;
9320 asection *s;
9321 struct elf32_arm_link_hash_table *globals;
9322
9323 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9324 BFD_ASSERT (globals != NULL);
9325 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9326
3d4d4302
AM		 9327 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9328 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9329 BFD_ASSERT (s != NULL);
9330 BFD_ASSERT (s->contents != NULL);
9331 BFD_ASSERT (s->output_section != NULL);
9332
9333 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9334
9335 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9336
9337 if ((globals->bx_glue_offset[reg] & 1) == 0)
9338 {
9339 p = s->contents + glue_addr;
9340 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9341 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9342 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9343 globals->bx_glue_offset[reg] |= 1;
9344 }
9345
9346 return glue_addr + s->output_section->vma + s->output_offset;
9347}
9348
a4fd1a8e
PB		 9349/* Generate Arm stubs for exported Thumb symbols. */
9350static void
906e58ca 9351elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9352 struct bfd_link_info *link_info)
9353{
9354 struct elf32_arm_link_hash_table * globals;
9355
8029a119
NC		 9356 if (link_info == NULL)
9357 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9358 return;
9359
9360 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9361 if (globals == NULL)
9362 return;
9363
84c08195
PB		 9364 /* If blx is available then exported Thumb symbols are OK and there is
9365 nothing to do. */
a4fd1a8e
PB		 9366 if (globals->use_blx)
9367 return;
9368
9369 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9370 link_info);
9371}
9372
47beaa6a
RS		 9373/* Reserve space for COUNT dynamic relocations in relocation selection
9374 SRELOC. */
9375
9376static void
9377elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9378 bfd_size_type count)
9379{
9380 struct elf32_arm_link_hash_table *htab;
9381
9382 htab = elf32_arm_hash_table (info);
9383 BFD_ASSERT (htab->root.dynamic_sections_created);
9384 if (sreloc == NULL)
9385 abort ();
9386 sreloc->size += RELOC_SIZE (htab) * count;
9387}
9388
34e77a92
RS		 9389/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9390 dynamic, the relocations should go in SRELOC, otherwise they should
9391 go in the special .rel.iplt section. */
9392
9393static void
9394elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9395 bfd_size_type count)
9396{
9397 struct elf32_arm_link_hash_table *htab;
9398
9399 htab = elf32_arm_hash_table (info);
9400 if (!htab->root.dynamic_sections_created)
9401 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9402 else
9403 {
9404 BFD_ASSERT (sreloc != NULL);
9405 sreloc->size += RELOC_SIZE (htab) * count;
9406 }
9407}
9408
47beaa6a
RS		 9409/* Add relocation REL to the end of relocation section SRELOC. */
9410
9411static void
9412elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9413 asection *sreloc, Elf_Internal_Rela *rel)
9414{
9415 bfd_byte *loc;
9416 struct elf32_arm_link_hash_table *htab;
9417
9418 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9419 if (!htab->root.dynamic_sections_created
9420 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9421 sreloc = htab->root.irelplt;
47beaa6a
RS		 9422 if (sreloc == NULL)
9423 abort ();
9424 loc = sreloc->contents;
9425 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9426 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9427 abort ();
9428 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9429}
9430
34e77a92
RS		 9431/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9432 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9433 to .plt. */
9434
9435static void
9436elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9437 bfd_boolean is_iplt_entry,
9438 union gotplt_union *root_plt,
9439 struct arm_plt_info *arm_plt)
9440{
9441 struct elf32_arm_link_hash_table *htab;
9442 asection *splt;
9443 asection *sgotplt;
9444
9445 htab = elf32_arm_hash_table (info);
9446
9447 if (is_iplt_entry)
9448 {
9449 splt = htab->root.iplt;
9450 sgotplt = htab->root.igotplt;
9451
99059e56
RM		 9452 /* NaCl uses a special first entry in .iplt too. */
9453 if (htab->nacl_p && splt->size == 0)
9454 splt->size += htab->plt_header_size;
9455
34e77a92
RS		 9456 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9457 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9458 }
9459 else
9460 {
9461 splt = htab->root.splt;
9462 sgotplt = htab->root.sgotplt;
9463
7801f98f
CL		 9464 if (htab->fdpic_p)
9465 {
9466 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9467 /* For lazy binding, relocations will be put into .rel.plt, in
9468 .rel.got otherwise. */
9469 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9470 if (info->flags & DF_BIND_NOW)
9471 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9472 else
9473 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9474 }
9475 else
9476 {
9477 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9478 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9479 }
34e77a92
RS		 9480
9481 /* If this is the first .plt entry, make room for the special
9482 first entry. */
9483 if (splt->size == 0)
9484 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9485
9486 htab->next_tls_desc_index++;
34e77a92
RS		 9487 }
9488
9489 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9490 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9491 splt->size += PLT_THUMB_STUB_SIZE;
9492 root_plt->offset = splt->size;
9493 splt->size += htab->plt_entry_size;
9494
9495 if (!htab->symbian_p)
9496 {
9497 /* We also need to make an entry in the .got.plt section, which
9498 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9499 if (is_iplt_entry)
9500 arm_plt->got_offset = sgotplt->size;
9501 else
9502 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
7801f98f
CL		 9503 if (htab->fdpic_p)
9504 /* Function descriptor takes 64 bits in GOT. */
9505 sgotplt->size += 8;
9506 else
9507 sgotplt->size += 4;
34e77a92
RS		 9508 }
9509}
9510
b38cadfb
NC		 9511static bfd_vma
9512arm_movw_immediate (bfd_vma value)
9513{
9514 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9515}
9516
9517static bfd_vma
9518arm_movt_immediate (bfd_vma value)
9519{
9520 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9521}
9522
34e77a92
RS		 9523/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9524 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9525 Otherwise, DYNINDX is the index of the symbol in the dynamic
9526 symbol table and SYM_VALUE is undefined.
9527
9528 ROOT_PLT points to the offset of the PLT entry from the start of its
9529 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9530 bookkeeping information.
34e77a92 9531
57460bcf
NC		 9532 Returns FALSE if there was a problem. */
9533
9534static bfd_boolean
34e77a92
RS		 9535elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9536 union gotplt_union *root_plt,
9537 struct arm_plt_info *arm_plt,
9538 int dynindx, bfd_vma sym_value)
9539{
9540 struct elf32_arm_link_hash_table *htab;
9541 asection *sgot;
9542 asection *splt;
9543 asection *srel;
9544 bfd_byte *loc;
9545 bfd_vma plt_index;
9546 Elf_Internal_Rela rel;
9547 bfd_vma plt_header_size;
9548 bfd_vma got_header_size;
9549
9550 htab = elf32_arm_hash_table (info);
9551
9552 /* Pick the appropriate sections and sizes. */
9553 if (dynindx == -1)
9554 {
9555 splt = htab->root.iplt;
9556 sgot = htab->root.igotplt;
9557 srel = htab->root.irelplt;
9558
9559 /* There are no reserved entries in .igot.plt, and no special
9560 first entry in .iplt. */
9561 got_header_size = 0;
9562 plt_header_size = 0;
9563 }
9564 else
9565 {
9566 splt = htab->root.splt;
9567 sgot = htab->root.sgotplt;
9568 srel = htab->root.srelplt;
9569
9570 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9571 plt_header_size = htab->plt_header_size;
9572 }
9573 BFD_ASSERT (splt != NULL && srel != NULL);
9574
9575 /* Fill in the entry in the procedure linkage table. */
9576 if (htab->symbian_p)
9577 {
9578 BFD_ASSERT (dynindx >= 0);
9579 put_arm_insn (htab, output_bfd,
9580 elf32_arm_symbian_plt_entry[0],
9581 splt->contents + root_plt->offset);
9582 bfd_put_32 (output_bfd,
9583 elf32_arm_symbian_plt_entry[1],
9584 splt->contents + root_plt->offset + 4);
9585
9586 /* Fill in the entry in the .rel.plt section. */
9587 rel.r_offset = (splt->output_section->vma
9588 + splt->output_offset
9589 + root_plt->offset + 4);
9590 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9591
9592 /* Get the index in the procedure linkage table which
9593 corresponds to this symbol. This is the index of this symbol
9594 in all the symbols for which we are making plt entries. The
9595 first entry in the procedure linkage table is reserved. */
9596 plt_index = ((root_plt->offset - plt_header_size)
9597 / htab->plt_entry_size);
9598 }
9599 else
9600 {
9601 bfd_vma got_offset, got_address, plt_address;
9602 bfd_vma got_displacement, initial_got_entry;
9603 bfd_byte * ptr;
9604
9605 BFD_ASSERT (sgot != NULL);
9606
9607 /* Get the offset into the .(i)got.plt table of the entry that
9608 corresponds to this function. */
9609 got_offset = (arm_plt->got_offset & -2);
9610
9611 /* Get the index in the procedure linkage table which
9612 corresponds to this symbol. This is the index of this symbol
9613 in all the symbols for which we are making plt entries.
9614 After the reserved .got.plt entries, all symbols appear in
9615 the same order as in .plt. */
7801f98f
CL		 9616 if (htab->fdpic_p)
9617 /* Function descriptor takes 8 bytes. */
9618 plt_index = (got_offset - got_header_size) / 8;
9619 else
9620 plt_index = (got_offset - got_header_size) / 4;
34e77a92
RS		 9621
9622 /* Calculate the address of the GOT entry. */
9623 got_address = (sgot->output_section->vma
9624 + sgot->output_offset
9625 + got_offset);
9626
9627 /* ...and the address of the PLT entry. */
9628 plt_address = (splt->output_section->vma
9629 + splt->output_offset
9630 + root_plt->offset);
9631
9632 ptr = splt->contents + root_plt->offset;
0e1862bb 9633 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9634 {
9635 unsigned int i;
9636 bfd_vma val;
9637
9638 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9639 {
9640 val = elf32_arm_vxworks_shared_plt_entry[i];
9641 if (i == 2)
9642 val |= got_address - sgot->output_section->vma;
9643 if (i == 5)
9644 val |= plt_index * RELOC_SIZE (htab);
9645 if (i == 2 || i == 5)
9646 bfd_put_32 (output_bfd, val, ptr);
9647 else
9648 put_arm_insn (htab, output_bfd, val, ptr);
9649 }
9650 }
9651 else if (htab->vxworks_p)
9652 {
9653 unsigned int i;
9654 bfd_vma val;
9655
9656 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9657 {
9658 val = elf32_arm_vxworks_exec_plt_entry[i];
9659 if (i == 2)
9660 val |= got_address;
9661 if (i == 4)
9662 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9663 if (i == 5)
9664 val |= plt_index * RELOC_SIZE (htab);
9665 if (i == 2 || i == 5)
9666 bfd_put_32 (output_bfd, val, ptr);
9667 else
9668 put_arm_insn (htab, output_bfd, val, ptr);
9669 }
9670
9671 loc = (htab->srelplt2->contents
9672 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9673
9674 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9675 referencing the GOT for this PLT entry. */
9676 rel.r_offset = plt_address + 8;
9677 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9678 rel.r_addend = got_offset;
9679 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9680 loc += RELOC_SIZE (htab);
9681
9682 /* Create the R_ARM_ABS32 relocation referencing the
9683 beginning of the PLT for this GOT entry. */
9684 rel.r_offset = got_address;
9685 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9686 rel.r_addend = 0;
9687 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9688 }
b38cadfb
NC		 9689 else if (htab->nacl_p)
9690 {
9691 /* Calculate the displacement between the PLT slot and the
9692 common tail that's part of the special initial PLT slot. */
6034aab8 9693 int32_t tail_displacement
b38cadfb
NC		 9694 = ((splt->output_section->vma + splt->output_offset
9695 + ARM_NACL_PLT_TAIL_OFFSET)
9696 - (plt_address + htab->plt_entry_size + 4));
9697 BFD_ASSERT ((tail_displacement & 3) == 0);
9698 tail_displacement >>= 2;
9699
9700 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9701 || (-tail_displacement & 0xff000000) == 0);
9702
9703 /* Calculate the displacement between the PLT slot and the entry
9704 in the GOT. The offset accounts for the value produced by
9705 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9706 got_displacement = (got_address
99059e56 9707 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9708
9709 /* NaCl does not support interworking at all. */
9710 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9711
9712 put_arm_insn (htab, output_bfd,
9713 elf32_arm_nacl_plt_entry[0]
9714 | arm_movw_immediate (got_displacement),
9715 ptr + 0);
9716 put_arm_insn (htab, output_bfd,
9717 elf32_arm_nacl_plt_entry[1]
9718 | arm_movt_immediate (got_displacement),
9719 ptr + 4);
9720 put_arm_insn (htab, output_bfd,
9721 elf32_arm_nacl_plt_entry[2],
9722 ptr + 8);
9723 put_arm_insn (htab, output_bfd,
9724 elf32_arm_nacl_plt_entry[3]
9725 | (tail_displacement & 0x00ffffff),
9726 ptr + 12);
9727 }
7801f98f
CL		 9728 else if (htab->fdpic_p)
9729 {
9730 /* Fill-up Thumb stub if needed. */
9731 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9732 {
9733 put_thumb_insn (htab, output_bfd,
9734 elf32_arm_plt_thumb_stub[0], ptr - 4);
9735 put_thumb_insn (htab, output_bfd,
9736 elf32_arm_plt_thumb_stub[1], ptr - 2);
9737 }
9738 put_arm_insn(htab, output_bfd,
9739 elf32_arm_fdpic_plt_entry[0], ptr + 0);
9740 put_arm_insn(htab, output_bfd,
9741 elf32_arm_fdpic_plt_entry[1], ptr + 4);
9742 put_arm_insn(htab, output_bfd,
9743 elf32_arm_fdpic_plt_entry[2], ptr + 8);
9744 put_arm_insn(htab, output_bfd,
9745 elf32_arm_fdpic_plt_entry[3], ptr + 12);
9746 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9747
9748 if (!(info->flags & DF_BIND_NOW))
9749 {
9750 /* funcdesc_value_reloc_offset. */
9751 bfd_put_32 (output_bfd,
9752 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9753 ptr + 20);
9754 put_arm_insn(htab, output_bfd,
9755 elf32_arm_fdpic_plt_entry[6], ptr + 24);
9756 put_arm_insn(htab, output_bfd,
9757 elf32_arm_fdpic_plt_entry[7], ptr + 28);
9758 put_arm_insn(htab, output_bfd,
9759 elf32_arm_fdpic_plt_entry[8], ptr + 32);
9760 put_arm_insn(htab, output_bfd,
9761 elf32_arm_fdpic_plt_entry[9], ptr + 36);
9762 }
9763 }
57460bcf
NC		 9764 else if (using_thumb_only (htab))
9765 {
eed94f8f 9766 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9767 if (!using_thumb2 (htab))
eed94f8f
NC		 9768 {
9769 /* FIXME: We ought to be able to generate thumb-1 PLT
9770 instructions... */
90b6238f 9771 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9772 output_bfd);
9773 return FALSE;
9774 }
57460bcf 9775
eed94f8f
NC		 9776 /* Calculate the displacement between the PLT slot and the entry in
9777 the GOT. The 12-byte offset accounts for the value produced by
9778 adding to pc in the 3rd instruction of the PLT stub. */
9779 got_displacement = got_address - (plt_address + 12);
9780
9781 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9782 instead of 'put_thumb_insn'. */
9783 put_arm_insn (htab, output_bfd,
9784 elf32_thumb2_plt_entry[0]
9785 | ((got_displacement & 0x000000ff) << 16)
9786 | ((got_displacement & 0x00000700) << 20)
9787 | ((got_displacement & 0x00000800) >> 1)
9788 | ((got_displacement & 0x0000f000) >> 12),
9789 ptr + 0);
9790 put_arm_insn (htab, output_bfd,
9791 elf32_thumb2_plt_entry[1]
9792 | ((got_displacement & 0x00ff0000) )
9793 | ((got_displacement & 0x07000000) << 4)
9794 | ((got_displacement & 0x08000000) >> 17)
9795 | ((got_displacement & 0xf0000000) >> 28),
9796 ptr + 4);
9797 put_arm_insn (htab, output_bfd,
9798 elf32_thumb2_plt_entry[2],
9799 ptr + 8);
9800 put_arm_insn (htab, output_bfd,
9801 elf32_thumb2_plt_entry[3],
9802 ptr + 12);
57460bcf 9803 }
34e77a92
RS		 9804 else
9805 {
9806 /* Calculate the displacement between the PLT slot and the
9807 entry in the GOT. The eight-byte offset accounts for the
9808 value produced by adding to pc in the first instruction
9809 of the PLT stub. */
9810 got_displacement = got_address - (plt_address + 8);
9811
34e77a92
RS		 9812 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9813 {
9814 put_thumb_insn (htab, output_bfd,
9815 elf32_arm_plt_thumb_stub[0], ptr - 4);
9816 put_thumb_insn (htab, output_bfd,
9817 elf32_arm_plt_thumb_stub[1], ptr - 2);
9818 }
9819
1db37fe6
YG		 9820 if (!elf32_arm_use_long_plt_entry)
9821 {
9822 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9823
9824 put_arm_insn (htab, output_bfd,
9825 elf32_arm_plt_entry_short[0]
9826 | ((got_displacement & 0x0ff00000) >> 20),
9827 ptr + 0);
9828 put_arm_insn (htab, output_bfd,
9829 elf32_arm_plt_entry_short[1]
9830 | ((got_displacement & 0x000ff000) >> 12),
9831 ptr+ 4);
9832 put_arm_insn (htab, output_bfd,
9833 elf32_arm_plt_entry_short[2]
9834 | (got_displacement & 0x00000fff),
9835 ptr + 8);
34e77a92 9836#ifdef FOUR_WORD_PLT
1db37fe6 9837 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9838#endif
1db37fe6
YG		 9839 }
9840 else
9841 {
9842 put_arm_insn (htab, output_bfd,
9843 elf32_arm_plt_entry_long[0]
9844 | ((got_displacement & 0xf0000000) >> 28),
9845 ptr + 0);
9846 put_arm_insn (htab, output_bfd,
9847 elf32_arm_plt_entry_long[1]
9848 | ((got_displacement & 0x0ff00000) >> 20),
9849 ptr + 4);
9850 put_arm_insn (htab, output_bfd,
9851 elf32_arm_plt_entry_long[2]
9852 | ((got_displacement & 0x000ff000) >> 12),
9853 ptr+ 8);
9854 put_arm_insn (htab, output_bfd,
9855 elf32_arm_plt_entry_long[3]
9856 | (got_displacement & 0x00000fff),
9857 ptr + 12);
9858 }
34e77a92
RS		 9859 }
9860
9861 /* Fill in the entry in the .rel(a).(i)plt section. */
9862 rel.r_offset = got_address;
9863 rel.r_addend = 0;
9864 if (dynindx == -1)
9865 {
9866 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9867 The dynamic linker or static executable then calls SYM_VALUE
9868 to determine the correct run-time value of the .igot.plt entry. */
9869 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9870 initial_got_entry = sym_value;
9871 }
9872 else
9873 {
7801f98f
CL		 9874 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9875 used by PLT entry. */
9876 if (htab->fdpic_p)
9877 {
9878 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
9879 initial_got_entry = 0;
9880 }
9881 else
9882 {
9883 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9884 initial_got_entry = (splt->output_section->vma
9885 + splt->output_offset);
9886 }
34e77a92
RS		 9887 }
9888
9889 /* Fill in the entry in the global offset table. */
9890 bfd_put_32 (output_bfd, initial_got_entry,
9891 sgot->contents + got_offset);
7801f98f
CL		 9892
9893 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
9894 {
9895 /* Setup initial funcdesc value. */
9896 /* FIXME: we don't support lazy binding because there is a
9897 race condition between both words getting written and
9898 some other thread attempting to read them. The ARM
9899 architecture does not have an atomic 64 bit load/store
9900 instruction that could be used to prevent it; it is
9901 recommended that threaded FDPIC applications run with the
9902 LD_BIND_NOW environment variable set. */
9903 bfd_put_32(output_bfd, plt_address + 0x18,
9904 sgot->contents + got_offset);
9905 bfd_put_32(output_bfd, -1 /*TODO*/,
9906 sgot->contents + got_offset + 4);
9907 }
34e77a92
RS		 9908 }
9909
aba8c3de
WN		 9910 if (dynindx == -1)
9911 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9912 else
9913 {
7801f98f
CL		 9914 if (htab->fdpic_p)
9915 {
9916 /* For FDPIC we put PLT relocationss into .rel.got when not
9917 lazy binding otherwise we put them in .rel.plt. For now,
9918 we don't support lazy binding so put it in .rel.got. */
9919 if (info->flags & DF_BIND_NOW)
9920 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelgot, &rel);
9921 else
9922 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelplt, &rel);
9923 }
9924 else
9925 {
9926 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9927 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9928 }
aba8c3de 9929 }
57460bcf
NC		 9930
9931 return TRUE;
34e77a92
RS		 9932}
9933
eb043451
PB		 9934/* Some relocations map to different relocations depending on the
9935 target. Return the real relocation. */
8029a119 9936
eb043451
PB		 9937static int
9938arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9939 int r_type)
9940{
9941 switch (r_type)
9942 {
9943 case R_ARM_TARGET1:
9944 if (globals->target1_is_rel)
9945 return R_ARM_REL32;
9946 else
9947 return R_ARM_ABS32;
9948
9949 case R_ARM_TARGET2:
9950 return globals->target2_reloc;
9951
9952 default:
9953 return r_type;
9954 }
9955}
eb043451 9956
ba93b8ac
DJ		 9957/* Return the base VMA address which should be subtracted from real addresses
9958 when resolving @dtpoff relocation.
9959 This is PT_TLS segment p_vaddr. */
9960
9961static bfd_vma
9962dtpoff_base (struct bfd_link_info *info)
9963{
9964 /* If tls_sec is NULL, we should have signalled an error already. */
9965 if (elf_hash_table (info)->tls_sec == NULL)
9966 return 0;
9967 return elf_hash_table (info)->tls_sec->vma;
9968}
9969
9970/* Return the relocation value for @tpoff relocation
9971 if STT_TLS virtual address is ADDRESS. */
9972
9973static bfd_vma
9974tpoff (struct bfd_link_info *info, bfd_vma address)
9975{
9976 struct elf_link_hash_table *htab = elf_hash_table (info);
9977 bfd_vma base;
9978
9979 /* If tls_sec is NULL, we should have signalled an error already. */
9980 if (htab->tls_sec == NULL)
9981 return 0;
9982 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
9983 return address - htab->tls_sec->vma + base;
9984}
9985
00a97672
RS		 9986/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
9987 VALUE is the relocation value. */
9988
9989static bfd_reloc_status_type
9990elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
9991{
9992 if (value > 0xfff)
9993 return bfd_reloc_overflow;
9994
9995 value |= bfd_get_32 (abfd, data) & 0xfffff000;
9996 bfd_put_32 (abfd, value, data);
9997 return bfd_reloc_ok;
9998}
9999
0855e32b
NS		 10000/* Handle TLS relaxations. Relaxing is possible for symbols that use
10001 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10002 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10003
10004 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10005 is to then call final_link_relocate. Return other values in the
62672b10
NS		 10006 case of error.
10007
10008 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10009 the pre-relaxed code. It would be nice if the relocs were updated
10010 to match the optimization. */
0855e32b 10011
b38cadfb 10012static bfd_reloc_status_type
0855e32b 10013elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 10014 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 10015 Elf_Internal_Rela *rel, unsigned long is_local)
10016{
10017 unsigned long insn;
b38cadfb 10018
0855e32b
NS		 10019 switch (ELF32_R_TYPE (rel->r_info))
10020 {
10021 default:
10022 return bfd_reloc_notsupported;
b38cadfb 10023
0855e32b
NS		 10024 case R_ARM_TLS_GOTDESC:
10025 if (is_local)
10026 insn = 0;
10027 else
10028 {
10029 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10030 if (insn & 1)
10031 insn -= 5; /* THUMB */
10032 else
10033 insn -= 8; /* ARM */
10034 }
10035 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10036 return bfd_reloc_continue;
10037
10038 case R_ARM_THM_TLS_DESCSEQ:
10039 /* Thumb insn. */
10040 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10041 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10042 {
10043 if (is_local)
10044 /* nop */
10045 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10046 }
10047 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10048 {
10049 if (is_local)
10050 /* nop */
10051 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10052 else
10053 /* ldr rx,[ry] */
10054 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10055 }
10056 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10057 {
10058 if (is_local)
10059 /* nop */
10060 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10061 else
10062 /* mov r0, rx */
10063 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10064 contents + rel->r_offset);
10065 }
10066 else
10067 {
10068 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10069 /* It's a 32 bit instruction, fetch the rest of it for
10070 error generation. */
10071 insn = (insn << 16)
10072 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 10073 _bfd_error_handler
695344c0 10074 /* xgettext:c-format */
2dcf00ce 10075 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10076 "unexpected %s instruction '%#lx' in TLS trampoline"),
10077 input_bfd, input_sec, (uint64_t) rel->r_offset,
10078 "Thumb", insn);
0855e32b
NS		 10079 return bfd_reloc_notsupported;
10080 }
10081 break;
b38cadfb 10082
0855e32b
NS		 10083 case R_ARM_TLS_DESCSEQ:
10084 /* arm insn. */
10085 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10086 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10087 {
10088 if (is_local)
10089 /* mov rx, ry */
10090 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10091 contents + rel->r_offset);
10092 }
10093 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10094 {
10095 if (is_local)
10096 /* nop */
10097 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10098 else
10099 /* ldr rx,[ry] */
10100 bfd_put_32 (input_bfd, insn & 0xfffff000,
10101 contents + rel->r_offset);
10102 }
10103 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10104 {
10105 if (is_local)
10106 /* nop */
10107 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10108 else
10109 /* mov r0, rx */
10110 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10111 contents + rel->r_offset);
10112 }
10113 else
10114 {
4eca0228 10115 _bfd_error_handler
695344c0 10116 /* xgettext:c-format */
2dcf00ce 10117 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10118 "unexpected %s instruction '%#lx' in TLS trampoline"),
10119 input_bfd, input_sec, (uint64_t) rel->r_offset,
10120 "ARM", insn);
0855e32b
NS		 10121 return bfd_reloc_notsupported;
10122 }
10123 break;
10124
10125 case R_ARM_TLS_CALL:
10126 /* GD->IE relaxation, turn the instruction into 'nop' or
10127 'ldr r0, [pc,r0]' */
10128 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10129 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10130 break;
b38cadfb 10131
0855e32b 10132 case R_ARM_THM_TLS_CALL:
6a631e86 10133 /* GD->IE relaxation. */
0855e32b
NS		 10134 if (!is_local)
10135 /* add r0,pc; ldr r0, [r0] */
10136 insn = 0x44786800;
60a019a0 10137 else if (using_thumb2 (globals))
0855e32b
NS		 10138 /* nop.w */
10139 insn = 0xf3af8000;
10140 else
10141 /* nop; nop */
10142 insn = 0xbf00bf00;
b38cadfb 10143
0855e32b
NS		 10144 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10145 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10146 break;
10147 }
10148 return bfd_reloc_ok;
10149}
10150
4962c51a
MS		 10151/* For a given value of n, calculate the value of G_n as required to
10152 deal with group relocations. We return it in the form of an
10153 encoded constant-and-rotation, together with the final residual. If n is
10154 specified as less than zero, then final_residual is filled with the
10155 input value and no further action is performed. */
10156
10157static bfd_vma
10158calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10159{
10160 int current_n;
10161 bfd_vma g_n;
10162 bfd_vma encoded_g_n = 0;
10163 bfd_vma residual = value; /* Also known as Y_n. */
10164
10165 for (current_n = 0; current_n <= n; current_n++)
10166 {
10167 int shift;
10168
10169 /* Calculate which part of the value to mask. */
10170 if (residual == 0)
99059e56 10171 shift = 0;
4962c51a 10172 else
99059e56
RM		 10173 {
10174 int msb;
10175
10176 /* Determine the most significant bit in the residual and
10177 align the resulting value to a 2-bit boundary. */
10178 for (msb = 30; msb >= 0; msb -= 2)
10179 if (residual & (3 << msb))
10180 break;
10181
10182 /* The desired shift is now (msb - 6), or zero, whichever
10183 is the greater. */
10184 shift = msb - 6;
10185 if (shift < 0)
10186 shift = 0;
10187 }
4962c51a
MS		 10188
10189 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10190 g_n = residual & (0xff << shift);
10191 encoded_g_n = (g_n >> shift)
99059e56 10192 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 10193
10194 /* Calculate the residual for the next time around. */
10195 residual &= ~g_n;
10196 }
10197
10198 *final_residual = residual;
10199
10200 return encoded_g_n;
10201}
10202
10203/* Given an ARM instruction, determine whether it is an ADD or a SUB.
10204 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 10205
4962c51a 10206static int
906e58ca 10207identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 10208{
10209 int opcode = insn & 0x1e00000;
10210
10211 if (opcode == 1 << 23) /* ADD */
10212 return 1;
10213
10214 if (opcode == 1 << 22) /* SUB */
10215 return -1;
10216
10217 return 0;
10218}
10219
252b5132 10220/* Perform a relocation as part of a final link. */
9b485d32 10221
252b5132 10222static bfd_reloc_status_type
07d6d2b8
AM		 10223elf32_arm_final_link_relocate (reloc_howto_type * howto,
10224 bfd * input_bfd,
10225 bfd * output_bfd,
10226 asection * input_section,
10227 bfd_byte * contents,
10228 Elf_Internal_Rela * rel,
10229 bfd_vma value,
10230 struct bfd_link_info * info,
10231 asection * sym_sec,
10232 const char * sym_name,
10233 unsigned char st_type,
10234 enum arm_st_branch_type branch_type,
0945cdfd 10235 struct elf_link_hash_entry * h,
07d6d2b8
AM		 10236 bfd_boolean * unresolved_reloc_p,
10237 char ** error_message)
10238{
10239 unsigned long r_type = howto->type;
10240 unsigned long r_symndx;
10241 bfd_byte * hit_data = contents + rel->r_offset;
10242 bfd_vma * local_got_offsets;
10243 bfd_vma * local_tlsdesc_gotents;
10244 asection * sgot;
10245 asection * splt;
10246 asection * sreloc = NULL;
10247 asection * srelgot;
10248 bfd_vma addend;
10249 bfd_signed_vma signed_addend;
10250 unsigned char dynreloc_st_type;
10251 bfd_vma dynreloc_value;
ba96a88f 10252 struct elf32_arm_link_hash_table * globals;
34e77a92 10253 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 10254 union gotplt_union *root_plt;
10255 struct arm_plt_info *arm_plt;
10256 bfd_vma plt_offset;
10257 bfd_vma gotplt_offset;
10258 bfd_boolean has_iplt_entry;
10259 bfd_boolean resolved_to_zero;
f21f3fe0 10260
9c504268 10261 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 10262 if (globals == NULL)
10263 return bfd_reloc_notsupported;
9c504268 10264
0ffa91dd 10265 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 10266 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 10267
10268 /* Some relocation types map to different relocations depending on the
9c504268 10269 target. We pick the right one here. */
eb043451 10270 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 10271
10272 /* It is possible to have linker relaxations on some TLS access
10273 models. Update our information here. */
10274 r_type = elf32_arm_tls_transition (info, r_type, h);
10275
eb043451
PB		 10276 if (r_type != howto->type)
10277 howto = elf32_arm_howto_from_type (r_type);
9c504268 10278
34e77a92 10279 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 10280 sgot = globals->root.sgot;
252b5132 10281 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 10282 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10283
34e77a92
RS		 10284 if (globals->root.dynamic_sections_created)
10285 srelgot = globals->root.srelgot;
10286 else
10287 srelgot = NULL;
10288
252b5132
RH		 10289 r_symndx = ELF32_R_SYM (rel->r_info);
10290
4e7fd91e 10291 if (globals->use_rel)
ba96a88f 10292 {
4e7fd91e
PB		 10293 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
10294
10295 if (addend & ((howto->src_mask + 1) >> 1))
10296 {
10297 signed_addend = -1;
10298 signed_addend &= ~ howto->src_mask;
10299 signed_addend |= addend;
10300 }
10301 else
10302 signed_addend = addend;
ba96a88f
NC		 10303 }
10304 else
4e7fd91e 10305 addend = signed_addend = rel->r_addend;
f21f3fe0 10306
39f21624
NC		 10307 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10308 are resolving a function call relocation. */
10309 if (using_thumb_only (globals)
10310 && (r_type == R_ARM_THM_CALL
10311 || r_type == R_ARM_THM_JUMP24)
10312 && branch_type == ST_BRANCH_TO_ARM)
10313 branch_type = ST_BRANCH_TO_THUMB;
10314
34e77a92
RS		 10315 /* Record the symbol information that should be used in dynamic
10316 relocations. */
10317 dynreloc_st_type = st_type;
10318 dynreloc_value = value;
10319 if (branch_type == ST_BRANCH_TO_THUMB)
10320 dynreloc_value |= 1;
10321
10322 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10323 VALUE appropriately for relocations that we resolve at link time. */
10324 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10325 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10326 &arm_plt)
34e77a92
RS		 10327 && root_plt->offset != (bfd_vma) -1)
10328 {
10329 plt_offset = root_plt->offset;
10330 gotplt_offset = arm_plt->got_offset;
10331
10332 if (h == NULL || eh->is_iplt)
10333 {
10334 has_iplt_entry = TRUE;
10335 splt = globals->root.iplt;
10336
10337 /* Populate .iplt entries here, because not all of them will
10338 be seen by finish_dynamic_symbol. The lower bit is set if
10339 we have already populated the entry. */
10340 if (plt_offset & 1)
10341 plt_offset--;
10342 else
10343 {
57460bcf
NC		 10344 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10345 -1, dynreloc_value))
10346 root_plt->offset |= 1;
10347 else
10348 return bfd_reloc_notsupported;
34e77a92
RS		 10349 }
10350
10351 /* Static relocations always resolve to the .iplt entry. */
10352 st_type = STT_FUNC;
10353 value = (splt->output_section->vma
10354 + splt->output_offset
10355 + plt_offset);
10356 branch_type = ST_BRANCH_TO_ARM;
10357
10358 /* If there are non-call relocations that resolve to the .iplt
10359 entry, then all dynamic ones must too. */
10360 if (arm_plt->noncall_refcount != 0)
10361 {
10362 dynreloc_st_type = st_type;
10363 dynreloc_value = value;
10364 }
10365 }
10366 else
10367 /* We populate the .plt entry in finish_dynamic_symbol. */
10368 splt = globals->root.splt;
10369 }
10370 else
10371 {
10372 splt = NULL;
10373 plt_offset = (bfd_vma) -1;
10374 gotplt_offset = (bfd_vma) -1;
10375 }
10376
95b03e4a
L		 10377 resolved_to_zero = (h != NULL
10378 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10379
252b5132
RH		 10380 switch (r_type)
10381 {
10382 case R_ARM_NONE:
28a094c2
DJ		 10383 /* We don't need to find a value for this symbol. It's just a
10384 marker. */
10385 *unresolved_reloc_p = FALSE;
252b5132
RH		 10386 return bfd_reloc_ok;
10387
00a97672
RS		 10388 case R_ARM_ABS12:
10389 if (!globals->vxworks_p)
10390 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10391 /* Fall through. */
00a97672 10392
252b5132
RH		 10393 case R_ARM_PC24:
10394 case R_ARM_ABS32:
bb224fc3 10395 case R_ARM_ABS32_NOI:
252b5132 10396 case R_ARM_REL32:
bb224fc3 10397 case R_ARM_REL32_NOI:
5b5bb741
PB		 10398 case R_ARM_CALL:
10399 case R_ARM_JUMP24:
dfc5f959 10400 case R_ARM_XPC25:
eb043451 10401 case R_ARM_PREL31:
7359ea65 10402 case R_ARM_PLT32:
7359ea65
DJ		 10403 /* Handle relocations which should use the PLT entry. ABS32/REL32
10404 will use the symbol's value, which may point to a PLT entry, but we
10405 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10406 branches in this object should go to it, except if the PLT is too
10407 far away, in which case a long branch stub should be inserted. */
bb224fc3 10408 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10409 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10410 && r_type != R_ARM_CALL
10411 && r_type != R_ARM_JUMP24
10412 && r_type != R_ARM_PLT32)
34e77a92 10413 && plt_offset != (bfd_vma) -1)
7359ea65 10414 {
34e77a92
RS		 10415 /* If we've created a .plt section, and assigned a PLT entry
10416 to this function, it must either be a STT_GNU_IFUNC reference
10417 or not be known to bind locally. In other cases, we should
10418 have cleared the PLT entry by now. */
10419 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10420
10421 value = (splt->output_section->vma
10422 + splt->output_offset
34e77a92 10423 + plt_offset);
0945cdfd 10424 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10425 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10426 contents, rel->r_offset, value,
00a97672 10427 rel->r_addend);
7359ea65
DJ		 10428 }
10429
67687978
PB		 10430 /* When generating a shared object or relocatable executable, these
10431 relocations are copied into the output file to be resolved at
10432 run time. */
0e1862bb 10433 if ((bfd_link_pic (info)
e8b09b87
CL		 10434 || globals->root.is_relocatable_executable
10435 || globals->fdpic_p)
7359ea65 10436 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10437 && !(globals->vxworks_p
3348747a
NS		 10438 && strcmp (input_section->output_section->name,
10439 ".tls_vars") == 0)
bb224fc3 10440 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10441 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10442 && !(input_bfd == globals->stub_bfd
10443 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10444 && (h == NULL
95b03e4a
L		 10445 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10446 && !resolved_to_zero)
7359ea65
DJ		 10447 || h->root.type != bfd_link_hash_undefweak)
10448 && r_type != R_ARM_PC24
5b5bb741
PB		 10449 && r_type != R_ARM_CALL
10450 && r_type != R_ARM_JUMP24
ee06dc07 10451 && r_type != R_ARM_PREL31
7359ea65 10452 && r_type != R_ARM_PLT32)
252b5132 10453 {
947216bf 10454 Elf_Internal_Rela outrel;
b34976b6 10455 bfd_boolean skip, relocate;
e8b09b87 10456 int isrofixup = 0;
f21f3fe0 10457
52db4ec2
JW		 10458 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10459 && !h->def_regular)
10460 {
10461 char *v = _("shared object");
10462
0e1862bb 10463 if (bfd_link_executable (info))
52db4ec2
JW		 10464 v = _("PIE executable");
10465
4eca0228 10466 _bfd_error_handler
871b3ab2 10467 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10468 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10469 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10470 return bfd_reloc_notsupported;
10471 }
10472
0945cdfd
DJ		 10473 *unresolved_reloc_p = FALSE;
10474
34e77a92 10475 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10476 {
83bac4b0
NC		 10477 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10478 ! globals->use_rel);
f21f3fe0 10479
83bac4b0 10480 if (sreloc == NULL)
252b5132 10481 return bfd_reloc_notsupported;
252b5132 10482 }
f21f3fe0 10483
b34976b6
AM		 10484 skip = FALSE;
10485 relocate = FALSE;
f21f3fe0 10486
00a97672 10487 outrel.r_addend = addend;
c629eae0
JJ		 10488 outrel.r_offset =
10489 _bfd_elf_section_offset (output_bfd, info, input_section,
10490 rel->r_offset);
10491 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10492 skip = TRUE;
0bb2d96a 10493 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10494 skip = TRUE, relocate = TRUE;
252b5132
RH		 10495 outrel.r_offset += (input_section->output_section->vma
10496 + input_section->output_offset);
f21f3fe0 10497
252b5132 10498 if (skip)
0bb2d96a 10499 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10500 else if (h != NULL
10501 && h->dynindx != -1
0e1862bb 10502 && (!bfd_link_pic (info)
1dcb9720
JW		 10503 || !(bfd_link_pie (info)
10504 || SYMBOLIC_BIND (info, h))
f5385ebf 10505 || !h->def_regular))
5e681ec4 10506 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10507 else
10508 {
a16385dc
MM		 10509 int symbol;
10510
5e681ec4 10511 /* This symbol is local, or marked to become local. */
e8b09b87
CL		 10512 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10513 || (globals->fdpic_p && !bfd_link_pic(info)));
a16385dc 10514 if (globals->symbian_p)
6366ff1e 10515 {
74541ad4
AM		 10516 asection *osec;
10517
6366ff1e
MM		 10518 /* On Symbian OS, the data segment and text segement
10519 can be relocated independently. Therefore, we
10520 must indicate the segment to which this
10521 relocation is relative. The BPABI allows us to
10522 use any symbol in the right segment; we just use
10523 the section symbol as it is convenient. (We
10524 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10525 will not appear in the dynamic symbol table.)
10526
10527 Note that the dynamic linker ignores the section
10528 symbol value, so we don't subtract osec->vma
10529 from the emitted reloc addend. */
10dbd1f3 10530 if (sym_sec)
74541ad4 10531 osec = sym_sec->output_section;
10dbd1f3 10532 else
74541ad4
AM		 10533 osec = input_section->output_section;
10534 symbol = elf_section_data (osec)->dynindx;
10535 if (symbol == 0)
10536 {
10537 struct elf_link_hash_table *htab = elf_hash_table (info);
10538
10539 if ((osec->flags & SEC_READONLY) == 0
10540 && htab->data_index_section != NULL)
10541 osec = htab->data_index_section;
10542 else
10543 osec = htab->text_index_section;
10544 symbol = elf_section_data (osec)->dynindx;
10545 }
6366ff1e
MM		 10546 BFD_ASSERT (symbol != 0);
10547 }
a16385dc
MM		 10548 else
10549 /* On SVR4-ish systems, the dynamic loader cannot
10550 relocate the text and data segments independently,
10551 so the symbol does not matter. */
10552 symbol = 0;
34e77a92
RS		 10553 if (dynreloc_st_type == STT_GNU_IFUNC)
10554 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10555 to the .iplt entry. Instead, every non-call reference
10556 must use an R_ARM_IRELATIVE relocation to obtain the
10557 correct run-time address. */
10558 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
e8b09b87
CL		 10559 else if (globals->fdpic_p && !bfd_link_pic(info))
10560 isrofixup = 1;
34e77a92
RS		 10561 else
10562 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10563 if (globals->use_rel)
10564 relocate = TRUE;
10565 else
34e77a92 10566 outrel.r_addend += dynreloc_value;
252b5132 10567 }
f21f3fe0 10568
e8b09b87
CL		 10569 if (isrofixup)
10570 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
10571 else
10572 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10573
f21f3fe0 10574 /* If this reloc is against an external symbol, we do not want to
252b5132 10575 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10576 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10577 if (! relocate)
10578 return bfd_reloc_ok;
9a5aca8c 10579
f21f3fe0 10580 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10581 contents, rel->r_offset,
10582 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10583 }
10584 else switch (r_type)
10585 {
00a97672
RS		 10586 case R_ARM_ABS12:
10587 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10588
dfc5f959 10589 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10590 case R_ARM_CALL:
10591 case R_ARM_JUMP24:
8029a119 10592 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10593 case R_ARM_PLT32:
906e58ca 10594 {
906e58ca
NC		 10595 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10596
dfc5f959 10597 if (r_type == R_ARM_XPC25)
252b5132 10598 {
dfc5f959
NC		 10599 /* Check for Arm calling Arm function. */
10600 /* FIXME: Should we translate the instruction into a BL
10601 instruction instead ? */
35fc36a8 10602 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10603 _bfd_error_handler
90b6238f
AM		 10604 (_("\%pB: warning: %s BLX instruction targets"
10605 " %s function '%s'"),
10606 input_bfd, "ARM",
10607 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10608 }
155d87d7 10609 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10610 {
10611 /* Check for Arm calling Thumb function. */
35fc36a8 10612 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10613 {
f2a9dd69
DJ		 10614 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10615 output_bfd, input_section,
10616 hit_data, sym_sec, rel->r_offset,
10617 signed_addend, value,
10618 error_message))
10619 return bfd_reloc_ok;
10620 else
10621 return bfd_reloc_dangerous;
dfc5f959 10622 }
252b5132 10623 }
ba96a88f 10624
906e58ca 10625 /* Check if a stub has to be inserted because the
8029a119 10626 destination is too far or we are changing mode. */
155d87d7
CL		 10627 if ( r_type == R_ARM_CALL
10628 || r_type == R_ARM_JUMP24
10629 || r_type == R_ARM_PLT32)
906e58ca 10630 {
fe33d2fa
CL		 10631 enum elf32_arm_stub_type stub_type = arm_stub_none;
10632 struct elf32_arm_link_hash_entry *hash;
10633
10634 hash = (struct elf32_arm_link_hash_entry *) h;
10635 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10636 st_type, &branch_type,
10637 hash, value, sym_sec,
fe33d2fa 10638 input_bfd, sym_name);
5fa9e92f 10639
fe33d2fa 10640 if (stub_type != arm_stub_none)
906e58ca
NC		 10641 {
10642 /* The target is out of reach, so redirect the
10643 branch to the local stub for this function. */
906e58ca
NC		 10644 stub_entry = elf32_arm_get_stub_entry (input_section,
10645 sym_sec, h,
fe33d2fa
CL		 10646 rel, globals,
10647 stub_type);
9cd3e4e5
NC		 10648 {
10649 if (stub_entry != NULL)
10650 value = (stub_entry->stub_offset
10651 + stub_entry->stub_sec->output_offset
10652 + stub_entry->stub_sec->output_section->vma);
10653
10654 if (plt_offset != (bfd_vma) -1)
10655 *unresolved_reloc_p = FALSE;
10656 }
906e58ca 10657 }
fe33d2fa
CL		 10658 else
10659 {
10660 /* If the call goes through a PLT entry, make sure to
10661 check distance to the right destination address. */
34e77a92 10662 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10663 {
10664 value = (splt->output_section->vma
10665 + splt->output_offset
34e77a92 10666 + plt_offset);
fe33d2fa
CL		 10667 *unresolved_reloc_p = FALSE;
10668 /* The PLT entry is in ARM mode, regardless of the
10669 target function. */
35fc36a8 10670 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10671 }
10672 }
906e58ca
NC		 10673 }
10674
dea514f5
PB		 10675 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10676 where:
10677 S is the address of the symbol in the relocation.
10678 P is address of the instruction being relocated.
10679 A is the addend (extracted from the instruction) in bytes.
10680
10681 S is held in 'value'.
10682 P is the base address of the section containing the
10683 instruction plus the offset of the reloc into that
10684 section, ie:
10685 (input_section->output_section->vma +
10686 input_section->output_offset +
10687 rel->r_offset).
10688 A is the addend, converted into bytes, ie:
10689 (signed_addend * 4)
10690
10691 Note: None of these operations have knowledge of the pipeline
10692 size of the processor, thus it is up to the assembler to
10693 encode this information into the addend. */
10694 value -= (input_section->output_section->vma
10695 + input_section->output_offset);
10696 value -= rel->r_offset;
4e7fd91e
PB		 10697 if (globals->use_rel)
10698 value += (signed_addend << howto->size);
10699 else
10700 /* RELA addends do not have to be adjusted by howto->size. */
10701 value += signed_addend;
23080146 10702
dcb5e6e6
NC		 10703 signed_addend = value;
10704 signed_addend >>= howto->rightshift;
9a5aca8c 10705
5ab79981 10706 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10707 the next instruction unless a PLT entry will be created.
77b4f08f 10708 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10709 The jump to the next instruction is optimized as a NOP depending
10710 on the architecture. */
ffcb4889 10711 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10712 && plt_offset == (bfd_vma) -1)
77b4f08f 10713 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10714 {
cd1dac3d
DG		 10715 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10716
10717 if (arch_has_arm_nop (globals))
10718 value |= 0x0320f000;
10719 else
10720 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10721 }
10722 else
59f2c4e7 10723 {
9b485d32 10724 /* Perform a signed range check. */
dcb5e6e6 10725 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10726 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10727 return bfd_reloc_overflow;
9a5aca8c 10728
5ab79981 10729 addend = (value & 2);
39b41c9c 10730
5ab79981
PB		 10731 value = (signed_addend & howto->dst_mask)
10732 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10733
5ab79981
PB		 10734 if (r_type == R_ARM_CALL)
10735 {
155d87d7 10736 /* Set the H bit in the BLX instruction. */
35fc36a8 10737 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10738 {
10739 if (addend)
10740 value |= (1 << 24);
10741 else
10742 value &= ~(bfd_vma)(1 << 24);
10743 }
10744
5ab79981 10745 /* Select the correct instruction (BL or BLX). */
906e58ca 10746 /* Only if we are not handling a BL to a stub. In this
8029a119 10747 case, mode switching is performed by the stub. */
35fc36a8 10748 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10749 value |= (1 << 28);
63e1a0fc 10750 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10751 {
10752 value &= ~(bfd_vma)(1 << 28);
10753 value |= (1 << 24);
10754 }
39b41c9c
PB		 10755 }
10756 }
906e58ca 10757 }
252b5132 10758 break;
f21f3fe0 10759
252b5132
RH		 10760 case R_ARM_ABS32:
10761 value += addend;
35fc36a8 10762 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10763 value |= 1;
10764 break;
f21f3fe0 10765
bb224fc3
MS		 10766 case R_ARM_ABS32_NOI:
10767 value += addend;
10768 break;
10769
252b5132 10770 case R_ARM_REL32:
a8bc6c78 10771 value += addend;
35fc36a8 10772 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10773 value |= 1;
252b5132 10774 value -= (input_section->output_section->vma
62efb346 10775 + input_section->output_offset + rel->r_offset);
252b5132 10776 break;
eb043451 10777
bb224fc3
MS		 10778 case R_ARM_REL32_NOI:
10779 value += addend;
10780 value -= (input_section->output_section->vma
10781 + input_section->output_offset + rel->r_offset);
10782 break;
10783
eb043451
PB		 10784 case R_ARM_PREL31:
10785 value -= (input_section->output_section->vma
10786 + input_section->output_offset + rel->r_offset);
10787 value += signed_addend;
10788 if (! h || h->root.type != bfd_link_hash_undefweak)
10789 {
8029a119 10790 /* Check for overflow. */
eb043451
PB		 10791 if ((value ^ (value >> 1)) & (1 << 30))
10792 return bfd_reloc_overflow;
10793 }
10794 value &= 0x7fffffff;
10795 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10796 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10797 value |= 1;
10798 break;
252b5132 10799 }
f21f3fe0 10800
252b5132
RH		 10801 bfd_put_32 (input_bfd, value, hit_data);
10802 return bfd_reloc_ok;
10803
10804 case R_ARM_ABS8:
fd0fd00c
MJ		 10805 /* PR 16202: Refectch the addend using the correct size. */
10806 if (globals->use_rel)
10807 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10808 value += addend;
4e67d4ca
DG		 10809
10810 /* There is no way to tell whether the user intended to use a signed or
10811 unsigned addend. When checking for overflow we accept either,
10812 as specified by the AAELF. */
10813 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10814 return bfd_reloc_overflow;
10815
10816 bfd_put_8 (input_bfd, value, hit_data);
10817 return bfd_reloc_ok;
10818
10819 case R_ARM_ABS16:
fd0fd00c
MJ		 10820 /* PR 16202: Refectch the addend using the correct size. */
10821 if (globals->use_rel)
10822 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10823 value += addend;
10824
4e67d4ca
DG		 10825 /* See comment for R_ARM_ABS8. */
10826 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10827 return bfd_reloc_overflow;
10828
10829 bfd_put_16 (input_bfd, value, hit_data);
10830 return bfd_reloc_ok;
10831
252b5132 10832 case R_ARM_THM_ABS5:
9b485d32 10833 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10834 if (globals->use_rel)
10835 {
10836 /* Need to refetch addend. */
10837 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10838 /* ??? Need to determine shift amount from operand size. */
10839 addend >>= howto->rightshift;
10840 }
252b5132
RH		 10841 value += addend;
10842
10843 /* ??? Isn't value unsigned? */
10844 if ((long) value > 0x1f || (long) value < -0x10)
10845 return bfd_reloc_overflow;
10846
10847 /* ??? Value needs to be properly shifted into place first. */
10848 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10849 bfd_put_16 (input_bfd, value, hit_data);
10850 return bfd_reloc_ok;
10851
2cab6cc3
MS		 10852 case R_ARM_THM_ALU_PREL_11_0:
10853 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10854 {
10855 bfd_vma insn;
10856 bfd_signed_vma relocation;
10857
10858 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10859 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10860
99059e56
RM		 10861 if (globals->use_rel)
10862 {
10863 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10864 | ((insn & (1 << 26)) >> 15);
10865 if (insn & 0xf00000)
10866 signed_addend = -signed_addend;
10867 }
2cab6cc3
MS		 10868
10869 relocation = value + signed_addend;
79f08007 10870 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10871 + input_section->output_offset
10872 + rel->r_offset);
2cab6cc3 10873
8c65b54f
CS		 10874 /* PR 21523: Use an absolute value. The user of this reloc will
10875 have already selected an ADD or SUB insn appropriately. */
e652757b 10876 value = labs (relocation);
2cab6cc3 10877
99059e56
RM		 10878 if (value >= 0x1000)
10879 return bfd_reloc_overflow;
2cab6cc3 10880
e645cf40
AG		 10881 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10882 if (branch_type == ST_BRANCH_TO_THUMB)
10883 value |= 1;
10884
2cab6cc3 10885 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10886 | ((value & 0x700) << 4)
10887 | ((value & 0x800) << 15);
10888 if (relocation < 0)
10889 insn |= 0xa00000;
2cab6cc3
MS		 10890
10891 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10892 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10893
99059e56 10894 return bfd_reloc_ok;
2cab6cc3
MS		 10895 }
10896
e1ec24c6
NC		 10897 case R_ARM_THM_PC8:
10898 /* PR 10073: This reloc is not generated by the GNU toolchain,
10899 but it is supported for compatibility with third party libraries
10900 generated by other compilers, specifically the ARM/IAR. */
10901 {
10902 bfd_vma insn;
10903 bfd_signed_vma relocation;
10904
10905 insn = bfd_get_16 (input_bfd, hit_data);
10906
99059e56 10907 if (globals->use_rel)
79f08007 10908 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10909
10910 relocation = value + addend;
79f08007 10911 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10912 + input_section->output_offset
10913 + rel->r_offset);
e1ec24c6 10914
b6518b38 10915 value = relocation;
e1ec24c6
NC		 10916
10917 /* We do not check for overflow of this reloc. Although strictly
10918 speaking this is incorrect, it appears to be necessary in order
10919 to work with IAR generated relocs. Since GCC and GAS do not
10920 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10921 a problem for them. */
10922 value &= 0x3fc;
10923
10924 insn = (insn & 0xff00) | (value >> 2);
10925
10926 bfd_put_16 (input_bfd, insn, hit_data);
10927
99059e56 10928 return bfd_reloc_ok;
e1ec24c6
NC		 10929 }
10930
2cab6cc3
MS		 10931 case R_ARM_THM_PC12:
10932 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10933 {
10934 bfd_vma insn;
10935 bfd_signed_vma relocation;
10936
10937 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10938 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10939
99059e56
RM		 10940 if (globals->use_rel)
10941 {
10942 signed_addend = insn & 0xfff;
10943 if (!(insn & (1 << 23)))
10944 signed_addend = -signed_addend;
10945 }
2cab6cc3
MS		 10946
10947 relocation = value + signed_addend;
79f08007 10948 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10949 + input_section->output_offset
10950 + rel->r_offset);
2cab6cc3 10951
b6518b38 10952 value = relocation;
2cab6cc3 10953
99059e56
RM		 10954 if (value >= 0x1000)
10955 return bfd_reloc_overflow;
2cab6cc3
MS		 10956
10957 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10958 if (relocation >= 0)
10959 insn |= (1 << 23);
2cab6cc3
MS		 10960
10961 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10962 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10963
99059e56 10964 return bfd_reloc_ok;
2cab6cc3
MS		 10965 }
10966
dfc5f959 10967 case R_ARM_THM_XPC22:
c19d1205 10968 case R_ARM_THM_CALL:
bd97cb95 10969 case R_ARM_THM_JUMP24:
dfc5f959 10970 /* Thumb BL (branch long instruction). */
252b5132 10971 {
b34976b6 10972 bfd_vma relocation;
99059e56 10973 bfd_vma reloc_sign;
b34976b6
AM		 10974 bfd_boolean overflow = FALSE;
10975 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10976 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 10977 bfd_signed_vma reloc_signed_max;
10978 bfd_signed_vma reloc_signed_min;
b34976b6 10979 bfd_vma check;
252b5132 10980 bfd_signed_vma signed_check;
e95de063 10981 int bitsize;
cd1dac3d 10982 const int thumb2 = using_thumb2 (globals);
5e866f5a 10983 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 10984
5ab79981 10985 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 10986 the next instruction unless a PLT entry will be created.
10987 The jump to the next instruction is optimized as a NOP.W for
10988 Thumb-2 enabled architectures. */
19540007 10989 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 10990 && plt_offset == (bfd_vma) -1)
5ab79981 10991 {
60a019a0 10992 if (thumb2)
cd1dac3d
DG		 10993 {
10994 bfd_put_16 (input_bfd, 0xf3af, hit_data);
10995 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
10996 }
10997 else
10998 {
10999 bfd_put_16 (input_bfd, 0xe000, hit_data);
11000 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11001 }
5ab79981
PB		 11002 return bfd_reloc_ok;
11003 }
11004
e95de063 11005 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 11006 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 11007 if (globals->use_rel)
11008 {
99059e56
RM		 11009 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11010 bfd_vma upper = upper_insn & 0x3ff;
11011 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 11012 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11013 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 11014 bfd_vma i1 = j1 ^ s ? 0 : 1;
11015 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 11016
99059e56
RM		 11017 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11018 /* Sign extend. */
11019 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 11020
4e7fd91e
PB		 11021 signed_addend = addend;
11022 }
cb1afa5c 11023
dfc5f959
NC		 11024 if (r_type == R_ARM_THM_XPC22)
11025 {
11026 /* Check for Thumb to Thumb call. */
11027 /* FIXME: Should we translate the instruction into a BL
11028 instruction instead ? */
35fc36a8 11029 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 11030 _bfd_error_handler
90b6238f
AM		 11031 (_("%pB: warning: %s BLX instruction targets"
11032 " %s function '%s'"),
11033 input_bfd, "Thumb",
11034 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 11035 }
11036 else
252b5132 11037 {
dfc5f959
NC		 11038 /* If it is not a call to Thumb, assume call to Arm.
11039 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 11040 function call at all, but rather a long jump. Calls through
11041 the PLT do not require stubs. */
34e77a92 11042 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 11043 {
bd97cb95 11044 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11045 {
11046 /* Convert BL to BLX. */
11047 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11048 }
155d87d7
CL		 11049 else if (( r_type != R_ARM_THM_CALL)
11050 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 11051 {
11052 if (elf32_thumb_to_arm_stub
11053 (info, sym_name, input_bfd, output_bfd, input_section,
11054 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11055 error_message))
11056 return bfd_reloc_ok;
11057 else
11058 return bfd_reloc_dangerous;
11059 }
da5938a2 11060 }
35fc36a8
RS		 11061 else if (branch_type == ST_BRANCH_TO_THUMB
11062 && globals->use_blx
bd97cb95 11063 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11064 {
11065 /* Make sure this is a BL. */
11066 lower_insn |= 0x1800;
11067 }
252b5132 11068 }
f21f3fe0 11069
fe33d2fa 11070 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 11071 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 11072 {
11073 /* Check if a stub has to be inserted because the destination
8029a119 11074 is too far. */
fe33d2fa
CL		 11075 struct elf32_arm_stub_hash_entry *stub_entry;
11076 struct elf32_arm_link_hash_entry *hash;
11077
11078 hash = (struct elf32_arm_link_hash_entry *) h;
11079
11080 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 11081 st_type, &branch_type,
11082 hash, value, sym_sec,
fe33d2fa
CL		 11083 input_bfd, sym_name);
11084
11085 if (stub_type != arm_stub_none)
906e58ca
NC		 11086 {
11087 /* The target is out of reach or we are changing modes, so
11088 redirect the branch to the local stub for this
11089 function. */
11090 stub_entry = elf32_arm_get_stub_entry (input_section,
11091 sym_sec, h,
fe33d2fa
CL		 11092 rel, globals,
11093 stub_type);
906e58ca 11094 if (stub_entry != NULL)
9cd3e4e5
NC		 11095 {
11096 value = (stub_entry->stub_offset
11097 + stub_entry->stub_sec->output_offset
11098 + stub_entry->stub_sec->output_section->vma);
11099
11100 if (plt_offset != (bfd_vma) -1)
11101 *unresolved_reloc_p = FALSE;
11102 }
906e58ca 11103
f4ac8484 11104 /* If this call becomes a call to Arm, force BLX. */
155d87d7 11105 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 11106 {
11107 if ((stub_entry
11108 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 11109 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 11110 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11111 }
906e58ca
NC		 11112 }
11113 }
11114
fe33d2fa 11115 /* Handle calls via the PLT. */
34e77a92 11116 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 11117 {
11118 value = (splt->output_section->vma
11119 + splt->output_offset
34e77a92 11120 + plt_offset);
fe33d2fa 11121
eed94f8f
NC		 11122 if (globals->use_blx
11123 && r_type == R_ARM_THM_CALL
11124 && ! using_thumb_only (globals))
fe33d2fa
CL		 11125 {
11126 /* If the Thumb BLX instruction is available, convert
11127 the BL to a BLX instruction to call the ARM-mode
11128 PLT entry. */
11129 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 11130 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 11131 }
11132 else
11133 {
eed94f8f
NC		 11134 if (! using_thumb_only (globals))
11135 /* Target the Thumb stub before the ARM PLT entry. */
11136 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 11137 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 11138 }
11139 *unresolved_reloc_p = FALSE;
11140 }
11141
ba96a88f 11142 relocation = value + signed_addend;
f21f3fe0 11143
252b5132 11144 relocation -= (input_section->output_section->vma
ba96a88f
NC		 11145 + input_section->output_offset
11146 + rel->r_offset);
9a5aca8c 11147
252b5132
RH		 11148 check = relocation >> howto->rightshift;
11149
11150 /* If this is a signed value, the rightshift just dropped
11151 leading 1 bits (assuming twos complement). */
11152 if ((bfd_signed_vma) relocation >= 0)
11153 signed_check = check;
11154 else
11155 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11156
e95de063
MS		 11157 /* Calculate the permissable maximum and minimum values for
11158 this relocation according to whether we're relocating for
11159 Thumb-2 or not. */
11160 bitsize = howto->bitsize;
5e866f5a 11161 if (!thumb2_bl)
e95de063 11162 bitsize -= 2;
f6ebfac0 11163 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 11164 reloc_signed_min = ~reloc_signed_max;
11165
252b5132 11166 /* Assumes two's complement. */
ba96a88f 11167 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 11168 overflow = TRUE;
252b5132 11169
bd97cb95 11170 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 11171 /* For a BLX instruction, make sure that the relocation is rounded up
11172 to a word boundary. This follows the semantics of the instruction
11173 which specifies that bit 1 of the target address will come from bit
11174 1 of the base address. */
11175 relocation = (relocation + 2) & ~ 3;
cb1afa5c 11176
e95de063
MS		 11177 /* Put RELOCATION back into the insn. Assumes two's complement.
11178 We use the Thumb-2 encoding, which is safe even if dealing with
11179 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 11180 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 11181 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 11182 | ((relocation >> 12) & 0x3ff)
11183 | (reloc_sign << 10);
906e58ca 11184 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 11185 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11186 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11187 | ((relocation >> 1) & 0x7ff);
c62e1cc3 11188
252b5132
RH		 11189 /* Put the relocated value back in the object file: */
11190 bfd_put_16 (input_bfd, upper_insn, hit_data);
11191 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11192
11193 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11194 }
11195 break;
11196
c19d1205
ZW		 11197 case R_ARM_THM_JUMP19:
11198 /* Thumb32 conditional branch instruction. */
11199 {
11200 bfd_vma relocation;
11201 bfd_boolean overflow = FALSE;
11202 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11203 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 11204 bfd_signed_vma reloc_signed_max = 0xffffe;
11205 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 11206 bfd_signed_vma signed_check;
07d6d2b8 11207 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 11208 struct elf32_arm_stub_hash_entry *stub_entry;
11209 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 11210
11211 /* Need to refetch the addend, reconstruct the top three bits,
11212 and squish the two 11 bit pieces together. */
11213 if (globals->use_rel)
11214 {
11215 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 11216 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 11217 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11218 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11219 bfd_vma lower = (lower_insn & 0x07ff);
11220
a00a1f35
MS		 11221 upper |= J1 << 6;
11222 upper |= J2 << 7;
11223 upper |= (!S) << 8;
c19d1205
ZW		 11224 upper -= 0x0100; /* Sign extend. */
11225
11226 addend = (upper << 12) | (lower << 1);
11227 signed_addend = addend;
11228 }
11229
bd97cb95 11230 /* Handle calls via the PLT. */
34e77a92 11231 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 11232 {
11233 value = (splt->output_section->vma
11234 + splt->output_offset
34e77a92 11235 + plt_offset);
bd97cb95
DJ		 11236 /* Target the Thumb stub before the ARM PLT entry. */
11237 value -= PLT_THUMB_STUB_SIZE;
11238 *unresolved_reloc_p = FALSE;
11239 }
11240
c5423981
TG		 11241 hash = (struct elf32_arm_link_hash_entry *)h;
11242
11243 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 11244 st_type, &branch_type,
11245 hash, value, sym_sec,
11246 input_bfd, sym_name);
c5423981
TG		 11247 if (stub_type != arm_stub_none)
11248 {
11249 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 11250 sym_sec, h,
11251 rel, globals,
11252 stub_type);
c5423981
TG		 11253 if (stub_entry != NULL)
11254 {
07d6d2b8
AM		 11255 value = (stub_entry->stub_offset
11256 + stub_entry->stub_sec->output_offset
11257 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 11258 }
11259 }
c19d1205 11260
99059e56 11261 relocation = value + signed_addend;
c19d1205
ZW		 11262 relocation -= (input_section->output_section->vma
11263 + input_section->output_offset
11264 + rel->r_offset);
a00a1f35 11265 signed_check = (bfd_signed_vma) relocation;
c19d1205 11266
c19d1205
ZW		 11267 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11268 overflow = TRUE;
11269
11270 /* Put RELOCATION back into the insn. */
11271 {
11272 bfd_vma S = (relocation & 0x00100000) >> 20;
11273 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11274 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11275 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11276 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11277
a00a1f35 11278 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 11279 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11280 }
11281
11282 /* Put the relocated value back in the object file: */
11283 bfd_put_16 (input_bfd, upper_insn, hit_data);
11284 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11285
11286 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11287 }
11288
11289 case R_ARM_THM_JUMP11:
11290 case R_ARM_THM_JUMP8:
11291 case R_ARM_THM_JUMP6:
51c5503b
NC		 11292 /* Thumb B (branch) instruction). */
11293 {
6cf9e9fe 11294 bfd_signed_vma relocation;
51c5503b
NC		 11295 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11296 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11297 bfd_signed_vma signed_check;
11298
c19d1205
ZW		 11299 /* CZB cannot jump backward. */
11300 if (r_type == R_ARM_THM_JUMP6)
11301 reloc_signed_min = 0;
11302
4e7fd91e 11303 if (globals->use_rel)
6cf9e9fe 11304 {
4e7fd91e
PB		 11305 /* Need to refetch addend. */
11306 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
11307 if (addend & ((howto->src_mask + 1) >> 1))
11308 {
11309 signed_addend = -1;
11310 signed_addend &= ~ howto->src_mask;
11311 signed_addend |= addend;
11312 }
11313 else
11314 signed_addend = addend;
11315 /* The value in the insn has been right shifted. We need to
11316 undo this, so that we can perform the address calculation
11317 in terms of bytes. */
11318 signed_addend <<= howto->rightshift;
6cf9e9fe 11319 }
6cf9e9fe 11320 relocation = value + signed_addend;
51c5503b
NC		 11321
11322 relocation -= (input_section->output_section->vma
11323 + input_section->output_offset
11324 + rel->r_offset);
11325
6cf9e9fe
NC		 11326 relocation >>= howto->rightshift;
11327 signed_check = relocation;
c19d1205
ZW		 11328
11329 if (r_type == R_ARM_THM_JUMP6)
11330 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11331 else
11332 relocation &= howto->dst_mask;
51c5503b 11333 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11334
51c5503b
NC		 11335 bfd_put_16 (input_bfd, relocation, hit_data);
11336
11337 /* Assumes two's complement. */
11338 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11339 return bfd_reloc_overflow;
11340
11341 return bfd_reloc_ok;
11342 }
cedb70c5 11343
8375c36b
PB		 11344 case R_ARM_ALU_PCREL7_0:
11345 case R_ARM_ALU_PCREL15_8:
11346 case R_ARM_ALU_PCREL23_15:
11347 {
11348 bfd_vma insn;
11349 bfd_vma relocation;
11350
11351 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11352 if (globals->use_rel)
11353 {
11354 /* Extract the addend. */
11355 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11356 signed_addend = addend;
11357 }
8375c36b
PB		 11358 relocation = value + signed_addend;
11359
11360 relocation -= (input_section->output_section->vma
11361 + input_section->output_offset
11362 + rel->r_offset);
11363 insn = (insn & ~0xfff)
11364 | ((howto->bitpos << 7) & 0xf00)
11365 | ((relocation >> howto->bitpos) & 0xff);
11366 bfd_put_32 (input_bfd, value, hit_data);
11367 }
11368 return bfd_reloc_ok;
11369
252b5132
RH		 11370 case R_ARM_GNU_VTINHERIT:
11371 case R_ARM_GNU_VTENTRY:
11372 return bfd_reloc_ok;
11373
c19d1205 11374 case R_ARM_GOTOFF32:
252b5132 11375 /* Relocation is relative to the start of the
99059e56 11376 global offset table. */
252b5132
RH		 11377
11378 BFD_ASSERT (sgot != NULL);
11379 if (sgot == NULL)
99059e56 11380 return bfd_reloc_notsupported;
9a5aca8c 11381
cedb70c5 11382 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11383 address by one, so that attempts to call the function pointer will
11384 correctly interpret it as Thumb code. */
35fc36a8 11385 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11386 value += 1;
11387
252b5132 11388 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11389 calculation. We always want the start of .got. If we
11390 define _GLOBAL_OFFSET_TABLE in a different way, as is
11391 permitted by the ABI, we might have to change this
11392 calculation. */
252b5132 11393 value -= sgot->output_section->vma;
f21f3fe0 11394 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11395 contents, rel->r_offset, value,
00a97672 11396 rel->r_addend);
252b5132
RH		 11397
11398 case R_ARM_GOTPC:
a7c10850 11399 /* Use global offset table as symbol value. */
252b5132 11400 BFD_ASSERT (sgot != NULL);
f21f3fe0 11401
252b5132 11402 if (sgot == NULL)
99059e56 11403 return bfd_reloc_notsupported;
252b5132 11404
0945cdfd 11405 *unresolved_reloc_p = FALSE;
252b5132 11406 value = sgot->output_section->vma;
f21f3fe0 11407 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11408 contents, rel->r_offset, value,
00a97672 11409 rel->r_addend);
f21f3fe0 11410
252b5132 11411 case R_ARM_GOT32:
eb043451 11412 case R_ARM_GOT_PREL:
252b5132 11413 /* Relocation is to the entry for this symbol in the
99059e56 11414 global offset table. */
252b5132
RH		 11415 if (sgot == NULL)
11416 return bfd_reloc_notsupported;
f21f3fe0 11417
34e77a92
RS		 11418 if (dynreloc_st_type == STT_GNU_IFUNC
11419 && plt_offset != (bfd_vma) -1
11420 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11421 {
11422 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11423 symbol, and the relocation resolves directly to the runtime
11424 target rather than to the .iplt entry. This means that any
11425 .got entry would be the same value as the .igot.plt entry,
11426 so there's no point creating both. */
11427 sgot = globals->root.igotplt;
11428 value = sgot->output_offset + gotplt_offset;
11429 }
11430 else if (h != NULL)
252b5132
RH		 11431 {
11432 bfd_vma off;
f21f3fe0 11433
252b5132
RH		 11434 off = h->got.offset;
11435 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11436 if ((off & 1) != 0)
252b5132 11437 {
b436d854
RS		 11438 /* We have already processsed one GOT relocation against
11439 this symbol. */
11440 off &= ~1;
11441 if (globals->root.dynamic_sections_created
11442 && !SYMBOL_REFERENCES_LOCAL (info, h))
11443 *unresolved_reloc_p = FALSE;
11444 }
11445 else
11446 {
11447 Elf_Internal_Rela outrel;
e8b09b87 11448 int isrofixup = 0;
b436d854 11449
e8b09b87
CL		 11450 if (((h->dynindx != -1) || globals->fdpic_p)
11451 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11452 {
11453 /* If the symbol doesn't resolve locally in a static
11454 object, we have an undefined reference. If the
11455 symbol doesn't resolve locally in a dynamic object,
11456 it should be resolved by the dynamic linker. */
11457 if (globals->root.dynamic_sections_created)
11458 {
11459 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11460 *unresolved_reloc_p = FALSE;
11461 }
11462 else
11463 outrel.r_info = 0;
11464 outrel.r_addend = 0;
11465 }
252b5132
RH		 11466 else
11467 {
34e77a92 11468 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11469 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11470 else if (bfd_link_pic (info)
11471 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11472 || h->root.type != bfd_link_hash_undefweak))
99059e56 11473 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
e8b09b87
CL		 11474 else if (globals->fdpic_p)
11475 isrofixup = 1;
99059e56
RM		 11476 else
11477 outrel.r_info = 0;
34e77a92 11478 outrel.r_addend = dynreloc_value;
b436d854 11479 }
ee29b9fb 11480
b436d854
RS		 11481 /* The GOT entry is initialized to zero by default.
11482 See if we should install a different value. */
11483 if (outrel.r_addend != 0
e8b09b87 11484 && (outrel.r_info == 0 || globals->use_rel || isrofixup))
b436d854
RS		 11485 {
11486 bfd_put_32 (output_bfd, outrel.r_addend,
11487 sgot->contents + off);
11488 outrel.r_addend = 0;
252b5132 11489 }
f21f3fe0 11490
e8b09b87 11491 if (outrel.r_info != 0 && !isrofixup)
b436d854
RS		 11492 {
11493 outrel.r_offset = (sgot->output_section->vma
11494 + sgot->output_offset
11495 + off);
11496 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11497 }
e8b09b87
CL		 11498 else if (isrofixup)
11499 {
11500 arm_elf_add_rofixup(output_bfd,
11501 elf32_arm_hash_table(info)->srofixup,
11502 sgot->output_section->vma
11503 + sgot->output_offset + off);
11504 }
b436d854
RS		 11505 h->got.offset |= 1;
11506 }
252b5132
RH		 11507 value = sgot->output_offset + off;
11508 }
11509 else
11510 {
11511 bfd_vma off;
f21f3fe0 11512
5025eb7c
AO		 11513 BFD_ASSERT (local_got_offsets != NULL
11514 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11515
252b5132 11516 off = local_got_offsets[r_symndx];
f21f3fe0 11517
252b5132
RH		 11518 /* The offset must always be a multiple of 4. We use the
11519 least significant bit to record whether we have already
9b485d32 11520 generated the necessary reloc. */
252b5132
RH		 11521 if ((off & 1) != 0)
11522 off &= ~1;
11523 else
11524 {
00a97672 11525 if (globals->use_rel)
34e77a92 11526 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 11527
0e1862bb 11528 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 11529 {
947216bf 11530 Elf_Internal_Rela outrel;
f21f3fe0 11531
34e77a92 11532 outrel.r_addend = addend + dynreloc_value;
252b5132 11533 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11534 + sgot->output_offset
252b5132 11535 + off);
34e77a92 11536 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11537 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 11538 else
11539 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 11540 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11541 }
e8b09b87
CL		 11542 else if (globals->fdpic_p)
11543 {
11544 /* For FDPIC executables, we use rofixup to fix
11545 address at runtime. */
11546 arm_elf_add_rofixup(output_bfd, globals->srofixup,
11547 sgot->output_section->vma + sgot->output_offset
11548 + off);
11549 }
f21f3fe0 11550
252b5132
RH		 11551 local_got_offsets[r_symndx] |= 1;
11552 }
f21f3fe0 11553
252b5132
RH		 11554 value = sgot->output_offset + off;
11555 }
eb043451
PB		 11556 if (r_type != R_ARM_GOT32)
11557 value += sgot->output_section->vma;
9a5aca8c 11558
f21f3fe0 11559 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11560 contents, rel->r_offset, value,
00a97672 11561 rel->r_addend);
f21f3fe0 11562
ba93b8ac
DJ		 11563 case R_ARM_TLS_LDO32:
11564 value = value - dtpoff_base (info);
11565
11566 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11567 contents, rel->r_offset, value,
11568 rel->r_addend);
ba93b8ac
DJ		 11569
11570 case R_ARM_TLS_LDM32:
5c5a4843 11571 case R_ARM_TLS_LDM32_FDPIC:
ba93b8ac
DJ		 11572 {
11573 bfd_vma off;
11574
362d30a1 11575 if (sgot == NULL)
ba93b8ac
DJ		 11576 abort ();
11577
11578 off = globals->tls_ldm_got.offset;
11579
11580 if ((off & 1) != 0)
11581 off &= ~1;
11582 else
11583 {
11584 /* If we don't know the module number, create a relocation
11585 for it. */
0e1862bb 11586 if (bfd_link_pic (info))
ba93b8ac
DJ		 11587 {
11588 Elf_Internal_Rela outrel;
ba93b8ac 11589
362d30a1 11590 if (srelgot == NULL)
ba93b8ac
DJ		 11591 abort ();
11592
00a97672 11593 outrel.r_addend = 0;
362d30a1
RS		 11594 outrel.r_offset = (sgot->output_section->vma
11595 + sgot->output_offset + off);
ba93b8ac
DJ		 11596 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11597
00a97672
RS		 11598 if (globals->use_rel)
11599 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11600 sgot->contents + off);
ba93b8ac 11601
47beaa6a 11602 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11603 }
11604 else
362d30a1 11605 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11606
11607 globals->tls_ldm_got.offset |= 1;
11608 }
11609
5c5a4843 11610 if (r_type == R_ARM_TLS_LDM32_FDPIC)
e8b09b87
CL		 11611 {
11612 bfd_put_32(output_bfd,
11613 globals->root.sgot->output_offset + off,
11614 contents + rel->r_offset);
11615
11616 return bfd_reloc_ok;
11617 }
11618 else
11619 {
11620 value = sgot->output_section->vma + sgot->output_offset + off
11621 - (input_section->output_section->vma
11622 + input_section->output_offset + rel->r_offset);
ba93b8ac 11623
e8b09b87
CL		 11624 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11625 contents, rel->r_offset, value,
11626 rel->r_addend);
11627 }
ba93b8ac
DJ		 11628 }
11629
0855e32b
NS		 11630 case R_ARM_TLS_CALL:
11631 case R_ARM_THM_TLS_CALL:
ba93b8ac 11632 case R_ARM_TLS_GD32:
5c5a4843 11633 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 11634 case R_ARM_TLS_IE32:
5c5a4843 11635 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 11636 case R_ARM_TLS_GOTDESC:
11637 case R_ARM_TLS_DESCSEQ:
11638 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11639 {
0855e32b
NS		 11640 bfd_vma off, offplt;
11641 int indx = 0;
ba93b8ac
DJ		 11642 char tls_type;
11643
0855e32b 11644 BFD_ASSERT (sgot != NULL);
ba93b8ac 11645
ba93b8ac
DJ		 11646 if (h != NULL)
11647 {
11648 bfd_boolean dyn;
11649 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11650 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11651 bfd_link_pic (info),
11652 h)
11653 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11654 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11655 {
11656 *unresolved_reloc_p = FALSE;
11657 indx = h->dynindx;
11658 }
11659 off = h->got.offset;
0855e32b 11660 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11661 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11662 }
11663 else
11664 {
0855e32b 11665 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11666 off = local_got_offsets[r_symndx];
0855e32b 11667 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11668 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11669 }
11670
0855e32b 11671 /* Linker relaxations happens from one of the
b38cadfb 11672 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11673 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11674 tls_type = GOT_TLS_IE;
0855e32b
NS		 11675
11676 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11677
11678 if ((off & 1) != 0)
11679 off &= ~1;
11680 else
11681 {
11682 bfd_boolean need_relocs = FALSE;
11683 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11684 int cur_off = off;
11685
11686 /* The GOT entries have not been initialized yet. Do it
11687 now, and emit any relocations. If both an IE GOT and a
11688 GD GOT are necessary, we emit the GD first. */
11689
0e1862bb 11690 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac 11691 && (h == NULL
95b03e4a
L		 11692 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11693 && !resolved_to_zero)
ba93b8ac
DJ		 11694 || h->root.type != bfd_link_hash_undefweak))
11695 {
11696 need_relocs = TRUE;
0855e32b 11697 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11698 }
11699
0855e32b
NS		 11700 if (tls_type & GOT_TLS_GDESC)
11701 {
47beaa6a
RS		 11702 bfd_byte *loc;
11703
0855e32b
NS		 11704 /* We should have relaxed, unless this is an undefined
11705 weak symbol. */
11706 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11707 || bfd_link_pic (info));
0855e32b 11708 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11709 <= globals->root.sgotplt->size);
0855e32b
NS		 11710
11711 outrel.r_addend = 0;
11712 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11713 + globals->root.sgotplt->output_offset
11714 + offplt
11715 + globals->sgotplt_jump_table_size);
b38cadfb 11716
0855e32b
NS		 11717 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11718 sreloc = globals->root.srelplt;
11719 loc = sreloc->contents;
11720 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11721 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11722 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11723
11724 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11725
11726 /* For globals, the first word in the relocation gets
11727 the relocation index and the top bit set, or zero,
11728 if we're binding now. For locals, it gets the
11729 symbol's offset in the tls section. */
99059e56 11730 bfd_put_32 (output_bfd,
0855e32b
NS		 11731 !h ? value - elf_hash_table (info)->tls_sec->vma
11732 : info->flags & DF_BIND_NOW ? 0
11733 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11734 globals->root.sgotplt->contents + offplt
11735 + globals->sgotplt_jump_table_size);
11736
0855e32b 11737 /* Second word in the relocation is always zero. */
99059e56 11738 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11739 globals->root.sgotplt->contents + offplt
11740 + globals->sgotplt_jump_table_size + 4);
0855e32b 11741 }
ba93b8ac
DJ		 11742 if (tls_type & GOT_TLS_GD)
11743 {
11744 if (need_relocs)
11745 {
00a97672 11746 outrel.r_addend = 0;
362d30a1
RS		 11747 outrel.r_offset = (sgot->output_section->vma
11748 + sgot->output_offset
00a97672 11749 + cur_off);
ba93b8ac 11750 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11751
00a97672
RS		 11752 if (globals->use_rel)
11753 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11754 sgot->contents + cur_off);
00a97672 11755
47beaa6a 11756 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11757
11758 if (indx == 0)
11759 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11760 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11761 else
11762 {
00a97672 11763 outrel.r_addend = 0;
ba93b8ac
DJ		 11764 outrel.r_info = ELF32_R_INFO (indx,
11765 R_ARM_TLS_DTPOFF32);
11766 outrel.r_offset += 4;
00a97672
RS		 11767
11768 if (globals->use_rel)
11769 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11770 sgot->contents + cur_off + 4);
00a97672 11771
47beaa6a
RS		 11772 elf32_arm_add_dynreloc (output_bfd, info,
11773 srelgot, &outrel);
ba93b8ac
DJ		 11774 }
11775 }
11776 else
11777 {
11778 /* If we are not emitting relocations for a
11779 general dynamic reference, then we must be in a
11780 static link or an executable link with the
11781 symbol binding locally. Mark it as belonging
11782 to module 1, the executable. */
11783 bfd_put_32 (output_bfd, 1,
362d30a1 11784 sgot->contents + cur_off);
ba93b8ac 11785 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11786 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11787 }
11788
11789 cur_off += 8;
11790 }
11791
11792 if (tls_type & GOT_TLS_IE)
11793 {
11794 if (need_relocs)
11795 {
00a97672
RS		 11796 if (indx == 0)
11797 outrel.r_addend = value - dtpoff_base (info);
11798 else
11799 outrel.r_addend = 0;
362d30a1
RS		 11800 outrel.r_offset = (sgot->output_section->vma
11801 + sgot->output_offset
ba93b8ac
DJ		 11802 + cur_off);
11803 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11804
00a97672
RS		 11805 if (globals->use_rel)
11806 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11807 sgot->contents + cur_off);
ba93b8ac 11808
47beaa6a 11809 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11810 }
11811 else
11812 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11813 sgot->contents + cur_off);
ba93b8ac
DJ		 11814 cur_off += 4;
11815 }
11816
11817 if (h != NULL)
11818 h->got.offset |= 1;
11819 else
11820 local_got_offsets[r_symndx] |= 1;
11821 }
11822
5c5a4843 11823 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
ba93b8ac 11824 off += 8;
0855e32b
NS		 11825 else if (tls_type & GOT_TLS_GDESC)
11826 off = offplt;
11827
11828 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11829 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11830 {
11831 bfd_signed_vma offset;
12352d3f
PB		 11832 /* TLS stubs are arm mode. The original symbol is a
11833 data object, so branch_type is bogus. */
11834 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11835 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11836 = arm_type_of_stub (info, input_section, rel,
11837 st_type, &branch_type,
0855e32b
NS		 11838 (struct elf32_arm_link_hash_entry *)h,
11839 globals->tls_trampoline, globals->root.splt,
11840 input_bfd, sym_name);
11841
11842 if (stub_type != arm_stub_none)
11843 {
11844 struct elf32_arm_stub_hash_entry *stub_entry
11845 = elf32_arm_get_stub_entry
11846 (input_section, globals->root.splt, 0, rel,
11847 globals, stub_type);
11848 offset = (stub_entry->stub_offset
11849 + stub_entry->stub_sec->output_offset
11850 + stub_entry->stub_sec->output_section->vma);
11851 }
11852 else
11853 offset = (globals->root.splt->output_section->vma
11854 + globals->root.splt->output_offset
11855 + globals->tls_trampoline);
11856
11857 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11858 {
11859 unsigned long inst;
b38cadfb
NC		 11860
11861 offset -= (input_section->output_section->vma
11862 + input_section->output_offset
11863 + rel->r_offset + 8);
0855e32b
NS		 11864
11865 inst = offset >> 2;
11866 inst &= 0x00ffffff;
11867 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11868 }
11869 else
11870 {
11871 /* Thumb blx encodes the offset in a complicated
11872 fashion. */
11873 unsigned upper_insn, lower_insn;
11874 unsigned neg;
11875
b38cadfb
NC		 11876 offset -= (input_section->output_section->vma
11877 + input_section->output_offset
0855e32b 11878 + rel->r_offset + 4);
b38cadfb 11879
12352d3f
PB		 11880 if (stub_type != arm_stub_none
11881 && arm_stub_is_thumb (stub_type))
11882 {
11883 lower_insn = 0xd000;
11884 }
11885 else
11886 {
11887 lower_insn = 0xc000;
6a631e86 11888 /* Round up the offset to a word boundary. */
12352d3f
PB		 11889 offset = (offset + 2) & ~2;
11890 }
11891
0855e32b
NS		 11892 neg = offset < 0;
11893 upper_insn = (0xf000
11894 | ((offset >> 12) & 0x3ff)
11895 | (neg << 10));
12352d3f 11896 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11897 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11898 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11899 bfd_put_16 (input_bfd, upper_insn, hit_data);
11900 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11901 return bfd_reloc_ok;
11902 }
11903 }
11904 /* These relocations needs special care, as besides the fact
11905 they point somewhere in .gotplt, the addend must be
11906 adjusted accordingly depending on the type of instruction
6a631e86 11907 we refer to. */
0855e32b
NS		 11908 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11909 {
11910 unsigned long data, insn;
11911 unsigned thumb;
b38cadfb 11912
0855e32b
NS		 11913 data = bfd_get_32 (input_bfd, hit_data);
11914 thumb = data & 1;
11915 data &= ~1u;
b38cadfb 11916
0855e32b
NS		 11917 if (thumb)
11918 {
11919 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11920 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11921 insn = (insn << 16)
11922 | bfd_get_16 (input_bfd,
11923 contents + rel->r_offset - data + 2);
11924 if ((insn & 0xf800c000) == 0xf000c000)
11925 /* bl/blx */
11926 value = -6;
11927 else if ((insn & 0xffffff00) == 0x4400)
11928 /* add */
11929 value = -5;
11930 else
11931 {
4eca0228 11932 _bfd_error_handler
695344c0 11933 /* xgettext:c-format */
2dcf00ce 11934 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 11935 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 11936 "referenced by TLS_GOTDESC"),
11937 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 11938 "Thumb", insn);
0855e32b
NS		 11939 return bfd_reloc_notsupported;
11940 }
11941 }
11942 else
11943 {
11944 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11945
11946 switch (insn >> 24)
11947 {
11948 case 0xeb: /* bl */
11949 case 0xfa: /* blx */
11950 value = -4;
11951 break;
11952
11953 case 0xe0: /* add */
11954 value = -8;
11955 break;
b38cadfb 11956
0855e32b 11957 default:
4eca0228 11958 _bfd_error_handler
695344c0 11959 /* xgettext:c-format */
2dcf00ce 11960 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 11961 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 11962 "referenced by TLS_GOTDESC"),
11963 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 11964 "ARM", insn);
0855e32b
NS		 11965 return bfd_reloc_notsupported;
11966 }
11967 }
b38cadfb 11968
0855e32b
NS		 11969 value += ((globals->root.sgotplt->output_section->vma
11970 + globals->root.sgotplt->output_offset + off)
11971 - (input_section->output_section->vma
11972 + input_section->output_offset
11973 + rel->r_offset)
11974 + globals->sgotplt_jump_table_size);
11975 }
11976 else
11977 value = ((globals->root.sgot->output_section->vma
11978 + globals->root.sgot->output_offset + off)
11979 - (input_section->output_section->vma
11980 + input_section->output_offset + rel->r_offset));
ba93b8ac 11981
5c5a4843
CL		 11982 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
11983 r_type == R_ARM_TLS_IE32_FDPIC))
e8b09b87
CL		 11984 {
11985 /* For FDPIC relocations, resolve to the offset of the GOT
11986 entry from the start of GOT. */
11987 bfd_put_32(output_bfd,
11988 globals->root.sgot->output_offset + off,
11989 contents + rel->r_offset);
11990
11991 return bfd_reloc_ok;
11992 }
11993 else
11994 {
11995 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11996 contents, rel->r_offset, value,
11997 rel->r_addend);
11998 }
ba93b8ac
DJ		 11999 }
12000
12001 case R_ARM_TLS_LE32:
3cbc1e5e 12002 if (bfd_link_dll (info))
ba93b8ac 12003 {
4eca0228 12004 _bfd_error_handler
695344c0 12005 /* xgettext:c-format */
2dcf00ce
AM		 12006 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12007 "in shared object"),
12008 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 12009 return bfd_reloc_notsupported;
ba93b8ac
DJ		 12010 }
12011 else
12012 value = tpoff (info, value);
906e58ca 12013
ba93b8ac 12014 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 12015 contents, rel->r_offset, value,
12016 rel->r_addend);
ba93b8ac 12017
319850b4
JB		 12018 case R_ARM_V4BX:
12019 if (globals->fix_v4bx)
845b51d6
PB		 12020 {
12021 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 12022
845b51d6
PB		 12023 /* Ensure that we have a BX instruction. */
12024 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 12025
845b51d6
PB		 12026 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12027 {
12028 /* Branch to veneer. */
12029 bfd_vma glue_addr;
12030 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12031 glue_addr -= input_section->output_section->vma
12032 + input_section->output_offset
12033 + rel->r_offset + 8;
12034 insn = (insn & 0xf0000000) | 0x0a000000
12035 | ((glue_addr >> 2) & 0x00ffffff);
12036 }
12037 else
12038 {
12039 /* Preserve Rm (lowest four bits) and the condition code
12040 (highest four bits). Other bits encode MOV PC,Rm. */
12041 insn = (insn & 0xf000000f) | 0x01a0f000;
12042 }
319850b4 12043
845b51d6
PB		 12044 bfd_put_32 (input_bfd, insn, hit_data);
12045 }
319850b4
JB		 12046 return bfd_reloc_ok;
12047
b6895b4f
PB		 12048 case R_ARM_MOVW_ABS_NC:
12049 case R_ARM_MOVT_ABS:
12050 case R_ARM_MOVW_PREL_NC:
12051 case R_ARM_MOVT_PREL:
92f5d02b
MS		 12052 /* Until we properly support segment-base-relative addressing then
12053 we assume the segment base to be zero, as for the group relocations.
12054 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12055 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12056 case R_ARM_MOVW_BREL_NC:
12057 case R_ARM_MOVW_BREL:
12058 case R_ARM_MOVT_BREL:
b6895b4f
PB		 12059 {
12060 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12061
12062 if (globals->use_rel)
12063 {
12064 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 12065 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12066 }
92f5d02b 12067
b6895b4f 12068 value += signed_addend;
b6895b4f
PB		 12069
12070 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12071 value -= (input_section->output_section->vma
12072 + input_section->output_offset + rel->r_offset);
12073
92f5d02b 12074 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 12075 return bfd_reloc_overflow;
92f5d02b 12076
35fc36a8 12077 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12078 value |= 1;
12079
12080 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 12081 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 12082 value >>= 16;
12083
12084 insn &= 0xfff0f000;
12085 insn |= value & 0xfff;
12086 insn |= (value & 0xf000) << 4;
12087 bfd_put_32 (input_bfd, insn, hit_data);
12088 }
12089 return bfd_reloc_ok;
12090
12091 case R_ARM_THM_MOVW_ABS_NC:
12092 case R_ARM_THM_MOVT_ABS:
12093 case R_ARM_THM_MOVW_PREL_NC:
12094 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 12095 /* Until we properly support segment-base-relative addressing then
12096 we assume the segment base to be zero, as for the above relocations.
12097 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12098 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12099 as R_ARM_THM_MOVT_ABS. */
12100 case R_ARM_THM_MOVW_BREL_NC:
12101 case R_ARM_THM_MOVW_BREL:
12102 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 12103 {
12104 bfd_vma insn;
906e58ca 12105
b6895b4f
PB		 12106 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12107 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12108
12109 if (globals->use_rel)
12110 {
12111 addend = ((insn >> 4) & 0xf000)
12112 | ((insn >> 15) & 0x0800)
12113 | ((insn >> 4) & 0x0700)
07d6d2b8 12114 | (insn & 0x00ff);
39623e12 12115 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12116 }
92f5d02b 12117
b6895b4f 12118 value += signed_addend;
b6895b4f
PB		 12119
12120 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12121 value -= (input_section->output_section->vma
12122 + input_section->output_offset + rel->r_offset);
12123
92f5d02b 12124 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 12125 return bfd_reloc_overflow;
92f5d02b 12126
35fc36a8 12127 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12128 value |= 1;
12129
12130 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 12131 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 12132 value >>= 16;
12133
12134 insn &= 0xfbf08f00;
12135 insn |= (value & 0xf000) << 4;
12136 insn |= (value & 0x0800) << 15;
12137 insn |= (value & 0x0700) << 4;
12138 insn |= (value & 0x00ff);
12139
12140 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12141 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12142 }
12143 return bfd_reloc_ok;
12144
4962c51a
MS		 12145 case R_ARM_ALU_PC_G0_NC:
12146 case R_ARM_ALU_PC_G1_NC:
12147 case R_ARM_ALU_PC_G0:
12148 case R_ARM_ALU_PC_G1:
12149 case R_ARM_ALU_PC_G2:
12150 case R_ARM_ALU_SB_G0_NC:
12151 case R_ARM_ALU_SB_G1_NC:
12152 case R_ARM_ALU_SB_G0:
12153 case R_ARM_ALU_SB_G1:
12154 case R_ARM_ALU_SB_G2:
12155 {
12156 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12157 bfd_vma pc = input_section->output_section->vma
4962c51a 12158 + input_section->output_offset + rel->r_offset;
31a91d61 12159 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12160 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 12161 bfd_vma residual;
12162 bfd_vma g_n;
4962c51a 12163 bfd_signed_vma signed_value;
99059e56
RM		 12164 int group = 0;
12165
12166 /* Determine which group of bits to select. */
12167 switch (r_type)
12168 {
12169 case R_ARM_ALU_PC_G0_NC:
12170 case R_ARM_ALU_PC_G0:
12171 case R_ARM_ALU_SB_G0_NC:
12172 case R_ARM_ALU_SB_G0:
12173 group = 0;
12174 break;
12175
12176 case R_ARM_ALU_PC_G1_NC:
12177 case R_ARM_ALU_PC_G1:
12178 case R_ARM_ALU_SB_G1_NC:
12179 case R_ARM_ALU_SB_G1:
12180 group = 1;
12181 break;
12182
12183 case R_ARM_ALU_PC_G2:
12184 case R_ARM_ALU_SB_G2:
12185 group = 2;
12186 break;
12187
12188 default:
12189 abort ();
12190 }
12191
12192 /* If REL, extract the addend from the insn. If RELA, it will
12193 have already been fetched for us. */
4962c51a 12194 if (globals->use_rel)
99059e56
RM		 12195 {
12196 int negative;
12197 bfd_vma constant = insn & 0xff;
12198 bfd_vma rotation = (insn & 0xf00) >> 8;
12199
12200 if (rotation == 0)
12201 signed_addend = constant;
12202 else
12203 {
12204 /* Compensate for the fact that in the instruction, the
12205 rotation is stored in multiples of 2 bits. */
12206 rotation *= 2;
12207
12208 /* Rotate "constant" right by "rotation" bits. */
12209 signed_addend = (constant >> rotation) |
12210 (constant << (8 * sizeof (bfd_vma) - rotation));
12211 }
12212
12213 /* Determine if the instruction is an ADD or a SUB.
12214 (For REL, this determines the sign of the addend.) */
12215 negative = identify_add_or_sub (insn);
12216 if (negative == 0)
12217 {
4eca0228 12218 _bfd_error_handler
695344c0 12219 /* xgettext:c-format */
90b6238f 12220 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 12221 "are allowed for ALU group relocations"),
12222 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 12223 return bfd_reloc_overflow;
12224 }
12225
12226 signed_addend *= negative;
12227 }
4962c51a
MS		 12228
12229 /* Compute the value (X) to go in the place. */
99059e56
RM		 12230 if (r_type == R_ARM_ALU_PC_G0_NC
12231 || r_type == R_ARM_ALU_PC_G1_NC
12232 || r_type == R_ARM_ALU_PC_G0
12233 || r_type == R_ARM_ALU_PC_G1
12234 || r_type == R_ARM_ALU_PC_G2)
12235 /* PC relative. */
12236 signed_value = value - pc + signed_addend;
12237 else
12238 /* Section base relative. */
12239 signed_value = value - sb + signed_addend;
12240
12241 /* If the target symbol is a Thumb function, then set the
12242 Thumb bit in the address. */
35fc36a8 12243 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 12244 signed_value |= 1;
12245
99059e56
RM		 12246 /* Calculate the value of the relevant G_n, in encoded
12247 constant-with-rotation format. */
b6518b38
NC		 12248 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12249 group, &residual);
99059e56
RM		 12250
12251 /* Check for overflow if required. */
12252 if ((r_type == R_ARM_ALU_PC_G0
12253 || r_type == R_ARM_ALU_PC_G1
12254 || r_type == R_ARM_ALU_PC_G2
12255 || r_type == R_ARM_ALU_SB_G0
12256 || r_type == R_ARM_ALU_SB_G1
12257 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12258 {
4eca0228 12259 _bfd_error_handler
695344c0 12260 /* xgettext:c-format */
90b6238f 12261 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12262 "splitting %#" PRIx64 " for group relocation %s"),
12263 input_bfd, input_section, (uint64_t) rel->r_offset,
12264 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12265 howto->name);
99059e56
RM		 12266 return bfd_reloc_overflow;
12267 }
12268
12269 /* Mask out the value and the ADD/SUB part of the opcode; take care
12270 not to destroy the S bit. */
12271 insn &= 0xff1ff000;
12272
12273 /* Set the opcode according to whether the value to go in the
12274 place is negative. */
12275 if (signed_value < 0)
12276 insn |= 1 << 22;
12277 else
12278 insn |= 1 << 23;
12279
12280 /* Encode the offset. */
12281 insn |= g_n;
4962c51a
MS		 12282
12283 bfd_put_32 (input_bfd, insn, hit_data);
12284 }
12285 return bfd_reloc_ok;
12286
12287 case R_ARM_LDR_PC_G0:
12288 case R_ARM_LDR_PC_G1:
12289 case R_ARM_LDR_PC_G2:
12290 case R_ARM_LDR_SB_G0:
12291 case R_ARM_LDR_SB_G1:
12292 case R_ARM_LDR_SB_G2:
12293 {
12294 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12295 bfd_vma pc = input_section->output_section->vma
4962c51a 12296 + input_section->output_offset + rel->r_offset;
31a91d61 12297 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12298 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12299 bfd_vma residual;
4962c51a 12300 bfd_signed_vma signed_value;
99059e56
RM		 12301 int group = 0;
12302
12303 /* Determine which groups of bits to calculate. */
12304 switch (r_type)
12305 {
12306 case R_ARM_LDR_PC_G0:
12307 case R_ARM_LDR_SB_G0:
12308 group = 0;
12309 break;
12310
12311 case R_ARM_LDR_PC_G1:
12312 case R_ARM_LDR_SB_G1:
12313 group = 1;
12314 break;
12315
12316 case R_ARM_LDR_PC_G2:
12317 case R_ARM_LDR_SB_G2:
12318 group = 2;
12319 break;
12320
12321 default:
12322 abort ();
12323 }
12324
12325 /* If REL, extract the addend from the insn. If RELA, it will
12326 have already been fetched for us. */
4962c51a 12327 if (globals->use_rel)
99059e56
RM		 12328 {
12329 int negative = (insn & (1 << 23)) ? 1 : -1;
12330 signed_addend = negative * (insn & 0xfff);
12331 }
4962c51a
MS		 12332
12333 /* Compute the value (X) to go in the place. */
99059e56
RM		 12334 if (r_type == R_ARM_LDR_PC_G0
12335 || r_type == R_ARM_LDR_PC_G1
12336 || r_type == R_ARM_LDR_PC_G2)
12337 /* PC relative. */
12338 signed_value = value - pc + signed_addend;
12339 else
12340 /* Section base relative. */
12341 signed_value = value - sb + signed_addend;
12342
12343 /* Calculate the value of the relevant G_{n-1} to obtain
12344 the residual at that stage. */
b6518b38
NC		 12345 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12346 group - 1, &residual);
99059e56
RM		 12347
12348 /* Check for overflow. */
12349 if (residual >= 0x1000)
12350 {
4eca0228 12351 _bfd_error_handler
695344c0 12352 /* xgettext:c-format */
90b6238f 12353 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12354 "splitting %#" PRIx64 " for group relocation %s"),
12355 input_bfd, input_section, (uint64_t) rel->r_offset,
12356 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12357 howto->name);
99059e56
RM		 12358 return bfd_reloc_overflow;
12359 }
12360
12361 /* Mask out the value and U bit. */
12362 insn &= 0xff7ff000;
12363
12364 /* Set the U bit if the value to go in the place is non-negative. */
12365 if (signed_value >= 0)
12366 insn |= 1 << 23;
12367
12368 /* Encode the offset. */
12369 insn |= residual;
4962c51a
MS		 12370
12371 bfd_put_32 (input_bfd, insn, hit_data);
12372 }
12373 return bfd_reloc_ok;
12374
12375 case R_ARM_LDRS_PC_G0:
12376 case R_ARM_LDRS_PC_G1:
12377 case R_ARM_LDRS_PC_G2:
12378 case R_ARM_LDRS_SB_G0:
12379 case R_ARM_LDRS_SB_G1:
12380 case R_ARM_LDRS_SB_G2:
12381 {
12382 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12383 bfd_vma pc = input_section->output_section->vma
4962c51a 12384 + input_section->output_offset + rel->r_offset;
31a91d61 12385 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12386 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12387 bfd_vma residual;
4962c51a 12388 bfd_signed_vma signed_value;
99059e56
RM		 12389 int group = 0;
12390
12391 /* Determine which groups of bits to calculate. */
12392 switch (r_type)
12393 {
12394 case R_ARM_LDRS_PC_G0:
12395 case R_ARM_LDRS_SB_G0:
12396 group = 0;
12397 break;
12398
12399 case R_ARM_LDRS_PC_G1:
12400 case R_ARM_LDRS_SB_G1:
12401 group = 1;
12402 break;
12403
12404 case R_ARM_LDRS_PC_G2:
12405 case R_ARM_LDRS_SB_G2:
12406 group = 2;
12407 break;
12408
12409 default:
12410 abort ();
12411 }
12412
12413 /* If REL, extract the addend from the insn. If RELA, it will
12414 have already been fetched for us. */
4962c51a 12415 if (globals->use_rel)
99059e56
RM		 12416 {
12417 int negative = (insn & (1 << 23)) ? 1 : -1;
12418 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12419 }
4962c51a
MS		 12420
12421 /* Compute the value (X) to go in the place. */
99059e56
RM		 12422 if (r_type == R_ARM_LDRS_PC_G0
12423 || r_type == R_ARM_LDRS_PC_G1
12424 || r_type == R_ARM_LDRS_PC_G2)
12425 /* PC relative. */
12426 signed_value = value - pc + signed_addend;
12427 else
12428 /* Section base relative. */
12429 signed_value = value - sb + signed_addend;
12430
12431 /* Calculate the value of the relevant G_{n-1} to obtain
12432 the residual at that stage. */
b6518b38
NC		 12433 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12434 group - 1, &residual);
99059e56
RM		 12435
12436 /* Check for overflow. */
12437 if (residual >= 0x100)
12438 {
4eca0228 12439 _bfd_error_handler
695344c0 12440 /* xgettext:c-format */
90b6238f 12441 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12442 "splitting %#" PRIx64 " for group relocation %s"),
12443 input_bfd, input_section, (uint64_t) rel->r_offset,
12444 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12445 howto->name);
99059e56
RM		 12446 return bfd_reloc_overflow;
12447 }
12448
12449 /* Mask out the value and U bit. */
12450 insn &= 0xff7ff0f0;
12451
12452 /* Set the U bit if the value to go in the place is non-negative. */
12453 if (signed_value >= 0)
12454 insn |= 1 << 23;
12455
12456 /* Encode the offset. */
12457 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12458
12459 bfd_put_32 (input_bfd, insn, hit_data);
12460 }
12461 return bfd_reloc_ok;
12462
12463 case R_ARM_LDC_PC_G0:
12464 case R_ARM_LDC_PC_G1:
12465 case R_ARM_LDC_PC_G2:
12466 case R_ARM_LDC_SB_G0:
12467 case R_ARM_LDC_SB_G1:
12468 case R_ARM_LDC_SB_G2:
12469 {
12470 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12471 bfd_vma pc = input_section->output_section->vma
4962c51a 12472 + input_section->output_offset + rel->r_offset;
31a91d61 12473 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12474 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12475 bfd_vma residual;
4962c51a 12476 bfd_signed_vma signed_value;
99059e56
RM		 12477 int group = 0;
12478
12479 /* Determine which groups of bits to calculate. */
12480 switch (r_type)
12481 {
12482 case R_ARM_LDC_PC_G0:
12483 case R_ARM_LDC_SB_G0:
12484 group = 0;
12485 break;
12486
12487 case R_ARM_LDC_PC_G1:
12488 case R_ARM_LDC_SB_G1:
12489 group = 1;
12490 break;
12491
12492 case R_ARM_LDC_PC_G2:
12493 case R_ARM_LDC_SB_G2:
12494 group = 2;
12495 break;
12496
12497 default:
12498 abort ();
12499 }
12500
12501 /* If REL, extract the addend from the insn. If RELA, it will
12502 have already been fetched for us. */
4962c51a 12503 if (globals->use_rel)
99059e56
RM		 12504 {
12505 int negative = (insn & (1 << 23)) ? 1 : -1;
12506 signed_addend = negative * ((insn & 0xff) << 2);
12507 }
4962c51a
MS		 12508
12509 /* Compute the value (X) to go in the place. */
99059e56
RM		 12510 if (r_type == R_ARM_LDC_PC_G0
12511 || r_type == R_ARM_LDC_PC_G1
12512 || r_type == R_ARM_LDC_PC_G2)
12513 /* PC relative. */
12514 signed_value = value - pc + signed_addend;
12515 else
12516 /* Section base relative. */
12517 signed_value = value - sb + signed_addend;
12518
12519 /* Calculate the value of the relevant G_{n-1} to obtain
12520 the residual at that stage. */
b6518b38
NC		 12521 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12522 group - 1, &residual);
99059e56
RM		 12523
12524 /* Check for overflow. (The absolute value to go in the place must be
12525 divisible by four and, after having been divided by four, must
12526 fit in eight bits.) */
12527 if ((residual & 0x3) != 0 || residual >= 0x400)
12528 {
4eca0228 12529 _bfd_error_handler
695344c0 12530 /* xgettext:c-format */
90b6238f 12531 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12532 "splitting %#" PRIx64 " for group relocation %s"),
12533 input_bfd, input_section, (uint64_t) rel->r_offset,
12534 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12535 howto->name);
99059e56
RM		 12536 return bfd_reloc_overflow;
12537 }
12538
12539 /* Mask out the value and U bit. */
12540 insn &= 0xff7fff00;
12541
12542 /* Set the U bit if the value to go in the place is non-negative. */
12543 if (signed_value >= 0)
12544 insn |= 1 << 23;
12545
12546 /* Encode the offset. */
12547 insn |= residual >> 2;
4962c51a
MS		 12548
12549 bfd_put_32 (input_bfd, insn, hit_data);
12550 }
12551 return bfd_reloc_ok;
12552
72d98d16
MG		 12553 case R_ARM_THM_ALU_ABS_G0_NC:
12554 case R_ARM_THM_ALU_ABS_G1_NC:
12555 case R_ARM_THM_ALU_ABS_G2_NC:
12556 case R_ARM_THM_ALU_ABS_G3_NC:
12557 {
12558 const int shift_array[4] = {0, 8, 16, 24};
12559 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12560 bfd_vma addr = value;
12561 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12562
12563 /* Compute address. */
12564 if (globals->use_rel)
12565 signed_addend = insn & 0xff;
12566 addr += signed_addend;
12567 if (branch_type == ST_BRANCH_TO_THUMB)
12568 addr |= 1;
12569 /* Clean imm8 insn. */
12570 insn &= 0xff00;
12571 /* And update with correct part of address. */
12572 insn |= (addr >> shift) & 0xff;
12573 /* Update insn. */
12574 bfd_put_16 (input_bfd, insn, hit_data);
12575 }
12576
12577 *unresolved_reloc_p = FALSE;
12578 return bfd_reloc_ok;
12579
e8b09b87
CL		 12580 case R_ARM_GOTOFFFUNCDESC:
12581 {
12582 if (h == NULL)
12583 {
12584 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12585 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12586 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12587 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12588 bfd_vma seg = -1;
12589
12590 if (bfd_link_pic(info) && dynindx == 0)
12591 abort();
12592
12593 /* Resolve relocation. */
12594 bfd_put_32(output_bfd, (offset + sgot->output_offset)
12595 , contents + rel->r_offset);
12596 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12597 not done yet. */
12598 arm_elf_fill_funcdesc(output_bfd, info,
12599 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12600 dynindx, offset, addr, dynreloc_value, seg);
12601 }
12602 else
12603 {
12604 int dynindx;
12605 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12606 bfd_vma addr;
12607 bfd_vma seg = -1;
12608
12609 /* For static binaries, sym_sec can be null. */
12610 if (sym_sec)
12611 {
12612 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12613 addr = dynreloc_value - sym_sec->output_section->vma;
12614 }
12615 else
12616 {
12617 dynindx = 0;
12618 addr = 0;
12619 }
12620
12621 if (bfd_link_pic(info) && dynindx == 0)
12622 abort();
12623
12624 /* This case cannot occur since funcdesc is allocated by
12625 the dynamic loader so we cannot resolve the relocation. */
12626 if (h->dynindx != -1)
12627 abort();
12628
12629 /* Resolve relocation. */
12630 bfd_put_32(output_bfd, (offset + sgot->output_offset),
12631 contents + rel->r_offset);
12632 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12633 arm_elf_fill_funcdesc(output_bfd, info,
12634 &eh->fdpic_cnts.funcdesc_offset,
12635 dynindx, offset, addr, dynreloc_value, seg);
12636 }
12637 }
12638 *unresolved_reloc_p = FALSE;
12639 return bfd_reloc_ok;
12640
12641 case R_ARM_GOTFUNCDESC:
12642 {
12643 if (h != NULL)
12644 {
12645 Elf_Internal_Rela outrel;
12646
12647 /* Resolve relocation. */
12648 bfd_put_32(output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12649 + sgot->output_offset),
12650 contents + rel->r_offset);
12651 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12652 if(h->dynindx == -1)
12653 {
12654 int dynindx;
12655 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12656 bfd_vma addr;
12657 bfd_vma seg = -1;
12658
12659 /* For static binaries sym_sec can be null. */
12660 if (sym_sec)
12661 {
12662 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12663 addr = dynreloc_value - sym_sec->output_section->vma;
12664 }
12665 else
12666 {
12667 dynindx = 0;
12668 addr = 0;
12669 }
12670
12671 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12672 arm_elf_fill_funcdesc(output_bfd, info,
12673 &eh->fdpic_cnts.funcdesc_offset,
12674 dynindx, offset, addr, dynreloc_value, seg);
12675 }
12676
12677 /* Add a dynamic relocation on GOT entry if not already done. */
12678 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12679 {
12680 if (h->dynindx == -1)
12681 {
12682 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12683 if (h->root.type == bfd_link_hash_undefweak)
12684 bfd_put_32(output_bfd, 0, sgot->contents
12685 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12686 else
12687 bfd_put_32(output_bfd, sgot->output_section->vma
12688 + sgot->output_offset
12689 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12690 sgot->contents
12691 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12692 }
12693 else
12694 {
12695 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12696 }
12697 outrel.r_offset = sgot->output_section->vma
12698 + sgot->output_offset
12699 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12700 outrel.r_addend = 0;
12701 if (h->dynindx == -1 && !bfd_link_pic(info))
12702 if (h->root.type == bfd_link_hash_undefweak)
12703 arm_elf_add_rofixup(output_bfd, globals->srofixup, -1);
12704 else
12705 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12706 else
12707 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12708 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12709 }
12710 }
12711 else
12712 {
12713 /* Such relocation on static function should not have been
12714 emitted by the compiler. */
12715 abort();
12716 }
12717 }
12718 *unresolved_reloc_p = FALSE;
12719 return bfd_reloc_ok;
12720
12721 case R_ARM_FUNCDESC:
12722 {
12723 if (h == NULL)
12724 {
12725 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12726 Elf_Internal_Rela outrel;
12727 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12728 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12729 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12730 bfd_vma seg = -1;
12731
12732 if (bfd_link_pic(info) && dynindx == 0)
12733 abort();
12734
12735 /* Replace static FUNCDESC relocation with a
12736 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12737 executable. */
12738 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12739 outrel.r_offset = input_section->output_section->vma
12740 + input_section->output_offset + rel->r_offset;
12741 outrel.r_addend = 0;
12742 if (bfd_link_pic(info))
12743 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12744 else
12745 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12746
12747 bfd_put_32 (input_bfd, sgot->output_section->vma
12748 + sgot->output_offset + offset, hit_data);
12749
12750 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12751 arm_elf_fill_funcdesc(output_bfd, info,
12752 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12753 dynindx, offset, addr, dynreloc_value, seg);
12754 }
12755 else
12756 {
12757 if (h->dynindx == -1)
12758 {
12759 int dynindx;
12760 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12761 bfd_vma addr;
12762 bfd_vma seg = -1;
12763 Elf_Internal_Rela outrel;
12764
12765 /* For static binaries sym_sec can be null. */
12766 if (sym_sec)
12767 {
12768 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12769 addr = dynreloc_value - sym_sec->output_section->vma;
12770 }
12771 else
12772 {
12773 dynindx = 0;
12774 addr = 0;
12775 }
12776
12777 if (bfd_link_pic(info) && dynindx == 0)
12778 abort();
12779
12780 /* Replace static FUNCDESC relocation with a
12781 R_ARM_RELATIVE dynamic relocation. */
12782 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12783 outrel.r_offset = input_section->output_section->vma
12784 + input_section->output_offset + rel->r_offset;
12785 outrel.r_addend = 0;
12786 if (bfd_link_pic(info))
12787 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12788 else
12789 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12790
12791 bfd_put_32 (input_bfd, sgot->output_section->vma
12792 + sgot->output_offset + offset, hit_data);
12793
12794 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12795 arm_elf_fill_funcdesc(output_bfd, info,
12796 &eh->fdpic_cnts.funcdesc_offset,
12797 dynindx, offset, addr, dynreloc_value, seg);
12798 }
12799 else
12800 {
12801 Elf_Internal_Rela outrel;
12802
12803 /* Add a dynamic relocation. */
12804 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12805 outrel.r_offset = input_section->output_section->vma
12806 + input_section->output_offset + rel->r_offset;
12807 outrel.r_addend = 0;
12808 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12809 }
12810 }
12811 }
12812 *unresolved_reloc_p = FALSE;
12813 return bfd_reloc_ok;
12814
252b5132
RH		 12815 default:
12816 return bfd_reloc_notsupported;
12817 }
12818}
12819
98c1d4aa
NC		 12820/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12821static void
07d6d2b8
AM		 12822arm_add_to_rel (bfd * abfd,
12823 bfd_byte * address,
57e8b36a 12824 reloc_howto_type * howto,
07d6d2b8 12825 bfd_signed_vma increment)
98c1d4aa 12826{
98c1d4aa
NC		 12827 bfd_signed_vma addend;
12828
bd97cb95
DJ		 12829 if (howto->type == R_ARM_THM_CALL
12830 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 12831 {
9a5aca8c
AM		 12832 int upper_insn, lower_insn;
12833 int upper, lower;
98c1d4aa 12834
9a5aca8c
AM		 12835 upper_insn = bfd_get_16 (abfd, address);
12836 lower_insn = bfd_get_16 (abfd, address + 2);
12837 upper = upper_insn & 0x7ff;
12838 lower = lower_insn & 0x7ff;
12839
12840 addend = (upper << 12) | (lower << 1);
ddda4409 12841 addend += increment;
9a5aca8c 12842 addend >>= 1;
98c1d4aa 12843
9a5aca8c
AM		 12844 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
12845 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
12846
dc810e39
AM		 12847 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
12848 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 12849 }
12850 else
12851 {
07d6d2b8 12852 bfd_vma contents;
9a5aca8c
AM		 12853
12854 contents = bfd_get_32 (abfd, address);
12855
12856 /* Get the (signed) value from the instruction. */
12857 addend = contents & howto->src_mask;
12858 if (addend & ((howto->src_mask + 1) >> 1))
12859 {
12860 bfd_signed_vma mask;
12861
12862 mask = -1;
12863 mask &= ~ howto->src_mask;
12864 addend |= mask;
12865 }
12866
12867 /* Add in the increment, (which is a byte value). */
12868 switch (howto->type)
12869 {
12870 default:
12871 addend += increment;
12872 break;
12873
12874 case R_ARM_PC24:
c6596c5e 12875 case R_ARM_PLT32:
5b5bb741
PB		 12876 case R_ARM_CALL:
12877 case R_ARM_JUMP24:
9a5aca8c 12878 addend <<= howto->size;
dc810e39 12879 addend += increment;
9a5aca8c
AM		 12880
12881 /* Should we check for overflow here ? */
12882
12883 /* Drop any undesired bits. */
12884 addend >>= howto->rightshift;
12885 break;
12886 }
12887
12888 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
12889
12890 bfd_put_32 (abfd, contents, address);
ddda4409 12891 }
98c1d4aa 12892}
252b5132 12893
ba93b8ac
DJ		 12894#define IS_ARM_TLS_RELOC(R_TYPE) \
12895 ((R_TYPE) == R_ARM_TLS_GD32 \
5c5a4843 12896 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
ba93b8ac
DJ		 12897 || (R_TYPE) == R_ARM_TLS_LDO32 \
12898 || (R_TYPE) == R_ARM_TLS_LDM32 \
5c5a4843 12899 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
ba93b8ac
DJ		 12900 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12901 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12902 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12903 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b 12904 || (R_TYPE) == R_ARM_TLS_IE32 \
5c5a4843 12905 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
0855e32b
NS		 12906 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12907
12908/* Specific set of relocations for the gnu tls dialect. */
12909#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12910 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12911 || (R_TYPE) == R_ARM_TLS_CALL \
12912 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12913 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12914 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 12915
252b5132 12916/* Relocate an ARM ELF section. */
906e58ca 12917
b34976b6 12918static bfd_boolean
07d6d2b8 12919elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 12920 struct bfd_link_info * info,
07d6d2b8
AM		 12921 bfd * input_bfd,
12922 asection * input_section,
12923 bfd_byte * contents,
12924 Elf_Internal_Rela * relocs,
12925 Elf_Internal_Sym * local_syms,
12926 asection ** local_sections)
252b5132 12927{
b34976b6
AM		 12928 Elf_Internal_Shdr *symtab_hdr;
12929 struct elf_link_hash_entry **sym_hashes;
12930 Elf_Internal_Rela *rel;
12931 Elf_Internal_Rela *relend;
12932 const char *name;
b32d3aa2 12933 struct elf32_arm_link_hash_table * globals;
252b5132 12934
4e7fd91e 12935 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 12936 if (globals == NULL)
12937 return FALSE;
b491616a 12938
0ffa91dd 12939 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 12940 sym_hashes = elf_sym_hashes (input_bfd);
12941
12942 rel = relocs;
12943 relend = relocs + input_section->reloc_count;
12944 for (; rel < relend; rel++)
12945 {
07d6d2b8
AM		 12946 int r_type;
12947 reloc_howto_type * howto;
12948 unsigned long r_symndx;
12949 Elf_Internal_Sym * sym;
12950 asection * sec;
252b5132 12951 struct elf_link_hash_entry * h;
07d6d2b8
AM		 12952 bfd_vma relocation;
12953 bfd_reloc_status_type r;
12954 arelent bfd_reloc;
12955 char sym_type;
12956 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 12957 char *error_message = NULL;
f21f3fe0 12958
252b5132 12959 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 12960 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 12961 r_type = arm_real_reloc_type (globals, r_type);
252b5132 12962
ba96a88f 12963 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 12964 || r_type == R_ARM_GNU_VTINHERIT)
12965 continue;
252b5132 12966
47aeb64c
NC		 12967 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
12968
12969 if (howto == NULL)
12970 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 12971
252b5132
RH		 12972 h = NULL;
12973 sym = NULL;
12974 sec = NULL;
9b485d32 12975
252b5132
RH		 12976 if (r_symndx < symtab_hdr->sh_info)
12977 {
12978 sym = local_syms + r_symndx;
ba93b8ac 12979 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 12980 sec = local_sections[r_symndx];
ffcb4889
NS		 12981
12982 /* An object file might have a reference to a local
12983 undefined symbol. This is a daft object file, but we
12984 should at least do something about it. V4BX & NONE
12985 relocations do not use the symbol and are explicitly
77b4f08f
TS		 12986 allowed to use the undefined symbol, so allow those.
12987 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 12988 if (r_type != R_ARM_V4BX
12989 && r_type != R_ARM_NONE
77b4f08f 12990 && r_symndx != STN_UNDEF
ffcb4889
NS		 12991 && bfd_is_und_section (sec)
12992 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 12993 (*info->callbacks->undefined_symbol)
12994 (info, bfd_elf_string_from_elf_section
12995 (input_bfd, symtab_hdr->sh_link, sym->st_name),
12996 input_bfd, input_section,
12997 rel->r_offset, TRUE);
b38cadfb 12998
4e7fd91e 12999 if (globals->use_rel)
f8df10f4 13000 {
4e7fd91e
PB		 13001 relocation = (sec->output_section->vma
13002 + sec->output_offset
13003 + sym->st_value);
0e1862bb 13004 if (!bfd_link_relocatable (info)
ab96bf03
AM		 13005 && (sec->flags & SEC_MERGE)
13006 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 13007 {
4e7fd91e
PB		 13008 asection *msec;
13009 bfd_vma addend, value;
13010
39623e12 13011 switch (r_type)
4e7fd91e 13012 {
39623e12
PB		 13013 case R_ARM_MOVW_ABS_NC:
13014 case R_ARM_MOVT_ABS:
13015 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13016 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13017 addend = (addend ^ 0x8000) - 0x8000;
13018 break;
f8df10f4 13019
39623e12
PB		 13020 case R_ARM_THM_MOVW_ABS_NC:
13021 case R_ARM_THM_MOVT_ABS:
13022 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13023 << 16;
13024 value |= bfd_get_16 (input_bfd,
13025 contents + rel->r_offset + 2);
13026 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13027 | ((value & 0x04000000) >> 15);
13028 addend = (addend ^ 0x8000) - 0x8000;
13029 break;
f8df10f4 13030
39623e12
PB		 13031 default:
13032 if (howto->rightshift
13033 || (howto->src_mask & (howto->src_mask + 1)))
13034 {
4eca0228 13035 _bfd_error_handler
695344c0 13036 /* xgettext:c-format */
2dcf00ce
AM		 13037 (_("%pB(%pA+%#" PRIx64 "): "
13038 "%s relocation against SEC_MERGE section"),
39623e12 13039 input_bfd, input_section,
2dcf00ce 13040 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 13041 return FALSE;
13042 }
13043
13044 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13045
13046 /* Get the (signed) value from the instruction. */
13047 addend = value & howto->src_mask;
13048 if (addend & ((howto->src_mask + 1) >> 1))
13049 {
13050 bfd_signed_vma mask;
13051
13052 mask = -1;
13053 mask &= ~ howto->src_mask;
13054 addend |= mask;
13055 }
13056 break;
4e7fd91e 13057 }
39623e12 13058
4e7fd91e
PB		 13059 msec = sec;
13060 addend =
13061 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13062 - relocation;
13063 addend += msec->output_section->vma + msec->output_offset;
39623e12 13064
cc643b88 13065 /* Cases here must match those in the preceding
39623e12
PB		 13066 switch statement. */
13067 switch (r_type)
13068 {
13069 case R_ARM_MOVW_ABS_NC:
13070 case R_ARM_MOVT_ABS:
13071 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13072 | (addend & 0xfff);
13073 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13074 break;
13075
13076 case R_ARM_THM_MOVW_ABS_NC:
13077 case R_ARM_THM_MOVT_ABS:
13078 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13079 | (addend & 0xff) | ((addend & 0x0800) << 15);
13080 bfd_put_16 (input_bfd, value >> 16,
13081 contents + rel->r_offset);
13082 bfd_put_16 (input_bfd, value,
13083 contents + rel->r_offset + 2);
13084 break;
13085
13086 default:
13087 value = (value & ~ howto->dst_mask)
13088 | (addend & howto->dst_mask);
13089 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13090 break;
13091 }
f8df10f4 13092 }
f8df10f4 13093 }
4e7fd91e
PB		 13094 else
13095 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 13096 }
13097 else
13098 {
62d887d4 13099 bfd_boolean warned, ignored;
560e09e9 13100
b2a8e766
AM		 13101 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13102 r_symndx, symtab_hdr, sym_hashes,
13103 h, sec, relocation,
62d887d4 13104 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 13105
13106 sym_type = h->type;
252b5132
RH		 13107 }
13108
dbaa2011 13109 if (sec != NULL && discarded_section (sec))
e4067dbb 13110 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 13111 rel, 1, relend, howto, 0, contents);
ab96bf03 13112
0e1862bb 13113 if (bfd_link_relocatable (info))
ab96bf03
AM		 13114 {
13115 /* This is a relocatable link. We don't have to change
13116 anything, unless the reloc is against a section symbol,
13117 in which case we have to adjust according to where the
13118 section symbol winds up in the output section. */
13119 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13120 {
13121 if (globals->use_rel)
13122 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13123 howto, (bfd_signed_vma) sec->output_offset);
13124 else
13125 rel->r_addend += sec->output_offset;
13126 }
13127 continue;
13128 }
13129
252b5132
RH		 13130 if (h != NULL)
13131 name = h->root.root.string;
13132 else
13133 {
13134 name = (bfd_elf_string_from_elf_section
13135 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13136 if (name == NULL || *name == '\0')
13137 name = bfd_section_name (input_bfd, sec);
13138 }
f21f3fe0 13139
cf35638d 13140 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 13141 && r_type != R_ARM_NONE
13142 && (h == NULL
13143 || h->root.type == bfd_link_hash_defined
13144 || h->root.type == bfd_link_hash_defweak)
13145 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13146 {
4eca0228 13147 _bfd_error_handler
ba93b8ac 13148 ((sym_type == STT_TLS
695344c0 13149 /* xgettext:c-format */
2dcf00ce 13150 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 13151 /* xgettext:c-format */
2dcf00ce 13152 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 13153 input_bfd,
13154 input_section,
2dcf00ce 13155 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 13156 howto->name,
13157 name);
13158 }
13159
0855e32b 13160 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 13161 done, i.e., the relaxation produced the final output we want,
13162 and we won't let anybody mess with it. Also, we have to do
13163 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 13164 both in relaxed and non-relaxed cases. */
39d911fc
TP		 13165 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13166 || (IS_ARM_TLS_GNU_RELOC (r_type)
13167 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13168 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13169 & GOT_TLS_GDESC)))
13170 {
13171 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13172 contents, rel, h == NULL);
13173 /* This may have been marked unresolved because it came from
13174 a shared library. But we've just dealt with that. */
13175 unresolved_reloc = 0;
13176 }
13177 else
13178 r = bfd_reloc_continue;
b38cadfb 13179
39d911fc
TP		 13180 if (r == bfd_reloc_continue)
13181 {
13182 unsigned char branch_type =
13183 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13184 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13185
13186 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13187 input_section, contents, rel,
13188 relocation, info, sec, name,
13189 sym_type, branch_type, h,
13190 &unresolved_reloc,
13191 &error_message);
13192 }
0945cdfd
DJ		 13193
13194 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13195 because such sections are not SEC_ALLOC and thus ld.so will
13196 not process them. */
13197 if (unresolved_reloc
99059e56
RM		 13198 && !((input_section->flags & SEC_DEBUGGING) != 0
13199 && h->def_dynamic)
1d5316ab
AM		 13200 && _bfd_elf_section_offset (output_bfd, info, input_section,
13201 rel->r_offset) != (bfd_vma) -1)
0945cdfd 13202 {
4eca0228 13203 _bfd_error_handler
695344c0 13204 /* xgettext:c-format */
2dcf00ce
AM		 13205 (_("%pB(%pA+%#" PRIx64 "): "
13206 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 13207 input_bfd,
13208 input_section,
2dcf00ce 13209 (uint64_t) rel->r_offset,
843fe662
L		 13210 howto->name,
13211 h->root.root.string);
0945cdfd
DJ		 13212 return FALSE;
13213 }
252b5132
RH		 13214
13215 if (r != bfd_reloc_ok)
13216 {
252b5132
RH		 13217 switch (r)
13218 {
13219 case bfd_reloc_overflow:
cf919dfd
PB		 13220 /* If the overflowing reloc was to an undefined symbol,
13221 we have already printed one error message and there
13222 is no point complaining again. */
1a72702b
AM		 13223 if (!h || h->root.type != bfd_link_hash_undefined)
13224 (*info->callbacks->reloc_overflow)
13225 (info, (h ? &h->root : NULL), name, howto->name,
13226 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13227 break;
13228
13229 case bfd_reloc_undefined:
1a72702b
AM		 13230 (*info->callbacks->undefined_symbol)
13231 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 13232 break;
13233
13234 case bfd_reloc_outofrange:
f2a9dd69 13235 error_message = _("out of range");
252b5132
RH		 13236 goto common_error;
13237
13238 case bfd_reloc_notsupported:
f2a9dd69 13239 error_message = _("unsupported relocation");
252b5132
RH		 13240 goto common_error;
13241
13242 case bfd_reloc_dangerous:
f2a9dd69 13243 /* error_message should already be set. */
252b5132
RH		 13244 goto common_error;
13245
13246 default:
f2a9dd69 13247 error_message = _("unknown error");
8029a119 13248 /* Fall through. */
252b5132
RH		 13249
13250 common_error:
f2a9dd69 13251 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 13252 (*info->callbacks->reloc_dangerous)
13253 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13254 break;
13255 }
13256 }
13257 }
13258
b34976b6 13259 return TRUE;
252b5132
RH		 13260}
13261
91d6fa6a 13262/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 13263 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 13264 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 13265 maintaining that condition). */
13266
13267static void
13268add_unwind_table_edit (arm_unwind_table_edit **head,
13269 arm_unwind_table_edit **tail,
13270 arm_unwind_edit_type type,
13271 asection *linked_section,
91d6fa6a 13272 unsigned int tindex)
2468f9c9 13273{
21d799b5
NC		 13274 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13275 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 13276
2468f9c9
PB		 13277 new_edit->type = type;
13278 new_edit->linked_section = linked_section;
91d6fa6a 13279 new_edit->index = tindex;
b38cadfb 13280
91d6fa6a 13281 if (tindex > 0)
2468f9c9
PB		 13282 {
13283 new_edit->next = NULL;
13284
13285 if (*tail)
13286 (*tail)->next = new_edit;
13287
13288 (*tail) = new_edit;
13289
13290 if (!*head)
13291 (*head) = new_edit;
13292 }
13293 else
13294 {
13295 new_edit->next = *head;
13296
13297 if (!*tail)
13298 *tail = new_edit;
13299
13300 *head = new_edit;
13301 }
13302}
13303
13304static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13305
13306/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13307static void
13308adjust_exidx_size(asection *exidx_sec, int adjust)
13309{
13310 asection *out_sec;
13311
13312 if (!exidx_sec->rawsize)
13313 exidx_sec->rawsize = exidx_sec->size;
13314
13315 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
13316 out_sec = exidx_sec->output_section;
13317 /* Adjust size of output section. */
13318 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
13319}
13320
13321/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13322static void
13323insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
13324{
13325 struct _arm_elf_section_data *exidx_arm_data;
13326
13327 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13328 add_unwind_table_edit (
13329 &exidx_arm_data->u.exidx.unwind_edit_list,
13330 &exidx_arm_data->u.exidx.unwind_edit_tail,
13331 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13332
491d01d3
YU		 13333 exidx_arm_data->additional_reloc_count++;
13334
2468f9c9
PB		 13335 adjust_exidx_size(exidx_sec, 8);
13336}
13337
13338/* Scan .ARM.exidx tables, and create a list describing edits which should be
13339 made to those tables, such that:
b38cadfb 13340
2468f9c9
PB		 13341 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13342 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 13343 codes which have been inlined into the index).
2468f9c9 13344
85fdf906
AH		 13345 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13346
2468f9c9 13347 The edits are applied when the tables are written
b38cadfb 13348 (in elf32_arm_write_section). */
2468f9c9
PB		 13349
13350bfd_boolean
13351elf32_arm_fix_exidx_coverage (asection **text_section_order,
13352 unsigned int num_text_sections,
85fdf906
AH		 13353 struct bfd_link_info *info,
13354 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 13355{
13356 bfd *inp;
13357 unsigned int last_second_word = 0, i;
13358 asection *last_exidx_sec = NULL;
13359 asection *last_text_sec = NULL;
13360 int last_unwind_type = -1;
13361
13362 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13363 text sections. */
c72f2fb2 13364 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 13365 {
13366 asection *sec;
b38cadfb 13367
2468f9c9 13368 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 13369 {
2468f9c9
PB		 13370 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13371 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 13372
dec9d5df 13373 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 13374 continue;
b38cadfb 13375
2468f9c9
PB		 13376 if (elf_sec->linked_to)
13377 {
13378 Elf_Internal_Shdr *linked_hdr
99059e56 13379 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 13380 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 13381 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 13382
13383 if (linked_sec_arm_data == NULL)
99059e56 13384 continue;
2468f9c9
PB		 13385
13386 /* Link this .ARM.exidx section back from the text section it
99059e56 13387 describes. */
2468f9c9
PB		 13388 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13389 }
13390 }
13391 }
13392
13393 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13394 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 13395 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 13396
13397 for (i = 0; i < num_text_sections; i++)
13398 {
13399 asection *sec = text_section_order[i];
13400 asection *exidx_sec;
13401 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13402 struct _arm_elf_section_data *exidx_arm_data;
13403 bfd_byte *contents = NULL;
13404 int deleted_exidx_bytes = 0;
13405 bfd_vma j;
13406 arm_unwind_table_edit *unwind_edit_head = NULL;
13407 arm_unwind_table_edit *unwind_edit_tail = NULL;
13408 Elf_Internal_Shdr *hdr;
13409 bfd *ibfd;
13410
13411 if (arm_data == NULL)
99059e56 13412 continue;
2468f9c9
PB		 13413
13414 exidx_sec = arm_data->u.text.arm_exidx_sec;
13415 if (exidx_sec == NULL)
13416 {
13417 /* Section has no unwind data. */
13418 if (last_unwind_type == 0 || !last_exidx_sec)
13419 continue;
13420
13421 /* Ignore zero sized sections. */
13422 if (sec->size == 0)
13423 continue;
13424
13425 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13426 last_unwind_type = 0;
13427 continue;
13428 }
13429
22a8f80e
PB		 13430 /* Skip /DISCARD/ sections. */
13431 if (bfd_is_abs_section (exidx_sec->output_section))
13432 continue;
13433
2468f9c9
PB		 13434 hdr = &elf_section_data (exidx_sec)->this_hdr;
13435 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 13436 continue;
b38cadfb 13437
2468f9c9
PB		 13438 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13439 if (exidx_arm_data == NULL)
99059e56 13440 continue;
b38cadfb 13441
2468f9c9 13442 ibfd = exidx_sec->owner;
b38cadfb 13443
2468f9c9
PB		 13444 if (hdr->contents != NULL)
13445 contents = hdr->contents;
13446 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13447 /* An error? */
13448 continue;
13449
ac06903d
YU		 13450 if (last_unwind_type > 0)
13451 {
13452 unsigned int first_word = bfd_get_32 (ibfd, contents);
13453 /* Add cantunwind if first unwind item does not match section
13454 start. */
13455 if (first_word != sec->vma)
13456 {
13457 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13458 last_unwind_type = 0;
13459 }
13460 }
13461
2468f9c9
PB		 13462 for (j = 0; j < hdr->sh_size; j += 8)
13463 {
13464 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13465 int unwind_type;
13466 int elide = 0;
13467
13468 /* An EXIDX_CANTUNWIND entry. */
13469 if (second_word == 1)
13470 {
13471 if (last_unwind_type == 0)
13472 elide = 1;
13473 unwind_type = 0;
13474 }
13475 /* Inlined unwinding data. Merge if equal to previous. */
13476 else if ((second_word & 0x80000000) != 0)
13477 {
85fdf906
AH		 13478 if (merge_exidx_entries
13479 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 13480 elide = 1;
13481 unwind_type = 1;
13482 last_second_word = second_word;
13483 }
13484 /* Normal table entry. In theory we could merge these too,
13485 but duplicate entries are likely to be much less common. */
13486 else
13487 unwind_type = 2;
13488
491d01d3 13489 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 13490 {
13491 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13492 DELETE_EXIDX_ENTRY, NULL, j / 8);
13493
13494 deleted_exidx_bytes += 8;
13495 }
13496
13497 last_unwind_type = unwind_type;
13498 }
13499
13500 /* Free contents if we allocated it ourselves. */
13501 if (contents != hdr->contents)
99059e56 13502 free (contents);
2468f9c9
PB		 13503
13504 /* Record edits to be applied later (in elf32_arm_write_section). */
13505 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13506 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 13507
2468f9c9
PB		 13508 if (deleted_exidx_bytes > 0)
13509 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
13510
13511 last_exidx_sec = exidx_sec;
13512 last_text_sec = sec;
13513 }
13514
13515 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 13516 if (!bfd_link_relocatable (info) && last_exidx_sec
13517 && last_unwind_type != 0)
2468f9c9
PB		 13518 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13519
13520 return TRUE;
13521}
13522
3e6b1042
DJ		 13523static bfd_boolean
13524elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13525 bfd *ibfd, const char *name)
13526{
13527 asection *sec, *osec;
13528
3d4d4302 13529 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 13530 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13531 return TRUE;
13532
13533 osec = sec->output_section;
13534 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13535 return TRUE;
13536
13537 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13538 sec->output_offset, sec->size))
13539 return FALSE;
13540
13541 return TRUE;
13542}
13543
13544static bfd_boolean
13545elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13546{
13547 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 13548 asection *sec, *osec;
3e6b1042 13549
4dfe6ac6
NC		 13550 if (globals == NULL)
13551 return FALSE;
13552
3e6b1042
DJ		 13553 /* Invoke the regular ELF backend linker to do all the work. */
13554 if (!bfd_elf_final_link (abfd, info))
13555 return FALSE;
13556
fe33d2fa
CL		 13557 /* Process stub sections (eg BE8 encoding, ...). */
13558 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 13559 unsigned int i;
cdb21a0a
NS		 13560 for (i=0; i<htab->top_id; i++)
13561 {
13562 sec = htab->stub_group[i].stub_sec;
13563 /* Only process it once, in its link_sec slot. */
13564 if (sec && i == htab->stub_group[i].link_sec->id)
13565 {
13566 osec = sec->output_section;
13567 elf32_arm_write_section (abfd, info, sec, sec->contents);
13568 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13569 sec->output_offset, sec->size))
13570 return FALSE;
13571 }
fe33d2fa 13572 }
fe33d2fa 13573
3e6b1042
DJ		 13574 /* Write out any glue sections now that we have created all the
13575 stubs. */
13576 if (globals->bfd_of_glue_owner != NULL)
13577 {
13578 if (! elf32_arm_output_glue_section (info, abfd,
13579 globals->bfd_of_glue_owner,
13580 ARM2THUMB_GLUE_SECTION_NAME))
13581 return FALSE;
13582
13583 if (! elf32_arm_output_glue_section (info, abfd,
13584 globals->bfd_of_glue_owner,
13585 THUMB2ARM_GLUE_SECTION_NAME))
13586 return FALSE;
13587
13588 if (! elf32_arm_output_glue_section (info, abfd,
13589 globals->bfd_of_glue_owner,
13590 VFP11_ERRATUM_VENEER_SECTION_NAME))
13591 return FALSE;
13592
a504d23a
LA		 13593 if (! elf32_arm_output_glue_section (info, abfd,
13594 globals->bfd_of_glue_owner,
13595 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13596 return FALSE;
13597
3e6b1042
DJ		 13598 if (! elf32_arm_output_glue_section (info, abfd,
13599 globals->bfd_of_glue_owner,
13600 ARM_BX_GLUE_SECTION_NAME))
13601 return FALSE;
13602 }
13603
13604 return TRUE;
13605}
13606
5968a7b8
NC		 13607/* Return a best guess for the machine number based on the attributes. */
13608
13609static unsigned int
13610bfd_arm_get_mach_from_attributes (bfd * abfd)
13611{
13612 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13613
13614 switch (arch)
13615 {
13616 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13617 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13618 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13619
13620 case TAG_CPU_ARCH_V5TE:
13621 {
13622 char * name;
13623
13624 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13625 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13626
13627 if (name)
13628 {
13629 if (strcmp (name, "IWMMXT2") == 0)
13630 return bfd_mach_arm_iWMMXt2;
13631
13632 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13633 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13634
13635 if (strcmp (name, "XSCALE") == 0)
13636 {
13637 int wmmx;
13638
13639 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13640 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13641 switch (wmmx)
13642 {
13643 case 1: return bfd_mach_arm_iWMMXt;
13644 case 2: return bfd_mach_arm_iWMMXt2;
13645 default: return bfd_mach_arm_XScale;
13646 }
13647 }
5968a7b8
NC		 13648 }
13649
13650 return bfd_mach_arm_5TE;
13651 }
13652
13653 default:
13654 return bfd_mach_arm_unknown;
13655 }
13656}
13657
c178919b
NC		 13658/* Set the right machine number. */
13659
13660static bfd_boolean
57e8b36a 13661elf32_arm_object_p (bfd *abfd)
c178919b 13662{
5a6c6817 13663 unsigned int mach;
57e8b36a 13664
5a6c6817 13665 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13666
5968a7b8
NC		 13667 if (mach == bfd_mach_arm_unknown)
13668 {
13669 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13670 mach = bfd_mach_arm_ep9312;
13671 else
13672 mach = bfd_arm_get_mach_from_attributes (abfd);
13673 }
c178919b 13674
5968a7b8 13675 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13676 return TRUE;
13677}
13678
fc830a83 13679/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13680
b34976b6 13681static bfd_boolean
57e8b36a 13682elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13683{
13684 if (elf_flags_init (abfd)
13685 && elf_elfheader (abfd)->e_flags != flags)
13686 {
fc830a83
NC		 13687 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13688 {
fd2ec330 13689 if (flags & EF_ARM_INTERWORK)
4eca0228 13690 _bfd_error_handler
90b6238f 13691 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13692 abfd);
fc830a83 13693 else
d003868e 13694 _bfd_error_handler
90b6238f 13695 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13696 abfd);
fc830a83 13697 }
252b5132
RH		 13698 }
13699 else
13700 {
13701 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13702 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13703 }
13704
b34976b6 13705 return TRUE;
252b5132
RH		 13706}
13707
fc830a83 13708/* Copy backend specific data from one object module to another. */
9b485d32 13709
b34976b6 13710static bfd_boolean
57e8b36a 13711elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13712{
13713 flagword in_flags;
13714 flagword out_flags;
13715
0ffa91dd 13716 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13717 return TRUE;
252b5132 13718
fc830a83 13719 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13720 out_flags = elf_elfheader (obfd)->e_flags;
13721
fc830a83
NC		 13722 if (elf_flags_init (obfd)
13723 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13724 && in_flags != out_flags)
252b5132 13725 {
252b5132 13726 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13727 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13728 return FALSE;
252b5132
RH		 13729
13730 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13731 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13732 return FALSE;
252b5132
RH		 13733
13734 /* If the src and dest have different interworking flags
99059e56 13735 then turn off the interworking bit. */
fd2ec330 13736 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13737 {
fd2ec330 13738 if (out_flags & EF_ARM_INTERWORK)
d003868e 13739 _bfd_error_handler
90b6238f 13740 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 13741 obfd, ibfd);
252b5132 13742
fd2ec330 13743 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13744 }
1006ba19
PB		 13745
13746 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13747 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13748 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13749 }
13750
13751 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13752 elf_flags_init (obfd) = TRUE;
252b5132 13753
e2349352 13754 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13755}
13756
13757/* Values for Tag_ABI_PCS_R9_use. */
13758enum
13759{
13760 AEABI_R9_V6,
13761 AEABI_R9_SB,
13762 AEABI_R9_TLS,
13763 AEABI_R9_unused
13764};
13765
13766/* Values for Tag_ABI_PCS_RW_data. */
13767enum
13768{
13769 AEABI_PCS_RW_data_absolute,
13770 AEABI_PCS_RW_data_PCrel,
13771 AEABI_PCS_RW_data_SBrel,
13772 AEABI_PCS_RW_data_unused
13773};
13774
13775/* Values for Tag_ABI_enum_size. */
13776enum
13777{
13778 AEABI_enum_unused,
13779 AEABI_enum_short,
13780 AEABI_enum_wide,
13781 AEABI_enum_forced_wide
13782};
13783
104d59d1
JM		 13784/* Determine whether an object attribute tag takes an integer, a
13785 string or both. */
906e58ca 13786
104d59d1
JM		 13787static int
13788elf32_arm_obj_attrs_arg_type (int tag)
13789{
13790 if (tag == Tag_compatibility)
3483fe2e 13791 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 13792 else if (tag == Tag_nodefaults)
3483fe2e
AS		 13793 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
13794 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
13795 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 13796 else if (tag < 32)
3483fe2e 13797 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 13798 else
3483fe2e 13799 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 13800}
13801
5aa6ff7c
AS		 13802/* The ABI defines that Tag_conformance should be emitted first, and that
13803 Tag_nodefaults should be second (if either is defined). This sets those
13804 two positions, and bumps up the position of all the remaining tags to
13805 compensate. */
13806static int
13807elf32_arm_obj_attrs_order (int num)
13808{
3de4a297 13809 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 13810 return Tag_conformance;
3de4a297 13811 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 13812 return Tag_nodefaults;
13813 if ((num - 2) < Tag_nodefaults)
13814 return num - 2;
13815 if ((num - 1) < Tag_conformance)
13816 return num - 1;
13817 return num;
13818}
13819
e8b36cd1
JM		 13820/* Attribute numbers >=64 (mod 128) can be safely ignored. */
13821static bfd_boolean
13822elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
13823{
13824 if ((tag & 127) < 64)
13825 {
13826 _bfd_error_handler
90b6238f 13827 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 13828 abfd, tag);
13829 bfd_set_error (bfd_error_bad_value);
13830 return FALSE;
13831 }
13832 else
13833 {
13834 _bfd_error_handler
90b6238f 13835 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 13836 abfd, tag);
13837 return TRUE;
13838 }
13839}
13840
91e22acd
AS		 13841/* Read the architecture from the Tag_also_compatible_with attribute, if any.
13842 Returns -1 if no architecture could be read. */
13843
13844static int
13845get_secondary_compatible_arch (bfd *abfd)
13846{
13847 obj_attribute *attr =
13848 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
13849
13850 /* Note: the tag and its argument below are uleb128 values, though
13851 currently-defined values fit in one byte for each. */
13852 if (attr->s
13853 && attr->s[0] == Tag_CPU_arch
13854 && (attr->s[1] & 128) != 128
13855 && attr->s[2] == 0)
13856 return attr->s[1];
13857
13858 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13859 return -1;
13860}
13861
13862/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13863 The tag is removed if ARCH is -1. */
13864
8e79c3df 13865static void
91e22acd 13866set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 13867{
91e22acd
AS		 13868 obj_attribute *attr =
13869 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 13870
91e22acd
AS		 13871 if (arch == -1)
13872 {
13873 attr->s = NULL;
13874 return;
8e79c3df 13875 }
91e22acd
AS		 13876
13877 /* Note: the tag and its argument below are uleb128 values, though
13878 currently-defined values fit in one byte for each. */
13879 if (!attr->s)
21d799b5 13880 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 13881 attr->s[0] = Tag_CPU_arch;
13882 attr->s[1] = arch;
13883 attr->s[2] = '\0';
8e79c3df
CM		 13884}
13885
91e22acd
AS		 13886/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13887 into account. */
13888
13889static int
13890tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
13891 int newtag, int secondary_compat)
8e79c3df 13892{
91e22acd
AS		 13893#define T(X) TAG_CPU_ARCH_##X
13894 int tagl, tagh, result;
13895 const int v6t2[] =
13896 {
13897 T(V6T2), /* PRE_V4. */
13898 T(V6T2), /* V4. */
13899 T(V6T2), /* V4T. */
13900 T(V6T2), /* V5T. */
13901 T(V6T2), /* V5TE. */
13902 T(V6T2), /* V5TEJ. */
13903 T(V6T2), /* V6. */
13904 T(V7), /* V6KZ. */
13905 T(V6T2) /* V6T2. */
13906 };
13907 const int v6k[] =
13908 {
13909 T(V6K), /* PRE_V4. */
13910 T(V6K), /* V4. */
13911 T(V6K), /* V4T. */
13912 T(V6K), /* V5T. */
13913 T(V6K), /* V5TE. */
13914 T(V6K), /* V5TEJ. */
13915 T(V6K), /* V6. */
13916 T(V6KZ), /* V6KZ. */
13917 T(V7), /* V6T2. */
13918 T(V6K) /* V6K. */
13919 };
13920 const int v7[] =
13921 {
13922 T(V7), /* PRE_V4. */
13923 T(V7), /* V4. */
13924 T(V7), /* V4T. */
13925 T(V7), /* V5T. */
13926 T(V7), /* V5TE. */
13927 T(V7), /* V5TEJ. */
13928 T(V7), /* V6. */
13929 T(V7), /* V6KZ. */
13930 T(V7), /* V6T2. */
13931 T(V7), /* V6K. */
13932 T(V7) /* V7. */
13933 };
13934 const int v6_m[] =
13935 {
07d6d2b8
AM		 13936 -1, /* PRE_V4. */
13937 -1, /* V4. */
91e22acd
AS		 13938 T(V6K), /* V4T. */
13939 T(V6K), /* V5T. */
13940 T(V6K), /* V5TE. */
13941 T(V6K), /* V5TEJ. */
13942 T(V6K), /* V6. */
13943 T(V6KZ), /* V6KZ. */
13944 T(V7), /* V6T2. */
13945 T(V6K), /* V6K. */
13946 T(V7), /* V7. */
13947 T(V6_M) /* V6_M. */
13948 };
13949 const int v6s_m[] =
13950 {
07d6d2b8
AM		 13951 -1, /* PRE_V4. */
13952 -1, /* V4. */
91e22acd
AS		 13953 T(V6K), /* V4T. */
13954 T(V6K), /* V5T. */
13955 T(V6K), /* V5TE. */
13956 T(V6K), /* V5TEJ. */
13957 T(V6K), /* V6. */
13958 T(V6KZ), /* V6KZ. */
13959 T(V7), /* V6T2. */
13960 T(V6K), /* V6K. */
13961 T(V7), /* V7. */
13962 T(V6S_M), /* V6_M. */
13963 T(V6S_M) /* V6S_M. */
13964 };
9e3c6df6
PB		 13965 const int v7e_m[] =
13966 {
07d6d2b8
AM		 13967 -1, /* PRE_V4. */
13968 -1, /* V4. */
9e3c6df6
PB		 13969 T(V7E_M), /* V4T. */
13970 T(V7E_M), /* V5T. */
13971 T(V7E_M), /* V5TE. */
13972 T(V7E_M), /* V5TEJ. */
13973 T(V7E_M), /* V6. */
13974 T(V7E_M), /* V6KZ. */
13975 T(V7E_M), /* V6T2. */
13976 T(V7E_M), /* V6K. */
13977 T(V7E_M), /* V7. */
13978 T(V7E_M), /* V6_M. */
13979 T(V7E_M), /* V6S_M. */
13980 T(V7E_M) /* V7E_M. */
13981 };
bca38921
MGD		 13982 const int v8[] =
13983 {
13984 T(V8), /* PRE_V4. */
13985 T(V8), /* V4. */
13986 T(V8), /* V4T. */
13987 T(V8), /* V5T. */
13988 T(V8), /* V5TE. */
13989 T(V8), /* V5TEJ. */
13990 T(V8), /* V6. */
13991 T(V8), /* V6KZ. */
13992 T(V8), /* V6T2. */
13993 T(V8), /* V6K. */
13994 T(V8), /* V7. */
13995 T(V8), /* V6_M. */
13996 T(V8), /* V6S_M. */
13997 T(V8), /* V7E_M. */
13998 T(V8) /* V8. */
13999 };
bff0500d
TP		 14000 const int v8r[] =
14001 {
14002 T(V8R), /* PRE_V4. */
14003 T(V8R), /* V4. */
14004 T(V8R), /* V4T. */
14005 T(V8R), /* V5T. */
14006 T(V8R), /* V5TE. */
14007 T(V8R), /* V5TEJ. */
14008 T(V8R), /* V6. */
14009 T(V8R), /* V6KZ. */
14010 T(V8R), /* V6T2. */
14011 T(V8R), /* V6K. */
14012 T(V8R), /* V7. */
14013 T(V8R), /* V6_M. */
14014 T(V8R), /* V6S_M. */
14015 T(V8R), /* V7E_M. */
14016 T(V8), /* V8. */
14017 T(V8R), /* V8R. */
14018 };
2fd158eb
TP		 14019 const int v8m_baseline[] =
14020 {
14021 -1, /* PRE_V4. */
14022 -1, /* V4. */
14023 -1, /* V4T. */
14024 -1, /* V5T. */
14025 -1, /* V5TE. */
14026 -1, /* V5TEJ. */
14027 -1, /* V6. */
14028 -1, /* V6KZ. */
14029 -1, /* V6T2. */
14030 -1, /* V6K. */
14031 -1, /* V7. */
14032 T(V8M_BASE), /* V6_M. */
14033 T(V8M_BASE), /* V6S_M. */
14034 -1, /* V7E_M. */
14035 -1, /* V8. */
bff0500d 14036 -1, /* V8R. */
2fd158eb
TP		 14037 T(V8M_BASE) /* V8-M BASELINE. */
14038 };
14039 const int v8m_mainline[] =
14040 {
14041 -1, /* PRE_V4. */
14042 -1, /* V4. */
14043 -1, /* V4T. */
14044 -1, /* V5T. */
14045 -1, /* V5TE. */
14046 -1, /* V5TEJ. */
14047 -1, /* V6. */
14048 -1, /* V6KZ. */
14049 -1, /* V6T2. */
14050 -1, /* V6K. */
14051 T(V8M_MAIN), /* V7. */
14052 T(V8M_MAIN), /* V6_M. */
14053 T(V8M_MAIN), /* V6S_M. */
14054 T(V8M_MAIN), /* V7E_M. */
14055 -1, /* V8. */
bff0500d 14056 -1, /* V8R. */
2fd158eb
TP		 14057 T(V8M_MAIN), /* V8-M BASELINE. */
14058 T(V8M_MAIN) /* V8-M MAINLINE. */
14059 };
91e22acd
AS		 14060 const int v4t_plus_v6_m[] =
14061 {
14062 -1, /* PRE_V4. */
14063 -1, /* V4. */
14064 T(V4T), /* V4T. */
14065 T(V5T), /* V5T. */
14066 T(V5TE), /* V5TE. */
14067 T(V5TEJ), /* V5TEJ. */
14068 T(V6), /* V6. */
14069 T(V6KZ), /* V6KZ. */
14070 T(V6T2), /* V6T2. */
14071 T(V6K), /* V6K. */
14072 T(V7), /* V7. */
14073 T(V6_M), /* V6_M. */
14074 T(V6S_M), /* V6S_M. */
9e3c6df6 14075 T(V7E_M), /* V7E_M. */
bca38921 14076 T(V8), /* V8. */
bff0500d 14077 -1, /* V8R. */
2fd158eb
TP		 14078 T(V8M_BASE), /* V8-M BASELINE. */
14079 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 14080 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14081 };
14082 const int *comb[] =
14083 {
14084 v6t2,
14085 v6k,
14086 v7,
14087 v6_m,
14088 v6s_m,
9e3c6df6 14089 v7e_m,
bca38921 14090 v8,
bff0500d 14091 v8r,
2fd158eb
TP		 14092 v8m_baseline,
14093 v8m_mainline,
91e22acd
AS		 14094 /* Pseudo-architecture. */
14095 v4t_plus_v6_m
14096 };
14097
14098 /* Check we've not got a higher architecture than we know about. */
14099
9e3c6df6 14100 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 14101 {
90b6238f 14102 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 14103 return -1;
14104 }
14105
14106 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14107
14108 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14109 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14110 oldtag = T(V4T_PLUS_V6_M);
14111
14112 /* And override the new tag if we have a Tag_also_compatible_with on the
14113 input. */
14114
14115 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14116 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14117 newtag = T(V4T_PLUS_V6_M);
14118
14119 tagl = (oldtag < newtag) ? oldtag : newtag;
14120 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14121
14122 /* Architectures before V6KZ add features monotonically. */
14123 if (tagh <= TAG_CPU_ARCH_V6KZ)
14124 return result;
14125
4ed7ed8d 14126 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 14127
14128 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14129 as the canonical version. */
14130 if (result == T(V4T_PLUS_V6_M))
14131 {
14132 result = T(V4T);
14133 *secondary_compat_out = T(V6_M);
14134 }
14135 else
14136 *secondary_compat_out = -1;
14137
14138 if (result == -1)
14139 {
90b6238f 14140 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 14141 ibfd, oldtag, newtag);
14142 return -1;
14143 }
14144
14145 return result;
14146#undef T
8e79c3df
CM		 14147}
14148
ac56ee8f
MGD		 14149/* Query attributes object to see if integer divide instructions may be
14150 present in an object. */
14151static bfd_boolean
14152elf32_arm_attributes_accept_div (const obj_attribute *attr)
14153{
14154 int arch = attr[Tag_CPU_arch].i;
14155 int profile = attr[Tag_CPU_arch_profile].i;
14156
14157 switch (attr[Tag_DIV_use].i)
14158 {
14159 case 0:
14160 /* Integer divide allowed if instruction contained in archetecture. */
14161 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14162 return TRUE;
14163 else if (arch >= TAG_CPU_ARCH_V7E_M)
14164 return TRUE;
14165 else
14166 return FALSE;
14167
14168 case 1:
14169 /* Integer divide explicitly prohibited. */
14170 return FALSE;
14171
14172 default:
14173 /* Unrecognised case - treat as allowing divide everywhere. */
14174 case 2:
14175 /* Integer divide allowed in ARM state. */
14176 return TRUE;
14177 }
14178}
14179
14180/* Query attributes object to see if integer divide instructions are
14181 forbidden to be in the object. This is not the inverse of
14182 elf32_arm_attributes_accept_div. */
14183static bfd_boolean
14184elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14185{
14186 return attr[Tag_DIV_use].i == 1;
14187}
14188
ee065d83
PB		 14189/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14190 are conflicting attributes. */
906e58ca 14191
ee065d83 14192static bfd_boolean
50e03d47 14193elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 14194{
50e03d47 14195 bfd *obfd = info->output_bfd;
104d59d1
JM		 14196 obj_attribute *in_attr;
14197 obj_attribute *out_attr;
ee065d83
PB		 14198 /* Some tags have 0 = don't care, 1 = strong requirement,
14199 2 = weak requirement. */
91e22acd 14200 static const int order_021[3] = {0, 2, 1};
ee065d83 14201 int i;
91e22acd 14202 bfd_boolean result = TRUE;
9274e9de 14203 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 14204
3e6b1042
DJ		 14205 /* Skip the linker stubs file. This preserves previous behavior
14206 of accepting unknown attributes in the first input file - but
14207 is that a bug? */
14208 if (ibfd->flags & BFD_LINKER_CREATED)
14209 return TRUE;
14210
9274e9de
TG		 14211 /* Skip any input that hasn't attribute section.
14212 This enables to link object files without attribute section with
14213 any others. */
14214 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14215 return TRUE;
14216
104d59d1 14217 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 14218 {
14219 /* This is the first object. Copy the attributes. */
104d59d1 14220 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 14221
cd21e546
MGD		 14222 out_attr = elf_known_obj_attributes_proc (obfd);
14223
004ae526
PB		 14224 /* Use the Tag_null value to indicate the attributes have been
14225 initialized. */
cd21e546 14226 out_attr[0].i = 1;
004ae526 14227
cd21e546
MGD		 14228 /* We do not output objects with Tag_MPextension_use_legacy - we move
14229 the attribute's value to Tag_MPextension_use. */
14230 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14231 {
14232 if (out_attr[Tag_MPextension_use].i != 0
14233 && out_attr[Tag_MPextension_use_legacy].i
99059e56 14234 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 14235 {
14236 _bfd_error_handler
871b3ab2 14237 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 14238 "Tag_MPextension_use attributes"), ibfd);
14239 result = FALSE;
14240 }
14241
14242 out_attr[Tag_MPextension_use] =
14243 out_attr[Tag_MPextension_use_legacy];
14244 out_attr[Tag_MPextension_use_legacy].type = 0;
14245 out_attr[Tag_MPextension_use_legacy].i = 0;
14246 }
14247
14248 return result;
ee065d83
PB		 14249 }
14250
104d59d1
JM		 14251 in_attr = elf_known_obj_attributes_proc (ibfd);
14252 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 14253 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14254 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14255 {
5c294fee
TG		 14256 /* Ignore mismatches if the object doesn't use floating point or is
14257 floating point ABI independent. */
14258 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14259 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14260 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 14261 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 14262 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14263 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 14264 {
14265 _bfd_error_handler
871b3ab2 14266 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 14267 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14268 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 14269 result = FALSE;
ee065d83
PB		 14270 }
14271 }
14272
3de4a297 14273 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 14274 {
14275 /* Merge this attribute with existing attributes. */
14276 switch (i)
14277 {
14278 case Tag_CPU_raw_name:
14279 case Tag_CPU_name:
6a631e86 14280 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 14281 break;
14282
14283 case Tag_ABI_optimization_goals:
14284 case Tag_ABI_FP_optimization_goals:
14285 /* Use the first value seen. */
14286 break;
14287
14288 case Tag_CPU_arch:
91e22acd
AS		 14289 {
14290 int secondary_compat = -1, secondary_compat_out = -1;
14291 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 14292 int arch_attr;
14293 static const char *name_table[] =
14294 {
91e22acd
AS		 14295 /* These aren't real CPU names, but we can't guess
14296 that from the architecture version alone. */
14297 "Pre v4",
14298 "ARM v4",
14299 "ARM v4T",
14300 "ARM v5T",
14301 "ARM v5TE",
14302 "ARM v5TEJ",
14303 "ARM v6",
14304 "ARM v6KZ",
14305 "ARM v6T2",
14306 "ARM v6K",
14307 "ARM v7",
14308 "ARM v6-M",
bca38921 14309 "ARM v6S-M",
2fd158eb
TP		 14310 "ARM v8",
14311 "",
14312 "ARM v8-M.baseline",
14313 "ARM v8-M.mainline",
91e22acd
AS		 14314 };
14315
14316 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14317 secondary_compat = get_secondary_compatible_arch (ibfd);
14318 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 14319 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14320 &secondary_compat_out,
14321 in_attr[i].i,
14322 secondary_compat);
14323
14324 /* Return with error if failed to merge. */
14325 if (arch_attr == -1)
14326 return FALSE;
14327
14328 out_attr[i].i = arch_attr;
14329
91e22acd
AS		 14330 set_secondary_compatible_arch (obfd, secondary_compat_out);
14331
14332 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14333 if (out_attr[i].i == saved_out_attr)
14334 ; /* Leave the names alone. */
14335 else if (out_attr[i].i == in_attr[i].i)
14336 {
14337 /* The output architecture has been changed to match the
14338 input architecture. Use the input names. */
14339 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14340 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14341 : NULL;
14342 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14343 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14344 : NULL;
14345 }
14346 else
14347 {
14348 out_attr[Tag_CPU_name].s = NULL;
14349 out_attr[Tag_CPU_raw_name].s = NULL;
14350 }
14351
14352 /* If we still don't have a value for Tag_CPU_name,
14353 make one up now. Tag_CPU_raw_name remains blank. */
14354 if (out_attr[Tag_CPU_name].s == NULL
14355 && out_attr[i].i < ARRAY_SIZE (name_table))
14356 out_attr[Tag_CPU_name].s =
14357 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14358 }
14359 break;
14360
ee065d83
PB		 14361 case Tag_ARM_ISA_use:
14362 case Tag_THUMB_ISA_use:
ee065d83 14363 case Tag_WMMX_arch:
91e22acd
AS		 14364 case Tag_Advanced_SIMD_arch:
14365 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 14366 case Tag_ABI_FP_rounding:
ee065d83
PB		 14367 case Tag_ABI_FP_exceptions:
14368 case Tag_ABI_FP_user_exceptions:
14369 case Tag_ABI_FP_number_model:
75375b3e 14370 case Tag_FP_HP_extension:
91e22acd
AS		 14371 case Tag_CPU_unaligned_access:
14372 case Tag_T2EE_use:
91e22acd 14373 case Tag_MPextension_use:
ee065d83
PB		 14374 /* Use the largest value specified. */
14375 if (in_attr[i].i > out_attr[i].i)
14376 out_attr[i].i = in_attr[i].i;
14377 break;
14378
75375b3e 14379 case Tag_ABI_align_preserved:
91e22acd
AS		 14380 case Tag_ABI_PCS_RO_data:
14381 /* Use the smallest value specified. */
14382 if (in_attr[i].i < out_attr[i].i)
14383 out_attr[i].i = in_attr[i].i;
14384 break;
14385
75375b3e 14386 case Tag_ABI_align_needed:
91e22acd 14387 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 14388 && (in_attr[Tag_ABI_align_preserved].i == 0
14389 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 14390 {
91e22acd
AS		 14391 /* This error message should be enabled once all non-conformant
14392 binaries in the toolchain have had the attributes set
14393 properly.
ee065d83 14394 _bfd_error_handler
871b3ab2 14395 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 14396 obfd, ibfd);
14397 result = FALSE; */
ee065d83 14398 }
91e22acd
AS		 14399 /* Fall through. */
14400 case Tag_ABI_FP_denormal:
14401 case Tag_ABI_PCS_GOT_use:
14402 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14403 value if greater than 2 (for future-proofing). */
14404 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14405 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14406 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 14407 out_attr[i].i = in_attr[i].i;
14408 break;
91e22acd 14409
75375b3e
MGD		 14410 case Tag_Virtualization_use:
14411 /* The virtualization tag effectively stores two bits of
14412 information: the intended use of TrustZone (in bit 0), and the
14413 intended use of Virtualization (in bit 1). */
14414 if (out_attr[i].i == 0)
14415 out_attr[i].i = in_attr[i].i;
14416 else if (in_attr[i].i != 0
14417 && in_attr[i].i != out_attr[i].i)
14418 {
14419 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14420 out_attr[i].i = 3;
14421 else
14422 {
14423 _bfd_error_handler
871b3ab2
AM		 14424 (_("error: %pB: unable to merge virtualization attributes "
14425 "with %pB"),
75375b3e
MGD		 14426 obfd, ibfd);
14427 result = FALSE;
14428 }
14429 }
14430 break;
91e22acd
AS		 14431
14432 case Tag_CPU_arch_profile:
14433 if (out_attr[i].i != in_attr[i].i)
14434 {
14435 /* 0 will merge with anything.
14436 'A' and 'S' merge to 'A'.
14437 'R' and 'S' merge to 'R'.
99059e56 14438 'M' and 'A|R|S' is an error. */
91e22acd
AS		 14439 if (out_attr[i].i == 0
14440 || (out_attr[i].i == 'S'
14441 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14442 out_attr[i].i = in_attr[i].i;
14443 else if (in_attr[i].i == 0
14444 || (in_attr[i].i == 'S'
14445 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 14446 ; /* Do nothing. */
91e22acd
AS		 14447 else
14448 {
14449 _bfd_error_handler
90b6238f 14450 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 14451 ibfd,
14452 in_attr[i].i ? in_attr[i].i : '0',
14453 out_attr[i].i ? out_attr[i].i : '0');
14454 result = FALSE;
14455 }
14456 }
14457 break;
15afaa63
TP		 14458
14459 case Tag_DSP_extension:
14460 /* No need to change output value if any of:
14461 - pre (<=) ARMv5T input architecture (do not have DSP)
14462 - M input profile not ARMv7E-M and do not have DSP. */
14463 if (in_attr[Tag_CPU_arch].i <= 3
14464 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14465 && in_attr[Tag_CPU_arch].i != 13
14466 && in_attr[i].i == 0))
14467 ; /* Do nothing. */
14468 /* Output value should be 0 if DSP part of architecture, ie.
14469 - post (>=) ARMv5te architecture output
14470 - A, R or S profile output or ARMv7E-M output architecture. */
14471 else if (out_attr[Tag_CPU_arch].i >= 4
14472 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14473 || out_attr[Tag_CPU_arch_profile].i == 'R'
14474 || out_attr[Tag_CPU_arch_profile].i == 'S'
14475 || out_attr[Tag_CPU_arch].i == 13))
14476 out_attr[i].i = 0;
14477 /* Otherwise, DSP instructions are added and not part of output
14478 architecture. */
14479 else
14480 out_attr[i].i = 1;
14481 break;
14482
75375b3e 14483 case Tag_FP_arch:
62f3b8c8 14484 {
4547cb56
NC		 14485 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14486 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14487 when it's 0. It might mean absence of FP hardware if
99654aaf 14488 Tag_FP_arch is zero. */
4547cb56 14489
a715796b 14490#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 14491 static const struct
14492 {
14493 int ver;
14494 int regs;
bca38921 14495 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 14496 {
14497 {0, 0},
14498 {1, 16},
14499 {2, 16},
14500 {3, 32},
14501 {3, 16},
14502 {4, 32},
bca38921 14503 {4, 16},
a715796b
TG		 14504 {8, 32},
14505 {8, 16}
62f3b8c8
PB		 14506 };
14507 int ver;
14508 int regs;
14509 int newval;
14510
4547cb56
NC		 14511 /* If the output has no requirement about FP hardware,
14512 follow the requirement of the input. */
14513 if (out_attr[i].i == 0)
14514 {
4ec192e6
RE		 14515 /* This assert is still reasonable, we shouldn't
14516 produce the suspicious build attribute
14517 combination (See below for in_attr). */
4547cb56
NC		 14518 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14519 out_attr[i].i = in_attr[i].i;
14520 out_attr[Tag_ABI_HardFP_use].i
14521 = in_attr[Tag_ABI_HardFP_use].i;
14522 break;
14523 }
14524 /* If the input has no requirement about FP hardware, do
14525 nothing. */
14526 else if (in_attr[i].i == 0)
14527 {
4ec192e6
RE		 14528 /* We used to assert that Tag_ABI_HardFP_use was
14529 zero here, but we should never assert when
14530 consuming an object file that has suspicious
14531 build attributes. The single precision variant
14532 of 'no FP architecture' is still 'no FP
14533 architecture', so we just ignore the tag in this
14534 case. */
4547cb56
NC		 14535 break;
14536 }
14537
14538 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 14539 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 14540
14541 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14542 do nothing. */
14543 if (in_attr[Tag_ABI_HardFP_use].i == 0
14544 && out_attr[Tag_ABI_HardFP_use].i == 0)
14545 ;
14546 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 14547 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 14548 else if (in_attr[Tag_ABI_HardFP_use].i
14549 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 14550 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 14551
14552 /* Now we can handle Tag_FP_arch. */
14553
bca38921
MGD		 14554 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14555 pick the biggest. */
14556 if (in_attr[i].i >= VFP_VERSION_COUNT
14557 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 14558 {
14559 out_attr[i] = in_attr[i];
14560 break;
14561 }
14562 /* The output uses the superset of input features
14563 (ISA version) and registers. */
14564 ver = vfp_versions[in_attr[i].i].ver;
14565 if (ver < vfp_versions[out_attr[i].i].ver)
14566 ver = vfp_versions[out_attr[i].i].ver;
14567 regs = vfp_versions[in_attr[i].i].regs;
14568 if (regs < vfp_versions[out_attr[i].i].regs)
14569 regs = vfp_versions[out_attr[i].i].regs;
14570 /* This assumes all possible supersets are also a valid
99059e56 14571 options. */
bca38921 14572 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 14573 {
14574 if (regs == vfp_versions[newval].regs
14575 && ver == vfp_versions[newval].ver)
14576 break;
14577 }
14578 out_attr[i].i = newval;
14579 }
b1cc4aeb 14580 break;
ee065d83
PB		 14581 case Tag_PCS_config:
14582 if (out_attr[i].i == 0)
14583 out_attr[i].i = in_attr[i].i;
b6009aca 14584 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14585 {
14586 /* It's sometimes ok to mix different configs, so this is only
99059e56 14587 a warning. */
ee065d83 14588 _bfd_error_handler
90b6238f 14589 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14590 }
14591 break;
14592 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14593 if (in_attr[i].i != out_attr[i].i
14594 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14595 && in_attr[i].i != AEABI_R9_unused)
14596 {
14597 _bfd_error_handler
90b6238f 14598 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14599 result = FALSE;
ee065d83
PB		 14600 }
14601 if (out_attr[i].i == AEABI_R9_unused)
14602 out_attr[i].i = in_attr[i].i;
14603 break;
14604 case Tag_ABI_PCS_RW_data:
14605 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14606 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14607 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14608 {
14609 _bfd_error_handler
871b3ab2 14610 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14611 ibfd);
91e22acd 14612 result = FALSE;
ee065d83
PB		 14613 }
14614 /* Use the smallest value specified. */
14615 if (in_attr[i].i < out_attr[i].i)
14616 out_attr[i].i = in_attr[i].i;
14617 break;
ee065d83 14618 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14619 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14620 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14621 {
14622 _bfd_error_handler
871b3ab2 14623 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14624 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14625 }
a9dc9481 14626 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14627 out_attr[i].i = in_attr[i].i;
14628 break;
ee065d83
PB		 14629 case Tag_ABI_enum_size:
14630 if (in_attr[i].i != AEABI_enum_unused)
14631 {
14632 if (out_attr[i].i == AEABI_enum_unused
14633 || out_attr[i].i == AEABI_enum_forced_wide)
14634 {
14635 /* The existing object is compatible with anything.
14636 Use whatever requirements the new object has. */
14637 out_attr[i].i = in_attr[i].i;
14638 }
14639 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14640 && out_attr[i].i != in_attr[i].i
0ffa91dd 14641 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14642 {
91e22acd 14643 static const char *aeabi_enum_names[] =
bf21ed78 14644 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14645 const char *in_name =
14646 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14647 ? aeabi_enum_names[in_attr[i].i]
14648 : "<unknown>";
14649 const char *out_name =
14650 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14651 ? aeabi_enum_names[out_attr[i].i]
14652 : "<unknown>";
ee065d83 14653 _bfd_error_handler
871b3ab2 14654 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14655 ibfd, in_name, out_name);
ee065d83
PB		 14656 }
14657 }
14658 break;
14659 case Tag_ABI_VFP_args:
14660 /* Aready done. */
14661 break;
14662 case Tag_ABI_WMMX_args:
14663 if (in_attr[i].i != out_attr[i].i)
14664 {
14665 _bfd_error_handler
871b3ab2 14666 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14667 ibfd, obfd);
91e22acd 14668 result = FALSE;
ee065d83
PB		 14669 }
14670 break;
7b86a9fa
AS		 14671 case Tag_compatibility:
14672 /* Merged in target-independent code. */
14673 break;
91e22acd 14674 case Tag_ABI_HardFP_use:
4547cb56 14675 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14676 break;
14677 case Tag_ABI_FP_16bit_format:
14678 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14679 {
14680 if (in_attr[i].i != out_attr[i].i)
14681 {
14682 _bfd_error_handler
871b3ab2 14683 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 14684 ibfd, obfd);
14685 result = FALSE;
14686 }
14687 }
14688 if (in_attr[i].i != 0)
14689 out_attr[i].i = in_attr[i].i;
14690 break;
7b86a9fa 14691
cd21e546 14692 case Tag_DIV_use:
ac56ee8f
MGD		 14693 /* A value of zero on input means that the divide instruction may
14694 be used if available in the base architecture as specified via
14695 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14696 the user did not want divide instructions. A value of 2
14697 explicitly means that divide instructions were allowed in ARM
14698 and Thumb state. */
14699 if (in_attr[i].i == out_attr[i].i)
14700 /* Do nothing. */ ;
14701 else if (elf32_arm_attributes_forbid_div (in_attr)
14702 && !elf32_arm_attributes_accept_div (out_attr))
14703 out_attr[i].i = 1;
14704 else if (elf32_arm_attributes_forbid_div (out_attr)
14705 && elf32_arm_attributes_accept_div (in_attr))
14706 out_attr[i].i = in_attr[i].i;
14707 else if (in_attr[i].i == 2)
14708 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14709 break;
14710
14711 case Tag_MPextension_use_legacy:
14712 /* We don't output objects with Tag_MPextension_use_legacy - we
14713 move the value to Tag_MPextension_use. */
14714 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14715 {
14716 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14717 {
14718 _bfd_error_handler
871b3ab2 14719 (_("%pB has both the current and legacy "
b38cadfb 14720 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14721 ibfd);
14722 result = FALSE;
14723 }
14724 }
14725
14726 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14727 out_attr[Tag_MPextension_use] = in_attr[i];
14728
14729 break;
14730
91e22acd 14731 case Tag_nodefaults:
2d0bb761
AS		 14732 /* This tag is set if it exists, but the value is unused (and is
14733 typically zero). We don't actually need to do anything here -
14734 the merge happens automatically when the type flags are merged
14735 below. */
91e22acd
AS		 14736 break;
14737 case Tag_also_compatible_with:
14738 /* Already done in Tag_CPU_arch. */
14739 break;
14740 case Tag_conformance:
14741 /* Keep the attribute if it matches. Throw it away otherwise.
14742 No attribute means no claim to conform. */
14743 if (!in_attr[i].s || !out_attr[i].s
14744 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
14745 out_attr[i].s = NULL;
14746 break;
3cfad14c 14747
91e22acd 14748 default:
e8b36cd1
JM		 14749 result
14750 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 14751 }
14752
14753 /* If out_attr was copied from in_attr then it won't have a type yet. */
14754 if (in_attr[i].type && !out_attr[i].type)
14755 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 14756 }
14757
104d59d1 14758 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 14759 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 14760 return FALSE;
ee065d83 14761
104d59d1 14762 /* Check for any attributes not known on ARM. */
e8b36cd1 14763 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 14764
91e22acd 14765 return result;
252b5132
RH		 14766}
14767
3a4a14e9
PB		 14768
14769/* Return TRUE if the two EABI versions are incompatible. */
14770
14771static bfd_boolean
14772elf32_arm_versions_compatible (unsigned iver, unsigned over)
14773{
14774 /* v4 and v5 are the same spec before and after it was released,
14775 so allow mixing them. */
14776 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
14777 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
14778 return TRUE;
14779
14780 return (iver == over);
14781}
14782
252b5132
RH		 14783/* Merge backend specific data from an object file to the output
14784 object file when linking. */
9b485d32 14785
b34976b6 14786static bfd_boolean
50e03d47 14787elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 14788
9b485d32
NC		 14789/* Display the flags field. */
14790
b34976b6 14791static bfd_boolean
57e8b36a 14792elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 14793{
fc830a83
NC		 14794 FILE * file = (FILE *) ptr;
14795 unsigned long flags;
252b5132
RH		 14796
14797 BFD_ASSERT (abfd != NULL && ptr != NULL);
14798
14799 /* Print normal ELF private data. */
14800 _bfd_elf_print_private_bfd_data (abfd, ptr);
14801
fc830a83 14802 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 14803 /* Ignore init flag - it may not be set, despite the flags field
14804 containing valid data. */
252b5132 14805
9b485d32 14806 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 14807
fc830a83
NC		 14808 switch (EF_ARM_EABI_VERSION (flags))
14809 {
14810 case EF_ARM_EABI_UNKNOWN:
4cc11e76 14811 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 14812 official ARM ELF extended ABI. Hence they are only decoded if
14813 the EABI version is not set. */
fd2ec330 14814 if (flags & EF_ARM_INTERWORK)
9b485d32 14815 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 14816
fd2ec330 14817 if (flags & EF_ARM_APCS_26)
6c571f00 14818 fprintf (file, " [APCS-26]");
fc830a83 14819 else
6c571f00 14820 fprintf (file, " [APCS-32]");
9a5aca8c 14821
96a846ea
RE		 14822 if (flags & EF_ARM_VFP_FLOAT)
14823 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 14824 else if (flags & EF_ARM_MAVERICK_FLOAT)
14825 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 14826 else
14827 fprintf (file, _(" [FPA float format]"));
14828
fd2ec330 14829 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 14830 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 14831
fd2ec330 14832 if (flags & EF_ARM_PIC)
9b485d32 14833 fprintf (file, _(" [position independent]"));
fc830a83 14834
fd2ec330 14835 if (flags & EF_ARM_NEW_ABI)
9b485d32 14836 fprintf (file, _(" [new ABI]"));
9a5aca8c 14837
fd2ec330 14838 if (flags & EF_ARM_OLD_ABI)
9b485d32 14839 fprintf (file, _(" [old ABI]"));
9a5aca8c 14840
fd2ec330 14841 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 14842 fprintf (file, _(" [software FP]"));
9a5aca8c 14843
96a846ea
RE		 14844 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
14845 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 14846 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
14847 | EF_ARM_MAVERICK_FLOAT);
fc830a83 14848 break;
9a5aca8c 14849
fc830a83 14850 case EF_ARM_EABI_VER1:
9b485d32 14851 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 14852
fc830a83 14853 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 14854 fprintf (file, _(" [sorted symbol table]"));
fc830a83 14855 else
9b485d32 14856 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 14857
fc830a83
NC		 14858 flags &= ~ EF_ARM_SYMSARESORTED;
14859 break;
9a5aca8c 14860
fd2ec330
PB		 14861 case EF_ARM_EABI_VER2:
14862 fprintf (file, _(" [Version2 EABI]"));
14863
14864 if (flags & EF_ARM_SYMSARESORTED)
14865 fprintf (file, _(" [sorted symbol table]"));
14866 else
14867 fprintf (file, _(" [unsorted symbol table]"));
14868
14869 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
14870 fprintf (file, _(" [dynamic symbols use segment index]"));
14871
14872 if (flags & EF_ARM_MAPSYMSFIRST)
14873 fprintf (file, _(" [mapping symbols precede others]"));
14874
99e4ae17 14875 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 14876 | EF_ARM_MAPSYMSFIRST);
14877 break;
14878
d507cf36
PB		 14879 case EF_ARM_EABI_VER3:
14880 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 14881 break;
14882
14883 case EF_ARM_EABI_VER4:
14884 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 14885 goto eabi;
d507cf36 14886
3a4a14e9
PB		 14887 case EF_ARM_EABI_VER5:
14888 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 14889
14890 if (flags & EF_ARM_ABI_FLOAT_SOFT)
14891 fprintf (file, _(" [soft-float ABI]"));
14892
14893 if (flags & EF_ARM_ABI_FLOAT_HARD)
14894 fprintf (file, _(" [hard-float ABI]"));
14895
14896 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
14897
3a4a14e9 14898 eabi:
d507cf36
PB		 14899 if (flags & EF_ARM_BE8)
14900 fprintf (file, _(" [BE8]"));
14901
14902 if (flags & EF_ARM_LE8)
14903 fprintf (file, _(" [LE8]"));
14904
14905 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
14906 break;
14907
fc830a83 14908 default:
9b485d32 14909 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 14910 break;
14911 }
252b5132 14912
fc830a83 14913 flags &= ~ EF_ARM_EABIMASK;
252b5132 14914
fc830a83 14915 if (flags & EF_ARM_RELEXEC)
9b485d32 14916 fprintf (file, _(" [relocatable executable]"));
252b5132 14917
18a20338
CL		 14918 if (flags & EF_ARM_PIC)
14919 fprintf (file, _(" [position independent]"));
14920
14921 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
14922 fprintf (file, _(" [FDPIC ABI supplement]"));
14923
14924 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 14925
14926 if (flags)
9b485d32 14927 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 14928
252b5132
RH		 14929 fputc ('\n', file);
14930
b34976b6 14931 return TRUE;
252b5132
RH		 14932}
14933
14934static int
57e8b36a 14935elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 14936{
2f0ca46a
NC		 14937 switch (ELF_ST_TYPE (elf_sym->st_info))
14938 {
14939 case STT_ARM_TFUNC:
14940 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 14941
2f0ca46a
NC		 14942 case STT_ARM_16BIT:
14943 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
14944 This allows us to distinguish between data used by Thumb instructions
14945 and non-data (which is probably code) inside Thumb regions of an
14946 executable. */
1a0eb693 14947 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 14948 return ELF_ST_TYPE (elf_sym->st_info);
14949 break;
9a5aca8c 14950
ce855c42
NC		 14951 default:
14952 break;
2f0ca46a
NC		 14953 }
14954
14955 return type;
252b5132 14956}
f21f3fe0 14957
252b5132 14958static asection *
07adf181
AM		 14959elf32_arm_gc_mark_hook (asection *sec,
14960 struct bfd_link_info *info,
14961 Elf_Internal_Rela *rel,
14962 struct elf_link_hash_entry *h,
14963 Elf_Internal_Sym *sym)
252b5132
RH		 14964{
14965 if (h != NULL)
07adf181 14966 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 14967 {
14968 case R_ARM_GNU_VTINHERIT:
14969 case R_ARM_GNU_VTENTRY:
07adf181
AM		 14970 return NULL;
14971 }
9ad5cbcf 14972
07adf181 14973 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 14974}
14975
780a67af
NC		 14976/* Look through the relocs for a section during the first phase. */
14977
b34976b6 14978static bfd_boolean
57e8b36a
NC		 14979elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
14980 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 14981{
b34976b6
AM		 14982 Elf_Internal_Shdr *symtab_hdr;
14983 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 14984 const Elf_Internal_Rela *rel;
14985 const Elf_Internal_Rela *rel_end;
14986 bfd *dynobj;
5e681ec4 14987 asection *sreloc;
5e681ec4 14988 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 14989 bfd_boolean call_reloc_p;
14990 bfd_boolean may_become_dynamic_p;
14991 bfd_boolean may_need_local_target_p;
ce98a316 14992 unsigned long nsyms;
9a5aca8c 14993
0e1862bb 14994 if (bfd_link_relocatable (info))
b34976b6 14995 return TRUE;
9a5aca8c 14996
0ffa91dd
NC		 14997 BFD_ASSERT (is_arm_elf (abfd));
14998
5e681ec4 14999 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15000 if (htab == NULL)
15001 return FALSE;
15002
5e681ec4 15003 sreloc = NULL;
9a5aca8c 15004
67687978
PB		 15005 /* Create dynamic sections for relocatable executables so that we can
15006 copy relocations. */
15007 if (htab->root.is_relocatable_executable
15008 && ! htab->root.dynamic_sections_created)
15009 {
15010 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15011 return FALSE;
15012 }
15013
cbc704f3
RS		 15014 if (htab->root.dynobj == NULL)
15015 htab->root.dynobj = abfd;
34e77a92
RS		 15016 if (!create_ifunc_sections (info))
15017 return FALSE;
cbc704f3
RS		 15018
15019 dynobj = htab->root.dynobj;
15020
0ffa91dd 15021 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 15022 sym_hashes = elf_sym_hashes (abfd);
ce98a316 15023 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 15024
252b5132
RH		 15025 rel_end = relocs + sec->reloc_count;
15026 for (rel = relocs; rel < rel_end; rel++)
15027 {
34e77a92 15028 Elf_Internal_Sym *isym;
252b5132 15029 struct elf_link_hash_entry *h;
b7693d02 15030 struct elf32_arm_link_hash_entry *eh;
d42c267e 15031 unsigned int r_symndx;
eb043451 15032 int r_type;
9a5aca8c 15033
252b5132 15034 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 15035 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 15036 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 15037
ce98a316
NC		 15038 if (r_symndx >= nsyms
15039 /* PR 9934: It is possible to have relocations that do not
15040 refer to symbols, thus it is also possible to have an
15041 object file containing relocations but no symbol table. */
cf35638d 15042 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 15043 {
871b3ab2 15044 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 15045 r_symndx);
ba93b8ac
DJ		 15046 return FALSE;
15047 }
15048
34e77a92
RS		 15049 h = NULL;
15050 isym = NULL;
15051 if (nsyms > 0)
973a3492 15052 {
34e77a92
RS		 15053 if (r_symndx < symtab_hdr->sh_info)
15054 {
15055 /* A local symbol. */
15056 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
15057 abfd, r_symndx);
15058 if (isym == NULL)
15059 return FALSE;
15060 }
15061 else
15062 {
15063 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15064 while (h->root.type == bfd_link_hash_indirect
15065 || h->root.type == bfd_link_hash_warning)
15066 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15067 }
973a3492 15068 }
9a5aca8c 15069
b7693d02
DJ		 15070 eh = (struct elf32_arm_link_hash_entry *) h;
15071
f6e32f6d
RS		 15072 call_reloc_p = FALSE;
15073 may_become_dynamic_p = FALSE;
15074 may_need_local_target_p = FALSE;
15075
0855e32b
NS		 15076 /* Could be done earlier, if h were already available. */
15077 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 15078 switch (r_type)
99059e56 15079 {
e8b09b87
CL		 15080 case R_ARM_GOTOFFFUNCDESC:
15081 {
15082 if (h == NULL)
15083 {
15084 if (!elf32_arm_allocate_local_sym_info (abfd))
15085 return FALSE;
15086 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].gotofffuncdesc_cnt += 1;
15087 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15088 }
15089 else
15090 {
15091 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15092 }
15093 }
15094 break;
15095
15096 case R_ARM_GOTFUNCDESC:
15097 {
15098 if (h == NULL)
15099 {
15100 /* Such a relocation is not supposed to be generated
15101 by gcc on a static function. */
15102 /* Anyway if needed it could be handled. */
15103 abort();
15104 }
15105 else
15106 {
15107 eh->fdpic_cnts.gotfuncdesc_cnt++;
15108 }
15109 }
15110 break;
15111
15112 case R_ARM_FUNCDESC:
15113 {
15114 if (h == NULL)
15115 {
15116 if (!elf32_arm_allocate_local_sym_info (abfd))
15117 return FALSE;
15118 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_cnt += 1;
15119 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15120 }
15121 else
15122 {
15123 eh->fdpic_cnts.funcdesc_cnt++;
15124 }
15125 }
15126 break;
15127
5e681ec4 15128 case R_ARM_GOT32:
eb043451 15129 case R_ARM_GOT_PREL:
ba93b8ac 15130 case R_ARM_TLS_GD32:
5c5a4843 15131 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 15132 case R_ARM_TLS_IE32:
5c5a4843 15133 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 15134 case R_ARM_TLS_GOTDESC:
15135 case R_ARM_TLS_DESCSEQ:
15136 case R_ARM_THM_TLS_DESCSEQ:
15137 case R_ARM_TLS_CALL:
15138 case R_ARM_THM_TLS_CALL:
5e681ec4 15139 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 15140 {
15141 int tls_type, old_tls_type;
5e681ec4 15142
ba93b8ac
DJ		 15143 switch (r_type)
15144 {
15145 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
5c5a4843 15146 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
b38cadfb 15147
ba93b8ac 15148 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
5c5a4843 15149 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
b38cadfb 15150
0855e32b
NS		 15151 case R_ARM_TLS_GOTDESC:
15152 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15153 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15154 tls_type = GOT_TLS_GDESC; break;
b38cadfb 15155
ba93b8ac
DJ		 15156 default: tls_type = GOT_NORMAL; break;
15157 }
252b5132 15158
0e1862bb 15159 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 15160 info->flags |= DF_STATIC_TLS;
15161
ba93b8ac
DJ		 15162 if (h != NULL)
15163 {
15164 h->got.refcount++;
15165 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15166 }
15167 else
15168 {
ba93b8ac 15169 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 15170 if (!elf32_arm_allocate_local_sym_info (abfd))
15171 return FALSE;
15172 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 15173 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15174 }
15175
0855e32b 15176 /* If a variable is accessed with both tls methods, two
99059e56 15177 slots may be created. */
0855e32b
NS		 15178 if (GOT_TLS_GD_ANY_P (old_tls_type)
15179 && GOT_TLS_GD_ANY_P (tls_type))
15180 tls_type |= old_tls_type;
15181
15182 /* We will already have issued an error message if there
15183 is a TLS/non-TLS mismatch, based on the symbol
15184 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 15185 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15186 && tls_type != GOT_NORMAL)
15187 tls_type |= old_tls_type;
15188
0855e32b 15189 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 15190 method, we're able to relax. Turn off the GDESC flag,
15191 without messing up with any other kind of tls types
6a631e86 15192 that may be involved. */
0855e32b
NS		 15193 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15194 tls_type &= ~GOT_TLS_GDESC;
15195
ba93b8ac
DJ		 15196 if (old_tls_type != tls_type)
15197 {
15198 if (h != NULL)
15199 elf32_arm_hash_entry (h)->tls_type = tls_type;
15200 else
15201 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15202 }
15203 }
8029a119 15204 /* Fall through. */
ba93b8ac
DJ		 15205
15206 case R_ARM_TLS_LDM32:
5c5a4843
CL		 15207 case R_ARM_TLS_LDM32_FDPIC:
15208 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
ba93b8ac 15209 htab->tls_ldm_got.refcount++;
8029a119 15210 /* Fall through. */
252b5132 15211
c19d1205 15212 case R_ARM_GOTOFF32:
5e681ec4 15213 case R_ARM_GOTPC:
cbc704f3
RS		 15214 if (htab->root.sgot == NULL
15215 && !create_got_section (htab->root.dynobj, info))
15216 return FALSE;
252b5132
RH		 15217 break;
15218
252b5132 15219 case R_ARM_PC24:
7359ea65 15220 case R_ARM_PLT32:
5b5bb741
PB		 15221 case R_ARM_CALL:
15222 case R_ARM_JUMP24:
eb043451 15223 case R_ARM_PREL31:
c19d1205 15224 case R_ARM_THM_CALL:
bd97cb95
DJ		 15225 case R_ARM_THM_JUMP24:
15226 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 15227 call_reloc_p = TRUE;
15228 may_need_local_target_p = TRUE;
15229 break;
15230
15231 case R_ARM_ABS12:
15232 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15233 ldr __GOTT_INDEX__ offsets. */
15234 if (!htab->vxworks_p)
15235 {
15236 may_need_local_target_p = TRUE;
15237 break;
15238 }
aebf9be7 15239 else goto jump_over;
9eaff861 15240
f6e32f6d 15241 /* Fall through. */
39623e12 15242
96c23d59
JM		 15243 case R_ARM_MOVW_ABS_NC:
15244 case R_ARM_MOVT_ABS:
15245 case R_ARM_THM_MOVW_ABS_NC:
15246 case R_ARM_THM_MOVT_ABS:
0e1862bb 15247 if (bfd_link_pic (info))
96c23d59 15248 {
4eca0228 15249 _bfd_error_handler
871b3ab2 15250 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 15251 abfd, elf32_arm_howto_table_1[r_type].name,
15252 (h) ? h->root.root.string : "a local symbol");
15253 bfd_set_error (bfd_error_bad_value);
15254 return FALSE;
15255 }
15256
15257 /* Fall through. */
39623e12
PB		 15258 case R_ARM_ABS32:
15259 case R_ARM_ABS32_NOI:
aebf9be7 15260 jump_over:
0e1862bb 15261 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 15262 {
15263 h->pointer_equality_needed = 1;
15264 }
15265 /* Fall through. */
39623e12
PB		 15266 case R_ARM_REL32:
15267 case R_ARM_REL32_NOI:
b6895b4f
PB		 15268 case R_ARM_MOVW_PREL_NC:
15269 case R_ARM_MOVT_PREL:
b6895b4f
PB		 15270 case R_ARM_THM_MOVW_PREL_NC:
15271 case R_ARM_THM_MOVT_PREL:
39623e12 15272
b7693d02 15273 /* Should the interworking branches be listed here? */
e8b09b87
CL		 15274 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15275 || htab->fdpic_p)
34e77a92
RS		 15276 && (sec->flags & SEC_ALLOC) != 0)
15277 {
15278 if (h == NULL
469a3493 15279 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 15280 {
15281 /* In shared libraries and relocatable executables,
15282 we treat local relative references as calls;
15283 see the related SYMBOL_CALLS_LOCAL code in
15284 allocate_dynrelocs. */
15285 call_reloc_p = TRUE;
15286 may_need_local_target_p = TRUE;
15287 }
15288 else
15289 /* We are creating a shared library or relocatable
15290 executable, and this is a reloc against a global symbol,
15291 or a non-PC-relative reloc against a local symbol.
15292 We may need to copy the reloc into the output. */
15293 may_become_dynamic_p = TRUE;
15294 }
f6e32f6d
RS		 15295 else
15296 may_need_local_target_p = TRUE;
252b5132
RH		 15297 break;
15298
99059e56
RM		 15299 /* This relocation describes the C++ object vtable hierarchy.
15300 Reconstruct it for later use during GC. */
15301 case R_ARM_GNU_VTINHERIT:
15302 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15303 return FALSE;
15304 break;
15305
15306 /* This relocation describes which C++ vtable entries are actually
15307 used. Record for later use during GC. */
15308 case R_ARM_GNU_VTENTRY:
15309 BFD_ASSERT (h != NULL);
15310 if (h != NULL
15311 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
15312 return FALSE;
15313 break;
15314 }
f6e32f6d
RS		 15315
15316 if (h != NULL)
15317 {
15318 if (call_reloc_p)
15319 /* We may need a .plt entry if the function this reloc
15320 refers to is in a different object, regardless of the
15321 symbol's type. We can't tell for sure yet, because
15322 something later might force the symbol local. */
15323 h->needs_plt = 1;
15324 else if (may_need_local_target_p)
15325 /* If this reloc is in a read-only section, we might
15326 need a copy reloc. We can't check reliably at this
15327 stage whether the section is read-only, as input
15328 sections have not yet been mapped to output sections.
15329 Tentatively set the flag for now, and correct in
15330 adjust_dynamic_symbol. */
15331 h->non_got_ref = 1;
15332 }
15333
34e77a92
RS		 15334 if (may_need_local_target_p
15335 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 15336 {
34e77a92
RS		 15337 union gotplt_union *root_plt;
15338 struct arm_plt_info *arm_plt;
15339 struct arm_local_iplt_info *local_iplt;
15340
15341 if (h != NULL)
15342 {
15343 root_plt = &h->plt;
15344 arm_plt = &eh->plt;
15345 }
15346 else
15347 {
15348 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15349 if (local_iplt == NULL)
15350 return FALSE;
15351 root_plt = &local_iplt->root;
15352 arm_plt = &local_iplt->arm;
15353 }
15354
f6e32f6d
RS		 15355 /* If the symbol is a function that doesn't bind locally,
15356 this relocation will need a PLT entry. */
a8c887dd
NC		 15357 if (root_plt->refcount != -1)
15358 root_plt->refcount += 1;
34e77a92
RS		 15359
15360 if (!call_reloc_p)
15361 arm_plt->noncall_refcount++;
f6e32f6d
RS		 15362
15363 /* It's too early to use htab->use_blx here, so we have to
15364 record possible blx references separately from
15365 relocs that definitely need a thumb stub. */
15366
15367 if (r_type == R_ARM_THM_CALL)
34e77a92 15368 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 15369
15370 if (r_type == R_ARM_THM_JUMP24
15371 || r_type == R_ARM_THM_JUMP19)
34e77a92 15372 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 15373 }
15374
15375 if (may_become_dynamic_p)
15376 {
15377 struct elf_dyn_relocs *p, **head;
15378
15379 /* Create a reloc section in dynobj. */
15380 if (sreloc == NULL)
15381 {
15382 sreloc = _bfd_elf_make_dynamic_reloc_section
15383 (sec, dynobj, 2, abfd, ! htab->use_rel);
15384
15385 if (sreloc == NULL)
15386 return FALSE;
15387
15388 /* BPABI objects never have dynamic relocations mapped. */
15389 if (htab->symbian_p)
15390 {
15391 flagword flags;
15392
15393 flags = bfd_get_section_flags (dynobj, sreloc);
15394 flags &= ~(SEC_LOAD | SEC_ALLOC);
15395 bfd_set_section_flags (dynobj, sreloc, flags);
15396 }
15397 }
15398
15399 /* If this is a global symbol, count the number of
15400 relocations we need for this symbol. */
15401 if (h != NULL)
15402 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
15403 else
15404 {
34e77a92
RS		 15405 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15406 if (head == NULL)
f6e32f6d 15407 return FALSE;
f6e32f6d
RS		 15408 }
15409
15410 p = *head;
15411 if (p == NULL || p->sec != sec)
15412 {
15413 bfd_size_type amt = sizeof *p;
15414
15415 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15416 if (p == NULL)
15417 return FALSE;
15418 p->next = *head;
15419 *head = p;
15420 p->sec = sec;
15421 p->count = 0;
15422 p->pc_count = 0;
15423 }
15424
469a3493 15425 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 15426 p->pc_count += 1;
15427 p->count += 1;
e8b09b87
CL		 15428 if (h == NULL && htab->fdpic_p && !bfd_link_pic(info)
15429 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI) {
15430 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15431 that will become rofixup. */
15432 /* This is due to the fact that we suppose all will become rofixup. */
15433 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15434 _bfd_error_handler
15435 (_("FDPIC does not yet support %s relocation"
15436 " to become dynamic for executable"),
15437 elf32_arm_howto_table_1[r_type].name);
15438 abort();
15439 }
f6e32f6d 15440 }
252b5132 15441 }
f21f3fe0 15442
b34976b6 15443 return TRUE;
252b5132
RH		 15444}
15445
9eaff861
AO		 15446static void
15447elf32_arm_update_relocs (asection *o,
15448 struct bfd_elf_section_reloc_data *reldata)
15449{
15450 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15451 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15452 const struct elf_backend_data *bed;
15453 _arm_elf_section_data *eado;
15454 struct bfd_link_order *p;
15455 bfd_byte *erela_head, *erela;
15456 Elf_Internal_Rela *irela_head, *irela;
15457 Elf_Internal_Shdr *rel_hdr;
15458 bfd *abfd;
15459 unsigned int count;
15460
15461 eado = get_arm_elf_section_data (o);
15462
15463 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15464 return;
15465
15466 abfd = o->owner;
15467 bed = get_elf_backend_data (abfd);
15468 rel_hdr = reldata->hdr;
15469
15470 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15471 {
15472 swap_in = bed->s->swap_reloc_in;
15473 swap_out = bed->s->swap_reloc_out;
15474 }
15475 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15476 {
15477 swap_in = bed->s->swap_reloca_in;
15478 swap_out = bed->s->swap_reloca_out;
15479 }
15480 else
15481 abort ();
15482
15483 erela_head = rel_hdr->contents;
15484 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15485 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15486
15487 erela = erela_head;
15488 irela = irela_head;
15489 count = 0;
15490
15491 for (p = o->map_head.link_order; p; p = p->next)
15492 {
15493 if (p->type == bfd_section_reloc_link_order
15494 || p->type == bfd_symbol_reloc_link_order)
15495 {
15496 (*swap_in) (abfd, erela, irela);
15497 erela += rel_hdr->sh_entsize;
15498 irela++;
15499 count++;
15500 }
15501 else if (p->type == bfd_indirect_link_order)
15502 {
15503 struct bfd_elf_section_reloc_data *input_reldata;
15504 arm_unwind_table_edit *edit_list, *edit_tail;
15505 _arm_elf_section_data *eadi;
15506 bfd_size_type j;
15507 bfd_vma offset;
15508 asection *i;
15509
15510 i = p->u.indirect.section;
15511
15512 eadi = get_arm_elf_section_data (i);
15513 edit_list = eadi->u.exidx.unwind_edit_list;
15514 edit_tail = eadi->u.exidx.unwind_edit_tail;
15515 offset = o->vma + i->output_offset;
15516
15517 if (eadi->elf.rel.hdr &&
15518 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15519 input_reldata = &eadi->elf.rel;
15520 else if (eadi->elf.rela.hdr &&
15521 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15522 input_reldata = &eadi->elf.rela;
15523 else
15524 abort ();
15525
15526 if (edit_list)
15527 {
15528 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15529 {
15530 arm_unwind_table_edit *edit_node, *edit_next;
15531 bfd_vma bias;
c48182bf 15532 bfd_vma reloc_index;
9eaff861
AO		 15533
15534 (*swap_in) (abfd, erela, irela);
c48182bf 15535 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 15536
15537 bias = 0;
15538 edit_node = edit_list;
15539 for (edit_next = edit_list;
c48182bf 15540 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 15541 edit_next = edit_node->next)
15542 {
15543 bias++;
15544 edit_node = edit_next;
15545 }
15546
15547 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 15548 || edit_node->index != reloc_index)
9eaff861
AO		 15549 {
15550 irela->r_offset -= bias * 8;
15551 irela++;
15552 count++;
15553 }
15554
15555 erela += rel_hdr->sh_entsize;
15556 }
15557
15558 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15559 {
15560 /* New relocation entity. */
15561 asection *text_sec = edit_tail->linked_section;
15562 asection *text_out = text_sec->output_section;
15563 bfd_vma exidx_offset = offset + i->size - 8;
15564
15565 irela->r_addend = 0;
15566 irela->r_offset = exidx_offset;
15567 irela->r_info = ELF32_R_INFO
15568 (text_out->target_index, R_ARM_PREL31);
15569 irela++;
15570 count++;
15571 }
15572 }
15573 else
15574 {
15575 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15576 {
15577 (*swap_in) (abfd, erela, irela);
15578 erela += rel_hdr->sh_entsize;
15579 irela++;
15580 }
15581
15582 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15583 }
15584 }
15585 }
15586
15587 reldata->count = count;
15588 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15589
15590 erela = erela_head;
15591 irela = irela_head;
15592 while (count > 0)
15593 {
15594 (*swap_out) (abfd, irela, erela);
15595 erela += rel_hdr->sh_entsize;
15596 irela++;
15597 count--;
15598 }
15599
15600 free (irela_head);
15601
15602 /* Hashes are no longer valid. */
15603 free (reldata->hashes);
15604 reldata->hashes = NULL;
15605}
15606
6a5bb875 15607/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15608 required if the corresponding code section is marked. Similarly, ARMv8-M
15609 secure entry functions can only be referenced by SG veneers which are
15610 created after the GC process. They need to be marked in case they reside in
15611 their own section (as would be the case if code was compiled with
15612 -ffunction-sections). */
6a5bb875
PB		 15613
15614static bfd_boolean
906e58ca
NC		 15615elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15616 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15617{
15618 bfd *sub;
15619 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15620 asection *cmse_sec;
15621 obj_attribute *out_attr;
15622 Elf_Internal_Shdr *symtab_hdr;
15623 unsigned i, sym_count, ext_start;
15624 const struct elf_backend_data *bed;
15625 struct elf_link_hash_entry **sym_hashes;
15626 struct elf32_arm_link_hash_entry *cmse_hash;
15627 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 15628
7f6ab9f8
AM		 15629 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15630
4ba2ef8f
TP		 15631 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15632 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15633 && out_attr[Tag_CPU_arch_profile].i == 'M';
15634
6a5bb875
PB		 15635 /* Marking EH data may cause additional code sections to be marked,
15636 requiring multiple passes. */
15637 again = TRUE;
15638 while (again)
15639 {
15640 again = FALSE;
c72f2fb2 15641 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15642 {
15643 asection *o;
15644
0ffa91dd 15645 if (! is_arm_elf (sub))
6a5bb875
PB		 15646 continue;
15647
15648 elf_shdrp = elf_elfsections (sub);
15649 for (o = sub->sections; o != NULL; o = o->next)
15650 {
15651 Elf_Internal_Shdr *hdr;
0ffa91dd 15652
6a5bb875 15653 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15654 if (hdr->sh_type == SHT_ARM_EXIDX
15655 && hdr->sh_link
15656 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15657 && !o->gc_mark
15658 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15659 {
15660 again = TRUE;
15661 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15662 return FALSE;
15663 }
15664 }
4ba2ef8f
TP		 15665
15666 /* Mark section holding ARMv8-M secure entry functions. We mark all
15667 of them so no need for a second browsing. */
15668 if (is_v8m && first_bfd_browse)
15669 {
15670 sym_hashes = elf_sym_hashes (sub);
15671 bed = get_elf_backend_data (sub);
15672 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15673 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15674 ext_start = symtab_hdr->sh_info;
15675
15676 /* Scan symbols. */
15677 for (i = ext_start; i < sym_count; i++)
15678 {
15679 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15680
15681 /* Assume it is a special symbol. If not, cmse_scan will
15682 warn about it and user can do something about it. */
15683 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
15684 {
15685 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15686 if (!cmse_sec->gc_mark
15687 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f
TP		 15688 return FALSE;
15689 }
15690 }
15691 }
6a5bb875 15692 }
4ba2ef8f 15693 first_bfd_browse = FALSE;
6a5bb875
PB		 15694 }
15695
15696 return TRUE;
15697}
15698
3c9458e9
NC		 15699/* Treat mapping symbols as special target symbols. */
15700
15701static bfd_boolean
15702elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
15703{
b0796911
PB		 15704 return bfd_is_arm_special_symbol_name (sym->name,
15705 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 15706}
15707
0367ecfb
NC		 15708/* This is a copy of elf_find_function() from elf.c except that
15709 ARM mapping symbols are ignored when looking for function names
15710 and STT_ARM_TFUNC is considered to a function type. */
252b5132 15711
0367ecfb 15712static bfd_boolean
07d6d2b8 15713arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 15714 asymbol ** symbols,
fb167eb2 15715 asection * section,
07d6d2b8 15716 bfd_vma offset,
0367ecfb
NC		 15717 const char ** filename_ptr,
15718 const char ** functionname_ptr)
15719{
15720 const char * filename = NULL;
15721 asymbol * func = NULL;
15722 bfd_vma low_func = 0;
15723 asymbol ** p;
252b5132
RH		 15724
15725 for (p = symbols; *p != NULL; p++)
15726 {
15727 elf_symbol_type *q;
15728
15729 q = (elf_symbol_type *) *p;
15730
252b5132
RH		 15731 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
15732 {
15733 default:
15734 break;
15735 case STT_FILE:
15736 filename = bfd_asymbol_name (&q->symbol);
15737 break;
252b5132
RH		 15738 case STT_FUNC:
15739 case STT_ARM_TFUNC:
9d2da7ca 15740 case STT_NOTYPE:
b0796911 15741 /* Skip mapping symbols. */
0367ecfb 15742 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 15743 && bfd_is_arm_special_symbol_name (q->symbol.name,
15744 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 15745 continue;
15746 /* Fall through. */
6b40fcba 15747 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 15748 && q->symbol.value >= low_func
15749 && q->symbol.value <= offset)
15750 {
15751 func = (asymbol *) q;
15752 low_func = q->symbol.value;
15753 }
15754 break;
15755 }
15756 }
15757
15758 if (func == NULL)
b34976b6 15759 return FALSE;
252b5132 15760
0367ecfb
NC		 15761 if (filename_ptr)
15762 *filename_ptr = filename;
15763 if (functionname_ptr)
15764 *functionname_ptr = bfd_asymbol_name (func);
15765
15766 return TRUE;
906e58ca 15767}
0367ecfb
NC		 15768
15769
15770/* Find the nearest line to a particular section and offset, for error
15771 reporting. This code is a duplicate of the code in elf.c, except
15772 that it uses arm_elf_find_function. */
15773
15774static bfd_boolean
07d6d2b8
AM		 15775elf32_arm_find_nearest_line (bfd * abfd,
15776 asymbol ** symbols,
15777 asection * section,
15778 bfd_vma offset,
0367ecfb
NC		 15779 const char ** filename_ptr,
15780 const char ** functionname_ptr,
fb167eb2
AM		 15781 unsigned int * line_ptr,
15782 unsigned int * discriminator_ptr)
0367ecfb
NC		 15783{
15784 bfd_boolean found = FALSE;
15785
fb167eb2 15786 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 15787 filename_ptr, functionname_ptr,
fb167eb2
AM		 15788 line_ptr, discriminator_ptr,
15789 dwarf_debug_sections, 0,
0367ecfb
NC		 15790 & elf_tdata (abfd)->dwarf2_find_line_info))
15791 {
15792 if (!*functionname_ptr)
fb167eb2 15793 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15794 *filename_ptr ? NULL : filename_ptr,
15795 functionname_ptr);
f21f3fe0 15796
0367ecfb
NC		 15797 return TRUE;
15798 }
15799
fb167eb2
AM		 15800 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15801 uses DWARF1. */
15802
0367ecfb
NC		 15803 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
15804 & found, filename_ptr,
15805 functionname_ptr, line_ptr,
15806 & elf_tdata (abfd)->line_info))
15807 return FALSE;
15808
15809 if (found && (*functionname_ptr || *line_ptr))
15810 return TRUE;
15811
15812 if (symbols == NULL)
15813 return FALSE;
15814
fb167eb2 15815 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15816 filename_ptr, functionname_ptr))
15817 return FALSE;
15818
15819 *line_ptr = 0;
b34976b6 15820 return TRUE;
252b5132
RH		 15821}
15822
4ab527b0 15823static bfd_boolean
07d6d2b8 15824elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 15825 const char ** filename_ptr,
15826 const char ** functionname_ptr,
15827 unsigned int * line_ptr)
15828{
15829 bfd_boolean found;
15830 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
15831 functionname_ptr, line_ptr,
15832 & elf_tdata (abfd)->dwarf2_find_line_info);
15833 return found;
15834}
15835
63c1f59d
AM		 15836/* Find dynamic relocs for H that apply to read-only sections. */
15837
15838static asection *
15839readonly_dynrelocs (struct elf_link_hash_entry *h)
15840{
15841 struct elf_dyn_relocs *p;
15842
15843 for (p = elf32_arm_hash_entry (h)->dyn_relocs; p != NULL; p = p->next)
15844 {
15845 asection *s = p->sec->output_section;
15846
15847 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15848 return p->sec;
15849 }
15850 return NULL;
15851}
15852
252b5132
RH		 15853/* Adjust a symbol defined by a dynamic object and referenced by a
15854 regular object. The current definition is in some section of the
15855 dynamic object, but we're not including those sections. We have to
15856 change the definition to something the rest of the link can
15857 understand. */
15858
b34976b6 15859static bfd_boolean
57e8b36a
NC		 15860elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
15861 struct elf_link_hash_entry * h)
252b5132
RH		 15862{
15863 bfd * dynobj;
5474d94f 15864 asection *s, *srel;
b7693d02 15865 struct elf32_arm_link_hash_entry * eh;
67687978 15866 struct elf32_arm_link_hash_table *globals;
252b5132 15867
67687978 15868 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15869 if (globals == NULL)
15870 return FALSE;
15871
252b5132
RH		 15872 dynobj = elf_hash_table (info)->dynobj;
15873
15874 /* Make sure we know what is going on here. */
15875 BFD_ASSERT (dynobj != NULL
f5385ebf 15876 && (h->needs_plt
34e77a92 15877 || h->type == STT_GNU_IFUNC
60d67dc8 15878 || h->is_weakalias
f5385ebf
AM		 15879 || (h->def_dynamic
15880 && h->ref_regular
15881 && !h->def_regular)));
252b5132 15882
b7693d02
DJ		 15883 eh = (struct elf32_arm_link_hash_entry *) h;
15884
252b5132
RH		 15885 /* If this is a function, put it in the procedure linkage table. We
15886 will fill in the contents of the procedure linkage table later,
15887 when we know the address of the .got section. */
34e77a92 15888 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 15889 {
34e77a92
RS		 15890 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
15891 symbol binds locally. */
5e681ec4 15892 if (h->plt.refcount <= 0
34e77a92
RS		 15893 || (h->type != STT_GNU_IFUNC
15894 && (SYMBOL_CALLS_LOCAL (info, h)
15895 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15896 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 15897 {
15898 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 15899 file, but the symbol was never referred to by a dynamic
15900 object, or if all references were garbage collected. In
15901 such a case, we don't actually need to build a procedure
15902 linkage table, and we can just do a PC24 reloc instead. */
15903 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15904 eh->plt.thumb_refcount = 0;
15905 eh->plt.maybe_thumb_refcount = 0;
15906 eh->plt.noncall_refcount = 0;
f5385ebf 15907 h->needs_plt = 0;
252b5132
RH		 15908 }
15909
b34976b6 15910 return TRUE;
252b5132 15911 }
5e681ec4 15912 else
b7693d02
DJ		 15913 {
15914 /* It's possible that we incorrectly decided a .plt reloc was
15915 needed for an R_ARM_PC24 or similar reloc to a non-function sym
15916 in check_relocs. We can't decide accurately between function
15917 and non-function syms in check-relocs; Objects loaded later in
15918 the link may change h->type. So fix it now. */
15919 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15920 eh->plt.thumb_refcount = 0;
15921 eh->plt.maybe_thumb_refcount = 0;
15922 eh->plt.noncall_refcount = 0;
b7693d02 15923 }
252b5132
RH		 15924
15925 /* If this is a weak symbol, and there is a real definition, the
15926 processor independent code will have arranged for us to see the
15927 real definition first, and we can just use the same value. */
60d67dc8 15928 if (h->is_weakalias)
252b5132 15929 {
60d67dc8
AM		 15930 struct elf_link_hash_entry *def = weakdef (h);
15931 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
15932 h->root.u.def.section = def->root.u.def.section;
15933 h->root.u.def.value = def->root.u.def.value;
b34976b6 15934 return TRUE;
252b5132
RH		 15935 }
15936
ba93b8ac
DJ		 15937 /* If there are no non-GOT references, we do not need a copy
15938 relocation. */
15939 if (!h->non_got_ref)
15940 return TRUE;
15941
252b5132
RH		 15942 /* This is a reference to a symbol defined by a dynamic object which
15943 is not a function. */
15944
15945 /* If we are creating a shared library, we must presume that the
15946 only references to the symbol are via the global offset table.
15947 For such cases we need not do anything here; the relocations will
67687978
PB		 15948 be handled correctly by relocate_section. Relocatable executables
15949 can reference data in shared objects directly, so we don't need to
15950 do anything here. */
0e1862bb 15951 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 15952 return TRUE;
252b5132
RH		 15953
15954 /* We must allocate the symbol in our .dynbss section, which will
15955 become part of the .bss section of the executable. There will be
15956 an entry for this symbol in the .dynsym section. The dynamic
15957 object will contain position independent code, so all references
15958 from the dynamic object to this symbol will go through the global
15959 offset table. The dynamic linker will use the .dynsym entry to
15960 determine the address it must put in the global offset table, so
15961 both the dynamic object and the regular object will refer to the
15962 same memory location for the variable. */
5522f910
NC		 15963 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
15964 linker to copy the initial value out of the dynamic object and into
15965 the runtime process image. We need to remember the offset into the
00a97672 15966 .rel(a).bss section we are going to use. */
5474d94f
AM		 15967 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
15968 {
15969 s = globals->root.sdynrelro;
15970 srel = globals->root.sreldynrelro;
15971 }
15972 else
15973 {
15974 s = globals->root.sdynbss;
15975 srel = globals->root.srelbss;
15976 }
5522f910
NC		 15977 if (info->nocopyreloc == 0
15978 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 15979 && h->size != 0)
252b5132 15980 {
47beaa6a 15981 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 15982 h->needs_copy = 1;
252b5132
RH		 15983 }
15984
6cabe1ea 15985 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 15986}
15987
5e681ec4
PB		 15988/* Allocate space in .plt, .got and associated reloc sections for
15989 dynamic relocs. */
15990
15991static bfd_boolean
47beaa6a 15992allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 15993{
15994 struct bfd_link_info *info;
15995 struct elf32_arm_link_hash_table *htab;
15996 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 15997 struct elf_dyn_relocs *p;
5e681ec4
PB		 15998
15999 if (h->root.type == bfd_link_hash_indirect)
16000 return TRUE;
16001
e6a6bb22
AM		 16002 eh = (struct elf32_arm_link_hash_entry *) h;
16003
5e681ec4
PB		 16004 info = (struct bfd_link_info *) inf;
16005 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16006 if (htab == NULL)
16007 return FALSE;
5e681ec4 16008
34e77a92 16009 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 16010 && h->plt.refcount > 0)
16011 {
16012 /* Make sure this symbol is output as a dynamic symbol.
16013 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16014 if (h->dynindx == -1 && !h->forced_local
16015 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16016 {
c152c796 16017 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16018 return FALSE;
16019 }
16020
34e77a92
RS		 16021 /* If the call in the PLT entry binds locally, the associated
16022 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16023 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16024 than the .plt section. */
16025 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16026 {
16027 eh->is_iplt = 1;
16028 if (eh->plt.noncall_refcount == 0
16029 && SYMBOL_REFERENCES_LOCAL (info, h))
16030 /* All non-call references can be resolved directly.
16031 This means that they can (and in some cases, must)
16032 resolve directly to the run-time target, rather than
16033 to the PLT. That in turns means that any .got entry
16034 would be equal to the .igot.plt entry, so there's
16035 no point having both. */
16036 h->got.refcount = 0;
16037 }
16038
0e1862bb 16039 if (bfd_link_pic (info)
34e77a92 16040 || eh->is_iplt
7359ea65 16041 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 16042 {
34e77a92 16043 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 16044
5e681ec4
PB		 16045 /* If this symbol is not defined in a regular file, and we are
16046 not generating a shared library, then set the symbol to this
16047 location in the .plt. This is required to make function
16048 pointers compare as equal between the normal executable and
16049 the shared library. */
0e1862bb 16050 if (! bfd_link_pic (info)
f5385ebf 16051 && !h->def_regular)
5e681ec4 16052 {
34e77a92 16053 h->root.u.def.section = htab->root.splt;
5e681ec4 16054 h->root.u.def.value = h->plt.offset;
5e681ec4 16055
67d74e43
DJ		 16056 /* Make sure the function is not marked as Thumb, in case
16057 it is the target of an ABS32 relocation, which will
16058 point to the PLT entry. */
39d911fc 16059 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 16060 }
022f8312 16061
00a97672
RS		 16062 /* VxWorks executables have a second set of relocations for
16063 each PLT entry. They go in a separate relocation section,
16064 which is processed by the kernel loader. */
0e1862bb 16065 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 16066 {
16067 /* There is a relocation for the initial PLT entry:
16068 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16069 if (h->plt.offset == htab->plt_header_size)
47beaa6a 16070 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 16071
16072 /* There are two extra relocations for each subsequent
16073 PLT entry: an R_ARM_32 relocation for the GOT entry,
16074 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 16075 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 16076 }
5e681ec4
PB		 16077 }
16078 else
16079 {
16080 h->plt.offset = (bfd_vma) -1;
f5385ebf 16081 h->needs_plt = 0;
5e681ec4
PB		 16082 }
16083 }
16084 else
16085 {
16086 h->plt.offset = (bfd_vma) -1;
f5385ebf 16087 h->needs_plt = 0;
5e681ec4
PB		 16088 }
16089
0855e32b
NS		 16090 eh = (struct elf32_arm_link_hash_entry *) h;
16091 eh->tlsdesc_got = (bfd_vma) -1;
16092
5e681ec4
PB		 16093 if (h->got.refcount > 0)
16094 {
16095 asection *s;
16096 bfd_boolean dyn;
ba93b8ac
DJ		 16097 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16098 int indx;
5e681ec4
PB		 16099
16100 /* Make sure this symbol is output as a dynamic symbol.
16101 Undefined weak syms won't yet be marked as dynamic. */
e8b09b87 16102 if (htab->root.dynamic_sections_created && h->dynindx == -1 && !h->forced_local
6c699715 16103 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16104 {
c152c796 16105 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16106 return FALSE;
16107 }
16108
e5a52504
MM		 16109 if (!htab->symbian_p)
16110 {
362d30a1 16111 s = htab->root.sgot;
e5a52504 16112 h->got.offset = s->size;
ba93b8ac
DJ		 16113
16114 if (tls_type == GOT_UNKNOWN)
16115 abort ();
16116
16117 if (tls_type == GOT_NORMAL)
16118 /* Non-TLS symbols need one GOT slot. */
16119 s->size += 4;
16120 else
16121 {
99059e56
RM		 16122 if (tls_type & GOT_TLS_GDESC)
16123 {
0855e32b 16124 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 16125 eh->tlsdesc_got
0855e32b
NS		 16126 = (htab->root.sgotplt->size
16127 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 16128 htab->root.sgotplt->size += 8;
16129 h->got.offset = (bfd_vma) -2;
34e77a92 16130 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16131 reloc in the middle of .got.plt. */
99059e56
RM		 16132 htab->num_tls_desc++;
16133 }
0855e32b 16134
ba93b8ac 16135 if (tls_type & GOT_TLS_GD)
0855e32b 16136 {
5c5a4843
CL		 16137 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16138 consecutive GOT slots. If the symbol is both GD
16139 and GDESC, got.offset may have been
16140 overwritten. */
0855e32b
NS		 16141 h->got.offset = s->size;
16142 s->size += 8;
16143 }
16144
ba93b8ac 16145 if (tls_type & GOT_TLS_IE)
5c5a4843
CL		 16146 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16147 slot. */
ba93b8ac
DJ		 16148 s->size += 4;
16149 }
16150
e5a52504 16151 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 16152
16153 indx = 0;
0e1862bb
L		 16154 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
16155 bfd_link_pic (info),
16156 h)
16157 && (!bfd_link_pic (info)
ba93b8ac
DJ		 16158 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16159 indx = h->dynindx;
16160
16161 if (tls_type != GOT_NORMAL
0e1862bb 16162 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 16163 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16164 || h->root.type != bfd_link_hash_undefweak))
16165 {
16166 if (tls_type & GOT_TLS_IE)
47beaa6a 16167 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16168
16169 if (tls_type & GOT_TLS_GD)
47beaa6a 16170 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16171
b38cadfb 16172 if (tls_type & GOT_TLS_GDESC)
0855e32b 16173 {
47beaa6a 16174 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 16175 /* GDESC needs a trampoline to jump to. */
16176 htab->tls_trampoline = -1;
16177 }
16178
16179 /* Only GD needs it. GDESC just emits one relocation per
16180 2 entries. */
b38cadfb 16181 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 16182 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16183 }
e8b09b87
CL		 16184 else if (((indx != -1) || htab->fdpic_p)
16185 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 16186 {
16187 if (htab->root.dynamic_sections_created)
16188 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16189 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16190 }
34e77a92
RS		 16191 else if (h->type == STT_GNU_IFUNC
16192 && eh->plt.noncall_refcount == 0)
16193 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16194 they all resolve dynamically instead. Reserve room for the
16195 GOT entry's R_ARM_IRELATIVE relocation. */
16196 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 16197 else if (bfd_link_pic (info)
16198 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16199 || h->root.type != bfd_link_hash_undefweak))
b436d854 16200 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 16201 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16202 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16203 /* Reserve room for rofixup for FDPIC executable. */
16204 /* TLS relocs do not need space since they are completely
16205 resolved. */
16206 htab->srofixup->size += 4;
e5a52504 16207 }
5e681ec4
PB		 16208 }
16209 else
16210 h->got.offset = (bfd_vma) -1;
16211
e8b09b87
CL		 16212 /* FDPIC support. */
16213 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16214 {
16215 /* Symbol musn't be exported. */
16216 if (h->dynindx != -1)
16217 abort();
16218
16219 /* We only allocate one function descriptor with its associated relocation. */
16220 if (eh->fdpic_cnts.funcdesc_offset == -1)
16221 {
16222 asection *s = htab->root.sgot;
16223
16224 eh->fdpic_cnts.funcdesc_offset = s->size;
16225 s->size += 8;
16226 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16227 if (bfd_link_pic(info))
16228 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16229 else
16230 htab->srofixup->size += 8;
16231 }
16232 }
16233
16234 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16235 {
16236 asection *s = htab->root.sgot;
16237
16238 if (htab->root.dynamic_sections_created && h->dynindx == -1
16239 && !h->forced_local)
16240 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16241 return FALSE;
16242
16243 if (h->dynindx == -1)
16244 {
16245 /* We only allocate one function descriptor with its associated relocation. q */
16246 if (eh->fdpic_cnts.funcdesc_offset == -1)
16247 {
16248
16249 eh->fdpic_cnts.funcdesc_offset = s->size;
16250 s->size += 8;
16251 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16252 if (bfd_link_pic(info))
16253 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16254 else
16255 htab->srofixup->size += 8;
16256 }
16257 }
16258
16259 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16260 R_ARM_RELATIVE/rofixup relocation on it. */
16261 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16262 s->size += 4;
16263 if (h->dynindx == -1 && !bfd_link_pic(info))
16264 htab->srofixup->size += 4;
16265 else
16266 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16267 }
16268
16269 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16270 {
16271 if (htab->root.dynamic_sections_created && h->dynindx == -1
16272 && !h->forced_local)
16273 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16274 return FALSE;
16275
16276 if (h->dynindx == -1)
16277 {
16278 /* We only allocate one function descriptor with its associated relocation. */
16279 if (eh->fdpic_cnts.funcdesc_offset == -1)
16280 {
16281 asection *s = htab->root.sgot;
16282
16283 eh->fdpic_cnts.funcdesc_offset = s->size;
16284 s->size += 8;
16285 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16286 if (bfd_link_pic(info))
16287 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16288 else
16289 htab->srofixup->size += 8;
16290 }
16291 }
16292 if (h->dynindx == -1 && !bfd_link_pic(info))
16293 {
16294 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16295 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16296 }
16297 else
16298 {
16299 /* Will need one dynamic reloc per reference. will be either
16300 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16301 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16302 eh->fdpic_cnts.funcdesc_cnt);
16303 }
16304 }
16305
a4fd1a8e
PB		 16306 /* Allocate stubs for exported Thumb functions on v4t. */
16307 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 16308 && h->def_regular
39d911fc 16309 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 16310 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16311 {
16312 struct elf_link_hash_entry * th;
16313 struct bfd_link_hash_entry * bh;
16314 struct elf_link_hash_entry * myh;
16315 char name[1024];
16316 asection *s;
16317 bh = NULL;
16318 /* Create a new symbol to regist the real location of the function. */
16319 s = h->root.u.def.section;
906e58ca 16320 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 16321 _bfd_generic_link_add_one_symbol (info, s->owner,
16322 name, BSF_GLOBAL, s,
16323 h->root.u.def.value,
16324 NULL, TRUE, FALSE, &bh);
16325
16326 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 16327 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 16328 myh->forced_local = 1;
39d911fc 16329 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 16330 eh->export_glue = myh;
16331 th = record_arm_to_thumb_glue (info, h);
16332 /* Point the symbol at the stub. */
16333 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 16334 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 16335 h->root.u.def.section = th->root.u.def.section;
16336 h->root.u.def.value = th->root.u.def.value & ~1;
16337 }
16338
0bdcacaf 16339 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 16340 return TRUE;
16341
16342 /* In the shared -Bsymbolic case, discard space allocated for
16343 dynamic pc-relative relocs against symbols which turn out to be
16344 defined in regular objects. For the normal shared case, discard
16345 space for pc-relative relocs that have become local due to symbol
16346 visibility changes. */
16347
e8b09b87 16348 if (bfd_link_pic (info) || htab->root.is_relocatable_executable || htab->fdpic_p)
5e681ec4 16349 {
469a3493
RM		 16350 /* Relocs that use pc_count are PC-relative forms, which will appear
16351 on something like ".long foo - ." or "movw REG, foo - .". We want
16352 calls to protected symbols to resolve directly to the function
16353 rather than going via the plt. If people want function pointer
16354 comparisons to work as expected then they should avoid writing
16355 assembly like ".long foo - .". */
ba93b8ac
DJ		 16356 if (SYMBOL_CALLS_LOCAL (info, h))
16357 {
0bdcacaf 16358 struct elf_dyn_relocs **pp;
ba93b8ac 16359
0bdcacaf 16360 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 16361 {
16362 p->count -= p->pc_count;
16363 p->pc_count = 0;
16364 if (p->count == 0)
16365 *pp = p->next;
16366 else
16367 pp = &p->next;
16368 }
16369 }
16370
4dfe6ac6 16371 if (htab->vxworks_p)
3348747a 16372 {
0bdcacaf 16373 struct elf_dyn_relocs **pp;
3348747a 16374
0bdcacaf 16375 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 16376 {
0bdcacaf 16377 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 16378 *pp = p->next;
16379 else
16380 pp = &p->next;
16381 }
16382 }
16383
ba93b8ac 16384 /* Also discard relocs on undefined weak syms with non-default
99059e56 16385 visibility. */
0bdcacaf 16386 if (eh->dyn_relocs != NULL
5e681ec4 16387 && h->root.type == bfd_link_hash_undefweak)
22d606e9 16388 {
95b03e4a
L		 16389 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16390 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
0bdcacaf 16391 eh->dyn_relocs = NULL;
22d606e9
AM		 16392
16393 /* Make sure undefined weak symbols are output as a dynamic
16394 symbol in PIEs. */
e8b09b87 16395 else if (htab->root.dynamic_sections_created && h->dynindx == -1
22d606e9
AM		 16396 && !h->forced_local)
16397 {
16398 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16399 return FALSE;
16400 }
16401 }
16402
67687978
PB		 16403 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16404 && h->root.type == bfd_link_hash_new)
16405 {
16406 /* Output absolute symbols so that we can create relocations
16407 against them. For normal symbols we output a relocation
16408 against the section that contains them. */
16409 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16410 return FALSE;
16411 }
16412
5e681ec4
PB		 16413 }
16414 else
16415 {
16416 /* For the non-shared case, discard space for relocs against
16417 symbols which turn out to need copy relocs or are not
16418 dynamic. */
16419
f5385ebf
AM		 16420 if (!h->non_got_ref
16421 && ((h->def_dynamic
16422 && !h->def_regular)
5e681ec4
PB		 16423 || (htab->root.dynamic_sections_created
16424 && (h->root.type == bfd_link_hash_undefweak
16425 || h->root.type == bfd_link_hash_undefined))))
16426 {
16427 /* Make sure this symbol is output as a dynamic symbol.
16428 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16429 if (h->dynindx == -1 && !h->forced_local
16430 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16431 {
c152c796 16432 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16433 return FALSE;
16434 }
16435
16436 /* If that succeeded, we know we'll be keeping all the
16437 relocs. */
16438 if (h->dynindx != -1)
16439 goto keep;
16440 }
16441
0bdcacaf 16442 eh->dyn_relocs = NULL;
5e681ec4
PB		 16443
16444 keep: ;
16445 }
16446
16447 /* Finally, allocate space. */
0bdcacaf 16448 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 16449 {
0bdcacaf 16450 asection *sreloc = elf_section_data (p->sec)->sreloc;
e8b09b87 16451
34e77a92
RS		 16452 if (h->type == STT_GNU_IFUNC
16453 && eh->plt.noncall_refcount == 0
16454 && SYMBOL_REFERENCES_LOCAL (info, h))
16455 elf32_arm_allocate_irelocs (info, sreloc, p->count);
e8b09b87
CL		 16456 else if (h->dynindx != -1 && (!bfd_link_pic(info) || !info->symbolic || !h->def_regular))
16457 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16458 else if (htab->fdpic_p && !bfd_link_pic(info))
16459 htab->srofixup->size += 4 * p->count;
34e77a92
RS		 16460 else
16461 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 16462 }
16463
16464 return TRUE;
16465}
16466
63c1f59d
AM		 16467/* Set DF_TEXTREL if we find any dynamic relocs that apply to
16468 read-only sections. */
08d1f311
DJ		 16469
16470static bfd_boolean
63c1f59d 16471maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p)
08d1f311 16472{
63c1f59d 16473 asection *sec;
08d1f311 16474
63c1f59d
AM		 16475 if (h->root.type == bfd_link_hash_indirect)
16476 return TRUE;
08d1f311 16477
63c1f59d
AM		 16478 sec = readonly_dynrelocs (h);
16479 if (sec != NULL)
16480 {
16481 struct bfd_link_info *info = (struct bfd_link_info *) info_p;
08d1f311 16482
63c1f59d
AM		 16483 info->flags |= DF_TEXTREL;
16484 info->callbacks->minfo
c1c8c1ef 16485 (_("%pB: dynamic relocation against `%pT' in read-only section `%pA'\n"),
63c1f59d 16486 sec->owner, h->root.root.string, sec);
08d1f311 16487
63c1f59d
AM		 16488 /* Not an error, just cut short the traversal. */
16489 return FALSE;
08d1f311 16490 }
cb10292c 16491
08d1f311
DJ		 16492 return TRUE;
16493}
16494
d504ffc8
DJ		 16495void
16496bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16497 int byteswap_code)
16498{
16499 struct elf32_arm_link_hash_table *globals;
16500
16501 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16502 if (globals == NULL)
16503 return;
16504
d504ffc8
DJ		 16505 globals->byteswap_code = byteswap_code;
16506}
16507
252b5132
RH		 16508/* Set the sizes of the dynamic sections. */
16509
b34976b6 16510static bfd_boolean
57e8b36a
NC		 16511elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16512 struct bfd_link_info * info)
252b5132
RH		 16513{
16514 bfd * dynobj;
16515 asection * s;
b34976b6
AM		 16516 bfd_boolean plt;
16517 bfd_boolean relocs;
5e681ec4
PB		 16518 bfd *ibfd;
16519 struct elf32_arm_link_hash_table *htab;
252b5132 16520
5e681ec4 16521 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16522 if (htab == NULL)
16523 return FALSE;
16524
252b5132
RH		 16525 dynobj = elf_hash_table (info)->dynobj;
16526 BFD_ASSERT (dynobj != NULL);
39b41c9c 16527 check_use_blx (htab);
252b5132
RH		 16528
16529 if (elf_hash_table (info)->dynamic_sections_created)
16530 {
16531 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 16532 if (bfd_link_executable (info) && !info->nointerp)
252b5132 16533 {
3d4d4302 16534 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 16535 BFD_ASSERT (s != NULL);
eea6121a 16536 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 16537 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16538 }
16539 }
5e681ec4
PB		 16540
16541 /* Set up .got offsets for local syms, and space for local dynamic
16542 relocs. */
c72f2fb2 16543 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 16544 {
5e681ec4
PB		 16545 bfd_signed_vma *local_got;
16546 bfd_signed_vma *end_local_got;
34e77a92 16547 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 16548 char *local_tls_type;
0855e32b 16549 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 16550 bfd_size_type locsymcount;
16551 Elf_Internal_Shdr *symtab_hdr;
16552 asection *srel;
4dfe6ac6 16553 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 16554 unsigned int symndx;
e8b09b87 16555 struct fdpic_local *local_fdpic_cnts;
5e681ec4 16556
0ffa91dd 16557 if (! is_arm_elf (ibfd))
5e681ec4
PB		 16558 continue;
16559
16560 for (s = ibfd->sections; s != NULL; s = s->next)
16561 {
0bdcacaf 16562 struct elf_dyn_relocs *p;
5e681ec4 16563
0bdcacaf 16564 for (p = (struct elf_dyn_relocs *)
99059e56 16565 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 16566 {
0bdcacaf
RS		 16567 if (!bfd_is_abs_section (p->sec)
16568 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 16569 {
16570 /* Input section has been discarded, either because
16571 it is a copy of a linkonce section or due to
16572 linker script /DISCARD/, so we'll be discarding
16573 the relocs too. */
16574 }
3348747a 16575 else if (is_vxworks
0bdcacaf 16576 && strcmp (p->sec->output_section->name,
3348747a
NS		 16577 ".tls_vars") == 0)
16578 {
16579 /* Relocations in vxworks .tls_vars sections are
16580 handled specially by the loader. */
16581 }
5e681ec4
PB		 16582 else if (p->count != 0)
16583 {
0bdcacaf 16584 srel = elf_section_data (p->sec)->sreloc;
e8b09b87
CL		 16585 if (htab->fdpic_p && !bfd_link_pic(info))
16586 htab->srofixup->size += 4 * p->count;
16587 else
16588 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 16589 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 16590 info->flags |= DF_TEXTREL;
16591 }
16592 }
16593 }
16594
16595 local_got = elf_local_got_refcounts (ibfd);
16596 if (!local_got)
16597 continue;
16598
0ffa91dd 16599 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 16600 locsymcount = symtab_hdr->sh_info;
16601 end_local_got = local_got + locsymcount;
34e77a92 16602 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 16603 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 16604 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
e8b09b87 16605 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
34e77a92 16606 symndx = 0;
362d30a1
RS		 16607 s = htab->root.sgot;
16608 srel = htab->root.srelgot;
0855e32b 16609 for (; local_got < end_local_got;
34e77a92 16610 ++local_got, ++local_iplt_ptr, ++local_tls_type,
e8b09b87 16611 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
5e681ec4 16612 {
0855e32b 16613 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92 16614 local_iplt = *local_iplt_ptr;
e8b09b87
CL		 16615
16616 /* FDPIC support. */
16617 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16618 {
16619 if (local_fdpic_cnts->funcdesc_offset == -1)
16620 {
16621 local_fdpic_cnts->funcdesc_offset = s->size;
16622 s->size += 8;
16623
16624 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16625 if (bfd_link_pic(info))
16626 elf32_arm_allocate_dynrelocs (info, srel, 1);
16627 else
16628 htab->srofixup->size += 8;
16629 }
16630 }
16631
16632 if (local_fdpic_cnts->funcdesc_cnt > 0)
16633 {
16634 if (local_fdpic_cnts->funcdesc_offset == -1)
16635 {
16636 local_fdpic_cnts->funcdesc_offset = s->size;
16637 s->size += 8;
16638
16639 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16640 if (bfd_link_pic(info))
16641 elf32_arm_allocate_dynrelocs (info, srel, 1);
16642 else
16643 htab->srofixup->size += 8;
16644 }
16645
16646 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16647 if (bfd_link_pic(info))
16648 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16649 else
16650 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16651 }
16652
34e77a92
RS		 16653 if (local_iplt != NULL)
16654 {
16655 struct elf_dyn_relocs *p;
16656
16657 if (local_iplt->root.refcount > 0)
16658 {
16659 elf32_arm_allocate_plt_entry (info, TRUE,
16660 &local_iplt->root,
16661 &local_iplt->arm);
16662 if (local_iplt->arm.noncall_refcount == 0)
16663 /* All references to the PLT are calls, so all
16664 non-call references can resolve directly to the
16665 run-time target. This means that the .got entry
16666 would be the same as the .igot.plt entry, so there's
16667 no point creating both. */
16668 *local_got = 0;
16669 }
16670 else
16671 {
16672 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
16673 local_iplt->root.offset = (bfd_vma) -1;
16674 }
16675
16676 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
16677 {
16678 asection *psrel;
16679
16680 psrel = elf_section_data (p->sec)->sreloc;
16681 if (local_iplt->arm.noncall_refcount == 0)
16682 elf32_arm_allocate_irelocs (info, psrel, p->count);
16683 else
16684 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
16685 }
16686 }
5e681ec4
PB		 16687 if (*local_got > 0)
16688 {
34e77a92
RS		 16689 Elf_Internal_Sym *isym;
16690
eea6121a 16691 *local_got = s->size;
ba93b8ac
DJ		 16692 if (*local_tls_type & GOT_TLS_GD)
16693 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16694 s->size += 8;
0855e32b
NS		 16695 if (*local_tls_type & GOT_TLS_GDESC)
16696 {
16697 *local_tlsdesc_gotent = htab->root.sgotplt->size
16698 - elf32_arm_compute_jump_table_size (htab);
16699 htab->root.sgotplt->size += 8;
16700 *local_got = (bfd_vma) -2;
34e77a92 16701 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16702 reloc in the middle of .got.plt. */
99059e56 16703 htab->num_tls_desc++;
0855e32b 16704 }
ba93b8ac
DJ		 16705 if (*local_tls_type & GOT_TLS_IE)
16706 s->size += 4;
ba93b8ac 16707
0855e32b
NS		 16708 if (*local_tls_type & GOT_NORMAL)
16709 {
16710 /* If the symbol is both GD and GDESC, *local_got
16711 may have been overwritten. */
16712 *local_got = s->size;
16713 s->size += 4;
16714 }
16715
34e77a92
RS		 16716 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
16717 if (isym == NULL)
16718 return FALSE;
16719
16720 /* If all references to an STT_GNU_IFUNC PLT are calls,
16721 then all non-call references, including this GOT entry,
16722 resolve directly to the run-time target. */
16723 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
16724 && (local_iplt == NULL
16725 || local_iplt->arm.noncall_refcount == 0))
16726 elf32_arm_allocate_irelocs (info, srel, 1);
e8b09b87 16727 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
0855e32b 16728 {
e8b09b87 16729 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
3064e1ff 16730 elf32_arm_allocate_dynrelocs (info, srel, 1);
e8b09b87
CL		 16731 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
16732 htab->srofixup->size += 4;
99059e56 16733
e8b09b87
CL		 16734 if ((bfd_link_pic (info) || htab->fdpic_p)
16735 && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 16736 {
16737 elf32_arm_allocate_dynrelocs (info,
16738 htab->root.srelplt, 1);
16739 htab->tls_trampoline = -1;
16740 }
0855e32b 16741 }
5e681ec4
PB		 16742 }
16743 else
16744 *local_got = (bfd_vma) -1;
16745 }
252b5132
RH		 16746 }
16747
ba93b8ac
DJ		 16748 if (htab->tls_ldm_got.refcount > 0)
16749 {
16750 /* Allocate two GOT entries and one dynamic relocation (if necessary)
5c5a4843 16751 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
362d30a1
RS		 16752 htab->tls_ldm_got.offset = htab->root.sgot->size;
16753 htab->root.sgot->size += 8;
0e1862bb 16754 if (bfd_link_pic (info))
47beaa6a 16755 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16756 }
16757 else
16758 htab->tls_ldm_got.offset = -1;
16759
e8b09b87
CL		 16760 /* At the very end of the .rofixup section is a pointer to the GOT,
16761 reserve space for it. */
16762 if (htab->fdpic_p && htab->srofixup != NULL)
16763 htab->srofixup->size += 4;
16764
5e681ec4
PB		 16765 /* Allocate global sym .plt and .got entries, and space for global
16766 sym dynamic relocs. */
47beaa6a 16767 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 16768
d504ffc8 16769 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 16770 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 16771 {
0ffa91dd 16772 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 16773 continue;
16774
c7b8f16e
JB		 16775 /* Initialise mapping tables for code/data. */
16776 bfd_elf32_arm_init_maps (ibfd);
906e58ca 16777
c7b8f16e 16778 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 16779 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
16780 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 16781 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 16782 }
d504ffc8 16783
3e6b1042
DJ		 16784 /* Allocate space for the glue sections now that we've sized them. */
16785 bfd_elf32_arm_allocate_interworking_sections (info);
16786
0855e32b
NS		 16787 /* For every jump slot reserved in the sgotplt, reloc_count is
16788 incremented. However, when we reserve space for TLS descriptors,
16789 it's not incremented, so in order to compute the space reserved
16790 for them, it suffices to multiply the reloc count by the jump
16791 slot size. */
16792 if (htab->root.srelplt)
16793 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
16794
16795 if (htab->tls_trampoline)
16796 {
16797 if (htab->root.splt->size == 0)
16798 htab->root.splt->size += htab->plt_header_size;
b38cadfb 16799
0855e32b
NS		 16800 htab->tls_trampoline = htab->root.splt->size;
16801 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 16802
0855e32b 16803 /* If we're not using lazy TLS relocations, don't generate the
99059e56 16804 PLT and GOT entries they require. */
0855e32b
NS		 16805 if (!(info->flags & DF_BIND_NOW))
16806 {
16807 htab->dt_tlsdesc_got = htab->root.sgot->size;
16808 htab->root.sgot->size += 4;
16809
16810 htab->dt_tlsdesc_plt = htab->root.splt->size;
16811 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
16812 }
16813 }
16814
252b5132
RH		 16815 /* The check_relocs and adjust_dynamic_symbol entry points have
16816 determined the sizes of the various dynamic sections. Allocate
16817 memory for them. */
b34976b6
AM		 16818 plt = FALSE;
16819 relocs = FALSE;
252b5132
RH		 16820 for (s = dynobj->sections; s != NULL; s = s->next)
16821 {
16822 const char * name;
252b5132
RH		 16823
16824 if ((s->flags & SEC_LINKER_CREATED) == 0)
16825 continue;
16826
16827 /* It's OK to base decisions on the section name, because none
16828 of the dynobj section names depend upon the input files. */
16829 name = bfd_get_section_name (dynobj, s);
16830
34e77a92 16831 if (s == htab->root.splt)
252b5132 16832 {
c456f082
AM		 16833 /* Remember whether there is a PLT. */
16834 plt = s->size != 0;
252b5132 16835 }
0112cd26 16836 else if (CONST_STRNEQ (name, ".rel"))
252b5132 16837 {
c456f082 16838 if (s->size != 0)
252b5132 16839 {
252b5132 16840 /* Remember whether there are any reloc sections other
00a97672 16841 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 16842 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 16843 relocs = TRUE;
252b5132
RH		 16844
16845 /* We use the reloc_count field as a counter if we need
16846 to copy relocs into the output file. */
16847 s->reloc_count = 0;
16848 }
16849 }
34e77a92
RS		 16850 else if (s != htab->root.sgot
16851 && s != htab->root.sgotplt
16852 && s != htab->root.iplt
16853 && s != htab->root.igotplt
5474d94f 16854 && s != htab->root.sdynbss
e8b09b87
CL		 16855 && s != htab->root.sdynrelro
16856 && s != htab->srofixup)
252b5132
RH		 16857 {
16858 /* It's not one of our sections, so don't allocate space. */
16859 continue;
16860 }
16861
c456f082 16862 if (s->size == 0)
252b5132 16863 {
c456f082 16864 /* If we don't need this section, strip it from the
00a97672
RS		 16865 output file. This is mostly to handle .rel(a).bss and
16866 .rel(a).plt. We must create both sections in
c456f082
AM		 16867 create_dynamic_sections, because they must be created
16868 before the linker maps input sections to output
16869 sections. The linker does that before
16870 adjust_dynamic_symbol is called, and it is that
16871 function which decides whether anything needs to go
16872 into these sections. */
8423293d 16873 s->flags |= SEC_EXCLUDE;
252b5132
RH		 16874 continue;
16875 }
16876
c456f082
AM		 16877 if ((s->flags & SEC_HAS_CONTENTS) == 0)
16878 continue;
16879
252b5132 16880 /* Allocate memory for the section contents. */
21d799b5 16881 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 16882 if (s->contents == NULL)
b34976b6 16883 return FALSE;
252b5132
RH		 16884 }
16885
16886 if (elf_hash_table (info)->dynamic_sections_created)
16887 {
16888 /* Add some entries to the .dynamic section. We fill in the
16889 values later, in elf32_arm_finish_dynamic_sections, but we
16890 must add the entries now so that we get the correct size for
16891 the .dynamic section. The DT_DEBUG entry is filled in by the
16892 dynamic linker and used by the debugger. */
dc810e39 16893#define add_dynamic_entry(TAG, VAL) \
5a580b3a 16894 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 16895
0e1862bb 16896 if (bfd_link_executable (info))
252b5132 16897 {
dc810e39 16898 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 16899 return FALSE;
252b5132
RH		 16900 }
16901
16902 if (plt)
16903 {
dc810e39
AM		 16904 if ( !add_dynamic_entry (DT_PLTGOT, 0)
16905 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 16906 || !add_dynamic_entry (DT_PLTREL,
16907 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 16908 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 16909 return FALSE;
0855e32b 16910
5025eb7c
AO		 16911 if (htab->dt_tlsdesc_plt
16912 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
16913 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 16914 return FALSE;
252b5132
RH		 16915 }
16916
16917 if (relocs)
16918 {
00a97672
RS		 16919 if (htab->use_rel)
16920 {
16921 if (!add_dynamic_entry (DT_REL, 0)
16922 || !add_dynamic_entry (DT_RELSZ, 0)
16923 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
16924 return FALSE;
16925 }
16926 else
16927 {
16928 if (!add_dynamic_entry (DT_RELA, 0)
16929 || !add_dynamic_entry (DT_RELASZ, 0)
16930 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
16931 return FALSE;
16932 }
252b5132
RH		 16933 }
16934
08d1f311
DJ		 16935 /* If any dynamic relocs apply to a read-only section,
16936 then we need a DT_TEXTREL entry. */
16937 if ((info->flags & DF_TEXTREL) == 0)
63c1f59d 16938 elf_link_hash_traverse (&htab->root, maybe_set_textrel, info);
08d1f311 16939
99e4ae17 16940 if ((info->flags & DF_TEXTREL) != 0)
252b5132 16941 {
dc810e39 16942 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 16943 return FALSE;
252b5132 16944 }
7a2b07ff
NS		 16945 if (htab->vxworks_p
16946 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
16947 return FALSE;
252b5132 16948 }
8532796c 16949#undef add_dynamic_entry
252b5132 16950
b34976b6 16951 return TRUE;
252b5132
RH		 16952}
16953
0855e32b
NS		 16954/* Size sections even though they're not dynamic. We use it to setup
16955 _TLS_MODULE_BASE_, if needed. */
16956
16957static bfd_boolean
16958elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 16959 struct bfd_link_info *info)
0855e32b
NS		 16960{
16961 asection *tls_sec;
cb10292c
CL		 16962 struct elf32_arm_link_hash_table *htab;
16963
16964 htab = elf32_arm_hash_table (info);
0855e32b 16965
0e1862bb 16966 if (bfd_link_relocatable (info))
0855e32b
NS		 16967 return TRUE;
16968
16969 tls_sec = elf_hash_table (info)->tls_sec;
16970
16971 if (tls_sec)
16972 {
16973 struct elf_link_hash_entry *tlsbase;
16974
16975 tlsbase = elf_link_hash_lookup
16976 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
16977
16978 if (tlsbase)
99059e56
RM		 16979 {
16980 struct bfd_link_hash_entry *bh = NULL;
0855e32b 16981 const struct elf_backend_data *bed
99059e56 16982 = get_elf_backend_data (output_bfd);
0855e32b 16983
99059e56 16984 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 16985 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
16986 tls_sec, 0, NULL, FALSE,
16987 bed->collect, &bh)))
16988 return FALSE;
b38cadfb 16989
99059e56
RM		 16990 tlsbase->type = STT_TLS;
16991 tlsbase = (struct elf_link_hash_entry *)bh;
16992 tlsbase->def_regular = 1;
16993 tlsbase->other = STV_HIDDEN;
16994 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 16995 }
16996 }
cb10292c
CL		 16997
16998 if (htab->fdpic_p && !bfd_link_relocatable (info)
16999 && !bfd_elf_stack_segment_size (output_bfd, info,
17000 "__stacksize", DEFAULT_STACK_SIZE))
17001 return FALSE;
17002
0855e32b
NS		 17003 return TRUE;
17004}
17005
252b5132
RH		 17006/* Finish up dynamic symbol handling. We set the contents of various
17007 dynamic sections here. */
17008
b34976b6 17009static bfd_boolean
906e58ca
NC		 17010elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17011 struct bfd_link_info * info,
17012 struct elf_link_hash_entry * h,
17013 Elf_Internal_Sym * sym)
252b5132 17014{
e5a52504 17015 struct elf32_arm_link_hash_table *htab;
b7693d02 17016 struct elf32_arm_link_hash_entry *eh;
252b5132 17017
e5a52504 17018 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17019 if (htab == NULL)
17020 return FALSE;
17021
b7693d02 17022 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 17023
17024 if (h->plt.offset != (bfd_vma) -1)
17025 {
34e77a92 17026 if (!eh->is_iplt)
e5a52504 17027 {
34e77a92 17028 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 17029 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17030 h->dynindx, 0))
17031 return FALSE;
e5a52504 17032 }
57e8b36a 17033
f5385ebf 17034 if (!h->def_regular)
252b5132
RH		 17035 {
17036 /* Mark the symbol as undefined, rather than as defined in
3a635617 17037 the .plt section. */
252b5132 17038 sym->st_shndx = SHN_UNDEF;
3a635617 17039 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 17040 Otherwise, the PLT entry would provide a definition for
17041 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 17042 and so the symbol would never be NULL. Leave the value if
17043 there were any relocations where pointer equality matters
17044 (this is a clue for the dynamic linker, to make function
17045 pointer comparisons work between an application and shared
17046 library). */
97323ad1 17047 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 17048 sym->st_value = 0;
252b5132 17049 }
34e77a92
RS		 17050 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17051 {
17052 /* At least one non-call relocation references this .iplt entry,
17053 so the .iplt entry is the function's canonical address. */
17054 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 17055 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 17056 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17057 (output_bfd, htab->root.iplt->output_section));
17058 sym->st_value = (h->plt.offset
17059 + htab->root.iplt->output_section->vma
17060 + htab->root.iplt->output_offset);
17061 }
252b5132
RH		 17062 }
17063
f5385ebf 17064 if (h->needs_copy)
252b5132
RH		 17065 {
17066 asection * s;
947216bf 17067 Elf_Internal_Rela rel;
252b5132
RH		 17068
17069 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 17070 BFD_ASSERT (h->dynindx != -1
17071 && (h->root.type == bfd_link_hash_defined
17072 || h->root.type == bfd_link_hash_defweak));
17073
00a97672 17074 rel.r_addend = 0;
252b5132
RH		 17075 rel.r_offset = (h->root.u.def.value
17076 + h->root.u.def.section->output_section->vma
17077 + h->root.u.def.section->output_offset);
17078 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 17079 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 17080 s = htab->root.sreldynrelro;
17081 else
17082 s = htab->root.srelbss;
47beaa6a 17083 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 17084 }
17085
00a97672
RS		 17086 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
17087 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
17088 to the ".got" section. */
9637f6ef 17089 if (h == htab->root.hdynamic
00a97672 17090 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 17091 sym->st_shndx = SHN_ABS;
17092
b34976b6 17093 return TRUE;
252b5132
RH		 17094}
17095
0855e32b
NS		 17096static void
17097arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17098 void *contents,
17099 const unsigned long *template, unsigned count)
17100{
17101 unsigned ix;
b38cadfb 17102
0855e32b
NS		 17103 for (ix = 0; ix != count; ix++)
17104 {
17105 unsigned long insn = template[ix];
17106
17107 /* Emit mov pc,rx if bx is not permitted. */
17108 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17109 insn = (insn & 0xf000000f) | 0x01a0f000;
17110 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17111 }
17112}
17113
99059e56
RM		 17114/* Install the special first PLT entry for elf32-arm-nacl. Unlike
17115 other variants, NaCl needs this entry in a static executable's
17116 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17117 zero. For .iplt really only the last bundle is useful, and .iplt
17118 could have a shorter first entry, with each individual PLT entry's
17119 relative branch calculated differently so it targets the last
17120 bundle instead of the instruction before it (labelled .Lplt_tail
17121 above). But it's simpler to keep the size and layout of PLT0
17122 consistent with the dynamic case, at the cost of some dead code at
17123 the start of .iplt and the one dead store to the stack at the start
17124 of .Lplt_tail. */
17125static void
17126arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17127 asection *plt, bfd_vma got_displacement)
17128{
17129 unsigned int i;
17130
17131 put_arm_insn (htab, output_bfd,
17132 elf32_arm_nacl_plt0_entry[0]
17133 | arm_movw_immediate (got_displacement),
17134 plt->contents + 0);
17135 put_arm_insn (htab, output_bfd,
17136 elf32_arm_nacl_plt0_entry[1]
17137 | arm_movt_immediate (got_displacement),
17138 plt->contents + 4);
17139
17140 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17141 put_arm_insn (htab, output_bfd,
17142 elf32_arm_nacl_plt0_entry[i],
17143 plt->contents + (i * 4));
17144}
17145
252b5132
RH		 17146/* Finish up the dynamic sections. */
17147
b34976b6 17148static bfd_boolean
57e8b36a 17149elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 17150{
17151 bfd * dynobj;
17152 asection * sgot;
17153 asection * sdyn;
4dfe6ac6
NC		 17154 struct elf32_arm_link_hash_table *htab;
17155
17156 htab = elf32_arm_hash_table (info);
17157 if (htab == NULL)
17158 return FALSE;
252b5132
RH		 17159
17160 dynobj = elf_hash_table (info)->dynobj;
17161
362d30a1 17162 sgot = htab->root.sgotplt;
894891db
NC		 17163 /* A broken linker script might have discarded the dynamic sections.
17164 Catch this here so that we do not seg-fault later on. */
17165 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17166 return FALSE;
3d4d4302 17167 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 17168
17169 if (elf_hash_table (info)->dynamic_sections_created)
17170 {
17171 asection *splt;
17172 Elf32_External_Dyn *dyncon, *dynconend;
17173
362d30a1 17174 splt = htab->root.splt;
24a1ba0f 17175 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 17176 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 17177
17178 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 17179 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 17180
252b5132
RH		 17181 for (; dyncon < dynconend; dyncon++)
17182 {
17183 Elf_Internal_Dyn dyn;
17184 const char * name;
17185 asection * s;
17186
17187 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17188
17189 switch (dyn.d_tag)
17190 {
229fcec5
MM		 17191 unsigned int type;
17192
252b5132 17193 default:
7a2b07ff
NS		 17194 if (htab->vxworks_p
17195 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17196 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 17197 break;
17198
229fcec5
MM		 17199 case DT_HASH:
17200 name = ".hash";
17201 goto get_vma_if_bpabi;
17202 case DT_STRTAB:
17203 name = ".dynstr";
17204 goto get_vma_if_bpabi;
17205 case DT_SYMTAB:
17206 name = ".dynsym";
17207 goto get_vma_if_bpabi;
c0042f5d
MM		 17208 case DT_VERSYM:
17209 name = ".gnu.version";
17210 goto get_vma_if_bpabi;
17211 case DT_VERDEF:
17212 name = ".gnu.version_d";
17213 goto get_vma_if_bpabi;
17214 case DT_VERNEED:
17215 name = ".gnu.version_r";
17216 goto get_vma_if_bpabi;
17217
252b5132 17218 case DT_PLTGOT:
4ade44b7 17219 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 17220 goto get_vma;
17221 case DT_JMPREL:
00a97672 17222 name = RELOC_SECTION (htab, ".plt");
252b5132 17223 get_vma:
4ade44b7 17224 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 17225 if (s == NULL)
17226 {
4eca0228 17227 _bfd_error_handler
4ade44b7 17228 (_("could not find section %s"), name);
05456594
NC		 17229 bfd_set_error (bfd_error_invalid_operation);
17230 return FALSE;
17231 }
229fcec5 17232 if (!htab->symbian_p)
4ade44b7 17233 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 17234 else
17235 /* In the BPABI, tags in the PT_DYNAMIC section point
17236 at the file offset, not the memory address, for the
17237 convenience of the post linker. */
4ade44b7 17238 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 17239 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17240 break;
17241
229fcec5
MM		 17242 get_vma_if_bpabi:
17243 if (htab->symbian_p)
17244 goto get_vma;
17245 break;
17246
252b5132 17247 case DT_PLTRELSZ:
362d30a1 17248 s = htab->root.srelplt;
252b5132 17249 BFD_ASSERT (s != NULL);
eea6121a 17250 dyn.d_un.d_val = s->size;
252b5132
RH		 17251 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17252 break;
906e58ca 17253
252b5132 17254 case DT_RELSZ:
00a97672 17255 case DT_RELASZ:
229fcec5
MM		 17256 case DT_REL:
17257 case DT_RELA:
229fcec5
MM		 17258 /* In the BPABI, the DT_REL tag must point at the file
17259 offset, not the VMA, of the first relocation
17260 section. So, we use code similar to that in
17261 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 17262 relocation section, since relocation sections are
17263 never allocated under the BPABI. PLT relocs are also
17264 included. */
229fcec5
MM		 17265 if (htab->symbian_p)
17266 {
17267 unsigned int i;
17268 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
17269 ? SHT_REL : SHT_RELA);
17270 dyn.d_un.d_val = 0;
17271 for (i = 1; i < elf_numsections (output_bfd); i++)
17272 {
906e58ca 17273 Elf_Internal_Shdr *hdr
229fcec5
MM		 17274 = elf_elfsections (output_bfd)[i];
17275 if (hdr->sh_type == type)
17276 {
906e58ca 17277 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 17278 || dyn.d_tag == DT_RELASZ)
17279 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 17280 else if ((ufile_ptr) hdr->sh_offset
17281 <= dyn.d_un.d_val - 1)
229fcec5
MM		 17282 dyn.d_un.d_val = hdr->sh_offset;
17283 }
17284 }
17285 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17286 }
252b5132 17287 break;
88f7bcd5 17288
0855e32b 17289 case DT_TLSDESC_PLT:
99059e56 17290 s = htab->root.splt;
0855e32b
NS		 17291 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
17292 + htab->dt_tlsdesc_plt);
17293 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17294 break;
17295
17296 case DT_TLSDESC_GOT:
99059e56 17297 s = htab->root.sgot;
0855e32b 17298 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 17299 + htab->dt_tlsdesc_got);
0855e32b
NS		 17300 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17301 break;
17302
88f7bcd5
NC		 17303 /* Set the bottom bit of DT_INIT/FINI if the
17304 corresponding function is Thumb. */
17305 case DT_INIT:
17306 name = info->init_function;
17307 goto get_sym;
17308 case DT_FINI:
17309 name = info->fini_function;
17310 get_sym:
17311 /* If it wasn't set by elf_bfd_final_link
4cc11e76 17312 then there is nothing to adjust. */
88f7bcd5
NC		 17313 if (dyn.d_un.d_val != 0)
17314 {
17315 struct elf_link_hash_entry * eh;
17316
17317 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 17318 FALSE, FALSE, TRUE);
39d911fc
TP		 17319 if (eh != NULL
17320 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17321 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 17322 {
17323 dyn.d_un.d_val |= 1;
b34976b6 17324 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 17325 }
17326 }
17327 break;
252b5132
RH		 17328 }
17329 }
17330
24a1ba0f 17331 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 17332 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 17333 {
00a97672
RS		 17334 const bfd_vma *plt0_entry;
17335 bfd_vma got_address, plt_address, got_displacement;
17336
17337 /* Calculate the addresses of the GOT and PLT. */
17338 got_address = sgot->output_section->vma + sgot->output_offset;
17339 plt_address = splt->output_section->vma + splt->output_offset;
17340
17341 if (htab->vxworks_p)
17342 {
17343 /* The VxWorks GOT is relocated by the dynamic linker.
17344 Therefore, we must emit relocations rather than simply
17345 computing the values now. */
17346 Elf_Internal_Rela rel;
17347
17348 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 17349 put_arm_insn (htab, output_bfd, plt0_entry[0],
17350 splt->contents + 0);
17351 put_arm_insn (htab, output_bfd, plt0_entry[1],
17352 splt->contents + 4);
17353 put_arm_insn (htab, output_bfd, plt0_entry[2],
17354 splt->contents + 8);
00a97672
RS		 17355 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17356
8029a119 17357 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 17358 rel.r_offset = plt_address + 12;
17359 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17360 rel.r_addend = 0;
17361 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17362 htab->srelplt2->contents);
17363 }
b38cadfb 17364 else if (htab->nacl_p)
99059e56
RM		 17365 arm_nacl_put_plt0 (htab, output_bfd, splt,
17366 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 17367 else if (using_thumb_only (htab))
17368 {
17369 got_displacement = got_address - (plt_address + 12);
17370
17371 plt0_entry = elf32_thumb2_plt0_entry;
17372 put_arm_insn (htab, output_bfd, plt0_entry[0],
17373 splt->contents + 0);
17374 put_arm_insn (htab, output_bfd, plt0_entry[1],
17375 splt->contents + 4);
17376 put_arm_insn (htab, output_bfd, plt0_entry[2],
17377 splt->contents + 8);
17378
17379 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17380 }
00a97672
RS		 17381 else
17382 {
17383 got_displacement = got_address - (plt_address + 16);
17384
17385 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 17386 put_arm_insn (htab, output_bfd, plt0_entry[0],
17387 splt->contents + 0);
17388 put_arm_insn (htab, output_bfd, plt0_entry[1],
17389 splt->contents + 4);
17390 put_arm_insn (htab, output_bfd, plt0_entry[2],
17391 splt->contents + 8);
17392 put_arm_insn (htab, output_bfd, plt0_entry[3],
17393 splt->contents + 12);
5e681ec4 17394
5e681ec4 17395#ifdef FOUR_WORD_PLT
00a97672
RS		 17396 /* The displacement value goes in the otherwise-unused
17397 last word of the second entry. */
17398 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 17399#else
00a97672 17400 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 17401#endif
00a97672 17402 }
f7a74f8c 17403 }
252b5132
RH		 17404
17405 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17406 really seem like the right value. */
74541ad4
AM		 17407 if (splt->output_section->owner == output_bfd)
17408 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 17409
0855e32b
NS		 17410 if (htab->dt_tlsdesc_plt)
17411 {
17412 bfd_vma got_address
17413 = sgot->output_section->vma + sgot->output_offset;
17414 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17415 + htab->root.sgot->output_offset);
17416 bfd_vma plt_address
17417 = splt->output_section->vma + splt->output_offset;
17418
b38cadfb 17419 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17420 splt->contents + htab->dt_tlsdesc_plt,
17421 dl_tlsdesc_lazy_trampoline, 6);
17422
17423 bfd_put_32 (output_bfd,
17424 gotplt_address + htab->dt_tlsdesc_got
17425 - (plt_address + htab->dt_tlsdesc_plt)
17426 - dl_tlsdesc_lazy_trampoline[6],
17427 splt->contents + htab->dt_tlsdesc_plt + 24);
17428 bfd_put_32 (output_bfd,
17429 got_address - (plt_address + htab->dt_tlsdesc_plt)
17430 - dl_tlsdesc_lazy_trampoline[7],
17431 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
17432 }
17433
17434 if (htab->tls_trampoline)
17435 {
b38cadfb 17436 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17437 splt->contents + htab->tls_trampoline,
17438 tls_trampoline, 3);
17439#ifdef FOUR_WORD_PLT
17440 bfd_put_32 (output_bfd, 0x00000000,
17441 splt->contents + htab->tls_trampoline + 12);
b38cadfb 17442#endif
0855e32b
NS		 17443 }
17444
0e1862bb
L		 17445 if (htab->vxworks_p
17446 && !bfd_link_pic (info)
17447 && htab->root.splt->size > 0)
00a97672
RS		 17448 {
17449 /* Correct the .rel(a).plt.unloaded relocations. They will have
17450 incorrect symbol indexes. */
17451 int num_plts;
eed62c48 17452 unsigned char *p;
00a97672 17453
362d30a1 17454 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 17455 / htab->plt_entry_size);
17456 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17457
17458 for (; num_plts; num_plts--)
17459 {
17460 Elf_Internal_Rela rel;
17461
17462 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17463 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17464 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17465 p += RELOC_SIZE (htab);
17466
17467 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17468 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17469 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17470 p += RELOC_SIZE (htab);
17471 }
17472 }
252b5132
RH		 17473 }
17474
99059e56
RM		 17475 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
17476 /* NaCl uses a special first entry in .iplt too. */
17477 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17478
252b5132 17479 /* Fill in the first three entries in the global offset table. */
229fcec5 17480 if (sgot)
252b5132 17481 {
229fcec5
MM		 17482 if (sgot->size > 0)
17483 {
17484 if (sdyn == NULL)
17485 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17486 else
17487 bfd_put_32 (output_bfd,
17488 sdyn->output_section->vma + sdyn->output_offset,
17489 sgot->contents);
17490 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17491 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17492 }
252b5132 17493
229fcec5
MM		 17494 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17495 }
252b5132 17496
e8b09b87
CL		 17497 /* At the very end of the .rofixup section is a pointer to the GOT. */
17498 if (htab->fdpic_p && htab->srofixup != NULL)
17499 {
17500 struct elf_link_hash_entry *hgot = htab->root.hgot;
17501
17502 bfd_vma got_value = hgot->root.u.def.value
17503 + hgot->root.u.def.section->output_section->vma
17504 + hgot->root.u.def.section->output_offset;
17505
17506 arm_elf_add_rofixup(output_bfd, htab->srofixup, got_value);
17507
17508 /* Make sure we allocated and generated the same number of fixups. */
17509 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17510 }
17511
b34976b6 17512 return TRUE;
252b5132
RH		 17513}
17514
ba96a88f 17515static void
57e8b36a 17516elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 17517{
9b485d32 17518 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 17519 struct elf32_arm_link_hash_table *globals;
ac4c9b04 17520 struct elf_segment_map *m;
ba96a88f
NC		 17521
17522 i_ehdrp = elf_elfheader (abfd);
17523
94a3258f
PB		 17524 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17525 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
17526 else
7394f108 17527 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 17528 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 17529
93204d3a
PB		 17530 if (link_info)
17531 {
17532 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 17533 if (globals != NULL && globals->byteswap_code)
93204d3a 17534 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 17535
17536 if (globals->fdpic_p)
17537 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 17538 }
3bfcb652
NC		 17539
17540 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17541 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17542 {
17543 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 17544 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 17545 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17546 else
17547 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17548 }
ac4c9b04
MG		 17549
17550 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 17551 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 17552 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17553 {
17554 unsigned int j;
17555
17556 if (m->count == 0)
17557 continue;
17558 for (j = 0; j < m->count; j++)
17559 {
f0728ee3 17560 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 17561 break;
17562 }
17563 if (j == m->count)
17564 {
17565 m->p_flags = PF_X;
17566 m->p_flags_valid = 1;
17567 }
17568 }
ba96a88f
NC		 17569}
17570
99e4ae17 17571static enum elf_reloc_type_class
7e612e98
AM		 17572elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17573 const asection *rel_sec ATTRIBUTE_UNUSED,
17574 const Elf_Internal_Rela *rela)
99e4ae17 17575{
f51e552e 17576 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 17577 {
17578 case R_ARM_RELATIVE:
17579 return reloc_class_relative;
17580 case R_ARM_JUMP_SLOT:
17581 return reloc_class_plt;
17582 case R_ARM_COPY:
17583 return reloc_class_copy;
109575d7
JW		 17584 case R_ARM_IRELATIVE:
17585 return reloc_class_ifunc;
99e4ae17
AJ		 17586 default:
17587 return reloc_class_normal;
17588 }
17589}
17590
e489d0ae 17591static void
57e8b36a 17592elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 17593{
5a6c6817 17594 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 17595}
17596
40a18ebd
NC		 17597/* Return TRUE if this is an unwinding table entry. */
17598
17599static bfd_boolean
17600is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17601{
0112cd26
NC		 17602 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
17603 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 17604}
17605
17606
17607/* Set the type and flags for an ARM section. We do this by
17608 the section name, which is a hack, but ought to work. */
17609
17610static bfd_boolean
17611elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17612{
17613 const char * name;
17614
17615 name = bfd_get_section_name (abfd, sec);
17616
17617 if (is_arm_elf_unwind_section_name (abfd, name))
17618 {
17619 hdr->sh_type = SHT_ARM_EXIDX;
17620 hdr->sh_flags |= SHF_LINK_ORDER;
17621 }
ac4c9b04 17622
f0728ee3
AV		 17623 if (sec->flags & SEC_ELF_PURECODE)
17624 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 17625
40a18ebd
NC		 17626 return TRUE;
17627}
17628
6dc132d9
L		 17629/* Handle an ARM specific section when reading an object file. This is
17630 called when bfd_section_from_shdr finds a section with an unknown
17631 type. */
40a18ebd
NC		 17632
17633static bfd_boolean
17634elf32_arm_section_from_shdr (bfd *abfd,
17635 Elf_Internal_Shdr * hdr,
6dc132d9
L		 17636 const char *name,
17637 int shindex)
40a18ebd
NC		 17638{
17639 /* There ought to be a place to keep ELF backend specific flags, but
17640 at the moment there isn't one. We just keep track of the
17641 sections by their name, instead. Fortunately, the ABI gives
17642 names for all the ARM specific sections, so we will probably get
17643 away with this. */
17644 switch (hdr->sh_type)
17645 {
17646 case SHT_ARM_EXIDX:
0951f019
RE		 17647 case SHT_ARM_PREEMPTMAP:
17648 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 17649 break;
17650
17651 default:
17652 return FALSE;
17653 }
17654
6dc132d9 17655 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 17656 return FALSE;
17657
17658 return TRUE;
17659}
e489d0ae 17660
44444f50
NC		 17661static _arm_elf_section_data *
17662get_arm_elf_section_data (asection * sec)
17663{
47b2e99c
JZ		 17664 if (sec && sec->owner && is_arm_elf (sec->owner))
17665 return elf32_arm_section_data (sec);
44444f50
NC		 17666 else
17667 return NULL;
8e3de13a
NC		 17668}
17669
4e617b1e
PB		 17670typedef struct
17671{
57402f1e 17672 void *flaginfo;
4e617b1e 17673 struct bfd_link_info *info;
91a5743d
PB		 17674 asection *sec;
17675 int sec_shndx;
6e0b88f1
AM		 17676 int (*func) (void *, const char *, Elf_Internal_Sym *,
17677 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 17678} output_arch_syminfo;
17679
17680enum map_symbol_type
17681{
17682 ARM_MAP_ARM,
17683 ARM_MAP_THUMB,
17684 ARM_MAP_DATA
17685};
17686
17687
7413f23f 17688/* Output a single mapping symbol. */
4e617b1e
PB		 17689
17690static bfd_boolean
7413f23f
DJ		 17691elf32_arm_output_map_sym (output_arch_syminfo *osi,
17692 enum map_symbol_type type,
17693 bfd_vma offset)
4e617b1e
PB		 17694{
17695 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 17696 Elf_Internal_Sym sym;
17697
91a5743d
PB		 17698 sym.st_value = osi->sec->output_section->vma
17699 + osi->sec->output_offset
17700 + offset;
4e617b1e
PB		 17701 sym.st_size = 0;
17702 sym.st_other = 0;
17703 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 17704 sym.st_shndx = osi->sec_shndx;
35fc36a8 17705 sym.st_target_internal = 0;
fe33d2fa 17706 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 17707 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 17708}
17709
34e77a92
RS		 17710/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17711 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 17712
17713static bfd_boolean
34e77a92
RS		 17714elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
17715 bfd_boolean is_iplt_entry_p,
17716 union gotplt_union *root_plt,
17717 struct arm_plt_info *arm_plt)
4e617b1e 17718{
4e617b1e 17719 struct elf32_arm_link_hash_table *htab;
34e77a92 17720 bfd_vma addr, plt_header_size;
4e617b1e 17721
34e77a92 17722 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 17723 return TRUE;
17724
4dfe6ac6
NC		 17725 htab = elf32_arm_hash_table (osi->info);
17726 if (htab == NULL)
17727 return FALSE;
17728
34e77a92
RS		 17729 if (is_iplt_entry_p)
17730 {
17731 osi->sec = htab->root.iplt;
17732 plt_header_size = 0;
17733 }
17734 else
17735 {
17736 osi->sec = htab->root.splt;
17737 plt_header_size = htab->plt_header_size;
17738 }
17739 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
17740 (osi->info->output_bfd, osi->sec->output_section));
17741
17742 addr = root_plt->offset & -2;
4e617b1e
PB		 17743 if (htab->symbian_p)
17744 {
7413f23f 17745 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17746 return FALSE;
7413f23f 17747 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 17748 return FALSE;
17749 }
17750 else if (htab->vxworks_p)
17751 {
7413f23f 17752 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17753 return FALSE;
7413f23f 17754 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 17755 return FALSE;
7413f23f 17756 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 17757 return FALSE;
7413f23f 17758 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 17759 return FALSE;
17760 }
b38cadfb
NC		 17761 else if (htab->nacl_p)
17762 {
17763 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
17764 return FALSE;
17765 }
7801f98f
CL		 17766 else if (htab->fdpic_p)
17767 {
17768 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
17769 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
17770 return FALSE;
17771 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
17772 return FALSE;
17773 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
17774 return FALSE;
17775 if (htab->plt_entry_size == 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry))
17776 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 24))
17777 return FALSE;
17778 }
eed94f8f
NC		 17779 else if (using_thumb_only (htab))
17780 {
17781 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
17782 return FALSE;
6a631e86 17783 }
4e617b1e
PB		 17784 else
17785 {
34e77a92 17786 bfd_boolean thumb_stub_p;
bd97cb95 17787
34e77a92
RS		 17788 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
17789 if (thumb_stub_p)
4e617b1e 17790 {
7413f23f 17791 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 17792 return FALSE;
17793 }
17794#ifdef FOUR_WORD_PLT
7413f23f 17795 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17796 return FALSE;
7413f23f 17797 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 17798 return FALSE;
17799#else
906e58ca 17800 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 17801 so only need to output a mapping symbol for the first PLT entry and
17802 entries with thumb thunks. */
34e77a92 17803 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 17804 {
7413f23f 17805 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 17806 return FALSE;
17807 }
17808#endif
17809 }
17810
17811 return TRUE;
17812}
17813
34e77a92
RS		 17814/* Output mapping symbols for PLT entries associated with H. */
17815
17816static bfd_boolean
17817elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
17818{
17819 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
17820 struct elf32_arm_link_hash_entry *eh;
17821
17822 if (h->root.type == bfd_link_hash_indirect)
17823 return TRUE;
17824
17825 if (h->root.type == bfd_link_hash_warning)
17826 /* When warning symbols are created, they **replace** the "real"
17827 entry in the hash table, thus we never get to see the real
17828 symbol in a hash traversal. So look at it now. */
17829 h = (struct elf_link_hash_entry *) h->root.u.i.link;
17830
17831 eh = (struct elf32_arm_link_hash_entry *) h;
17832 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
17833 &h->plt, &eh->plt);
17834}
17835
4f4faa4d
TP		 17836/* Bind a veneered symbol to its veneer identified by its hash entry
17837 STUB_ENTRY. The veneered location thus loose its symbol. */
17838
17839static void
17840arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
17841{
17842 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
17843
17844 BFD_ASSERT (hash);
17845 hash->root.root.u.def.section = stub_entry->stub_sec;
17846 hash->root.root.u.def.value = stub_entry->stub_offset;
17847 hash->root.size = stub_entry->stub_size;
17848}
17849
7413f23f
DJ		 17850/* Output a single local symbol for a generated stub. */
17851
17852static bfd_boolean
17853elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
17854 bfd_vma offset, bfd_vma size)
17855{
7413f23f
DJ		 17856 Elf_Internal_Sym sym;
17857
7413f23f
DJ		 17858 sym.st_value = osi->sec->output_section->vma
17859 + osi->sec->output_offset
17860 + offset;
17861 sym.st_size = size;
17862 sym.st_other = 0;
17863 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
17864 sym.st_shndx = osi->sec_shndx;
35fc36a8 17865 sym.st_target_internal = 0;
57402f1e 17866 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 17867}
4e617b1e 17868
da5938a2 17869static bfd_boolean
8029a119
NC		 17870arm_map_one_stub (struct bfd_hash_entry * gen_entry,
17871 void * in_arg)
da5938a2
NC		 17872{
17873 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 17874 asection *stub_sec;
17875 bfd_vma addr;
7413f23f 17876 char *stub_name;
9a008db3 17877 output_arch_syminfo *osi;
d3ce72d0 17878 const insn_sequence *template_sequence;
461a49ca
DJ		 17879 enum stub_insn_type prev_type;
17880 int size;
17881 int i;
17882 enum map_symbol_type sym_type;
da5938a2
NC		 17883
17884 /* Massage our args to the form they really have. */
17885 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 17886 osi = (output_arch_syminfo *) in_arg;
da5938a2 17887
da5938a2
NC		 17888 stub_sec = stub_entry->stub_sec;
17889
17890 /* Ensure this stub is attached to the current section being
7413f23f 17891 processed. */
da5938a2
NC		 17892 if (stub_sec != osi->sec)
17893 return TRUE;
17894
7413f23f 17895 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 17896 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 17897
17898 if (arm_stub_sym_claimed (stub_entry->stub_type))
17899 arm_stub_claim_sym (stub_entry);
17900 else
7413f23f 17901 {
4f4faa4d
TP		 17902 stub_name = stub_entry->output_name;
17903 switch (template_sequence[0].type)
17904 {
17905 case ARM_TYPE:
17906 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
17907 stub_entry->stub_size))
17908 return FALSE;
17909 break;
17910 case THUMB16_TYPE:
17911 case THUMB32_TYPE:
17912 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
17913 stub_entry->stub_size))
17914 return FALSE;
17915 break;
17916 default:
17917 BFD_FAIL ();
17918 return 0;
17919 }
7413f23f 17920 }
da5938a2 17921
461a49ca
DJ		 17922 prev_type = DATA_TYPE;
17923 size = 0;
17924 for (i = 0; i < stub_entry->stub_template_size; i++)
17925 {
d3ce72d0 17926 switch (template_sequence[i].type)
461a49ca
DJ		 17927 {
17928 case ARM_TYPE:
17929 sym_type = ARM_MAP_ARM;
17930 break;
17931
17932 case THUMB16_TYPE:
48229727 17933 case THUMB32_TYPE:
461a49ca
DJ		 17934 sym_type = ARM_MAP_THUMB;
17935 break;
17936
17937 case DATA_TYPE:
17938 sym_type = ARM_MAP_DATA;
17939 break;
17940
17941 default:
17942 BFD_FAIL ();
4e31c731 17943 return FALSE;
461a49ca
DJ		 17944 }
17945
d3ce72d0 17946 if (template_sequence[i].type != prev_type)
461a49ca 17947 {
d3ce72d0 17948 prev_type = template_sequence[i].type;
461a49ca
DJ		 17949 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
17950 return FALSE;
17951 }
17952
d3ce72d0 17953 switch (template_sequence[i].type)
461a49ca
DJ		 17954 {
17955 case ARM_TYPE:
48229727 17956 case THUMB32_TYPE:
461a49ca
DJ		 17957 size += 4;
17958 break;
17959
17960 case THUMB16_TYPE:
17961 size += 2;
17962 break;
17963
17964 case DATA_TYPE:
17965 size += 4;
17966 break;
17967
17968 default:
17969 BFD_FAIL ();
4e31c731 17970 return FALSE;
461a49ca
DJ		 17971 }
17972 }
17973
da5938a2
NC		 17974 return TRUE;
17975}
17976
33811162
DG		 17977/* Output mapping symbols for linker generated sections,
17978 and for those data-only sections that do not have a
17979 $d. */
4e617b1e
PB		 17980
17981static bfd_boolean
17982elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 17983 struct bfd_link_info *info,
57402f1e 17984 void *flaginfo,
6e0b88f1
AM		 17985 int (*func) (void *, const char *,
17986 Elf_Internal_Sym *,
17987 asection *,
17988 struct elf_link_hash_entry *))
4e617b1e
PB		 17989{
17990 output_arch_syminfo osi;
17991 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 17992 bfd_vma offset;
17993 bfd_size_type size;
33811162 17994 bfd *input_bfd;
4e617b1e
PB		 17995
17996 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17997 if (htab == NULL)
17998 return FALSE;
17999
906e58ca 18000 check_use_blx (htab);
91a5743d 18001
57402f1e 18002 osi.flaginfo = flaginfo;
4e617b1e
PB		 18003 osi.info = info;
18004 osi.func = func;
906e58ca 18005
33811162
DG		 18006 /* Add a $d mapping symbol to data-only sections that
18007 don't have any mapping symbol. This may result in (harmless) redundant
18008 mapping symbols. */
18009 for (input_bfd = info->input_bfds;
18010 input_bfd != NULL;
c72f2fb2 18011 input_bfd = input_bfd->link.next)
33811162
DG		 18012 {
18013 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18014 for (osi.sec = input_bfd->sections;
18015 osi.sec != NULL;
18016 osi.sec = osi.sec->next)
18017 {
18018 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 18019 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18020 != 0)
33811162
DG		 18021 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18022 == SEC_HAS_CONTENTS
18023 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 18024 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 18025 && osi.sec->size > 0
18026 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 18027 {
18028 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18029 (output_bfd, osi.sec->output_section);
18030 if (osi.sec_shndx != (int)SHN_BAD)
18031 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18032 }
18033 }
18034 }
18035
91a5743d
PB		 18036 /* ARM->Thumb glue. */
18037 if (htab->arm_glue_size > 0)
18038 {
3d4d4302
AM		 18039 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18040 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 18041
18042 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18043 (output_bfd, osi.sec->output_section);
0e1862bb 18044 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 18045 || htab->pic_veneer)
18046 size = ARM2THUMB_PIC_GLUE_SIZE;
18047 else if (htab->use_blx)
18048 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18049 else
18050 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 18051
91a5743d
PB		 18052 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18053 {
7413f23f
DJ		 18054 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18055 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 18056 }
18057 }
18058
18059 /* Thumb->ARM glue. */
18060 if (htab->thumb_glue_size > 0)
18061 {
3d4d4302
AM		 18062 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18063 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 18064
18065 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18066 (output_bfd, osi.sec->output_section);
18067 size = THUMB2ARM_GLUE_SIZE;
18068
18069 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18070 {
7413f23f
DJ		 18071 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18072 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 18073 }
18074 }
18075
845b51d6
PB		 18076 /* ARMv4 BX veneers. */
18077 if (htab->bx_glue_size > 0)
18078 {
3d4d4302
AM		 18079 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18080 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 18081
18082 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18083 (output_bfd, osi.sec->output_section);
18084
7413f23f 18085 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 18086 }
18087
8029a119
NC		 18088 /* Long calls stubs. */
18089 if (htab->stub_bfd && htab->stub_bfd->sections)
18090 {
da5938a2 18091 asection* stub_sec;
8029a119 18092
da5938a2
NC		 18093 for (stub_sec = htab->stub_bfd->sections;
18094 stub_sec != NULL;
8029a119
NC		 18095 stub_sec = stub_sec->next)
18096 {
18097 /* Ignore non-stub sections. */
18098 if (!strstr (stub_sec->name, STUB_SUFFIX))
18099 continue;
da5938a2 18100
8029a119 18101 osi.sec = stub_sec;
da5938a2 18102
8029a119
NC		 18103 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18104 (output_bfd, osi.sec->output_section);
da5938a2 18105
8029a119
NC		 18106 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18107 }
18108 }
da5938a2 18109
91a5743d 18110 /* Finally, output mapping symbols for the PLT. */
34e77a92 18111 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 18112 {
34e77a92
RS		 18113 osi.sec = htab->root.splt;
18114 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18115 (output_bfd, osi.sec->output_section));
18116
18117 /* Output mapping symbols for the plt header. SymbianOS does not have a
18118 plt header. */
18119 if (htab->vxworks_p)
18120 {
18121 /* VxWorks shared libraries have no PLT header. */
0e1862bb 18122 if (!bfd_link_pic (info))
34e77a92
RS		 18123 {
18124 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18125 return FALSE;
18126 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18127 return FALSE;
18128 }
18129 }
b38cadfb
NC		 18130 else if (htab->nacl_p)
18131 {
18132 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18133 return FALSE;
18134 }
eed94f8f
NC		 18135 else if (using_thumb_only (htab))
18136 {
18137 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18138 return FALSE;
18139 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18140 return FALSE;
18141 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18142 return FALSE;
18143 }
e8b09b87 18144 else if (!htab->symbian_p && !htab->fdpic_p)
4e617b1e 18145 {
7413f23f 18146 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 18147 return FALSE;
34e77a92
RS		 18148#ifndef FOUR_WORD_PLT
18149 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 18150 return FALSE;
34e77a92 18151#endif
4e617b1e
PB		 18152 }
18153 }
99059e56
RM		 18154 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
18155 {
18156 /* NaCl uses a special first entry in .iplt too. */
18157 osi.sec = htab->root.iplt;
18158 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18159 (output_bfd, osi.sec->output_section));
18160 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18161 return FALSE;
18162 }
34e77a92
RS		 18163 if ((htab->root.splt && htab->root.splt->size > 0)
18164 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 18165 {
34e77a92
RS		 18166 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18167 for (input_bfd = info->input_bfds;
18168 input_bfd != NULL;
c72f2fb2 18169 input_bfd = input_bfd->link.next)
34e77a92
RS		 18170 {
18171 struct arm_local_iplt_info **local_iplt;
18172 unsigned int i, num_syms;
4e617b1e 18173
34e77a92
RS		 18174 local_iplt = elf32_arm_local_iplt (input_bfd);
18175 if (local_iplt != NULL)
18176 {
18177 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18178 for (i = 0; i < num_syms; i++)
18179 if (local_iplt[i] != NULL
18180 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
18181 &local_iplt[i]->root,
18182 &local_iplt[i]->arm))
18183 return FALSE;
18184 }
18185 }
18186 }
0855e32b
NS		 18187 if (htab->dt_tlsdesc_plt != 0)
18188 {
18189 /* Mapping symbols for the lazy tls trampoline. */
18190 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
18191 return FALSE;
b38cadfb 18192
0855e32b
NS		 18193 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18194 htab->dt_tlsdesc_plt + 24))
18195 return FALSE;
18196 }
18197 if (htab->tls_trampoline != 0)
18198 {
18199 /* Mapping symbols for the tls trampoline. */
18200 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18201 return FALSE;
18202#ifdef FOUR_WORD_PLT
18203 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18204 htab->tls_trampoline + 12))
18205 return FALSE;
b38cadfb 18206#endif
0855e32b 18207 }
b38cadfb 18208
4e617b1e
PB		 18209 return TRUE;
18210}
18211
54ddd295
TP		 18212/* Filter normal symbols of CMSE entry functions of ABFD to include in
18213 the import library. All SYMCOUNT symbols of ABFD can be examined
18214 from their pointers in SYMS. Pointers of symbols to keep should be
18215 stored continuously at the beginning of that array.
18216
18217 Returns the number of symbols to keep. */
18218
18219static unsigned int
18220elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18221 struct bfd_link_info *info,
18222 asymbol **syms, long symcount)
18223{
18224 size_t maxnamelen;
18225 char *cmse_name;
18226 long src_count, dst_count = 0;
18227 struct elf32_arm_link_hash_table *htab;
18228
18229 htab = elf32_arm_hash_table (info);
18230 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18231 symcount = 0;
18232
18233 maxnamelen = 128;
18234 cmse_name = (char *) bfd_malloc (maxnamelen);
18235 for (src_count = 0; src_count < symcount; src_count++)
18236 {
18237 struct elf32_arm_link_hash_entry *cmse_hash;
18238 asymbol *sym;
18239 flagword flags;
18240 char *name;
18241 size_t namelen;
18242
18243 sym = syms[src_count];
18244 flags = sym->flags;
18245 name = (char *) bfd_asymbol_name (sym);
18246
18247 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18248 continue;
18249 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18250 continue;
18251
18252 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18253 if (namelen > maxnamelen)
18254 {
18255 cmse_name = (char *)
18256 bfd_realloc (cmse_name, namelen);
18257 maxnamelen = namelen;
18258 }
18259 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18260 cmse_hash = (struct elf32_arm_link_hash_entry *)
18261 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
18262
18263 if (!cmse_hash
18264 || (cmse_hash->root.root.type != bfd_link_hash_defined
18265 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18266 || cmse_hash->root.type != STT_FUNC)
18267 continue;
18268
18269 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
18270 continue;
18271
18272 syms[dst_count++] = sym;
18273 }
18274 free (cmse_name);
18275
18276 syms[dst_count] = NULL;
18277
18278 return dst_count;
18279}
18280
18281/* Filter symbols of ABFD to include in the import library. All
18282 SYMCOUNT symbols of ABFD can be examined from their pointers in
18283 SYMS. Pointers of symbols to keep should be stored continuously at
18284 the beginning of that array.
18285
18286 Returns the number of symbols to keep. */
18287
18288static unsigned int
18289elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18290 struct bfd_link_info *info,
18291 asymbol **syms, long symcount)
18292{
18293 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18294
046734ff
TP		 18295 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18296 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18297 library to be a relocatable object file. */
18298 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 18299 if (globals->cmse_implib)
18300 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18301 else
18302 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18303}
18304
e489d0ae
PB		 18305/* Allocate target specific section data. */
18306
18307static bfd_boolean
18308elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18309{
f592407e
AM		 18310 if (!sec->used_by_bfd)
18311 {
18312 _arm_elf_section_data *sdata;
18313 bfd_size_type amt = sizeof (*sdata);
e489d0ae 18314
21d799b5 18315 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 18316 if (sdata == NULL)
18317 return FALSE;
18318 sec->used_by_bfd = sdata;
18319 }
e489d0ae
PB		 18320
18321 return _bfd_elf_new_section_hook (abfd, sec);
18322}
18323
18324
18325/* Used to order a list of mapping symbols by address. */
18326
18327static int
18328elf32_arm_compare_mapping (const void * a, const void * b)
18329{
7f6a71ff
JM		 18330 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18331 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18332
18333 if (amap->vma > bmap->vma)
18334 return 1;
18335 else if (amap->vma < bmap->vma)
18336 return -1;
18337 else if (amap->type > bmap->type)
18338 /* Ensure results do not depend on the host qsort for objects with
18339 multiple mapping symbols at the same address by sorting on type
18340 after vma. */
18341 return 1;
18342 else if (amap->type < bmap->type)
18343 return -1;
18344 else
18345 return 0;
e489d0ae
PB		 18346}
18347
2468f9c9
PB		 18348/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18349
18350static unsigned long
18351offset_prel31 (unsigned long addr, bfd_vma offset)
18352{
18353 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18354}
18355
18356/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18357 relocations. */
18358
18359static void
18360copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18361{
18362 unsigned long first_word = bfd_get_32 (output_bfd, from);
18363 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 18364
2468f9c9
PB		 18365 /* High bit of first word is supposed to be zero. */
18366 if ((first_word & 0x80000000ul) == 0)
18367 first_word = offset_prel31 (first_word, offset);
b38cadfb 18368
2468f9c9
PB		 18369 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18370 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18371 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18372 second_word = offset_prel31 (second_word, offset);
b38cadfb 18373
2468f9c9
PB		 18374 bfd_put_32 (output_bfd, first_word, to);
18375 bfd_put_32 (output_bfd, second_word, to + 4);
18376}
e489d0ae 18377
48229727
JB		 18378/* Data for make_branch_to_a8_stub(). */
18379
b38cadfb
NC		 18380struct a8_branch_to_stub_data
18381{
48229727
JB		 18382 asection *writing_section;
18383 bfd_byte *contents;
18384};
18385
18386
18387/* Helper to insert branches to Cortex-A8 erratum stubs in the right
18388 places for a particular section. */
18389
18390static bfd_boolean
18391make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 18392 void *in_arg)
48229727
JB		 18393{
18394 struct elf32_arm_stub_hash_entry *stub_entry;
18395 struct a8_branch_to_stub_data *data;
18396 bfd_byte *contents;
18397 unsigned long branch_insn;
18398 bfd_vma veneered_insn_loc, veneer_entry_loc;
18399 bfd_signed_vma branch_offset;
18400 bfd *abfd;
8d9d9490 18401 unsigned int loc;
48229727
JB		 18402
18403 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18404 data = (struct a8_branch_to_stub_data *) in_arg;
18405
18406 if (stub_entry->target_section != data->writing_section
4563a860 18407 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 18408 return TRUE;
18409
18410 contents = data->contents;
18411
8d9d9490
TP		 18412 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18413 generated when both source and target are in the same section. */
48229727
JB		 18414 veneered_insn_loc = stub_entry->target_section->output_section->vma
18415 + stub_entry->target_section->output_offset
8d9d9490 18416 + stub_entry->source_value;
48229727
JB		 18417
18418 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18419 + stub_entry->stub_sec->output_offset
18420 + stub_entry->stub_offset;
18421
18422 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18423 veneered_insn_loc &= ~3u;
18424
18425 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18426
18427 abfd = stub_entry->target_section->owner;
8d9d9490 18428 loc = stub_entry->source_value;
48229727
JB		 18429
18430 /* We attempt to avoid this condition by setting stubs_always_after_branch
18431 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18432 This check is just to be on the safe side... */
18433 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18434 {
871b3ab2 18435 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 18436 "allocated in unsafe location"), abfd);
48229727
JB		 18437 return FALSE;
18438 }
18439
18440 switch (stub_entry->stub_type)
18441 {
18442 case arm_stub_a8_veneer_b:
18443 case arm_stub_a8_veneer_b_cond:
18444 branch_insn = 0xf0009000;
18445 goto jump24;
18446
18447 case arm_stub_a8_veneer_blx:
18448 branch_insn = 0xf000e800;
18449 goto jump24;
18450
18451 case arm_stub_a8_veneer_bl:
18452 {
18453 unsigned int i1, j1, i2, j2, s;
18454
18455 branch_insn = 0xf000d000;
18456
18457 jump24:
18458 if (branch_offset < -16777216 || branch_offset > 16777214)
18459 {
18460 /* There's not much we can do apart from complain if this
18461 happens. */
871b3ab2 18462 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 18463 "of range (input file too large)"), abfd);
48229727
JB		 18464 return FALSE;
18465 }
18466
18467 /* i1 = not(j1 eor s), so:
18468 not i1 = j1 eor s
18469 j1 = (not i1) eor s. */
18470
18471 branch_insn |= (branch_offset >> 1) & 0x7ff;
18472 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18473 i2 = (branch_offset >> 22) & 1;
18474 i1 = (branch_offset >> 23) & 1;
18475 s = (branch_offset >> 24) & 1;
18476 j1 = (!i1) ^ s;
18477 j2 = (!i2) ^ s;
18478 branch_insn |= j2 << 11;
18479 branch_insn |= j1 << 13;
18480 branch_insn |= s << 26;
18481 }
18482 break;
18483
18484 default:
18485 BFD_FAIL ();
18486 return FALSE;
18487 }
18488
8d9d9490
TP		 18489 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18490 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 18491
18492 return TRUE;
18493}
18494
a504d23a
LA		 18495/* Beginning of stm32l4xx work-around. */
18496
18497/* Functions encoding instructions necessary for the emission of the
18498 fix-stm32l4xx-629360.
18499 Encoding is extracted from the
18500 ARM (C) Architecture Reference Manual
18501 ARMv7-A and ARMv7-R edition
18502 ARM DDI 0406C.b (ID072512). */
18503
18504static inline bfd_vma
82188b29 18505create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 18506{
18507 /* A8.8.18 B (A8-334)
18508 B target_address (Encoding T4). */
18509 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18510 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18511 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18512
a504d23a
LA		 18513 int s = ((branch_offset & 0x1000000) >> 24);
18514 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18515 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18516
18517 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18518 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18519
18520 bfd_vma patched_inst = 0xf0009000
18521 | s << 26 /* S. */
18522 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18523 | j1 << 13 /* J1. */
18524 | j2 << 11 /* J2. */
18525 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18526
18527 return patched_inst;
18528}
18529
18530static inline bfd_vma
18531create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18532{
18533 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18534 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18535 bfd_vma patched_inst = 0xe8900000
18536 | (/*W=*/wback << 21)
18537 | (base_reg << 16)
18538 | (reg_mask & 0x0000ffff);
18539
18540 return patched_inst;
18541}
18542
18543static inline bfd_vma
18544create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18545{
18546 /* A8.8.60 LDMDB/LDMEA (A8-402)
18547 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18548 bfd_vma patched_inst = 0xe9100000
18549 | (/*W=*/wback << 21)
18550 | (base_reg << 16)
18551 | (reg_mask & 0x0000ffff);
18552
18553 return patched_inst;
18554}
18555
18556static inline bfd_vma
18557create_instruction_mov (int target_reg, int source_reg)
18558{
18559 /* A8.8.103 MOV (register) (A8-486)
18560 MOV Rd, Rm (Encoding T1). */
18561 bfd_vma patched_inst = 0x4600
18562 | (target_reg & 0x7)
18563 | ((target_reg & 0x8) >> 3) << 7
18564 | (source_reg << 3);
18565
18566 return patched_inst;
18567}
18568
18569static inline bfd_vma
18570create_instruction_sub (int target_reg, int source_reg, int value)
18571{
18572 /* A8.8.221 SUB (immediate) (A8-708)
18573 SUB Rd, Rn, #value (Encoding T3). */
18574 bfd_vma patched_inst = 0xf1a00000
18575 | (target_reg << 8)
18576 | (source_reg << 16)
18577 | (/*S=*/0 << 20)
18578 | ((value & 0x800) >> 11) << 26
18579 | ((value & 0x700) >> 8) << 12
18580 | (value & 0x0ff);
18581
18582 return patched_inst;
18583}
18584
18585static inline bfd_vma
9239bbd3 18586create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 18587 int first_reg)
18588{
18589 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18590 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18591 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 18592 | (/*W=*/wback << 21)
18593 | (base_reg << 16)
9239bbd3
CM		 18594 | (num_words & 0x000000ff)
18595 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 18596 | (first_reg & 0x00000001) << 22;
18597
18598 return patched_inst;
18599}
18600
18601static inline bfd_vma
9239bbd3
CM		 18602create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18603 int first_reg)
a504d23a
LA		 18604{
18605 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18606 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18607 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 18608 | (base_reg << 16)
9239bbd3
CM		 18609 | (num_words & 0x000000ff)
18610 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 18611 | (first_reg & 0x00000001) << 22;
18612
18613 return patched_inst;
18614}
18615
18616static inline bfd_vma
18617create_instruction_udf_w (int value)
18618{
18619 /* A8.8.247 UDF (A8-758)
18620 Undefined (Encoding T2). */
18621 bfd_vma patched_inst = 0xf7f0a000
18622 | (value & 0x00000fff)
18623 | (value & 0x000f0000) << 16;
18624
18625 return patched_inst;
18626}
18627
18628static inline bfd_vma
18629create_instruction_udf (int value)
18630{
18631 /* A8.8.247 UDF (A8-758)
18632 Undefined (Encoding T1). */
18633 bfd_vma patched_inst = 0xde00
18634 | (value & 0xff);
18635
18636 return patched_inst;
18637}
18638
18639/* Functions writing an instruction in memory, returning the next
18640 memory position to write to. */
18641
18642static inline bfd_byte *
18643push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18644 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18645{
18646 put_thumb2_insn (htab, output_bfd, insn, pt);
18647 return pt + 4;
18648}
18649
18650static inline bfd_byte *
18651push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
18652 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18653{
18654 put_thumb_insn (htab, output_bfd, insn, pt);
18655 return pt + 2;
18656}
18657
18658/* Function filling up a region in memory with T1 and T2 UDFs taking
18659 care of alignment. */
18660
18661static bfd_byte *
18662stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 18663 bfd * output_bfd,
18664 const bfd_byte * const base_stub_contents,
18665 bfd_byte * const from_stub_contents,
18666 const bfd_byte * const end_stub_contents)
a504d23a
LA		 18667{
18668 bfd_byte *current_stub_contents = from_stub_contents;
18669
18670 /* Fill the remaining of the stub with deterministic contents : UDF
18671 instructions.
18672 Check if realignment is needed on modulo 4 frontier using T1, to
18673 further use T2. */
18674 if ((current_stub_contents < end_stub_contents)
18675 && !((current_stub_contents - base_stub_contents) % 2)
18676 && ((current_stub_contents - base_stub_contents) % 4))
18677 current_stub_contents =
18678 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18679 create_instruction_udf (0));
18680
18681 for (; current_stub_contents < end_stub_contents;)
18682 current_stub_contents =
18683 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18684 create_instruction_udf_w (0));
18685
18686 return current_stub_contents;
18687}
18688
18689/* Functions writing the stream of instructions equivalent to the
18690 derived sequence for ldmia, ldmdb, vldm respectively. */
18691
18692static void
18693stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
18694 bfd * output_bfd,
18695 const insn32 initial_insn,
18696 const bfd_byte *const initial_insn_addr,
18697 bfd_byte *const base_stub_contents)
18698{
18699 int wback = (initial_insn & 0x00200000) >> 21;
18700 int ri, rn = (initial_insn & 0x000F0000) >> 16;
18701 int insn_all_registers = initial_insn & 0x0000ffff;
18702 int insn_low_registers, insn_high_registers;
18703 int usable_register_mask;
b25e998d 18704 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18705 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18706 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
18707 bfd_byte *current_stub_contents = base_stub_contents;
18708
18709 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
18710
18711 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18712 smaller than 8 registers load sequences that do not cause the
18713 hardware issue. */
18714 if (nb_registers <= 8)
18715 {
18716 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18717 current_stub_contents =
18718 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18719 initial_insn);
18720
18721 /* B initial_insn_addr+4. */
18722 if (!restore_pc)
18723 current_stub_contents =
18724 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18725 create_instruction_branch_absolute
82188b29 18726 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18727
18728 /* Fill the remaining of the stub with deterministic contents. */
18729 current_stub_contents =
18730 stm32l4xx_fill_stub_udf (htab, output_bfd,
18731 base_stub_contents, current_stub_contents,
18732 base_stub_contents +
18733 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18734
18735 return;
18736 }
18737
18738 /* - reg_list[13] == 0. */
18739 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
18740
18741 /* - reg_list[14] & reg_list[15] != 1. */
18742 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18743
18744 /* - if (wback==1) reg_list[rn] == 0. */
18745 BFD_ASSERT (!wback || !restore_rn);
18746
18747 /* - nb_registers > 8. */
b25e998d 18748 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 18749
18750 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18751
18752 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
18753 - One with the 7 lowest registers (register mask 0x007F)
18754 This LDM will finally contain between 2 and 7 registers
18755 - One with the 7 highest registers (register mask 0xDF80)
18756 This ldm will finally contain between 2 and 7 registers. */
18757 insn_low_registers = insn_all_registers & 0x007F;
18758 insn_high_registers = insn_all_registers & 0xDF80;
18759
18760 /* A spare register may be needed during this veneer to temporarily
18761 handle the base register. This register will be restored with the
18762 last LDM operation.
18763 The usable register may be any general purpose register (that
18764 excludes PC, SP, LR : register mask is 0x1FFF). */
18765 usable_register_mask = 0x1FFF;
18766
18767 /* Generate the stub function. */
18768 if (wback)
18769 {
18770 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
18771 current_stub_contents =
18772 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18773 create_instruction_ldmia
18774 (rn, /*wback=*/1, insn_low_registers));
18775
18776 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
18777 current_stub_contents =
18778 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18779 create_instruction_ldmia
18780 (rn, /*wback=*/1, insn_high_registers));
18781 if (!restore_pc)
18782 {
18783 /* B initial_insn_addr+4. */
18784 current_stub_contents =
18785 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18786 create_instruction_branch_absolute
82188b29 18787 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18788 }
18789 }
18790 else /* if (!wback). */
18791 {
18792 ri = rn;
18793
18794 /* If Rn is not part of the high-register-list, move it there. */
18795 if (!(insn_high_registers & (1 << rn)))
18796 {
18797 /* Choose a Ri in the high-register-list that will be restored. */
18798 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18799
18800 /* MOV Ri, Rn. */
18801 current_stub_contents =
18802 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18803 create_instruction_mov (ri, rn));
18804 }
18805
18806 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18807 current_stub_contents =
18808 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18809 create_instruction_ldmia
18810 (ri, /*wback=*/1, insn_low_registers));
18811
18812 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18813 current_stub_contents =
18814 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18815 create_instruction_ldmia
18816 (ri, /*wback=*/0, insn_high_registers));
18817
18818 if (!restore_pc)
18819 {
18820 /* B initial_insn_addr+4. */
18821 current_stub_contents =
18822 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18823 create_instruction_branch_absolute
82188b29 18824 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18825 }
18826 }
18827
18828 /* Fill the remaining of the stub with deterministic contents. */
18829 current_stub_contents =
18830 stm32l4xx_fill_stub_udf (htab, output_bfd,
18831 base_stub_contents, current_stub_contents,
18832 base_stub_contents +
18833 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18834}
18835
18836static void
18837stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
18838 bfd * output_bfd,
18839 const insn32 initial_insn,
18840 const bfd_byte *const initial_insn_addr,
18841 bfd_byte *const base_stub_contents)
18842{
18843 int wback = (initial_insn & 0x00200000) >> 21;
18844 int ri, rn = (initial_insn & 0x000f0000) >> 16;
18845 int insn_all_registers = initial_insn & 0x0000ffff;
18846 int insn_low_registers, insn_high_registers;
18847 int usable_register_mask;
18848 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18849 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 18850 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18851 bfd_byte *current_stub_contents = base_stub_contents;
18852
18853 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
18854
18855 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18856 smaller than 8 registers load sequences that do not cause the
18857 hardware issue. */
18858 if (nb_registers <= 8)
18859 {
18860 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18861 current_stub_contents =
18862 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18863 initial_insn);
18864
18865 /* B initial_insn_addr+4. */
18866 current_stub_contents =
18867 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18868 create_instruction_branch_absolute
82188b29 18869 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18870
18871 /* Fill the remaining of the stub with deterministic contents. */
18872 current_stub_contents =
18873 stm32l4xx_fill_stub_udf (htab, output_bfd,
18874 base_stub_contents, current_stub_contents,
18875 base_stub_contents +
18876 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18877
18878 return;
18879 }
18880
18881 /* - reg_list[13] == 0. */
18882 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
18883
18884 /* - reg_list[14] & reg_list[15] != 1. */
18885 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18886
18887 /* - if (wback==1) reg_list[rn] == 0. */
18888 BFD_ASSERT (!wback || !restore_rn);
18889
18890 /* - nb_registers > 8. */
b25e998d 18891 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 18892
18893 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18894
18895 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
18896 - One with the 7 lowest registers (register mask 0x007F)
18897 This LDM will finally contain between 2 and 7 registers
18898 - One with the 7 highest registers (register mask 0xDF80)
18899 This ldm will finally contain between 2 and 7 registers. */
18900 insn_low_registers = insn_all_registers & 0x007F;
18901 insn_high_registers = insn_all_registers & 0xDF80;
18902
18903 /* A spare register may be needed during this veneer to temporarily
18904 handle the base register. This register will be restored with
18905 the last LDM operation.
18906 The usable register may be any general purpose register (that excludes
18907 PC, SP, LR : register mask is 0x1FFF). */
18908 usable_register_mask = 0x1FFF;
18909
18910 /* Generate the stub function. */
18911 if (!wback && !restore_pc && !restore_rn)
18912 {
18913 /* Choose a Ri in the low-register-list that will be restored. */
18914 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18915
18916 /* MOV Ri, Rn. */
18917 current_stub_contents =
18918 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18919 create_instruction_mov (ri, rn));
18920
18921 /* LDMDB Ri!, {R-high-register-list}. */
18922 current_stub_contents =
18923 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18924 create_instruction_ldmdb
18925 (ri, /*wback=*/1, insn_high_registers));
18926
18927 /* LDMDB Ri, {R-low-register-list}. */
18928 current_stub_contents =
18929 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18930 create_instruction_ldmdb
18931 (ri, /*wback=*/0, insn_low_registers));
18932
18933 /* B initial_insn_addr+4. */
18934 current_stub_contents =
18935 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18936 create_instruction_branch_absolute
82188b29 18937 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18938 }
18939 else if (wback && !restore_pc && !restore_rn)
18940 {
18941 /* LDMDB Rn!, {R-high-register-list}. */
18942 current_stub_contents =
18943 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18944 create_instruction_ldmdb
18945 (rn, /*wback=*/1, insn_high_registers));
18946
18947 /* LDMDB Rn!, {R-low-register-list}. */
18948 current_stub_contents =
18949 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18950 create_instruction_ldmdb
18951 (rn, /*wback=*/1, insn_low_registers));
18952
18953 /* B initial_insn_addr+4. */
18954 current_stub_contents =
18955 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18956 create_instruction_branch_absolute
82188b29 18957 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18958 }
18959 else if (!wback && restore_pc && !restore_rn)
18960 {
18961 /* Choose a Ri in the high-register-list that will be restored. */
18962 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18963
18964 /* SUB Ri, Rn, #(4*nb_registers). */
18965 current_stub_contents =
18966 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18967 create_instruction_sub (ri, rn, (4 * nb_registers)));
18968
18969 /* LDMIA Ri!, {R-low-register-list}. */
18970 current_stub_contents =
18971 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18972 create_instruction_ldmia
18973 (ri, /*wback=*/1, insn_low_registers));
18974
18975 /* LDMIA Ri, {R-high-register-list}. */
18976 current_stub_contents =
18977 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18978 create_instruction_ldmia
18979 (ri, /*wback=*/0, insn_high_registers));
18980 }
18981 else if (wback && restore_pc && !restore_rn)
18982 {
18983 /* Choose a Ri in the high-register-list that will be restored. */
18984 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18985
18986 /* SUB Rn, Rn, #(4*nb_registers) */
18987 current_stub_contents =
18988 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18989 create_instruction_sub (rn, rn, (4 * nb_registers)));
18990
18991 /* MOV Ri, Rn. */
18992 current_stub_contents =
18993 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18994 create_instruction_mov (ri, rn));
18995
18996 /* LDMIA Ri!, {R-low-register-list}. */
18997 current_stub_contents =
18998 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18999 create_instruction_ldmia
19000 (ri, /*wback=*/1, insn_low_registers));
19001
19002 /* LDMIA Ri, {R-high-register-list}. */
19003 current_stub_contents =
19004 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19005 create_instruction_ldmia
19006 (ri, /*wback=*/0, insn_high_registers));
19007 }
19008 else if (!wback && !restore_pc && restore_rn)
19009 {
19010 ri = rn;
19011 if (!(insn_low_registers & (1 << rn)))
19012 {
19013 /* Choose a Ri in the low-register-list that will be restored. */
19014 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19015
19016 /* MOV Ri, Rn. */
19017 current_stub_contents =
19018 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19019 create_instruction_mov (ri, rn));
19020 }
19021
19022 /* LDMDB Ri!, {R-high-register-list}. */
19023 current_stub_contents =
19024 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19025 create_instruction_ldmdb
19026 (ri, /*wback=*/1, insn_high_registers));
19027
19028 /* LDMDB Ri, {R-low-register-list}. */
19029 current_stub_contents =
19030 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19031 create_instruction_ldmdb
19032 (ri, /*wback=*/0, insn_low_registers));
19033
19034 /* B initial_insn_addr+4. */
19035 current_stub_contents =
19036 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19037 create_instruction_branch_absolute
82188b29 19038 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19039 }
19040 else if (!wback && restore_pc && restore_rn)
19041 {
19042 ri = rn;
19043 if (!(insn_high_registers & (1 << rn)))
19044 {
19045 /* Choose a Ri in the high-register-list that will be restored. */
19046 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19047 }
19048
19049 /* SUB Ri, Rn, #(4*nb_registers). */
19050 current_stub_contents =
19051 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19052 create_instruction_sub (ri, rn, (4 * nb_registers)));
19053
19054 /* LDMIA Ri!, {R-low-register-list}. */
19055 current_stub_contents =
19056 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19057 create_instruction_ldmia
19058 (ri, /*wback=*/1, insn_low_registers));
19059
19060 /* LDMIA Ri, {R-high-register-list}. */
19061 current_stub_contents =
19062 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19063 create_instruction_ldmia
19064 (ri, /*wback=*/0, insn_high_registers));
19065 }
19066 else if (wback && restore_rn)
19067 {
19068 /* The assembler should not have accepted to encode this. */
19069 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19070 "undefined behavior.\n");
19071 }
19072
19073 /* Fill the remaining of the stub with deterministic contents. */
19074 current_stub_contents =
19075 stm32l4xx_fill_stub_udf (htab, output_bfd,
19076 base_stub_contents, current_stub_contents,
19077 base_stub_contents +
19078 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19079
19080}
19081
19082static void
19083stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19084 bfd * output_bfd,
19085 const insn32 initial_insn,
19086 const bfd_byte *const initial_insn_addr,
19087 bfd_byte *const base_stub_contents)
19088{
9239bbd3 19089 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 19090 bfd_byte *current_stub_contents = base_stub_contents;
19091
19092 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19093
19094 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 19095 smaller than 8 words load sequences that do not cause the
a504d23a 19096 hardware issue. */
9239bbd3 19097 if (num_words <= 8)
a504d23a
LA		 19098 {
19099 /* Untouched instruction. */
19100 current_stub_contents =
19101 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19102 initial_insn);
19103
19104 /* B initial_insn_addr+4. */
19105 current_stub_contents =
19106 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19107 create_instruction_branch_absolute
82188b29 19108 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19109 }
19110 else
19111 {
9eaff861 19112 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 19113 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 19114 bfd_boolean is_ia_nobang = /* (IA without !). */
19115 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19116 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
19117 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19118 bfd_boolean is_db_bang = /* (DB with !). */
19119 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 19120 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 19121 /* d = UInt (Vd:D);. */
9239bbd3 19122 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 19123 | (((unsigned int)initial_insn << 9) >> 31);
19124
9239bbd3
CM		 19125 /* Compute the number of 8-words chunks needed to split. */
19126 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 19127 int chunk;
19128
19129 /* The test coverage has been done assuming the following
19130 hypothesis that exactly one of the previous is_ predicates is
19131 true. */
9239bbd3
CM		 19132 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19133 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 19134
9239bbd3 19135 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 19136 cases, then we emit the adjustments:
19137
19138 vldm rx, {...}
19139 -> vldm rx!, {8_words_or_less} for each needed 8_word
19140 -> sub rx, rx, #size (list)
19141
19142 vldm rx!, {...}
19143 -> vldm rx!, {8_words_or_less} for each needed 8_word
19144 This also handles vpop instruction (when rx is sp)
19145
19146 vldmd rx!, {...}
19147 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 19148 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 19149 {
9239bbd3
CM		 19150 bfd_vma new_insn = 0;
19151
a504d23a
LA		 19152 if (is_ia_nobang || is_ia_bang)
19153 {
9239bbd3
CM		 19154 new_insn = create_instruction_vldmia
19155 (base_reg,
19156 is_dp,
19157 /*wback= . */1,
19158 chunks - (chunk + 1) ?
19159 8 : num_words - chunk * 8,
19160 first_reg + chunk * 8);
a504d23a
LA		 19161 }
19162 else if (is_db_bang)
19163 {
9239bbd3
CM		 19164 new_insn = create_instruction_vldmdb
19165 (base_reg,
19166 is_dp,
19167 chunks - (chunk + 1) ?
19168 8 : num_words - chunk * 8,
19169 first_reg + chunk * 8);
a504d23a 19170 }
9239bbd3
CM		 19171
19172 if (new_insn)
19173 current_stub_contents =
19174 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19175 new_insn);
a504d23a
LA		 19176 }
19177
19178 /* Only this case requires the base register compensation
19179 subtract. */
19180 if (is_ia_nobang)
19181 {
19182 current_stub_contents =
19183 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19184 create_instruction_sub
9239bbd3 19185 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 19186 }
19187
19188 /* B initial_insn_addr+4. */
19189 current_stub_contents =
19190 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19191 create_instruction_branch_absolute
82188b29 19192 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19193 }
19194
19195 /* Fill the remaining of the stub with deterministic contents. */
19196 current_stub_contents =
19197 stm32l4xx_fill_stub_udf (htab, output_bfd,
19198 base_stub_contents, current_stub_contents,
19199 base_stub_contents +
19200 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19201}
19202
19203static void
19204stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19205 bfd * output_bfd,
19206 const insn32 wrong_insn,
19207 const bfd_byte *const wrong_insn_addr,
19208 bfd_byte *const stub_contents)
19209{
19210 if (is_thumb2_ldmia (wrong_insn))
19211 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19212 wrong_insn, wrong_insn_addr,
19213 stub_contents);
19214 else if (is_thumb2_ldmdb (wrong_insn))
19215 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19216 wrong_insn, wrong_insn_addr,
19217 stub_contents);
19218 else if (is_thumb2_vldm (wrong_insn))
19219 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19220 wrong_insn, wrong_insn_addr,
19221 stub_contents);
19222}
19223
19224/* End of stm32l4xx work-around. */
19225
19226
e489d0ae
PB		 19227/* Do code byteswapping. Return FALSE afterwards so that the section is
19228 written out as normal. */
19229
19230static bfd_boolean
c7b8f16e 19231elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 19232 struct bfd_link_info *link_info,
19233 asection *sec,
e489d0ae
PB		 19234 bfd_byte *contents)
19235{
48229727 19236 unsigned int mapcount, errcount;
8e3de13a 19237 _arm_elf_section_data *arm_data;
c7b8f16e 19238 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 19239 elf32_arm_section_map *map;
c7b8f16e 19240 elf32_vfp11_erratum_list *errnode;
a504d23a 19241 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 19242 bfd_vma ptr;
19243 bfd_vma end;
c7b8f16e 19244 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 19245 bfd_byte tmp;
48229727 19246 unsigned int i;
57e8b36a 19247
4dfe6ac6
NC		 19248 if (globals == NULL)
19249 return FALSE;
19250
8e3de13a
NC		 19251 /* If this section has not been allocated an _arm_elf_section_data
19252 structure then we cannot record anything. */
19253 arm_data = get_arm_elf_section_data (sec);
19254 if (arm_data == NULL)
19255 return FALSE;
19256
19257 mapcount = arm_data->mapcount;
19258 map = arm_data->map;
c7b8f16e
JB		 19259 errcount = arm_data->erratumcount;
19260
19261 if (errcount != 0)
19262 {
19263 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19264
19265 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 19266 errnode = errnode->next)
19267 {
19268 bfd_vma target = errnode->vma - offset;
19269
19270 switch (errnode->type)
19271 {
19272 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19273 {
19274 bfd_vma branch_to_veneer;
19275 /* Original condition code of instruction, plus bit mask for
19276 ARM B instruction. */
19277 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19278 | 0x0a000000;
c7b8f16e
JB		 19279
19280 /* The instruction is before the label. */
91d6fa6a 19281 target -= 4;
c7b8f16e
JB		 19282
19283 /* Above offset included in -4 below. */
19284 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 19285 - errnode->vma - 4;
c7b8f16e
JB		 19286
19287 if ((signed) branch_to_veneer < -(1 << 25)
19288 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 19289 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19290 "range"), output_bfd);
c7b8f16e 19291
99059e56
RM		 19292 insn |= (branch_to_veneer >> 2) & 0xffffff;
19293 contents[endianflip ^ target] = insn & 0xff;
19294 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19295 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19296 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19297 }
19298 break;
c7b8f16e
JB		 19299
19300 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 19301 {
19302 bfd_vma branch_from_veneer;
19303 unsigned int insn;
c7b8f16e 19304
99059e56
RM		 19305 /* Take size of veneer into account. */
19306 branch_from_veneer = errnode->u.v.branch->vma
19307 - errnode->vma - 12;
c7b8f16e
JB		 19308
19309 if ((signed) branch_from_veneer < -(1 << 25)
19310 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 19311 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19312 "range"), output_bfd);
c7b8f16e 19313
99059e56
RM		 19314 /* Original instruction. */
19315 insn = errnode->u.v.branch->u.b.vfp_insn;
19316 contents[endianflip ^ target] = insn & 0xff;
19317 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19318 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19319 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19320
19321 /* Branch back to insn after original insn. */
19322 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19323 contents[endianflip ^ (target + 4)] = insn & 0xff;
19324 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19325 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19326 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19327 }
19328 break;
c7b8f16e 19329
99059e56
RM		 19330 default:
19331 abort ();
19332 }
19333 }
c7b8f16e 19334 }
e489d0ae 19335
a504d23a
LA		 19336 if (arm_data->stm32l4xx_erratumcount != 0)
19337 {
19338 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19339 stm32l4xx_errnode != 0;
19340 stm32l4xx_errnode = stm32l4xx_errnode->next)
19341 {
19342 bfd_vma target = stm32l4xx_errnode->vma - offset;
19343
19344 switch (stm32l4xx_errnode->type)
19345 {
19346 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19347 {
19348 unsigned int insn;
19349 bfd_vma branch_to_veneer =
19350 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19351
19352 if ((signed) branch_to_veneer < -(1 << 24)
19353 || (signed) branch_to_veneer >= (1 << 24))
19354 {
19355 bfd_vma out_of_range =
19356 ((signed) branch_to_veneer < -(1 << 24)) ?
19357 - branch_to_veneer - (1 << 24) :
19358 ((signed) branch_to_veneer >= (1 << 24)) ?
19359 branch_to_veneer - (1 << 24) : 0;
19360
4eca0228 19361 _bfd_error_handler
2dcf00ce 19362 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 19363 "cannot create STM32L4XX veneer; "
19364 "jump out of range by %" PRId64 " bytes; "
19365 "cannot encode branch instruction"),
a504d23a 19366 output_bfd,
2dcf00ce
AM		 19367 (uint64_t) (stm32l4xx_errnode->vma - 4),
19368 (int64_t) out_of_range);
a504d23a
LA		 19369 continue;
19370 }
19371
19372 insn = create_instruction_branch_absolute
82188b29 19373 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 19374
19375 /* The instruction is before the label. */
19376 target -= 4;
19377
19378 put_thumb2_insn (globals, output_bfd,
19379 (bfd_vma) insn, contents + target);
19380 }
19381 break;
19382
19383 case STM32L4XX_ERRATUM_VENEER:
19384 {
82188b29
NC		 19385 bfd_byte * veneer;
19386 bfd_byte * veneer_r;
a504d23a
LA		 19387 unsigned int insn;
19388
82188b29
NC		 19389 veneer = contents + target;
19390 veneer_r = veneer
19391 + stm32l4xx_errnode->u.b.veneer->vma
19392 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 19393
19394 if ((signed) (veneer_r - veneer -
19395 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19396 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19397 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19398 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19399 || (signed) (veneer_r - veneer) >= (1 << 24))
19400 {
90b6238f
AM		 19401 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19402 "veneer"), output_bfd);
a504d23a
LA		 19403 continue;
19404 }
19405
19406 /* Original instruction. */
19407 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19408
19409 stm32l4xx_create_replacing_stub
19410 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19411 }
19412 break;
19413
19414 default:
19415 abort ();
19416 }
19417 }
19418 }
19419
2468f9c9
PB		 19420 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19421 {
19422 arm_unwind_table_edit *edit_node
99059e56 19423 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 19424 /* Now, sec->size is the size of the section we will write. The original
99059e56 19425 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 19426 markers) was sec->rawsize. (This isn't the case if we perform no
19427 edits, then rawsize will be zero and we should use size). */
21d799b5 19428 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 19429 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19430 unsigned int in_index, out_index;
19431 bfd_vma add_to_offsets = 0;
19432
19433 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 19434 {
2468f9c9
PB		 19435 if (edit_node)
19436 {
19437 unsigned int edit_index = edit_node->index;
b38cadfb 19438
2468f9c9 19439 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 19440 {
2468f9c9
PB		 19441 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19442 contents + in_index * 8, add_to_offsets);
19443 out_index++;
19444 in_index++;
19445 }
19446 else if (in_index == edit_index
19447 || (in_index * 8 >= input_size
19448 && edit_index == UINT_MAX))
99059e56 19449 {
2468f9c9
PB		 19450 switch (edit_node->type)
19451 {
19452 case DELETE_EXIDX_ENTRY:
19453 in_index++;
19454 add_to_offsets += 8;
19455 break;
b38cadfb 19456
2468f9c9
PB		 19457 case INSERT_EXIDX_CANTUNWIND_AT_END:
19458 {
99059e56 19459 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 19460 bfd_vma text_offset = text_sec->output_section->vma
19461 + text_sec->output_offset
19462 + text_sec->size;
19463 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 19464 unsigned long prel31_offset;
2468f9c9
PB		 19465
19466 /* Note: this is meant to be equivalent to an
19467 R_ARM_PREL31 relocation. These synthetic
19468 EXIDX_CANTUNWIND markers are not relocated by the
19469 usual BFD method. */
19470 prel31_offset = (text_offset - exidx_offset)
19471 & 0x7ffffffful;
491d01d3
YU		 19472 if (bfd_link_relocatable (link_info))
19473 {
19474 /* Here relocation for new EXIDX_CANTUNWIND is
19475 created, so there is no need to
19476 adjust offset by hand. */
19477 prel31_offset = text_sec->output_offset
19478 + text_sec->size;
491d01d3 19479 }
2468f9c9
PB		 19480
19481 /* First address we can't unwind. */
19482 bfd_put_32 (output_bfd, prel31_offset,
19483 &edited_contents[out_index * 8]);
19484
19485 /* Code for EXIDX_CANTUNWIND. */
19486 bfd_put_32 (output_bfd, 0x1,
19487 &edited_contents[out_index * 8 + 4]);
19488
19489 out_index++;
19490 add_to_offsets -= 8;
19491 }
19492 break;
19493 }
b38cadfb 19494
2468f9c9
PB		 19495 edit_node = edit_node->next;
19496 }
19497 }
19498 else
19499 {
19500 /* No more edits, copy remaining entries verbatim. */
19501 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19502 contents + in_index * 8, add_to_offsets);
19503 out_index++;
19504 in_index++;
19505 }
19506 }
19507
19508 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19509 bfd_set_section_contents (output_bfd, sec->output_section,
19510 edited_contents,
19511 (file_ptr) sec->output_offset, sec->size);
19512
19513 return TRUE;
19514 }
19515
48229727
JB		 19516 /* Fix code to point to Cortex-A8 erratum stubs. */
19517 if (globals->fix_cortex_a8)
19518 {
19519 struct a8_branch_to_stub_data data;
19520
19521 data.writing_section = sec;
19522 data.contents = contents;
19523
a504d23a
LA		 19524 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19525 & data);
48229727
JB		 19526 }
19527
e489d0ae
PB		 19528 if (mapcount == 0)
19529 return FALSE;
19530
c7b8f16e 19531 if (globals->byteswap_code)
e489d0ae 19532 {
c7b8f16e 19533 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 19534
c7b8f16e
JB		 19535 ptr = map[0].vma;
19536 for (i = 0; i < mapcount; i++)
99059e56
RM		 19537 {
19538 if (i == mapcount - 1)
c7b8f16e 19539 end = sec->size;
99059e56
RM		 19540 else
19541 end = map[i + 1].vma;
e489d0ae 19542
99059e56 19543 switch (map[i].type)
e489d0ae 19544 {
c7b8f16e
JB		 19545 case 'a':
19546 /* Byte swap code words. */
19547 while (ptr + 3 < end)
99059e56
RM		 19548 {
19549 tmp = contents[ptr];
19550 contents[ptr] = contents[ptr + 3];
19551 contents[ptr + 3] = tmp;
19552 tmp = contents[ptr + 1];
19553 contents[ptr + 1] = contents[ptr + 2];
19554 contents[ptr + 2] = tmp;
19555 ptr += 4;
19556 }
c7b8f16e 19557 break;
e489d0ae 19558
c7b8f16e
JB		 19559 case 't':
19560 /* Byte swap code halfwords. */
19561 while (ptr + 1 < end)
99059e56
RM		 19562 {
19563 tmp = contents[ptr];
19564 contents[ptr] = contents[ptr + 1];
19565 contents[ptr + 1] = tmp;
19566 ptr += 2;
19567 }
c7b8f16e
JB		 19568 break;
19569
19570 case 'd':
19571 /* Leave data alone. */
19572 break;
19573 }
99059e56
RM		 19574 ptr = end;
19575 }
e489d0ae 19576 }
8e3de13a 19577
93204d3a 19578 free (map);
47b2e99c 19579 arm_data->mapcount = -1;
c7b8f16e 19580 arm_data->mapsize = 0;
8e3de13a 19581 arm_data->map = NULL;
8e3de13a 19582
e489d0ae
PB		 19583 return FALSE;
19584}
19585
0beaef2b
PB		 19586/* Mangle thumb function symbols as we read them in. */
19587
8384fb8f 19588static bfd_boolean
0beaef2b
PB		 19589elf32_arm_swap_symbol_in (bfd * abfd,
19590 const void *psrc,
19591 const void *pshn,
19592 Elf_Internal_Sym *dst)
19593{
4ba2ef8f
TP		 19594 Elf_Internal_Shdr *symtab_hdr;
19595 const char *name = NULL;
19596
8384fb8f
AM		 19597 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19598 return FALSE;
39d911fc 19599 dst->st_target_internal = 0;
0beaef2b
PB		 19600
19601 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 19602 the address. */
63e1a0fc
PB		 19603 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19604 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 19605 {
63e1a0fc
PB		 19606 if (dst->st_value & 1)
19607 {
19608 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 19609 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19610 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 19611 }
19612 else
39d911fc 19613 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 19614 }
19615 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19616 {
19617 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 19618 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 19619 }
35fc36a8 19620 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 19621 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 19622 else
39d911fc 19623 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 19624
4ba2ef8f
TP		 19625 /* Mark CMSE special symbols. */
19626 symtab_hdr = & elf_symtab_hdr (abfd);
19627 if (symtab_hdr->sh_size)
19628 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
19629 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
19630 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
19631
8384fb8f 19632 return TRUE;
0beaef2b
PB		 19633}
19634
19635
19636/* Mangle thumb function symbols as we write them out. */
19637
19638static void
19639elf32_arm_swap_symbol_out (bfd *abfd,
19640 const Elf_Internal_Sym *src,
19641 void *cdst,
19642 void *shndx)
19643{
19644 Elf_Internal_Sym newsym;
19645
19646 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19647 of the address set, as per the new EABI. We do this unconditionally
19648 because objcopy does not set the elf header flags until after
19649 it writes out the symbol table. */
39d911fc 19650 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 19651 {
19652 newsym = *src;
34e77a92
RS		 19653 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19654 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 19655 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 19656 {
19657 /* Do this only for defined symbols. At link type, the static
19658 linker will simulate the work of dynamic linker of resolving
19659 symbols and will carry over the thumbness of found symbols to
19660 the output symbol table. It's not clear how it happens, but
19661 the thumbness of undefined symbols can well be different at
19662 runtime, and writing '1' for them will be confusing for users
19663 and possibly for dynamic linker itself.
19664 */
19665 newsym.st_value |= 1;
19666 }
906e58ca 19667
0beaef2b
PB		 19668 src = &newsym;
19669 }
19670 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
19671}
19672
b294bdf8
MM		 19673/* Add the PT_ARM_EXIDX program header. */
19674
19675static bfd_boolean
906e58ca 19676elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 19677 struct bfd_link_info *info ATTRIBUTE_UNUSED)
19678{
19679 struct elf_segment_map *m;
19680 asection *sec;
19681
19682 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19683 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19684 {
19685 /* If there is already a PT_ARM_EXIDX header, then we do not
19686 want to add another one. This situation arises when running
19687 "strip"; the input binary already has the header. */
12bd6957 19688 m = elf_seg_map (abfd);
b294bdf8
MM		 19689 while (m && m->p_type != PT_ARM_EXIDX)
19690 m = m->next;
19691 if (!m)
19692 {
21d799b5 19693 m = (struct elf_segment_map *)
99059e56 19694 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 19695 if (m == NULL)
19696 return FALSE;
19697 m->p_type = PT_ARM_EXIDX;
19698 m->count = 1;
19699 m->sections[0] = sec;
19700
12bd6957
AM		 19701 m->next = elf_seg_map (abfd);
19702 elf_seg_map (abfd) = m;
b294bdf8
MM		 19703 }
19704 }
19705
19706 return TRUE;
19707}
19708
19709/* We may add a PT_ARM_EXIDX program header. */
19710
19711static int
a6b96beb
AM		 19712elf32_arm_additional_program_headers (bfd *abfd,
19713 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 19714{
19715 asection *sec;
19716
19717 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19718 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19719 return 1;
19720 else
19721 return 0;
19722}
19723
34e77a92
RS		 19724/* Hook called by the linker routine which adds symbols from an object
19725 file. */
19726
19727static bfd_boolean
19728elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
19729 Elf_Internal_Sym *sym, const char **namep,
19730 flagword *flagsp, asection **secp, bfd_vma *valp)
19731{
a43942db 19732 if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
f1885d1e
AM		 19733 && (abfd->flags & DYNAMIC) == 0
19734 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
a43942db 19735 elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc;
34e77a92 19736
c792917c
NC		 19737 if (elf32_arm_hash_table (info) == NULL)
19738 return FALSE;
19739
34e77a92
RS		 19740 if (elf32_arm_hash_table (info)->vxworks_p
19741 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
19742 flagsp, secp, valp))
19743 return FALSE;
19744
19745 return TRUE;
19746}
19747
0beaef2b 19748/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 19749const struct elf_size_info elf32_arm_size_info =
19750{
0beaef2b
PB		 19751 sizeof (Elf32_External_Ehdr),
19752 sizeof (Elf32_External_Phdr),
19753 sizeof (Elf32_External_Shdr),
19754 sizeof (Elf32_External_Rel),
19755 sizeof (Elf32_External_Rela),
19756 sizeof (Elf32_External_Sym),
19757 sizeof (Elf32_External_Dyn),
19758 sizeof (Elf_External_Note),
19759 4,
19760 1,
19761 32, 2,
19762 ELFCLASS32, EV_CURRENT,
19763 bfd_elf32_write_out_phdrs,
19764 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 19765 bfd_elf32_checksum_contents,
0beaef2b
PB		 19766 bfd_elf32_write_relocs,
19767 elf32_arm_swap_symbol_in,
19768 elf32_arm_swap_symbol_out,
19769 bfd_elf32_slurp_reloc_table,
19770 bfd_elf32_slurp_symbol_table,
19771 bfd_elf32_swap_dyn_in,
19772 bfd_elf32_swap_dyn_out,
19773 bfd_elf32_swap_reloc_in,
19774 bfd_elf32_swap_reloc_out,
19775 bfd_elf32_swap_reloca_in,
19776 bfd_elf32_swap_reloca_out
19777};
19778
685e70ae
VK		 19779static bfd_vma
19780read_code32 (const bfd *abfd, const bfd_byte *addr)
19781{
19782 /* V7 BE8 code is always little endian. */
19783 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19784 return bfd_getl32 (addr);
19785
19786 return bfd_get_32 (abfd, addr);
19787}
19788
19789static bfd_vma
19790read_code16 (const bfd *abfd, const bfd_byte *addr)
19791{
19792 /* V7 BE8 code is always little endian. */
19793 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19794 return bfd_getl16 (addr);
19795
19796 return bfd_get_16 (abfd, addr);
19797}
19798
6a631e86
YG		 19799/* Return size of plt0 entry starting at ADDR
19800 or (bfd_vma) -1 if size can not be determined. */
19801
19802static bfd_vma
19803elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
19804{
19805 bfd_vma first_word;
19806 bfd_vma plt0_size;
19807
685e70ae 19808 first_word = read_code32 (abfd, addr);
6a631e86
YG		 19809
19810 if (first_word == elf32_arm_plt0_entry[0])
19811 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
19812 else if (first_word == elf32_thumb2_plt0_entry[0])
19813 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
19814 else
19815 /* We don't yet handle this PLT format. */
19816 return (bfd_vma) -1;
19817
19818 return plt0_size;
19819}
19820
19821/* Return size of plt entry starting at offset OFFSET
19822 of plt section located at address START
19823 or (bfd_vma) -1 if size can not be determined. */
19824
19825static bfd_vma
19826elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
19827{
19828 bfd_vma first_insn;
19829 bfd_vma plt_size = 0;
19830 const bfd_byte *addr = start + offset;
19831
19832 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 19833 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 19834 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
19835
19836 /* Respect Thumb stub if necessary. */
685e70ae 19837 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 19838 {
19839 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
19840 }
19841
19842 /* Strip immediate from first add. */
685e70ae 19843 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 19844
19845#ifdef FOUR_WORD_PLT
19846 if (first_insn == elf32_arm_plt_entry[0])
19847 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
19848#else
19849 if (first_insn == elf32_arm_plt_entry_long[0])
19850 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
19851 else if (first_insn == elf32_arm_plt_entry_short[0])
19852 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
19853#endif
19854 else
19855 /* We don't yet handle this PLT format. */
19856 return (bfd_vma) -1;
19857
19858 return plt_size;
19859}
19860
19861/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19862
19863static long
19864elf32_arm_get_synthetic_symtab (bfd *abfd,
19865 long symcount ATTRIBUTE_UNUSED,
19866 asymbol **syms ATTRIBUTE_UNUSED,
19867 long dynsymcount,
19868 asymbol **dynsyms,
19869 asymbol **ret)
19870{
19871 asection *relplt;
19872 asymbol *s;
19873 arelent *p;
19874 long count, i, n;
19875 size_t size;
19876 Elf_Internal_Shdr *hdr;
19877 char *names;
19878 asection *plt;
19879 bfd_vma offset;
19880 bfd_byte *data;
19881
19882 *ret = NULL;
19883
19884 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
19885 return 0;
19886
19887 if (dynsymcount <= 0)
19888 return 0;
19889
19890 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
19891 if (relplt == NULL)
19892 return 0;
19893
19894 hdr = &elf_section_data (relplt)->this_hdr;
19895 if (hdr->sh_link != elf_dynsymtab (abfd)
19896 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
19897 return 0;
19898
19899 plt = bfd_get_section_by_name (abfd, ".plt");
19900 if (plt == NULL)
19901 return 0;
19902
19903 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
19904 return -1;
19905
19906 data = plt->contents;
19907 if (data == NULL)
19908 {
19909 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
19910 return -1;
19911 bfd_cache_section_contents((asection *) plt, data);
19912 }
19913
19914 count = relplt->size / hdr->sh_entsize;
19915 size = count * sizeof (asymbol);
19916 p = relplt->relocation;
19917 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19918 {
19919 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
19920 if (p->addend != 0)
19921 size += sizeof ("+0x") - 1 + 8;
19922 }
19923
19924 s = *ret = (asymbol *) bfd_malloc (size);
19925 if (s == NULL)
19926 return -1;
19927
19928 offset = elf32_arm_plt0_size (abfd, data);
19929 if (offset == (bfd_vma) -1)
19930 return -1;
19931
19932 names = (char *) (s + count);
19933 p = relplt->relocation;
19934 n = 0;
19935 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19936 {
19937 size_t len;
19938
19939 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
19940 if (plt_size == (bfd_vma) -1)
19941 break;
19942
19943 *s = **p->sym_ptr_ptr;
19944 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
19945 we are defining a symbol, ensure one of them is set. */
19946 if ((s->flags & BSF_LOCAL) == 0)
19947 s->flags |= BSF_GLOBAL;
19948 s->flags |= BSF_SYNTHETIC;
19949 s->section = plt;
19950 s->value = offset;
19951 s->name = names;
19952 s->udata.p = NULL;
19953 len = strlen ((*p->sym_ptr_ptr)->name);
19954 memcpy (names, (*p->sym_ptr_ptr)->name, len);
19955 names += len;
19956 if (p->addend != 0)
19957 {
19958 char buf[30], *a;
19959
19960 memcpy (names, "+0x", sizeof ("+0x") - 1);
19961 names += sizeof ("+0x") - 1;
19962 bfd_sprintf_vma (abfd, buf, p->addend);
19963 for (a = buf; *a == '0'; ++a)
19964 ;
19965 len = strlen (a);
19966 memcpy (names, a, len);
19967 names += len;
19968 }
19969 memcpy (names, "@plt", sizeof ("@plt"));
19970 names += sizeof ("@plt");
19971 ++s, ++n;
19972 offset += plt_size;
19973 }
19974
19975 return n;
19976}
19977
ac4c9b04
MG		 19978static bfd_boolean
19979elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
19980{
f0728ee3
AV		 19981 if (hdr->sh_flags & SHF_ARM_PURECODE)
19982 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 19983 return TRUE;
19984}
19985
19986static flagword
19987elf32_arm_lookup_section_flags (char *flag_name)
19988{
f0728ee3
AV		 19989 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
19990 return SHF_ARM_PURECODE;
ac4c9b04
MG		 19991
19992 return SEC_NO_FLAGS;
19993}
19994
491d01d3
YU		 19995static unsigned int
19996elf32_arm_count_additional_relocs (asection *sec)
19997{
19998 struct _arm_elf_section_data *arm_data;
19999 arm_data = get_arm_elf_section_data (sec);
5025eb7c 20000
6342be70 20001 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 20002}
20003
5522f910 20004/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 20005 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 20006 FALSE otherwise. ISECTION is the best guess matching section from the
20007 input bfd IBFD, but it might be NULL. */
20008
20009static bfd_boolean
20010elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20011 bfd *obfd ATTRIBUTE_UNUSED,
20012 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20013 Elf_Internal_Shdr *osection)
20014{
20015 switch (osection->sh_type)
20016 {
20017 case SHT_ARM_EXIDX:
20018 {
20019 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20020 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20021 unsigned i = 0;
20022
20023 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20024 osection->sh_info = 0;
20025
20026 /* The sh_link field must be set to the text section associated with
20027 this index section. Unfortunately the ARM EHABI does not specify
20028 exactly how to determine this association. Our caller does try
20029 to match up OSECTION with its corresponding input section however
20030 so that is a good first guess. */
20031 if (isection != NULL
20032 && osection->bfd_section != NULL
20033 && isection->bfd_section != NULL
20034 && isection->bfd_section->output_section != NULL
20035 && isection->bfd_section->output_section == osection->bfd_section
20036 && iheaders != NULL
20037 && isection->sh_link > 0
20038 && isection->sh_link < elf_numsections (ibfd)
20039 && iheaders[isection->sh_link]->bfd_section != NULL
20040 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20041 )
20042 {
20043 for (i = elf_numsections (obfd); i-- > 0;)
20044 if (oheaders[i]->bfd_section
20045 == iheaders[isection->sh_link]->bfd_section->output_section)
20046 break;
20047 }
9eaff861 20048
5522f910
NC		 20049 if (i == 0)
20050 {
20051 /* Failing that we have to find a matching section ourselves. If
20052 we had the output section name available we could compare that
20053 with input section names. Unfortunately we don't. So instead
20054 we use a simple heuristic and look for the nearest executable
20055 section before this one. */
20056 for (i = elf_numsections (obfd); i-- > 0;)
20057 if (oheaders[i] == osection)
20058 break;
20059 if (i == 0)
20060 break;
20061
20062 while (i-- > 0)
20063 if (oheaders[i]->sh_type == SHT_PROGBITS
20064 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20065 == (SHF_ALLOC | SHF_EXECINSTR))
20066 break;
20067 }
20068
20069 if (i)
20070 {
20071 osection->sh_link = i;
20072 /* If the text section was part of a group
20073 then the index section should be too. */
20074 if (oheaders[i]->sh_flags & SHF_GROUP)
20075 osection->sh_flags |= SHF_GROUP;
20076 return TRUE;
20077 }
20078 }
20079 break;
20080
20081 case SHT_ARM_PREEMPTMAP:
20082 osection->sh_flags = SHF_ALLOC;
20083 break;
20084
20085 case SHT_ARM_ATTRIBUTES:
20086 case SHT_ARM_DEBUGOVERLAY:
20087 case SHT_ARM_OVERLAYSECTION:
20088 default:
20089 break;
20090 }
20091
20092 return FALSE;
20093}
20094
d691934d
NC		 20095/* Returns TRUE if NAME is an ARM mapping symbol.
20096 Traditionally the symbols $a, $d and $t have been used.
20097 The ARM ELF standard also defines $x (for A64 code). It also allows a
20098 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20099 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20100 not support them here. $t.x indicates the start of ThumbEE instructions. */
20101
20102static bfd_boolean
20103is_arm_mapping_symbol (const char * name)
20104{
20105 return name != NULL /* Paranoia. */
20106 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20107 the mapping symbols could have acquired a prefix.
20108 We do not support this here, since such symbols no
20109 longer conform to the ARM ELF ABI. */
20110 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20111 && (name[2] == 0 || name[2] == '.');
20112 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20113 any characters that follow the period are legal characters for the body
20114 of a symbol's name. For now we just assume that this is the case. */
20115}
20116
fca2a38f
NC		 20117/* Make sure that mapping symbols in object files are not removed via the
20118 "strip --strip-unneeded" tool. These symbols are needed in order to
20119 correctly generate interworking veneers, and for byte swapping code
20120 regions. Once an object file has been linked, it is safe to remove the
20121 symbols as they will no longer be needed. */
20122
20123static void
20124elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20125{
20126 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 20127 && sym->section != bfd_abs_section_ptr
d691934d 20128 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 20129 sym->flags |= BSF_KEEP;
20130}
20131
5522f910
NC		 20132#undef elf_backend_copy_special_section_fields
20133#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20134
252b5132 20135#define ELF_ARCH bfd_arch_arm
ae95ffa6 20136#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 20137#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 20138#ifdef __QNXTARGET__
20139#define ELF_MAXPAGESIZE 0x1000
20140#else
7572ca89 20141#define ELF_MAXPAGESIZE 0x10000
d0facd1b 20142#endif
b1342370 20143#define ELF_MINPAGESIZE 0x1000
24718e3b 20144#define ELF_COMMONPAGESIZE 0x1000
252b5132 20145
07d6d2b8 20146#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 20147
99e4ae17
AJ		 20148#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20149#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 20150#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20151#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 20152#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 20153#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 20154#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8
AM		 20155#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
20156#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 20157#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 20158#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 20159#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 20160#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 20161
07d6d2b8
AM		 20162#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20163#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 20164#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 20165#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 20166#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 20167#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 20168#define elf_backend_write_section elf32_arm_write_section
252b5132 20169#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 20170#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 20171#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20172#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20173#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 20174#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 20175#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 20176#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 20177#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 20178#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 20179#define elf_backend_fake_sections elf32_arm_fake_sections
20180#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20181#define elf_backend_final_write_processing elf32_arm_final_write_processing
20182#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 20183#define elf_backend_size_info elf32_arm_size_info
b294bdf8 20184#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 20185#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20186#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 20187#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 20188#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 20189#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 20190#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 20191#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 20192
20193#define elf_backend_can_refcount 1
20194#define elf_backend_can_gc_sections 1
20195#define elf_backend_plt_readonly 1
20196#define elf_backend_want_got_plt 1
20197#define elf_backend_want_plt_sym 0
5474d94f 20198#define elf_backend_want_dynrelro 1
906e58ca
NC		 20199#define elf_backend_may_use_rel_p 1
20200#define elf_backend_may_use_rela_p 0
4e7fd91e 20201#define elf_backend_default_use_rela_p 0
64f52338 20202#define elf_backend_dtrel_excludes_plt 1
252b5132 20203
04f7c78d 20204#define elf_backend_got_header_size 12
b68a20d6 20205#define elf_backend_extern_protected_data 1
04f7c78d 20206
07d6d2b8 20207#undef elf_backend_obj_attrs_vendor
906e58ca 20208#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 20209#undef elf_backend_obj_attrs_section
906e58ca 20210#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 20211#undef elf_backend_obj_attrs_arg_type
906e58ca 20212#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 20213#undef elf_backend_obj_attrs_section_type
104d59d1 20214#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 20215#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 20216#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 20217
07d6d2b8 20218#undef elf_backend_section_flags
ac4c9b04 20219#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 20220#undef elf_backend_lookup_section_flags_hook
20221#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 20222
a2f63b2e
MR		 20223#define elf_backend_linux_prpsinfo32_ugid16 TRUE
20224
252b5132 20225#include "elf32-target.h"
7f266840 20226
b38cadfb
NC		 20227/* Native Client targets. */
20228
20229#undef TARGET_LITTLE_SYM
6d00b590 20230#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 20231#undef TARGET_LITTLE_NAME
20232#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20233#undef TARGET_BIG_SYM
6d00b590 20234#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 20235#undef TARGET_BIG_NAME
20236#define TARGET_BIG_NAME "elf32-bigarm-nacl"
20237
20238/* Like elf32_arm_link_hash_table_create -- but overrides
20239 appropriately for NaCl. */
20240
20241static struct bfd_link_hash_table *
20242elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20243{
20244 struct bfd_link_hash_table *ret;
20245
20246 ret = elf32_arm_link_hash_table_create (abfd);
20247 if (ret)
20248 {
20249 struct elf32_arm_link_hash_table *htab
20250 = (struct elf32_arm_link_hash_table *) ret;
20251
20252 htab->nacl_p = 1;
20253
20254 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20255 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20256 }
20257 return ret;
20258}
20259
20260/* Since NaCl doesn't use the ARM-specific unwind format, we don't
20261 really need to use elf32_arm_modify_segment_map. But we do it
20262 anyway just to reduce gratuitous differences with the stock ARM backend. */
20263
20264static bfd_boolean
20265elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20266{
20267 return (elf32_arm_modify_segment_map (abfd, info)
20268 && nacl_modify_segment_map (abfd, info));
20269}
20270
887badb3
RM		 20271static void
20272elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
20273{
20274 elf32_arm_final_write_processing (abfd, linker);
20275 nacl_final_write_processing (abfd, linker);
20276}
20277
6a631e86
YG		 20278static bfd_vma
20279elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20280 const arelent *rel ATTRIBUTE_UNUSED)
20281{
20282 return plt->vma
20283 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20284 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20285}
887badb3 20286
b38cadfb 20287#undef elf32_bed
6a631e86 20288#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 20289#undef bfd_elf32_bfd_link_hash_table_create
20290#define bfd_elf32_bfd_link_hash_table_create \
20291 elf32_arm_nacl_link_hash_table_create
20292#undef elf_backend_plt_alignment
6a631e86 20293#define elf_backend_plt_alignment 4
b38cadfb
NC		 20294#undef elf_backend_modify_segment_map
20295#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
20296#undef elf_backend_modify_program_headers
20297#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 20298#undef elf_backend_final_write_processing
20299#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 20300#undef bfd_elf32_get_synthetic_symtab
20301#undef elf_backend_plt_sym_val
20302#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 20303#undef elf_backend_copy_special_section_fields
b38cadfb 20304
887badb3
RM		 20305#undef ELF_MINPAGESIZE
20306#undef ELF_COMMONPAGESIZE
20307
b38cadfb
NC		 20308
20309#include "elf32-target.h"
20310
20311/* Reset to defaults. */
20312#undef elf_backend_plt_alignment
20313#undef elf_backend_modify_segment_map
20314#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20315#undef elf_backend_modify_program_headers
887badb3
RM		 20316#undef elf_backend_final_write_processing
20317#define elf_backend_final_write_processing elf32_arm_final_write_processing
20318#undef ELF_MINPAGESIZE
20319#define ELF_MINPAGESIZE 0x1000
20320#undef ELF_COMMONPAGESIZE
20321#define ELF_COMMONPAGESIZE 0x1000
20322
b38cadfb 20323
617a5ada
CL		 20324/* FDPIC Targets. */
20325
20326#undef TARGET_LITTLE_SYM
20327#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20328#undef TARGET_LITTLE_NAME
20329#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20330#undef TARGET_BIG_SYM
20331#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20332#undef TARGET_BIG_NAME
20333#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20334#undef elf_match_priority
20335#define elf_match_priority 128
18a20338
CL		 20336#undef ELF_OSABI
20337#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 20338
20339/* Like elf32_arm_link_hash_table_create -- but overrides
20340 appropriately for FDPIC. */
20341
20342static struct bfd_link_hash_table *
20343elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20344{
20345 struct bfd_link_hash_table *ret;
20346
20347 ret = elf32_arm_link_hash_table_create (abfd);
20348 if (ret)
20349 {
20350 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20351
20352 htab->fdpic_p = 1;
20353 }
20354 return ret;
20355}
20356
e8b09b87
CL		 20357/* We need dynamic symbols for every section, since segments can
20358 relocate independently. */
20359static bfd_boolean
20360elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20361 struct bfd_link_info *info
20362 ATTRIBUTE_UNUSED,
20363 asection *p ATTRIBUTE_UNUSED)
20364{
20365 switch (elf_section_data (p)->this_hdr.sh_type)
20366 {
20367 case SHT_PROGBITS:
20368 case SHT_NOBITS:
20369 /* If sh_type is yet undecided, assume it could be
20370 SHT_PROGBITS/SHT_NOBITS. */
20371 case SHT_NULL:
20372 return FALSE;
20373
20374 /* There shouldn't be section relative relocations
20375 against any other section. */
20376 default:
20377 return TRUE;
20378 }
20379}
20380
617a5ada
CL		 20381#undef elf32_bed
20382#define elf32_bed elf32_arm_fdpic_bed
20383
20384#undef bfd_elf32_bfd_link_hash_table_create
20385#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
20386
e8b09b87
CL		 20387#undef elf_backend_omit_section_dynsym
20388#define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20389
617a5ada 20390#include "elf32-target.h"
e8b09b87 20391
617a5ada 20392#undef elf_match_priority
18a20338 20393#undef ELF_OSABI
e8b09b87 20394#undef elf_backend_omit_section_dynsym
617a5ada 20395
906e58ca 20396/* VxWorks Targets. */
4e7fd91e 20397
07d6d2b8
AM		 20398#undef TARGET_LITTLE_SYM
20399#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20400#undef TARGET_LITTLE_NAME
20401#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20402#undef TARGET_BIG_SYM
20403#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20404#undef TARGET_BIG_NAME
20405#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 20406
20407/* Like elf32_arm_link_hash_table_create -- but overrides
20408 appropriately for VxWorks. */
906e58ca 20409
4e7fd91e
PB		 20410static struct bfd_link_hash_table *
20411elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20412{
20413 struct bfd_link_hash_table *ret;
20414
20415 ret = elf32_arm_link_hash_table_create (abfd);
20416 if (ret)
20417 {
20418 struct elf32_arm_link_hash_table *htab
00a97672 20419 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 20420 htab->use_rel = 0;
00a97672 20421 htab->vxworks_p = 1;
4e7fd91e
PB		 20422 }
20423 return ret;
906e58ca 20424}
4e7fd91e 20425
00a97672
RS		 20426static void
20427elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
20428{
20429 elf32_arm_final_write_processing (abfd, linker);
20430 elf_vxworks_final_write_processing (abfd, linker);
20431}
20432
906e58ca 20433#undef elf32_bed
4e7fd91e
PB		 20434#define elf32_bed elf32_arm_vxworks_bed
20435
906e58ca
NC		 20436#undef bfd_elf32_bfd_link_hash_table_create
20437#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 20438#undef elf_backend_final_write_processing
20439#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20440#undef elf_backend_emit_relocs
9eaff861 20441#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 20442
906e58ca 20443#undef elf_backend_may_use_rel_p
00a97672 20444#define elf_backend_may_use_rel_p 0
906e58ca 20445#undef elf_backend_may_use_rela_p
00a97672 20446#define elf_backend_may_use_rela_p 1
906e58ca 20447#undef elf_backend_default_use_rela_p
00a97672 20448#define elf_backend_default_use_rela_p 1
906e58ca 20449#undef elf_backend_want_plt_sym
00a97672 20450#define elf_backend_want_plt_sym 1
906e58ca 20451#undef ELF_MAXPAGESIZE
00a97672 20452#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 20453
20454#include "elf32-target.h"
20455
20456
21d799b5
NC		 20457/* Merge backend specific data from an object file to the output
20458 object file when linking. */
20459
20460static bfd_boolean
50e03d47 20461elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 20462{
50e03d47 20463 bfd *obfd = info->output_bfd;
21d799b5
NC		 20464 flagword out_flags;
20465 flagword in_flags;
20466 bfd_boolean flags_compatible = TRUE;
20467 asection *sec;
20468
cc643b88 20469 /* Check if we have the same endianness. */
50e03d47 20470 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 20471 return FALSE;
20472
20473 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20474 return TRUE;
20475
50e03d47 20476 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 20477 return FALSE;
20478
20479 /* The input BFD must have had its flags initialised. */
20480 /* The following seems bogus to me -- The flags are initialized in
20481 the assembler but I don't think an elf_flags_init field is
20482 written into the object. */
20483 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20484
20485 in_flags = elf_elfheader (ibfd)->e_flags;
20486 out_flags = elf_elfheader (obfd)->e_flags;
20487
20488 /* In theory there is no reason why we couldn't handle this. However
20489 in practice it isn't even close to working and there is no real
20490 reason to want it. */
20491 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20492 && !(ibfd->flags & DYNAMIC)
20493 && (in_flags & EF_ARM_BE8))
20494 {
871b3ab2 20495 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 20496 ibfd);
20497 return FALSE;
20498 }
20499
20500 if (!elf_flags_init (obfd))
20501 {
20502 /* If the input is the default architecture and had the default
20503 flags then do not bother setting the flags for the output
20504 architecture, instead allow future merges to do this. If no
20505 future merges ever set these flags then they will retain their
99059e56
RM		 20506 uninitialised values, which surprise surprise, correspond
20507 to the default values. */
21d799b5
NC		 20508 if (bfd_get_arch_info (ibfd)->the_default
20509 && elf_elfheader (ibfd)->e_flags == 0)
20510 return TRUE;
20511
20512 elf_flags_init (obfd) = TRUE;
20513 elf_elfheader (obfd)->e_flags = in_flags;
20514
20515 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20516 && bfd_get_arch_info (obfd)->the_default)
20517 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20518
20519 return TRUE;
20520 }
20521
20522 /* Determine what should happen if the input ARM architecture
20523 does not match the output ARM architecture. */
20524 if (! bfd_arm_merge_machines (ibfd, obfd))
20525 return FALSE;
20526
20527 /* Identical flags must be compatible. */
20528 if (in_flags == out_flags)
20529 return TRUE;
20530
20531 /* Check to see if the input BFD actually contains any sections. If
20532 not, its flags may not have been initialised either, but it
20533 cannot actually cause any incompatiblity. Do not short-circuit
20534 dynamic objects; their section list may be emptied by
20535 elf_link_add_object_symbols.
20536
20537 Also check to see if there are no code sections in the input.
20538 In this case there is no need to check for code specific flags.
20539 XXX - do we need to worry about floating-point format compatability
20540 in data sections ? */
20541 if (!(ibfd->flags & DYNAMIC))
20542 {
20543 bfd_boolean null_input_bfd = TRUE;
20544 bfd_boolean only_data_sections = TRUE;
20545
20546 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20547 {
20548 /* Ignore synthetic glue sections. */
20549 if (strcmp (sec->name, ".glue_7")
20550 && strcmp (sec->name, ".glue_7t"))
20551 {
20552 if ((bfd_get_section_flags (ibfd, sec)
20553 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20554 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 20555 only_data_sections = FALSE;
21d799b5
NC		 20556
20557 null_input_bfd = FALSE;
20558 break;
20559 }
20560 }
20561
20562 if (null_input_bfd || only_data_sections)
20563 return TRUE;
20564 }
20565
20566 /* Complain about various flag mismatches. */
20567 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20568 EF_ARM_EABI_VERSION (out_flags)))
20569 {
20570 _bfd_error_handler
90b6238f 20571 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 20572 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20573 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 20574 return FALSE;
20575 }
20576
20577 /* Not sure what needs to be checked for EABI versions >= 1. */
20578 /* VxWorks libraries do not use these flags. */
20579 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20580 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20581 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20582 {
20583 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20584 {
20585 _bfd_error_handler
871b3ab2 20586 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 20587 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20588 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 20589 flags_compatible = FALSE;
20590 }
20591
20592 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20593 {
20594 if (in_flags & EF_ARM_APCS_FLOAT)
20595 _bfd_error_handler
871b3ab2 20596 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 20597 ibfd, obfd);
20598 else
20599 _bfd_error_handler
871b3ab2 20600 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 20601 ibfd, obfd);
20602
20603 flags_compatible = FALSE;
20604 }
20605
20606 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20607 {
20608 if (in_flags & EF_ARM_VFP_FLOAT)
20609 _bfd_error_handler
90b6238f
AM		 20610 (_("error: %pB uses %s instructions, whereas %pB does not"),
20611 ibfd, "VFP", obfd);
21d799b5
NC		 20612 else
20613 _bfd_error_handler
90b6238f
AM		 20614 (_("error: %pB uses %s instructions, whereas %pB does not"),
20615 ibfd, "FPA", obfd);
21d799b5
NC		 20616
20617 flags_compatible = FALSE;
20618 }
20619
20620 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20621 {
20622 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20623 _bfd_error_handler
90b6238f
AM		 20624 (_("error: %pB uses %s instructions, whereas %pB does not"),
20625 ibfd, "Maverick", obfd);
21d799b5
NC		 20626 else
20627 _bfd_error_handler
90b6238f
AM		 20628 (_("error: %pB does not use %s instructions, whereas %pB does"),
20629 ibfd, "Maverick", obfd);
21d799b5
NC		 20630
20631 flags_compatible = FALSE;
20632 }
20633
20634#ifdef EF_ARM_SOFT_FLOAT
20635 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20636 {
20637 /* We can allow interworking between code that is VFP format
20638 layout, and uses either soft float or integer regs for
20639 passing floating point arguments and results. We already
20640 know that the APCS_FLOAT flags match; similarly for VFP
20641 flags. */
20642 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20643 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20644 {
20645 if (in_flags & EF_ARM_SOFT_FLOAT)
20646 _bfd_error_handler
871b3ab2 20647 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 20648 ibfd, obfd);
20649 else
20650 _bfd_error_handler
871b3ab2 20651 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 20652 ibfd, obfd);
20653
20654 flags_compatible = FALSE;
20655 }
20656 }
20657#endif
20658
20659 /* Interworking mismatch is only a warning. */
20660 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
20661 {
20662 if (in_flags & EF_ARM_INTERWORK)
20663 {
20664 _bfd_error_handler
90b6238f 20665 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 20666 ibfd, obfd);
20667 }
20668 else
20669 {
20670 _bfd_error_handler
90b6238f 20671 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 20672 ibfd, obfd);
20673 }
20674 }
20675 }
20676
20677 return flags_compatible;
20678}
20679
20680
906e58ca 20681/* Symbian OS Targets. */
7f266840 20682
07d6d2b8
AM		 20683#undef TARGET_LITTLE_SYM
20684#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
20685#undef TARGET_LITTLE_NAME
20686#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
20687#undef TARGET_BIG_SYM
20688#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
20689#undef TARGET_BIG_NAME
20690#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 20691
20692/* Like elf32_arm_link_hash_table_create -- but overrides
20693 appropriately for Symbian OS. */
906e58ca 20694
7f266840
DJ		 20695static struct bfd_link_hash_table *
20696elf32_arm_symbian_link_hash_table_create (bfd *abfd)
20697{
20698 struct bfd_link_hash_table *ret;
20699
20700 ret = elf32_arm_link_hash_table_create (abfd);
20701 if (ret)
20702 {
20703 struct elf32_arm_link_hash_table *htab
20704 = (struct elf32_arm_link_hash_table *)ret;
20705 /* There is no PLT header for Symbian OS. */
20706 htab->plt_header_size = 0;
95720a86
DJ		 20707 /* The PLT entries are each one instruction and one word. */
20708 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 20709 htab->symbian_p = 1;
33bfe774
JB		 20710 /* Symbian uses armv5t or above, so use_blx is always true. */
20711 htab->use_blx = 1;
67687978 20712 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 20713 }
20714 return ret;
906e58ca 20715}
7f266840 20716
b35d266b 20717static const struct bfd_elf_special_section
551b43fd 20718elf32_arm_symbian_special_sections[] =
7f266840 20719{
5cd3778d
MM		 20720 /* In a BPABI executable, the dynamic linking sections do not go in
20721 the loadable read-only segment. The post-linker may wish to
20722 refer to these sections, but they are not part of the final
20723 program image. */
07d6d2b8
AM		 20724 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
20725 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
20726 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
20727 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
20728 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 20729 /* These sections do not need to be writable as the SymbianOS
20730 postlinker will arrange things so that no dynamic relocation is
20731 required. */
07d6d2b8
AM		 20732 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
20733 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 20734 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 20735 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 20736};
20737
c3c76620 20738static void
906e58ca 20739elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 20740 struct bfd_link_info *link_info)
c3c76620
MM		 20741{
20742 /* BPABI objects are never loaded directly by an OS kernel; they are
20743 processed by a postlinker first, into an OS-specific format. If
20744 the D_PAGED bit is set on the file, BFD will align segments on
20745 page boundaries, so that an OS can directly map the file. With
20746 BPABI objects, that just results in wasted space. In addition,
20747 because we clear the D_PAGED bit, map_sections_to_segments will
20748 recognize that the program headers should not be mapped into any
20749 loadable segment. */
20750 abfd->flags &= ~D_PAGED;
906e58ca 20751 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 20752}
7f266840
DJ		 20753
20754static bfd_boolean
906e58ca 20755elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 20756 struct bfd_link_info *info)
7f266840
DJ		 20757{
20758 struct elf_segment_map *m;
20759 asection *dynsec;
20760
7f266840
DJ		 20761 /* BPABI shared libraries and executables should have a PT_DYNAMIC
20762 segment. However, because the .dynamic section is not marked
20763 with SEC_LOAD, the generic ELF code will not create such a
20764 segment. */
20765 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
20766 if (dynsec)
20767 {
12bd6957 20768 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 20769 if (m->p_type == PT_DYNAMIC)
20770 break;
20771
20772 if (m == NULL)
20773 {
20774 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 20775 m->next = elf_seg_map (abfd);
20776 elf_seg_map (abfd) = m;
8ded5a0f 20777 }
7f266840
DJ		 20778 }
20779
b294bdf8
MM		 20780 /* Also call the generic arm routine. */
20781 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 20782}
20783
95720a86
DJ		 20784/* Return address for Ith PLT stub in section PLT, for relocation REL
20785 or (bfd_vma) -1 if it should not be included. */
20786
20787static bfd_vma
20788elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
20789 const arelent *rel ATTRIBUTE_UNUSED)
20790{
20791 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
20792}
20793
8029a119 20794#undef elf32_bed
7f266840
DJ		 20795#define elf32_bed elf32_arm_symbian_bed
20796
20797/* The dynamic sections are not allocated on SymbianOS; the postlinker
20798 will process them and then discard them. */
906e58ca 20799#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 20800#define ELF_DYNAMIC_SEC_FLAGS \
20801 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
20802
9eaff861 20803#undef elf_backend_emit_relocs
c3c76620 20804
906e58ca
NC		 20805#undef bfd_elf32_bfd_link_hash_table_create
20806#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
20807#undef elf_backend_special_sections
07d6d2b8 20808#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 20809#undef elf_backend_begin_write_processing
20810#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
20811#undef elf_backend_final_write_processing
20812#define elf_backend_final_write_processing elf32_arm_final_write_processing
20813
20814#undef elf_backend_modify_segment_map
7f266840
DJ		 20815#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
20816
20817/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 20818#undef elf_backend_got_header_size
7f266840
DJ		 20819#define elf_backend_got_header_size 0
20820
20821/* Similarly, there is no .got.plt section. */
906e58ca 20822#undef elf_backend_want_got_plt
7f266840
DJ		 20823#define elf_backend_want_got_plt 0
20824
906e58ca 20825#undef elf_backend_plt_sym_val
95720a86
DJ		 20826#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
20827
906e58ca 20828#undef elf_backend_may_use_rel_p
00a97672 20829#define elf_backend_may_use_rel_p 1
906e58ca 20830#undef elf_backend_may_use_rela_p
00a97672 20831#define elf_backend_may_use_rela_p 0
906e58ca 20832#undef elf_backend_default_use_rela_p
00a97672 20833#define elf_backend_default_use_rela_p 0
906e58ca 20834#undef elf_backend_want_plt_sym
00a97672 20835#define elf_backend_want_plt_sym 0
64f52338
AM		 20836#undef elf_backend_dtrel_excludes_plt
20837#define elf_backend_dtrel_excludes_plt 0
906e58ca 20838#undef ELF_MAXPAGESIZE
00a97672 20839#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 20840
7f266840 20841#include "elf32-target.h"
GDB Binutils - Deliverables
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