projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Add support for non-contiguous memory regions
[deliverable/binutils-gdb.git] / bfd / elf32-m68hc11.c
CommitLineData
60bcf0fa 1/* Motorola 68HC11-specific support for 32-bit ELF
b3adc24a 2 Copyright (C) 1999-2020 Free Software Foundation, Inc.
dae78fb0 3 Contributed by Stephane Carrez (stcarrez@nerim.fr)
60bcf0fa
NC		 4 (Heavily copied from the D10V port by Martin Hunt (hunt@cygnus.com))
5
cd123cb7 6 This file is part of BFD, the Binary File Descriptor library.
60bcf0fa 7
cd123cb7
NC		 8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
60bcf0fa 12
cd123cb7
NC		 13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
60bcf0fa 17
cd123cb7
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
60bcf0fa 22
60bcf0fa 23#include "sysdep.h"
3db64b00 24#include "bfd.h"
1fd03b5a 25#include "bfdlink.h"
60bcf0fa
NC		 26#include "libbfd.h"
27#include "elf-bfd.h"
3a65329d 28#include "elf32-m68hc1x.h"
60bcf0fa 29#include "elf/m68hc11.h"
3a65329d 30#include "opcode/m68hc11.h"
60bcf0fa 31
3a65329d 32/* Relocation functions. */
60bcf0fa 33static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup
0a6a3ebe 34 (bfd *, bfd_reloc_code_real_type);
f3185997 35static bfd_boolean m68hc11_info_to_howto_rel
0a6a3ebe 36 (bfd *, arelent *, Elf_Internal_Rela *);
60bcf0fa 37
3a65329d
SC		 38/* Trampoline generation. */
39static bfd_boolean m68hc11_elf_size_one_stub
0a6a3ebe 40 (struct bfd_hash_entry *gen_entry, void *in_arg);
3a65329d 41static bfd_boolean m68hc11_elf_build_one_stub
0a6a3ebe 42 (struct bfd_hash_entry *gen_entry, void *in_arg);
3a65329d 43static struct bfd_link_hash_table* m68hc11_elf_bfd_link_hash_table_create
0a6a3ebe 44 (bfd* abfd);
3a65329d
SC		 45
46/* Linker relaxation. */
b34976b6 47static bfd_boolean m68hc11_elf_relax_section
0a6a3ebe 48 (bfd *, asection *, struct bfd_link_info *, bfd_boolean *);
1fd03b5a 49static void m68hc11_elf_relax_delete_bytes
0a6a3ebe 50 (bfd *, asection *, bfd_vma, int);
1fd03b5a 51static void m68hc11_relax_group
0a6a3ebe
SC		 52 (bfd *, asection *, bfd_byte *, unsigned, unsigned long, unsigned long);
53static int compare_reloc (const void *, const void *);
1fd03b5a 54
60bcf0fa 55/* Use REL instead of RELA to save space */
acf8aed4 56#define USE_REL 1
60bcf0fa 57
3a65329d
SC		 58/* The Motorola 68HC11 microcontroller only addresses 64Kb but we also
59 support a memory bank switching mechanism similar to 68HC12.
60bcf0fa 60 We must handle 8 and 16-bit relocations. The 32-bit relocation
3a65329d
SC		 61 are used for debugging sections (DWARF2) to represent a virtual
62 address.
60bcf0fa
NC		 63 The 3-bit and 16-bit PC rel relocation is only used by 68HC12. */
64static reloc_howto_type elf_m68hc11_howto_table[] = {
65 /* This reloc does nothing. */
66 HOWTO (R_M68HC11_NONE, /* type */
67 0, /* rightshift */
6346d5ca
AM		 68 3, /* size (0 = byte, 1 = short, 2 = long) */
69 0, /* bitsize */
b34976b6 70 FALSE, /* pc_relative */
60bcf0fa 71 0, /* bitpos */
7a897be4 72 complain_overflow_dont,/* complain_on_overflow */
60bcf0fa
NC		 73 bfd_elf_generic_reloc, /* special_function */
74 "R_M68HC11_NONE", /* name */
b34976b6 75 FALSE, /* partial_inplace */
60bcf0fa
NC		 76 0, /* src_mask */
77 0, /* dst_mask */
b34976b6 78 FALSE), /* pcrel_offset */
60bcf0fa
NC		 79
80 /* A 8 bit absolute relocation */
81 HOWTO (R_M68HC11_8, /* type */
82 0, /* rightshift */
83 0, /* size (0 = byte, 1 = short, 2 = long) */
84 8, /* bitsize */
b34976b6 85 FALSE, /* pc_relative */
60bcf0fa
NC		 86 0, /* bitpos */
87 complain_overflow_bitfield, /* complain_on_overflow */
88 bfd_elf_generic_reloc, /* special_function */
89 "R_M68HC11_8", /* name */
b34976b6 90 FALSE, /* partial_inplace */
60bcf0fa
NC		 91 0x00ff, /* src_mask */
92 0x00ff, /* dst_mask */
b34976b6 93 FALSE), /* pcrel_offset */
60bcf0fa
NC		 94
95 /* A 8 bit absolute relocation (upper address) */
96 HOWTO (R_M68HC11_HI8, /* type */
97 8, /* rightshift */
98 0, /* size (0 = byte, 1 = short, 2 = long) */
99 8, /* bitsize */
b34976b6 100 FALSE, /* pc_relative */
60bcf0fa
NC		 101 0, /* bitpos */
102 complain_overflow_bitfield, /* complain_on_overflow */
103 bfd_elf_generic_reloc, /* special_function */
104 "R_M68HC11_HI8", /* name */
b34976b6 105 FALSE, /* partial_inplace */
60bcf0fa
NC		 106 0x00ff, /* src_mask */
107 0x00ff, /* dst_mask */
b34976b6 108 FALSE), /* pcrel_offset */
60bcf0fa
NC		 109
110 /* A 8 bit absolute relocation (upper address) */
111 HOWTO (R_M68HC11_LO8, /* type */
112 0, /* rightshift */
113 0, /* size (0 = byte, 1 = short, 2 = long) */
114 8, /* bitsize */
b34976b6 115 FALSE, /* pc_relative */
60bcf0fa
NC		 116 0, /* bitpos */
117 complain_overflow_dont, /* complain_on_overflow */
118 bfd_elf_generic_reloc, /* special_function */
119 "R_M68HC11_LO8", /* name */
b34976b6 120 FALSE, /* partial_inplace */
60bcf0fa
NC		 121 0x00ff, /* src_mask */
122 0x00ff, /* dst_mask */
b34976b6 123 FALSE), /* pcrel_offset */
60bcf0fa
NC		 124
125 /* A 8 bit PC-rel relocation */
126 HOWTO (R_M68HC11_PCREL_8, /* type */
127 0, /* rightshift */
128 0, /* size (0 = byte, 1 = short, 2 = long) */
129 8, /* bitsize */
b34976b6 130 TRUE, /* pc_relative */
60bcf0fa
NC		 131 0, /* bitpos */
132 complain_overflow_bitfield, /* complain_on_overflow */
133 bfd_elf_generic_reloc, /* special_function */
134 "R_M68HC11_PCREL_8", /* name */
b34976b6 135 FALSE, /* partial_inplace */
dae78fb0 136 0x00ff, /* src_mask */
60bcf0fa 137 0x00ff, /* dst_mask */
07d6d2b8 138 TRUE), /* pcrel_offset */
60bcf0fa
NC		 139
140 /* A 16 bit absolute relocation */
141 HOWTO (R_M68HC11_16, /* type */
142 0, /* rightshift */
143 1, /* size (0 = byte, 1 = short, 2 = long) */
144 16, /* bitsize */
b34976b6 145 FALSE, /* pc_relative */
60bcf0fa
NC		 146 0, /* bitpos */
147 complain_overflow_dont /*bitfield */ , /* complain_on_overflow */
148 bfd_elf_generic_reloc, /* special_function */
149 "R_M68HC11_16", /* name */
b34976b6 150 FALSE, /* partial_inplace */
60bcf0fa
NC		 151 0xffff, /* src_mask */
152 0xffff, /* dst_mask */
b34976b6 153 FALSE), /* pcrel_offset */
60bcf0fa
NC		 154
155 /* A 32 bit absolute relocation. This one is never used for the
156 code relocation. It's used by gas for -gstabs generation. */
157 HOWTO (R_M68HC11_32, /* type */
158 0, /* rightshift */
159 2, /* size (0 = byte, 1 = short, 2 = long) */
160 32, /* bitsize */
b34976b6 161 FALSE, /* pc_relative */
60bcf0fa
NC		 162 0, /* bitpos */
163 complain_overflow_bitfield, /* complain_on_overflow */
164 bfd_elf_generic_reloc, /* special_function */
165 "R_M68HC11_32", /* name */
b34976b6 166 FALSE, /* partial_inplace */
60bcf0fa
NC		 167 0xffffffff, /* src_mask */
168 0xffffffff, /* dst_mask */
b34976b6 169 FALSE), /* pcrel_offset */
60bcf0fa
NC		 170
171 /* A 3 bit absolute relocation */
172 HOWTO (R_M68HC11_3B, /* type */
173 0, /* rightshift */
174 0, /* size (0 = byte, 1 = short, 2 = long) */
175 3, /* bitsize */
b34976b6 176 FALSE, /* pc_relative */
60bcf0fa
NC		 177 0, /* bitpos */
178 complain_overflow_bitfield, /* complain_on_overflow */
179 bfd_elf_generic_reloc, /* special_function */
180 "R_M68HC11_4B", /* name */
b34976b6 181 FALSE, /* partial_inplace */
60bcf0fa
NC		 182 0x003, /* src_mask */
183 0x003, /* dst_mask */
b34976b6 184 FALSE), /* pcrel_offset */
60bcf0fa
NC		 185
186 /* A 16 bit PC-rel relocation */
187 HOWTO (R_M68HC11_PCREL_16, /* type */
188 0, /* rightshift */
189 1, /* size (0 = byte, 1 = short, 2 = long) */
190 16, /* bitsize */
b34976b6 191 TRUE, /* pc_relative */
60bcf0fa
NC		 192 0, /* bitpos */
193 complain_overflow_dont, /* complain_on_overflow */
194 bfd_elf_generic_reloc, /* special_function */
195 "R_M68HC11_PCREL_16", /* name */
b34976b6 196 FALSE, /* partial_inplace */
dae78fb0 197 0xffff, /* src_mask */
60bcf0fa 198 0xffff, /* dst_mask */
07d6d2b8 199 TRUE), /* pcrel_offset */
60bcf0fa
NC		 200
201 /* GNU extension to record C++ vtable hierarchy */
202 HOWTO (R_M68HC11_GNU_VTINHERIT, /* type */
203 0, /* rightshift */
204 1, /* size (0 = byte, 1 = short, 2 = long) */
205 0, /* bitsize */
b34976b6 206 FALSE, /* pc_relative */
60bcf0fa
NC		 207 0, /* bitpos */
208 complain_overflow_dont, /* complain_on_overflow */
209 NULL, /* special_function */
210 "R_M68HC11_GNU_VTINHERIT", /* name */
b34976b6 211 FALSE, /* partial_inplace */
60bcf0fa
NC		 212 0, /* src_mask */
213 0, /* dst_mask */
b34976b6 214 FALSE), /* pcrel_offset */
60bcf0fa
NC		 215
216 /* GNU extension to record C++ vtable member usage */
217 HOWTO (R_M68HC11_GNU_VTENTRY, /* type */
218 0, /* rightshift */
219 1, /* size (0 = byte, 1 = short, 2 = long) */
220 0, /* bitsize */
b34976b6 221 FALSE, /* pc_relative */
60bcf0fa
NC		 222 0, /* bitpos */
223 complain_overflow_dont, /* complain_on_overflow */
224 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
225 "R_M68HC11_GNU_VTENTRY", /* name */
b34976b6 226 FALSE, /* partial_inplace */
60bcf0fa
NC		 227 0, /* src_mask */
228 0, /* dst_mask */
b34976b6 229 FALSE), /* pcrel_offset */
dae78fb0 230
7a897be4 231 /* A 24 bit relocation */
07d6d2b8 232 HOWTO (R_M68HC11_24, /* type */
7a897be4
SC		 233 0, /* rightshift */
234 1, /* size (0 = byte, 1 = short, 2 = long) */
235 24, /* bitsize */
b34976b6 236 FALSE, /* pc_relative */
7a897be4
SC		 237 0, /* bitpos */
238 complain_overflow_bitfield, /* complain_on_overflow */
239 bfd_elf_generic_reloc, /* special_function */
240 "R_M68HC11_24", /* name */
b34976b6 241 FALSE, /* partial_inplace */
196486be
SC		 242 0xffffff, /* src_mask */
243 0xffffff, /* dst_mask */
b34976b6
AM		 244 FALSE), /* pcrel_offset */
245
7a897be4 246 /* A 16-bit low relocation */
07d6d2b8 247 HOWTO (R_M68HC11_LO16, /* type */
7a897be4
SC		 248 0, /* rightshift */
249 1, /* size (0 = byte, 1 = short, 2 = long) */
250 16, /* bitsize */
b34976b6 251 FALSE, /* pc_relative */
7a897be4
SC		 252 0, /* bitpos */
253 complain_overflow_bitfield, /* complain_on_overflow */
254 bfd_elf_generic_reloc, /* special_function */
255 "R_M68HC11_LO16", /* name */
b34976b6 256 FALSE, /* partial_inplace */
7a897be4
SC		 257 0xffff, /* src_mask */
258 0xffff, /* dst_mask */
b34976b6 259 FALSE), /* pcrel_offset */
7a897be4
SC		 260
261 /* A page relocation */
07d6d2b8 262 HOWTO (R_M68HC11_PAGE, /* type */
7a897be4
SC		 263 0, /* rightshift */
264 0, /* size (0 = byte, 1 = short, 2 = long) */
265 8, /* bitsize */
b34976b6 266 FALSE, /* pc_relative */
7a897be4
SC		 267 0, /* bitpos */
268 complain_overflow_bitfield, /* complain_on_overflow */
269 bfd_elf_generic_reloc, /* special_function */
270 "R_M68HC11_PAGE", /* name */
b34976b6 271 FALSE, /* partial_inplace */
7a897be4
SC		 272 0x00ff, /* src_mask */
273 0x00ff, /* dst_mask */
b34976b6 274 FALSE), /* pcrel_offset */
7a897be4 275
dae78fb0
SC		 276 EMPTY_HOWTO (14),
277 EMPTY_HOWTO (15),
278 EMPTY_HOWTO (16),
279 EMPTY_HOWTO (17),
280 EMPTY_HOWTO (18),
281 EMPTY_HOWTO (19),
b34976b6 282
dae78fb0
SC		 283 /* Mark beginning of a jump instruction (any form). */
284 HOWTO (R_M68HC11_RL_JUMP, /* type */
285 0, /* rightshift */
286 1, /* size (0 = byte, 1 = short, 2 = long) */
287 0, /* bitsize */
b34976b6 288 FALSE, /* pc_relative */
dae78fb0
SC		 289 0, /* bitpos */
290 complain_overflow_dont, /* complain_on_overflow */
291 m68hc11_elf_ignore_reloc, /* special_function */
292 "R_M68HC11_RL_JUMP", /* name */
b34976b6 293 TRUE, /* partial_inplace */
dae78fb0
SC		 294 0, /* src_mask */
295 0, /* dst_mask */
07d6d2b8 296 TRUE), /* pcrel_offset */
dae78fb0
SC		 297
298 /* Mark beginning of Gcc relaxation group instruction. */
299 HOWTO (R_M68HC11_RL_GROUP, /* type */
300 0, /* rightshift */
301 1, /* size (0 = byte, 1 = short, 2 = long) */
302 0, /* bitsize */
b34976b6 303 FALSE, /* pc_relative */
dae78fb0
SC		 304 0, /* bitpos */
305 complain_overflow_dont, /* complain_on_overflow */
306 m68hc11_elf_ignore_reloc, /* special_function */
307 "R_M68HC11_RL_GROUP", /* name */
b34976b6 308 TRUE, /* partial_inplace */
dae78fb0
SC		 309 0, /* src_mask */
310 0, /* dst_mask */
07d6d2b8 311 TRUE), /* pcrel_offset */
60bcf0fa
NC		 312};
313
314/* Map BFD reloc types to M68HC11 ELF reloc types. */
315
316struct m68hc11_reloc_map
317{
318 bfd_reloc_code_real_type bfd_reloc_val;
319 unsigned char elf_reloc_val;
320};
321
322static const struct m68hc11_reloc_map m68hc11_reloc_map[] = {
323 {BFD_RELOC_NONE, R_M68HC11_NONE,},
324 {BFD_RELOC_8, R_M68HC11_8},
325 {BFD_RELOC_M68HC11_HI8, R_M68HC11_HI8},
326 {BFD_RELOC_M68HC11_LO8, R_M68HC11_LO8},
327 {BFD_RELOC_8_PCREL, R_M68HC11_PCREL_8},
328 {BFD_RELOC_16_PCREL, R_M68HC11_PCREL_16},
329 {BFD_RELOC_16, R_M68HC11_16},
330 {BFD_RELOC_32, R_M68HC11_32},
331 {BFD_RELOC_M68HC11_3B, R_M68HC11_3B},
332
60bcf0fa
NC		 333 {BFD_RELOC_VTABLE_INHERIT, R_M68HC11_GNU_VTINHERIT},
334 {BFD_RELOC_VTABLE_ENTRY, R_M68HC11_GNU_VTENTRY},
dae78fb0 335
7a897be4
SC		 336 {BFD_RELOC_M68HC11_LO16, R_M68HC11_LO16},
337 {BFD_RELOC_M68HC11_PAGE, R_M68HC11_PAGE},
338 {BFD_RELOC_M68HC11_24, R_M68HC11_24},
339
dae78fb0
SC		 340 {BFD_RELOC_M68HC11_RL_JUMP, R_M68HC11_RL_JUMP},
341 {BFD_RELOC_M68HC11_RL_GROUP, R_M68HC11_RL_GROUP},
60bcf0fa
NC		 342};
343
344static reloc_howto_type *
0a6a3ebe 345bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
07d6d2b8 346 bfd_reloc_code_real_type code)
60bcf0fa
NC		 347{
348 unsigned int i;
349
350 for (i = 0;
351 i < sizeof (m68hc11_reloc_map) / sizeof (struct m68hc11_reloc_map);
352 i++)
353 {
354 if (m68hc11_reloc_map[i].bfd_reloc_val == code)
355 return &elf_m68hc11_howto_table[m68hc11_reloc_map[i].elf_reloc_val];
356 }
357
358 return NULL;
359}
360
157090f7
AM		 361static reloc_howto_type *
362bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
363 const char *r_name)
364{
365 unsigned int i;
366
367 for (i = 0;
368 i < (sizeof (elf_m68hc11_howto_table)
369 / sizeof (elf_m68hc11_howto_table[0]));
370 i++)
371 if (elf_m68hc11_howto_table[i].name != NULL
372 && strcasecmp (elf_m68hc11_howto_table[i].name, r_name) == 0)
373 return &elf_m68hc11_howto_table[i];
374
375 return NULL;
376}
377
60bcf0fa
NC		 378/* Set the howto pointer for an M68HC11 ELF reloc. */
379
f3185997 380static bfd_boolean
0aa13fee 381m68hc11_info_to_howto_rel (bfd *abfd,
07d6d2b8 382 arelent *cache_ptr, Elf_Internal_Rela *dst)
60bcf0fa
NC		 383{
384 unsigned int r_type;
385
386 r_type = ELF32_R_TYPE (dst->r_info);
5860e3f8
NC		 387 if (r_type >= (unsigned int) R_M68HC11_max)
388 {
695344c0 389 /* xgettext:c-format */
0aa13fee
AM		 390 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
391 abfd, r_type);
f3185997
NC		 392 bfd_set_error (bfd_error_bad_value);
393 return FALSE;
5860e3f8 394 }
60bcf0fa 395 cache_ptr->howto = &elf_m68hc11_howto_table[r_type];
f3185997 396 return TRUE;
60bcf0fa
NC		 397}
398
3a65329d
SC		 399\f
400/* Far trampoline generation. */
9b701e44 401
3a65329d
SC		 402/* Build a 68HC11 trampoline stub. */
403static bfd_boolean
0a6a3ebe 404m68hc11_elf_build_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg)
3a65329d
SC		 405{
406 struct elf32_m68hc11_stub_hash_entry *stub_entry;
407 struct bfd_link_info *info;
408 struct m68hc11_elf_link_hash_table *htab;
409 asection *stub_sec;
410 bfd *stub_bfd;
411 bfd_byte *loc;
412 bfd_vma sym_value, phys_page, phys_addr;
413
414 /* Massage our args to the form they really have. */
415 stub_entry = (struct elf32_m68hc11_stub_hash_entry *) gen_entry;
416 info = (struct bfd_link_info *) in_arg;
417
abf874aa
CL		 418 /* Fail if the target section could not be assigned to an output
419 section. The user should fix his linker script. */
420 if (stub_entry->target_section->output_section == NULL
421 && info->non_contiguous_regions)
422 {
423 _bfd_error_handler (_("Could not assign '%pA' to an output section. "
424 "Retry without --enable-non-contiguous-regions.\n"),
425 stub_entry->target_section);
426 abort();
427 }
428
3a65329d 429 htab = m68hc11_elf_hash_table (info);
4dfe6ac6
NC		 430 if (htab == NULL)
431 return FALSE;
3a65329d
SC		 432
433 stub_sec = stub_entry->stub_sec;
434
435 /* Make a note of the offset within the stubs for this entry. */
eea6121a
AM		 436 stub_entry->stub_offset = stub_sec->size;
437 stub_sec->size += 10;
3a65329d
SC		 438 loc = stub_sec->contents + stub_entry->stub_offset;
439
440 stub_bfd = stub_sec->owner;
441
442 /* Create the trampoline call stub:
443
444 pshb
445 ldab #%page(symbol)
446 ldy #%addr(symbol)
447 jmp __trampoline
448
449 */
450 sym_value = (stub_entry->target_value
07d6d2b8
AM		 451 + stub_entry->target_section->output_offset
452 + stub_entry->target_section->output_section->vma);
3a65329d
SC		 453 phys_addr = m68hc11_phys_addr (&htab->pinfo, sym_value);
454 phys_page = m68hc11_phys_page (&htab->pinfo, sym_value);
455
456 /* pshb; ldab #%page(sym) */
457 bfd_put_8 (stub_bfd, 0x37, loc);
458 bfd_put_8 (stub_bfd, 0xC6, loc + 1);
459 bfd_put_8 (stub_bfd, phys_page, loc + 2);
460 loc += 3;
461
462 /* ldy #%addr(sym) */
463 bfd_put_8 (stub_bfd, 0x18, loc);
464 bfd_put_8 (stub_bfd, 0xCE, loc + 1);
465 bfd_put_16 (stub_bfd, phys_addr, loc + 2);
466 loc += 4;
467
468 /* jmp __trampoline */
469 bfd_put_8 (stub_bfd, 0x7E, loc);
470 bfd_put_16 (stub_bfd, htab->pinfo.trampoline_addr, loc + 1);
56780f18 471
3a65329d 472 return TRUE;
9b701e44
SC		 473}
474
3a65329d
SC		 475/* As above, but don't actually build the stub. Just bump offset so
476 we know stub section sizes. */
477
b34976b6 478static bfd_boolean
0a6a3ebe 479m68hc11_elf_size_one_stub (struct bfd_hash_entry *gen_entry,
07d6d2b8 480 void *in_arg ATTRIBUTE_UNUSED)
9b701e44 481{
3a65329d
SC		 482 struct elf32_m68hc11_stub_hash_entry *stub_entry;
483
484 /* Massage our args to the form they really have. */
485 stub_entry = (struct elf32_m68hc11_stub_hash_entry *) gen_entry;
486
eea6121a 487 stub_entry->stub_sec->size += 10;
b34976b6 488 return TRUE;
9b701e44
SC		 489}
490
3a65329d
SC		 491/* Create a 68HC11 ELF linker hash table. */
492
493static struct bfd_link_hash_table *
0a6a3ebe 494m68hc11_elf_bfd_link_hash_table_create (bfd *abfd)
3a65329d
SC		 495{
496 struct m68hc11_elf_link_hash_table *ret;
497
498 ret = m68hc11_elf_hash_table_create (abfd);
499 if (ret == (struct m68hc11_elf_link_hash_table *) NULL)
500 return NULL;
501
502 ret->size_one_stub = m68hc11_elf_size_one_stub;
503 ret->build_one_stub = m68hc11_elf_build_one_stub;
504
505 return &ret->root.root;
506}
507
196486be
SC		 508\f
509/* 68HC11 Linker Relaxation. */
510
b34976b6 511struct m68hc11_direct_relax
1fd03b5a
SC		 512{
513 const char *name;
514 unsigned char code;
515 unsigned char direct_code;
516} m68hc11_direct_relax_table[] = {
517 { "adca", 0xB9, 0x99 },
518 { "adcb", 0xF9, 0xD9 },
519 { "adda", 0xBB, 0x9B },
520 { "addb", 0xFB, 0xDB },
521 { "addd", 0xF3, 0xD3 },
522 { "anda", 0xB4, 0x94 },
523 { "andb", 0xF4, 0xD4 },
524 { "cmpa", 0xB1, 0x91 },
525 { "cmpb", 0xF1, 0xD1 },
526 { "cpd", 0xB3, 0x93 },
527 { "cpxy", 0xBC, 0x9C },
528/* { "cpy", 0xBC, 0x9C }, */
529 { "eora", 0xB8, 0x98 },
530 { "eorb", 0xF8, 0xD8 },
531 { "jsr", 0xBD, 0x9D },
532 { "ldaa", 0xB6, 0x96 },
533 { "ldab", 0xF6, 0xD6 },
534 { "ldd", 0xFC, 0xDC },
535 { "lds", 0xBE, 0x9E },
536 { "ldxy", 0xFE, 0xDE },
537 /* { "ldy", 0xFE, 0xDE },*/
538 { "oraa", 0xBA, 0x9A },
539 { "orab", 0xFA, 0xDA },
540 { "sbca", 0xB2, 0x92 },
541 { "sbcb", 0xF2, 0xD2 },
542 { "staa", 0xB7, 0x97 },
543 { "stab", 0xF7, 0xD7 },
544 { "std", 0xFD, 0xDD },
545 { "sts", 0xBF, 0x9F },
546 { "stxy", 0xFF, 0xDF },
547 /* { "sty", 0xFF, 0xDF },*/
548 { "suba", 0xB0, 0x90 },
549 { "subb", 0xF0, 0xD0 },
550 { "subd", 0xB3, 0x93 },
551 { 0, 0, 0 }
552};
553
554static struct m68hc11_direct_relax *
555find_relaxable_insn (unsigned char code)
556{
557 int i;
558
559 for (i = 0; m68hc11_direct_relax_table[i].name; i++)
560 if (m68hc11_direct_relax_table[i].code == code)
561 return &m68hc11_direct_relax_table[i];
562
563 return 0;
564}
565
566static int
0a6a3ebe 567compare_reloc (const void *e1, const void *e2)
1fd03b5a
SC		 568{
569 const Elf_Internal_Rela *i1 = (const Elf_Internal_Rela *) e1;
570 const Elf_Internal_Rela *i2 = (const Elf_Internal_Rela *) e2;
571
572 if (i1->r_offset == i2->r_offset)
573 return 0;
574 else
575 return i1->r_offset < i2->r_offset ? -1 : 1;
576}
577
578#define M6811_OP_LDX_IMMEDIATE (0xCE)
579
580static void
0a6a3ebe 581m68hc11_relax_group (bfd *abfd, asection *sec, bfd_byte *contents,
07d6d2b8
AM		 582 unsigned value, unsigned long offset,
583 unsigned long end_group)
1fd03b5a
SC		 584{
585 unsigned char code;
586 unsigned long start_offset;
587 unsigned long ldx_offset = offset;
588 unsigned long ldx_size;
589 int can_delete_ldx;
590 int relax_ldy = 0;
591
592 /* First instruction of the relax group must be a
593 LDX #value or LDY #value. If this is not the case,
594 ignore the relax group. */
595 code = bfd_get_8 (abfd, contents + offset);
596 if (code == 0x18)
597 {
598 relax_ldy++;
599 offset++;
600 code = bfd_get_8 (abfd, contents + offset);
601 }
602 ldx_size = offset - ldx_offset + 3;
603 offset += 3;
604 if (code != M6811_OP_LDX_IMMEDIATE || offset >= end_group)
605 return;
606
607
608 /* We can remove the LDX/LDY only when all bset/brclr instructions
609 of the relax group have been converted to use direct addressing
610 mode. */
611 can_delete_ldx = 1;
612 while (offset < end_group)
613 {
614 unsigned isize;
615 unsigned new_value;
616 int bset_use_y;
617
618 bset_use_y = 0;
619 start_offset = offset;
620 code = bfd_get_8 (abfd, contents + offset);
621 if (code == 0x18)
07d6d2b8
AM		 622 {
623 bset_use_y++;
624 offset++;
625 code = bfd_get_8 (abfd, contents + offset);
626 }
1fd03b5a
SC		 627
628 /* Check the instruction and translate to use direct addressing mode. */
629 switch (code)
07d6d2b8
AM		 630 {
631 /* bset */
632 case 0x1C:
633 code = 0x14;
634 isize = 3;
635 break;
636
637 /* brclr */
638 case 0x1F:
639 code = 0x13;
640 isize = 4;
641 break;
642
643 /* brset */
644 case 0x1E:
645 code = 0x12;
646 isize = 4;
647 break;
648
649 /* bclr */
650 case 0x1D:
651 code = 0x15;
652 isize = 3;
653 break;
654
655 /* This instruction is not recognized and we are not
656 at end of the relax group. Ignore and don't remove
657 the first LDX (we don't know what it is used for...). */
658 default:
659 return;
660 }
1fd03b5a
SC		 661 new_value = (unsigned) bfd_get_8 (abfd, contents + offset + 1);
662 new_value += value;
663 if ((new_value & 0xff00) == 0 && bset_use_y == relax_ldy)
07d6d2b8
AM		 664 {
665 bfd_put_8 (abfd, code, contents + offset);
666 bfd_put_8 (abfd, new_value, contents + offset + 1);
667 if (start_offset != offset)
668 {
669 m68hc11_elf_relax_delete_bytes (abfd, sec, start_offset,
670 offset - start_offset);
671 end_group--;
672 }
673 }
1fd03b5a 674 else
07d6d2b8
AM		 675 {
676 can_delete_ldx = 0;
677 }
1fd03b5a
SC		 678 offset = start_offset + isize;
679 }
680 if (can_delete_ldx)
681 {
682 /* Remove the move instruction (3 or 4 bytes win). */
683 m68hc11_elf_relax_delete_bytes (abfd, sec, ldx_offset, ldx_size);
684 }
685}
686
687/* This function handles relaxing for the 68HC11.
688
b34976b6 689
1fd03b5a
SC		 690 and somewhat more difficult to support. */
691
b34976b6 692static bfd_boolean
0a6a3ebe 693m68hc11_elf_relax_section (bfd *abfd, asection *sec,
07d6d2b8 694 struct bfd_link_info *link_info, bfd_boolean *again)
1fd03b5a
SC		 695{
696 Elf_Internal_Shdr *symtab_hdr;
1fd03b5a
SC		 697 Elf_Internal_Rela *internal_relocs;
698 Elf_Internal_Rela *free_relocs = NULL;
699 Elf_Internal_Rela *irel, *irelend;
700 bfd_byte *contents = NULL;
701 bfd_byte *free_contents = NULL;
1fd03b5a
SC		 702 Elf32_External_Sym *free_extsyms = NULL;
703 Elf_Internal_Rela *prev_insn_branch = NULL;
704 Elf_Internal_Rela *prev_insn_group = NULL;
705 unsigned insn_group_value = 0;
1f4c5b47 706 Elf_Internal_Sym *isymbuf = NULL;
1fd03b5a
SC		 707
708 /* Assume nothing changes. */
b34976b6 709 *again = FALSE;
1fd03b5a 710
1049f94e 711 /* We don't have to do anything for a relocatable link, if
1fd03b5a
SC		 712 this section does not have relocs, or if this is not a
713 code section. */
0e1862bb 714 if (bfd_link_relocatable (link_info)
1fd03b5a
SC		 715 || (sec->flags & SEC_RELOC) == 0
716 || sec->reloc_count == 0
717 || (sec->flags & SEC_CODE) == 0)
b34976b6 718 return TRUE;
1fd03b5a 719
1fd03b5a 720 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
1fd03b5a
SC		 721
722 /* Get a copy of the native relocations. */
45d6a902 723 internal_relocs = (_bfd_elf_link_read_relocs
2c3fc389 724 (abfd, sec, NULL, (Elf_Internal_Rela *) NULL,
1fd03b5a
SC		 725 link_info->keep_memory));
726 if (internal_relocs == NULL)
727 goto error_return;
728 if (! link_info->keep_memory)
729 free_relocs = internal_relocs;
730
731 /* Checking for branch relaxation relies on the relocations to
732 be sorted on 'r_offset'. This is not guaranteed so we must sort. */
733 qsort (internal_relocs, sec->reloc_count, sizeof (Elf_Internal_Rela),
07d6d2b8 734 compare_reloc);
1fd03b5a
SC		 735
736 /* Walk through them looking for relaxing opportunities. */
737 irelend = internal_relocs + sec->reloc_count;
738 for (irel = internal_relocs; irel < irelend; irel++)
739 {
740 bfd_vma symval;
741 bfd_vma value;
1f4c5b47 742 Elf_Internal_Sym *isym;
9b691193 743 asection *sym_sec;
196486be 744 int is_far = 0;
1fd03b5a
SC		 745
746 /* If this isn't something that can be relaxed, then ignore
747 this reloc. */
748 if (ELF32_R_TYPE (irel->r_info) != (int) R_M68HC11_16
07d6d2b8
AM		 749 && ELF32_R_TYPE (irel->r_info) != (int) R_M68HC11_RL_JUMP
750 && ELF32_R_TYPE (irel->r_info) != (int) R_M68HC11_RL_GROUP)
751 {
752 prev_insn_branch = 0;
753 prev_insn_group = 0;
754 continue;
755 }
1fd03b5a
SC		 756
757 /* Get the section contents if we haven't done so already. */
758 if (contents == NULL)
759 {
760 /* Get cached copy if it exists. */
761 if (elf_section_data (sec)->this_hdr.contents != NULL)
762 contents = elf_section_data (sec)->this_hdr.contents;
763 else
764 {
765 /* Go get them off disk. */
eea6121a 766 if (!bfd_malloc_and_get_section (abfd, sec, &contents))
1fd03b5a
SC		 767 goto error_return;
768 }
769 }
770
771 /* Try to eliminate an unconditional 8 bit pc-relative branch
772 which immediately follows a conditional 8 bit pc-relative
773 branch around the unconditional branch.
774
775 original: new:
776 bCC lab1 bCC' lab2
777 bra lab2
778 lab1: lab1:
779
780 This happens when the bCC can't reach lab2 at assembly time,
781 but due to other relaxations it can reach at link time. */
782 if (ELF32_R_TYPE (irel->r_info) == (int) R_M68HC11_RL_JUMP)
783 {
784 Elf_Internal_Rela *nrel;
785 unsigned char code;
07d6d2b8 786 unsigned char roffset;
1fd03b5a 787
07d6d2b8
AM		 788 prev_insn_branch = 0;
789 prev_insn_group = 0;
b34976b6 790
1fd03b5a 791 /* Do nothing if this reloc is the last byte in the section. */
eea6121a 792 if (irel->r_offset + 2 >= sec->size)
1fd03b5a
SC		 793 continue;
794
795 /* See if the next instruction is an unconditional pc-relative
796 branch, more often than not this test will fail, so we
797 test it first to speed things up. */
798 code = bfd_get_8 (abfd, contents + irel->r_offset + 2);
799 if (code != 0x7e)
800 continue;
801
802 /* Also make sure the next relocation applies to the next
803 instruction and that it's a pc-relative 8 bit branch. */
804 nrel = irel + 1;
805 if (nrel == irelend
806 || irel->r_offset + 3 != nrel->r_offset
807 || ELF32_R_TYPE (nrel->r_info) != (int) R_M68HC11_16)
808 continue;
809
810 /* Make sure our destination immediately follows the
811 unconditional branch. */
07d6d2b8
AM		 812 roffset = bfd_get_8 (abfd, contents + irel->r_offset + 1);
813 if (roffset != 3)
814 continue;
1fd03b5a 815
07d6d2b8
AM		 816 prev_insn_branch = irel;
817 prev_insn_group = 0;
818 continue;
819 }
1fd03b5a
SC		 820
821 /* Read this BFD's symbols if we haven't done so already. */
1f4c5b47 822 if (isymbuf == NULL && symtab_hdr->sh_info != 0)
1fd03b5a 823 {
1f4c5b47
SC		 824 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
825 if (isymbuf == NULL)
826 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
827 symtab_hdr->sh_info, 0,
828 NULL, NULL, NULL);
829 if (isymbuf == NULL)
830 goto error_return;
1fd03b5a
SC		 831 }
832
833 /* Get the value of the symbol referred to by the reloc. */
834 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
835 {
1fd03b5a 836 /* A local symbol. */
1f4c5b47 837 isym = isymbuf + ELF32_R_SYM (irel->r_info);
07d6d2b8
AM		 838 is_far = isym->st_other & STO_M68HC12_FAR;
839 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
1f4c5b47 840 symval = (isym->st_value
1fd03b5a
SC		 841 + sym_sec->output_section->vma
842 + sym_sec->output_offset);
843 }
844 else
845 {
846 unsigned long indx;
847 struct elf_link_hash_entry *h;
848
849 /* An external symbol. */
850 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
851 h = elf_sym_hashes (abfd)[indx];
852 BFD_ASSERT (h != NULL);
853 if (h->root.type != bfd_link_hash_defined
854 && h->root.type != bfd_link_hash_defweak)
855 {
856 /* This appears to be a reference to an undefined
07d6d2b8
AM		 857 symbol. Just ignore it--it will be caught by the
858 regular reloc processing. */
859 prev_insn_branch = 0;
860 prev_insn_group = 0;
1fd03b5a
SC		 861 continue;
862 }
863
07d6d2b8
AM		 864 is_far = h->other & STO_M68HC12_FAR;
865 isym = 0;
866 sym_sec = h->root.u.def.section;
1fd03b5a 867 symval = (h->root.u.def.value
9b691193
SC		 868 + sym_sec->output_section->vma
869 + sym_sec->output_offset);
1fd03b5a
SC		 870 }
871
872 if (ELF32_R_TYPE (irel->r_info) == (int) R_M68HC11_RL_GROUP)
873 {
07d6d2b8
AM		 874 prev_insn_branch = 0;
875 prev_insn_group = 0;
b34976b6 876
1fd03b5a 877 /* Do nothing if this reloc is the last byte in the section. */
eea6121a 878 if (irel->r_offset == sec->size)
1fd03b5a
SC		 879 continue;
880
07d6d2b8
AM		 881 prev_insn_group = irel;
882 insn_group_value = isym->st_value;
883 continue;
884 }
1fd03b5a 885
9b691193 886 /* When we relax some bytes, the size of our section changes.
07d6d2b8
AM		 887 This affects the layout of next input sections that go in our
888 output section. When the symbol is part of another section that
889 will go in the same output section as the current one, it's
890 final address may now be incorrect (too far). We must let the
891 linker re-compute all section offsets before processing this
892 reloc. Code example:
893
894 Initial Final
895 .sect .text section size = 6 section size = 4
896 jmp foo
897 jmp bar
898 .sect .text.foo_bar output_offset = 6 output_offset = 4
899 foo: rts
900 bar: rts
901
902 If we process the reloc now, the jmp bar is replaced by a
903 relative branch to the initial bar address (output_offset 6). */
9b691193 904 if (*again && sym_sec != sec
07d6d2b8
AM		 905 && sym_sec->output_section == sec->output_section)
906 {
907 prev_insn_group = 0;
908 prev_insn_branch = 0;
909 continue;
910 }
b34976b6 911
1fd03b5a
SC		 912 value = symval;
913 /* Try to turn a far branch to a near branch. */
914 if (ELF32_R_TYPE (irel->r_info) == (int) R_M68HC11_16
07d6d2b8
AM		 915 && prev_insn_branch)
916 {
917 bfd_vma offset;
918 unsigned char code;
919
920 offset = value - (prev_insn_branch->r_offset
921 + sec->output_section->vma
922 + sec->output_offset + 2);
923
924 /* If the offset is still out of -128..+127 range,
925 leave that far branch unchanged. */
926 if ((offset & 0xff80) != 0 && (offset & 0xff80) != 0xff80)
927 {
928 prev_insn_branch = 0;
929 continue;
930 }
931
932 /* Shrink the branch. */
933 code = bfd_get_8 (abfd, contents + prev_insn_branch->r_offset);
934 if (code == 0x7e)
935 {
936 code = 0x20;
937 bfd_put_8 (abfd, code, contents + prev_insn_branch->r_offset);
938 bfd_put_8 (abfd, 0xff,
939 contents + prev_insn_branch->r_offset + 1);
940 irel->r_offset = prev_insn_branch->r_offset + 1;
941 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
942 R_M68HC11_PCREL_8);
943 m68hc11_elf_relax_delete_bytes (abfd, sec,
944 irel->r_offset + 1, 1);
945 }
946 else
947 {
948 code ^= 0x1;
949 bfd_put_8 (abfd, code, contents + prev_insn_branch->r_offset);
950 bfd_put_8 (abfd, 0xff,
951 contents + prev_insn_branch->r_offset + 1);
952 irel->r_offset = prev_insn_branch->r_offset + 1;
953 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
954 R_M68HC11_PCREL_8);
955 m68hc11_elf_relax_delete_bytes (abfd, sec,
956 irel->r_offset + 1, 3);
957 }
958 prev_insn_branch = 0;
959 *again = TRUE;
960 }
1fd03b5a
SC		 961
962 /* Try to turn a 16 bit address into a 8 bit page0 address. */
963 else if (ELF32_R_TYPE (irel->r_info) == (int) R_M68HC11_16
07d6d2b8 964 && (value & 0xff00) == 0)
1fd03b5a 965 {
07d6d2b8
AM		 966 unsigned char code;
967 unsigned short offset;
968 struct m68hc11_direct_relax *rinfo;
969
970 prev_insn_branch = 0;
971 offset = bfd_get_16 (abfd, contents + irel->r_offset);
972 offset += value;
973 if ((offset & 0xff00) != 0)
974 {
975 prev_insn_group = 0;
976 continue;
977 }
978
979 if (prev_insn_group)
980 {
981 unsigned long old_sec_size = sec->size;
982
983 /* Note that we've changed the relocation contents, etc. */
984 elf_section_data (sec)->relocs = internal_relocs;
985 free_relocs = NULL;
986
987 elf_section_data (sec)->this_hdr.contents = contents;
988 free_contents = NULL;
989
990 symtab_hdr->contents = (bfd_byte *) isymbuf;
991 free_extsyms = NULL;
992
993 m68hc11_relax_group (abfd, sec, contents, offset,
994 prev_insn_group->r_offset,
995 insn_group_value);
996 irel = prev_insn_group;
997 prev_insn_group = 0;
998 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
999 R_M68HC11_NONE);
1000 if (sec->size != old_sec_size)
1001 *again = TRUE;
1002 continue;
1003 }
1004
1005 /* Get the opcode. */
1006 code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
1007 rinfo = find_relaxable_insn (code);
1008 if (rinfo == 0)
1009 {
1010 prev_insn_group = 0;
1011 continue;
1012 }
1013
1014 /* Note that we've changed the relocation contents, etc. */
1015 elf_section_data (sec)->relocs = internal_relocs;
1016 free_relocs = NULL;
1017
1018 elf_section_data (sec)->this_hdr.contents = contents;
1019 free_contents = NULL;
1020
1021 symtab_hdr->contents = (bfd_byte *) isymbuf;
1022 free_extsyms = NULL;
1023
1024 /* Fix the opcode. */
1025 /* printf ("A relaxable case : 0x%02x (%s)\n",
1026 code, rinfo->name); */
1027 bfd_put_8 (abfd, rinfo->direct_code,
1028 contents + irel->r_offset - 1);
1029
1030 /* Delete one byte of data (upper byte of address). */
1031 m68hc11_elf_relax_delete_bytes (abfd, sec, irel->r_offset, 1);
1032
1033 /* Fix the relocation's type. */
1034 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
1035 R_M68HC11_8);
1036
1037 /* That will change things, so, we should relax again. */
1038 *again = TRUE;
1039 }
196486be 1040 else if (ELF32_R_TYPE (irel->r_info) == R_M68HC11_16 && !is_far)
07d6d2b8
AM		 1041 {
1042 unsigned char code;
1043 bfd_vma offset;
1044
1045 prev_insn_branch = 0;
1046 code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
1047 if (code == 0x7e || code == 0xbd)
1048 {
1049 offset = value - (irel->r_offset
1050 + sec->output_section->vma
1051 + sec->output_offset + 1);
1052 offset += bfd_get_16 (abfd, contents + irel->r_offset);
1053
1054 /* If the offset is still out of -128..+127 range,
1055 leave that far branch unchanged. */
1056 if ((offset & 0xff80) == 0 || (offset & 0xff80) == 0xff80)
1057 {
1058
1059 /* Note that we've changed the relocation contents, etc. */
1060 elf_section_data (sec)->relocs = internal_relocs;
1061 free_relocs = NULL;
1062
1063 elf_section_data (sec)->this_hdr.contents = contents;
1064 free_contents = NULL;
1065
1066 symtab_hdr->contents = (bfd_byte *) isymbuf;
1067 free_extsyms = NULL;
1068
1069 /* Shrink the branch. */
1070 code = (code == 0x7e) ? 0x20 : 0x8d;
1071 bfd_put_8 (abfd, code,
1072 contents + irel->r_offset - 1);
1073 bfd_put_8 (abfd, 0xff,
1074 contents + irel->r_offset);
1075 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
1076 R_M68HC11_PCREL_8);
1077 m68hc11_elf_relax_delete_bytes (abfd, sec,
1078 irel->r_offset + 1, 1);
1079 /* That will change things, so, we should relax again. */
1080 *again = TRUE;
1081 }
1082 }
1083 }
1fd03b5a 1084 prev_insn_branch = 0;
d204f4c0 1085 prev_insn_group = 0;
1fd03b5a
SC		 1086 }
1087
1088 if (free_relocs != NULL)
1089 {
1090 free (free_relocs);
1091 free_relocs = NULL;
1092 }
1093
1094 if (free_contents != NULL)
1095 {
1096 if (! link_info->keep_memory)
1097 free (free_contents);
1098 else
1099 {
1100 /* Cache the section contents for elf_link_input_bfd. */
1101 elf_section_data (sec)->this_hdr.contents = contents;
1102 }
1103 free_contents = NULL;
1104 }
1105
1106 if (free_extsyms != NULL)
1107 {
1108 if (! link_info->keep_memory)
1109 free (free_extsyms);
1110 else
1111 {
1112 /* Cache the symbols for elf_link_input_bfd. */
1f4c5b47 1113 symtab_hdr->contents = (unsigned char *) isymbuf;
1fd03b5a
SC		 1114 }
1115 free_extsyms = NULL;
1116 }
1117
b34976b6 1118 return TRUE;
1fd03b5a
SC		 1119
1120 error_return:
1121 if (free_relocs != NULL)
1122 free (free_relocs);
1123 if (free_contents != NULL)
1124 free (free_contents);
1125 if (free_extsyms != NULL)
1126 free (free_extsyms);
b34976b6 1127 return FALSE;
1fd03b5a
SC		 1128}
1129
1130/* Delete some bytes from a section while relaxing. */
1131
1132static void
0a6a3ebe 1133m68hc11_elf_relax_delete_bytes (bfd *abfd, asection *sec,
07d6d2b8 1134 bfd_vma addr, int count)
1fd03b5a
SC		 1135{
1136 Elf_Internal_Shdr *symtab_hdr;
1fd03b5a 1137 unsigned int sec_shndx;
1fd03b5a
SC		 1138 bfd_byte *contents;
1139 Elf_Internal_Rela *irel, *irelend;
1140 bfd_vma toaddr;
1f4c5b47 1141 Elf_Internal_Sym *isymbuf, *isym, *isymend;
1fd03b5a
SC		 1142 struct elf_link_hash_entry **sym_hashes;
1143 struct elf_link_hash_entry **end_hashes;
1144 unsigned int symcount;
1145
1146 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
1f4c5b47 1147 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
1fd03b5a
SC		 1148
1149 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1150
1151 contents = elf_section_data (sec)->this_hdr.contents;
1152
eea6121a 1153 toaddr = sec->size;
1fd03b5a
SC		 1154
1155 irel = elf_section_data (sec)->relocs;
1156 irelend = irel + sec->reloc_count;
1157
1158 /* Actually delete the bytes. */
1159 memmove (contents + addr, contents + addr + count,
1160 (size_t) (toaddr - addr - count));
1fd03b5a 1161
eea6121a 1162 sec->size -= count;
b34976b6 1163
1fd03b5a
SC		 1164 /* Adjust all the relocs. */
1165 for (irel = elf_section_data (sec)->relocs; irel < irelend; irel++)
1166 {
1167 unsigned char code;
1168 unsigned char offset;
1169 unsigned short raddr;
1170 unsigned long old_offset;
1171 int branch_pos;
1172
1173 old_offset = irel->r_offset;
1174
1175 /* See if this reloc was for the bytes we have deleted, in which
1176 case we no longer care about it. Don't delete relocs which
1177 represent addresses, though. */
1178 if (ELF32_R_TYPE (irel->r_info) != R_M68HC11_RL_JUMP
07d6d2b8
AM		 1179 && irel->r_offset >= addr && irel->r_offset < addr + count)
1180 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
1181 R_M68HC11_NONE);
1fd03b5a
SC		 1182
1183 if (ELF32_R_TYPE (irel->r_info) == R_M68HC11_NONE)
07d6d2b8 1184 continue;
1fd03b5a
SC		 1185
1186 /* Get the new reloc address. */
1187 if ((irel->r_offset > addr
1188 && irel->r_offset < toaddr))
1189 irel->r_offset -= count;
1190
1191 /* If this is a PC relative reloc, see if the range it covers
07d6d2b8 1192 includes the bytes we have deleted. */
1fd03b5a
SC		 1193 switch (ELF32_R_TYPE (irel->r_info))
1194 {
1195 default:
1196 break;
1197
1198 case R_M68HC11_RL_JUMP:
07d6d2b8
AM		 1199 code = bfd_get_8 (abfd, contents + irel->r_offset);
1200 switch (code)
1201 {
1202 /* jsr and jmp instruction are also marked with RL_JUMP
1203 relocs but no adjustment must be made. */
1204 case 0x7e:
1205 case 0x9d:
1206 case 0xbd:
1207 continue;
1208
1209 case 0x12:
1210 case 0x13:
1211 branch_pos = 3;
1212 raddr = 4;
1213
1214 /* Special case when we translate a brclr N,y into brclr *<addr>
1215 In this case, the 0x18 page2 prefix is removed.
1216 The reloc offset is not modified but the instruction
1217 size is reduced by 1. */
1218 if (old_offset == addr)
1219 raddr++;
1220 break;
1221
1222 case 0x1e:
1223 case 0x1f:
1224 branch_pos = 3;
1225 raddr = 4;
1226 break;
1227
1228 case 0x18:
1229 branch_pos = 4;
1230 raddr = 5;
1231 break;
1232
1233 default:
1234 branch_pos = 1;
1235 raddr = 2;
1236 break;
1237 }
1238 offset = bfd_get_8 (abfd, contents + irel->r_offset + branch_pos);
1239 raddr += old_offset;
1240 raddr += ((unsigned short) offset | ((offset & 0x80) ? 0xff00 : 0));
1241 if (irel->r_offset < addr && raddr > addr)
1242 {
1243 offset -= count;
1244 bfd_put_8 (abfd, offset, contents + irel->r_offset + branch_pos);
1245 }
1246 else if (irel->r_offset >= addr && raddr <= addr)
1247 {
1248 offset += count;
1249 bfd_put_8 (abfd, offset, contents + irel->r_offset + branch_pos);
1250 }
1251 else
1252 {
1253 /*printf ("Not adjusted 0x%04x [0x%4x 0x%4x]\n", raddr,
1254 irel->r_offset, addr);*/
1255 }
1256
1257 break;
1fd03b5a
SC		 1258 }
1259 }
1260
1261 /* Adjust the local symbols defined in this section. */
1f4c5b47
SC		 1262 isymend = isymbuf + symtab_hdr->sh_info;
1263 for (isym = isymbuf; isym < isymend; isym++)
1fd03b5a 1264 {
1f4c5b47
SC		 1265 if (isym->st_shndx == sec_shndx
1266 && isym->st_value > addr
196486be 1267 && isym->st_value <= toaddr)
1f4c5b47 1268 isym->st_value -= count;
1fd03b5a
SC		 1269 }
1270
1271 /* Now adjust the global symbols defined in this section. */
1272 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1273 - symtab_hdr->sh_info);
1274 sym_hashes = elf_sym_hashes (abfd);
1275 end_hashes = sym_hashes + symcount;
1276 for (; sym_hashes < end_hashes; sym_hashes++)
1277 {
1278 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1279 if ((sym_hash->root.type == bfd_link_hash_defined
1280 || sym_hash->root.type == bfd_link_hash_defweak)
1281 && sym_hash->root.u.def.section == sec
1282 && sym_hash->root.u.def.value > addr
196486be 1283 && sym_hash->root.u.def.value <= toaddr)
1fd03b5a
SC		 1284 {
1285 sym_hash->root.u.def.value -= count;
1286 }
1287 }
1288}
1289
2f89ff8d
L		 1290/* Specific sections:
1291 - The .page0 is a data section that is mapped in [0x0000..0x00FF].
1292 Page0 accesses are faster on the M68HC11. Soft registers used by GCC-m6811
1293 are located in .page0.
3f533aa9 1294 - The .vectors is the section that represents the interrupt
2f89ff8d 1295 vectors. */
b35d266b 1296static const struct bfd_elf_special_section elf32_m68hc11_special_sections[] =
2f89ff8d 1297{
0112cd26
NC		 1298 { STRING_COMMA_LEN (".eeprom"), 0, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE },
1299 { STRING_COMMA_LEN (".page0"), 0, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE },
1300 { STRING_COMMA_LEN (".softregs"), 0, SHT_NOBITS, SHF_ALLOC + SHF_WRITE },
1301 { STRING_COMMA_LEN (".vectors"), 0, SHT_PROGBITS, SHF_ALLOC },
07d6d2b8 1302 { NULL, 0, 0, 0, 0 }
7f4d3958 1303};
96405e3c 1304\f
60bcf0fa 1305#define ELF_ARCH bfd_arch_m68hc11
ae95ffa6 1306#define ELF_TARGET_ID M68HC11_ELF_DATA
60bcf0fa
NC		 1307#define ELF_MACHINE_CODE EM_68HC11
1308#define ELF_MAXPAGESIZE 0x1000
1309
07d6d2b8 1310#define TARGET_BIG_SYM m68hc11_elf32_vec
60bcf0fa
NC		 1311#define TARGET_BIG_NAME "elf32-m68hc11"
1312
f3185997 1313#define elf_info_to_howto NULL
60bcf0fa 1314#define elf_info_to_howto_rel m68hc11_info_to_howto_rel
1fd03b5a 1315#define bfd_elf32_bfd_relax_section m68hc11_elf_relax_section
1fd03b5a
SC		 1316#define elf_backend_check_relocs elf32_m68hc11_check_relocs
1317#define elf_backend_relocate_section elf32_m68hc11_relocate_section
3a65329d 1318#define elf_backend_add_symbol_hook elf32_m68hc11_add_symbol_hook
60bcf0fa 1319#define elf_backend_object_p 0
9b701e44 1320#define elf_backend_can_gc_sections 1
29ef7005 1321#define elf_backend_special_sections elf32_m68hc11_special_sections
5efbbc43 1322#define elf_backend_merge_symbol_attribute elf32_m68hc11_merge_symbol_attribute
3a65329d
SC		 1323
1324#define bfd_elf32_bfd_link_hash_table_create \
07d6d2b8 1325 m68hc11_elf_bfd_link_hash_table_create
96405e3c
SC		 1326#define bfd_elf32_bfd_merge_private_bfd_data \
1327 _bfd_m68hc11_elf_merge_private_bfd_data
1328#define bfd_elf32_bfd_set_private_flags _bfd_m68hc11_elf_set_private_flags
1329#define bfd_elf32_bfd_print_private_bfd_data \
1330 _bfd_m68hc11_elf_print_private_bfd_data
1331
60bcf0fa 1332#include "elf32-target.h"
GDB Binutils - Deliverables
This page took 1.088965 seconds and 4 git commands to generate.