Commit | Line | Data |
---|---|---|
2469cfa2 | 1 | /* MSP430-specific support for 32-bit ELF |
b3adc24a | 2 | Copyright (C) 2002-2020 Free Software Foundation, Inc. |
2469cfa2 NC |
3 | Contributed by Dmitry Diky <diwil@mail.ru> |
4 | ||
5 | This file is part of BFD, the Binary File Descriptor library. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
cd123cb7 | 9 | the Free Software Foundation; either version 3 of the License, or |
2469cfa2 NC |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
cd123cb7 NC |
19 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
20 | MA 02110-1301, USA. */ | |
2469cfa2 | 21 | |
2469cfa2 | 22 | #include "sysdep.h" |
3db64b00 | 23 | #include "bfd.h" |
2469cfa2 NC |
24 | #include "libiberty.h" |
25 | #include "libbfd.h" | |
26 | #include "elf-bfd.h" | |
27 | #include "elf/msp430.h" | |
28 | ||
d60f5448 JL |
29 | static bfd_boolean debug_relocs = 0; |
30 | ||
bb294208 AM |
31 | /* All users of this file have bfd_octets_per_byte (abfd, sec) == 1. */ |
32 | #define OCTETS_PER_BYTE(ABFD, SEC) 1 | |
33 | ||
1ade7175 NC |
34 | static bfd_reloc_status_type |
35 | rl78_sym_diff_handler (bfd * abfd, | |
36 | arelent * reloc, | |
37 | asymbol * sym ATTRIBUTE_UNUSED, | |
38 | void * addr ATTRIBUTE_UNUSED, | |
39 | asection * input_sec, | |
40 | bfd * out_bfd ATTRIBUTE_UNUSED, | |
41 | char ** error_message ATTRIBUTE_UNUSED) | |
42 | { | |
43 | bfd_size_type octets; | |
bb294208 | 44 | octets = reloc->address * OCTETS_PER_BYTE (abfd, input_sec); |
1ade7175 NC |
45 | |
46 | /* Catch the case where bfd_install_relocation would return | |
47 | bfd_reloc_outofrange because the SYM_DIFF reloc is being used in a very | |
48 | small section. It does not actually matter if this happens because all | |
49 | that SYM_DIFF does is compute a (4-byte) value. A second reloc then uses | |
50 | this value, and it is that reloc that must fit into the section. | |
51 | ||
52 | This happens in eg, gcc/testsuite/gcc.c-torture/compile/labels-3.c. */ | |
53 | if ((octets + bfd_get_reloc_size (reloc->howto)) | |
54 | > bfd_get_section_limit_octets (abfd, input_sec)) | |
55 | return bfd_reloc_ok; | |
56 | return bfd_reloc_continue; | |
57 | } | |
58 | ||
2469cfa2 NC |
59 | static reloc_howto_type elf_msp430_howto_table[] = |
60 | { | |
61 | HOWTO (R_MSP430_NONE, /* type */ | |
62 | 0, /* rightshift */ | |
6346d5ca AM |
63 | 3, /* size (0 = byte, 1 = short, 2 = long) */ |
64 | 0, /* bitsize */ | |
2469cfa2 NC |
65 | FALSE, /* pc_relative */ |
66 | 0, /* bitpos */ | |
6346d5ca | 67 | complain_overflow_dont,/* complain_on_overflow */ |
2469cfa2 NC |
68 | bfd_elf_generic_reloc, /* special_function */ |
69 | "R_MSP430_NONE", /* name */ | |
70 | FALSE, /* partial_inplace */ | |
71 | 0, /* src_mask */ | |
72 | 0, /* dst_mask */ | |
73 | FALSE), /* pcrel_offset */ | |
74 | ||
75 | HOWTO (R_MSP430_32, /* type */ | |
76 | 0, /* rightshift */ | |
77 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
78 | 32, /* bitsize */ | |
79 | FALSE, /* pc_relative */ | |
80 | 0, /* bitpos */ | |
b18c562e | 81 | complain_overflow_bitfield,/* complain_on_overflow */ |
2469cfa2 NC |
82 | bfd_elf_generic_reloc, /* special_function */ |
83 | "R_MSP430_32", /* name */ | |
84 | FALSE, /* partial_inplace */ | |
85 | 0xffffffff, /* src_mask */ | |
86 | 0xffffffff, /* dst_mask */ | |
87 | FALSE), /* pcrel_offset */ | |
88 | ||
df301bfc | 89 | /* A 10 bit PC relative relocation. */ |
2469cfa2 NC |
90 | HOWTO (R_MSP430_10_PCREL, /* type */ |
91 | 1, /* rightshift */ | |
92 | 1, /* size (0 = byte, 1 = short, 2 = long) */ | |
93 | 10, /* bitsize */ | |
94 | TRUE, /* pc_relative */ | |
95 | 0, /* bitpos */ | |
b18c562e | 96 | complain_overflow_bitfield,/* complain_on_overflow */ |
2469cfa2 | 97 | bfd_elf_generic_reloc, /* special_function */ |
13761a11 | 98 | "R_MSP430_10_PCREL", /* name */ |
2469cfa2 | 99 | FALSE, /* partial_inplace */ |
df301bfc NC |
100 | 0x3ff, /* src_mask */ |
101 | 0x3ff, /* dst_mask */ | |
2469cfa2 NC |
102 | TRUE), /* pcrel_offset */ |
103 | ||
104 | /* A 16 bit absolute relocation. */ | |
105 | HOWTO (R_MSP430_16, /* type */ | |
106 | 0, /* rightshift */ | |
107 | 1, /* size (0 = byte, 1 = short, 2 = long) */ | |
108 | 16, /* bitsize */ | |
109 | FALSE, /* pc_relative */ | |
110 | 0, /* bitpos */ | |
111 | complain_overflow_dont,/* complain_on_overflow */ | |
112 | bfd_elf_generic_reloc, /* special_function */ | |
113 | "R_MSP430_16", /* name */ | |
114 | FALSE, /* partial_inplace */ | |
b18c562e | 115 | 0, /* src_mask */ |
2469cfa2 NC |
116 | 0xffff, /* dst_mask */ |
117 | FALSE), /* pcrel_offset */ | |
118 | ||
13761a11 | 119 | /* A 16 bit PC relative relocation for command address. */ |
2469cfa2 NC |
120 | HOWTO (R_MSP430_16_PCREL, /* type */ |
121 | 1, /* rightshift */ | |
122 | 1, /* size (0 = byte, 1 = short, 2 = long) */ | |
123 | 16, /* bitsize */ | |
124 | TRUE, /* pc_relative */ | |
125 | 0, /* bitpos */ | |
126 | complain_overflow_dont,/* complain_on_overflow */ | |
127 | bfd_elf_generic_reloc, /* special_function */ | |
128 | "R_MSP430_16_PCREL", /* name */ | |
129 | FALSE, /* partial_inplace */ | |
b18c562e | 130 | 0, /* src_mask */ |
2469cfa2 NC |
131 | 0xffff, /* dst_mask */ |
132 | TRUE), /* pcrel_offset */ | |
133 | ||
134 | /* A 16 bit absolute relocation, byte operations. */ | |
135 | HOWTO (R_MSP430_16_BYTE, /* type */ | |
136 | 0, /* rightshift */ | |
137 | 1, /* size (0 = byte, 1 = short, 2 = long) */ | |
138 | 16, /* bitsize */ | |
139 | FALSE, /* pc_relative */ | |
140 | 0, /* bitpos */ | |
141 | complain_overflow_dont,/* complain_on_overflow */ | |
142 | bfd_elf_generic_reloc, /* special_function */ | |
143 | "R_MSP430_16_BYTE", /* name */ | |
144 | FALSE, /* partial_inplace */ | |
145 | 0xffff, /* src_mask */ | |
146 | 0xffff, /* dst_mask */ | |
147 | FALSE), /* pcrel_offset */ | |
148 | ||
149 | /* A 16 bit absolute relocation for command address. */ | |
150 | HOWTO (R_MSP430_16_PCREL_BYTE,/* type */ | |
151 | 1, /* rightshift */ | |
152 | 1, /* size (0 = byte, 1 = short, 2 = long) */ | |
153 | 16, /* bitsize */ | |
154 | TRUE, /* pc_relative */ | |
155 | 0, /* bitpos */ | |
156 | complain_overflow_dont,/* complain_on_overflow */ | |
157 | bfd_elf_generic_reloc, /* special_function */ | |
b18c562e | 158 | "R_MSP430_16_PCREL_BYTE",/* name */ |
2469cfa2 NC |
159 | FALSE, /* partial_inplace */ |
160 | 0xffff, /* src_mask */ | |
161 | 0xffff, /* dst_mask */ | |
b18c562e NC |
162 | TRUE), /* pcrel_offset */ |
163 | ||
df301bfc | 164 | /* A 10 bit PC relative relocation for complicated polymorphs. */ |
b18c562e NC |
165 | HOWTO (R_MSP430_2X_PCREL, /* type */ |
166 | 1, /* rightshift */ | |
167 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
168 | 10, /* bitsize */ | |
169 | TRUE, /* pc_relative */ | |
170 | 0, /* bitpos */ | |
171 | complain_overflow_bitfield,/* complain_on_overflow */ | |
172 | bfd_elf_generic_reloc, /* special_function */ | |
173 | "R_MSP430_2X_PCREL", /* name */ | |
174 | FALSE, /* partial_inplace */ | |
df301bfc NC |
175 | 0x3ff, /* src_mask */ |
176 | 0x3ff, /* dst_mask */ | |
b18c562e NC |
177 | TRUE), /* pcrel_offset */ |
178 | ||
179 | /* A 16 bit relaxable relocation for command address. */ | |
180 | HOWTO (R_MSP430_RL_PCREL, /* type */ | |
181 | 1, /* rightshift */ | |
182 | 1, /* size (0 = byte, 1 = short, 2 = long) */ | |
183 | 16, /* bitsize */ | |
184 | TRUE, /* pc_relative */ | |
185 | 0, /* bitpos */ | |
186 | complain_overflow_dont,/* complain_on_overflow */ | |
187 | bfd_elf_generic_reloc, /* special_function */ | |
188 | "R_MSP430_RL_PCREL", /* name */ | |
189 | FALSE, /* partial_inplace */ | |
190 | 0, /* src_mask */ | |
191 | 0xffff, /* dst_mask */ | |
2469cfa2 | 192 | TRUE) /* pcrel_offset */ |
13761a11 NC |
193 | |
194 | /* A 8-bit absolute relocation. */ | |
195 | , HOWTO (R_MSP430_8, /* type */ | |
196 | 0, /* rightshift */ | |
197 | 0, /* size (0 = byte, 1 = short, 2 = long) */ | |
198 | 8, /* bitsize */ | |
199 | FALSE, /* pc_relative */ | |
200 | 0, /* bitpos */ | |
201 | complain_overflow_dont,/* complain_on_overflow */ | |
202 | bfd_elf_generic_reloc, /* special_function */ | |
203 | "R_MSP430_8", /* name */ | |
204 | FALSE, /* partial_inplace */ | |
205 | 0, /* src_mask */ | |
206 | 0xffff, /* dst_mask */ | |
207 | FALSE), /* pcrel_offset */ | |
208 | ||
209 | /* Together with a following reloc, allows for the difference | |
210 | between two symbols to be the real addend of the second reloc. */ | |
211 | HOWTO (R_MSP430_SYM_DIFF, /* type */ | |
212 | 0, /* rightshift */ | |
213 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
214 | 32, /* bitsize */ | |
215 | FALSE, /* pc_relative */ | |
216 | 0, /* bitpos */ | |
217 | complain_overflow_dont,/* complain_on_overflow */ | |
1ade7175 | 218 | rl78_sym_diff_handler, /* special handler. */ |
13761a11 NC |
219 | "R_MSP430_SYM_DIFF", /* name */ |
220 | FALSE, /* partial_inplace */ | |
221 | 0xffffffff, /* src_mask */ | |
222 | 0xffffffff, /* dst_mask */ | |
1b786873 | 223 | FALSE) /* pcrel_offset */ |
13761a11 NC |
224 | }; |
225 | ||
226 | static reloc_howto_type elf_msp430x_howto_table[] = | |
227 | { | |
228 | HOWTO (R_MSP430_NONE, /* type */ | |
229 | 0, /* rightshift */ | |
6346d5ca AM |
230 | 3, /* size (0 = byte, 1 = short, 2 = long) */ |
231 | 0, /* bitsize */ | |
13761a11 NC |
232 | FALSE, /* pc_relative */ |
233 | 0, /* bitpos */ | |
6346d5ca | 234 | complain_overflow_dont,/* complain_on_overflow */ |
13761a11 NC |
235 | bfd_elf_generic_reloc, /* special_function */ |
236 | "R_MSP430_NONE", /* name */ | |
237 | FALSE, /* partial_inplace */ | |
238 | 0, /* src_mask */ | |
239 | 0, /* dst_mask */ | |
240 | FALSE), /* pcrel_offset */ | |
241 | ||
242 | HOWTO (R_MSP430_ABS32, /* type */ | |
243 | 0, /* rightshift */ | |
244 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
245 | 32, /* bitsize */ | |
246 | FALSE, /* pc_relative */ | |
247 | 0, /* bitpos */ | |
248 | complain_overflow_bitfield,/* complain_on_overflow */ | |
249 | bfd_elf_generic_reloc, /* special_function */ | |
250 | "R_MSP430_ABS32", /* name */ | |
251 | FALSE, /* partial_inplace */ | |
252 | 0xffffffff, /* src_mask */ | |
253 | 0xffffffff, /* dst_mask */ | |
254 | FALSE), /* pcrel_offset */ | |
255 | ||
256 | HOWTO (R_MSP430_ABS16, /* type */ | |
257 | 0, /* rightshift */ | |
258 | 1, /* size (0 = byte, 1 = short, 2 = long) */ | |
259 | 16, /* bitsize */ | |
260 | FALSE, /* pc_relative */ | |
261 | 0, /* bitpos */ | |
262 | complain_overflow_dont,/* complain_on_overflow */ | |
263 | bfd_elf_generic_reloc, /* special_function */ | |
264 | "R_MSP430_ABS16", /* name */ | |
265 | FALSE, /* partial_inplace */ | |
266 | 0, /* src_mask */ | |
267 | 0xffff, /* dst_mask */ | |
268 | FALSE), /* pcrel_offset */ | |
269 | ||
270 | HOWTO (R_MSP430_ABS8, /* type */ | |
271 | 0, /* rightshift */ | |
272 | 0, /* size (0 = byte, 1 = short, 2 = long) */ | |
273 | 8, /* bitsize */ | |
274 | FALSE, /* pc_relative */ | |
275 | 0, /* bitpos */ | |
276 | complain_overflow_bitfield,/* complain_on_overflow */ | |
277 | bfd_elf_generic_reloc, /* special_function */ | |
278 | "R_MSP430_ABS8", /* name */ | |
279 | FALSE, /* partial_inplace */ | |
280 | 0xff, /* src_mask */ | |
281 | 0xff, /* dst_mask */ | |
282 | FALSE), /* pcrel_offset */ | |
283 | ||
284 | HOWTO (R_MSP430_PCR16, /* type */ | |
285 | 1, /* rightshift */ | |
286 | 1, /* size (0 = byte, 1 = short, 2 = long) */ | |
287 | 16, /* bitsize */ | |
288 | TRUE, /* pc_relative */ | |
289 | 0, /* bitpos */ | |
290 | complain_overflow_dont,/* complain_on_overflow */ | |
291 | bfd_elf_generic_reloc, /* special_function */ | |
292 | "R_MSP430_PCR16", /* name */ | |
293 | FALSE, /* partial_inplace */ | |
294 | 0, /* src_mask */ | |
295 | 0xffff, /* dst_mask */ | |
296 | TRUE), /* pcrel_offset */ | |
297 | ||
298 | HOWTO (R_MSP430X_PCR20_EXT_SRC,/* type */ | |
299 | 0, /* rightshift */ | |
300 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
301 | 32, /* bitsize */ | |
302 | TRUE, /* pc_relative */ | |
303 | 0, /* bitpos */ | |
304 | complain_overflow_dont,/* complain_on_overflow */ | |
305 | bfd_elf_generic_reloc, /* special_function */ | |
306 | "R_MSP430X_PCR20_EXT_SRC",/* name */ | |
307 | FALSE, /* partial_inplace */ | |
308 | 0, /* src_mask */ | |
309 | 0xffff, /* dst_mask */ | |
310 | TRUE), /* pcrel_offset */ | |
311 | ||
312 | HOWTO (R_MSP430X_PCR20_EXT_DST,/* type */ | |
313 | 0, /* rightshift */ | |
314 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
315 | 32, /* bitsize */ | |
316 | TRUE, /* pc_relative */ | |
317 | 0, /* bitpos */ | |
318 | complain_overflow_dont,/* complain_on_overflow */ | |
319 | bfd_elf_generic_reloc, /* special_function */ | |
320 | "R_MSP430X_PCR20_EXT_DST",/* name */ | |
321 | FALSE, /* partial_inplace */ | |
322 | 0, /* src_mask */ | |
323 | 0xffff, /* dst_mask */ | |
324 | TRUE), /* pcrel_offset */ | |
325 | ||
326 | HOWTO (R_MSP430X_PCR20_EXT_ODST,/* type */ | |
327 | 0, /* rightshift */ | |
328 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
329 | 32, /* bitsize */ | |
330 | TRUE, /* pc_relative */ | |
331 | 0, /* bitpos */ | |
332 | complain_overflow_dont,/* complain_on_overflow */ | |
333 | bfd_elf_generic_reloc, /* special_function */ | |
334 | "R_MSP430X_PCR20_EXT_ODST",/* name */ | |
335 | FALSE, /* partial_inplace */ | |
336 | 0, /* src_mask */ | |
337 | 0xffff, /* dst_mask */ | |
338 | TRUE), /* pcrel_offset */ | |
339 | ||
340 | HOWTO (R_MSP430X_ABS20_EXT_SRC,/* type */ | |
341 | 0, /* rightshift */ | |
342 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
343 | 32, /* bitsize */ | |
344 | TRUE, /* pc_relative */ | |
345 | 0, /* bitpos */ | |
346 | complain_overflow_dont,/* complain_on_overflow */ | |
347 | bfd_elf_generic_reloc, /* special_function */ | |
348 | "R_MSP430X_ABS20_EXT_SRC",/* name */ | |
349 | FALSE, /* partial_inplace */ | |
350 | 0, /* src_mask */ | |
351 | 0xffff, /* dst_mask */ | |
352 | TRUE), /* pcrel_offset */ | |
353 | ||
354 | HOWTO (R_MSP430X_ABS20_EXT_DST,/* type */ | |
355 | 0, /* rightshift */ | |
356 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
357 | 32, /* bitsize */ | |
358 | TRUE, /* pc_relative */ | |
359 | 0, /* bitpos */ | |
360 | complain_overflow_dont,/* complain_on_overflow */ | |
361 | bfd_elf_generic_reloc, /* special_function */ | |
362 | "R_MSP430X_ABS20_EXT_DST",/* name */ | |
363 | FALSE, /* partial_inplace */ | |
364 | 0, /* src_mask */ | |
365 | 0xffff, /* dst_mask */ | |
366 | TRUE), /* pcrel_offset */ | |
367 | ||
368 | HOWTO (R_MSP430X_ABS20_EXT_ODST,/* type */ | |
369 | 0, /* rightshift */ | |
370 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
371 | 32, /* bitsize */ | |
372 | TRUE, /* pc_relative */ | |
373 | 0, /* bitpos */ | |
374 | complain_overflow_dont,/* complain_on_overflow */ | |
375 | bfd_elf_generic_reloc, /* special_function */ | |
376 | "R_MSP430X_ABS20_EXT_ODST",/* name */ | |
377 | FALSE, /* partial_inplace */ | |
378 | 0, /* src_mask */ | |
379 | 0xffff, /* dst_mask */ | |
380 | TRUE), /* pcrel_offset */ | |
381 | ||
382 | HOWTO (R_MSP430X_ABS20_ADR_SRC,/* type */ | |
383 | 0, /* rightshift */ | |
384 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
385 | 32, /* bitsize */ | |
386 | TRUE, /* pc_relative */ | |
387 | 0, /* bitpos */ | |
388 | complain_overflow_dont,/* complain_on_overflow */ | |
389 | bfd_elf_generic_reloc, /* special_function */ | |
390 | "R_MSP430X_ABS20_ADR_SRC",/* name */ | |
391 | FALSE, /* partial_inplace */ | |
392 | 0, /* src_mask */ | |
393 | 0xffff, /* dst_mask */ | |
394 | TRUE), /* pcrel_offset */ | |
395 | ||
396 | HOWTO (R_MSP430X_ABS20_ADR_DST,/* type */ | |
397 | 0, /* rightshift */ | |
398 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
399 | 32, /* bitsize */ | |
400 | TRUE, /* pc_relative */ | |
401 | 0, /* bitpos */ | |
402 | complain_overflow_dont,/* complain_on_overflow */ | |
403 | bfd_elf_generic_reloc, /* special_function */ | |
404 | "R_MSP430X_ABS20_ADR_DST",/* name */ | |
405 | FALSE, /* partial_inplace */ | |
406 | 0, /* src_mask */ | |
407 | 0xffff, /* dst_mask */ | |
408 | TRUE), /* pcrel_offset */ | |
409 | ||
410 | HOWTO (R_MSP430X_PCR16, /* type */ | |
411 | 0, /* rightshift */ | |
412 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
413 | 32, /* bitsize */ | |
414 | TRUE, /* pc_relative */ | |
415 | 0, /* bitpos */ | |
416 | complain_overflow_dont,/* complain_on_overflow */ | |
417 | bfd_elf_generic_reloc, /* special_function */ | |
418 | "R_MSP430X_PCR16", /* name */ | |
419 | FALSE, /* partial_inplace */ | |
420 | 0, /* src_mask */ | |
421 | 0xffff, /* dst_mask */ | |
422 | TRUE), /* pcrel_offset */ | |
423 | ||
424 | HOWTO (R_MSP430X_PCR20_CALL, /* type */ | |
425 | 0, /* rightshift */ | |
426 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
427 | 32, /* bitsize */ | |
428 | TRUE, /* pc_relative */ | |
429 | 0, /* bitpos */ | |
430 | complain_overflow_dont,/* complain_on_overflow */ | |
431 | bfd_elf_generic_reloc, /* special_function */ | |
432 | "R_MSP430X_PCR20_CALL",/* name */ | |
433 | FALSE, /* partial_inplace */ | |
434 | 0, /* src_mask */ | |
435 | 0xffff, /* dst_mask */ | |
436 | TRUE), /* pcrel_offset */ | |
437 | ||
438 | HOWTO (R_MSP430X_ABS16, /* type */ | |
439 | 0, /* rightshift */ | |
440 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
441 | 32, /* bitsize */ | |
442 | TRUE, /* pc_relative */ | |
443 | 0, /* bitpos */ | |
444 | complain_overflow_dont,/* complain_on_overflow */ | |
445 | bfd_elf_generic_reloc, /* special_function */ | |
446 | "R_MSP430X_ABS16", /* name */ | |
447 | FALSE, /* partial_inplace */ | |
448 | 0, /* src_mask */ | |
449 | 0xffff, /* dst_mask */ | |
450 | TRUE), /* pcrel_offset */ | |
451 | ||
452 | HOWTO (R_MSP430_ABS_HI16, /* type */ | |
453 | 0, /* rightshift */ | |
454 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
455 | 32, /* bitsize */ | |
456 | TRUE, /* pc_relative */ | |
457 | 0, /* bitpos */ | |
458 | complain_overflow_dont,/* complain_on_overflow */ | |
459 | bfd_elf_generic_reloc, /* special_function */ | |
460 | "R_MSP430_ABS_HI16", /* name */ | |
461 | FALSE, /* partial_inplace */ | |
462 | 0, /* src_mask */ | |
463 | 0xffff, /* dst_mask */ | |
464 | TRUE), /* pcrel_offset */ | |
465 | ||
466 | HOWTO (R_MSP430_PREL31, /* type */ | |
467 | 0, /* rightshift */ | |
468 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
469 | 32, /* bitsize */ | |
470 | TRUE, /* pc_relative */ | |
471 | 0, /* bitpos */ | |
472 | complain_overflow_dont,/* complain_on_overflow */ | |
473 | bfd_elf_generic_reloc, /* special_function */ | |
474 | "R_MSP430_PREL31", /* name */ | |
475 | FALSE, /* partial_inplace */ | |
476 | 0, /* src_mask */ | |
477 | 0xffff, /* dst_mask */ | |
07d6d2b8 | 478 | TRUE), /* pcrel_offset */ |
13761a11 NC |
479 | |
480 | EMPTY_HOWTO (R_MSP430_EHTYPE), | |
1b786873 | 481 | |
df301bfc | 482 | /* A 10 bit PC relative relocation. */ |
13761a11 NC |
483 | HOWTO (R_MSP430X_10_PCREL, /* type */ |
484 | 1, /* rightshift */ | |
485 | 1, /* size (0 = byte, 1 = short, 2 = long) */ | |
486 | 10, /* bitsize */ | |
487 | TRUE, /* pc_relative */ | |
488 | 0, /* bitpos */ | |
489 | complain_overflow_bitfield,/* complain_on_overflow */ | |
490 | bfd_elf_generic_reloc, /* special_function */ | |
491 | "R_MSP430X_10_PCREL", /* name */ | |
492 | FALSE, /* partial_inplace */ | |
df301bfc NC |
493 | 0x3ff, /* src_mask */ |
494 | 0x3ff, /* dst_mask */ | |
07d6d2b8 | 495 | TRUE), /* pcrel_offset */ |
13761a11 | 496 | |
df301bfc | 497 | /* A 10 bit PC relative relocation for complicated polymorphs. */ |
13761a11 NC |
498 | HOWTO (R_MSP430X_2X_PCREL, /* type */ |
499 | 1, /* rightshift */ | |
500 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
501 | 10, /* bitsize */ | |
502 | TRUE, /* pc_relative */ | |
503 | 0, /* bitpos */ | |
504 | complain_overflow_bitfield,/* complain_on_overflow */ | |
505 | bfd_elf_generic_reloc, /* special_function */ | |
506 | "R_MSP430X_2X_PCREL", /* name */ | |
507 | FALSE, /* partial_inplace */ | |
df301bfc NC |
508 | 0x3ff, /* src_mask */ |
509 | 0x3ff, /* dst_mask */ | |
13761a11 NC |
510 | TRUE), /* pcrel_offset */ |
511 | ||
512 | /* Together with a following reloc, allows for the difference | |
513 | between two symbols to be the real addend of the second reloc. */ | |
514 | HOWTO (R_MSP430X_SYM_DIFF, /* type */ | |
515 | 0, /* rightshift */ | |
516 | 2, /* size (0 = byte, 1 = short, 2 = long) */ | |
517 | 32, /* bitsize */ | |
518 | FALSE, /* pc_relative */ | |
519 | 0, /* bitpos */ | |
520 | complain_overflow_dont,/* complain_on_overflow */ | |
1ade7175 | 521 | rl78_sym_diff_handler, /* special handler. */ |
13761a11 NC |
522 | "R_MSP430X_SYM_DIFF", /* name */ |
523 | FALSE, /* partial_inplace */ | |
524 | 0xffffffff, /* src_mask */ | |
525 | 0xffffffff, /* dst_mask */ | |
1b786873 | 526 | FALSE) /* pcrel_offset */ |
2469cfa2 NC |
527 | }; |
528 | ||
529 | /* Map BFD reloc types to MSP430 ELF reloc types. */ | |
530 | ||
531 | struct msp430_reloc_map | |
532 | { | |
533 | bfd_reloc_code_real_type bfd_reloc_val; | |
534 | unsigned int elf_reloc_val; | |
535 | }; | |
536 | ||
537 | static const struct msp430_reloc_map msp430_reloc_map[] = | |
13761a11 | 538 | { |
07d6d2b8 AM |
539 | {BFD_RELOC_NONE, R_MSP430_NONE}, |
540 | {BFD_RELOC_32, R_MSP430_32}, | |
541 | {BFD_RELOC_MSP430_10_PCREL, R_MSP430_10_PCREL}, | |
542 | {BFD_RELOC_16, R_MSP430_16_BYTE}, | |
543 | {BFD_RELOC_MSP430_16_PCREL, R_MSP430_16_PCREL}, | |
544 | {BFD_RELOC_MSP430_16, R_MSP430_16}, | |
13761a11 | 545 | {BFD_RELOC_MSP430_16_PCREL_BYTE, R_MSP430_16_PCREL_BYTE}, |
07d6d2b8 AM |
546 | {BFD_RELOC_MSP430_16_BYTE, R_MSP430_16_BYTE}, |
547 | {BFD_RELOC_MSP430_2X_PCREL, R_MSP430_2X_PCREL}, | |
548 | {BFD_RELOC_MSP430_RL_PCREL, R_MSP430_RL_PCREL}, | |
549 | {BFD_RELOC_8, R_MSP430_8}, | |
550 | {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430_SYM_DIFF} | |
13761a11 NC |
551 | }; |
552 | ||
553 | static const struct msp430_reloc_map msp430x_reloc_map[] = | |
554 | { | |
07d6d2b8 AM |
555 | {BFD_RELOC_NONE, R_MSP430_NONE}, |
556 | {BFD_RELOC_32, R_MSP430_ABS32}, | |
557 | {BFD_RELOC_16, R_MSP430_ABS16}, | |
558 | {BFD_RELOC_8, R_MSP430_ABS8}, | |
559 | {BFD_RELOC_MSP430_ABS8, R_MSP430_ABS8}, | |
13761a11 NC |
560 | {BFD_RELOC_MSP430X_PCR20_EXT_SRC, R_MSP430X_PCR20_EXT_SRC}, |
561 | {BFD_RELOC_MSP430X_PCR20_EXT_DST, R_MSP430X_PCR20_EXT_DST}, | |
562 | {BFD_RELOC_MSP430X_PCR20_EXT_ODST, R_MSP430X_PCR20_EXT_ODST}, | |
563 | {BFD_RELOC_MSP430X_ABS20_EXT_SRC, R_MSP430X_ABS20_EXT_SRC}, | |
564 | {BFD_RELOC_MSP430X_ABS20_EXT_DST, R_MSP430X_ABS20_EXT_DST}, | |
565 | {BFD_RELOC_MSP430X_ABS20_EXT_ODST, R_MSP430X_ABS20_EXT_ODST}, | |
566 | {BFD_RELOC_MSP430X_ABS20_ADR_SRC, R_MSP430X_ABS20_ADR_SRC}, | |
567 | {BFD_RELOC_MSP430X_ABS20_ADR_DST, R_MSP430X_ABS20_ADR_DST}, | |
07d6d2b8 | 568 | {BFD_RELOC_MSP430X_PCR16, R_MSP430X_PCR16}, |
13761a11 | 569 | {BFD_RELOC_MSP430X_PCR20_CALL, R_MSP430X_PCR20_CALL}, |
07d6d2b8 AM |
570 | {BFD_RELOC_MSP430X_ABS16, R_MSP430X_ABS16}, |
571 | {BFD_RELOC_MSP430_ABS_HI16, R_MSP430_ABS_HI16}, | |
572 | {BFD_RELOC_MSP430_PREL31, R_MSP430_PREL31}, | |
573 | {BFD_RELOC_MSP430_10_PCREL, R_MSP430X_10_PCREL}, | |
574 | {BFD_RELOC_MSP430_2X_PCREL, R_MSP430X_2X_PCREL}, | |
575 | {BFD_RELOC_MSP430_RL_PCREL, R_MSP430X_PCR16}, | |
576 | {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430X_SYM_DIFF} | |
13761a11 NC |
577 | }; |
578 | ||
579 | static inline bfd_boolean | |
580 | uses_msp430x_relocs (bfd * abfd) | |
581 | { | |
6d00b590 | 582 | extern const bfd_target msp430_elf32_ti_vec; |
13761a11 NC |
583 | |
584 | return bfd_get_mach (abfd) == bfd_mach_msp430x | |
6d00b590 | 585 | || abfd->xvec == & msp430_elf32_ti_vec; |
13761a11 | 586 | } |
2469cfa2 NC |
587 | |
588 | static reloc_howto_type * | |
b18c562e NC |
589 | bfd_elf32_bfd_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, |
590 | bfd_reloc_code_real_type code) | |
2469cfa2 NC |
591 | { |
592 | unsigned int i; | |
593 | ||
13761a11 NC |
594 | if (uses_msp430x_relocs (abfd)) |
595 | { | |
596 | for (i = ARRAY_SIZE (msp430x_reloc_map); i--;) | |
597 | if (msp430x_reloc_map[i].bfd_reloc_val == code) | |
598 | return elf_msp430x_howto_table + msp430x_reloc_map[i].elf_reloc_val; | |
599 | } | |
600 | else | |
601 | { | |
602 | for (i = 0; i < ARRAY_SIZE (msp430_reloc_map); i++) | |
603 | if (msp430_reloc_map[i].bfd_reloc_val == code) | |
604 | return &elf_msp430_howto_table[msp430_reloc_map[i].elf_reloc_val]; | |
605 | } | |
2469cfa2 NC |
606 | |
607 | return NULL; | |
608 | } | |
609 | ||
157090f7 AM |
610 | static reloc_howto_type * |
611 | bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, | |
612 | const char *r_name) | |
613 | { | |
614 | unsigned int i; | |
615 | ||
13761a11 NC |
616 | if (uses_msp430x_relocs (abfd)) |
617 | { | |
618 | for (i = ARRAY_SIZE (elf_msp430x_howto_table); i--;) | |
619 | if (elf_msp430x_howto_table[i].name != NULL | |
620 | && strcasecmp (elf_msp430x_howto_table[i].name, r_name) == 0) | |
621 | return elf_msp430x_howto_table + i; | |
622 | } | |
623 | else | |
624 | { | |
625 | for (i = 0; | |
626 | i < (sizeof (elf_msp430_howto_table) | |
627 | / sizeof (elf_msp430_howto_table[0])); | |
628 | i++) | |
629 | if (elf_msp430_howto_table[i].name != NULL | |
630 | && strcasecmp (elf_msp430_howto_table[i].name, r_name) == 0) | |
631 | return &elf_msp430_howto_table[i]; | |
632 | } | |
157090f7 AM |
633 | |
634 | return NULL; | |
635 | } | |
636 | ||
2469cfa2 NC |
637 | /* Set the howto pointer for an MSP430 ELF reloc. */ |
638 | ||
f3185997 | 639 | static bfd_boolean |
0aa13fee | 640 | msp430_info_to_howto_rela (bfd * abfd, |
b18c562e NC |
641 | arelent * cache_ptr, |
642 | Elf_Internal_Rela * dst) | |
2469cfa2 NC |
643 | { |
644 | unsigned int r_type; | |
645 | ||
646 | r_type = ELF32_R_TYPE (dst->r_info); | |
13761a11 NC |
647 | |
648 | if (uses_msp430x_relocs (abfd)) | |
649 | { | |
5860e3f8 NC |
650 | if (r_type >= (unsigned int) R_MSP430x_max) |
651 | { | |
695344c0 | 652 | /* xgettext:c-format */ |
0aa13fee AM |
653 | _bfd_error_handler (_("%pB: unsupported relocation type %#x"), |
654 | abfd, r_type); | |
f3185997 NC |
655 | bfd_set_error (bfd_error_bad_value); |
656 | return FALSE; | |
5860e3f8 | 657 | } |
13761a11 | 658 | cache_ptr->howto = elf_msp430x_howto_table + r_type; |
13761a11 | 659 | } |
f3185997 | 660 | else if (r_type >= (unsigned int) R_MSP430_max) |
5860e3f8 | 661 | { |
695344c0 | 662 | /* xgettext:c-format */ |
0aa13fee AM |
663 | _bfd_error_handler (_("%pB: unsupported relocation type %#x"), |
664 | abfd, r_type); | |
f3185997 NC |
665 | bfd_set_error (bfd_error_bad_value); |
666 | return FALSE; | |
5860e3f8 | 667 | } |
f3185997 NC |
668 | else |
669 | cache_ptr->howto = &elf_msp430_howto_table[r_type]; | |
670 | ||
671 | return TRUE; | |
2469cfa2 NC |
672 | } |
673 | ||
2469cfa2 NC |
674 | /* Look through the relocs for a section during the first phase. |
675 | Since we don't do .gots or .plts, we just need to consider the | |
676 | virtual table relocs for gc. */ | |
677 | ||
678 | static bfd_boolean | |
b18c562e NC |
679 | elf32_msp430_check_relocs (bfd * abfd, struct bfd_link_info * info, |
680 | asection * sec, const Elf_Internal_Rela * relocs) | |
2469cfa2 NC |
681 | { |
682 | Elf_Internal_Shdr *symtab_hdr; | |
5582a088 | 683 | struct elf_link_hash_entry **sym_hashes; |
2469cfa2 NC |
684 | const Elf_Internal_Rela *rel; |
685 | const Elf_Internal_Rela *rel_end; | |
686 | ||
0e1862bb | 687 | if (bfd_link_relocatable (info)) |
2469cfa2 NC |
688 | return TRUE; |
689 | ||
690 | symtab_hdr = &elf_tdata (abfd)->symtab_hdr; | |
691 | sym_hashes = elf_sym_hashes (abfd); | |
2469cfa2 NC |
692 | |
693 | rel_end = relocs + sec->reloc_count; | |
694 | for (rel = relocs; rel < rel_end; rel++) | |
695 | { | |
696 | struct elf_link_hash_entry *h; | |
697 | unsigned long r_symndx; | |
698 | ||
699 | r_symndx = ELF32_R_SYM (rel->r_info); | |
700 | if (r_symndx < symtab_hdr->sh_info) | |
701 | h = NULL; | |
702 | else | |
973a3492 L |
703 | { |
704 | h = sym_hashes[r_symndx - symtab_hdr->sh_info]; | |
705 | while (h->root.type == bfd_link_hash_indirect | |
706 | || h->root.type == bfd_link_hash_warning) | |
707 | h = (struct elf_link_hash_entry *) h->root.u.i.link; | |
708 | } | |
2469cfa2 NC |
709 | } |
710 | ||
711 | return TRUE; | |
712 | } | |
713 | ||
714 | /* Perform a single relocation. By default we use the standard BFD | |
715 | routines, but a few relocs, we have to do them ourselves. */ | |
716 | ||
717 | static bfd_reloc_status_type | |
07d6d2b8 AM |
718 | msp430_final_link_relocate (reloc_howto_type * howto, |
719 | bfd * input_bfd, | |
720 | asection * input_section, | |
721 | bfd_byte * contents, | |
722 | Elf_Internal_Rela * rel, | |
723 | bfd_vma relocation, | |
13761a11 | 724 | struct bfd_link_info * info) |
2469cfa2 | 725 | { |
13761a11 NC |
726 | static asection * sym_diff_section; |
727 | static bfd_vma sym_diff_value; | |
728 | ||
729 | struct bfd_elf_section_data * esd = elf_section_data (input_section); | |
2469cfa2 NC |
730 | bfd_reloc_status_type r = bfd_reloc_ok; |
731 | bfd_vma x; | |
732 | bfd_signed_vma srel; | |
13761a11 NC |
733 | bfd_boolean is_rel_reloc = FALSE; |
734 | ||
735 | if (uses_msp430x_relocs (input_bfd)) | |
736 | { | |
737 | /* See if we have a REL type relocation. */ | |
738 | is_rel_reloc = (esd->rel.hdr != NULL); | |
739 | /* Sanity check - only one type of relocation per section. | |
740 | FIXME: Theoretically it is possible to have both types, | |
741 | but if that happens how can we distinguish between the two ? */ | |
742 | BFD_ASSERT (! is_rel_reloc || ! esd->rela.hdr); | |
743 | /* If we are using a REL relocation then the addend should be empty. */ | |
744 | BFD_ASSERT (! is_rel_reloc || rel->r_addend == 0); | |
745 | } | |
2469cfa2 | 746 | |
d60f5448 JL |
747 | if (debug_relocs) |
748 | printf ("writing relocation (%p) at 0x%lx type: %d\n", rel, | |
c675ec1e NC |
749 | (long) (input_section->output_section->vma + input_section->output_offset |
750 | + rel->r_offset), howto->type); | |
13761a11 | 751 | if (sym_diff_section != NULL) |
2469cfa2 | 752 | { |
13761a11 | 753 | BFD_ASSERT (sym_diff_section == input_section); |
1b786873 | 754 | |
13761a11 NC |
755 | if (uses_msp430x_relocs (input_bfd)) |
756 | switch (howto->type) | |
757 | { | |
758 | case R_MSP430_ABS32: | |
759 | /* If we are computing a 32-bit value for the location lists | |
760 | and the result is 0 then we add one to the value. A zero | |
761 | value can result because of linker relaxation deleteing | |
762 | prologue instructions and using a value of 1 (for the begin | |
763 | and end offsets in the location list entry) results in a | |
764 | nul entry which does not prevent the following entries from | |
765 | being parsed. */ | |
766 | if (relocation == sym_diff_value | |
767 | && strcmp (input_section->name, ".debug_loc") == 0) | |
768 | ++ relocation; | |
769 | /* Fall through. */ | |
770 | case R_MSP430_ABS16: | |
771 | case R_MSP430X_ABS16: | |
772 | case R_MSP430_ABS8: | |
773 | BFD_ASSERT (! is_rel_reloc); | |
774 | relocation -= sym_diff_value; | |
775 | break; | |
776 | ||
777 | default: | |
778 | return bfd_reloc_dangerous; | |
779 | } | |
780 | else | |
781 | switch (howto->type) | |
782 | { | |
783 | case R_MSP430_32: | |
784 | case R_MSP430_16: | |
785 | case R_MSP430_16_BYTE: | |
786 | case R_MSP430_8: | |
787 | relocation -= sym_diff_value; | |
788 | break; | |
789 | ||
790 | default: | |
791 | return bfd_reloc_dangerous; | |
792 | } | |
1b786873 | 793 | |
13761a11 NC |
794 | sym_diff_section = NULL; |
795 | } | |
796 | ||
797 | if (uses_msp430x_relocs (input_bfd)) | |
798 | switch (howto->type) | |
799 | { | |
800 | case R_MSP430X_SYM_DIFF: | |
801 | /* Cache the input section and value. | |
802 | The offset is unreliable, since relaxation may | |
803 | have reduced the following reloc's offset. */ | |
804 | BFD_ASSERT (! is_rel_reloc); | |
805 | sym_diff_section = input_section; | |
806 | sym_diff_value = relocation; | |
807 | return bfd_reloc_ok; | |
808 | ||
809 | case R_MSP430_ABS16: | |
810 | contents += rel->r_offset; | |
811 | srel = (bfd_signed_vma) relocation; | |
812 | if (is_rel_reloc) | |
813 | srel += bfd_get_16 (input_bfd, contents); | |
814 | else | |
815 | srel += rel->r_addend; | |
816 | bfd_put_16 (input_bfd, srel & 0xffff, contents); | |
817 | break; | |
818 | ||
819 | case R_MSP430X_10_PCREL: | |
820 | contents += rel->r_offset; | |
821 | srel = (bfd_signed_vma) relocation; | |
822 | if (is_rel_reloc) | |
823 | srel += bfd_get_16 (input_bfd, contents) & 0x3ff; | |
824 | else | |
825 | srel += rel->r_addend; | |
826 | srel -= rel->r_offset; | |
827 | srel -= 2; /* Branch instructions add 2 to the PC... */ | |
828 | srel -= (input_section->output_section->vma + | |
829 | input_section->output_offset); | |
830 | if (srel & 1) | |
831 | return bfd_reloc_outofrange; | |
832 | ||
833 | /* MSP430 addresses commands as words. */ | |
834 | srel >>= 1; | |
835 | ||
836 | /* Check for an overflow. */ | |
837 | if (srel < -512 || srel > 511) | |
838 | { | |
839 | if (info->disable_target_specific_optimizations < 0) | |
840 | { | |
841 | static bfd_boolean warned = FALSE; | |
842 | if (! warned) | |
843 | { | |
844 | info->callbacks->warning | |
845 | (info, | |
38f14ab8 | 846 | _("try enabling relaxation to avoid relocation truncations"), |
13761a11 NC |
847 | NULL, input_bfd, input_section, relocation); |
848 | warned = TRUE; | |
849 | } | |
850 | } | |
851 | return bfd_reloc_overflow; | |
852 | } | |
853 | ||
854 | x = bfd_get_16 (input_bfd, contents); | |
855 | x = (x & 0xfc00) | (srel & 0x3ff); | |
856 | bfd_put_16 (input_bfd, x, contents); | |
857 | break; | |
858 | ||
859 | case R_MSP430X_PCR20_EXT_ODST: | |
3f307074 | 860 | /* [0,4]+[48,16] = ---F ---- ---- FFFF */ |
13761a11 NC |
861 | contents += rel->r_offset; |
862 | srel = (bfd_signed_vma) relocation; | |
863 | if (is_rel_reloc) | |
864 | { | |
865 | bfd_vma addend; | |
866 | addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16; | |
3f307074 | 867 | addend |= bfd_get_16 (input_bfd, contents + 6); |
13761a11 | 868 | srel += addend; |
1b786873 | 869 | |
13761a11 NC |
870 | } |
871 | else | |
872 | srel += rel->r_addend; | |
873 | srel -= rel->r_offset; | |
874 | srel -= (input_section->output_section->vma + | |
875 | input_section->output_offset); | |
876 | bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6); | |
877 | x = bfd_get_16 (input_bfd, contents); | |
878 | x = (x & 0xfff0) | ((srel >> 16) & 0xf); | |
879 | bfd_put_16 (input_bfd, x, contents); | |
880 | break; | |
881 | ||
882 | case R_MSP430X_ABS20_EXT_SRC: | |
3f307074 | 883 | /* [7,4]+[32,16] = -78- ---- FFFF */ |
13761a11 NC |
884 | contents += rel->r_offset; |
885 | srel = (bfd_signed_vma) relocation; | |
886 | if (is_rel_reloc) | |
887 | { | |
888 | bfd_vma addend; | |
889 | addend = (bfd_get_16 (input_bfd, contents) & 0x0780) << 9; | |
3f307074 | 890 | addend |= bfd_get_16 (input_bfd, contents + 4); |
13761a11 NC |
891 | srel += addend; |
892 | } | |
893 | else | |
894 | srel += rel->r_addend; | |
895 | bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4); | |
896 | srel >>= 16; | |
897 | x = bfd_get_16 (input_bfd, contents); | |
898 | x = (x & 0xf87f) | ((srel << 7) & 0x0780); | |
899 | bfd_put_16 (input_bfd, x, contents); | |
900 | break; | |
901 | ||
902 | case R_MSP430_16_PCREL: | |
903 | contents += rel->r_offset; | |
904 | srel = (bfd_signed_vma) relocation; | |
905 | if (is_rel_reloc) | |
906 | srel += bfd_get_16 (input_bfd, contents); | |
907 | else | |
908 | srel += rel->r_addend; | |
909 | srel -= rel->r_offset; | |
910 | /* Only branch instructions add 2 to the PC... */ | |
911 | srel -= (input_section->output_section->vma + | |
912 | input_section->output_offset); | |
913 | if (srel & 1) | |
914 | return bfd_reloc_outofrange; | |
915 | bfd_put_16 (input_bfd, srel & 0xffff, contents); | |
916 | break; | |
917 | ||
918 | case R_MSP430X_PCR20_EXT_DST: | |
3f307074 | 919 | /* [0,4]+[32,16] = ---F ---- FFFF */ |
13761a11 NC |
920 | contents += rel->r_offset; |
921 | srel = (bfd_signed_vma) relocation; | |
922 | if (is_rel_reloc) | |
923 | { | |
924 | bfd_vma addend; | |
925 | addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16; | |
3f307074 | 926 | addend |= bfd_get_16 (input_bfd, contents + 4); |
13761a11 NC |
927 | srel += addend; |
928 | } | |
929 | else | |
930 | srel += rel->r_addend; | |
931 | srel -= rel->r_offset; | |
932 | srel -= (input_section->output_section->vma + | |
933 | input_section->output_offset); | |
934 | bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4); | |
935 | srel >>= 16; | |
936 | x = bfd_get_16 (input_bfd, contents); | |
937 | x = (x & 0xfff0) | (srel & 0xf); | |
938 | bfd_put_16 (input_bfd, x, contents); | |
939 | break; | |
940 | ||
941 | case R_MSP430X_PCR20_EXT_SRC: | |
3f307074 | 942 | /* [7,4]+[32,16] = -78- ---- FFFF */ |
13761a11 NC |
943 | contents += rel->r_offset; |
944 | srel = (bfd_signed_vma) relocation; | |
945 | if (is_rel_reloc) | |
946 | { | |
947 | bfd_vma addend; | |
948 | addend = ((bfd_get_16 (input_bfd, contents) & 0x0780) << 9); | |
3f307074 | 949 | addend |= bfd_get_16 (input_bfd, contents + 4); |
13761a11 NC |
950 | srel += addend;; |
951 | } | |
952 | else | |
953 | srel += rel->r_addend; | |
954 | srel -= rel->r_offset; | |
955 | /* Only branch instructions add 2 to the PC... */ | |
956 | srel -= (input_section->output_section->vma + | |
957 | input_section->output_offset); | |
958 | bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4); | |
959 | srel >>= 16; | |
960 | x = bfd_get_16 (input_bfd, contents); | |
961 | x = (x & 0xf87f) | ((srel << 7) & 0x0780); | |
962 | bfd_put_16 (input_bfd, x, contents); | |
963 | break; | |
964 | ||
965 | case R_MSP430_ABS8: | |
966 | contents += rel->r_offset; | |
967 | srel = (bfd_signed_vma) relocation; | |
968 | if (is_rel_reloc) | |
969 | srel += bfd_get_8 (input_bfd, contents); | |
970 | else | |
971 | srel += rel->r_addend; | |
972 | bfd_put_8 (input_bfd, srel & 0xff, contents); | |
973 | break; | |
974 | ||
975 | case R_MSP430X_ABS20_EXT_DST: | |
3f307074 | 976 | /* [0,4]+[32,16] = ---F ---- FFFF */ |
13761a11 NC |
977 | contents += rel->r_offset; |
978 | srel = (bfd_signed_vma) relocation; | |
979 | if (is_rel_reloc) | |
3f307074 DD |
980 | { |
981 | bfd_vma addend; | |
982 | addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16; | |
983 | addend |= bfd_get_16 (input_bfd, contents + 4); | |
984 | srel += addend; | |
985 | } | |
13761a11 NC |
986 | else |
987 | srel += rel->r_addend; | |
988 | bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4); | |
989 | srel >>= 16; | |
990 | x = bfd_get_16 (input_bfd, contents); | |
991 | x = (x & 0xfff0) | (srel & 0xf); | |
992 | bfd_put_16 (input_bfd, x, contents); | |
993 | break; | |
994 | ||
995 | case R_MSP430X_ABS20_EXT_ODST: | |
3f307074 | 996 | /* [0,4]+[48,16] = ---F ---- ---- FFFF */ |
13761a11 NC |
997 | contents += rel->r_offset; |
998 | srel = (bfd_signed_vma) relocation; | |
999 | if (is_rel_reloc) | |
1000 | { | |
1001 | bfd_vma addend; | |
1002 | addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16; | |
3f307074 | 1003 | addend |= bfd_get_16 (input_bfd, contents + 6); |
13761a11 NC |
1004 | srel += addend; |
1005 | } | |
1006 | else | |
1007 | srel += rel->r_addend; | |
1008 | bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6); | |
1009 | srel >>= 16; | |
1010 | x = bfd_get_16 (input_bfd, contents); | |
1011 | x = (x & 0xfff0) | (srel & 0xf); | |
1012 | bfd_put_16 (input_bfd, x, contents); | |
1013 | break; | |
1014 | ||
1015 | case R_MSP430X_ABS20_ADR_SRC: | |
3f307074 | 1016 | /* [8,4]+[16,16] = -F-- FFFF */ |
13761a11 NC |
1017 | contents += rel->r_offset; |
1018 | srel = (bfd_signed_vma) relocation; | |
1019 | if (is_rel_reloc) | |
1020 | { | |
1021 | bfd_vma addend; | |
1022 | ||
1023 | addend = ((bfd_get_16 (input_bfd, contents) & 0xf00) << 8); | |
3f307074 | 1024 | addend |= bfd_get_16 (input_bfd, contents + 2); |
13761a11 NC |
1025 | srel += addend; |
1026 | } | |
1027 | else | |
1028 | srel += rel->r_addend; | |
1029 | bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2); | |
1030 | srel >>= 16; | |
1031 | x = bfd_get_16 (input_bfd, contents); | |
1032 | x = (x & 0xf0ff) | ((srel << 8) & 0x0f00); | |
1033 | bfd_put_16 (input_bfd, x, contents); | |
1034 | break; | |
1035 | ||
1036 | case R_MSP430X_ABS20_ADR_DST: | |
3f307074 | 1037 | /* [0,4]+[16,16] = ---F FFFF */ |
13761a11 NC |
1038 | contents += rel->r_offset; |
1039 | srel = (bfd_signed_vma) relocation; | |
1040 | if (is_rel_reloc) | |
1041 | { | |
1042 | bfd_vma addend; | |
1043 | addend = ((bfd_get_16 (input_bfd, contents) & 0xf) << 16); | |
3f307074 | 1044 | addend |= bfd_get_16 (input_bfd, contents + 2); |
13761a11 NC |
1045 | srel += addend; |
1046 | } | |
1047 | else | |
1048 | srel += rel->r_addend; | |
1049 | bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2); | |
1050 | srel >>= 16; | |
1051 | x = bfd_get_16 (input_bfd, contents); | |
1052 | x = (x & 0xfff0) | (srel & 0xf); | |
1053 | bfd_put_16 (input_bfd, x, contents); | |
1054 | break; | |
1055 | ||
1056 | case R_MSP430X_ABS16: | |
1057 | contents += rel->r_offset; | |
1058 | srel = (bfd_signed_vma) relocation; | |
1059 | if (is_rel_reloc) | |
1060 | srel += bfd_get_16 (input_bfd, contents); | |
1061 | else | |
1062 | srel += rel->r_addend; | |
1063 | x = srel; | |
1064 | if (x > 0xffff) | |
1b786873 | 1065 | return bfd_reloc_overflow; |
13761a11 NC |
1066 | bfd_put_16 (input_bfd, srel & 0xffff, contents); |
1067 | break; | |
1068 | ||
1069 | case R_MSP430_ABS_HI16: | |
1070 | /* The EABI specifies that this must be a RELA reloc. */ | |
1071 | BFD_ASSERT (! is_rel_reloc); | |
1072 | contents += rel->r_offset; | |
1073 | srel = (bfd_signed_vma) relocation; | |
1074 | srel += rel->r_addend; | |
1075 | bfd_put_16 (input_bfd, (srel >> 16) & 0xffff, contents); | |
1076 | break; | |
1b786873 | 1077 | |
13761a11 | 1078 | case R_MSP430X_PCR20_CALL: |
3f307074 | 1079 | /* [0,4]+[16,16] = ---F FFFF*/ |
13761a11 NC |
1080 | contents += rel->r_offset; |
1081 | srel = (bfd_signed_vma) relocation; | |
1082 | if (is_rel_reloc) | |
1083 | { | |
1084 | bfd_vma addend; | |
1085 | addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16; | |
3f307074 | 1086 | addend |= bfd_get_16 (input_bfd, contents + 2); |
13761a11 NC |
1087 | srel += addend; |
1088 | } | |
1089 | else | |
1090 | srel += rel->r_addend; | |
1091 | srel -= rel->r_offset; | |
1092 | srel -= (input_section->output_section->vma + | |
1093 | input_section->output_offset); | |
1094 | bfd_put_16 (input_bfd, srel & 0xffff, contents + 2); | |
1095 | srel >>= 16; | |
1096 | x = bfd_get_16 (input_bfd, contents); | |
1097 | x = (x & 0xfff0) | (srel & 0xf); | |
1098 | bfd_put_16 (input_bfd, x, contents); | |
1099 | break; | |
1b786873 | 1100 | |
13761a11 NC |
1101 | case R_MSP430X_PCR16: |
1102 | contents += rel->r_offset; | |
1103 | srel = (bfd_signed_vma) relocation; | |
1104 | if (is_rel_reloc) | |
1105 | srel += bfd_get_16 (input_bfd, contents); | |
1106 | else | |
1107 | srel += rel->r_addend; | |
1108 | srel -= rel->r_offset; | |
1109 | srel -= (input_section->output_section->vma + | |
1110 | input_section->output_offset); | |
1111 | bfd_put_16 (input_bfd, srel & 0xffff, contents); | |
1112 | break; | |
1b786873 | 1113 | |
13761a11 NC |
1114 | case R_MSP430_PREL31: |
1115 | contents += rel->r_offset; | |
1116 | srel = (bfd_signed_vma) relocation; | |
1117 | if (is_rel_reloc) | |
1118 | srel += (bfd_get_32 (input_bfd, contents) & 0x7fffffff); | |
1119 | else | |
1120 | srel += rel->r_addend; | |
1121 | srel += rel->r_addend; | |
1122 | x = bfd_get_32 (input_bfd, contents); | |
1123 | x = (x & 0x80000000) | ((srel >> 31) & 0x7fffffff); | |
1124 | bfd_put_32 (input_bfd, x, contents); | |
1125 | break; | |
1b786873 | 1126 | |
13761a11 NC |
1127 | default: |
1128 | r = _bfd_final_link_relocate (howto, input_bfd, input_section, | |
1129 | contents, rel->r_offset, | |
1130 | relocation, rel->r_addend); | |
1131 | } | |
1132 | else | |
1133 | switch (howto->type) | |
1134 | { | |
2469cfa2 NC |
1135 | case R_MSP430_10_PCREL: |
1136 | contents += rel->r_offset; | |
1137 | srel = (bfd_signed_vma) relocation; | |
1138 | srel += rel->r_addend; | |
1139 | srel -= rel->r_offset; | |
1140 | srel -= 2; /* Branch instructions add 2 to the PC... */ | |
1141 | srel -= (input_section->output_section->vma + | |
1142 | input_section->output_offset); | |
1143 | ||
1144 | if (srel & 1) | |
1145 | return bfd_reloc_outofrange; | |
1146 | ||
1147 | /* MSP430 addresses commands as words. */ | |
1148 | srel >>= 1; | |
1149 | ||
1150 | /* Check for an overflow. */ | |
1151 | if (srel < -512 || srel > 511) | |
13761a11 NC |
1152 | { |
1153 | if (info->disable_target_specific_optimizations < 0) | |
1154 | { | |
1155 | static bfd_boolean warned = FALSE; | |
1156 | if (! warned) | |
1157 | { | |
1158 | info->callbacks->warning | |
1159 | (info, | |
38f14ab8 | 1160 | _("try enabling relaxation to avoid relocation truncations"), |
13761a11 NC |
1161 | NULL, input_bfd, input_section, relocation); |
1162 | warned = TRUE; | |
1163 | } | |
1164 | } | |
1165 | return bfd_reloc_overflow; | |
1166 | } | |
1b786873 | 1167 | |
2469cfa2 NC |
1168 | x = bfd_get_16 (input_bfd, contents); |
1169 | x = (x & 0xfc00) | (srel & 0x3ff); | |
1170 | bfd_put_16 (input_bfd, x, contents); | |
1171 | break; | |
1172 | ||
b18c562e NC |
1173 | case R_MSP430_2X_PCREL: |
1174 | contents += rel->r_offset; | |
1175 | srel = (bfd_signed_vma) relocation; | |
1176 | srel += rel->r_addend; | |
1177 | srel -= rel->r_offset; | |
1178 | srel -= 2; /* Branch instructions add 2 to the PC... */ | |
1179 | srel -= (input_section->output_section->vma + | |
1180 | input_section->output_offset); | |
1181 | ||
1182 | if (srel & 1) | |
1183 | return bfd_reloc_outofrange; | |
1184 | ||
1185 | /* MSP430 addresses commands as words. */ | |
1186 | srel >>= 1; | |
1187 | ||
1188 | /* Check for an overflow. */ | |
1189 | if (srel < -512 || srel > 511) | |
1190 | return bfd_reloc_overflow; | |
1191 | ||
1192 | x = bfd_get_16 (input_bfd, contents); | |
1193 | x = (x & 0xfc00) | (srel & 0x3ff); | |
1194 | bfd_put_16 (input_bfd, x, contents); | |
1195 | /* Handle second jump instruction. */ | |
1196 | x = bfd_get_16 (input_bfd, contents - 2); | |
1197 | srel += 1; | |
1198 | x = (x & 0xfc00) | (srel & 0x3ff); | |
1199 | bfd_put_16 (input_bfd, x, contents - 2); | |
1200 | break; | |
1201 | ||
b18c562e | 1202 | case R_MSP430_RL_PCREL: |
77bf820f | 1203 | case R_MSP430_16_PCREL: |
2469cfa2 NC |
1204 | contents += rel->r_offset; |
1205 | srel = (bfd_signed_vma) relocation; | |
1206 | srel += rel->r_addend; | |
1207 | srel -= rel->r_offset; | |
1208 | /* Only branch instructions add 2 to the PC... */ | |
1209 | srel -= (input_section->output_section->vma + | |
1210 | input_section->output_offset); | |
1211 | ||
1212 | if (srel & 1) | |
1213 | return bfd_reloc_outofrange; | |
1214 | ||
1215 | bfd_put_16 (input_bfd, srel & 0xffff, contents); | |
1216 | break; | |
1217 | ||
1218 | case R_MSP430_16_PCREL_BYTE: | |
1219 | contents += rel->r_offset; | |
1220 | srel = (bfd_signed_vma) relocation; | |
1221 | srel += rel->r_addend; | |
1222 | srel -= rel->r_offset; | |
1223 | /* Only branch instructions add 2 to the PC... */ | |
1224 | srel -= (input_section->output_section->vma + | |
1225 | input_section->output_offset); | |
1226 | ||
1227 | bfd_put_16 (input_bfd, srel & 0xffff, contents); | |
1228 | break; | |
1229 | ||
1230 | case R_MSP430_16_BYTE: | |
1231 | contents += rel->r_offset; | |
1232 | srel = (bfd_signed_vma) relocation; | |
1233 | srel += rel->r_addend; | |
1234 | bfd_put_16 (input_bfd, srel & 0xffff, contents); | |
1235 | break; | |
1236 | ||
1237 | case R_MSP430_16: | |
1238 | contents += rel->r_offset; | |
1239 | srel = (bfd_signed_vma) relocation; | |
1240 | srel += rel->r_addend; | |
1241 | ||
1242 | if (srel & 1) | |
1243 | return bfd_reloc_notsupported; | |
1244 | ||
1245 | bfd_put_16 (input_bfd, srel & 0xffff, contents); | |
1246 | break; | |
1247 | ||
13761a11 NC |
1248 | case R_MSP430_8: |
1249 | contents += rel->r_offset; | |
1250 | srel = (bfd_signed_vma) relocation; | |
1251 | srel += rel->r_addend; | |
1252 | ||
1253 | bfd_put_8 (input_bfd, srel & 0xff, contents); | |
1254 | break; | |
1b786873 | 1255 | |
13761a11 NC |
1256 | case R_MSP430_SYM_DIFF: |
1257 | /* Cache the input section and value. | |
1258 | The offset is unreliable, since relaxation may | |
1259 | have reduced the following reloc's offset. */ | |
1260 | sym_diff_section = input_section; | |
1261 | sym_diff_value = relocation; | |
1262 | return bfd_reloc_ok; | |
1263 | ||
1264 | default: | |
1265 | r = _bfd_final_link_relocate (howto, input_bfd, input_section, | |
1266 | contents, rel->r_offset, | |
1267 | relocation, rel->r_addend); | |
1268 | } | |
2469cfa2 NC |
1269 | |
1270 | return r; | |
1271 | } | |
1272 | ||
1273 | /* Relocate an MSP430 ELF section. */ | |
1274 | ||
1275 | static bfd_boolean | |
b18c562e NC |
1276 | elf32_msp430_relocate_section (bfd * output_bfd ATTRIBUTE_UNUSED, |
1277 | struct bfd_link_info * info, | |
1278 | bfd * input_bfd, | |
1279 | asection * input_section, | |
1280 | bfd_byte * contents, | |
1281 | Elf_Internal_Rela * relocs, | |
1282 | Elf_Internal_Sym * local_syms, | |
1283 | asection ** local_sections) | |
2469cfa2 NC |
1284 | { |
1285 | Elf_Internal_Shdr *symtab_hdr; | |
1286 | struct elf_link_hash_entry **sym_hashes; | |
1287 | Elf_Internal_Rela *rel; | |
1288 | Elf_Internal_Rela *relend; | |
1289 | ||
1290 | symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; | |
1291 | sym_hashes = elf_sym_hashes (input_bfd); | |
1292 | relend = relocs + input_section->reloc_count; | |
1293 | ||
1294 | for (rel = relocs; rel < relend; rel++) | |
1295 | { | |
1296 | reloc_howto_type *howto; | |
1297 | unsigned long r_symndx; | |
1298 | Elf_Internal_Sym *sym; | |
1299 | asection *sec; | |
1300 | struct elf_link_hash_entry *h; | |
1301 | bfd_vma relocation; | |
1302 | bfd_reloc_status_type r; | |
1303 | const char *name = NULL; | |
1304 | int r_type; | |
1305 | ||
2469cfa2 NC |
1306 | r_type = ELF32_R_TYPE (rel->r_info); |
1307 | r_symndx = ELF32_R_SYM (rel->r_info); | |
13761a11 NC |
1308 | |
1309 | if (uses_msp430x_relocs (input_bfd)) | |
1310 | howto = elf_msp430x_howto_table + r_type; | |
1311 | else | |
1312 | howto = elf_msp430_howto_table + r_type; | |
1313 | ||
2469cfa2 NC |
1314 | h = NULL; |
1315 | sym = NULL; | |
1316 | sec = NULL; | |
1317 | ||
1318 | if (r_symndx < symtab_hdr->sh_info) | |
1319 | { | |
1320 | sym = local_syms + r_symndx; | |
1321 | sec = local_sections[r_symndx]; | |
8517fae7 | 1322 | relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); |
2469cfa2 NC |
1323 | |
1324 | name = bfd_elf_string_from_elf_section | |
1325 | (input_bfd, symtab_hdr->sh_link, sym->st_name); | |
fd361982 | 1326 | name = name == NULL || *name == 0 ? bfd_section_name (sec) : name; |
2469cfa2 NC |
1327 | } |
1328 | else | |
1329 | { | |
62d887d4 | 1330 | bfd_boolean unresolved_reloc, warned, ignored; |
2469cfa2 | 1331 | |
b2a8e766 AM |
1332 | RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, |
1333 | r_symndx, symtab_hdr, sym_hashes, | |
1334 | h, sec, relocation, | |
62d887d4 | 1335 | unresolved_reloc, warned, ignored); |
13761a11 | 1336 | name = h->root.root.string; |
2469cfa2 NC |
1337 | } |
1338 | ||
dbaa2011 | 1339 | if (sec != NULL && discarded_section (sec)) |
e4067dbb | 1340 | RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section, |
545fd46b | 1341 | rel, 1, relend, howto, 0, contents); |
ab96bf03 | 1342 | |
0e1862bb | 1343 | if (bfd_link_relocatable (info)) |
ab96bf03 AM |
1344 | continue; |
1345 | ||
2469cfa2 | 1346 | r = msp430_final_link_relocate (howto, input_bfd, input_section, |
13761a11 | 1347 | contents, rel, relocation, info); |
2469cfa2 NC |
1348 | |
1349 | if (r != bfd_reloc_ok) | |
1350 | { | |
1351 | const char *msg = (const char *) NULL; | |
1352 | ||
1353 | switch (r) | |
1354 | { | |
1355 | case bfd_reloc_overflow: | |
1a72702b | 1356 | (*info->callbacks->reloc_overflow) |
13761a11 | 1357 | (info, (h ? &h->root : NULL), name, howto->name, |
1a72702b | 1358 | (bfd_vma) 0, input_bfd, input_section, rel->r_offset); |
2469cfa2 NC |
1359 | break; |
1360 | ||
1361 | case bfd_reloc_undefined: | |
1a72702b AM |
1362 | (*info->callbacks->undefined_symbol) |
1363 | (info, name, input_bfd, input_section, rel->r_offset, TRUE); | |
2469cfa2 NC |
1364 | break; |
1365 | ||
1366 | case bfd_reloc_outofrange: | |
13761a11 | 1367 | msg = _("internal error: branch/jump to an odd address detected"); |
2469cfa2 NC |
1368 | break; |
1369 | ||
1370 | case bfd_reloc_notsupported: | |
1371 | msg = _("internal error: unsupported relocation error"); | |
1372 | break; | |
1373 | ||
1374 | case bfd_reloc_dangerous: | |
1375 | msg = _("internal error: dangerous relocation"); | |
1376 | break; | |
1377 | ||
1378 | default: | |
1379 | msg = _("internal error: unknown error"); | |
1380 | break; | |
1381 | } | |
1382 | ||
1383 | if (msg) | |
1a72702b AM |
1384 | (*info->callbacks->warning) (info, msg, name, input_bfd, |
1385 | input_section, rel->r_offset); | |
2469cfa2 NC |
1386 | } |
1387 | ||
1388 | } | |
1389 | ||
1390 | return TRUE; | |
1391 | } | |
1392 | ||
1393 | /* The final processing done just before writing out a MSP430 ELF object | |
1394 | file. This gets the MSP430 architecture right based on the machine | |
1395 | number. */ | |
1396 | ||
cc364be6 AM |
1397 | static bfd_boolean |
1398 | bfd_elf_msp430_final_write_processing (bfd *abfd) | |
2469cfa2 NC |
1399 | { |
1400 | unsigned long val; | |
1401 | ||
1402 | switch (bfd_get_mach (abfd)) | |
1403 | { | |
1404 | default: | |
13761a11 NC |
1405 | case bfd_mach_msp110: val = E_MSP430_MACH_MSP430x11x1; break; |
1406 | case bfd_mach_msp11: val = E_MSP430_MACH_MSP430x11; break; | |
1407 | case bfd_mach_msp12: val = E_MSP430_MACH_MSP430x12; break; | |
1408 | case bfd_mach_msp13: val = E_MSP430_MACH_MSP430x13; break; | |
1409 | case bfd_mach_msp14: val = E_MSP430_MACH_MSP430x14; break; | |
1410 | case bfd_mach_msp15: val = E_MSP430_MACH_MSP430x15; break; | |
1411 | case bfd_mach_msp16: val = E_MSP430_MACH_MSP430x16; break; | |
1412 | case bfd_mach_msp31: val = E_MSP430_MACH_MSP430x31; break; | |
1413 | case bfd_mach_msp32: val = E_MSP430_MACH_MSP430x32; break; | |
1414 | case bfd_mach_msp33: val = E_MSP430_MACH_MSP430x33; break; | |
1415 | case bfd_mach_msp41: val = E_MSP430_MACH_MSP430x41; break; | |
1416 | case bfd_mach_msp42: val = E_MSP430_MACH_MSP430x42; break; | |
1417 | case bfd_mach_msp43: val = E_MSP430_MACH_MSP430x43; break; | |
1418 | case bfd_mach_msp44: val = E_MSP430_MACH_MSP430x44; break; | |
1419 | case bfd_mach_msp20: val = E_MSP430_MACH_MSP430x20; break; | |
1420 | case bfd_mach_msp22: val = E_MSP430_MACH_MSP430x22; break; | |
1421 | case bfd_mach_msp23: val = E_MSP430_MACH_MSP430x23; break; | |
1422 | case bfd_mach_msp24: val = E_MSP430_MACH_MSP430x24; break; | |
1423 | case bfd_mach_msp26: val = E_MSP430_MACH_MSP430x26; break; | |
1424 | case bfd_mach_msp46: val = E_MSP430_MACH_MSP430x46; break; | |
1425 | case bfd_mach_msp47: val = E_MSP430_MACH_MSP430x47; break; | |
1426 | case bfd_mach_msp54: val = E_MSP430_MACH_MSP430x54; break; | |
1427 | case bfd_mach_msp430x: val = E_MSP430_MACH_MSP430X; break; | |
2469cfa2 NC |
1428 | } |
1429 | ||
1430 | elf_elfheader (abfd)->e_machine = EM_MSP430; | |
1431 | elf_elfheader (abfd)->e_flags &= ~EF_MSP430_MACH; | |
1432 | elf_elfheader (abfd)->e_flags |= val; | |
cc364be6 | 1433 | return _bfd_elf_final_write_processing (abfd); |
2469cfa2 NC |
1434 | } |
1435 | ||
1436 | /* Set the right machine number. */ | |
1437 | ||
1438 | static bfd_boolean | |
b18c562e | 1439 | elf32_msp430_object_p (bfd * abfd) |
2469cfa2 NC |
1440 | { |
1441 | int e_set = bfd_mach_msp14; | |
1442 | ||
1443 | if (elf_elfheader (abfd)->e_machine == EM_MSP430 | |
1444 | || elf_elfheader (abfd)->e_machine == EM_MSP430_OLD) | |
1445 | { | |
1446 | int e_mach = elf_elfheader (abfd)->e_flags & EF_MSP430_MACH; | |
1447 | ||
1448 | switch (e_mach) | |
1449 | { | |
1450 | default: | |
13761a11 NC |
1451 | case E_MSP430_MACH_MSP430x11: e_set = bfd_mach_msp11; break; |
1452 | case E_MSP430_MACH_MSP430x11x1: e_set = bfd_mach_msp110; break; | |
1453 | case E_MSP430_MACH_MSP430x12: e_set = bfd_mach_msp12; break; | |
1454 | case E_MSP430_MACH_MSP430x13: e_set = bfd_mach_msp13; break; | |
1455 | case E_MSP430_MACH_MSP430x14: e_set = bfd_mach_msp14; break; | |
1456 | case E_MSP430_MACH_MSP430x15: e_set = bfd_mach_msp15; break; | |
1457 | case E_MSP430_MACH_MSP430x16: e_set = bfd_mach_msp16; break; | |
1458 | case E_MSP430_MACH_MSP430x31: e_set = bfd_mach_msp31; break; | |
1459 | case E_MSP430_MACH_MSP430x32: e_set = bfd_mach_msp32; break; | |
1460 | case E_MSP430_MACH_MSP430x33: e_set = bfd_mach_msp33; break; | |
1461 | case E_MSP430_MACH_MSP430x41: e_set = bfd_mach_msp41; break; | |
1462 | case E_MSP430_MACH_MSP430x42: e_set = bfd_mach_msp42; break; | |
1463 | case E_MSP430_MACH_MSP430x43: e_set = bfd_mach_msp43; break; | |
1464 | case E_MSP430_MACH_MSP430x44: e_set = bfd_mach_msp44; break; | |
1465 | case E_MSP430_MACH_MSP430x20: e_set = bfd_mach_msp20; break; | |
1466 | case E_MSP430_MACH_MSP430x22: e_set = bfd_mach_msp22; break; | |
1467 | case E_MSP430_MACH_MSP430x23: e_set = bfd_mach_msp23; break; | |
1468 | case E_MSP430_MACH_MSP430x24: e_set = bfd_mach_msp24; break; | |
1469 | case E_MSP430_MACH_MSP430x26: e_set = bfd_mach_msp26; break; | |
1470 | case E_MSP430_MACH_MSP430x46: e_set = bfd_mach_msp46; break; | |
1471 | case E_MSP430_MACH_MSP430x47: e_set = bfd_mach_msp47; break; | |
1472 | case E_MSP430_MACH_MSP430x54: e_set = bfd_mach_msp54; break; | |
1473 | case E_MSP430_MACH_MSP430X: e_set = bfd_mach_msp430x; break; | |
2469cfa2 NC |
1474 | } |
1475 | } | |
1b786873 | 1476 | |
2469cfa2 NC |
1477 | return bfd_default_set_arch_mach (abfd, bfd_arch_msp430, e_set); |
1478 | } | |
1479 | ||
b18c562e NC |
1480 | /* These functions handle relaxing for the msp430. |
1481 | Relaxation required only in two cases: | |
1482 | - Bad hand coding like jumps from one section to another or | |
1483 | from file to file. | |
77bf820f | 1484 | - Sibling calls. This will affect only 'jump label' polymorph. Without |
b18c562e NC |
1485 | relaxing this enlarges code by 2 bytes. Sibcalls implemented but |
1486 | do not work in gcc's port by the reason I do not know. | |
13761a11 NC |
1487 | - To convert out of range conditional jump instructions (found inside |
1488 | a function) into inverted jumps over an unconditional branch instruction. | |
b18c562e NC |
1489 | Anyway, if a relaxation required, user should pass -relax option to the |
1490 | linker. | |
1491 | ||
1492 | There are quite a few relaxing opportunities available on the msp430: | |
1493 | ||
1494 | ================================================================ | |
1495 | ||
1496 | 1. 3 words -> 1 word | |
1497 | ||
07d6d2b8 AM |
1498 | eq == jeq label jne +4; br lab |
1499 | ne != jne label jeq +4; br lab | |
1500 | lt < jl label jge +4; br lab | |
1501 | ltu < jlo label lhs +4; br lab | |
1502 | ge >= jge label jl +4; br lab | |
1503 | geu >= jhs label jlo +4; br lab | |
b18c562e NC |
1504 | |
1505 | 2. 4 words -> 1 word | |
1506 | ||
07d6d2b8 | 1507 | ltn < jn jn +2; jmp +4; br lab |
b18c562e NC |
1508 | |
1509 | 3. 4 words -> 2 words | |
1510 | ||
07d6d2b8 AM |
1511 | gt > jeq +2; jge label jeq +6; jl +4; br label |
1512 | gtu > jeq +2; jhs label jeq +6; jlo +4; br label | |
b18c562e NC |
1513 | |
1514 | 4. 4 words -> 2 words and 2 labels | |
1515 | ||
07d6d2b8 AM |
1516 | leu <= jeq label; jlo label jeq +2; jhs +4; br label |
1517 | le <= jeq label; jl label jeq +2; jge +4; br label | |
b18c562e NC |
1518 | ================================================================= |
1519 | ||
1520 | codemap for first cases is (labels masked ): | |
1521 | eq: 0x2002,0x4010,0x0000 -> 0x2400 | |
1522 | ne: 0x2402,0x4010,0x0000 -> 0x2000 | |
1523 | lt: 0x3402,0x4010,0x0000 -> 0x3800 | |
1524 | ltu: 0x2c02,0x4010,0x0000 -> 0x2800 | |
1525 | ge: 0x3802,0x4010,0x0000 -> 0x3400 | |
1526 | geu: 0x2802,0x4010,0x0000 -> 0x2c00 | |
1527 | ||
1528 | second case: | |
1529 | ltn: 0x3001,0x3c02,0x4010,0x0000 -> 0x3000 | |
1530 | ||
1531 | third case: | |
1532 | gt: 0x2403,0x3802,0x4010,0x0000 -> 0x2401,0x3400 | |
1533 | gtu: 0x2403,0x2802,0x4010,0x0000 -> 0x2401,0x2c00 | |
1534 | ||
1535 | fourth case: | |
1536 | leu: 0x2401,0x2c02,0x4010,0x0000 -> 0x2400,0x2800 | |
1537 | le: 0x2401,0x3402,0x4010,0x0000 -> 0x2400,0x3800 | |
1538 | ||
1539 | Unspecified case :) | |
1540 | jump: 0x4010,0x0000 -> 0x3c00. */ | |
1541 | ||
1542 | #define NUMB_RELAX_CODES 12 | |
1543 | static struct rcodes_s | |
1544 | { | |
1545 | int f0, f1; /* From code. */ | |
1546 | int t0, t1; /* To code. */ | |
1547 | int labels; /* Position of labels: 1 - one label at first | |
1548 | word, 2 - one at second word, 3 - two | |
1549 | labels at both. */ | |
1550 | int cdx; /* Words to match. */ | |
1551 | int bs; /* Shrink bytes. */ | |
1552 | int off; /* Offset from old label for new code. */ | |
1553 | int ncl; /* New code length. */ | |
1554 | } rcode[] = | |
07d6d2b8 | 1555 | {/* lab,cdx,bs,off,ncl */ |
b18c562e NC |
1556 | { 0x0000, 0x0000, 0x3c00, 0x0000, 1, 0, 2, 2, 2}, /* jump */ |
1557 | { 0x0000, 0x2002, 0x2400, 0x0000, 1, 1, 4, 4, 2}, /* eq */ | |
1558 | { 0x0000, 0x2402, 0x2000, 0x0000, 1, 1, 4, 4, 2}, /* ne */ | |
1559 | { 0x0000, 0x3402, 0x3800, 0x0000, 1, 1, 4, 4, 2}, /* lt */ | |
1560 | { 0x0000, 0x2c02, 0x2800, 0x0000, 1, 1, 4, 4, 2}, /* ltu */ | |
1561 | { 0x0000, 0x3802, 0x3400, 0x0000, 1, 1, 4, 4, 2}, /* ge */ | |
1562 | { 0x0000, 0x2802, 0x2c00, 0x0000, 1, 1, 4, 4, 2}, /* geu */ | |
1563 | { 0x3001, 0x3c02, 0x3000, 0x0000, 1, 2, 6, 6, 2}, /* ltn */ | |
1564 | { 0x2403, 0x3802, 0x2401, 0x3400, 2, 2, 4, 6, 4}, /* gt */ | |
1565 | { 0x2403, 0x2802, 0x2401, 0x2c00, 2, 2, 4, 6, 4}, /* gtu */ | |
1566 | { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* leu , 2 labels */ | |
1567 | { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* le , 2 labels */ | |
07d6d2b8 | 1568 | { 0, 0, 0, 0, 0, 0, 0, 0, 0} |
b18c562e NC |
1569 | }; |
1570 | ||
1571 | /* Return TRUE if a symbol exists at the given address. */ | |
1572 | ||
1573 | static bfd_boolean | |
1574 | msp430_elf_symbol_address_p (bfd * abfd, | |
1575 | asection * sec, | |
1576 | Elf_Internal_Sym * isym, | |
1577 | bfd_vma addr) | |
1578 | { | |
1579 | Elf_Internal_Shdr *symtab_hdr; | |
1580 | unsigned int sec_shndx; | |
1581 | Elf_Internal_Sym *isymend; | |
1582 | struct elf_link_hash_entry **sym_hashes; | |
1583 | struct elf_link_hash_entry **end_hashes; | |
1584 | unsigned int symcount; | |
1585 | ||
1586 | sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec); | |
1587 | ||
1588 | /* Examine all the local symbols. */ | |
1589 | symtab_hdr = &elf_tdata (abfd)->symtab_hdr; | |
1590 | for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++) | |
1591 | if (isym->st_shndx == sec_shndx && isym->st_value == addr) | |
1592 | return TRUE; | |
1593 | ||
1594 | symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym) | |
1595 | - symtab_hdr->sh_info); | |
1596 | sym_hashes = elf_sym_hashes (abfd); | |
1597 | end_hashes = sym_hashes + symcount; | |
1598 | for (; sym_hashes < end_hashes; sym_hashes++) | |
1599 | { | |
1600 | struct elf_link_hash_entry *sym_hash = *sym_hashes; | |
1601 | ||
1602 | if ((sym_hash->root.type == bfd_link_hash_defined | |
1603 | || sym_hash->root.type == bfd_link_hash_defweak) | |
1604 | && sym_hash->root.u.def.section == sec | |
1605 | && sym_hash->root.u.def.value == addr) | |
1606 | return TRUE; | |
1607 | } | |
1608 | ||
1609 | return FALSE; | |
1610 | } | |
1611 | ||
13761a11 NC |
1612 | /* Adjust all local symbols defined as '.section + 0xXXXX' (.section has |
1613 | sec_shndx) referenced from current and other sections. */ | |
1614 | ||
046aeb74 | 1615 | static bfd_boolean |
13761a11 NC |
1616 | msp430_elf_relax_adjust_locals (bfd * abfd, asection * sec, bfd_vma addr, |
1617 | int count, unsigned int sec_shndx, | |
1618 | bfd_vma toaddr) | |
046aeb74 DD |
1619 | { |
1620 | Elf_Internal_Shdr *symtab_hdr; | |
1621 | Elf_Internal_Rela *irel; | |
1622 | Elf_Internal_Rela *irelend; | |
1623 | Elf_Internal_Sym *isym; | |
1624 | ||
1625 | irel = elf_section_data (sec)->relocs; | |
13761a11 NC |
1626 | if (irel == NULL) |
1627 | return TRUE; | |
1628 | ||
046aeb74 DD |
1629 | irelend = irel + sec->reloc_count; |
1630 | symtab_hdr = & elf_tdata (abfd)->symtab_hdr; | |
1631 | isym = (Elf_Internal_Sym *) symtab_hdr->contents; | |
bceec4b9 | 1632 | |
13761a11 | 1633 | for (;irel < irelend; irel++) |
046aeb74 | 1634 | { |
bceec4b9 | 1635 | unsigned int sidx = ELF32_R_SYM(irel->r_info); |
046aeb74 | 1636 | Elf_Internal_Sym *lsym = isym + sidx; |
bceec4b9 | 1637 | |
1ade7175 | 1638 | /* Adjust symbols referenced by .sec+0xXX. */ |
bceec4b9 DD |
1639 | if (irel->r_addend > addr && irel->r_addend < toaddr |
1640 | && sidx < symtab_hdr->sh_info | |
046aeb74 DD |
1641 | && lsym->st_shndx == sec_shndx) |
1642 | irel->r_addend -= count; | |
1643 | } | |
1b786873 | 1644 | |
046aeb74 DD |
1645 | return TRUE; |
1646 | } | |
1647 | ||
b18c562e NC |
1648 | /* Delete some bytes from a section while relaxing. */ |
1649 | ||
1650 | static bfd_boolean | |
1651 | msp430_elf_relax_delete_bytes (bfd * abfd, asection * sec, bfd_vma addr, | |
1652 | int count) | |
1653 | { | |
1654 | Elf_Internal_Shdr *symtab_hdr; | |
1655 | unsigned int sec_shndx; | |
1656 | bfd_byte *contents; | |
1657 | Elf_Internal_Rela *irel; | |
1658 | Elf_Internal_Rela *irelend; | |
b18c562e NC |
1659 | bfd_vma toaddr; |
1660 | Elf_Internal_Sym *isym; | |
1661 | Elf_Internal_Sym *isymend; | |
1662 | struct elf_link_hash_entry **sym_hashes; | |
1663 | struct elf_link_hash_entry **end_hashes; | |
1664 | unsigned int symcount; | |
046aeb74 | 1665 | asection *p; |
b18c562e NC |
1666 | |
1667 | sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec); | |
1668 | ||
1669 | contents = elf_section_data (sec)->this_hdr.contents; | |
1670 | ||
b18c562e | 1671 | toaddr = sec->size; |
d60f5448 JL |
1672 | if (debug_relocs) |
1673 | printf (" deleting %d bytes between 0x%lx to 0x%lx\n", | |
c675ec1e | 1674 | count, (long) addr, (long) toaddr); |
b18c562e NC |
1675 | |
1676 | irel = elf_section_data (sec)->relocs; | |
1677 | irelend = irel + sec->reloc_count; | |
1678 | ||
1679 | /* Actually delete the bytes. */ | |
1680 | memmove (contents + addr, contents + addr + count, | |
1681 | (size_t) (toaddr - addr - count)); | |
1682 | sec->size -= count; | |
1683 | ||
1684 | /* Adjust all the relocs. */ | |
fa9ee72b DD |
1685 | symtab_hdr = & elf_tdata (abfd)->symtab_hdr; |
1686 | isym = (Elf_Internal_Sym *) symtab_hdr->contents; | |
13761a11 | 1687 | for (; irel < irelend; irel++) |
fa9ee72b | 1688 | { |
fa9ee72b DD |
1689 | /* Get the new reloc address. */ |
1690 | if ((irel->r_offset > addr && irel->r_offset < toaddr)) | |
1691 | irel->r_offset -= count; | |
fa9ee72b | 1692 | } |
b18c562e | 1693 | |
046aeb74 | 1694 | for (p = abfd->sections; p != NULL; p = p->next) |
13761a11 | 1695 | msp430_elf_relax_adjust_locals (abfd,p,addr,count,sec_shndx,toaddr); |
1b786873 | 1696 | |
b18c562e NC |
1697 | /* Adjust the local symbols defined in this section. */ |
1698 | symtab_hdr = & elf_tdata (abfd)->symtab_hdr; | |
1699 | isym = (Elf_Internal_Sym *) symtab_hdr->contents; | |
1700 | for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++) | |
0f8f0c57 NC |
1701 | { |
1702 | const char * name; | |
1703 | ||
1704 | name = bfd_elf_string_from_elf_section | |
1705 | (abfd, symtab_hdr->sh_link, isym->st_name); | |
fd361982 | 1706 | name = name == NULL || *name == 0 ? bfd_section_name (sec) : name; |
0f8f0c57 NC |
1707 | |
1708 | if (isym->st_shndx != sec_shndx) | |
1709 | continue; | |
1b786873 | 1710 | |
0f8f0c57 NC |
1711 | if (isym->st_value > addr |
1712 | && (isym->st_value < toaddr | |
1713 | /* We also adjust a symbol at the end of the section if its name is | |
1714 | on the list below. These symbols are used for debug info | |
1715 | generation and they refer to the end of the current section, not | |
1716 | the start of the next section. */ | |
1717 | || (isym->st_value == toaddr | |
1718 | && name != NULL | |
1719 | && (CONST_STRNEQ (name, ".Letext") | |
1720 | || CONST_STRNEQ (name, ".LFE"))))) | |
1721 | { | |
d60f5448 JL |
1722 | if (debug_relocs) |
1723 | printf (" adjusting value of local symbol %s from 0x%lx ", | |
c675ec1e | 1724 | name, (long) isym->st_value); |
0f8f0c57 NC |
1725 | if (isym->st_value < addr + count) |
1726 | isym->st_value = addr; | |
1727 | else | |
1728 | isym->st_value -= count; | |
d60f5448 | 1729 | if (debug_relocs) |
c675ec1e | 1730 | printf ("to 0x%lx\n", (long) isym->st_value); |
0f8f0c57 NC |
1731 | } |
1732 | /* Adjust the function symbol's size as well. */ | |
1733 | else if (ELF_ST_TYPE (isym->st_info) == STT_FUNC | |
1734 | && isym->st_value + isym->st_size > addr | |
1735 | && isym->st_value + isym->st_size < toaddr) | |
1736 | isym->st_size -= count; | |
1737 | } | |
b18c562e NC |
1738 | |
1739 | /* Now adjust the global symbols defined in this section. */ | |
1740 | symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym) | |
1741 | - symtab_hdr->sh_info); | |
1742 | sym_hashes = elf_sym_hashes (abfd); | |
1743 | end_hashes = sym_hashes + symcount; | |
1744 | for (; sym_hashes < end_hashes; sym_hashes++) | |
1745 | { | |
1746 | struct elf_link_hash_entry *sym_hash = *sym_hashes; | |
1747 | ||
1748 | if ((sym_hash->root.type == bfd_link_hash_defined | |
1749 | || sym_hash->root.type == bfd_link_hash_defweak) | |
1750 | && sym_hash->root.u.def.section == sec | |
1751 | && sym_hash->root.u.def.value > addr | |
1752 | && sym_hash->root.u.def.value < toaddr) | |
0f8f0c57 NC |
1753 | { |
1754 | if (sym_hash->root.u.def.value < addr + count) | |
1755 | sym_hash->root.u.def.value = addr; | |
1756 | else | |
1757 | sym_hash->root.u.def.value -= count; | |
1758 | } | |
1759 | /* Adjust the function symbol's size as well. */ | |
1760 | else if (sym_hash->root.type == bfd_link_hash_defined | |
1761 | && sym_hash->root.u.def.section == sec | |
1762 | && sym_hash->type == STT_FUNC | |
1763 | && sym_hash->root.u.def.value + sym_hash->size > addr | |
1764 | && sym_hash->root.u.def.value + sym_hash->size < toaddr) | |
1765 | sym_hash->size -= count; | |
b18c562e NC |
1766 | } |
1767 | ||
1768 | return TRUE; | |
1769 | } | |
1770 | ||
8d6cb116 | 1771 | /* Insert one or two words into a section whilst relaxing. */ |
13761a11 NC |
1772 | |
1773 | static bfd_byte * | |
8d6cb116 JL |
1774 | msp430_elf_relax_add_words (bfd * abfd, asection * sec, bfd_vma addr, |
1775 | int num_words, int word1, int word2) | |
13761a11 NC |
1776 | { |
1777 | Elf_Internal_Shdr *symtab_hdr; | |
1778 | unsigned int sec_shndx; | |
1779 | bfd_byte *contents; | |
1780 | Elf_Internal_Rela *irel; | |
1781 | Elf_Internal_Rela *irelend; | |
1782 | Elf_Internal_Sym *isym; | |
1783 | Elf_Internal_Sym *isymend; | |
1784 | struct elf_link_hash_entry **sym_hashes; | |
1785 | struct elf_link_hash_entry **end_hashes; | |
1786 | unsigned int symcount; | |
1787 | bfd_vma sec_end; | |
1788 | asection *p; | |
d60f5448 | 1789 | if (debug_relocs) |
8d6cb116 | 1790 | printf (" adding %d words at 0x%lx\n", num_words, |
c675ec1e | 1791 | (long) (sec->output_section->vma + sec->output_offset + addr)); |
13761a11 NC |
1792 | |
1793 | contents = elf_section_data (sec)->this_hdr.contents; | |
1794 | sec_end = sec->size; | |
8d6cb116 | 1795 | int num_bytes = num_words * 2; |
13761a11 NC |
1796 | |
1797 | /* Make space for the new words. */ | |
8d6cb116 JL |
1798 | contents = bfd_realloc (contents, sec_end + num_bytes); |
1799 | memmove (contents + addr + num_bytes, contents + addr, sec_end - addr); | |
13761a11 NC |
1800 | |
1801 | /* Insert the new words. */ | |
1802 | bfd_put_16 (abfd, word1, contents + addr); | |
8d6cb116 JL |
1803 | if (num_words == 2) |
1804 | bfd_put_16 (abfd, word2, contents + addr + 2); | |
13761a11 NC |
1805 | |
1806 | /* Update the section information. */ | |
8d6cb116 | 1807 | sec->size += num_bytes; |
1b786873 | 1808 | elf_section_data (sec)->this_hdr.contents = contents; |
13761a11 NC |
1809 | |
1810 | /* Adjust all the relocs. */ | |
1811 | irel = elf_section_data (sec)->relocs; | |
1812 | irelend = irel + sec->reloc_count; | |
1813 | ||
1814 | for (; irel < irelend; irel++) | |
1815 | if ((irel->r_offset >= addr && irel->r_offset < sec_end)) | |
8d6cb116 | 1816 | irel->r_offset += num_bytes; |
13761a11 NC |
1817 | |
1818 | /* Adjust the local symbols defined in this section. */ | |
1819 | sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec); | |
1820 | for (p = abfd->sections; p != NULL; p = p->next) | |
8d6cb116 | 1821 | msp430_elf_relax_adjust_locals (abfd, p, addr, -num_bytes, |
13761a11 NC |
1822 | sec_shndx, sec_end); |
1823 | ||
1824 | /* Adjust the global symbols affected by the move. */ | |
1825 | symtab_hdr = & elf_tdata (abfd)->symtab_hdr; | |
1826 | isym = (Elf_Internal_Sym *) symtab_hdr->contents; | |
1827 | for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++) | |
1828 | if (isym->st_shndx == sec_shndx | |
1829 | && isym->st_value >= addr && isym->st_value < sec_end) | |
d60f5448 JL |
1830 | { |
1831 | if (debug_relocs) | |
1832 | printf (" adjusting value of local symbol %s from 0x%lx to " | |
1833 | "0x%lx\n", bfd_elf_string_from_elf_section | |
1834 | (abfd, symtab_hdr->sh_link, isym->st_name), | |
c675ec1e | 1835 | (long) isym->st_value, (long)(isym->st_value + num_bytes)); |
8d6cb116 | 1836 | isym->st_value += num_bytes; |
d60f5448 | 1837 | } |
13761a11 NC |
1838 | |
1839 | /* Now adjust the global symbols defined in this section. */ | |
1840 | symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym) | |
1841 | - symtab_hdr->sh_info); | |
1842 | sym_hashes = elf_sym_hashes (abfd); | |
1843 | end_hashes = sym_hashes + symcount; | |
1844 | for (; sym_hashes < end_hashes; sym_hashes++) | |
1845 | { | |
1846 | struct elf_link_hash_entry *sym_hash = *sym_hashes; | |
1847 | ||
1848 | if ((sym_hash->root.type == bfd_link_hash_defined | |
1849 | || sym_hash->root.type == bfd_link_hash_defweak) | |
1850 | && sym_hash->root.u.def.section == sec | |
1851 | && sym_hash->root.u.def.value >= addr | |
1852 | && sym_hash->root.u.def.value < sec_end) | |
8d6cb116 | 1853 | sym_hash->root.u.def.value += num_bytes; |
13761a11 NC |
1854 | } |
1855 | ||
1856 | return contents; | |
1857 | } | |
1b786873 | 1858 | |
b18c562e NC |
1859 | static bfd_boolean |
1860 | msp430_elf_relax_section (bfd * abfd, asection * sec, | |
1861 | struct bfd_link_info * link_info, | |
1862 | bfd_boolean * again) | |
1863 | { | |
1864 | Elf_Internal_Shdr * symtab_hdr; | |
1865 | Elf_Internal_Rela * internal_relocs; | |
1866 | Elf_Internal_Rela * irel; | |
1867 | Elf_Internal_Rela * irelend; | |
07d6d2b8 | 1868 | bfd_byte * contents = NULL; |
b18c562e NC |
1869 | Elf_Internal_Sym * isymbuf = NULL; |
1870 | ||
1871 | /* Assume nothing changes. */ | |
1872 | *again = FALSE; | |
1873 | ||
1874 | /* We don't have to do anything for a relocatable link, if | |
1875 | this section does not have relocs, or if this is not a | |
1876 | code section. */ | |
0e1862bb | 1877 | if (bfd_link_relocatable (link_info) |
13761a11 NC |
1878 | || (sec->flags & SEC_RELOC) == 0 |
1879 | || sec->reloc_count == 0 || (sec->flags & SEC_CODE) == 0) | |
b18c562e NC |
1880 | return TRUE; |
1881 | ||
d60f5448 JL |
1882 | if (debug_relocs) |
1883 | printf ("Relaxing %s (%p), output_offset: 0x%lx sec size: 0x%lx\n", | |
c675ec1e | 1884 | sec->name, sec, (long) sec->output_offset, (long) sec->size); |
d60f5448 | 1885 | |
b18c562e NC |
1886 | symtab_hdr = & elf_tdata (abfd)->symtab_hdr; |
1887 | ||
1888 | /* Get a copy of the native relocations. */ | |
1889 | internal_relocs = | |
1890 | _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory); | |
1891 | if (internal_relocs == NULL) | |
1892 | goto error_return; | |
1893 | ||
1894 | /* Walk through them looking for relaxing opportunities. */ | |
1895 | irelend = internal_relocs + sec->reloc_count; | |
13761a11 | 1896 | |
d60f5448 JL |
1897 | if (debug_relocs) |
1898 | printf (" trying code size growing relocs\n"); | |
13761a11 | 1899 | /* Do code size growing relocs first. */ |
b18c562e NC |
1900 | for (irel = internal_relocs; irel < irelend; irel++) |
1901 | { | |
1902 | bfd_vma symval; | |
1903 | ||
1904 | /* If this isn't something that can be relaxed, then ignore | |
07d6d2b8 | 1905 | this reloc. */ |
13761a11 | 1906 | if (uses_msp430x_relocs (abfd) |
07d6d2b8 | 1907 | && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430X_10_PCREL) |
13761a11 NC |
1908 | ; |
1909 | else if (! uses_msp430x_relocs (abfd) | |
07d6d2b8 | 1910 | && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_10_PCREL) |
13761a11 NC |
1911 | ; |
1912 | else | |
b18c562e NC |
1913 | continue; |
1914 | ||
1915 | /* Get the section contents if we haven't done so already. */ | |
1916 | if (contents == NULL) | |
1917 | { | |
1918 | /* Get cached copy if it exists. */ | |
1919 | if (elf_section_data (sec)->this_hdr.contents != NULL) | |
1920 | contents = elf_section_data (sec)->this_hdr.contents; | |
1921 | else if (! bfd_malloc_and_get_section (abfd, sec, &contents)) | |
1922 | goto error_return; | |
1923 | } | |
1924 | ||
1925 | /* Read this BFD's local symbols if we haven't done so already. */ | |
1926 | if (isymbuf == NULL && symtab_hdr->sh_info != 0) | |
1927 | { | |
1928 | isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; | |
1929 | if (isymbuf == NULL) | |
1930 | isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, | |
1931 | symtab_hdr->sh_info, 0, | |
1932 | NULL, NULL, NULL); | |
1933 | if (isymbuf == NULL) | |
1934 | goto error_return; | |
1935 | } | |
1936 | ||
1937 | /* Get the value of the symbol referred to by the reloc. */ | |
1938 | if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info) | |
1939 | { | |
1940 | /* A local symbol. */ | |
1941 | Elf_Internal_Sym *isym; | |
1942 | asection *sym_sec; | |
1943 | ||
1944 | isym = isymbuf + ELF32_R_SYM (irel->r_info); | |
1945 | if (isym->st_shndx == SHN_UNDEF) | |
1946 | sym_sec = bfd_und_section_ptr; | |
1947 | else if (isym->st_shndx == SHN_ABS) | |
1948 | sym_sec = bfd_abs_section_ptr; | |
1949 | else if (isym->st_shndx == SHN_COMMON) | |
1950 | sym_sec = bfd_com_section_ptr; | |
1951 | else | |
1952 | sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx); | |
1953 | symval = (isym->st_value | |
1954 | + sym_sec->output_section->vma + sym_sec->output_offset); | |
d60f5448 JL |
1955 | |
1956 | if (debug_relocs) | |
1957 | printf (" processing reloc at 0x%lx for local sym: %s " | |
c675ec1e NC |
1958 | "st_value: 0x%lx adj value: 0x%lx\n", |
1959 | (long) (sec->output_offset + sec->output_section->vma | |
1960 | + irel->r_offset), | |
d60f5448 JL |
1961 | bfd_elf_string_from_elf_section (abfd, symtab_hdr->sh_link, |
1962 | isym->st_name), | |
c675ec1e | 1963 | (long) isym->st_value, (long) symval); |
b18c562e NC |
1964 | } |
1965 | else | |
1966 | { | |
1967 | unsigned long indx; | |
1968 | struct elf_link_hash_entry *h; | |
1969 | ||
1970 | /* An external symbol. */ | |
1971 | indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info; | |
1972 | h = elf_sym_hashes (abfd)[indx]; | |
1973 | BFD_ASSERT (h != NULL); | |
1974 | ||
1975 | if (h->root.type != bfd_link_hash_defined | |
1976 | && h->root.type != bfd_link_hash_defweak) | |
1977 | /* This appears to be a reference to an undefined | |
1978 | symbol. Just ignore it--it will be caught by the | |
1979 | regular reloc processing. */ | |
1980 | continue; | |
1981 | ||
1982 | symval = (h->root.u.def.value | |
1983 | + h->root.u.def.section->output_section->vma | |
1984 | + h->root.u.def.section->output_offset); | |
d60f5448 JL |
1985 | if (debug_relocs) |
1986 | printf (" processing reloc at 0x%lx for global sym: %s " | |
c675ec1e NC |
1987 | "st_value: 0x%lx adj value: 0x%lx\n", |
1988 | (long) (sec->output_offset + sec->output_section->vma | |
1989 | + irel->r_offset), | |
1990 | h->root.root.string, (long) h->root.u.def.value, | |
1991 | (long) symval); | |
b18c562e NC |
1992 | } |
1993 | ||
1994 | /* For simplicity of coding, we are going to modify the section | |
07d6d2b8 AM |
1995 | contents, the section relocs, and the BFD symbol table. We |
1996 | must tell the rest of the code not to free up this | |
1997 | information. It would be possible to instead create a table | |
1998 | of changes which have to be made, as is done in coff-mips.c; | |
1999 | that would be more work, but would require less memory when | |
2000 | the linker is run. */ | |
b18c562e | 2001 | |
13761a11 NC |
2002 | bfd_signed_vma value = symval; |
2003 | int opcode; | |
b18c562e | 2004 | |
13761a11 NC |
2005 | /* Compute the value that will be relocated. */ |
2006 | value += irel->r_addend; | |
2007 | /* Convert to PC relative. */ | |
2008 | value -= (sec->output_section->vma + sec->output_offset); | |
2009 | value -= irel->r_offset; | |
2010 | value -= 2; | |
d60f5448 | 2011 | |
13761a11 NC |
2012 | /* Scale. */ |
2013 | value >>= 1; | |
b18c562e | 2014 | |
13761a11 NC |
2015 | /* If it is in range then no modifications are needed. */ |
2016 | if (value >= -512 && value <= 511) | |
2017 | continue; | |
b18c562e | 2018 | |
13761a11 NC |
2019 | /* Get the opcode. */ |
2020 | opcode = bfd_get_16 (abfd, contents + irel->r_offset); | |
1b786873 | 2021 | |
13761a11 | 2022 | /* Compute the new opcode. We are going to convert: |
8d6cb116 JL |
2023 | JMP label |
2024 | into: | |
2025 | BR[A] label | |
2026 | or | |
13761a11 | 2027 | J<cond> label |
8d6cb116 | 2028 | into: |
13761a11 NC |
2029 | J<inv-cond> 1f |
2030 | BR[A] #label | |
07d6d2b8 | 2031 | 1: */ |
13761a11 NC |
2032 | switch (opcode & 0xfc00) |
2033 | { | |
1b786873 | 2034 | case 0x3800: opcode = 0x3402; break; /* Jl -> Jge +2 */ |
13761a11 NC |
2035 | case 0x3400: opcode = 0x3802; break; /* Jge -> Jl +2 */ |
2036 | case 0x2c00: opcode = 0x2802; break; /* Jhs -> Jlo +2 */ | |
2037 | case 0x2800: opcode = 0x2c02; break; /* Jlo -> Jhs +2 */ | |
2038 | case 0x2400: opcode = 0x2002; break; /* Jeq -> Jne +2 */ | |
2039 | case 0x2000: opcode = 0x2402; break; /* jne -> Jeq +2 */ | |
2040 | case 0x3000: /* jn */ | |
2041 | /* There is no direct inverse of the Jn insn. | |
2042 | FIXME: we could do this as: | |
07d6d2b8 AM |
2043 | Jn 1f |
2044 | br 2f | |
13761a11 | 2045 | 1: br label |
07d6d2b8 | 2046 | 2: */ |
13761a11 | 2047 | continue; |
8d6cb116 JL |
2048 | case 0x3c00: |
2049 | if (uses_msp430x_relocs (abfd)) | |
2050 | opcode = 0x0080; /* JMP -> BRA */ | |
2051 | else | |
2052 | opcode = 0x4030; /* JMP -> BR */ | |
2053 | break; | |
13761a11 | 2054 | default: |
8d6cb116 | 2055 | /* Unhandled branch instruction. */ |
13761a11 | 2056 | /* fprintf (stderr, "unrecog: %x\n", opcode); */ |
2d071cfc | 2057 | continue; |
13761a11 | 2058 | } |
b18c562e | 2059 | |
13761a11 NC |
2060 | /* Note that we've changed the relocs, section contents, etc. */ |
2061 | elf_section_data (sec)->relocs = internal_relocs; | |
2062 | elf_section_data (sec)->this_hdr.contents = contents; | |
2063 | symtab_hdr->contents = (unsigned char *) isymbuf; | |
b18c562e | 2064 | |
13761a11 NC |
2065 | /* Install the new opcode. */ |
2066 | bfd_put_16 (abfd, opcode, contents + irel->r_offset); | |
b18c562e | 2067 | |
13761a11 NC |
2068 | /* Insert the new branch instruction. */ |
2069 | if (uses_msp430x_relocs (abfd)) | |
2070 | { | |
d60f5448 JL |
2071 | if (debug_relocs) |
2072 | printf (" R_MSP430X_10_PCREL -> R_MSP430X_ABS20_ADR_SRC " | |
2073 | "(growing with new opcode 0x%x)\n", opcode); | |
2074 | ||
8d6cb116 JL |
2075 | /* Insert an absolute branch (aka MOVA) instruction. |
2076 | Note that bits 19:16 of the address are stored in the first word | |
2077 | of the insn, so this is where r_offset will point to. */ | |
2078 | if (opcode == 0x0080) | |
2079 | { | |
2080 | /* If we're inserting a BRA because we are converting from a JMP, | |
2081 | then only add one word for destination address; the BRA opcode | |
2082 | has already been written. */ | |
2083 | contents = msp430_elf_relax_add_words | |
2084 | (abfd, sec, irel->r_offset + 2, 1, 0x0000, 0); | |
2085 | } | |
2086 | else | |
2087 | { | |
2088 | contents = msp430_elf_relax_add_words | |
2089 | (abfd, sec, irel->r_offset + 2, 2, 0x0080, 0x0000); | |
2090 | /* Update the relocation to point to the inserted branch | |
2091 | instruction. Note - we are changing a PC-relative reloc | |
2092 | into an absolute reloc, but this is OK because we have | |
2093 | arranged with the assembler to have the reloc's value be | |
2094 | a (local) symbol, not a section+offset value. */ | |
2095 | irel->r_offset += 2; | |
2096 | } | |
13761a11 | 2097 | |
13761a11 NC |
2098 | irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), |
2099 | R_MSP430X_ABS20_ADR_SRC); | |
2100 | } | |
2101 | else | |
2102 | { | |
d60f5448 JL |
2103 | if (debug_relocs) |
2104 | printf (" R_MSP430_10_PCREL -> R_MSP430_16 " | |
2105 | "(growing with new opcode 0x%x)\n", opcode); | |
8d6cb116 JL |
2106 | if (opcode == 0x4030) |
2107 | { | |
2108 | /* If we're inserting a BR because we are converting from a JMP, | |
2109 | then only add one word for destination address; the BR opcode | |
2110 | has already been written. */ | |
2111 | contents = msp430_elf_relax_add_words | |
2112 | (abfd, sec, irel->r_offset + 2, 1, 0x0000, 0); | |
2113 | irel->r_offset += 2; | |
2114 | } | |
2115 | else | |
2116 | { | |
2117 | contents = msp430_elf_relax_add_words | |
2118 | (abfd, sec, irel->r_offset + 2, 2, 0x4030, 0x0000); | |
2119 | /* See comment above about converting a 10-bit PC-rel | |
2120 | relocation into a 16-bit absolute relocation. */ | |
2121 | irel->r_offset += 4; | |
2122 | } | |
13761a11 NC |
2123 | irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), |
2124 | R_MSP430_16); | |
2125 | } | |
b18c562e | 2126 | |
13761a11 NC |
2127 | /* Growing the section may mean that other |
2128 | conditional branches need to be fixed. */ | |
2129 | *again = TRUE; | |
2130 | } | |
b18c562e | 2131 | |
d60f5448 JL |
2132 | if (debug_relocs) |
2133 | printf (" trying code size shrinking relocs\n"); | |
2134 | ||
13761a11 NC |
2135 | for (irel = internal_relocs; irel < irelend; irel++) |
2136 | { | |
2137 | bfd_vma symval; | |
2138 | ||
2139 | /* Get the section contents if we haven't done so already. */ | |
2140 | if (contents == NULL) | |
2141 | { | |
2142 | /* Get cached copy if it exists. */ | |
2143 | if (elf_section_data (sec)->this_hdr.contents != NULL) | |
2144 | contents = elf_section_data (sec)->this_hdr.contents; | |
2145 | else if (! bfd_malloc_and_get_section (abfd, sec, &contents)) | |
2146 | goto error_return; | |
2147 | } | |
2148 | ||
2149 | /* Read this BFD's local symbols if we haven't done so already. */ | |
2150 | if (isymbuf == NULL && symtab_hdr->sh_info != 0) | |
2151 | { | |
2152 | isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; | |
2153 | if (isymbuf == NULL) | |
2154 | isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, | |
2155 | symtab_hdr->sh_info, 0, | |
2156 | NULL, NULL, NULL); | |
2157 | if (isymbuf == NULL) | |
2158 | goto error_return; | |
2159 | } | |
2160 | ||
2161 | /* Get the value of the symbol referred to by the reloc. */ | |
2162 | if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info) | |
2163 | { | |
2164 | /* A local symbol. */ | |
2165 | Elf_Internal_Sym *isym; | |
2166 | asection *sym_sec; | |
2167 | ||
2168 | isym = isymbuf + ELF32_R_SYM (irel->r_info); | |
2169 | if (isym->st_shndx == SHN_UNDEF) | |
2170 | sym_sec = bfd_und_section_ptr; | |
2171 | else if (isym->st_shndx == SHN_ABS) | |
2172 | sym_sec = bfd_abs_section_ptr; | |
2173 | else if (isym->st_shndx == SHN_COMMON) | |
2174 | sym_sec = bfd_com_section_ptr; | |
2175 | else | |
2176 | sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx); | |
2177 | symval = (isym->st_value | |
2178 | + sym_sec->output_section->vma + sym_sec->output_offset); | |
d60f5448 JL |
2179 | |
2180 | if (debug_relocs) | |
2181 | printf (" processing reloc at 0x%lx for local sym: %s " | |
c675ec1e NC |
2182 | "st_value: 0x%lx adj value: 0x%lx\n", |
2183 | (long) (sec->output_offset + sec->output_section->vma | |
2184 | + irel->r_offset), | |
d60f5448 JL |
2185 | bfd_elf_string_from_elf_section |
2186 | (abfd, symtab_hdr->sh_link, isym->st_name), | |
c675ec1e | 2187 | (long) isym->st_value, (long) symval); |
13761a11 NC |
2188 | } |
2189 | else | |
2190 | { | |
2191 | unsigned long indx; | |
2192 | struct elf_link_hash_entry *h; | |
2193 | ||
2194 | /* An external symbol. */ | |
2195 | indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info; | |
2196 | h = elf_sym_hashes (abfd)[indx]; | |
2197 | BFD_ASSERT (h != NULL); | |
2198 | ||
2199 | if (h->root.type != bfd_link_hash_defined | |
2200 | && h->root.type != bfd_link_hash_defweak) | |
2201 | /* This appears to be a reference to an undefined | |
2202 | symbol. Just ignore it--it will be caught by the | |
2203 | regular reloc processing. */ | |
2204 | continue; | |
2205 | ||
2206 | symval = (h->root.u.def.value | |
2207 | + h->root.u.def.section->output_section->vma | |
2208 | + h->root.u.def.section->output_offset); | |
d60f5448 JL |
2209 | if (debug_relocs) |
2210 | printf (" processing reloc at 0x%lx for global sym: %s " | |
c675ec1e NC |
2211 | "st_value: 0x%lx adj value: 0x%lx\n", (long) |
2212 | (sec->output_offset + sec->output_section->vma | |
2213 | + irel->r_offset), | |
2214 | h->root.root.string, (long) h->root.u.def.value, | |
2215 | (long) symval); | |
13761a11 NC |
2216 | } |
2217 | ||
2218 | /* For simplicity of coding, we are going to modify the section | |
2219 | contents, the section relocs, and the BFD symbol table. We | |
2220 | must tell the rest of the code not to free up this | |
2221 | information. It would be possible to instead create a table | |
2222 | of changes which have to be made, as is done in coff-mips.c; | |
2223 | that would be more work, but would require less memory when | |
2224 | the linker is run. */ | |
2225 | ||
2226 | /* Try to turn a 16bit pc-relative branch into a 10bit pc-relative | |
2227 | branch. */ | |
1b786873 | 2228 | /* Paranoia? paranoia... */ |
23d4663e NC |
2229 | if (! uses_msp430x_relocs (abfd) |
2230 | && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_RL_PCREL) | |
13761a11 NC |
2231 | { |
2232 | bfd_vma value = symval; | |
2233 | ||
2234 | /* Deal with pc-relative gunk. */ | |
2235 | value -= (sec->output_section->vma + sec->output_offset); | |
2236 | value -= irel->r_offset; | |
2237 | value += irel->r_addend; | |
2238 | ||
2239 | /* See if the value will fit in 10 bits, note the high value is | |
2240 | 1016 as the target will be two bytes closer if we are | |
2241 | able to relax. */ | |
2242 | if ((long) value < 1016 && (long) value > -1016) | |
2243 | { | |
2244 | int code0 = 0, code1 = 0, code2 = 0; | |
2245 | int i; | |
2246 | struct rcodes_s *rx; | |
2247 | ||
2248 | /* Get the opcode. */ | |
2249 | if (irel->r_offset >= 6) | |
2250 | code0 = bfd_get_16 (abfd, contents + irel->r_offset - 6); | |
2251 | ||
2252 | if (irel->r_offset >= 4) | |
2253 | code1 = bfd_get_16 (abfd, contents + irel->r_offset - 4); | |
2254 | ||
2255 | code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2); | |
2256 | ||
2257 | if (code2 != 0x4010) | |
2258 | continue; | |
2259 | ||
2260 | /* Check r4 and r3. */ | |
2261 | for (i = NUMB_RELAX_CODES - 1; i >= 0; i--) | |
2262 | { | |
2263 | rx = &rcode[i]; | |
2264 | if (rx->cdx == 2 && rx->f0 == code0 && rx->f1 == code1) | |
2265 | break; | |
2266 | else if (rx->cdx == 1 && rx->f1 == code1) | |
2267 | break; | |
2268 | else if (rx->cdx == 0) /* This is an unconditional jump. */ | |
2269 | break; | |
2270 | } | |
2271 | ||
2272 | /* Check labels: | |
b18c562e | 2273 | .Label0: ; we do not care about this label |
13761a11 | 2274 | jeq +6 |
b18c562e | 2275 | .Label1: ; make sure there is no label here |
13761a11 | 2276 | jl +4 |
b18c562e | 2277 | .Label2: ; make sure there is no label here |
13761a11 NC |
2278 | br .Label_dst |
2279 | ||
2280 | So, if there is .Label1 or .Label2 we cannot relax this code. | |
2281 | This actually should not happen, cause for relaxable | |
2282 | instructions we use RL_PCREL reloc instead of 16_PCREL. | |
2283 | Will change this in the future. */ | |
2284 | ||
2285 | if (rx->cdx > 0 | |
2286 | && msp430_elf_symbol_address_p (abfd, sec, isymbuf, | |
2287 | irel->r_offset - 2)) | |
2288 | continue; | |
2289 | if (rx->cdx > 1 | |
2290 | && msp430_elf_symbol_address_p (abfd, sec, isymbuf, | |
2291 | irel->r_offset - 4)) | |
2292 | continue; | |
2293 | ||
2294 | /* Note that we've changed the relocs, section contents, etc. */ | |
2295 | elf_section_data (sec)->relocs = internal_relocs; | |
2296 | elf_section_data (sec)->this_hdr.contents = contents; | |
2297 | symtab_hdr->contents = (unsigned char *) isymbuf; | |
2298 | ||
d60f5448 JL |
2299 | if (debug_relocs) |
2300 | printf (" R_MSP430_RL_PCREL -> "); | |
13761a11 NC |
2301 | /* Fix the relocation's type. */ |
2302 | if (uses_msp430x_relocs (abfd)) | |
2303 | { | |
2304 | if (rx->labels == 3) /* Handle special cases. */ | |
2305 | irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), | |
2306 | R_MSP430X_2X_PCREL); | |
2307 | else | |
2308 | irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), | |
2309 | R_MSP430X_10_PCREL); | |
2310 | } | |
2311 | else | |
2312 | { | |
2313 | if (rx->labels == 3) /* Handle special cases. */ | |
d60f5448 JL |
2314 | { |
2315 | irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), | |
2316 | R_MSP430_2X_PCREL); | |
2317 | if (debug_relocs) | |
2318 | printf ("R_MSP430_2X_PCREL (shrinking with new opcode" | |
2319 | " 0x%x)\n", rx->t0); | |
2320 | } | |
13761a11 | 2321 | else |
d60f5448 JL |
2322 | { |
2323 | irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), | |
2324 | R_MSP430_10_PCREL); | |
2325 | if (debug_relocs) | |
2326 | printf ("R_MSP430_10_PCREL (shrinking with new opcode" | |
2327 | " 0x%x)\n", rx->t0); | |
2328 | } | |
13761a11 NC |
2329 | } |
2330 | ||
2331 | /* Fix the opcode right way. */ | |
2332 | bfd_put_16 (abfd, rx->t0, contents + irel->r_offset - rx->off); | |
2333 | if (rx->t1) | |
2334 | bfd_put_16 (abfd, rx->t1, | |
2335 | contents + irel->r_offset - rx->off + 2); | |
2336 | ||
2337 | /* Delete bytes. */ | |
2338 | if (!msp430_elf_relax_delete_bytes (abfd, sec, | |
2339 | irel->r_offset - rx->off + | |
2340 | rx->ncl, rx->bs)) | |
2341 | goto error_return; | |
2342 | ||
2343 | /* Handle unconditional jumps. */ | |
2344 | if (rx->cdx == 0) | |
2345 | irel->r_offset -= 2; | |
2346 | ||
2347 | /* That will change things, so, we should relax again. | |
2348 | Note that this is not required, and it may be slow. */ | |
2349 | *again = TRUE; | |
2350 | } | |
2351 | } | |
23d4663e NC |
2352 | |
2353 | /* Try to turn a 16-bit absolute branch into a 10-bit pc-relative | |
2354 | branch. */ | |
133193b8 NC |
2355 | if ((uses_msp430x_relocs (abfd) |
2356 | && ELF32_R_TYPE (irel->r_info) == R_MSP430X_ABS16) | |
2357 | || (! uses_msp430x_relocs (abfd) | |
2358 | && ELF32_R_TYPE (irel->r_info) == R_MSP430_16)) | |
23d4663e NC |
2359 | { |
2360 | bfd_vma value = symval; | |
2361 | ||
2d071cfc | 2362 | value -= (sec->output_section->vma + sec->output_offset); |
23d4663e NC |
2363 | value -= irel->r_offset; |
2364 | value += irel->r_addend; | |
1b786873 | 2365 | |
23d4663e NC |
2366 | /* See if the value will fit in 10 bits, note the high value is |
2367 | 1016 as the target will be two bytes closer if we are | |
2368 | able to relax. */ | |
2369 | if ((long) value < 1016 && (long) value > -1016) | |
2370 | { | |
ac4280da | 2371 | int code1, code2, opcode; |
23d4663e NC |
2372 | |
2373 | /* Get the opcode. */ | |
2374 | code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2); | |
ac4280da | 2375 | if (code2 != 0x4030) /* BR -> JMP */ |
23d4663e NC |
2376 | continue; |
2377 | /* FIXME: check r4 and r3 ? */ | |
2378 | /* FIXME: Handle 0x4010 as well ? */ | |
2379 | ||
2380 | /* Note that we've changed the relocs, section contents, etc. */ | |
2381 | elf_section_data (sec)->relocs = internal_relocs; | |
2382 | elf_section_data (sec)->this_hdr.contents = contents; | |
2383 | symtab_hdr->contents = (unsigned char *) isymbuf; | |
2384 | ||
2385 | /* Fix the relocation's type. */ | |
2386 | if (uses_msp430x_relocs (abfd)) | |
2387 | { | |
2388 | irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), | |
2389 | R_MSP430X_10_PCREL); | |
d60f5448 JL |
2390 | if (debug_relocs) |
2391 | printf (" R_MSP430X_16 -> R_MSP430X_10_PCREL "); | |
23d4663e NC |
2392 | } |
2393 | else | |
2394 | { | |
2395 | irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), | |
2396 | R_MSP430_10_PCREL); | |
d60f5448 JL |
2397 | if (debug_relocs) |
2398 | printf (" R_MSP430_16 -> R_MSP430_10_PCREL "); | |
23d4663e | 2399 | } |
ac4280da JL |
2400 | /* If we're trying to shrink a BR[A] after previously having |
2401 | grown a JMP for this reloc, then we have a sequence like | |
2402 | this: | |
2403 | J<cond> 1f | |
2404 | BR[A] | |
2405 | 1: | |
2406 | The opcode for J<cond> has the target hard-coded as 2 words | |
2407 | ahead of the insn, instead of using a reloc. | |
2408 | This means we cannot rely on any of the helper functions to | |
2409 | update this hard-coded jump destination if we remove the | |
2410 | BR[A] insn, so we must explicitly update it here. | |
2411 | This does mean that we can remove the entire branch | |
2412 | instruction, and invert the conditional jump, saving us 4 | |
2413 | bytes rather than only 2 if we detected this in the normal | |
2414 | way. */ | |
2415 | code1 = bfd_get_16 (abfd, contents + irel->r_offset - 4); | |
2416 | switch (code1) | |
2417 | { | |
2418 | case 0x3802: opcode = 0x3401; break; /* Jl +2 -> Jge +1 */ | |
2419 | case 0x3402: opcode = 0x3801; break; /* Jge +2 -> Jl +1 */ | |
2420 | case 0x2c02: opcode = 0x2801; break; /* Jhs +2 -> Jlo +1 */ | |
2421 | case 0x2802: opcode = 0x2c01; break; /* Jlo +2 -> Jhs +1 */ | |
2422 | case 0x2402: opcode = 0x2001; break; /* Jeq +2 -> Jne +1 */ | |
2423 | case 0x2002: opcode = 0x2401; break; /* jne +2 -> Jeq +1 */ | |
2424 | case 0x3002: /* jn +2 */ | |
2425 | /* FIXME: There is no direct inverse of the Jn insn. */ | |
2426 | continue; | |
2427 | default: | |
2428 | /* The previous opcode does not have a hard-coded jump | |
2429 | that we added when previously relaxing, so relax the | |
2430 | current branch as normal. */ | |
2431 | opcode = 0x3c00; | |
2432 | break; | |
2433 | } | |
d60f5448 | 2434 | if (debug_relocs) |
ac4280da | 2435 | printf ("(shrinking with new opcode 0x%x)\n", opcode); |
23d4663e | 2436 | |
ac4280da JL |
2437 | if (opcode != 0x3c00) |
2438 | { | |
2439 | /* Invert the opcode of the conditional jump. */ | |
2440 | bfd_put_16 (abfd, opcode, contents + irel->r_offset - 4); | |
2441 | irel->r_offset -= 4; | |
2442 | ||
2443 | /* Delete 4 bytes - the full BR insn. */ | |
2444 | if (!msp430_elf_relax_delete_bytes (abfd, sec, | |
2445 | irel->r_offset + 2, 4)) | |
2446 | goto error_return; | |
2447 | } | |
2448 | else | |
2449 | { | |
2450 | /* Fix the opcode right way. */ | |
2451 | bfd_put_16 (abfd, opcode, contents + irel->r_offset - 2); | |
2452 | irel->r_offset -= 2; | |
2453 | ||
2454 | /* Delete bytes. */ | |
2455 | if (!msp430_elf_relax_delete_bytes (abfd, sec, | |
2456 | irel->r_offset + 2, 2)) | |
2457 | goto error_return; | |
2458 | } | |
23d4663e NC |
2459 | |
2460 | /* That will change things, so, we should relax again. | |
2461 | Note that this is not required, and it may be slow. */ | |
2462 | *again = TRUE; | |
2463 | } | |
2464 | } | |
13761a11 | 2465 | } |
b18c562e NC |
2466 | |
2467 | if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf) | |
2468 | { | |
2469 | if (!link_info->keep_memory) | |
2470 | free (isymbuf); | |
2471 | else | |
2472 | { | |
2473 | /* Cache the symbols for elf_link_input_bfd. */ | |
2474 | symtab_hdr->contents = (unsigned char *) isymbuf; | |
2475 | } | |
2476 | } | |
2477 | ||
2478 | if (contents != NULL | |
2479 | && elf_section_data (sec)->this_hdr.contents != contents) | |
2480 | { | |
2481 | if (!link_info->keep_memory) | |
2482 | free (contents); | |
2483 | else | |
2484 | { | |
2485 | /* Cache the section contents for elf_link_input_bfd. */ | |
2486 | elf_section_data (sec)->this_hdr.contents = contents; | |
2487 | } | |
2488 | } | |
2489 | ||
2490 | if (internal_relocs != NULL | |
2491 | && elf_section_data (sec)->relocs != internal_relocs) | |
2492 | free (internal_relocs); | |
2493 | ||
2494 | return TRUE; | |
2495 | ||
dc1e8a47 | 2496 | error_return: |
b18c562e NC |
2497 | if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf) |
2498 | free (isymbuf); | |
2499 | if (contents != NULL | |
2500 | && elf_section_data (sec)->this_hdr.contents != contents) | |
2501 | free (contents); | |
2502 | if (internal_relocs != NULL | |
2503 | && elf_section_data (sec)->relocs != internal_relocs) | |
2504 | free (internal_relocs); | |
2505 | ||
2506 | return FALSE; | |
2507 | } | |
2508 | ||
13761a11 NC |
2509 | /* Handle an MSP430 specific section when reading an object file. |
2510 | This is called when bfd_section_from_shdr finds a section with | |
2511 | an unknown type. */ | |
2512 | ||
2513 | static bfd_boolean | |
2514 | elf32_msp430_section_from_shdr (bfd *abfd, | |
2515 | Elf_Internal_Shdr * hdr, | |
2516 | const char *name, | |
2517 | int shindex) | |
2518 | { | |
2519 | switch (hdr->sh_type) | |
2520 | { | |
2521 | case SHT_MSP430_SEC_FLAGS: | |
2522 | case SHT_MSP430_SYM_ALIASES: | |
2523 | case SHT_MSP430_ATTRIBUTES: | |
2524 | return _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex); | |
2525 | default: | |
2526 | return FALSE; | |
2527 | } | |
2528 | } | |
2529 | ||
2530 | static bfd_boolean | |
2531 | elf32_msp430_obj_attrs_handle_unknown (bfd *abfd, int tag) | |
2532 | { | |
2533 | _bfd_error_handler | |
695344c0 | 2534 | /* xgettext:c-format */ |
38f14ab8 | 2535 | (_("warning: %pB: unknown MSPABI object attribute %d"), |
13761a11 NC |
2536 | abfd, tag); |
2537 | return TRUE; | |
2538 | } | |
2539 | ||
2540 | /* Determine whether an object attribute tag takes an integer, a | |
2541 | string or both. */ | |
2542 | ||
2543 | static int | |
2544 | elf32_msp430_obj_attrs_arg_type (int tag) | |
2545 | { | |
2546 | if (tag == Tag_compatibility) | |
2547 | return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL; | |
2548 | ||
2549 | if (tag < 32) | |
2550 | return ATTR_TYPE_FLAG_INT_VAL; | |
2551 | ||
2552 | return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL; | |
2553 | } | |
2554 | ||
2555 | static inline const char * | |
2556 | isa_type (int isa) | |
2557 | { | |
2558 | switch (isa) | |
2559 | { | |
2560 | case 1: return "MSP430"; | |
2561 | case 2: return "MSP430X"; | |
2562 | default: return "unknown"; | |
2563 | } | |
2564 | } | |
2565 | ||
2566 | static inline const char * | |
2567 | code_model (int model) | |
2568 | { | |
2569 | switch (model) | |
2570 | { | |
2571 | case 1: return "small"; | |
2572 | case 2: return "large"; | |
2573 | default: return "unknown"; | |
2574 | } | |
2575 | } | |
2576 | ||
2577 | static inline const char * | |
2578 | data_model (int model) | |
2579 | { | |
2580 | switch (model) | |
2581 | { | |
2582 | case 1: return "small"; | |
2583 | case 2: return "large"; | |
2584 | case 3: return "restricted large"; | |
2585 | default: return "unknown"; | |
2586 | } | |
2587 | } | |
2588 | ||
c0ea7c52 | 2589 | /* Merge MSPABI and GNU object attributes from IBFD into OBFD. |
13761a11 NC |
2590 | Raise an error if there are conflicting attributes. */ |
2591 | ||
2592 | static bfd_boolean | |
c0ea7c52 | 2593 | elf32_msp430_merge_msp430_attributes (bfd *ibfd, struct bfd_link_info *info) |
13761a11 | 2594 | { |
50e03d47 | 2595 | bfd *obfd = info->output_bfd; |
c0ea7c52 JL |
2596 | obj_attribute *in_msp_attr, *in_gnu_attr; |
2597 | obj_attribute *out_msp_attr, *out_gnu_attr; | |
13761a11 NC |
2598 | bfd_boolean result = TRUE; |
2599 | static bfd * first_input_bfd = NULL; | |
2600 | ||
2601 | /* Skip linker created files. */ | |
2602 | if (ibfd->flags & BFD_LINKER_CREATED) | |
2603 | return TRUE; | |
2604 | ||
ca94519e JL |
2605 | /* LTO can create temporary files for linking which may not have an attribute |
2606 | section. */ | |
2607 | if (ibfd->lto_output | |
2608 | && bfd_get_section_by_name (ibfd, ".MSP430.attributes") == NULL) | |
2609 | return TRUE; | |
2610 | ||
13761a11 NC |
2611 | /* If this is the first real object just copy the attributes. */ |
2612 | if (!elf_known_obj_attributes_proc (obfd)[0].i) | |
2613 | { | |
2614 | _bfd_elf_copy_obj_attributes (ibfd, obfd); | |
2615 | ||
c0ea7c52 | 2616 | out_msp_attr = elf_known_obj_attributes_proc (obfd); |
13761a11 NC |
2617 | |
2618 | /* Use the Tag_null value to indicate that | |
2619 | the attributes have been initialized. */ | |
c0ea7c52 | 2620 | out_msp_attr[0].i = 1; |
13761a11 NC |
2621 | |
2622 | first_input_bfd = ibfd; | |
2623 | return TRUE; | |
2624 | } | |
2625 | ||
c0ea7c52 JL |
2626 | in_msp_attr = elf_known_obj_attributes_proc (ibfd); |
2627 | out_msp_attr = elf_known_obj_attributes_proc (obfd); | |
2628 | in_gnu_attr = elf_known_obj_attributes (ibfd) [OBJ_ATTR_GNU]; | |
2629 | out_gnu_attr = elf_known_obj_attributes (obfd) [OBJ_ATTR_GNU]; | |
13761a11 NC |
2630 | |
2631 | /* The ISAs must be the same. */ | |
c0ea7c52 | 2632 | if (in_msp_attr[OFBA_MSPABI_Tag_ISA].i != out_msp_attr[OFBA_MSPABI_Tag_ISA].i) |
13761a11 NC |
2633 | { |
2634 | _bfd_error_handler | |
695344c0 | 2635 | /* xgettext:c-format */ |
871b3ab2 | 2636 | (_("error: %pB uses %s instructions but %pB uses %s"), |
c0ea7c52 JL |
2637 | ibfd, isa_type (in_msp_attr[OFBA_MSPABI_Tag_ISA].i), |
2638 | first_input_bfd, isa_type (out_msp_attr[OFBA_MSPABI_Tag_ISA].i)); | |
13761a11 NC |
2639 | result = FALSE; |
2640 | } | |
2641 | ||
2642 | /* The code models must be the same. */ | |
c0ea7c52 JL |
2643 | if (in_msp_attr[OFBA_MSPABI_Tag_Code_Model].i |
2644 | != out_msp_attr[OFBA_MSPABI_Tag_Code_Model].i) | |
13761a11 NC |
2645 | { |
2646 | _bfd_error_handler | |
695344c0 | 2647 | /* xgettext:c-format */ |
871b3ab2 | 2648 | (_("error: %pB uses the %s code model whereas %pB uses the %s code model"), |
c0ea7c52 JL |
2649 | ibfd, code_model (in_msp_attr[OFBA_MSPABI_Tag_Code_Model].i), |
2650 | first_input_bfd, | |
2651 | code_model (out_msp_attr[OFBA_MSPABI_Tag_Code_Model].i)); | |
13761a11 NC |
2652 | result = FALSE; |
2653 | } | |
2654 | ||
2655 | /* The large code model is only supported by the MSP430X. */ | |
c0ea7c52 JL |
2656 | if (in_msp_attr[OFBA_MSPABI_Tag_Code_Model].i == 2 |
2657 | && out_msp_attr[OFBA_MSPABI_Tag_ISA].i != 2) | |
13761a11 NC |
2658 | { |
2659 | _bfd_error_handler | |
695344c0 | 2660 | /* xgettext:c-format */ |
871b3ab2 | 2661 | (_("error: %pB uses the large code model but %pB uses MSP430 instructions"), |
13761a11 NC |
2662 | ibfd, first_input_bfd); |
2663 | result = FALSE; | |
2664 | } | |
2665 | ||
2666 | /* The data models must be the same. */ | |
c0ea7c52 JL |
2667 | if (in_msp_attr[OFBA_MSPABI_Tag_Data_Model].i |
2668 | != out_msp_attr[OFBA_MSPABI_Tag_Data_Model].i) | |
13761a11 NC |
2669 | { |
2670 | _bfd_error_handler | |
695344c0 | 2671 | /* xgettext:c-format */ |
871b3ab2 | 2672 | (_("error: %pB uses the %s data model whereas %pB uses the %s data model"), |
c0ea7c52 JL |
2673 | ibfd, data_model (in_msp_attr[OFBA_MSPABI_Tag_Data_Model].i), |
2674 | first_input_bfd, | |
2675 | data_model (out_msp_attr[OFBA_MSPABI_Tag_Data_Model].i)); | |
13761a11 NC |
2676 | result = FALSE; |
2677 | } | |
2678 | ||
2679 | /* The small code model requires the use of the small data model. */ | |
c0ea7c52 JL |
2680 | if (in_msp_attr[OFBA_MSPABI_Tag_Code_Model].i == 1 |
2681 | && out_msp_attr[OFBA_MSPABI_Tag_Data_Model].i != 1) | |
13761a11 NC |
2682 | { |
2683 | _bfd_error_handler | |
695344c0 | 2684 | /* xgettext:c-format */ |
871b3ab2 | 2685 | (_("error: %pB uses the small code model but %pB uses the %s data model"), |
13761a11 | 2686 | ibfd, first_input_bfd, |
c0ea7c52 | 2687 | data_model (out_msp_attr[OFBA_MSPABI_Tag_Data_Model].i)); |
13761a11 NC |
2688 | result = FALSE; |
2689 | } | |
2690 | ||
2691 | /* The large data models are only supported by the MSP430X. */ | |
c0ea7c52 JL |
2692 | if (in_msp_attr[OFBA_MSPABI_Tag_Data_Model].i > 1 |
2693 | && out_msp_attr[OFBA_MSPABI_Tag_ISA].i != 2) | |
13761a11 NC |
2694 | { |
2695 | _bfd_error_handler | |
695344c0 | 2696 | /* xgettext:c-format */ |
871b3ab2 | 2697 | (_("error: %pB uses the %s data model but %pB only uses MSP430 instructions"), |
c0ea7c52 | 2698 | ibfd, data_model (in_msp_attr[OFBA_MSPABI_Tag_Data_Model].i), |
c08bb8dd | 2699 | first_input_bfd); |
13761a11 NC |
2700 | result = FALSE; |
2701 | } | |
1b786873 | 2702 | |
c0ea7c52 JL |
2703 | /* Just ignore the data region unless the large memory model is in use. |
2704 | We have already checked that ibfd and obfd use the same memory model. */ | |
2705 | if ((in_msp_attr[OFBA_MSPABI_Tag_Code_Model].i | |
2706 | == OFBA_MSPABI_Val_Code_Model_LARGE) | |
2707 | && (in_msp_attr[OFBA_MSPABI_Tag_Data_Model].i | |
2708 | == OFBA_MSPABI_Val_Data_Model_LARGE)) | |
2709 | { | |
2710 | /* We cannot allow "lower region only" to be linked with any other | |
2711 | values (i.e. ANY or NONE). | |
2712 | Before this attribute existed, "ANY" region was the default. */ | |
2713 | bfd_boolean ibfd_lower_region_used | |
2714 | = (in_gnu_attr[Tag_GNU_MSP430_Data_Region].i | |
2715 | == Val_GNU_MSP430_Data_Region_Lower); | |
2716 | bfd_boolean obfd_lower_region_used | |
2717 | = (out_gnu_attr[Tag_GNU_MSP430_Data_Region].i | |
2718 | == Val_GNU_MSP430_Data_Region_Lower); | |
2719 | if (ibfd_lower_region_used != obfd_lower_region_used) | |
2720 | { | |
2721 | _bfd_error_handler | |
2722 | (_("error: %pB can use the upper region for data, " | |
2723 | "but %pB assumes data is exclusively in lower memory"), | |
2724 | ibfd_lower_region_used ? obfd : ibfd, | |
2725 | ibfd_lower_region_used ? ibfd : obfd); | |
2726 | result = FALSE; | |
2727 | } | |
2728 | } | |
2729 | ||
13761a11 NC |
2730 | return result; |
2731 | } | |
2732 | ||
2733 | /* Merge backend specific data from an object file to the output | |
2734 | object file when linking. */ | |
2735 | ||
2736 | static bfd_boolean | |
50e03d47 | 2737 | elf32_msp430_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info) |
13761a11 | 2738 | { |
50e03d47 | 2739 | bfd *obfd = info->output_bfd; |
13761a11 NC |
2740 | /* Make sure that the machine number reflects the most |
2741 | advanced version of the MSP architecture required. */ | |
2742 | #define max(a,b) ((a) > (b) ? (a) : (b)) | |
2743 | if (bfd_get_mach (ibfd) != bfd_get_mach (obfd)) | |
2744 | bfd_default_set_arch_mach (obfd, bfd_get_arch (obfd), | |
2745 | max (bfd_get_mach (ibfd), bfd_get_mach (obfd))); | |
2746 | #undef max | |
2747 | ||
c0ea7c52 | 2748 | return elf32_msp430_merge_msp430_attributes (ibfd, info); |
13761a11 NC |
2749 | } |
2750 | ||
13761a11 NC |
2751 | static bfd_boolean |
2752 | msp430_elf_is_target_special_symbol (bfd *abfd, asymbol *sym) | |
2753 | { | |
2754 | return _bfd_elf_is_local_label_name (abfd, sym->name); | |
2755 | } | |
2756 | ||
79559014 NC |
2757 | static bfd_boolean |
2758 | uses_large_model (bfd *abfd) | |
2759 | { | |
2760 | obj_attribute * attr; | |
2761 | ||
2762 | if (abfd->flags & BFD_LINKER_CREATED) | |
2763 | return FALSE; | |
2764 | ||
2765 | attr = elf_known_obj_attributes_proc (abfd); | |
2766 | if (attr == NULL) | |
2767 | return FALSE; | |
2768 | ||
2769 | return attr[OFBA_MSPABI_Tag_Code_Model].i == 2; | |
2770 | } | |
2771 | ||
2772 | static unsigned int | |
76c20d54 AM |
2773 | elf32_msp430_eh_frame_address_size (bfd *abfd, |
2774 | const asection *sec ATTRIBUTE_UNUSED) | |
79559014 NC |
2775 | { |
2776 | return uses_large_model (abfd) ? 4 : 2; | |
2777 | } | |
2778 | ||
13761a11 NC |
2779 | /* This is gross. The MSP430 EABI says that (sec 11.5): |
2780 | ||
2781 | "An implementation may choose to use Rel or Rela | |
2782 | type relocations for other relocations." | |
2783 | ||
2784 | But it also says that: | |
1b786873 | 2785 | |
13761a11 NC |
2786 | "Certain relocations are identified as Rela only. [snip] |
2787 | Where Rela is specified, an implementation must honor | |
2788 | this requirement." | |
2789 | ||
2790 | There is one relocation marked as requiring RELA - R_MSP430_ABS_HI16 - but | |
2791 | to keep things simple we choose to use RELA relocations throughout. The | |
2792 | problem is that the TI compiler generates REL relocations, so we have to | |
2793 | be able to accept those as well. */ | |
2794 | ||
2795 | #define elf_backend_may_use_rel_p 1 | |
2796 | #define elf_backend_may_use_rela_p 1 | |
2797 | #define elf_backend_default_use_rela_p 1 | |
2798 | ||
07d6d2b8 | 2799 | #undef elf_backend_obj_attrs_vendor |
13761a11 | 2800 | #define elf_backend_obj_attrs_vendor "mspabi" |
07d6d2b8 | 2801 | #undef elf_backend_obj_attrs_section |
13761a11 | 2802 | #define elf_backend_obj_attrs_section ".MSP430.attributes" |
07d6d2b8 | 2803 | #undef elf_backend_obj_attrs_section_type |
13761a11 | 2804 | #define elf_backend_obj_attrs_section_type SHT_MSP430_ATTRIBUTES |
07d6d2b8 AM |
2805 | #define elf_backend_section_from_shdr elf32_msp430_section_from_shdr |
2806 | #define elf_backend_obj_attrs_handle_unknown elf32_msp430_obj_attrs_handle_unknown | |
2807 | #undef elf_backend_obj_attrs_arg_type | |
13761a11 | 2808 | #define elf_backend_obj_attrs_arg_type elf32_msp430_obj_attrs_arg_type |
13761a11 | 2809 | #define bfd_elf32_bfd_merge_private_bfd_data elf32_msp430_merge_private_bfd_data |
79559014 | 2810 | #define elf_backend_eh_frame_address_size elf32_msp430_eh_frame_address_size |
2469cfa2 NC |
2811 | |
2812 | #define ELF_ARCH bfd_arch_msp430 | |
2813 | #define ELF_MACHINE_CODE EM_MSP430 | |
2814 | #define ELF_MACHINE_ALT1 EM_MSP430_OLD | |
13761a11 | 2815 | #define ELF_MAXPAGESIZE 4 |
d1036acb | 2816 | #define ELF_OSABI ELFOSABI_STANDALONE |
2469cfa2 | 2817 | |
07d6d2b8 | 2818 | #define TARGET_LITTLE_SYM msp430_elf32_vec |
2469cfa2 NC |
2819 | #define TARGET_LITTLE_NAME "elf32-msp430" |
2820 | ||
07d6d2b8 AM |
2821 | #define elf_info_to_howto msp430_info_to_howto_rela |
2822 | #define elf_info_to_howto_rel NULL | |
2823 | #define elf_backend_relocate_section elf32_msp430_relocate_section | |
2824 | #define elf_backend_check_relocs elf32_msp430_check_relocs | |
2825 | #define elf_backend_can_gc_sections 1 | |
2469cfa2 NC |
2826 | #define elf_backend_final_write_processing bfd_elf_msp430_final_write_processing |
2827 | #define elf_backend_object_p elf32_msp430_object_p | |
b18c562e | 2828 | #define bfd_elf32_bfd_relax_section msp430_elf_relax_section |
13761a11 NC |
2829 | #define bfd_elf32_bfd_is_target_special_symbol msp430_elf_is_target_special_symbol |
2830 | ||
07d6d2b8 | 2831 | #undef elf32_bed |
13761a11 NC |
2832 | #define elf32_bed elf32_msp430_bed |
2833 | ||
2834 | #include "elf32-target.h" | |
2835 | ||
2836 | /* The TI compiler sets the OSABI field to ELFOSABI_NONE. */ | |
07d6d2b8 AM |
2837 | #undef TARGET_LITTLE_SYM |
2838 | #define TARGET_LITTLE_SYM msp430_elf32_ti_vec | |
13761a11 | 2839 | |
07d6d2b8 | 2840 | #undef elf32_bed |
13761a11 NC |
2841 | #define elf32_bed elf32_msp430_ti_bed |
2842 | ||
1b786873 | 2843 | #undef ELF_OSABI |
13761a11 NC |
2844 | #define ELF_OSABI ELFOSABI_NONE |
2845 | ||
2846 | static const struct bfd_elf_special_section msp430_ti_elf_special_sections[] = | |
2847 | { | |
07d6d2b8 | 2848 | /* prefix, prefix_length, suffix_len, type, attributes. */ |
13761a11 NC |
2849 | { STRING_COMMA_LEN (".TI.symbol.alias"), 0, SHT_MSP430_SYM_ALIASES, 0 }, |
2850 | { STRING_COMMA_LEN (".TI.section.flags"), 0, SHT_MSP430_SEC_FLAGS, 0 }, | |
2851 | { STRING_COMMA_LEN ("_TI_build_attrib"), 0, SHT_MSP430_ATTRIBUTES, 0 }, | |
07d6d2b8 | 2852 | { NULL, 0, 0, 0, 0 } |
13761a11 | 2853 | }; |
2469cfa2 | 2854 | |
07d6d2b8 AM |
2855 | #undef elf_backend_special_sections |
2856 | #define elf_backend_special_sections msp430_ti_elf_special_sections | |
b6518b38 | 2857 | |
2469cfa2 | 2858 | #include "elf32-target.h" |