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caed7120 | 1 | /* AArch64-specific support for ELF. |
2571583a | 2 | Copyright (C) 2009-2017 Free Software Foundation, Inc. |
caed7120 YZ |
3 | Contributed by ARM Ltd. |
4 | ||
5 | This file is part of BFD, the Binary File Descriptor library. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; see the file COPYING3. If not, | |
19 | see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "sysdep.h" | |
22 | #include "elfxx-aarch64.h" | |
d0ae9fbd OJ |
23 | #include <stdarg.h> |
24 | #include <string.h> | |
caed7120 YZ |
25 | |
26 | #define MASK(n) ((1u << (n)) - 1) | |
27 | ||
4106101c MS |
28 | /* Sign-extend VALUE, which has the indicated number of BITS. */ |
29 | ||
30 | bfd_signed_vma | |
31 | _bfd_aarch64_sign_extend (bfd_vma value, int bits) | |
32 | { | |
33 | if (value & ((bfd_vma) 1 << (bits - 1))) | |
34 | /* VALUE is negative. */ | |
35 | value |= ((bfd_vma) - 1) << bits; | |
36 | ||
37 | return value; | |
38 | } | |
39 | ||
40 | /* Decode the IMM field of ADRP. */ | |
41 | ||
42 | uint32_t | |
43 | _bfd_aarch64_decode_adrp_imm (uint32_t insn) | |
44 | { | |
45 | return (((insn >> 5) & MASK (19)) << 2) | ((insn >> 29) & MASK (2)); | |
46 | } | |
47 | ||
caed7120 YZ |
48 | /* Reencode the imm field of add immediate. */ |
49 | static inline uint32_t | |
50 | reencode_add_imm (uint32_t insn, uint32_t imm) | |
51 | { | |
52 | return (insn & ~(MASK (12) << 10)) | ((imm & MASK (12)) << 10); | |
53 | } | |
54 | ||
4106101c MS |
55 | /* Reencode the IMM field of ADR. */ |
56 | ||
57 | uint32_t | |
58 | _bfd_aarch64_reencode_adr_imm (uint32_t insn, uint32_t imm) | |
caed7120 YZ |
59 | { |
60 | return (insn & ~((MASK (2) << 29) | (MASK (19) << 5))) | |
61 | | ((imm & MASK (2)) << 29) | ((imm & (MASK (19) << 2)) << 3); | |
62 | } | |
63 | ||
64 | /* Reencode the imm field of ld/st pos immediate. */ | |
65 | static inline uint32_t | |
66 | reencode_ldst_pos_imm (uint32_t insn, uint32_t imm) | |
67 | { | |
68 | return (insn & ~(MASK (12) << 10)) | ((imm & MASK (12)) << 10); | |
69 | } | |
70 | ||
71 | /* Encode the 26-bit offset of unconditional branch. */ | |
72 | static inline uint32_t | |
73 | reencode_branch_ofs_26 (uint32_t insn, uint32_t ofs) | |
74 | { | |
75 | return (insn & ~MASK (26)) | (ofs & MASK (26)); | |
76 | } | |
77 | ||
78 | /* Encode the 19-bit offset of conditional branch and compare & branch. */ | |
79 | static inline uint32_t | |
80 | reencode_cond_branch_ofs_19 (uint32_t insn, uint32_t ofs) | |
81 | { | |
82 | return (insn & ~(MASK (19) << 5)) | ((ofs & MASK (19)) << 5); | |
83 | } | |
84 | ||
85 | /* Decode the 19-bit offset of load literal. */ | |
86 | static inline uint32_t | |
87 | reencode_ld_lit_ofs_19 (uint32_t insn, uint32_t ofs) | |
88 | { | |
89 | return (insn & ~(MASK (19) << 5)) | ((ofs & MASK (19)) << 5); | |
90 | } | |
91 | ||
92 | /* Encode the 14-bit offset of test & branch. */ | |
93 | static inline uint32_t | |
94 | reencode_tst_branch_ofs_14 (uint32_t insn, uint32_t ofs) | |
95 | { | |
96 | return (insn & ~(MASK (14) << 5)) | ((ofs & MASK (14)) << 5); | |
97 | } | |
98 | ||
99 | /* Reencode the imm field of move wide. */ | |
100 | static inline uint32_t | |
101 | reencode_movw_imm (uint32_t insn, uint32_t imm) | |
102 | { | |
103 | return (insn & ~(MASK (16) << 5)) | ((imm & MASK (16)) << 5); | |
104 | } | |
105 | ||
106 | /* Reencode mov[zn] to movz. */ | |
107 | static inline uint32_t | |
108 | reencode_movzn_to_movz (uint32_t opcode) | |
109 | { | |
110 | return opcode | (1 << 30); | |
111 | } | |
112 | ||
113 | /* Reencode mov[zn] to movn. */ | |
114 | static inline uint32_t | |
115 | reencode_movzn_to_movn (uint32_t opcode) | |
116 | { | |
117 | return opcode & ~(1 << 30); | |
118 | } | |
119 | ||
120 | /* Return non-zero if the indicated VALUE has overflowed the maximum | |
121 | range expressible by a unsigned number with the indicated number of | |
122 | BITS. */ | |
123 | ||
124 | static bfd_reloc_status_type | |
125 | aarch64_unsigned_overflow (bfd_vma value, unsigned int bits) | |
126 | { | |
127 | bfd_vma lim; | |
128 | if (bits >= sizeof (bfd_vma) * 8) | |
129 | return bfd_reloc_ok; | |
130 | lim = (bfd_vma) 1 << bits; | |
131 | if (value >= lim) | |
132 | return bfd_reloc_overflow; | |
133 | return bfd_reloc_ok; | |
134 | } | |
135 | ||
136 | /* Return non-zero if the indicated VALUE has overflowed the maximum | |
137 | range expressible by an signed number with the indicated number of | |
138 | BITS. */ | |
139 | ||
140 | static bfd_reloc_status_type | |
141 | aarch64_signed_overflow (bfd_vma value, unsigned int bits) | |
142 | { | |
143 | bfd_signed_vma svalue = (bfd_signed_vma) value; | |
144 | bfd_signed_vma lim; | |
145 | ||
146 | if (bits >= sizeof (bfd_vma) * 8) | |
147 | return bfd_reloc_ok; | |
148 | lim = (bfd_signed_vma) 1 << (bits - 1); | |
149 | if (svalue < -lim || svalue >= lim) | |
150 | return bfd_reloc_overflow; | |
151 | return bfd_reloc_ok; | |
152 | } | |
153 | ||
154 | /* Insert the addend/value into the instruction or data object being | |
155 | relocated. */ | |
156 | bfd_reloc_status_type | |
157 | _bfd_aarch64_elf_put_addend (bfd *abfd, | |
158 | bfd_byte *address, bfd_reloc_code_real_type r_type, | |
159 | reloc_howto_type *howto, bfd_signed_vma addend) | |
160 | { | |
161 | bfd_reloc_status_type status = bfd_reloc_ok; | |
162 | bfd_signed_vma old_addend = addend; | |
163 | bfd_vma contents; | |
164 | int size; | |
165 | ||
166 | size = bfd_get_reloc_size (howto); | |
167 | switch (size) | |
168 | { | |
6346d5ca AM |
169 | case 0: |
170 | return status; | |
caed7120 YZ |
171 | case 2: |
172 | contents = bfd_get_16 (abfd, address); | |
173 | break; | |
174 | case 4: | |
175 | if (howto->src_mask != 0xffffffff) | |
176 | /* Must be 32-bit instruction, always little-endian. */ | |
177 | contents = bfd_getl32 (address); | |
178 | else | |
179 | /* Must be 32-bit data (endianness dependent). */ | |
180 | contents = bfd_get_32 (abfd, address); | |
181 | break; | |
182 | case 8: | |
183 | contents = bfd_get_64 (abfd, address); | |
184 | break; | |
185 | default: | |
186 | abort (); | |
187 | } | |
188 | ||
189 | switch (howto->complain_on_overflow) | |
190 | { | |
191 | case complain_overflow_dont: | |
192 | break; | |
193 | case complain_overflow_signed: | |
194 | status = aarch64_signed_overflow (addend, | |
195 | howto->bitsize + howto->rightshift); | |
196 | break; | |
197 | case complain_overflow_unsigned: | |
198 | status = aarch64_unsigned_overflow (addend, | |
199 | howto->bitsize + howto->rightshift); | |
200 | break; | |
201 | case complain_overflow_bitfield: | |
202 | default: | |
203 | abort (); | |
204 | } | |
205 | ||
206 | addend >>= howto->rightshift; | |
207 | ||
208 | switch (r_type) | |
209 | { | |
caed7120 | 210 | case BFD_RELOC_AARCH64_CALL26: |
ce336788 | 211 | case BFD_RELOC_AARCH64_JUMP26: |
caed7120 YZ |
212 | contents = reencode_branch_ofs_26 (contents, addend); |
213 | break; | |
214 | ||
215 | case BFD_RELOC_AARCH64_BRANCH19: | |
216 | contents = reencode_cond_branch_ofs_19 (contents, addend); | |
217 | break; | |
218 | ||
219 | case BFD_RELOC_AARCH64_TSTBR14: | |
220 | contents = reencode_tst_branch_ofs_14 (contents, addend); | |
221 | break; | |
222 | ||
caed7120 | 223 | case BFD_RELOC_AARCH64_GOT_LD_PREL19: |
ce336788 JW |
224 | case BFD_RELOC_AARCH64_LD_LO19_PCREL: |
225 | case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19: | |
043bf05a | 226 | case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19: |
caed7120 YZ |
227 | if (old_addend & ((1 << howto->rightshift) - 1)) |
228 | return bfd_reloc_overflow; | |
229 | contents = reencode_ld_lit_ofs_19 (contents, addend); | |
230 | break; | |
231 | ||
232 | case BFD_RELOC_AARCH64_TLSDESC_CALL: | |
233 | break; | |
234 | ||
ce336788 JW |
235 | case BFD_RELOC_AARCH64_ADR_GOT_PAGE: |
236 | case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL: | |
237 | case BFD_RELOC_AARCH64_ADR_HI21_PCREL: | |
238 | case BFD_RELOC_AARCH64_ADR_LO21_PCREL: | |
239 | case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21: | |
389b8029 | 240 | case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21: |
caed7120 | 241 | case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21: |
ce336788 | 242 | case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21: |
caed7120 | 243 | case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: |
f69e4920 | 244 | case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21: |
77a69ff8 | 245 | case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21: |
4106101c | 246 | contents = _bfd_aarch64_reencode_adr_imm (contents, addend); |
caed7120 YZ |
247 | break; |
248 | ||
ce336788 | 249 | case BFD_RELOC_AARCH64_ADD_LO12: |
f955cccf | 250 | case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12: |
caed7120 | 251 | case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC: |
6ffe9a1b | 252 | case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12: |
40fbed84 | 253 | case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12: |
753999c1 | 254 | case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC: |
73f925cc | 255 | case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC: |
caed7120 | 256 | case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12: |
ce336788 | 257 | case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12: |
caed7120 | 258 | case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC: |
caed7120 YZ |
259 | /* Corresponds to: add rd, rn, #uimm12 to provide the low order |
260 | 12 bits of the page offset following | |
261 | BFD_RELOC_AARCH64_ADR_HI21_PCREL which computes the | |
262 | (pc-relative) page base. */ | |
263 | contents = reencode_add_imm (contents, addend); | |
264 | break; | |
265 | ||
7018c030 | 266 | case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14: |
ce336788 | 267 | case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC: |
a2e1db00 | 268 | case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15: |
99ad26cb | 269 | case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15: |
ce336788 JW |
270 | case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC: |
271 | case BFD_RELOC_AARCH64_LDST128_LO12: | |
caed7120 YZ |
272 | case BFD_RELOC_AARCH64_LDST16_LO12: |
273 | case BFD_RELOC_AARCH64_LDST32_LO12: | |
274 | case BFD_RELOC_AARCH64_LDST64_LO12: | |
ce336788 | 275 | case BFD_RELOC_AARCH64_LDST8_LO12: |
caed7120 | 276 | case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC: |
f955cccf | 277 | case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12: |
caed7120 | 278 | case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC: |
ce336788 | 279 | case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: |
07c9aa07 JW |
280 | case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12: |
281 | case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC: | |
282 | case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12: | |
283 | case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC: | |
284 | case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12: | |
285 | case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC: | |
286 | case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12: | |
287 | case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC: | |
caed7120 YZ |
288 | if (old_addend & ((1 << howto->rightshift) - 1)) |
289 | return bfd_reloc_overflow; | |
290 | /* Used for ldr*|str* rt, [rn, #uimm12] to provide the low order | |
291 | 12 bits of the page offset following BFD_RELOC_AARCH64_ADR_HI21_PCREL | |
292 | which computes the (pc-relative) page base. */ | |
293 | contents = reencode_ldst_pos_imm (contents, addend); | |
294 | break; | |
295 | ||
296 | /* Group relocations to create high bits of a 16, 32, 48 or 64 | |
297 | bit signed data or abs address inline. Will change | |
298 | instruction to MOVN or MOVZ depending on sign of calculated | |
299 | value. */ | |
300 | ||
caed7120 YZ |
301 | case BFD_RELOC_AARCH64_MOVW_G0_S: |
302 | case BFD_RELOC_AARCH64_MOVW_G1_S: | |
303 | case BFD_RELOC_AARCH64_MOVW_G2_S: | |
6ffe9a1b JW |
304 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0: |
305 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1: | |
306 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2: | |
ce336788 JW |
307 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0: |
308 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1: | |
309 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2: | |
caed7120 YZ |
310 | /* NOTE: We can only come here with movz or movn. */ |
311 | if (addend < 0) | |
312 | { | |
313 | /* Force use of MOVN. */ | |
314 | addend = ~addend; | |
315 | contents = reencode_movzn_to_movn (contents); | |
316 | } | |
317 | else | |
318 | { | |
319 | /* Force use of MOVZ. */ | |
320 | contents = reencode_movzn_to_movz (contents); | |
321 | } | |
1a0670f3 | 322 | /* Fall through. */ |
caed7120 YZ |
323 | |
324 | /* Group relocations to create a 16, 32, 48 or 64 bit unsigned | |
325 | data or abs address inline. */ | |
326 | ||
327 | case BFD_RELOC_AARCH64_MOVW_G0: | |
328 | case BFD_RELOC_AARCH64_MOVW_G0_NC: | |
329 | case BFD_RELOC_AARCH64_MOVW_G1: | |
330 | case BFD_RELOC_AARCH64_MOVW_G1_NC: | |
331 | case BFD_RELOC_AARCH64_MOVW_G2: | |
332 | case BFD_RELOC_AARCH64_MOVW_G2_NC: | |
333 | case BFD_RELOC_AARCH64_MOVW_G3: | |
dc8008f5 | 334 | case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC: |
74a1bfe1 | 335 | case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1: |
0484b454 RL |
336 | case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC: |
337 | case BFD_RELOC_AARCH64_TLSDESC_OFF_G1: | |
7ba7cfe4 | 338 | case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC: |
94facae3 | 339 | case BFD_RELOC_AARCH64_TLSGD_MOVW_G1: |
3b957e5b RL |
340 | case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC: |
341 | case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1: | |
6ffe9a1b JW |
342 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC: |
343 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC: | |
ce336788 JW |
344 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC: |
345 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC: | |
caed7120 YZ |
346 | contents = reencode_movw_imm (contents, addend); |
347 | break; | |
348 | ||
349 | default: | |
350 | /* Repack simple data */ | |
351 | if (howto->dst_mask & (howto->dst_mask + 1)) | |
352 | return bfd_reloc_notsupported; | |
353 | ||
354 | contents = ((contents & ~howto->dst_mask) | (addend & howto->dst_mask)); | |
355 | break; | |
356 | } | |
357 | ||
358 | switch (size) | |
359 | { | |
360 | case 2: | |
361 | bfd_put_16 (abfd, contents, address); | |
362 | break; | |
363 | case 4: | |
364 | if (howto->dst_mask != 0xffffffff) | |
365 | /* must be 32-bit instruction, always little-endian */ | |
366 | bfd_putl32 (contents, address); | |
367 | else | |
368 | /* must be 32-bit data (endianness dependent) */ | |
369 | bfd_put_32 (abfd, contents, address); | |
370 | break; | |
371 | case 8: | |
372 | bfd_put_64 (abfd, contents, address); | |
373 | break; | |
374 | default: | |
375 | abort (); | |
376 | } | |
377 | ||
378 | return status; | |
379 | } | |
380 | ||
381 | bfd_vma | |
382 | _bfd_aarch64_elf_resolve_relocation (bfd_reloc_code_real_type r_type, | |
383 | bfd_vma place, bfd_vma value, | |
384 | bfd_vma addend, bfd_boolean weak_undef_p) | |
385 | { | |
386 | switch (r_type) | |
387 | { | |
caed7120 | 388 | case BFD_RELOC_AARCH64_NONE: |
ce336788 | 389 | case BFD_RELOC_AARCH64_TLSDESC_CALL: |
caed7120 YZ |
390 | break; |
391 | ||
ce336788 JW |
392 | case BFD_RELOC_AARCH64_16_PCREL: |
393 | case BFD_RELOC_AARCH64_32_PCREL: | |
394 | case BFD_RELOC_AARCH64_64_PCREL: | |
395 | case BFD_RELOC_AARCH64_ADR_LO21_PCREL: | |
396 | case BFD_RELOC_AARCH64_BRANCH19: | |
397 | case BFD_RELOC_AARCH64_LD_LO19_PCREL: | |
389b8029 | 398 | case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21: |
1ada945d | 399 | case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19: |
3c12b054 | 400 | case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21: |
043bf05a | 401 | case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19: |
77a69ff8 | 402 | case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21: |
caed7120 YZ |
403 | case BFD_RELOC_AARCH64_TSTBR14: |
404 | if (weak_undef_p) | |
405 | value = place; | |
406 | value = value + addend - place; | |
407 | break; | |
408 | ||
409 | case BFD_RELOC_AARCH64_CALL26: | |
410 | case BFD_RELOC_AARCH64_JUMP26: | |
411 | value = value + addend - place; | |
412 | break; | |
413 | ||
414 | case BFD_RELOC_AARCH64_16: | |
415 | case BFD_RELOC_AARCH64_32: | |
caed7120 YZ |
416 | case BFD_RELOC_AARCH64_MOVW_G0: |
417 | case BFD_RELOC_AARCH64_MOVW_G0_NC: | |
ce336788 | 418 | case BFD_RELOC_AARCH64_MOVW_G0_S: |
caed7120 YZ |
419 | case BFD_RELOC_AARCH64_MOVW_G1: |
420 | case BFD_RELOC_AARCH64_MOVW_G1_NC: | |
ce336788 | 421 | case BFD_RELOC_AARCH64_MOVW_G1_S: |
caed7120 YZ |
422 | case BFD_RELOC_AARCH64_MOVW_G2: |
423 | case BFD_RELOC_AARCH64_MOVW_G2_NC: | |
ce336788 | 424 | case BFD_RELOC_AARCH64_MOVW_G2_S: |
caed7120 | 425 | case BFD_RELOC_AARCH64_MOVW_G3: |
0484b454 RL |
426 | case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC: |
427 | case BFD_RELOC_AARCH64_TLSDESC_OFF_G1: | |
7ba7cfe4 | 428 | case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC: |
94facae3 | 429 | case BFD_RELOC_AARCH64_TLSGD_MOVW_G1: |
6ffe9a1b | 430 | case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12: |
40fbed84 | 431 | case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12: |
753999c1 | 432 | case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC: |
07c9aa07 JW |
433 | case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12: |
434 | case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC: | |
435 | case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12: | |
436 | case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC: | |
437 | case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12: | |
438 | case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC: | |
439 | case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12: | |
440 | case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC: | |
6ffe9a1b JW |
441 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0: |
442 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC: | |
443 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1: | |
444 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC: | |
445 | case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2: | |
caed7120 YZ |
446 | value = value + addend; |
447 | break; | |
448 | ||
caed7120 | 449 | case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL: |
ce336788 | 450 | case BFD_RELOC_AARCH64_ADR_HI21_PCREL: |
caed7120 YZ |
451 | if (weak_undef_p) |
452 | value = PG (place); | |
453 | value = PG (value + addend) - PG (place); | |
454 | break; | |
455 | ||
456 | case BFD_RELOC_AARCH64_GOT_LD_PREL19: | |
457 | value = value + addend - place; | |
458 | break; | |
459 | ||
460 | case BFD_RELOC_AARCH64_ADR_GOT_PAGE: | |
461 | case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21: | |
462 | case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21: | |
463 | case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: | |
f69e4920 | 464 | case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21: |
caed7120 YZ |
465 | value = PG (value + addend) - PG (place); |
466 | break; | |
467 | ||
2aff25ba | 468 | /* Caller must make sure addend is the base address of .got section. */ |
7018c030 | 469 | case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14: |
99ad26cb | 470 | case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15: |
2aff25ba JW |
471 | addend = PG (addend); |
472 | /* Fall through. */ | |
473 | case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15: | |
474 | case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC: | |
475 | case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1: | |
476 | value = value - addend; | |
99ad26cb JW |
477 | break; |
478 | ||
caed7120 | 479 | case BFD_RELOC_AARCH64_ADD_LO12: |
caed7120 | 480 | case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC: |
ce336788 JW |
481 | case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC: |
482 | case BFD_RELOC_AARCH64_LDST128_LO12: | |
caed7120 YZ |
483 | case BFD_RELOC_AARCH64_LDST16_LO12: |
484 | case BFD_RELOC_AARCH64_LDST32_LO12: | |
485 | case BFD_RELOC_AARCH64_LDST64_LO12: | |
ce336788 | 486 | case BFD_RELOC_AARCH64_LDST8_LO12: |
caed7120 | 487 | case BFD_RELOC_AARCH64_TLSDESC_ADD: |
f955cccf | 488 | case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12: |
caed7120 | 489 | case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC: |
f955cccf | 490 | case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12: |
caed7120 YZ |
491 | case BFD_RELOC_AARCH64_TLSDESC_LDR: |
492 | case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC: | |
caed7120 | 493 | case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC: |
ce336788 | 494 | case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: |
caed7120 YZ |
495 | case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC: |
496 | value = PG_OFFSET (value + addend); | |
497 | break; | |
498 | ||
36e6c140 JW |
499 | case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12: |
500 | value = value + addend; | |
501 | break; | |
502 | ||
3b957e5b | 503 | case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1: |
caed7120 YZ |
504 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1: |
505 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC: | |
506 | value = (value + addend) & (bfd_vma) 0xffff0000; | |
507 | break; | |
508 | case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12: | |
bab91cce JW |
509 | /* Mask off low 12bits, keep all other high bits, so that the later |
510 | generic code could check whehter there is overflow. */ | |
511 | value = (value + addend) & ~(bfd_vma) 0xfff; | |
caed7120 YZ |
512 | break; |
513 | ||
3b957e5b | 514 | case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC: |
caed7120 YZ |
515 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0: |
516 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC: | |
517 | value = (value + addend) & (bfd_vma) 0xffff; | |
518 | break; | |
519 | ||
520 | case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2: | |
521 | value = (value + addend) & ~(bfd_vma) 0xffffffff; | |
522 | value -= place & ~(bfd_vma) 0xffffffff; | |
523 | break; | |
524 | ||
525 | default: | |
526 | break; | |
527 | } | |
528 | ||
529 | return value; | |
530 | } | |
531 | ||
532 | /* Hook called by the linker routine which adds symbols from an object | |
533 | file. */ | |
534 | ||
535 | bfd_boolean | |
536 | _bfd_aarch64_elf_add_symbol_hook (bfd *abfd, struct bfd_link_info *info, | |
537 | Elf_Internal_Sym *sym, | |
538 | const char **namep ATTRIBUTE_UNUSED, | |
539 | flagword *flagsp ATTRIBUTE_UNUSED, | |
540 | asection **secp ATTRIBUTE_UNUSED, | |
541 | bfd_vma *valp ATTRIBUTE_UNUSED) | |
542 | { | |
a43942db | 543 | if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC |
f1885d1e AM |
544 | && (abfd->flags & DYNAMIC) == 0 |
545 | && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour) | |
a43942db | 546 | elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc; |
caed7120 YZ |
547 | |
548 | return TRUE; | |
549 | } | |
550 | ||
551 | /* Support for core dump NOTE sections. */ | |
552 | ||
553 | bfd_boolean | |
554 | _bfd_aarch64_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note) | |
555 | { | |
556 | int offset; | |
557 | size_t size; | |
558 | ||
559 | switch (note->descsz) | |
560 | { | |
561 | default: | |
562 | return FALSE; | |
563 | ||
3b570dee | 564 | case 392: /* sizeof(struct elf_prstatus) on Linux/arm64. */ |
caed7120 YZ |
565 | /* pr_cursig */ |
566 | elf_tdata (abfd)->core->signal | |
567 | = bfd_get_16 (abfd, note->descdata + 12); | |
568 | ||
569 | /* pr_pid */ | |
570 | elf_tdata (abfd)->core->lwpid | |
571 | = bfd_get_32 (abfd, note->descdata + 32); | |
572 | ||
573 | /* pr_reg */ | |
574 | offset = 112; | |
575 | size = 272; | |
576 | ||
577 | break; | |
578 | } | |
579 | ||
580 | /* Make a ".reg/999" section. */ | |
581 | return _bfd_elfcore_make_pseudosection (abfd, ".reg", | |
582 | size, note->descpos + offset); | |
583 | } | |
d0ae9fbd OJ |
584 | |
585 | bfd_boolean | |
586 | _bfd_aarch64_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note) | |
587 | { | |
588 | switch (note->descsz) | |
589 | { | |
590 | default: | |
591 | return FALSE; | |
592 | ||
593 | case 136: /* This is sizeof(struct elf_prpsinfo) on Linux/aarch64. */ | |
594 | elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24); | |
595 | elf_tdata (abfd)->core->program | |
596 | = _bfd_elfcore_strndup (abfd, note->descdata + 40, 16); | |
597 | elf_tdata (abfd)->core->command | |
598 | = _bfd_elfcore_strndup (abfd, note->descdata + 56, 80); | |
599 | } | |
600 | ||
601 | /* Note that for some reason, a spurious space is tacked | |
602 | onto the end of the args in some (at least one anyway) | |
603 | implementations, so strip it off if it exists. */ | |
604 | ||
605 | { | |
606 | char *command = elf_tdata (abfd)->core->command; | |
607 | int n = strlen (command); | |
608 | ||
609 | if (0 < n && command[n - 1] == ' ') | |
610 | command[n - 1] = '\0'; | |
611 | } | |
612 | ||
613 | return TRUE; | |
614 | } | |
615 | ||
616 | char * | |
617 | _bfd_aarch64_elf_write_core_note (bfd *abfd, char *buf, int *bufsiz, int note_type, | |
618 | ...) | |
619 | { | |
620 | switch (note_type) | |
621 | { | |
622 | default: | |
623 | return NULL; | |
624 | ||
625 | case NT_PRPSINFO: | |
626 | { | |
627 | char data[136]; | |
628 | va_list ap; | |
629 | ||
630 | va_start (ap, note_type); | |
631 | memset (data, 0, sizeof (data)); | |
632 | strncpy (data + 40, va_arg (ap, const char *), 16); | |
633 | strncpy (data + 56, va_arg (ap, const char *), 80); | |
634 | va_end (ap); | |
635 | ||
636 | return elfcore_write_note (abfd, buf, bufsiz, "CORE", | |
637 | note_type, data, sizeof (data)); | |
638 | } | |
639 | ||
640 | case NT_PRSTATUS: | |
641 | { | |
642 | char data[392]; | |
643 | va_list ap; | |
644 | long pid; | |
645 | int cursig; | |
646 | const void *greg; | |
647 | ||
648 | va_start (ap, note_type); | |
649 | memset (data, 0, sizeof (data)); | |
650 | pid = va_arg (ap, long); | |
651 | bfd_put_32 (abfd, pid, data + 32); | |
652 | cursig = va_arg (ap, int); | |
653 | bfd_put_16 (abfd, cursig, data + 12); | |
654 | greg = va_arg (ap, const void *); | |
655 | memcpy (data + 112, greg, 272); | |
656 | va_end (ap); | |
657 | ||
658 | return elfcore_write_note (abfd, buf, bufsiz, "CORE", | |
659 | note_type, data, sizeof (data)); | |
660 | } | |
661 | } | |
662 | } |