Commit | Line | Data |
---|---|---|
e0001a05 | 1 | /* Xtensa configuration-specific ISA information. |
43cd72b9 | 2 | Copyright 2003, 2004 Free Software Foundation, Inc. |
e0001a05 NC |
3 | |
4 | This file is part of BFD, the Binary File Descriptor library. | |
5 | ||
43cd72b9 BW |
6 | This program is free software; you can redistribute it and/or |
7 | modify it under the terms of the GNU General Public License as | |
8 | published by the Free Software Foundation; either version 2 of the | |
9 | License, or (at your option) any later version. | |
e0001a05 NC |
10 | |
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
43cd72b9 BW |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
14 | General Public License for more details. | |
e0001a05 NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
43cd72b9 BW |
18 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA |
19 | 02111-1307, USA. */ | |
e0001a05 | 20 | |
43cd72b9 | 21 | #include "ansidecl.h" |
e0001a05 NC |
22 | #include <xtensa-isa.h> |
23 | #include "xtensa-isa-internal.h" | |
e0001a05 | 24 | |
43cd72b9 BW |
25 | \f |
26 | /* Sysregs. */ | |
27 | ||
28 | static xtensa_sysreg_internal sysregs[] = { | |
29 | { "LBEG", 0, 0 }, | |
30 | { "LEND", 1, 0 }, | |
31 | { "LCOUNT", 2, 0 }, | |
32 | { "DDR", 104, 0 }, | |
33 | { "176", 176, 0 }, | |
34 | { "208", 208, 0 }, | |
35 | { "INTERRUPT", 226, 0 }, | |
36 | { "INTCLEAR", 227, 0 }, | |
37 | { "CCOUNT", 234, 0 }, | |
38 | { "PRID", 235, 0 }, | |
39 | { "ICOUNT", 236, 0 }, | |
40 | { "CCOMPARE0", 240, 0 }, | |
41 | { "CCOMPARE1", 241, 0 }, | |
42 | { "CCOMPARE2", 242, 0 }, | |
43 | { "EPC1", 177, 0 }, | |
44 | { "EPC2", 178, 0 }, | |
45 | { "EPC3", 179, 0 }, | |
46 | { "EPC4", 180, 0 }, | |
47 | { "EXCSAVE1", 209, 0 }, | |
48 | { "EXCSAVE2", 210, 0 }, | |
49 | { "EXCSAVE3", 211, 0 }, | |
50 | { "EXCSAVE4", 212, 0 }, | |
51 | { "EPS2", 194, 0 }, | |
52 | { "EPS3", 195, 0 }, | |
53 | { "EPS4", 196, 0 }, | |
54 | { "EXCCAUSE", 232, 0 }, | |
55 | { "DEPC", 192, 0 }, | |
56 | { "EXCVADDR", 238, 0 }, | |
57 | { "WINDOWBASE", 72, 0 }, | |
58 | { "WINDOWSTART", 73, 0 }, | |
59 | { "SAR", 3, 0 }, | |
60 | { "LITBASE", 5, 0 }, | |
61 | { "PS", 230, 0 }, | |
62 | { "MISC0", 244, 0 }, | |
63 | { "MISC1", 245, 0 }, | |
64 | { "INTENABLE", 228, 0 }, | |
65 | { "DBREAKA0", 144, 0 }, | |
66 | { "DBREAKC0", 160, 0 }, | |
67 | { "DBREAKA1", 145, 0 }, | |
68 | { "DBREAKC1", 161, 0 }, | |
69 | { "IBREAKA0", 128, 0 }, | |
70 | { "IBREAKA1", 129, 0 }, | |
71 | { "IBREAKENABLE", 96, 0 }, | |
72 | { "ICOUNTLEVEL", 237, 0 }, | |
73 | { "DEBUGCAUSE", 233, 0 } | |
74 | }; | |
75 | ||
76 | #define NUM_SYSREGS 45 | |
77 | #define MAX_SPECIAL_REG 245 | |
78 | #define MAX_USER_REG 0 | |
79 | ||
80 | \f | |
81 | /* Processor states. */ | |
82 | ||
83 | static xtensa_state_internal states[] = { | |
84 | { "LCOUNT", 32, 0 }, | |
85 | { "PC", 32, 0 }, | |
86 | { "ICOUNT", 32, 0 }, | |
87 | { "DDR", 32, 0 }, | |
88 | { "INTERRUPT", 17, 0 }, | |
89 | { "CCOUNT", 32, 0 }, | |
90 | { "XTSYNC", 1, 0 }, | |
91 | { "EPC1", 32, 0 }, | |
92 | { "EPC2", 32, 0 }, | |
93 | { "EPC3", 32, 0 }, | |
94 | { "EPC4", 32, 0 }, | |
95 | { "EXCSAVE1", 32, 0 }, | |
96 | { "EXCSAVE2", 32, 0 }, | |
97 | { "EXCSAVE3", 32, 0 }, | |
98 | { "EXCSAVE4", 32, 0 }, | |
99 | { "EPS2", 13, 0 }, | |
100 | { "EPS3", 13, 0 }, | |
101 | { "EPS4", 13, 0 }, | |
102 | { "EXCCAUSE", 6, 0 }, | |
103 | { "PSINTLEVEL", 4, 0 }, | |
104 | { "PSUM", 1, 0 }, | |
105 | { "PSWOE", 1, 0 }, | |
106 | { "PSEXCM", 1, 0 }, | |
107 | { "DEPC", 32, 0 }, | |
108 | { "EXCVADDR", 32, 0 }, | |
109 | { "WindowBase", 4, 0 }, | |
110 | { "WindowStart", 16, 0 }, | |
111 | { "PSCALLINC", 2, 0 }, | |
112 | { "PSOWB", 4, 0 }, | |
113 | { "LBEG", 32, 0 }, | |
114 | { "LEND", 32, 0 }, | |
115 | { "SAR", 6, 0 }, | |
116 | { "LITBADDR", 20, 0 }, | |
117 | { "LITBEN", 1, 0 }, | |
118 | { "MISC0", 32, 0 }, | |
119 | { "MISC1", 32, 0 }, | |
120 | { "InOCDMode", 1, 0 }, | |
121 | { "INTENABLE", 17, 0 }, | |
122 | { "DBREAKA0", 32, 0 }, | |
123 | { "DBREAKC0", 8, 0 }, | |
124 | { "DBREAKA1", 32, 0 }, | |
125 | { "DBREAKC1", 8, 0 }, | |
126 | { "IBREAKA0", 32, 0 }, | |
127 | { "IBREAKA1", 32, 0 }, | |
128 | { "IBREAKENABLE", 2, 0 }, | |
129 | { "ICOUNTLEVEL", 4, 0 }, | |
130 | { "DEBUGCAUSE", 6, 0 }, | |
131 | { "DBNUM", 4, 0 }, | |
132 | { "CCOMPARE0", 32, 0 }, | |
133 | { "CCOMPARE1", 32, 0 }, | |
134 | { "CCOMPARE2", 32, 0 } | |
135 | }; | |
136 | ||
137 | #define NUM_STATES 51 | |
138 | ||
139 | /* Macros for xtensa_state numbers (for use in iclasses because the | |
140 | state numbers are not available when the iclass table is generated). */ | |
141 | ||
142 | #define STATE_LCOUNT 0 | |
143 | #define STATE_PC 1 | |
144 | #define STATE_ICOUNT 2 | |
145 | #define STATE_DDR 3 | |
146 | #define STATE_INTERRUPT 4 | |
147 | #define STATE_CCOUNT 5 | |
148 | #define STATE_XTSYNC 6 | |
149 | #define STATE_EPC1 7 | |
150 | #define STATE_EPC2 8 | |
151 | #define STATE_EPC3 9 | |
152 | #define STATE_EPC4 10 | |
153 | #define STATE_EXCSAVE1 11 | |
154 | #define STATE_EXCSAVE2 12 | |
155 | #define STATE_EXCSAVE3 13 | |
156 | #define STATE_EXCSAVE4 14 | |
157 | #define STATE_EPS2 15 | |
158 | #define STATE_EPS3 16 | |
159 | #define STATE_EPS4 17 | |
160 | #define STATE_EXCCAUSE 18 | |
161 | #define STATE_PSINTLEVEL 19 | |
162 | #define STATE_PSUM 20 | |
163 | #define STATE_PSWOE 21 | |
164 | #define STATE_PSEXCM 22 | |
165 | #define STATE_DEPC 23 | |
166 | #define STATE_EXCVADDR 24 | |
167 | #define STATE_WindowBase 25 | |
168 | #define STATE_WindowStart 26 | |
169 | #define STATE_PSCALLINC 27 | |
170 | #define STATE_PSOWB 28 | |
171 | #define STATE_LBEG 29 | |
172 | #define STATE_LEND 30 | |
173 | #define STATE_SAR 31 | |
174 | #define STATE_LITBADDR 32 | |
175 | #define STATE_LITBEN 33 | |
176 | #define STATE_MISC0 34 | |
177 | #define STATE_MISC1 35 | |
178 | #define STATE_InOCDMode 36 | |
179 | #define STATE_INTENABLE 37 | |
180 | #define STATE_DBREAKA0 38 | |
181 | #define STATE_DBREAKC0 39 | |
182 | #define STATE_DBREAKA1 40 | |
183 | #define STATE_DBREAKC1 41 | |
184 | #define STATE_IBREAKA0 42 | |
185 | #define STATE_IBREAKA1 43 | |
186 | #define STATE_IBREAKENABLE 44 | |
187 | #define STATE_ICOUNTLEVEL 45 | |
188 | #define STATE_DEBUGCAUSE 46 | |
189 | #define STATE_DBNUM 47 | |
190 | #define STATE_CCOMPARE0 48 | |
191 | #define STATE_CCOMPARE1 49 | |
192 | #define STATE_CCOMPARE2 50 | |
193 | ||
194 | \f | |
195 | /* Field definitions. */ | |
196 | ||
197 | static unsigned | |
198 | Field_t_Slot_inst_get (const xtensa_insnbuf insn) | |
199 | { | |
200 | unsigned tie_t = 0; | |
201 | tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); | |
202 | return tie_t; | |
203 | } | |
204 | ||
205 | static void | |
206 | Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
207 | { | |
208 | uint32 tie_t; | |
209 | tie_t = (val << 28) >> 28; | |
210 | insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); | |
211 | } | |
212 | ||
213 | static unsigned | |
214 | Field_s_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 215 | { |
43cd72b9 BW |
216 | unsigned tie_t = 0; |
217 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); | |
218 | return tie_t; | |
e0001a05 NC |
219 | } |
220 | ||
43cd72b9 BW |
221 | static void |
222 | Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 223 | { |
43cd72b9 BW |
224 | uint32 tie_t; |
225 | tie_t = (val << 28) >> 28; | |
226 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); | |
e0001a05 NC |
227 | } |
228 | ||
43cd72b9 BW |
229 | static unsigned |
230 | Field_r_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 231 | { |
43cd72b9 BW |
232 | unsigned tie_t = 0; |
233 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); | |
234 | return tie_t; | |
e0001a05 NC |
235 | } |
236 | ||
43cd72b9 BW |
237 | static void |
238 | Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 239 | { |
43cd72b9 BW |
240 | uint32 tie_t; |
241 | tie_t = (val << 28) >> 28; | |
242 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); | |
e0001a05 NC |
243 | } |
244 | ||
43cd72b9 BW |
245 | static unsigned |
246 | Field_op2_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 247 | { |
43cd72b9 BW |
248 | unsigned tie_t = 0; |
249 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); | |
250 | return tie_t; | |
e0001a05 NC |
251 | } |
252 | ||
43cd72b9 BW |
253 | static void |
254 | Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 255 | { |
43cd72b9 BW |
256 | uint32 tie_t; |
257 | tie_t = (val << 28) >> 28; | |
258 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); | |
e0001a05 NC |
259 | } |
260 | ||
43cd72b9 BW |
261 | static unsigned |
262 | Field_op1_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 263 | { |
43cd72b9 BW |
264 | unsigned tie_t = 0; |
265 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); | |
266 | return tie_t; | |
e0001a05 NC |
267 | } |
268 | ||
43cd72b9 BW |
269 | static void |
270 | Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 271 | { |
43cd72b9 BW |
272 | uint32 tie_t; |
273 | tie_t = (val << 28) >> 28; | |
274 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); | |
e0001a05 NC |
275 | } |
276 | ||
43cd72b9 BW |
277 | static unsigned |
278 | Field_op0_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 279 | { |
43cd72b9 BW |
280 | unsigned tie_t = 0; |
281 | tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); | |
282 | return tie_t; | |
e0001a05 NC |
283 | } |
284 | ||
43cd72b9 BW |
285 | static void |
286 | Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 287 | { |
43cd72b9 BW |
288 | uint32 tie_t; |
289 | tie_t = (val << 28) >> 28; | |
290 | insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); | |
e0001a05 NC |
291 | } |
292 | ||
43cd72b9 BW |
293 | static unsigned |
294 | Field_n_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 295 | { |
43cd72b9 BW |
296 | unsigned tie_t = 0; |
297 | tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); | |
298 | return tie_t; | |
e0001a05 NC |
299 | } |
300 | ||
43cd72b9 BW |
301 | static void |
302 | Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 303 | { |
43cd72b9 BW |
304 | uint32 tie_t; |
305 | tie_t = (val << 30) >> 30; | |
306 | insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); | |
e0001a05 NC |
307 | } |
308 | ||
43cd72b9 BW |
309 | static unsigned |
310 | Field_m_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 311 | { |
43cd72b9 BW |
312 | unsigned tie_t = 0; |
313 | tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); | |
314 | return tie_t; | |
e0001a05 NC |
315 | } |
316 | ||
43cd72b9 BW |
317 | static void |
318 | Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 319 | { |
43cd72b9 BW |
320 | uint32 tie_t; |
321 | tie_t = (val << 30) >> 30; | |
322 | insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); | |
e0001a05 NC |
323 | } |
324 | ||
43cd72b9 BW |
325 | static unsigned |
326 | Field_sr_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 327 | { |
43cd72b9 BW |
328 | unsigned tie_t = 0; |
329 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); | |
330 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); | |
331 | return tie_t; | |
e0001a05 NC |
332 | } |
333 | ||
43cd72b9 BW |
334 | static void |
335 | Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 336 | { |
43cd72b9 BW |
337 | uint32 tie_t; |
338 | tie_t = (val << 28) >> 28; | |
339 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); | |
340 | tie_t = (val << 24) >> 28; | |
341 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); | |
e0001a05 NC |
342 | } |
343 | ||
43cd72b9 BW |
344 | static unsigned |
345 | Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 346 | { |
43cd72b9 BW |
347 | unsigned tie_t = 0; |
348 | tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); | |
349 | return tie_t; | |
e0001a05 NC |
350 | } |
351 | ||
43cd72b9 BW |
352 | static void |
353 | Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 354 | { |
43cd72b9 BW |
355 | uint32 tie_t; |
356 | tie_t = (val << 29) >> 29; | |
357 | insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); | |
e0001a05 NC |
358 | } |
359 | ||
43cd72b9 BW |
360 | static unsigned |
361 | Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) | |
e0001a05 | 362 | { |
43cd72b9 BW |
363 | unsigned tie_t = 0; |
364 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); | |
365 | return tie_t; | |
e0001a05 NC |
366 | } |
367 | ||
43cd72b9 BW |
368 | static void |
369 | Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 370 | { |
43cd72b9 BW |
371 | uint32 tie_t; |
372 | tie_t = (val << 28) >> 28; | |
373 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); | |
e0001a05 NC |
374 | } |
375 | ||
43cd72b9 BW |
376 | static unsigned |
377 | Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) | |
e0001a05 | 378 | { |
43cd72b9 BW |
379 | unsigned tie_t = 0; |
380 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); | |
381 | return tie_t; | |
e0001a05 NC |
382 | } |
383 | ||
43cd72b9 BW |
384 | static void |
385 | Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 386 | { |
43cd72b9 BW |
387 | uint32 tie_t; |
388 | tie_t = (val << 28) >> 28; | |
389 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); | |
e0001a05 NC |
390 | } |
391 | ||
43cd72b9 BW |
392 | static unsigned |
393 | Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) | |
e0001a05 | 394 | { |
43cd72b9 BW |
395 | unsigned tie_t = 0; |
396 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); | |
397 | return tie_t; | |
e0001a05 NC |
398 | } |
399 | ||
43cd72b9 BW |
400 | static void |
401 | Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 402 | { |
43cd72b9 BW |
403 | uint32 tie_t; |
404 | tie_t = (val << 28) >> 28; | |
405 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); | |
e0001a05 NC |
406 | } |
407 | ||
43cd72b9 BW |
408 | static unsigned |
409 | Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) | |
e0001a05 | 410 | { |
43cd72b9 BW |
411 | unsigned tie_t = 0; |
412 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); | |
413 | return tie_t; | |
e0001a05 NC |
414 | } |
415 | ||
43cd72b9 BW |
416 | static void |
417 | Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 418 | { |
43cd72b9 BW |
419 | uint32 tie_t; |
420 | tie_t = (val << 28) >> 28; | |
421 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); | |
e0001a05 NC |
422 | } |
423 | ||
43cd72b9 BW |
424 | static unsigned |
425 | Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) | |
e0001a05 | 426 | { |
43cd72b9 BW |
427 | unsigned tie_t = 0; |
428 | tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); | |
429 | return tie_t; | |
e0001a05 NC |
430 | } |
431 | ||
43cd72b9 BW |
432 | static void |
433 | Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 434 | { |
43cd72b9 BW |
435 | uint32 tie_t; |
436 | tie_t = (val << 31) >> 31; | |
437 | insn[0] = (insn[0] & ~0x400) | (tie_t << 10); | |
e0001a05 NC |
438 | } |
439 | ||
43cd72b9 BW |
440 | static unsigned |
441 | Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) | |
e0001a05 | 442 | { |
43cd72b9 BW |
443 | unsigned tie_t = 0; |
444 | tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); | |
445 | return tie_t; | |
e0001a05 NC |
446 | } |
447 | ||
43cd72b9 BW |
448 | static void |
449 | Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 450 | { |
43cd72b9 BW |
451 | uint32 tie_t; |
452 | tie_t = (val << 31) >> 31; | |
453 | insn[0] = (insn[0] & ~0x800) | (tie_t << 11); | |
e0001a05 NC |
454 | } |
455 | ||
43cd72b9 BW |
456 | static unsigned |
457 | Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) | |
e0001a05 | 458 | { |
43cd72b9 BW |
459 | unsigned tie_t = 0; |
460 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); | |
461 | return tie_t; | |
e0001a05 NC |
462 | } |
463 | ||
43cd72b9 BW |
464 | static void |
465 | Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 466 | { |
43cd72b9 BW |
467 | uint32 tie_t; |
468 | tie_t = (val << 28) >> 28; | |
469 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); | |
e0001a05 NC |
470 | } |
471 | ||
43cd72b9 BW |
472 | static unsigned |
473 | Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) | |
e0001a05 | 474 | { |
43cd72b9 BW |
475 | unsigned tie_t = 0; |
476 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); | |
477 | return tie_t; | |
e0001a05 NC |
478 | } |
479 | ||
43cd72b9 BW |
480 | static void |
481 | Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 482 | { |
43cd72b9 BW |
483 | uint32 tie_t; |
484 | tie_t = (val << 28) >> 28; | |
485 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); | |
e0001a05 NC |
486 | } |
487 | ||
43cd72b9 BW |
488 | static unsigned |
489 | Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 490 | { |
43cd72b9 BW |
491 | unsigned tie_t = 0; |
492 | tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); | |
493 | return tie_t; | |
e0001a05 NC |
494 | } |
495 | ||
43cd72b9 BW |
496 | static void |
497 | Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 498 | { |
43cd72b9 BW |
499 | uint32 tie_t; |
500 | tie_t = (val << 31) >> 31; | |
501 | insn[0] = (insn[0] & ~0x100) | (tie_t << 8); | |
e0001a05 NC |
502 | } |
503 | ||
43cd72b9 BW |
504 | static unsigned |
505 | Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 506 | { |
43cd72b9 BW |
507 | unsigned tie_t = 0; |
508 | tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); | |
509 | tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); | |
510 | return tie_t; | |
e0001a05 NC |
511 | } |
512 | ||
43cd72b9 BW |
513 | static void |
514 | Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 515 | { |
43cd72b9 BW |
516 | uint32 tie_t; |
517 | tie_t = (val << 28) >> 28; | |
518 | insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); | |
519 | tie_t = (val << 27) >> 31; | |
520 | insn[0] = (insn[0] & ~0x100) | (tie_t << 8); | |
e0001a05 NC |
521 | } |
522 | ||
43cd72b9 BW |
523 | static unsigned |
524 | Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 525 | { |
43cd72b9 BW |
526 | unsigned tie_t = 0; |
527 | tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); | |
528 | return tie_t; | |
e0001a05 NC |
529 | } |
530 | ||
43cd72b9 BW |
531 | static void |
532 | Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 533 | { |
43cd72b9 BW |
534 | uint32 tie_t; |
535 | tie_t = (val << 20) >> 20; | |
536 | insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); | |
e0001a05 NC |
537 | } |
538 | ||
43cd72b9 BW |
539 | static unsigned |
540 | Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 541 | { |
43cd72b9 BW |
542 | unsigned tie_t = 0; |
543 | tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); | |
544 | return tie_t; | |
e0001a05 NC |
545 | } |
546 | ||
43cd72b9 BW |
547 | static void |
548 | Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 549 | { |
43cd72b9 BW |
550 | uint32 tie_t; |
551 | tie_t = (val << 24) >> 24; | |
552 | insn[0] = (insn[0] & ~0xff) | (tie_t << 0); | |
e0001a05 NC |
553 | } |
554 | ||
43cd72b9 BW |
555 | static unsigned |
556 | Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) | |
e0001a05 | 557 | { |
43cd72b9 BW |
558 | unsigned tie_t = 0; |
559 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); | |
560 | return tie_t; | |
e0001a05 NC |
561 | } |
562 | ||
43cd72b9 BW |
563 | static void |
564 | Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 565 | { |
43cd72b9 BW |
566 | uint32 tie_t; |
567 | tie_t = (val << 28) >> 28; | |
568 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); | |
e0001a05 NC |
569 | } |
570 | ||
43cd72b9 BW |
571 | static unsigned |
572 | Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 573 | { |
43cd72b9 BW |
574 | unsigned tie_t = 0; |
575 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); | |
576 | tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); | |
577 | return tie_t; | |
e0001a05 NC |
578 | } |
579 | ||
43cd72b9 BW |
580 | static void |
581 | Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 582 | { |
43cd72b9 BW |
583 | uint32 tie_t; |
584 | tie_t = (val << 24) >> 24; | |
585 | insn[0] = (insn[0] & ~0xff) | (tie_t << 0); | |
586 | tie_t = (val << 20) >> 28; | |
587 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); | |
e0001a05 NC |
588 | } |
589 | ||
43cd72b9 BW |
590 | static unsigned |
591 | Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 592 | { |
43cd72b9 BW |
593 | unsigned tie_t = 0; |
594 | tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); | |
595 | return tie_t; | |
e0001a05 NC |
596 | } |
597 | ||
43cd72b9 BW |
598 | static void |
599 | Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 600 | { |
43cd72b9 BW |
601 | uint32 tie_t; |
602 | tie_t = (val << 16) >> 16; | |
603 | insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); | |
e0001a05 NC |
604 | } |
605 | ||
43cd72b9 BW |
606 | static unsigned |
607 | Field_offset_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 608 | { |
43cd72b9 BW |
609 | unsigned tie_t = 0; |
610 | tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); | |
611 | return tie_t; | |
e0001a05 NC |
612 | } |
613 | ||
43cd72b9 BW |
614 | static void |
615 | Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 616 | { |
43cd72b9 BW |
617 | uint32 tie_t; |
618 | tie_t = (val << 14) >> 14; | |
619 | insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); | |
e0001a05 NC |
620 | } |
621 | ||
43cd72b9 BW |
622 | static unsigned |
623 | Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) | |
e0001a05 | 624 | { |
43cd72b9 BW |
625 | unsigned tie_t = 0; |
626 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); | |
627 | return tie_t; | |
e0001a05 NC |
628 | } |
629 | ||
43cd72b9 BW |
630 | static void |
631 | Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 632 | { |
43cd72b9 BW |
633 | uint32 tie_t; |
634 | tie_t = (val << 28) >> 28; | |
635 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); | |
e0001a05 NC |
636 | } |
637 | ||
43cd72b9 BW |
638 | static unsigned |
639 | Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 640 | { |
43cd72b9 BW |
641 | unsigned tie_t = 0; |
642 | tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); | |
643 | return tie_t; | |
e0001a05 NC |
644 | } |
645 | ||
43cd72b9 BW |
646 | static void |
647 | Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 648 | { |
43cd72b9 BW |
649 | uint32 tie_t; |
650 | tie_t = (val << 31) >> 31; | |
651 | insn[0] = (insn[0] & ~0x1) | (tie_t << 0); | |
e0001a05 NC |
652 | } |
653 | ||
43cd72b9 BW |
654 | static unsigned |
655 | Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 656 | { |
43cd72b9 BW |
657 | unsigned tie_t = 0; |
658 | tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); | |
659 | return tie_t; | |
e0001a05 NC |
660 | } |
661 | ||
43cd72b9 BW |
662 | static void |
663 | Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 664 | { |
43cd72b9 BW |
665 | uint32 tie_t; |
666 | tie_t = (val << 31) >> 31; | |
667 | insn[0] = (insn[0] & ~0x10) | (tie_t << 4); | |
e0001a05 NC |
668 | } |
669 | ||
43cd72b9 BW |
670 | static unsigned |
671 | Field_sae_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 672 | { |
43cd72b9 BW |
673 | unsigned tie_t = 0; |
674 | tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); | |
675 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); | |
676 | return tie_t; | |
e0001a05 NC |
677 | } |
678 | ||
43cd72b9 BW |
679 | static void |
680 | Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 681 | { |
43cd72b9 BW |
682 | uint32 tie_t; |
683 | tie_t = (val << 28) >> 28; | |
684 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); | |
685 | tie_t = (val << 27) >> 31; | |
686 | insn[0] = (insn[0] & ~0x10) | (tie_t << 4); | |
e0001a05 NC |
687 | } |
688 | ||
43cd72b9 BW |
689 | static unsigned |
690 | Field_sal_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 691 | { |
43cd72b9 BW |
692 | unsigned tie_t = 0; |
693 | tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); | |
694 | tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); | |
695 | return tie_t; | |
e0001a05 NC |
696 | } |
697 | ||
43cd72b9 BW |
698 | static void |
699 | Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 700 | { |
43cd72b9 BW |
701 | uint32 tie_t; |
702 | tie_t = (val << 28) >> 28; | |
703 | insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); | |
704 | tie_t = (val << 27) >> 31; | |
705 | insn[0] = (insn[0] & ~0x1) | (tie_t << 0); | |
e0001a05 NC |
706 | } |
707 | ||
43cd72b9 BW |
708 | static unsigned |
709 | Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 710 | { |
43cd72b9 BW |
711 | unsigned tie_t = 0; |
712 | tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); | |
713 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); | |
714 | return tie_t; | |
e0001a05 NC |
715 | } |
716 | ||
43cd72b9 BW |
717 | static void |
718 | Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 719 | { |
43cd72b9 BW |
720 | uint32 tie_t; |
721 | tie_t = (val << 28) >> 28; | |
722 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); | |
723 | tie_t = (val << 27) >> 31; | |
724 | insn[0] = (insn[0] & ~0x1) | (tie_t << 0); | |
e0001a05 NC |
725 | } |
726 | ||
43cd72b9 BW |
727 | static unsigned |
728 | Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 729 | { |
43cd72b9 BW |
730 | unsigned tie_t = 0; |
731 | tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); | |
732 | return tie_t; | |
e0001a05 NC |
733 | } |
734 | ||
43cd72b9 BW |
735 | static void |
736 | Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 737 | { |
43cd72b9 BW |
738 | uint32 tie_t; |
739 | tie_t = (val << 31) >> 31; | |
740 | insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); | |
e0001a05 NC |
741 | } |
742 | ||
43cd72b9 BW |
743 | static unsigned |
744 | Field_sas_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 745 | { |
43cd72b9 BW |
746 | unsigned tie_t = 0; |
747 | tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); | |
748 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); | |
749 | return tie_t; | |
e0001a05 NC |
750 | } |
751 | ||
43cd72b9 BW |
752 | static void |
753 | Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 754 | { |
43cd72b9 BW |
755 | uint32 tie_t; |
756 | tie_t = (val << 28) >> 28; | |
757 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); | |
758 | tie_t = (val << 27) >> 31; | |
759 | insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); | |
e0001a05 NC |
760 | } |
761 | ||
43cd72b9 BW |
762 | static unsigned |
763 | Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) | |
e0001a05 | 764 | { |
43cd72b9 BW |
765 | unsigned tie_t = 0; |
766 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); | |
767 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); | |
768 | return tie_t; | |
e0001a05 NC |
769 | } |
770 | ||
43cd72b9 BW |
771 | static void |
772 | Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 773 | { |
43cd72b9 BW |
774 | uint32 tie_t; |
775 | tie_t = (val << 28) >> 28; | |
776 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); | |
777 | tie_t = (val << 24) >> 28; | |
778 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); | |
e0001a05 NC |
779 | } |
780 | ||
43cd72b9 BW |
781 | static unsigned |
782 | Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) | |
e0001a05 | 783 | { |
43cd72b9 BW |
784 | unsigned tie_t = 0; |
785 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); | |
786 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); | |
787 | return tie_t; | |
e0001a05 NC |
788 | } |
789 | ||
43cd72b9 BW |
790 | static void |
791 | Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) | |
792 | { | |
793 | uint32 tie_t; | |
794 | tie_t = (val << 28) >> 28; | |
795 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); | |
796 | tie_t = (val << 24) >> 28; | |
797 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); | |
798 | } | |
e0001a05 | 799 | |
43cd72b9 BW |
800 | static unsigned |
801 | Field_st_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 802 | { |
43cd72b9 BW |
803 | unsigned tie_t = 0; |
804 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); | |
805 | tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); | |
806 | return tie_t; | |
e0001a05 NC |
807 | } |
808 | ||
43cd72b9 BW |
809 | static void |
810 | Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 811 | { |
43cd72b9 BW |
812 | uint32 tie_t; |
813 | tie_t = (val << 28) >> 28; | |
814 | insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); | |
815 | tie_t = (val << 24) >> 28; | |
816 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); | |
e0001a05 NC |
817 | } |
818 | ||
43cd72b9 BW |
819 | static unsigned |
820 | Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) | |
e0001a05 | 821 | { |
43cd72b9 BW |
822 | unsigned tie_t = 0; |
823 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); | |
824 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); | |
825 | return tie_t; | |
e0001a05 NC |
826 | } |
827 | ||
43cd72b9 BW |
828 | static void |
829 | Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 830 | { |
43cd72b9 BW |
831 | uint32 tie_t; |
832 | tie_t = (val << 28) >> 28; | |
833 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); | |
834 | tie_t = (val << 24) >> 28; | |
835 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); | |
e0001a05 NC |
836 | } |
837 | ||
43cd72b9 BW |
838 | static unsigned |
839 | Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) | |
e0001a05 | 840 | { |
43cd72b9 BW |
841 | unsigned tie_t = 0; |
842 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); | |
843 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); | |
844 | return tie_t; | |
e0001a05 NC |
845 | } |
846 | ||
43cd72b9 BW |
847 | static void |
848 | Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 849 | { |
43cd72b9 BW |
850 | uint32 tie_t; |
851 | tie_t = (val << 28) >> 28; | |
852 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); | |
853 | tie_t = (val << 24) >> 28; | |
854 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); | |
e0001a05 NC |
855 | } |
856 | ||
43cd72b9 BW |
857 | static unsigned |
858 | Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 859 | { |
43cd72b9 BW |
860 | unsigned tie_t = 0; |
861 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); | |
862 | return tie_t; | |
e0001a05 NC |
863 | } |
864 | ||
43cd72b9 BW |
865 | static void |
866 | Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 867 | { |
43cd72b9 BW |
868 | uint32 tie_t; |
869 | tie_t = (val << 28) >> 28; | |
870 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); | |
e0001a05 NC |
871 | } |
872 | ||
43cd72b9 BW |
873 | static unsigned |
874 | Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) | |
e0001a05 | 875 | { |
43cd72b9 BW |
876 | unsigned tie_t = 0; |
877 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); | |
878 | return tie_t; | |
e0001a05 NC |
879 | } |
880 | ||
43cd72b9 BW |
881 | static void |
882 | Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 883 | { |
43cd72b9 BW |
884 | uint32 tie_t; |
885 | tie_t = (val << 28) >> 28; | |
886 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); | |
e0001a05 NC |
887 | } |
888 | ||
43cd72b9 BW |
889 | static unsigned |
890 | Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) | |
e0001a05 | 891 | { |
43cd72b9 BW |
892 | unsigned tie_t = 0; |
893 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); | |
894 | return tie_t; | |
e0001a05 NC |
895 | } |
896 | ||
43cd72b9 BW |
897 | static void |
898 | Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 899 | { |
43cd72b9 BW |
900 | uint32 tie_t; |
901 | tie_t = (val << 28) >> 28; | |
902 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); | |
e0001a05 NC |
903 | } |
904 | ||
43cd72b9 BW |
905 | static unsigned |
906 | Field_mn_Slot_inst_get (const xtensa_insnbuf insn) | |
e0001a05 | 907 | { |
43cd72b9 BW |
908 | unsigned tie_t = 0; |
909 | tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); | |
910 | tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); | |
911 | return tie_t; | |
e0001a05 NC |
912 | } |
913 | ||
43cd72b9 BW |
914 | static void |
915 | Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 916 | { |
43cd72b9 BW |
917 | uint32 tie_t; |
918 | tie_t = (val << 30) >> 30; | |
919 | insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); | |
920 | tie_t = (val << 28) >> 30; | |
921 | insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); | |
e0001a05 NC |
922 | } |
923 | ||
43cd72b9 BW |
924 | static unsigned |
925 | Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) | |
e0001a05 | 926 | { |
43cd72b9 BW |
927 | unsigned tie_t = 0; |
928 | tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); | |
929 | return tie_t; | |
e0001a05 NC |
930 | } |
931 | ||
43cd72b9 BW |
932 | static void |
933 | Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 934 | { |
43cd72b9 BW |
935 | uint32 tie_t; |
936 | tie_t = (val << 31) >> 31; | |
937 | insn[0] = (insn[0] & ~0x800) | (tie_t << 11); | |
e0001a05 NC |
938 | } |
939 | ||
43cd72b9 BW |
940 | static unsigned |
941 | Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) | |
e0001a05 | 942 | { |
43cd72b9 BW |
943 | unsigned tie_t = 0; |
944 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); | |
945 | return tie_t; | |
e0001a05 NC |
946 | } |
947 | ||
43cd72b9 BW |
948 | static void |
949 | Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 950 | { |
43cd72b9 BW |
951 | uint32 tie_t; |
952 | tie_t = (val << 28) >> 28; | |
953 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); | |
e0001a05 NC |
954 | } |
955 | ||
43cd72b9 BW |
956 | static unsigned |
957 | Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) | |
e0001a05 | 958 | { |
43cd72b9 BW |
959 | unsigned tie_t = 0; |
960 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); | |
961 | return tie_t; | |
e0001a05 NC |
962 | } |
963 | ||
43cd72b9 BW |
964 | static void |
965 | Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 966 | { |
43cd72b9 BW |
967 | uint32 tie_t; |
968 | tie_t = (val << 28) >> 28; | |
969 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); | |
e0001a05 NC |
970 | } |
971 | ||
43cd72b9 BW |
972 | static unsigned |
973 | Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) | |
974 | { | |
975 | unsigned tie_t = 0; | |
976 | tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); | |
977 | return tie_t; | |
978 | } | |
e0001a05 | 979 | |
43cd72b9 BW |
980 | static void |
981 | Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 982 | { |
43cd72b9 BW |
983 | uint32 tie_t; |
984 | tie_t = (val << 30) >> 30; | |
985 | insn[0] = (insn[0] & ~0x300) | (tie_t << 8); | |
e0001a05 NC |
986 | } |
987 | ||
43cd72b9 BW |
988 | static unsigned |
989 | Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) | |
e0001a05 | 990 | { |
43cd72b9 BW |
991 | unsigned tie_t = 0; |
992 | tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); | |
993 | return tie_t; | |
e0001a05 NC |
994 | } |
995 | ||
43cd72b9 BW |
996 | static void |
997 | Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 998 | { |
43cd72b9 BW |
999 | uint32 tie_t; |
1000 | tie_t = (val << 30) >> 30; | |
1001 | insn[0] = (insn[0] & ~0x300) | (tie_t << 8); | |
e0001a05 NC |
1002 | } |
1003 | ||
43cd72b9 BW |
1004 | static unsigned |
1005 | Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) | |
e0001a05 | 1006 | { |
43cd72b9 BW |
1007 | unsigned tie_t = 0; |
1008 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); | |
1009 | return tie_t; | |
e0001a05 NC |
1010 | } |
1011 | ||
43cd72b9 BW |
1012 | static void |
1013 | Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 1014 | { |
43cd72b9 BW |
1015 | uint32 tie_t; |
1016 | tie_t = (val << 28) >> 28; | |
1017 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); | |
e0001a05 NC |
1018 | } |
1019 | ||
43cd72b9 BW |
1020 | static unsigned |
1021 | Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) | |
e0001a05 | 1022 | { |
43cd72b9 BW |
1023 | unsigned tie_t = 0; |
1024 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); | |
1025 | return tie_t; | |
e0001a05 NC |
1026 | } |
1027 | ||
43cd72b9 BW |
1028 | static void |
1029 | Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 1030 | { |
43cd72b9 BW |
1031 | uint32 tie_t; |
1032 | tie_t = (val << 28) >> 28; | |
1033 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); | |
e0001a05 NC |
1034 | } |
1035 | ||
43cd72b9 BW |
1036 | static unsigned |
1037 | Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) | |
e0001a05 | 1038 | { |
43cd72b9 BW |
1039 | unsigned tie_t = 0; |
1040 | tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); | |
1041 | return tie_t; | |
e0001a05 NC |
1042 | } |
1043 | ||
43cd72b9 BW |
1044 | static void |
1045 | Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 1046 | { |
43cd72b9 BW |
1047 | uint32 tie_t; |
1048 | tie_t = (val << 29) >> 29; | |
1049 | insn[0] = (insn[0] & ~0x700) | (tie_t << 8); | |
e0001a05 NC |
1050 | } |
1051 | ||
43cd72b9 BW |
1052 | static unsigned |
1053 | Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) | |
e0001a05 | 1054 | { |
43cd72b9 BW |
1055 | unsigned tie_t = 0; |
1056 | tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); | |
1057 | return tie_t; | |
e0001a05 NC |
1058 | } |
1059 | ||
43cd72b9 BW |
1060 | static void |
1061 | Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 1062 | { |
43cd72b9 BW |
1063 | uint32 tie_t; |
1064 | tie_t = (val << 29) >> 29; | |
1065 | insn[0] = (insn[0] & ~0x700) | (tie_t << 8); | |
e0001a05 NC |
1066 | } |
1067 | ||
43cd72b9 BW |
1068 | static unsigned |
1069 | Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) | |
e0001a05 | 1070 | { |
43cd72b9 BW |
1071 | unsigned tie_t = 0; |
1072 | tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); | |
1073 | return tie_t; | |
e0001a05 NC |
1074 | } |
1075 | ||
43cd72b9 BW |
1076 | static void |
1077 | Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 1078 | { |
43cd72b9 BW |
1079 | uint32 tie_t; |
1080 | tie_t = (val << 31) >> 31; | |
1081 | insn[0] = (insn[0] & ~0x400) | (tie_t << 10); | |
e0001a05 NC |
1082 | } |
1083 | ||
43cd72b9 BW |
1084 | static unsigned |
1085 | Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) | |
e0001a05 | 1086 | { |
43cd72b9 BW |
1087 | unsigned tie_t = 0; |
1088 | tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); | |
1089 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); | |
1090 | return tie_t; | |
e0001a05 NC |
1091 | } |
1092 | ||
43cd72b9 BW |
1093 | static void |
1094 | Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 1095 | { |
43cd72b9 BW |
1096 | uint32 tie_t; |
1097 | tie_t = (val << 28) >> 28; | |
1098 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); | |
1099 | tie_t = (val << 26) >> 30; | |
1100 | insn[0] = (insn[0] & ~0x300) | (tie_t << 8); | |
e0001a05 NC |
1101 | } |
1102 | ||
43cd72b9 BW |
1103 | static unsigned |
1104 | Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) | |
e0001a05 | 1105 | { |
43cd72b9 BW |
1106 | unsigned tie_t = 0; |
1107 | tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); | |
1108 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); | |
1109 | return tie_t; | |
e0001a05 NC |
1110 | } |
1111 | ||
43cd72b9 BW |
1112 | static void |
1113 | Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 1114 | { |
43cd72b9 BW |
1115 | uint32 tie_t; |
1116 | tie_t = (val << 28) >> 28; | |
1117 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); | |
1118 | tie_t = (val << 26) >> 30; | |
1119 | insn[0] = (insn[0] & ~0x300) | (tie_t << 8); | |
e0001a05 NC |
1120 | } |
1121 | ||
43cd72b9 BW |
1122 | static unsigned |
1123 | Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) | |
e0001a05 | 1124 | { |
43cd72b9 BW |
1125 | unsigned tie_t = 0; |
1126 | tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); | |
1127 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); | |
1128 | return tie_t; | |
e0001a05 NC |
1129 | } |
1130 | ||
43cd72b9 BW |
1131 | static void |
1132 | Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 1133 | { |
43cd72b9 BW |
1134 | uint32 tie_t; |
1135 | tie_t = (val << 28) >> 28; | |
1136 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); | |
1137 | tie_t = (val << 25) >> 29; | |
1138 | insn[0] = (insn[0] & ~0x700) | (tie_t << 8); | |
e0001a05 NC |
1139 | } |
1140 | ||
43cd72b9 BW |
1141 | static unsigned |
1142 | Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) | |
e0001a05 | 1143 | { |
43cd72b9 BW |
1144 | unsigned tie_t = 0; |
1145 | tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); | |
1146 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); | |
1147 | return tie_t; | |
e0001a05 NC |
1148 | } |
1149 | ||
43cd72b9 BW |
1150 | static void |
1151 | Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) | |
e0001a05 | 1152 | { |
43cd72b9 BW |
1153 | uint32 tie_t; |
1154 | tie_t = (val << 28) >> 28; | |
1155 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); | |
1156 | tie_t = (val << 25) >> 29; | |
1157 | insn[0] = (insn[0] & ~0x700) | (tie_t << 8); | |
e0001a05 NC |
1158 | } |
1159 | ||
43cd72b9 BW |
1160 | static void |
1161 | Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, | |
1162 | uint32 val ATTRIBUTE_UNUSED) | |
e0001a05 | 1163 | { |
43cd72b9 | 1164 | /* Do nothing. */ |
e0001a05 NC |
1165 | } |
1166 | ||
43cd72b9 BW |
1167 | static unsigned |
1168 | Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) | |
e0001a05 | 1169 | { |
43cd72b9 | 1170 | return 0; |
e0001a05 NC |
1171 | } |
1172 | ||
43cd72b9 BW |
1173 | static unsigned |
1174 | Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) | |
e0001a05 | 1175 | { |
43cd72b9 | 1176 | return 4; |
e0001a05 NC |
1177 | } |
1178 | ||
43cd72b9 BW |
1179 | static unsigned |
1180 | Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) | |
e0001a05 | 1181 | { |
43cd72b9 | 1182 | return 8; |
e0001a05 NC |
1183 | } |
1184 | ||
43cd72b9 BW |
1185 | static unsigned |
1186 | Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) | |
e0001a05 | 1187 | { |
43cd72b9 | 1188 | return 12; |
e0001a05 NC |
1189 | } |
1190 | ||
43cd72b9 BW |
1191 | \f |
1192 | /* Functional units. */ | |
1193 | ||
1194 | static xtensa_funcUnit_internal funcUnits[] = { | |
1195 | ||
1196 | }; | |
1197 | ||
1198 | \f | |
1199 | /* Register files. */ | |
1200 | ||
1201 | static xtensa_regfile_internal regfiles[] = { | |
1202 | { "AR", "a", 0, 32, 64 } | |
1203 | }; | |
1204 | ||
1205 | \f | |
1206 | /* Interfaces. */ | |
1207 | ||
1208 | static xtensa_interface_internal interfaces[] = { | |
1209 | ||
1210 | }; | |
1211 | ||
1212 | \f | |
1213 | /* Constant tables. */ | |
1214 | ||
1215 | /* constant table ai4c */ | |
1216 | static const unsigned CONST_TBL_ai4c_0[] = { | |
1217 | 0xffffffff, | |
1218 | 0x1, | |
1219 | 0x2, | |
1220 | 0x3, | |
1221 | 0x4, | |
1222 | 0x5, | |
1223 | 0x6, | |
1224 | 0x7, | |
1225 | 0x8, | |
1226 | 0x9, | |
1227 | 0xa, | |
1228 | 0xb, | |
1229 | 0xc, | |
1230 | 0xd, | |
1231 | 0xe, | |
1232 | 0xf, | |
1233 | 0 | |
1234 | }; | |
1235 | ||
1236 | /* constant table b4c */ | |
1237 | static const unsigned CONST_TBL_b4c_0[] = { | |
1238 | 0xffffffff, | |
1239 | 0x1, | |
1240 | 0x2, | |
1241 | 0x3, | |
1242 | 0x4, | |
1243 | 0x5, | |
1244 | 0x6, | |
1245 | 0x7, | |
1246 | 0x8, | |
1247 | 0xa, | |
1248 | 0xc, | |
1249 | 0x10, | |
1250 | 0x20, | |
1251 | 0x40, | |
1252 | 0x80, | |
1253 | 0x100, | |
1254 | 0 | |
1255 | }; | |
1256 | ||
1257 | /* constant table b4cu */ | |
1258 | static const unsigned CONST_TBL_b4cu_0[] = { | |
1259 | 0x8000, | |
1260 | 0x10000, | |
1261 | 0x2, | |
1262 | 0x3, | |
1263 | 0x4, | |
1264 | 0x5, | |
1265 | 0x6, | |
1266 | 0x7, | |
1267 | 0x8, | |
1268 | 0xa, | |
1269 | 0xc, | |
1270 | 0x10, | |
1271 | 0x20, | |
1272 | 0x40, | |
1273 | 0x80, | |
1274 | 0x100, | |
1275 | 0 | |
1276 | }; | |
1277 | ||
1278 | \f | |
1279 | /* Instruction operands. */ | |
1280 | ||
1281 | static int | |
1282 | Operand_soffsetx4_decode (uint32 *valp) | |
e0001a05 | 1283 | { |
43cd72b9 BW |
1284 | unsigned soffsetx4_0, offset_0; |
1285 | offset_0 = *valp & 0x3ffff; | |
1286 | soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); | |
1287 | *valp = soffsetx4_0; | |
1288 | return 0; | |
e0001a05 NC |
1289 | } |
1290 | ||
43cd72b9 BW |
1291 | static int |
1292 | Operand_soffsetx4_encode (uint32 *valp) | |
e0001a05 | 1293 | { |
43cd72b9 BW |
1294 | unsigned offset_0, soffsetx4_0; |
1295 | soffsetx4_0 = *valp; | |
1296 | offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; | |
1297 | *valp = offset_0; | |
1298 | return 0; | |
e0001a05 NC |
1299 | } |
1300 | ||
43cd72b9 BW |
1301 | static int |
1302 | Operand_soffsetx4_ator (uint32 *valp, uint32 pc) | |
e0001a05 | 1303 | { |
43cd72b9 BW |
1304 | *valp -= (pc & ~0x3); |
1305 | return 0; | |
e0001a05 NC |
1306 | } |
1307 | ||
43cd72b9 BW |
1308 | static int |
1309 | Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) | |
e0001a05 | 1310 | { |
43cd72b9 BW |
1311 | *valp += (pc & ~0x3); |
1312 | return 0; | |
e0001a05 NC |
1313 | } |
1314 | ||
43cd72b9 BW |
1315 | static int |
1316 | Operand_uimm12x8_decode (uint32 *valp) | |
e0001a05 | 1317 | { |
43cd72b9 BW |
1318 | unsigned uimm12x8_0, imm12_0; |
1319 | imm12_0 = *valp & 0xfff; | |
1320 | uimm12x8_0 = imm12_0 << 3; | |
1321 | *valp = uimm12x8_0; | |
1322 | return 0; | |
e0001a05 NC |
1323 | } |
1324 | ||
43cd72b9 BW |
1325 | static int |
1326 | Operand_uimm12x8_encode (uint32 *valp) | |
e0001a05 | 1327 | { |
43cd72b9 BW |
1328 | unsigned imm12_0, uimm12x8_0; |
1329 | uimm12x8_0 = *valp; | |
1330 | imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); | |
1331 | *valp = imm12_0; | |
1332 | return 0; | |
e0001a05 NC |
1333 | } |
1334 | ||
43cd72b9 BW |
1335 | static int |
1336 | Operand_simm4_decode (uint32 *valp) | |
e0001a05 | 1337 | { |
43cd72b9 BW |
1338 | unsigned simm4_0, mn_0; |
1339 | mn_0 = *valp & 0xf; | |
1340 | simm4_0 = ((int) mn_0 << 28) >> 28; | |
1341 | *valp = simm4_0; | |
1342 | return 0; | |
e0001a05 NC |
1343 | } |
1344 | ||
43cd72b9 BW |
1345 | static int |
1346 | Operand_simm4_encode (uint32 *valp) | |
e0001a05 | 1347 | { |
43cd72b9 BW |
1348 | unsigned mn_0, simm4_0; |
1349 | simm4_0 = *valp; | |
1350 | mn_0 = (simm4_0 & 0xf); | |
1351 | *valp = mn_0; | |
1352 | return 0; | |
e0001a05 NC |
1353 | } |
1354 | ||
43cd72b9 BW |
1355 | static int |
1356 | Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) | |
e0001a05 | 1357 | { |
43cd72b9 | 1358 | return 0; |
e0001a05 NC |
1359 | } |
1360 | ||
43cd72b9 BW |
1361 | static int |
1362 | Operand_arr_encode (uint32 *valp) | |
e0001a05 | 1363 | { |
43cd72b9 BW |
1364 | int error; |
1365 | error = (*valp & ~0xf) != 0; | |
1366 | return error; | |
e0001a05 NC |
1367 | } |
1368 | ||
43cd72b9 BW |
1369 | static int |
1370 | Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) | |
e0001a05 | 1371 | { |
43cd72b9 | 1372 | return 0; |
e0001a05 NC |
1373 | } |
1374 | ||
43cd72b9 BW |
1375 | static int |
1376 | Operand_ars_encode (uint32 *valp) | |
e0001a05 | 1377 | { |
43cd72b9 BW |
1378 | int error; |
1379 | error = (*valp & ~0xf) != 0; | |
1380 | return error; | |
e0001a05 NC |
1381 | } |
1382 | ||
43cd72b9 BW |
1383 | static int |
1384 | Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) | |
1385 | { | |
1386 | return 0; | |
1387 | } | |
e0001a05 | 1388 | |
43cd72b9 BW |
1389 | static int |
1390 | Operand_art_encode (uint32 *valp) | |
e0001a05 | 1391 | { |
43cd72b9 BW |
1392 | int error; |
1393 | error = (*valp & ~0xf) != 0; | |
1394 | return error; | |
e0001a05 NC |
1395 | } |
1396 | ||
43cd72b9 BW |
1397 | static int |
1398 | Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) | |
e0001a05 | 1399 | { |
43cd72b9 | 1400 | return 0; |
e0001a05 NC |
1401 | } |
1402 | ||
43cd72b9 BW |
1403 | static int |
1404 | Operand_ar0_encode (uint32 *valp) | |
e0001a05 | 1405 | { |
43cd72b9 BW |
1406 | int error; |
1407 | error = (*valp & ~0x3f) != 0; | |
1408 | return error; | |
e0001a05 NC |
1409 | } |
1410 | ||
43cd72b9 BW |
1411 | static int |
1412 | Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) | |
e0001a05 | 1413 | { |
43cd72b9 | 1414 | return 0; |
e0001a05 NC |
1415 | } |
1416 | ||
43cd72b9 BW |
1417 | static int |
1418 | Operand_ar4_encode (uint32 *valp) | |
1419 | { | |
1420 | int error; | |
1421 | error = (*valp & ~0x3f) != 0; | |
1422 | return error; | |
e0001a05 NC |
1423 | } |
1424 | ||
43cd72b9 BW |
1425 | static int |
1426 | Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) | |
e0001a05 | 1427 | { |
43cd72b9 | 1428 | return 0; |
e0001a05 NC |
1429 | } |
1430 | ||
43cd72b9 BW |
1431 | static int |
1432 | Operand_ar8_encode (uint32 *valp) | |
e0001a05 | 1433 | { |
43cd72b9 BW |
1434 | int error; |
1435 | error = (*valp & ~0x3f) != 0; | |
1436 | return error; | |
e0001a05 NC |
1437 | } |
1438 | ||
43cd72b9 BW |
1439 | static int |
1440 | Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) | |
e0001a05 | 1441 | { |
43cd72b9 | 1442 | return 0; |
e0001a05 NC |
1443 | } |
1444 | ||
43cd72b9 BW |
1445 | static int |
1446 | Operand_ar12_encode (uint32 *valp) | |
e0001a05 | 1447 | { |
43cd72b9 BW |
1448 | int error; |
1449 | error = (*valp & ~0x3f) != 0; | |
1450 | return error; | |
e0001a05 NC |
1451 | } |
1452 | ||
43cd72b9 BW |
1453 | static int |
1454 | Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) | |
1455 | { | |
1456 | return 0; | |
1457 | } | |
e0001a05 | 1458 | |
43cd72b9 BW |
1459 | static int |
1460 | Operand_ars_entry_encode (uint32 *valp) | |
e0001a05 | 1461 | { |
43cd72b9 BW |
1462 | int error; |
1463 | error = (*valp & ~0x3f) != 0; | |
1464 | return error; | |
e0001a05 NC |
1465 | } |
1466 | ||
43cd72b9 BW |
1467 | static int |
1468 | Operand_immrx4_decode (uint32 *valp) | |
e0001a05 | 1469 | { |
43cd72b9 BW |
1470 | unsigned immrx4_0, r_0; |
1471 | r_0 = *valp & 0xf; | |
1472 | immrx4_0 = ((((0xfffffff)) << 4) | r_0) << 2; | |
1473 | *valp = immrx4_0; | |
1474 | return 0; | |
e0001a05 NC |
1475 | } |
1476 | ||
43cd72b9 BW |
1477 | static int |
1478 | Operand_immrx4_encode (uint32 *valp) | |
e0001a05 | 1479 | { |
43cd72b9 BW |
1480 | unsigned r_0, immrx4_0; |
1481 | immrx4_0 = *valp; | |
1482 | r_0 = ((immrx4_0 >> 2) & 0xf); | |
1483 | *valp = r_0; | |
1484 | return 0; | |
e0001a05 NC |
1485 | } |
1486 | ||
43cd72b9 BW |
1487 | static int |
1488 | Operand_lsi4x4_decode (uint32 *valp) | |
e0001a05 | 1489 | { |
43cd72b9 BW |
1490 | unsigned lsi4x4_0, r_0; |
1491 | r_0 = *valp & 0xf; | |
1492 | lsi4x4_0 = r_0 << 2; | |
1493 | *valp = lsi4x4_0; | |
1494 | return 0; | |
e0001a05 NC |
1495 | } |
1496 | ||
43cd72b9 BW |
1497 | static int |
1498 | Operand_lsi4x4_encode (uint32 *valp) | |
e0001a05 | 1499 | { |
43cd72b9 BW |
1500 | unsigned r_0, lsi4x4_0; |
1501 | lsi4x4_0 = *valp; | |
1502 | r_0 = ((lsi4x4_0 >> 2) & 0xf); | |
1503 | *valp = r_0; | |
1504 | return 0; | |
e0001a05 NC |
1505 | } |
1506 | ||
43cd72b9 BW |
1507 | static int |
1508 | Operand_simm7_decode (uint32 *valp) | |
e0001a05 | 1509 | { |
43cd72b9 BW |
1510 | unsigned simm7_0, imm7_0; |
1511 | imm7_0 = *valp & 0x7f; | |
1512 | simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; | |
1513 | *valp = simm7_0; | |
1514 | return 0; | |
e0001a05 NC |
1515 | } |
1516 | ||
43cd72b9 BW |
1517 | static int |
1518 | Operand_simm7_encode (uint32 *valp) | |
e0001a05 | 1519 | { |
43cd72b9 BW |
1520 | unsigned imm7_0, simm7_0; |
1521 | simm7_0 = *valp; | |
1522 | imm7_0 = (simm7_0 & 0x7f); | |
1523 | *valp = imm7_0; | |
1524 | return 0; | |
e0001a05 NC |
1525 | } |
1526 | ||
43cd72b9 BW |
1527 | static int |
1528 | Operand_uimm6_decode (uint32 *valp) | |
e0001a05 | 1529 | { |
43cd72b9 BW |
1530 | unsigned uimm6_0, imm6_0; |
1531 | imm6_0 = *valp & 0x3f; | |
1532 | uimm6_0 = 0x4 + ((((0)) << 6) | imm6_0); | |
1533 | *valp = uimm6_0; | |
1534 | return 0; | |
e0001a05 NC |
1535 | } |
1536 | ||
43cd72b9 BW |
1537 | static int |
1538 | Operand_uimm6_encode (uint32 *valp) | |
e0001a05 | 1539 | { |
43cd72b9 BW |
1540 | unsigned imm6_0, uimm6_0; |
1541 | uimm6_0 = *valp; | |
1542 | imm6_0 = (uimm6_0 - 0x4) & 0x3f; | |
1543 | *valp = imm6_0; | |
1544 | return 0; | |
e0001a05 NC |
1545 | } |
1546 | ||
43cd72b9 BW |
1547 | static int |
1548 | Operand_uimm6_ator (uint32 *valp, uint32 pc) | |
e0001a05 | 1549 | { |
43cd72b9 BW |
1550 | *valp -= pc; |
1551 | return 0; | |
e0001a05 NC |
1552 | } |
1553 | ||
43cd72b9 BW |
1554 | static int |
1555 | Operand_uimm6_rtoa (uint32 *valp, uint32 pc) | |
e0001a05 | 1556 | { |
43cd72b9 BW |
1557 | *valp += pc; |
1558 | return 0; | |
e0001a05 NC |
1559 | } |
1560 | ||
43cd72b9 BW |
1561 | static int |
1562 | Operand_ai4const_decode (uint32 *valp) | |
e0001a05 | 1563 | { |
43cd72b9 BW |
1564 | unsigned ai4const_0, t_0; |
1565 | t_0 = *valp & 0xf; | |
1566 | ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; | |
1567 | *valp = ai4const_0; | |
1568 | return 0; | |
e0001a05 NC |
1569 | } |
1570 | ||
43cd72b9 BW |
1571 | static int |
1572 | Operand_ai4const_encode (uint32 *valp) | |
e0001a05 | 1573 | { |
43cd72b9 BW |
1574 | unsigned t_0, ai4const_0; |
1575 | ai4const_0 = *valp; | |
1576 | switch (ai4const_0) | |
1577 | { | |
1578 | case 0xffffffff: t_0 = 0; break; | |
1579 | case 0x1: t_0 = 0x1; break; | |
1580 | case 0x2: t_0 = 0x2; break; | |
1581 | case 0x3: t_0 = 0x3; break; | |
1582 | case 0x4: t_0 = 0x4; break; | |
1583 | case 0x5: t_0 = 0x5; break; | |
1584 | case 0x6: t_0 = 0x6; break; | |
1585 | case 0x7: t_0 = 0x7; break; | |
1586 | case 0x8: t_0 = 0x8; break; | |
1587 | case 0x9: t_0 = 0x9; break; | |
1588 | case 0xa: t_0 = 0xa; break; | |
1589 | case 0xb: t_0 = 0xb; break; | |
1590 | case 0xc: t_0 = 0xc; break; | |
1591 | case 0xd: t_0 = 0xd; break; | |
1592 | case 0xe: t_0 = 0xe; break; | |
1593 | default: t_0 = 0xf; break; | |
1594 | } | |
1595 | *valp = t_0; | |
1596 | return 0; | |
e0001a05 NC |
1597 | } |
1598 | ||
43cd72b9 BW |
1599 | static int |
1600 | Operand_b4const_decode (uint32 *valp) | |
e0001a05 | 1601 | { |
43cd72b9 BW |
1602 | unsigned b4const_0, r_0; |
1603 | r_0 = *valp & 0xf; | |
1604 | b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; | |
1605 | *valp = b4const_0; | |
1606 | return 0; | |
e0001a05 NC |
1607 | } |
1608 | ||
43cd72b9 BW |
1609 | static int |
1610 | Operand_b4const_encode (uint32 *valp) | |
e0001a05 | 1611 | { |
43cd72b9 BW |
1612 | unsigned r_0, b4const_0; |
1613 | b4const_0 = *valp; | |
1614 | switch (b4const_0) | |
1615 | { | |
1616 | case 0xffffffff: r_0 = 0; break; | |
1617 | case 0x1: r_0 = 0x1; break; | |
1618 | case 0x2: r_0 = 0x2; break; | |
1619 | case 0x3: r_0 = 0x3; break; | |
1620 | case 0x4: r_0 = 0x4; break; | |
1621 | case 0x5: r_0 = 0x5; break; | |
1622 | case 0x6: r_0 = 0x6; break; | |
1623 | case 0x7: r_0 = 0x7; break; | |
1624 | case 0x8: r_0 = 0x8; break; | |
1625 | case 0xa: r_0 = 0x9; break; | |
1626 | case 0xc: r_0 = 0xa; break; | |
1627 | case 0x10: r_0 = 0xb; break; | |
1628 | case 0x20: r_0 = 0xc; break; | |
1629 | case 0x40: r_0 = 0xd; break; | |
1630 | case 0x80: r_0 = 0xe; break; | |
1631 | default: r_0 = 0xf; break; | |
1632 | } | |
1633 | *valp = r_0; | |
1634 | return 0; | |
e0001a05 NC |
1635 | } |
1636 | ||
43cd72b9 BW |
1637 | static int |
1638 | Operand_b4constu_decode (uint32 *valp) | |
e0001a05 | 1639 | { |
43cd72b9 BW |
1640 | unsigned b4constu_0, r_0; |
1641 | r_0 = *valp & 0xf; | |
1642 | b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; | |
1643 | *valp = b4constu_0; | |
1644 | return 0; | |
e0001a05 NC |
1645 | } |
1646 | ||
43cd72b9 BW |
1647 | static int |
1648 | Operand_b4constu_encode (uint32 *valp) | |
e0001a05 | 1649 | { |
43cd72b9 BW |
1650 | unsigned r_0, b4constu_0; |
1651 | b4constu_0 = *valp; | |
1652 | switch (b4constu_0) | |
1653 | { | |
1654 | case 0x8000: r_0 = 0; break; | |
1655 | case 0x10000: r_0 = 0x1; break; | |
1656 | case 0x2: r_0 = 0x2; break; | |
1657 | case 0x3: r_0 = 0x3; break; | |
1658 | case 0x4: r_0 = 0x4; break; | |
1659 | case 0x5: r_0 = 0x5; break; | |
1660 | case 0x6: r_0 = 0x6; break; | |
1661 | case 0x7: r_0 = 0x7; break; | |
1662 | case 0x8: r_0 = 0x8; break; | |
1663 | case 0xa: r_0 = 0x9; break; | |
1664 | case 0xc: r_0 = 0xa; break; | |
1665 | case 0x10: r_0 = 0xb; break; | |
1666 | case 0x20: r_0 = 0xc; break; | |
1667 | case 0x40: r_0 = 0xd; break; | |
1668 | case 0x80: r_0 = 0xe; break; | |
1669 | default: r_0 = 0xf; break; | |
1670 | } | |
1671 | *valp = r_0; | |
1672 | return 0; | |
e0001a05 NC |
1673 | } |
1674 | ||
43cd72b9 BW |
1675 | static int |
1676 | Operand_uimm8_decode (uint32 *valp) | |
e0001a05 | 1677 | { |
43cd72b9 BW |
1678 | unsigned uimm8_0, imm8_0; |
1679 | imm8_0 = *valp & 0xff; | |
1680 | uimm8_0 = imm8_0; | |
1681 | *valp = uimm8_0; | |
1682 | return 0; | |
e0001a05 NC |
1683 | } |
1684 | ||
43cd72b9 BW |
1685 | static int |
1686 | Operand_uimm8_encode (uint32 *valp) | |
e0001a05 | 1687 | { |
43cd72b9 BW |
1688 | unsigned imm8_0, uimm8_0; |
1689 | uimm8_0 = *valp; | |
1690 | imm8_0 = (uimm8_0 & 0xff); | |
1691 | *valp = imm8_0; | |
1692 | return 0; | |
e0001a05 NC |
1693 | } |
1694 | ||
43cd72b9 BW |
1695 | static int |
1696 | Operand_uimm8x2_decode (uint32 *valp) | |
e0001a05 | 1697 | { |
43cd72b9 BW |
1698 | unsigned uimm8x2_0, imm8_0; |
1699 | imm8_0 = *valp & 0xff; | |
1700 | uimm8x2_0 = imm8_0 << 1; | |
1701 | *valp = uimm8x2_0; | |
1702 | return 0; | |
e0001a05 NC |
1703 | } |
1704 | ||
43cd72b9 BW |
1705 | static int |
1706 | Operand_uimm8x2_encode (uint32 *valp) | |
e0001a05 | 1707 | { |
43cd72b9 BW |
1708 | unsigned imm8_0, uimm8x2_0; |
1709 | uimm8x2_0 = *valp; | |
1710 | imm8_0 = ((uimm8x2_0 >> 1) & 0xff); | |
1711 | *valp = imm8_0; | |
1712 | return 0; | |
e0001a05 NC |
1713 | } |
1714 | ||
43cd72b9 BW |
1715 | static int |
1716 | Operand_uimm8x4_decode (uint32 *valp) | |
e0001a05 | 1717 | { |
43cd72b9 BW |
1718 | unsigned uimm8x4_0, imm8_0; |
1719 | imm8_0 = *valp & 0xff; | |
1720 | uimm8x4_0 = imm8_0 << 2; | |
1721 | *valp = uimm8x4_0; | |
1722 | return 0; | |
e0001a05 NC |
1723 | } |
1724 | ||
43cd72b9 BW |
1725 | static int |
1726 | Operand_uimm8x4_encode (uint32 *valp) | |
e0001a05 | 1727 | { |
43cd72b9 BW |
1728 | unsigned imm8_0, uimm8x4_0; |
1729 | uimm8x4_0 = *valp; | |
1730 | imm8_0 = ((uimm8x4_0 >> 2) & 0xff); | |
1731 | *valp = imm8_0; | |
1732 | return 0; | |
e0001a05 NC |
1733 | } |
1734 | ||
43cd72b9 BW |
1735 | static int |
1736 | Operand_uimm4x16_decode (uint32 *valp) | |
e0001a05 | 1737 | { |
43cd72b9 BW |
1738 | unsigned uimm4x16_0, op2_0; |
1739 | op2_0 = *valp & 0xf; | |
1740 | uimm4x16_0 = op2_0 << 4; | |
1741 | *valp = uimm4x16_0; | |
1742 | return 0; | |
e0001a05 NC |
1743 | } |
1744 | ||
43cd72b9 BW |
1745 | static int |
1746 | Operand_uimm4x16_encode (uint32 *valp) | |
e0001a05 | 1747 | { |
43cd72b9 BW |
1748 | unsigned op2_0, uimm4x16_0; |
1749 | uimm4x16_0 = *valp; | |
1750 | op2_0 = ((uimm4x16_0 >> 4) & 0xf); | |
1751 | *valp = op2_0; | |
1752 | return 0; | |
e0001a05 NC |
1753 | } |
1754 | ||
43cd72b9 BW |
1755 | static int |
1756 | Operand_simm8_decode (uint32 *valp) | |
e0001a05 | 1757 | { |
43cd72b9 BW |
1758 | unsigned simm8_0, imm8_0; |
1759 | imm8_0 = *valp & 0xff; | |
1760 | simm8_0 = ((int) imm8_0 << 24) >> 24; | |
1761 | *valp = simm8_0; | |
1762 | return 0; | |
e0001a05 NC |
1763 | } |
1764 | ||
43cd72b9 BW |
1765 | static int |
1766 | Operand_simm8_encode (uint32 *valp) | |
e0001a05 | 1767 | { |
43cd72b9 BW |
1768 | unsigned imm8_0, simm8_0; |
1769 | simm8_0 = *valp; | |
1770 | imm8_0 = (simm8_0 & 0xff); | |
1771 | *valp = imm8_0; | |
1772 | return 0; | |
e0001a05 NC |
1773 | } |
1774 | ||
43cd72b9 BW |
1775 | static int |
1776 | Operand_simm8x256_decode (uint32 *valp) | |
e0001a05 | 1777 | { |
43cd72b9 BW |
1778 | unsigned simm8x256_0, imm8_0; |
1779 | imm8_0 = *valp & 0xff; | |
1780 | simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; | |
1781 | *valp = simm8x256_0; | |
1782 | return 0; | |
e0001a05 NC |
1783 | } |
1784 | ||
43cd72b9 BW |
1785 | static int |
1786 | Operand_simm8x256_encode (uint32 *valp) | |
e0001a05 | 1787 | { |
43cd72b9 BW |
1788 | unsigned imm8_0, simm8x256_0; |
1789 | simm8x256_0 = *valp; | |
1790 | imm8_0 = ((simm8x256_0 >> 8) & 0xff); | |
1791 | *valp = imm8_0; | |
1792 | return 0; | |
e0001a05 NC |
1793 | } |
1794 | ||
43cd72b9 BW |
1795 | static int |
1796 | Operand_simm12b_decode (uint32 *valp) | |
e0001a05 | 1797 | { |
43cd72b9 BW |
1798 | unsigned simm12b_0, imm12b_0; |
1799 | imm12b_0 = *valp & 0xfff; | |
1800 | simm12b_0 = ((int) imm12b_0 << 20) >> 20; | |
1801 | *valp = simm12b_0; | |
1802 | return 0; | |
e0001a05 NC |
1803 | } |
1804 | ||
43cd72b9 BW |
1805 | static int |
1806 | Operand_simm12b_encode (uint32 *valp) | |
e0001a05 | 1807 | { |
43cd72b9 BW |
1808 | unsigned imm12b_0, simm12b_0; |
1809 | simm12b_0 = *valp; | |
1810 | imm12b_0 = (simm12b_0 & 0xfff); | |
1811 | *valp = imm12b_0; | |
1812 | return 0; | |
e0001a05 NC |
1813 | } |
1814 | ||
43cd72b9 BW |
1815 | static int |
1816 | Operand_msalp32_decode (uint32 *valp) | |
e0001a05 | 1817 | { |
43cd72b9 BW |
1818 | unsigned msalp32_0, sal_0; |
1819 | sal_0 = *valp & 0x1f; | |
1820 | msalp32_0 = 0x20 - sal_0; | |
1821 | *valp = msalp32_0; | |
1822 | return 0; | |
e0001a05 NC |
1823 | } |
1824 | ||
43cd72b9 BW |
1825 | static int |
1826 | Operand_msalp32_encode (uint32 *valp) | |
e0001a05 | 1827 | { |
43cd72b9 BW |
1828 | unsigned sal_0, msalp32_0; |
1829 | msalp32_0 = *valp; | |
1830 | sal_0 = (0x20 - msalp32_0) & 0x1f; | |
1831 | *valp = sal_0; | |
1832 | return 0; | |
e0001a05 NC |
1833 | } |
1834 | ||
43cd72b9 BW |
1835 | static int |
1836 | Operand_op2p1_decode (uint32 *valp) | |
e0001a05 | 1837 | { |
43cd72b9 BW |
1838 | unsigned op2p1_0, op2_0; |
1839 | op2_0 = *valp & 0xf; | |
1840 | op2p1_0 = op2_0 + 0x1; | |
1841 | *valp = op2p1_0; | |
1842 | return 0; | |
e0001a05 NC |
1843 | } |
1844 | ||
43cd72b9 BW |
1845 | static int |
1846 | Operand_op2p1_encode (uint32 *valp) | |
e0001a05 | 1847 | { |
43cd72b9 BW |
1848 | unsigned op2_0, op2p1_0; |
1849 | op2p1_0 = *valp; | |
1850 | op2_0 = (op2p1_0 - 0x1) & 0xf; | |
1851 | *valp = op2_0; | |
1852 | return 0; | |
e0001a05 NC |
1853 | } |
1854 | ||
43cd72b9 BW |
1855 | static int |
1856 | Operand_label8_decode (uint32 *valp) | |
e0001a05 | 1857 | { |
43cd72b9 BW |
1858 | unsigned label8_0, imm8_0; |
1859 | imm8_0 = *valp & 0xff; | |
1860 | label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); | |
1861 | *valp = label8_0; | |
1862 | return 0; | |
e0001a05 NC |
1863 | } |
1864 | ||
43cd72b9 BW |
1865 | static int |
1866 | Operand_label8_encode (uint32 *valp) | |
e0001a05 | 1867 | { |
43cd72b9 BW |
1868 | unsigned imm8_0, label8_0; |
1869 | label8_0 = *valp; | |
1870 | imm8_0 = (label8_0 - 0x4) & 0xff; | |
1871 | *valp = imm8_0; | |
1872 | return 0; | |
e0001a05 NC |
1873 | } |
1874 | ||
43cd72b9 BW |
1875 | static int |
1876 | Operand_label8_ator (uint32 *valp, uint32 pc) | |
e0001a05 | 1877 | { |
43cd72b9 BW |
1878 | *valp -= pc; |
1879 | return 0; | |
e0001a05 NC |
1880 | } |
1881 | ||
43cd72b9 BW |
1882 | static int |
1883 | Operand_label8_rtoa (uint32 *valp, uint32 pc) | |
e0001a05 | 1884 | { |
43cd72b9 BW |
1885 | *valp += pc; |
1886 | return 0; | |
e0001a05 NC |
1887 | } |
1888 | ||
43cd72b9 BW |
1889 | static int |
1890 | Operand_ulabel8_decode (uint32 *valp) | |
e0001a05 | 1891 | { |
43cd72b9 BW |
1892 | unsigned ulabel8_0, imm8_0; |
1893 | imm8_0 = *valp & 0xff; | |
1894 | ulabel8_0 = 0x4 + ((((0)) << 8) | imm8_0); | |
1895 | *valp = ulabel8_0; | |
1896 | return 0; | |
e0001a05 NC |
1897 | } |
1898 | ||
43cd72b9 BW |
1899 | static int |
1900 | Operand_ulabel8_encode (uint32 *valp) | |
e0001a05 | 1901 | { |
43cd72b9 BW |
1902 | unsigned imm8_0, ulabel8_0; |
1903 | ulabel8_0 = *valp; | |
1904 | imm8_0 = (ulabel8_0 - 0x4) & 0xff; | |
1905 | *valp = imm8_0; | |
1906 | return 0; | |
e0001a05 NC |
1907 | } |
1908 | ||
43cd72b9 BW |
1909 | static int |
1910 | Operand_ulabel8_ator (uint32 *valp, uint32 pc) | |
e0001a05 | 1911 | { |
43cd72b9 BW |
1912 | *valp -= pc; |
1913 | return 0; | |
e0001a05 NC |
1914 | } |
1915 | ||
43cd72b9 BW |
1916 | static int |
1917 | Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) | |
e0001a05 | 1918 | { |
43cd72b9 BW |
1919 | *valp += pc; |
1920 | return 0; | |
e0001a05 NC |
1921 | } |
1922 | ||
43cd72b9 BW |
1923 | static int |
1924 | Operand_label12_decode (uint32 *valp) | |
e0001a05 | 1925 | { |
43cd72b9 BW |
1926 | unsigned label12_0, imm12_0; |
1927 | imm12_0 = *valp & 0xfff; | |
1928 | label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); | |
1929 | *valp = label12_0; | |
1930 | return 0; | |
e0001a05 NC |
1931 | } |
1932 | ||
43cd72b9 BW |
1933 | static int |
1934 | Operand_label12_encode (uint32 *valp) | |
1935 | { | |
1936 | unsigned imm12_0, label12_0; | |
1937 | label12_0 = *valp; | |
1938 | imm12_0 = (label12_0 - 0x4) & 0xfff; | |
1939 | *valp = imm12_0; | |
1940 | return 0; | |
1941 | } | |
e0001a05 | 1942 | |
43cd72b9 BW |
1943 | static int |
1944 | Operand_label12_ator (uint32 *valp, uint32 pc) | |
1945 | { | |
1946 | *valp -= pc; | |
1947 | return 0; | |
1948 | } | |
e0001a05 | 1949 | |
43cd72b9 BW |
1950 | static int |
1951 | Operand_label12_rtoa (uint32 *valp, uint32 pc) | |
1952 | { | |
1953 | *valp += pc; | |
1954 | return 0; | |
1955 | } | |
e0001a05 | 1956 | |
43cd72b9 BW |
1957 | static int |
1958 | Operand_soffset_decode (uint32 *valp) | |
1959 | { | |
1960 | unsigned soffset_0, offset_0; | |
1961 | offset_0 = *valp & 0x3ffff; | |
1962 | soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); | |
1963 | *valp = soffset_0; | |
1964 | return 0; | |
1965 | } | |
e0001a05 | 1966 | |
43cd72b9 BW |
1967 | static int |
1968 | Operand_soffset_encode (uint32 *valp) | |
e0001a05 | 1969 | { |
43cd72b9 BW |
1970 | unsigned offset_0, soffset_0; |
1971 | soffset_0 = *valp; | |
1972 | offset_0 = (soffset_0 - 0x4) & 0x3ffff; | |
1973 | *valp = offset_0; | |
1974 | return 0; | |
e0001a05 NC |
1975 | } |
1976 | ||
43cd72b9 BW |
1977 | static int |
1978 | Operand_soffset_ator (uint32 *valp, uint32 pc) | |
e0001a05 | 1979 | { |
43cd72b9 BW |
1980 | *valp -= pc; |
1981 | return 0; | |
e0001a05 NC |
1982 | } |
1983 | ||
43cd72b9 BW |
1984 | static int |
1985 | Operand_soffset_rtoa (uint32 *valp, uint32 pc) | |
e0001a05 | 1986 | { |
43cd72b9 BW |
1987 | *valp += pc; |
1988 | return 0; | |
e0001a05 NC |
1989 | } |
1990 | ||
43cd72b9 BW |
1991 | static int |
1992 | Operand_uimm16x4_decode (uint32 *valp) | |
e0001a05 | 1993 | { |
43cd72b9 BW |
1994 | unsigned uimm16x4_0, imm16_0; |
1995 | imm16_0 = *valp & 0xffff; | |
1996 | uimm16x4_0 = ((((0xffff)) << 16) | imm16_0) << 2; | |
1997 | *valp = uimm16x4_0; | |
1998 | return 0; | |
e0001a05 NC |
1999 | } |
2000 | ||
43cd72b9 BW |
2001 | static int |
2002 | Operand_uimm16x4_encode (uint32 *valp) | |
e0001a05 | 2003 | { |
43cd72b9 BW |
2004 | unsigned imm16_0, uimm16x4_0; |
2005 | uimm16x4_0 = *valp; | |
2006 | imm16_0 = (uimm16x4_0 >> 2) & 0xffff; | |
2007 | *valp = imm16_0; | |
2008 | return 0; | |
e0001a05 NC |
2009 | } |
2010 | ||
43cd72b9 BW |
2011 | static int |
2012 | Operand_uimm16x4_ator (uint32 *valp, uint32 pc) | |
e0001a05 | 2013 | { |
43cd72b9 BW |
2014 | *valp -= ((pc + 3) & ~0x3); |
2015 | return 0; | |
e0001a05 NC |
2016 | } |
2017 | ||
43cd72b9 BW |
2018 | static int |
2019 | Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) | |
2020 | { | |
2021 | *valp += ((pc + 3) & ~0x3); | |
2022 | return 0; | |
2023 | } | |
2024 | ||
2025 | static int | |
2026 | Operand_immt_decode (uint32 *valp) | |
2027 | { | |
2028 | unsigned immt_0, t_0; | |
2029 | t_0 = *valp & 0xf; | |
2030 | immt_0 = t_0; | |
2031 | *valp = immt_0; | |
2032 | return 0; | |
2033 | } | |
2034 | ||
2035 | static int | |
2036 | Operand_immt_encode (uint32 *valp) | |
2037 | { | |
2038 | unsigned t_0, immt_0; | |
2039 | immt_0 = *valp; | |
2040 | t_0 = immt_0 & 0xf; | |
2041 | *valp = t_0; | |
2042 | return 0; | |
2043 | } | |
2044 | ||
2045 | static int | |
2046 | Operand_imms_decode (uint32 *valp) | |
2047 | { | |
2048 | unsigned imms_0, s_0; | |
2049 | s_0 = *valp & 0xf; | |
2050 | imms_0 = s_0; | |
2051 | *valp = imms_0; | |
2052 | return 0; | |
2053 | } | |
2054 | ||
2055 | static int | |
2056 | Operand_imms_encode (uint32 *valp) | |
2057 | { | |
2058 | unsigned s_0, imms_0; | |
2059 | imms_0 = *valp; | |
2060 | s_0 = imms_0 & 0xf; | |
2061 | *valp = s_0; | |
2062 | return 0; | |
2063 | } | |
2064 | ||
2065 | static xtensa_operand_internal operands[] = { | |
2066 | { "soffsetx4", 10, -1, 0, | |
2067 | XTENSA_OPERAND_IS_PCRELATIVE, | |
2068 | Operand_soffsetx4_encode, Operand_soffsetx4_decode, | |
2069 | Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, | |
2070 | { "uimm12x8", 3, -1, 0, | |
2071 | 0, | |
2072 | Operand_uimm12x8_encode, Operand_uimm12x8_decode, | |
2073 | 0, 0 }, | |
2074 | { "simm4", 26, -1, 0, | |
2075 | 0, | |
2076 | Operand_simm4_encode, Operand_simm4_decode, | |
2077 | 0, 0 }, | |
2078 | { "arr", 14, 0, 1, | |
2079 | XTENSA_OPERAND_IS_REGISTER, | |
2080 | Operand_arr_encode, Operand_arr_decode, | |
2081 | 0, 0 }, | |
2082 | { "ars", 5, 0, 1, | |
2083 | XTENSA_OPERAND_IS_REGISTER, | |
2084 | Operand_ars_encode, Operand_ars_decode, | |
2085 | 0, 0 }, | |
2086 | { "*ars_invisible", 5, 0, 1, | |
2087 | XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, | |
2088 | Operand_ars_encode, Operand_ars_decode, | |
2089 | 0, 0 }, | |
2090 | { "art", 0, 0, 1, | |
2091 | XTENSA_OPERAND_IS_REGISTER, | |
2092 | Operand_art_encode, Operand_art_decode, | |
2093 | 0, 0 }, | |
2094 | { "ar0", 35, 0, 1, | |
2095 | XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, | |
2096 | Operand_ar0_encode, Operand_ar0_decode, | |
2097 | 0, 0 }, | |
2098 | { "ar4", 36, 0, 1, | |
2099 | XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, | |
2100 | Operand_ar4_encode, Operand_ar4_decode, | |
2101 | 0, 0 }, | |
2102 | { "ar8", 37, 0, 1, | |
2103 | XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, | |
2104 | Operand_ar8_encode, Operand_ar8_decode, | |
2105 | 0, 0 }, | |
2106 | { "ar12", 38, 0, 1, | |
2107 | XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, | |
2108 | Operand_ar12_encode, Operand_ar12_decode, | |
2109 | 0, 0 }, | |
2110 | { "ars_entry", 5, 0, 1, | |
2111 | XTENSA_OPERAND_IS_REGISTER, | |
2112 | Operand_ars_entry_encode, Operand_ars_entry_decode, | |
2113 | 0, 0 }, | |
2114 | { "immrx4", 14, -1, 0, | |
2115 | 0, | |
2116 | Operand_immrx4_encode, Operand_immrx4_decode, | |
2117 | 0, 0 }, | |
2118 | { "lsi4x4", 14, -1, 0, | |
2119 | 0, | |
2120 | Operand_lsi4x4_encode, Operand_lsi4x4_decode, | |
2121 | 0, 0 }, | |
2122 | { "simm7", 34, -1, 0, | |
2123 | 0, | |
2124 | Operand_simm7_encode, Operand_simm7_decode, | |
2125 | 0, 0 }, | |
2126 | { "uimm6", 33, -1, 0, | |
2127 | XTENSA_OPERAND_IS_PCRELATIVE, | |
2128 | Operand_uimm6_encode, Operand_uimm6_decode, | |
2129 | Operand_uimm6_ator, Operand_uimm6_rtoa }, | |
2130 | { "ai4const", 0, -1, 0, | |
2131 | 0, | |
2132 | Operand_ai4const_encode, Operand_ai4const_decode, | |
2133 | 0, 0 }, | |
2134 | { "b4const", 14, -1, 0, | |
2135 | 0, | |
2136 | Operand_b4const_encode, Operand_b4const_decode, | |
2137 | 0, 0 }, | |
2138 | { "b4constu", 14, -1, 0, | |
2139 | 0, | |
2140 | Operand_b4constu_encode, Operand_b4constu_decode, | |
2141 | 0, 0 }, | |
2142 | { "uimm8", 4, -1, 0, | |
2143 | 0, | |
2144 | Operand_uimm8_encode, Operand_uimm8_decode, | |
2145 | 0, 0 }, | |
2146 | { "uimm8x2", 4, -1, 0, | |
2147 | 0, | |
2148 | Operand_uimm8x2_encode, Operand_uimm8x2_decode, | |
2149 | 0, 0 }, | |
2150 | { "uimm8x4", 4, -1, 0, | |
2151 | 0, | |
2152 | Operand_uimm8x4_encode, Operand_uimm8x4_decode, | |
2153 | 0, 0 }, | |
2154 | { "uimm4x16", 13, -1, 0, | |
2155 | 0, | |
2156 | Operand_uimm4x16_encode, Operand_uimm4x16_decode, | |
2157 | 0, 0 }, | |
2158 | { "simm8", 4, -1, 0, | |
2159 | 0, | |
2160 | Operand_simm8_encode, Operand_simm8_decode, | |
2161 | 0, 0 }, | |
2162 | { "simm8x256", 4, -1, 0, | |
2163 | 0, | |
2164 | Operand_simm8x256_encode, Operand_simm8x256_decode, | |
2165 | 0, 0 }, | |
2166 | { "simm12b", 6, -1, 0, | |
2167 | 0, | |
2168 | Operand_simm12b_encode, Operand_simm12b_decode, | |
2169 | 0, 0 }, | |
2170 | { "msalp32", 18, -1, 0, | |
2171 | 0, | |
2172 | Operand_msalp32_encode, Operand_msalp32_decode, | |
2173 | 0, 0 }, | |
2174 | { "op2p1", 13, -1, 0, | |
2175 | 0, | |
2176 | Operand_op2p1_encode, Operand_op2p1_decode, | |
2177 | 0, 0 }, | |
2178 | { "label8", 4, -1, 0, | |
2179 | XTENSA_OPERAND_IS_PCRELATIVE, | |
2180 | Operand_label8_encode, Operand_label8_decode, | |
2181 | Operand_label8_ator, Operand_label8_rtoa }, | |
2182 | { "ulabel8", 4, -1, 0, | |
2183 | XTENSA_OPERAND_IS_PCRELATIVE, | |
2184 | Operand_ulabel8_encode, Operand_ulabel8_decode, | |
2185 | Operand_ulabel8_ator, Operand_ulabel8_rtoa }, | |
2186 | { "label12", 3, -1, 0, | |
2187 | XTENSA_OPERAND_IS_PCRELATIVE, | |
2188 | Operand_label12_encode, Operand_label12_decode, | |
2189 | Operand_label12_ator, Operand_label12_rtoa }, | |
2190 | { "soffset", 10, -1, 0, | |
2191 | XTENSA_OPERAND_IS_PCRELATIVE, | |
2192 | Operand_soffset_encode, Operand_soffset_decode, | |
2193 | Operand_soffset_ator, Operand_soffset_rtoa }, | |
2194 | { "uimm16x4", 7, -1, 0, | |
2195 | XTENSA_OPERAND_IS_PCRELATIVE, | |
2196 | Operand_uimm16x4_encode, Operand_uimm16x4_decode, | |
2197 | Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, | |
2198 | { "immt", 0, -1, 0, | |
2199 | 0, | |
2200 | Operand_immt_encode, Operand_immt_decode, | |
2201 | 0, 0 }, | |
2202 | { "imms", 5, -1, 0, | |
2203 | 0, | |
2204 | Operand_imms_encode, Operand_imms_decode, | |
2205 | 0, 0 }, | |
2206 | { "t", 0, -1, 0, 0, 0, 0, 0, 0 }, | |
2207 | { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 }, | |
2208 | { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 }, | |
2209 | { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 }, | |
2210 | { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 }, | |
2211 | { "s", 5, -1, 0, 0, 0, 0, 0, 0 }, | |
2212 | { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 }, | |
2213 | { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 }, | |
2214 | { "m", 8, -1, 0, 0, 0, 0, 0, 0 }, | |
2215 | { "n", 9, -1, 0, 0, 0, 0, 0, 0 }, | |
2216 | { "offset", 10, -1, 0, 0, 0, 0, 0, 0 }, | |
2217 | { "op0", 11, -1, 0, 0, 0, 0, 0, 0 }, | |
2218 | { "op1", 12, -1, 0, 0, 0, 0, 0, 0 }, | |
2219 | { "op2", 13, -1, 0, 0, 0, 0, 0, 0 }, | |
2220 | { "r", 14, -1, 0, 0, 0, 0, 0, 0 }, | |
2221 | { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 }, | |
2222 | { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 }, | |
2223 | { "sae", 17, -1, 0, 0, 0, 0, 0, 0 }, | |
2224 | { "sal", 18, -1, 0, 0, 0, 0, 0, 0 }, | |
2225 | { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 }, | |
2226 | { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 }, | |
2227 | { "sas", 21, -1, 0, 0, 0, 0, 0, 0 }, | |
2228 | { "sr", 22, -1, 0, 0, 0, 0, 0, 0 }, | |
2229 | { "st", 23, -1, 0, 0, 0, 0, 0, 0 }, | |
2230 | { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 }, | |
2231 | { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 }, | |
2232 | { "mn", 26, -1, 0, 0, 0, 0, 0, 0 }, | |
2233 | { "i", 27, -1, 0, 0, 0, 0, 0, 0 }, | |
2234 | { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 }, | |
2235 | { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 }, | |
2236 | { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 }, | |
2237 | { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 }, | |
2238 | { "z", 32, -1, 0, 0, 0, 0, 0, 0 }, | |
2239 | { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 }, | |
2240 | { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 } | |
2241 | }; | |
2242 | ||
2243 | \f | |
2244 | /* Iclass table. */ | |
2245 | ||
2246 | static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { | |
2247 | { { STATE_PSEXCM }, 'o' }, | |
2248 | { { STATE_EPC1 }, 'i' } | |
2249 | }; | |
2250 | ||
2251 | static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { | |
2252 | { { STATE_DEPC }, 'i' } | |
2253 | }; | |
2254 | ||
2255 | static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { | |
2256 | { { 0 /* soffsetx4 */ }, 'i' }, | |
2257 | { { 10 /* ar12 */ }, 'o' } | |
2258 | }; | |
2259 | ||
2260 | static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { | |
2261 | { { STATE_PSCALLINC }, 'o' } | |
2262 | }; | |
2263 | ||
2264 | static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { | |
2265 | { { 0 /* soffsetx4 */ }, 'i' }, | |
2266 | { { 9 /* ar8 */ }, 'o' } | |
e0001a05 NC |
2267 | }; |
2268 | ||
43cd72b9 BW |
2269 | static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { |
2270 | { { STATE_PSCALLINC }, 'o' } | |
e0001a05 NC |
2271 | }; |
2272 | ||
43cd72b9 BW |
2273 | static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { |
2274 | { { 0 /* soffsetx4 */ }, 'i' }, | |
2275 | { { 8 /* ar4 */ }, 'o' } | |
e0001a05 NC |
2276 | }; |
2277 | ||
43cd72b9 BW |
2278 | static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { |
2279 | { { STATE_PSCALLINC }, 'o' } | |
e0001a05 NC |
2280 | }; |
2281 | ||
43cd72b9 BW |
2282 | static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { |
2283 | { { 4 /* ars */ }, 'i' }, | |
2284 | { { 10 /* ar12 */ }, 'o' } | |
e0001a05 NC |
2285 | }; |
2286 | ||
43cd72b9 BW |
2287 | static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { |
2288 | { { STATE_PSCALLINC }, 'o' } | |
e0001a05 NC |
2289 | }; |
2290 | ||
43cd72b9 BW |
2291 | static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { |
2292 | { { 4 /* ars */ }, 'i' }, | |
2293 | { { 9 /* ar8 */ }, 'o' } | |
e0001a05 NC |
2294 | }; |
2295 | ||
43cd72b9 BW |
2296 | static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { |
2297 | { { STATE_PSCALLINC }, 'o' } | |
e0001a05 NC |
2298 | }; |
2299 | ||
43cd72b9 BW |
2300 | static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { |
2301 | { { 4 /* ars */ }, 'i' }, | |
2302 | { { 8 /* ar4 */ }, 'o' } | |
e0001a05 NC |
2303 | }; |
2304 | ||
43cd72b9 BW |
2305 | static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { |
2306 | { { STATE_PSCALLINC }, 'o' } | |
e0001a05 NC |
2307 | }; |
2308 | ||
43cd72b9 BW |
2309 | static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { |
2310 | { { 11 /* ars_entry */ }, 's' }, | |
2311 | { { 4 /* ars */ }, 'i' }, | |
2312 | { { 1 /* uimm12x8 */ }, 'i' } | |
e0001a05 NC |
2313 | }; |
2314 | ||
43cd72b9 BW |
2315 | static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { |
2316 | { { STATE_PSCALLINC }, 'i' }, | |
2317 | { { STATE_PSEXCM }, 'i' }, | |
2318 | { { STATE_PSWOE }, 'i' }, | |
2319 | { { STATE_WindowBase }, 'm' }, | |
2320 | { { STATE_WindowStart }, 'm' } | |
e0001a05 NC |
2321 | }; |
2322 | ||
43cd72b9 BW |
2323 | static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { |
2324 | { { 6 /* art */ }, 'o' }, | |
2325 | { { 4 /* ars */ }, 'i' } | |
e0001a05 NC |
2326 | }; |
2327 | ||
43cd72b9 BW |
2328 | static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { |
2329 | { { STATE_WindowBase }, 'i' }, | |
2330 | { { STATE_WindowStart }, 'i' } | |
e0001a05 NC |
2331 | }; |
2332 | ||
43cd72b9 BW |
2333 | static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { |
2334 | { { 2 /* simm4 */ }, 'i' } | |
e0001a05 NC |
2335 | }; |
2336 | ||
43cd72b9 BW |
2337 | static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { |
2338 | { { STATE_WindowBase }, 'm' } | |
e0001a05 NC |
2339 | }; |
2340 | ||
43cd72b9 BW |
2341 | static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { |
2342 | { { 5 /* *ars_invisible */ }, 'i' } | |
e0001a05 NC |
2343 | }; |
2344 | ||
43cd72b9 BW |
2345 | static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { |
2346 | { { STATE_WindowBase }, 'm' }, | |
2347 | { { STATE_WindowStart }, 'm' }, | |
2348 | { { STATE_PSEXCM }, 'i' }, | |
2349 | { { STATE_PSWOE }, 'i' } | |
e0001a05 NC |
2350 | }; |
2351 | ||
43cd72b9 BW |
2352 | static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { |
2353 | { { STATE_EPC1 }, 'i' }, | |
2354 | { { STATE_PSEXCM }, 'o' }, | |
2355 | { { STATE_WindowBase }, 'm' }, | |
2356 | { { STATE_WindowStart }, 'm' }, | |
2357 | { { STATE_PSOWB }, 'i' } | |
e0001a05 NC |
2358 | }; |
2359 | ||
43cd72b9 BW |
2360 | static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { |
2361 | { { 6 /* art */ }, 'o' }, | |
2362 | { { 4 /* ars */ }, 'i' }, | |
2363 | { { 12 /* immrx4 */ }, 'i' } | |
e0001a05 NC |
2364 | }; |
2365 | ||
43cd72b9 BW |
2366 | static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { |
2367 | { { 6 /* art */ }, 'i' }, | |
2368 | { { 4 /* ars */ }, 'i' }, | |
2369 | { { 12 /* immrx4 */ }, 'i' } | |
e0001a05 NC |
2370 | }; |
2371 | ||
43cd72b9 BW |
2372 | static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { |
2373 | { { 6 /* art */ }, 'o' } | |
e0001a05 NC |
2374 | }; |
2375 | ||
43cd72b9 BW |
2376 | static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { |
2377 | { { STATE_WindowBase }, 'i' } | |
e0001a05 NC |
2378 | }; |
2379 | ||
43cd72b9 BW |
2380 | static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { |
2381 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
2382 | }; |
2383 | ||
43cd72b9 BW |
2384 | static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { |
2385 | { { STATE_WindowBase }, 'o' } | |
e0001a05 NC |
2386 | }; |
2387 | ||
43cd72b9 BW |
2388 | static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { |
2389 | { { 6 /* art */ }, 'm' } | |
e0001a05 NC |
2390 | }; |
2391 | ||
43cd72b9 BW |
2392 | static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { |
2393 | { { STATE_WindowBase }, 'm' } | |
e0001a05 NC |
2394 | }; |
2395 | ||
43cd72b9 BW |
2396 | static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { |
2397 | { { 6 /* art */ }, 'o' } | |
e0001a05 NC |
2398 | }; |
2399 | ||
43cd72b9 BW |
2400 | static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { |
2401 | { { STATE_WindowStart }, 'i' } | |
e0001a05 NC |
2402 | }; |
2403 | ||
43cd72b9 BW |
2404 | static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { |
2405 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
2406 | }; |
2407 | ||
43cd72b9 BW |
2408 | static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { |
2409 | { { STATE_WindowStart }, 'o' } | |
e0001a05 NC |
2410 | }; |
2411 | ||
43cd72b9 BW |
2412 | static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { |
2413 | { { 6 /* art */ }, 'm' } | |
e0001a05 NC |
2414 | }; |
2415 | ||
43cd72b9 BW |
2416 | static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { |
2417 | { { STATE_WindowStart }, 'm' } | |
e0001a05 NC |
2418 | }; |
2419 | ||
43cd72b9 BW |
2420 | static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { |
2421 | { { 3 /* arr */ }, 'o' }, | |
2422 | { { 4 /* ars */ }, 'i' }, | |
2423 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
2424 | }; |
2425 | ||
43cd72b9 BW |
2426 | static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { |
2427 | { { 3 /* arr */ }, 'o' }, | |
2428 | { { 4 /* ars */ }, 'i' }, | |
2429 | { { 16 /* ai4const */ }, 'i' } | |
e0001a05 NC |
2430 | }; |
2431 | ||
43cd72b9 BW |
2432 | static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { |
2433 | { { 4 /* ars */ }, 'i' }, | |
2434 | { { 15 /* uimm6 */ }, 'i' } | |
e0001a05 NC |
2435 | }; |
2436 | ||
43cd72b9 BW |
2437 | static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { |
2438 | { { 6 /* art */ }, 'o' }, | |
2439 | { { 4 /* ars */ }, 'i' }, | |
2440 | { { 13 /* lsi4x4 */ }, 'i' } | |
e0001a05 NC |
2441 | }; |
2442 | ||
43cd72b9 BW |
2443 | static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { |
2444 | { { 6 /* art */ }, 'o' }, | |
2445 | { { 4 /* ars */ }, 'i' } | |
e0001a05 NC |
2446 | }; |
2447 | ||
43cd72b9 BW |
2448 | static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { |
2449 | { { 4 /* ars */ }, 'o' }, | |
2450 | { { 14 /* simm7 */ }, 'i' } | |
e0001a05 NC |
2451 | }; |
2452 | ||
43cd72b9 BW |
2453 | static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { |
2454 | { { 5 /* *ars_invisible */ }, 'i' } | |
e0001a05 NC |
2455 | }; |
2456 | ||
43cd72b9 BW |
2457 | static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { |
2458 | { { 6 /* art */ }, 'i' }, | |
2459 | { { 4 /* ars */ }, 'i' }, | |
2460 | { { 13 /* lsi4x4 */ }, 'i' } | |
e0001a05 NC |
2461 | }; |
2462 | ||
43cd72b9 BW |
2463 | static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { |
2464 | { { 6 /* art */ }, 'o' }, | |
2465 | { { 4 /* ars */ }, 'i' }, | |
2466 | { { 23 /* simm8 */ }, 'i' } | |
e0001a05 NC |
2467 | }; |
2468 | ||
43cd72b9 BW |
2469 | static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { |
2470 | { { 6 /* art */ }, 'o' }, | |
2471 | { { 4 /* ars */ }, 'i' }, | |
2472 | { { 24 /* simm8x256 */ }, 'i' } | |
e0001a05 NC |
2473 | }; |
2474 | ||
43cd72b9 BW |
2475 | static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { |
2476 | { { 3 /* arr */ }, 'o' }, | |
2477 | { { 4 /* ars */ }, 'i' }, | |
2478 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
2479 | }; |
2480 | ||
43cd72b9 BW |
2481 | static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { |
2482 | { { 3 /* arr */ }, 'o' }, | |
2483 | { { 4 /* ars */ }, 'i' }, | |
2484 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
2485 | }; |
2486 | ||
43cd72b9 BW |
2487 | static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { |
2488 | { { 4 /* ars */ }, 'i' }, | |
2489 | { { 17 /* b4const */ }, 'i' }, | |
2490 | { { 28 /* label8 */ }, 'i' } | |
e0001a05 NC |
2491 | }; |
2492 | ||
43cd72b9 BW |
2493 | static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { |
2494 | { { 4 /* ars */ }, 'i' }, | |
2495 | { { 37 /* bbi */ }, 'i' }, | |
2496 | { { 28 /* label8 */ }, 'i' } | |
e0001a05 NC |
2497 | }; |
2498 | ||
43cd72b9 BW |
2499 | static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { |
2500 | { { 4 /* ars */ }, 'i' }, | |
2501 | { { 18 /* b4constu */ }, 'i' }, | |
2502 | { { 28 /* label8 */ }, 'i' } | |
e0001a05 NC |
2503 | }; |
2504 | ||
43cd72b9 BW |
2505 | static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { |
2506 | { { 4 /* ars */ }, 'i' }, | |
2507 | { { 6 /* art */ }, 'i' }, | |
2508 | { { 28 /* label8 */ }, 'i' } | |
e0001a05 NC |
2509 | }; |
2510 | ||
43cd72b9 BW |
2511 | static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { |
2512 | { { 4 /* ars */ }, 'i' }, | |
2513 | { { 30 /* label12 */ }, 'i' } | |
e0001a05 NC |
2514 | }; |
2515 | ||
43cd72b9 BW |
2516 | static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { |
2517 | { { 0 /* soffsetx4 */ }, 'i' }, | |
2518 | { { 7 /* ar0 */ }, 'o' } | |
e0001a05 NC |
2519 | }; |
2520 | ||
43cd72b9 BW |
2521 | static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { |
2522 | { { 4 /* ars */ }, 'i' }, | |
2523 | { { 7 /* ar0 */ }, 'o' } | |
e0001a05 NC |
2524 | }; |
2525 | ||
43cd72b9 BW |
2526 | static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { |
2527 | { { 3 /* arr */ }, 'o' }, | |
2528 | { { 6 /* art */ }, 'i' }, | |
2529 | { { 52 /* sae */ }, 'i' }, | |
2530 | { { 27 /* op2p1 */ }, 'i' } | |
e0001a05 NC |
2531 | }; |
2532 | ||
43cd72b9 BW |
2533 | static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { |
2534 | { { 31 /* soffset */ }, 'i' } | |
e0001a05 NC |
2535 | }; |
2536 | ||
43cd72b9 BW |
2537 | static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { |
2538 | { { 4 /* ars */ }, 'i' } | |
e0001a05 NC |
2539 | }; |
2540 | ||
43cd72b9 BW |
2541 | static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { |
2542 | { { 6 /* art */ }, 'o' }, | |
2543 | { { 4 /* ars */ }, 'i' }, | |
2544 | { { 20 /* uimm8x2 */ }, 'i' } | |
e0001a05 NC |
2545 | }; |
2546 | ||
43cd72b9 BW |
2547 | static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { |
2548 | { { 6 /* art */ }, 'o' }, | |
2549 | { { 4 /* ars */ }, 'i' }, | |
2550 | { { 20 /* uimm8x2 */ }, 'i' } | |
e0001a05 NC |
2551 | }; |
2552 | ||
43cd72b9 BW |
2553 | static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { |
2554 | { { 6 /* art */ }, 'o' }, | |
2555 | { { 4 /* ars */ }, 'i' }, | |
2556 | { { 21 /* uimm8x4 */ }, 'i' } | |
e0001a05 NC |
2557 | }; |
2558 | ||
43cd72b9 BW |
2559 | static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { |
2560 | { { 6 /* art */ }, 'o' }, | |
2561 | { { 32 /* uimm16x4 */ }, 'i' } | |
e0001a05 NC |
2562 | }; |
2563 | ||
43cd72b9 BW |
2564 | static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { |
2565 | { { STATE_LITBADDR }, 'i' }, | |
2566 | { { STATE_LITBEN }, 'i' } | |
e0001a05 NC |
2567 | }; |
2568 | ||
43cd72b9 BW |
2569 | static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { |
2570 | { { 6 /* art */ }, 'o' }, | |
2571 | { { 4 /* ars */ }, 'i' }, | |
2572 | { { 19 /* uimm8 */ }, 'i' } | |
e0001a05 NC |
2573 | }; |
2574 | ||
43cd72b9 BW |
2575 | static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { |
2576 | { { 4 /* ars */ }, 'i' }, | |
2577 | { { 29 /* ulabel8 */ }, 'i' } | |
e0001a05 NC |
2578 | }; |
2579 | ||
43cd72b9 BW |
2580 | static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { |
2581 | { { STATE_LBEG }, 'o' }, | |
2582 | { { STATE_LEND }, 'o' }, | |
2583 | { { STATE_LCOUNT }, 'o' } | |
e0001a05 NC |
2584 | }; |
2585 | ||
43cd72b9 BW |
2586 | static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { |
2587 | { { 4 /* ars */ }, 'i' }, | |
2588 | { { 29 /* ulabel8 */ }, 'i' } | |
e0001a05 NC |
2589 | }; |
2590 | ||
43cd72b9 BW |
2591 | static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { |
2592 | { { STATE_LBEG }, 'o' }, | |
2593 | { { STATE_LEND }, 'o' }, | |
2594 | { { STATE_LCOUNT }, 'o' } | |
e0001a05 NC |
2595 | }; |
2596 | ||
43cd72b9 BW |
2597 | static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { |
2598 | { { 6 /* art */ }, 'o' }, | |
2599 | { { 25 /* simm12b */ }, 'i' } | |
e0001a05 NC |
2600 | }; |
2601 | ||
43cd72b9 BW |
2602 | static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { |
2603 | { { 3 /* arr */ }, 'm' }, | |
2604 | { { 4 /* ars */ }, 'i' }, | |
2605 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
2606 | }; |
2607 | ||
43cd72b9 BW |
2608 | static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { |
2609 | { { 3 /* arr */ }, 'o' }, | |
2610 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
2611 | }; |
2612 | ||
43cd72b9 BW |
2613 | static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { |
2614 | { { 5 /* *ars_invisible */ }, 'i' } | |
e0001a05 NC |
2615 | }; |
2616 | ||
43cd72b9 BW |
2617 | static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { |
2618 | { { 6 /* art */ }, 'i' }, | |
2619 | { { 4 /* ars */ }, 'i' }, | |
2620 | { { 20 /* uimm8x2 */ }, 'i' } | |
e0001a05 NC |
2621 | }; |
2622 | ||
43cd72b9 BW |
2623 | static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { |
2624 | { { 6 /* art */ }, 'i' }, | |
2625 | { { 4 /* ars */ }, 'i' }, | |
2626 | { { 21 /* uimm8x4 */ }, 'i' } | |
e0001a05 NC |
2627 | }; |
2628 | ||
43cd72b9 BW |
2629 | static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { |
2630 | { { 6 /* art */ }, 'i' }, | |
2631 | { { 4 /* ars */ }, 'i' }, | |
2632 | { { 19 /* uimm8 */ }, 'i' } | |
e0001a05 NC |
2633 | }; |
2634 | ||
43cd72b9 BW |
2635 | static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { |
2636 | { { 4 /* ars */ }, 'i' } | |
e0001a05 NC |
2637 | }; |
2638 | ||
43cd72b9 BW |
2639 | static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { |
2640 | { { STATE_SAR }, 'o' } | |
e0001a05 NC |
2641 | }; |
2642 | ||
43cd72b9 BW |
2643 | static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { |
2644 | { { 56 /* sas */ }, 'i' } | |
e0001a05 NC |
2645 | }; |
2646 | ||
43cd72b9 BW |
2647 | static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { |
2648 | { { STATE_SAR }, 'o' } | |
e0001a05 NC |
2649 | }; |
2650 | ||
43cd72b9 BW |
2651 | static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { |
2652 | { { 3 /* arr */ }, 'o' }, | |
2653 | { { 4 /* ars */ }, 'i' } | |
e0001a05 NC |
2654 | }; |
2655 | ||
43cd72b9 BW |
2656 | static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { |
2657 | { { STATE_SAR }, 'i' } | |
e0001a05 NC |
2658 | }; |
2659 | ||
43cd72b9 BW |
2660 | static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { |
2661 | { { 3 /* arr */ }, 'o' }, | |
2662 | { { 4 /* ars */ }, 'i' }, | |
2663 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
2664 | }; |
2665 | ||
43cd72b9 BW |
2666 | static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { |
2667 | { { STATE_SAR }, 'i' } | |
e0001a05 NC |
2668 | }; |
2669 | ||
43cd72b9 BW |
2670 | static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { |
2671 | { { 3 /* arr */ }, 'o' }, | |
2672 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
2673 | }; |
2674 | ||
43cd72b9 BW |
2675 | static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { |
2676 | { { STATE_SAR }, 'i' } | |
e0001a05 NC |
2677 | }; |
2678 | ||
43cd72b9 BW |
2679 | static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { |
2680 | { { 3 /* arr */ }, 'o' }, | |
2681 | { { 4 /* ars */ }, 'i' }, | |
2682 | { { 26 /* msalp32 */ }, 'i' } | |
e0001a05 NC |
2683 | }; |
2684 | ||
43cd72b9 BW |
2685 | static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { |
2686 | { { 3 /* arr */ }, 'o' }, | |
2687 | { { 6 /* art */ }, 'i' }, | |
2688 | { { 54 /* sargt */ }, 'i' } | |
e0001a05 NC |
2689 | }; |
2690 | ||
43cd72b9 BW |
2691 | static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { |
2692 | { { 3 /* arr */ }, 'o' }, | |
2693 | { { 6 /* art */ }, 'i' }, | |
2694 | { { 40 /* s */ }, 'i' } | |
e0001a05 NC |
2695 | }; |
2696 | ||
43cd72b9 BW |
2697 | static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { |
2698 | { { STATE_XTSYNC }, 'i' } | |
e0001a05 NC |
2699 | }; |
2700 | ||
43cd72b9 BW |
2701 | static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { |
2702 | { { 6 /* art */ }, 'o' }, | |
2703 | { { 40 /* s */ }, 'i' } | |
e0001a05 NC |
2704 | }; |
2705 | ||
43cd72b9 BW |
2706 | static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { |
2707 | { { STATE_PSWOE }, 'i' }, | |
2708 | { { STATE_PSCALLINC }, 'i' }, | |
2709 | { { STATE_PSOWB }, 'i' }, | |
2710 | { { STATE_PSUM }, 'i' }, | |
2711 | { { STATE_PSEXCM }, 'i' }, | |
2712 | { { STATE_PSINTLEVEL }, 'm' } | |
e0001a05 NC |
2713 | }; |
2714 | ||
43cd72b9 BW |
2715 | static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { |
2716 | { { 6 /* art */ }, 'o' } | |
e0001a05 NC |
2717 | }; |
2718 | ||
43cd72b9 BW |
2719 | static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { |
2720 | { { STATE_LEND }, 'i' } | |
e0001a05 NC |
2721 | }; |
2722 | ||
43cd72b9 BW |
2723 | static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { |
2724 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
2725 | }; |
2726 | ||
43cd72b9 BW |
2727 | static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { |
2728 | { { STATE_LEND }, 'o' } | |
e0001a05 NC |
2729 | }; |
2730 | ||
43cd72b9 BW |
2731 | static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { |
2732 | { { 6 /* art */ }, 'm' } | |
e0001a05 NC |
2733 | }; |
2734 | ||
43cd72b9 BW |
2735 | static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { |
2736 | { { STATE_LEND }, 'm' } | |
e0001a05 NC |
2737 | }; |
2738 | ||
43cd72b9 BW |
2739 | static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { |
2740 | { { 6 /* art */ }, 'o' } | |
e0001a05 NC |
2741 | }; |
2742 | ||
43cd72b9 BW |
2743 | static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { |
2744 | { { STATE_LCOUNT }, 'i' } | |
e0001a05 NC |
2745 | }; |
2746 | ||
43cd72b9 BW |
2747 | static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { |
2748 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
2749 | }; |
2750 | ||
43cd72b9 BW |
2751 | static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { |
2752 | { { STATE_XTSYNC }, 'o' }, | |
2753 | { { STATE_LCOUNT }, 'o' } | |
e0001a05 NC |
2754 | }; |
2755 | ||
43cd72b9 BW |
2756 | static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { |
2757 | { { 6 /* art */ }, 'm' } | |
e0001a05 NC |
2758 | }; |
2759 | ||
43cd72b9 BW |
2760 | static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { |
2761 | { { STATE_XTSYNC }, 'o' }, | |
2762 | { { STATE_LCOUNT }, 'm' } | |
e0001a05 NC |
2763 | }; |
2764 | ||
43cd72b9 BW |
2765 | static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { |
2766 | { { 6 /* art */ }, 'o' } | |
e0001a05 NC |
2767 | }; |
2768 | ||
43cd72b9 BW |
2769 | static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { |
2770 | { { STATE_LBEG }, 'i' } | |
e0001a05 NC |
2771 | }; |
2772 | ||
43cd72b9 BW |
2773 | static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { |
2774 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
2775 | }; |
2776 | ||
43cd72b9 BW |
2777 | static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { |
2778 | { { STATE_LBEG }, 'o' } | |
e0001a05 NC |
2779 | }; |
2780 | ||
43cd72b9 BW |
2781 | static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { |
2782 | { { 6 /* art */ }, 'm' } | |
e0001a05 NC |
2783 | }; |
2784 | ||
43cd72b9 BW |
2785 | static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { |
2786 | { { STATE_LBEG }, 'm' } | |
e0001a05 NC |
2787 | }; |
2788 | ||
43cd72b9 BW |
2789 | static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { |
2790 | { { 6 /* art */ }, 'o' } | |
e0001a05 NC |
2791 | }; |
2792 | ||
43cd72b9 BW |
2793 | static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { |
2794 | { { STATE_SAR }, 'i' } | |
e0001a05 NC |
2795 | }; |
2796 | ||
43cd72b9 BW |
2797 | static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { |
2798 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
2799 | }; |
2800 | ||
43cd72b9 BW |
2801 | static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { |
2802 | { { STATE_SAR }, 'o' }, | |
2803 | { { STATE_XTSYNC }, 'o' } | |
e0001a05 NC |
2804 | }; |
2805 | ||
43cd72b9 BW |
2806 | static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { |
2807 | { { 6 /* art */ }, 'm' } | |
e0001a05 NC |
2808 | }; |
2809 | ||
43cd72b9 BW |
2810 | static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { |
2811 | { { STATE_SAR }, 'm' } | |
e0001a05 NC |
2812 | }; |
2813 | ||
43cd72b9 BW |
2814 | static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { |
2815 | { { 6 /* art */ }, 'o' } | |
e0001a05 NC |
2816 | }; |
2817 | ||
43cd72b9 BW |
2818 | static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { |
2819 | { { STATE_LITBADDR }, 'i' }, | |
2820 | { { STATE_LITBEN }, 'i' } | |
e0001a05 NC |
2821 | }; |
2822 | ||
43cd72b9 BW |
2823 | static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { |
2824 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
2825 | }; |
2826 | ||
43cd72b9 BW |
2827 | static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { |
2828 | { { STATE_LITBADDR }, 'o' }, | |
2829 | { { STATE_LITBEN }, 'o' } | |
e0001a05 NC |
2830 | }; |
2831 | ||
43cd72b9 BW |
2832 | static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { |
2833 | { { 6 /* art */ }, 'm' } | |
e0001a05 NC |
2834 | }; |
2835 | ||
43cd72b9 BW |
2836 | static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { |
2837 | { { STATE_LITBADDR }, 'm' }, | |
2838 | { { STATE_LITBEN }, 'm' } | |
e0001a05 NC |
2839 | }; |
2840 | ||
43cd72b9 BW |
2841 | static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { |
2842 | { { 6 /* art */ }, 'o' } | |
e0001a05 NC |
2843 | }; |
2844 | ||
43cd72b9 BW |
2845 | static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { |
2846 | { { 6 /* art */ }, 'o' } | |
e0001a05 NC |
2847 | }; |
2848 | ||
43cd72b9 BW |
2849 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { |
2850 | { { 6 /* art */ }, 'o' } | |
e0001a05 NC |
2851 | }; |
2852 | ||
43cd72b9 BW |
2853 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { |
2854 | { { STATE_PSWOE }, 'i' }, | |
2855 | { { STATE_PSCALLINC }, 'i' }, | |
2856 | { { STATE_PSOWB }, 'i' }, | |
2857 | { { STATE_PSUM }, 'i' }, | |
2858 | { { STATE_PSEXCM }, 'i' }, | |
2859 | { { STATE_PSINTLEVEL }, 'i' } | |
e0001a05 NC |
2860 | }; |
2861 | ||
43cd72b9 BW |
2862 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { |
2863 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
2864 | }; |
2865 | ||
43cd72b9 BW |
2866 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { |
2867 | { { STATE_PSWOE }, 'o' }, | |
2868 | { { STATE_PSCALLINC }, 'o' }, | |
2869 | { { STATE_PSOWB }, 'o' }, | |
2870 | { { STATE_PSUM }, 'o' }, | |
2871 | { { STATE_PSEXCM }, 'o' }, | |
2872 | { { STATE_PSINTLEVEL }, 'o' } | |
e0001a05 NC |
2873 | }; |
2874 | ||
43cd72b9 BW |
2875 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { |
2876 | { { 6 /* art */ }, 'm' } | |
e0001a05 NC |
2877 | }; |
2878 | ||
43cd72b9 BW |
2879 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { |
2880 | { { STATE_PSWOE }, 'm' }, | |
2881 | { { STATE_PSCALLINC }, 'm' }, | |
2882 | { { STATE_PSOWB }, 'm' }, | |
2883 | { { STATE_PSUM }, 'm' }, | |
2884 | { { STATE_PSEXCM }, 'm' }, | |
2885 | { { STATE_PSINTLEVEL }, 'm' } | |
e0001a05 NC |
2886 | }; |
2887 | ||
43cd72b9 BW |
2888 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { |
2889 | { { 6 /* art */ }, 'o' } | |
e0001a05 NC |
2890 | }; |
2891 | ||
43cd72b9 BW |
2892 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { |
2893 | { { STATE_EPC1 }, 'i' } | |
e0001a05 NC |
2894 | }; |
2895 | ||
43cd72b9 BW |
2896 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { |
2897 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
2898 | }; |
2899 | ||
43cd72b9 BW |
2900 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { |
2901 | { { STATE_EPC1 }, 'o' } | |
e0001a05 NC |
2902 | }; |
2903 | ||
43cd72b9 BW |
2904 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { |
2905 | { { 6 /* art */ }, 'm' } | |
e0001a05 NC |
2906 | }; |
2907 | ||
43cd72b9 BW |
2908 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { |
2909 | { { STATE_EPC1 }, 'm' } | |
e0001a05 NC |
2910 | }; |
2911 | ||
43cd72b9 BW |
2912 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { |
2913 | { { 6 /* art */ }, 'o' } | |
e0001a05 NC |
2914 | }; |
2915 | ||
43cd72b9 BW |
2916 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { |
2917 | { { STATE_EXCSAVE1 }, 'i' } | |
e0001a05 NC |
2918 | }; |
2919 | ||
43cd72b9 BW |
2920 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { |
2921 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
2922 | }; |
2923 | ||
43cd72b9 BW |
2924 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { |
2925 | { { STATE_EXCSAVE1 }, 'o' } | |
e0001a05 NC |
2926 | }; |
2927 | ||
43cd72b9 BW |
2928 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { |
2929 | { { 6 /* art */ }, 'm' } | |
e0001a05 NC |
2930 | }; |
2931 | ||
43cd72b9 BW |
2932 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { |
2933 | { { STATE_EXCSAVE1 }, 'm' } | |
e0001a05 NC |
2934 | }; |
2935 | ||
43cd72b9 BW |
2936 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { |
2937 | { { 6 /* art */ }, 'o' } | |
e0001a05 NC |
2938 | }; |
2939 | ||
43cd72b9 BW |
2940 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { |
2941 | { { STATE_EPC2 }, 'i' } | |
e0001a05 NC |
2942 | }; |
2943 | ||
43cd72b9 BW |
2944 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { |
2945 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
2946 | }; |
2947 | ||
43cd72b9 BW |
2948 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { |
2949 | { { STATE_EPC2 }, 'o' } | |
e0001a05 NC |
2950 | }; |
2951 | ||
43cd72b9 BW |
2952 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { |
2953 | { { 6 /* art */ }, 'm' } | |
e0001a05 NC |
2954 | }; |
2955 | ||
43cd72b9 BW |
2956 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { |
2957 | { { STATE_EPC2 }, 'm' } | |
e0001a05 NC |
2958 | }; |
2959 | ||
43cd72b9 BW |
2960 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { |
2961 | { { 6 /* art */ }, 'o' } | |
e0001a05 NC |
2962 | }; |
2963 | ||
43cd72b9 BW |
2964 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { |
2965 | { { STATE_EXCSAVE2 }, 'i' } | |
e0001a05 NC |
2966 | }; |
2967 | ||
43cd72b9 BW |
2968 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { |
2969 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
2970 | }; |
2971 | ||
43cd72b9 BW |
2972 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { |
2973 | { { STATE_EXCSAVE2 }, 'o' } | |
e0001a05 NC |
2974 | }; |
2975 | ||
43cd72b9 BW |
2976 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { |
2977 | { { 6 /* art */ }, 'm' } | |
e0001a05 NC |
2978 | }; |
2979 | ||
43cd72b9 BW |
2980 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { |
2981 | { { STATE_EXCSAVE2 }, 'm' } | |
e0001a05 NC |
2982 | }; |
2983 | ||
43cd72b9 BW |
2984 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { |
2985 | { { 6 /* art */ }, 'o' } | |
e0001a05 NC |
2986 | }; |
2987 | ||
43cd72b9 BW |
2988 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { |
2989 | { { STATE_EPC3 }, 'i' } | |
e0001a05 NC |
2990 | }; |
2991 | ||
43cd72b9 BW |
2992 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { |
2993 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
2994 | }; |
2995 | ||
43cd72b9 BW |
2996 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { |
2997 | { { STATE_EPC3 }, 'o' } | |
e0001a05 NC |
2998 | }; |
2999 | ||
43cd72b9 BW |
3000 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { |
3001 | { { 6 /* art */ }, 'm' } | |
e0001a05 NC |
3002 | }; |
3003 | ||
43cd72b9 BW |
3004 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { |
3005 | { { STATE_EPC3 }, 'm' } | |
e0001a05 NC |
3006 | }; |
3007 | ||
43cd72b9 BW |
3008 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { |
3009 | { { 6 /* art */ }, 'o' } | |
e0001a05 NC |
3010 | }; |
3011 | ||
43cd72b9 BW |
3012 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { |
3013 | { { STATE_EXCSAVE3 }, 'i' } | |
e0001a05 NC |
3014 | }; |
3015 | ||
43cd72b9 BW |
3016 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { |
3017 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
3018 | }; |
3019 | ||
43cd72b9 BW |
3020 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { |
3021 | { { STATE_EXCSAVE3 }, 'o' } | |
e0001a05 NC |
3022 | }; |
3023 | ||
43cd72b9 BW |
3024 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { |
3025 | { { 6 /* art */ }, 'm' } | |
e0001a05 NC |
3026 | }; |
3027 | ||
43cd72b9 BW |
3028 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { |
3029 | { { STATE_EXCSAVE3 }, 'm' } | |
e0001a05 NC |
3030 | }; |
3031 | ||
43cd72b9 BW |
3032 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { |
3033 | { { 6 /* art */ }, 'o' } | |
e0001a05 NC |
3034 | }; |
3035 | ||
43cd72b9 BW |
3036 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { |
3037 | { { STATE_EPC4 }, 'i' } | |
e0001a05 NC |
3038 | }; |
3039 | ||
43cd72b9 BW |
3040 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { |
3041 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
3042 | }; |
3043 | ||
43cd72b9 BW |
3044 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { |
3045 | { { STATE_EPC4 }, 'o' } | |
e0001a05 NC |
3046 | }; |
3047 | ||
43cd72b9 BW |
3048 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { |
3049 | { { 6 /* art */ }, 'm' } | |
e0001a05 NC |
3050 | }; |
3051 | ||
43cd72b9 BW |
3052 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { |
3053 | { { STATE_EPC4 }, 'm' } | |
e0001a05 NC |
3054 | }; |
3055 | ||
43cd72b9 BW |
3056 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { |
3057 | { { 6 /* art */ }, 'o' } | |
e0001a05 NC |
3058 | }; |
3059 | ||
43cd72b9 BW |
3060 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { |
3061 | { { STATE_EXCSAVE4 }, 'i' } | |
e0001a05 NC |
3062 | }; |
3063 | ||
43cd72b9 BW |
3064 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { |
3065 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
3066 | }; |
3067 | ||
43cd72b9 BW |
3068 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { |
3069 | { { STATE_EXCSAVE4 }, 'o' } | |
e0001a05 NC |
3070 | }; |
3071 | ||
43cd72b9 BW |
3072 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { |
3073 | { { 6 /* art */ }, 'm' } | |
e0001a05 NC |
3074 | }; |
3075 | ||
43cd72b9 BW |
3076 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { |
3077 | { { STATE_EXCSAVE4 }, 'm' } | |
e0001a05 NC |
3078 | }; |
3079 | ||
43cd72b9 BW |
3080 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { |
3081 | { { 6 /* art */ }, 'o' } | |
e0001a05 NC |
3082 | }; |
3083 | ||
43cd72b9 BW |
3084 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { |
3085 | { { STATE_EPS2 }, 'i' } | |
e0001a05 NC |
3086 | }; |
3087 | ||
43cd72b9 BW |
3088 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { |
3089 | { { 6 /* art */ }, 'i' } | |
e0001a05 NC |
3090 | }; |
3091 | ||
43cd72b9 BW |
3092 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { |
3093 | { { STATE_EPS2 }, 'o' } | |
e0001a05 NC |
3094 | }; |
3095 | ||
43cd72b9 BW |
3096 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { |
3097 | { { 6 /* art */ }, 'm' } | |
e0001a05 NC |
3098 | }; |
3099 | ||
43cd72b9 BW |
3100 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { |
3101 | { { STATE_EPS2 }, 'm' } | |
e0001a05 NC |
3102 | }; |
3103 | ||
43cd72b9 BW |
3104 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { |
3105 | { { 6 /* art */ }, 'o' } | |
e0001a05 NC |
3106 | }; |
3107 | ||
43cd72b9 BW |
3108 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { |
3109 | { { STATE_EPS3 }, 'i' } | |
e0001a05 NC |
3110 | }; |
3111 | ||
43cd72b9 BW |
3112 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { |
3113 | { { 6 /* art */ }, 'i' } | |
3114 | }; | |
e0001a05 | 3115 | |
43cd72b9 BW |
3116 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { |
3117 | { { STATE_EPS3 }, 'o' } | |
3118 | }; | |
e0001a05 | 3119 | |
43cd72b9 BW |
3120 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { |
3121 | { { 6 /* art */ }, 'm' } | |
3122 | }; | |
e0001a05 | 3123 | |
43cd72b9 BW |
3124 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { |
3125 | { { STATE_EPS3 }, 'm' } | |
3126 | }; | |
3127 | ||
3128 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { | |
3129 | { { 6 /* art */ }, 'o' } | |
3130 | }; | |
3131 | ||
3132 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { | |
3133 | { { STATE_EPS4 }, 'i' } | |
3134 | }; | |
3135 | ||
3136 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { | |
3137 | { { 6 /* art */ }, 'i' } | |
3138 | }; | |
3139 | ||
3140 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { | |
3141 | { { STATE_EPS4 }, 'o' } | |
3142 | }; | |
3143 | ||
3144 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { | |
3145 | { { 6 /* art */ }, 'm' } | |
3146 | }; | |
3147 | ||
3148 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { | |
3149 | { { STATE_EPS4 }, 'm' } | |
3150 | }; | |
3151 | ||
3152 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { | |
3153 | { { 6 /* art */ }, 'o' } | |
3154 | }; | |
3155 | ||
3156 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { | |
3157 | { { STATE_EXCVADDR }, 'i' } | |
3158 | }; | |
3159 | ||
3160 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { | |
3161 | { { 6 /* art */ }, 'i' } | |
3162 | }; | |
3163 | ||
3164 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { | |
3165 | { { STATE_EXCVADDR }, 'o' } | |
3166 | }; | |
3167 | ||
3168 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { | |
3169 | { { 6 /* art */ }, 'm' } | |
3170 | }; | |
3171 | ||
3172 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { | |
3173 | { { STATE_EXCVADDR }, 'm' } | |
3174 | }; | |
3175 | ||
3176 | static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { | |
3177 | { { 6 /* art */ }, 'o' } | |
3178 | }; | |
3179 | ||
3180 | static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { | |
3181 | { { STATE_DEPC }, 'i' } | |
3182 | }; | |
3183 | ||
3184 | static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { | |
3185 | { { 6 /* art */ }, 'i' } | |
3186 | }; | |
3187 | ||
3188 | static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { | |
3189 | { { STATE_DEPC }, 'o' } | |
3190 | }; | |
3191 | ||
3192 | static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { | |
3193 | { { 6 /* art */ }, 'm' } | |
3194 | }; | |
3195 | ||
3196 | static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { | |
3197 | { { STATE_DEPC }, 'm' } | |
3198 | }; | |
3199 | ||
3200 | static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { | |
3201 | { { 6 /* art */ }, 'o' } | |
3202 | }; | |
3203 | ||
3204 | static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { | |
3205 | { { STATE_EXCCAUSE }, 'i' }, | |
3206 | { { STATE_XTSYNC }, 'i' } | |
3207 | }; | |
3208 | ||
3209 | static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { | |
3210 | { { 6 /* art */ }, 'i' } | |
3211 | }; | |
3212 | ||
3213 | static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { | |
3214 | { { STATE_EXCCAUSE }, 'o' } | |
3215 | }; | |
3216 | ||
3217 | static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { | |
3218 | { { 6 /* art */ }, 'm' } | |
3219 | }; | |
3220 | ||
3221 | static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { | |
3222 | { { STATE_EXCCAUSE }, 'm' } | |
3223 | }; | |
3224 | ||
3225 | static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { | |
3226 | { { 6 /* art */ }, 'o' } | |
3227 | }; | |
3228 | ||
3229 | static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { | |
3230 | { { STATE_MISC0 }, 'i' } | |
3231 | }; | |
3232 | ||
3233 | static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { | |
3234 | { { 6 /* art */ }, 'i' } | |
3235 | }; | |
3236 | ||
3237 | static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { | |
3238 | { { STATE_MISC0 }, 'o' } | |
3239 | }; | |
3240 | ||
3241 | static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { | |
3242 | { { 6 /* art */ }, 'm' } | |
3243 | }; | |
3244 | ||
3245 | static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { | |
3246 | { { STATE_MISC0 }, 'm' } | |
3247 | }; | |
3248 | ||
3249 | static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { | |
3250 | { { 6 /* art */ }, 'o' } | |
3251 | }; | |
3252 | ||
3253 | static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { | |
3254 | { { STATE_MISC1 }, 'i' } | |
3255 | }; | |
3256 | ||
3257 | static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { | |
3258 | { { 6 /* art */ }, 'i' } | |
3259 | }; | |
3260 | ||
3261 | static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { | |
3262 | { { STATE_MISC1 }, 'o' } | |
3263 | }; | |
3264 | ||
3265 | static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { | |
3266 | { { 6 /* art */ }, 'm' } | |
3267 | }; | |
3268 | ||
3269 | static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { | |
3270 | { { STATE_MISC1 }, 'm' } | |
3271 | }; | |
3272 | ||
3273 | static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { | |
3274 | { { 6 /* art */ }, 'o' } | |
3275 | }; | |
3276 | ||
3277 | static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { | |
3278 | { { 40 /* s */ }, 'i' } | |
3279 | }; | |
3280 | ||
3281 | static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { | |
3282 | { { STATE_PSWOE }, 'o' }, | |
3283 | { { STATE_PSCALLINC }, 'o' }, | |
3284 | { { STATE_PSOWB }, 'o' }, | |
3285 | { { STATE_PSUM }, 'o' }, | |
3286 | { { STATE_PSEXCM }, 'o' }, | |
3287 | { { STATE_PSINTLEVEL }, 'o' }, | |
3288 | { { STATE_EPC1 }, 'i' }, | |
3289 | { { STATE_EPC2 }, 'i' }, | |
3290 | { { STATE_EPC3 }, 'i' }, | |
3291 | { { STATE_EPC4 }, 'i' }, | |
3292 | { { STATE_EPS2 }, 'i' }, | |
3293 | { { STATE_EPS3 }, 'i' }, | |
3294 | { { STATE_EPS4 }, 'i' }, | |
3295 | { { STATE_InOCDMode }, 'm' } | |
3296 | }; | |
3297 | ||
3298 | static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { | |
3299 | { { 40 /* s */ }, 'i' } | |
3300 | }; | |
3301 | ||
3302 | static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { | |
3303 | { { STATE_PSINTLEVEL }, 'o' } | |
3304 | }; | |
3305 | ||
3306 | static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { | |
3307 | { { 6 /* art */ }, 'o' } | |
3308 | }; | |
3309 | ||
3310 | static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { | |
3311 | { { STATE_INTERRUPT }, 'i' } | |
3312 | }; | |
3313 | ||
3314 | static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { | |
3315 | { { 6 /* art */ }, 'i' } | |
3316 | }; | |
3317 | ||
3318 | static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { | |
3319 | { { STATE_XTSYNC }, 'o' }, | |
3320 | { { STATE_INTERRUPT }, 'm' } | |
3321 | }; | |
3322 | ||
3323 | static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { | |
3324 | { { 6 /* art */ }, 'i' } | |
3325 | }; | |
3326 | ||
3327 | static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { | |
3328 | { { STATE_XTSYNC }, 'o' }, | |
3329 | { { STATE_INTERRUPT }, 'm' } | |
3330 | }; | |
3331 | ||
3332 | static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { | |
3333 | { { 6 /* art */ }, 'o' } | |
3334 | }; | |
3335 | ||
3336 | static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { | |
3337 | { { STATE_INTENABLE }, 'i' } | |
3338 | }; | |
3339 | ||
3340 | static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { | |
3341 | { { 6 /* art */ }, 'i' } | |
3342 | }; | |
3343 | ||
3344 | static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { | |
3345 | { { STATE_INTENABLE }, 'o' } | |
3346 | }; | |
3347 | ||
3348 | static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { | |
3349 | { { 6 /* art */ }, 'm' } | |
3350 | }; | |
3351 | ||
3352 | static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { | |
3353 | { { STATE_INTENABLE }, 'm' } | |
3354 | }; | |
3355 | ||
3356 | static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { | |
3357 | { { 34 /* imms */ }, 'i' }, | |
3358 | { { 33 /* immt */ }, 'i' } | |
3359 | }; | |
3360 | ||
3361 | static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { | |
3362 | { { STATE_PSEXCM }, 'i' }, | |
3363 | { { STATE_PSINTLEVEL }, 'i' } | |
3364 | }; | |
3365 | ||
3366 | static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { | |
3367 | { { 34 /* imms */ }, 'i' } | |
3368 | }; | |
3369 | ||
3370 | static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { | |
3371 | { { STATE_PSEXCM }, 'i' }, | |
3372 | { { STATE_PSINTLEVEL }, 'i' } | |
3373 | }; | |
3374 | ||
3375 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { | |
3376 | { { 6 /* art */ }, 'o' } | |
3377 | }; | |
3378 | ||
3379 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { | |
3380 | { { STATE_DBREAKA0 }, 'i' } | |
3381 | }; | |
3382 | ||
3383 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { | |
3384 | { { 6 /* art */ }, 'i' } | |
3385 | }; | |
3386 | ||
3387 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { | |
3388 | { { STATE_DBREAKA0 }, 'o' }, | |
3389 | { { STATE_XTSYNC }, 'o' } | |
3390 | }; | |
3391 | ||
3392 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { | |
3393 | { { 6 /* art */ }, 'm' } | |
3394 | }; | |
3395 | ||
3396 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { | |
3397 | { { STATE_DBREAKA0 }, 'm' }, | |
3398 | { { STATE_XTSYNC }, 'o' } | |
3399 | }; | |
3400 | ||
3401 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { | |
3402 | { { 6 /* art */ }, 'o' } | |
3403 | }; | |
3404 | ||
3405 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { | |
3406 | { { STATE_DBREAKC0 }, 'i' } | |
3407 | }; | |
3408 | ||
3409 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { | |
3410 | { { 6 /* art */ }, 'i' } | |
3411 | }; | |
3412 | ||
3413 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { | |
3414 | { { STATE_DBREAKC0 }, 'o' }, | |
3415 | { { STATE_XTSYNC }, 'o' } | |
3416 | }; | |
3417 | ||
3418 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { | |
3419 | { { 6 /* art */ }, 'm' } | |
3420 | }; | |
3421 | ||
3422 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { | |
3423 | { { STATE_DBREAKC0 }, 'm' }, | |
3424 | { { STATE_XTSYNC }, 'o' } | |
3425 | }; | |
3426 | ||
3427 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { | |
3428 | { { 6 /* art */ }, 'o' } | |
3429 | }; | |
3430 | ||
3431 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { | |
3432 | { { STATE_DBREAKA1 }, 'i' } | |
3433 | }; | |
3434 | ||
3435 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { | |
3436 | { { 6 /* art */ }, 'i' } | |
3437 | }; | |
3438 | ||
3439 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { | |
3440 | { { STATE_DBREAKA1 }, 'o' }, | |
3441 | { { STATE_XTSYNC }, 'o' } | |
3442 | }; | |
3443 | ||
3444 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { | |
3445 | { { 6 /* art */ }, 'm' } | |
3446 | }; | |
3447 | ||
3448 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { | |
3449 | { { STATE_DBREAKA1 }, 'm' }, | |
3450 | { { STATE_XTSYNC }, 'o' } | |
3451 | }; | |
3452 | ||
3453 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { | |
3454 | { { 6 /* art */ }, 'o' } | |
3455 | }; | |
3456 | ||
3457 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { | |
3458 | { { STATE_DBREAKC1 }, 'i' } | |
3459 | }; | |
3460 | ||
3461 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { | |
3462 | { { 6 /* art */ }, 'i' } | |
3463 | }; | |
3464 | ||
3465 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { | |
3466 | { { STATE_DBREAKC1 }, 'o' }, | |
3467 | { { STATE_XTSYNC }, 'o' } | |
3468 | }; | |
3469 | ||
3470 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { | |
3471 | { { 6 /* art */ }, 'm' } | |
3472 | }; | |
3473 | ||
3474 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { | |
3475 | { { STATE_DBREAKC1 }, 'm' }, | |
3476 | { { STATE_XTSYNC }, 'o' } | |
3477 | }; | |
3478 | ||
3479 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { | |
3480 | { { 6 /* art */ }, 'o' } | |
3481 | }; | |
3482 | ||
3483 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { | |
3484 | { { STATE_IBREAKA0 }, 'i' } | |
3485 | }; | |
3486 | ||
3487 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { | |
3488 | { { 6 /* art */ }, 'i' } | |
3489 | }; | |
3490 | ||
3491 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { | |
3492 | { { STATE_IBREAKA0 }, 'o' } | |
3493 | }; | |
3494 | ||
3495 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { | |
3496 | { { 6 /* art */ }, 'm' } | |
3497 | }; | |
3498 | ||
3499 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { | |
3500 | { { STATE_IBREAKA0 }, 'm' } | |
3501 | }; | |
3502 | ||
3503 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { | |
3504 | { { 6 /* art */ }, 'o' } | |
3505 | }; | |
3506 | ||
3507 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { | |
3508 | { { STATE_IBREAKA1 }, 'i' } | |
3509 | }; | |
3510 | ||
3511 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { | |
3512 | { { 6 /* art */ }, 'i' } | |
3513 | }; | |
3514 | ||
3515 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { | |
3516 | { { STATE_IBREAKA1 }, 'o' } | |
3517 | }; | |
3518 | ||
3519 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { | |
3520 | { { 6 /* art */ }, 'm' } | |
3521 | }; | |
3522 | ||
3523 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { | |
3524 | { { STATE_IBREAKA1 }, 'm' } | |
3525 | }; | |
3526 | ||
3527 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { | |
3528 | { { 6 /* art */ }, 'o' } | |
3529 | }; | |
3530 | ||
3531 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { | |
3532 | { { STATE_IBREAKENABLE }, 'i' } | |
3533 | }; | |
3534 | ||
3535 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { | |
3536 | { { 6 /* art */ }, 'i' } | |
3537 | }; | |
3538 | ||
3539 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { | |
3540 | { { STATE_IBREAKENABLE }, 'o' } | |
3541 | }; | |
3542 | ||
3543 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { | |
3544 | { { 6 /* art */ }, 'm' } | |
3545 | }; | |
3546 | ||
3547 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { | |
3548 | { { STATE_IBREAKENABLE }, 'm' } | |
3549 | }; | |
3550 | ||
3551 | static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { | |
3552 | { { 6 /* art */ }, 'o' } | |
3553 | }; | |
3554 | ||
3555 | static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { | |
3556 | { { STATE_DEBUGCAUSE }, 'i' }, | |
3557 | { { STATE_DBNUM }, 'i' } | |
3558 | }; | |
3559 | ||
3560 | static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { | |
3561 | { { 6 /* art */ }, 'i' } | |
3562 | }; | |
3563 | ||
3564 | static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { | |
3565 | { { STATE_DEBUGCAUSE }, 'o' }, | |
3566 | { { STATE_DBNUM }, 'o' } | |
3567 | }; | |
3568 | ||
3569 | static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { | |
3570 | { { 6 /* art */ }, 'm' } | |
3571 | }; | |
3572 | ||
3573 | static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { | |
3574 | { { STATE_DEBUGCAUSE }, 'm' }, | |
3575 | { { STATE_DBNUM }, 'm' } | |
3576 | }; | |
3577 | ||
3578 | static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { | |
3579 | { { 6 /* art */ }, 'o' } | |
3580 | }; | |
3581 | ||
3582 | static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { | |
3583 | { { STATE_ICOUNT }, 'i' } | |
3584 | }; | |
3585 | ||
3586 | static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { | |
3587 | { { 6 /* art */ }, 'i' } | |
3588 | }; | |
3589 | ||
3590 | static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { | |
3591 | { { STATE_XTSYNC }, 'o' }, | |
3592 | { { STATE_ICOUNT }, 'o' } | |
3593 | }; | |
3594 | ||
3595 | static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { | |
3596 | { { 6 /* art */ }, 'm' } | |
3597 | }; | |
3598 | ||
3599 | static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { | |
3600 | { { STATE_XTSYNC }, 'o' }, | |
3601 | { { STATE_ICOUNT }, 'm' } | |
3602 | }; | |
3603 | ||
3604 | static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { | |
3605 | { { 6 /* art */ }, 'o' } | |
3606 | }; | |
3607 | ||
3608 | static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { | |
3609 | { { STATE_ICOUNTLEVEL }, 'i' } | |
3610 | }; | |
3611 | ||
3612 | static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { | |
3613 | { { 6 /* art */ }, 'i' } | |
3614 | }; | |
3615 | ||
3616 | static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { | |
3617 | { { STATE_ICOUNTLEVEL }, 'o' } | |
3618 | }; | |
3619 | ||
3620 | static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { | |
3621 | { { 6 /* art */ }, 'm' } | |
3622 | }; | |
3623 | ||
3624 | static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { | |
3625 | { { STATE_ICOUNTLEVEL }, 'm' } | |
3626 | }; | |
3627 | ||
3628 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { | |
3629 | { { 6 /* art */ }, 'o' } | |
3630 | }; | |
3631 | ||
3632 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { | |
3633 | { { STATE_DDR }, 'i' } | |
3634 | }; | |
3635 | ||
3636 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { | |
3637 | { { 6 /* art */ }, 'i' } | |
3638 | }; | |
3639 | ||
3640 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { | |
3641 | { { STATE_XTSYNC }, 'o' }, | |
3642 | { { STATE_DDR }, 'o' } | |
3643 | }; | |
3644 | ||
3645 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { | |
3646 | { { 6 /* art */ }, 'm' } | |
3647 | }; | |
3648 | ||
3649 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { | |
3650 | { { STATE_XTSYNC }, 'o' }, | |
3651 | { { STATE_DDR }, 'm' } | |
3652 | }; | |
3653 | ||
3654 | static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { | |
3655 | { { STATE_InOCDMode }, 'm' }, | |
3656 | { { STATE_EPC4 }, 'i' }, | |
3657 | { { STATE_PSWOE }, 'o' }, | |
3658 | { { STATE_PSCALLINC }, 'o' }, | |
3659 | { { STATE_PSOWB }, 'o' }, | |
3660 | { { STATE_PSUM }, 'o' }, | |
3661 | { { STATE_PSEXCM }, 'o' }, | |
3662 | { { STATE_PSINTLEVEL }, 'o' }, | |
3663 | { { STATE_EPS4 }, 'i' } | |
3664 | }; | |
3665 | ||
3666 | static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { | |
3667 | { { STATE_InOCDMode }, 'm' } | |
3668 | }; | |
3669 | ||
3670 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { | |
3671 | { { 6 /* art */ }, 'o' } | |
3672 | }; | |
3673 | ||
3674 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { | |
3675 | { { STATE_CCOUNT }, 'i' } | |
3676 | }; | |
3677 | ||
3678 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { | |
3679 | { { 6 /* art */ }, 'i' } | |
3680 | }; | |
3681 | ||
3682 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { | |
3683 | { { STATE_XTSYNC }, 'o' }, | |
3684 | { { STATE_CCOUNT }, 'o' } | |
3685 | }; | |
3686 | ||
3687 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { | |
3688 | { { 6 /* art */ }, 'm' } | |
3689 | }; | |
3690 | ||
3691 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { | |
3692 | { { STATE_XTSYNC }, 'o' }, | |
3693 | { { STATE_CCOUNT }, 'm' } | |
3694 | }; | |
3695 | ||
3696 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { | |
3697 | { { 6 /* art */ }, 'o' } | |
3698 | }; | |
3699 | ||
3700 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { | |
3701 | { { STATE_CCOMPARE0 }, 'i' } | |
3702 | }; | |
3703 | ||
3704 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { | |
3705 | { { 6 /* art */ }, 'i' } | |
3706 | }; | |
3707 | ||
3708 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { | |
3709 | { { STATE_CCOMPARE0 }, 'o' }, | |
3710 | { { STATE_INTERRUPT }, 'm' } | |
3711 | }; | |
3712 | ||
3713 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { | |
3714 | { { 6 /* art */ }, 'm' } | |
3715 | }; | |
3716 | ||
3717 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { | |
3718 | { { STATE_CCOMPARE0 }, 'm' }, | |
3719 | { { STATE_INTERRUPT }, 'm' } | |
3720 | }; | |
3721 | ||
3722 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { | |
3723 | { { 6 /* art */ }, 'o' } | |
3724 | }; | |
3725 | ||
3726 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { | |
3727 | { { STATE_CCOMPARE1 }, 'i' } | |
3728 | }; | |
3729 | ||
3730 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { | |
3731 | { { 6 /* art */ }, 'i' } | |
3732 | }; | |
3733 | ||
3734 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { | |
3735 | { { STATE_CCOMPARE1 }, 'o' }, | |
3736 | { { STATE_INTERRUPT }, 'm' } | |
3737 | }; | |
3738 | ||
3739 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { | |
3740 | { { 6 /* art */ }, 'm' } | |
3741 | }; | |
3742 | ||
3743 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { | |
3744 | { { STATE_CCOMPARE1 }, 'm' }, | |
3745 | { { STATE_INTERRUPT }, 'm' } | |
3746 | }; | |
3747 | ||
3748 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { | |
3749 | { { 6 /* art */ }, 'o' } | |
3750 | }; | |
3751 | ||
3752 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { | |
3753 | { { STATE_CCOMPARE2 }, 'i' } | |
3754 | }; | |
3755 | ||
3756 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { | |
3757 | { { 6 /* art */ }, 'i' } | |
3758 | }; | |
3759 | ||
3760 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { | |
3761 | { { STATE_CCOMPARE2 }, 'o' }, | |
3762 | { { STATE_INTERRUPT }, 'm' } | |
3763 | }; | |
3764 | ||
3765 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { | |
3766 | { { 6 /* art */ }, 'm' } | |
3767 | }; | |
3768 | ||
3769 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { | |
3770 | { { STATE_CCOMPARE2 }, 'm' }, | |
3771 | { { STATE_INTERRUPT }, 'm' } | |
3772 | }; | |
3773 | ||
3774 | static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { | |
3775 | { { 4 /* ars */ }, 'i' }, | |
3776 | { { 21 /* uimm8x4 */ }, 'i' } | |
3777 | }; | |
3778 | ||
3779 | static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { | |
3780 | { { 4 /* ars */ }, 'i' }, | |
3781 | { { 21 /* uimm8x4 */ }, 'i' } | |
3782 | }; | |
3783 | ||
3784 | static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { | |
3785 | { { 6 /* art */ }, 'o' }, | |
3786 | { { 4 /* ars */ }, 'i' } | |
3787 | }; | |
3788 | ||
3789 | static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { | |
3790 | { { 6 /* art */ }, 'i' }, | |
3791 | { { 4 /* ars */ }, 'i' } | |
3792 | }; | |
3793 | ||
3794 | static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { | |
3795 | { { 4 /* ars */ }, 'i' }, | |
3796 | { { 21 /* uimm8x4 */ }, 'i' } | |
3797 | }; | |
3798 | ||
3799 | static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { | |
3800 | { { 4 /* ars */ }, 'i' }, | |
3801 | { { 22 /* uimm4x16 */ }, 'i' } | |
3802 | }; | |
3803 | ||
3804 | static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { | |
3805 | { { 4 /* ars */ }, 'i' }, | |
3806 | { { 21 /* uimm8x4 */ }, 'i' } | |
3807 | }; | |
3808 | ||
3809 | static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { | |
3810 | { { 4 /* ars */ }, 'i' }, | |
3811 | { { 21 /* uimm8x4 */ }, 'i' } | |
3812 | }; | |
3813 | ||
3814 | static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { | |
3815 | { { 6 /* art */ }, 'i' }, | |
3816 | { { 4 /* ars */ }, 'i' } | |
3817 | }; | |
3818 | ||
3819 | static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { | |
3820 | { { 6 /* art */ }, 'o' }, | |
3821 | { { 4 /* ars */ }, 'i' } | |
3822 | }; | |
3823 | ||
3824 | static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { | |
3825 | { { 4 /* ars */ }, 'i' } | |
3826 | }; | |
3827 | ||
3828 | static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { | |
3829 | { { STATE_XTSYNC }, 'o' } | |
3830 | }; | |
3831 | ||
3832 | static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { | |
3833 | { { 6 /* art */ }, 'o' }, | |
3834 | { { 4 /* ars */ }, 'i' } | |
3835 | }; | |
3836 | ||
3837 | static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { | |
3838 | { { 6 /* art */ }, 'i' }, | |
3839 | { { 4 /* ars */ }, 'i' } | |
3840 | }; | |
3841 | ||
3842 | static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { | |
3843 | { { STATE_XTSYNC }, 'o' } | |
3844 | }; | |
3845 | ||
3846 | static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { | |
3847 | { { 4 /* ars */ }, 'i' } | |
3848 | }; | |
3849 | ||
3850 | static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { | |
3851 | { { 6 /* art */ }, 'o' }, | |
3852 | { { 4 /* ars */ }, 'i' } | |
3853 | }; | |
3854 | ||
3855 | static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { | |
3856 | { { 6 /* art */ }, 'i' }, | |
3857 | { { 4 /* ars */ }, 'i' } | |
3858 | }; | |
3859 | ||
3860 | static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { | |
3861 | { { 6 /* art */ }, 'o' }, | |
3862 | { { 4 /* ars */ }, 'i' } | |
3863 | }; | |
3864 | ||
3865 | static xtensa_iclass_internal iclasses[] = { | |
3866 | { 0, 0 /* xt_iclass_excw */, | |
3867 | 0, 0, 0, 0 }, | |
3868 | { 0, 0 /* xt_iclass_rfe */, | |
3869 | 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, | |
3870 | { 0, 0 /* xt_iclass_rfde */, | |
3871 | 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, | |
3872 | { 0, 0 /* xt_iclass_syscall */, | |
3873 | 0, 0, 0, 0 }, | |
3874 | { 0, 0 /* xt_iclass_simcall */, | |
3875 | 0, 0, 0, 0 }, | |
3876 | { 2, Iclass_xt_iclass_call12_args, | |
3877 | 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, | |
3878 | { 2, Iclass_xt_iclass_call8_args, | |
3879 | 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, | |
3880 | { 2, Iclass_xt_iclass_call4_args, | |
3881 | 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, | |
3882 | { 2, Iclass_xt_iclass_callx12_args, | |
3883 | 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, | |
3884 | { 2, Iclass_xt_iclass_callx8_args, | |
3885 | 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, | |
3886 | { 2, Iclass_xt_iclass_callx4_args, | |
3887 | 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, | |
3888 | { 3, Iclass_xt_iclass_entry_args, | |
3889 | 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, | |
3890 | { 2, Iclass_xt_iclass_movsp_args, | |
3891 | 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, | |
3892 | { 1, Iclass_xt_iclass_rotw_args, | |
3893 | 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, | |
3894 | { 1, Iclass_xt_iclass_retw_args, | |
3895 | 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, | |
3896 | { 0, 0 /* xt_iclass_rfwou */, | |
3897 | 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, | |
3898 | { 3, Iclass_xt_iclass_l32e_args, | |
3899 | 0, 0, 0, 0 }, | |
3900 | { 3, Iclass_xt_iclass_s32e_args, | |
3901 | 0, 0, 0, 0 }, | |
3902 | { 1, Iclass_xt_iclass_rsr_windowbase_args, | |
3903 | 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, | |
3904 | { 1, Iclass_xt_iclass_wsr_windowbase_args, | |
3905 | 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, | |
3906 | { 1, Iclass_xt_iclass_xsr_windowbase_args, | |
3907 | 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, | |
3908 | { 1, Iclass_xt_iclass_rsr_windowstart_args, | |
3909 | 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, | |
3910 | { 1, Iclass_xt_iclass_wsr_windowstart_args, | |
3911 | 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, | |
3912 | { 1, Iclass_xt_iclass_xsr_windowstart_args, | |
3913 | 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, | |
3914 | { 3, Iclass_xt_iclass_add_n_args, | |
3915 | 0, 0, 0, 0 }, | |
3916 | { 3, Iclass_xt_iclass_addi_n_args, | |
3917 | 0, 0, 0, 0 }, | |
3918 | { 2, Iclass_xt_iclass_bz6_args, | |
3919 | 0, 0, 0, 0 }, | |
3920 | { 0, 0 /* xt_iclass_ill_n */, | |
3921 | 0, 0, 0, 0 }, | |
3922 | { 3, Iclass_xt_iclass_loadi4_args, | |
3923 | 0, 0, 0, 0 }, | |
3924 | { 2, Iclass_xt_iclass_mov_n_args, | |
3925 | 0, 0, 0, 0 }, | |
3926 | { 2, Iclass_xt_iclass_movi_n_args, | |
3927 | 0, 0, 0, 0 }, | |
3928 | { 0, 0 /* xt_iclass_nopn */, | |
3929 | 0, 0, 0, 0 }, | |
3930 | { 1, Iclass_xt_iclass_retn_args, | |
3931 | 0, 0, 0, 0 }, | |
3932 | { 3, Iclass_xt_iclass_storei4_args, | |
3933 | 0, 0, 0, 0 }, | |
3934 | { 3, Iclass_xt_iclass_addi_args, | |
3935 | 0, 0, 0, 0 }, | |
3936 | { 3, Iclass_xt_iclass_addmi_args, | |
3937 | 0, 0, 0, 0 }, | |
3938 | { 3, Iclass_xt_iclass_addsub_args, | |
3939 | 0, 0, 0, 0 }, | |
3940 | { 3, Iclass_xt_iclass_bit_args, | |
3941 | 0, 0, 0, 0 }, | |
3942 | { 3, Iclass_xt_iclass_bsi8_args, | |
3943 | 0, 0, 0, 0 }, | |
3944 | { 3, Iclass_xt_iclass_bsi8b_args, | |
3945 | 0, 0, 0, 0 }, | |
3946 | { 3, Iclass_xt_iclass_bsi8u_args, | |
3947 | 0, 0, 0, 0 }, | |
3948 | { 3, Iclass_xt_iclass_bst8_args, | |
3949 | 0, 0, 0, 0 }, | |
3950 | { 2, Iclass_xt_iclass_bsz12_args, | |
3951 | 0, 0, 0, 0 }, | |
3952 | { 2, Iclass_xt_iclass_call0_args, | |
3953 | 0, 0, 0, 0 }, | |
3954 | { 2, Iclass_xt_iclass_callx0_args, | |
3955 | 0, 0, 0, 0 }, | |
3956 | { 4, Iclass_xt_iclass_exti_args, | |
3957 | 0, 0, 0, 0 }, | |
3958 | { 0, 0 /* xt_iclass_ill */, | |
3959 | 0, 0, 0, 0 }, | |
3960 | { 1, Iclass_xt_iclass_jump_args, | |
3961 | 0, 0, 0, 0 }, | |
3962 | { 1, Iclass_xt_iclass_jumpx_args, | |
3963 | 0, 0, 0, 0 }, | |
3964 | { 3, Iclass_xt_iclass_l16ui_args, | |
3965 | 0, 0, 0, 0 }, | |
3966 | { 3, Iclass_xt_iclass_l16si_args, | |
3967 | 0, 0, 0, 0 }, | |
3968 | { 3, Iclass_xt_iclass_l32i_args, | |
3969 | 0, 0, 0, 0 }, | |
3970 | { 2, Iclass_xt_iclass_l32r_args, | |
3971 | 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, | |
3972 | { 3, Iclass_xt_iclass_l8i_args, | |
3973 | 0, 0, 0, 0 }, | |
3974 | { 2, Iclass_xt_iclass_loop_args, | |
3975 | 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, | |
3976 | { 2, Iclass_xt_iclass_loopz_args, | |
3977 | 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, | |
3978 | { 2, Iclass_xt_iclass_movi_args, | |
3979 | 0, 0, 0, 0 }, | |
3980 | { 3, Iclass_xt_iclass_movz_args, | |
3981 | 0, 0, 0, 0 }, | |
3982 | { 2, Iclass_xt_iclass_neg_args, | |
3983 | 0, 0, 0, 0 }, | |
3984 | { 0, 0 /* xt_iclass_nop */, | |
3985 | 0, 0, 0, 0 }, | |
3986 | { 1, Iclass_xt_iclass_return_args, | |
3987 | 0, 0, 0, 0 }, | |
3988 | { 3, Iclass_xt_iclass_s16i_args, | |
3989 | 0, 0, 0, 0 }, | |
3990 | { 3, Iclass_xt_iclass_s32i_args, | |
3991 | 0, 0, 0, 0 }, | |
3992 | { 3, Iclass_xt_iclass_s8i_args, | |
3993 | 0, 0, 0, 0 }, | |
3994 | { 1, Iclass_xt_iclass_sar_args, | |
3995 | 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, | |
3996 | { 1, Iclass_xt_iclass_sari_args, | |
3997 | 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, | |
3998 | { 2, Iclass_xt_iclass_shifts_args, | |
3999 | 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, | |
4000 | { 3, Iclass_xt_iclass_shiftst_args, | |
4001 | 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, | |
4002 | { 2, Iclass_xt_iclass_shiftt_args, | |
4003 | 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, | |
4004 | { 3, Iclass_xt_iclass_slli_args, | |
4005 | 0, 0, 0, 0 }, | |
4006 | { 3, Iclass_xt_iclass_srai_args, | |
4007 | 0, 0, 0, 0 }, | |
4008 | { 3, Iclass_xt_iclass_srli_args, | |
4009 | 0, 0, 0, 0 }, | |
4010 | { 0, 0 /* xt_iclass_memw */, | |
4011 | 0, 0, 0, 0 }, | |
4012 | { 0, 0 /* xt_iclass_extw */, | |
4013 | 0, 0, 0, 0 }, | |
4014 | { 0, 0 /* xt_iclass_isync */, | |
4015 | 0, 0, 0, 0 }, | |
4016 | { 0, 0 /* xt_iclass_sync */, | |
4017 | 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, | |
4018 | { 2, Iclass_xt_iclass_rsil_args, | |
4019 | 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, | |
4020 | { 1, Iclass_xt_iclass_rsr_lend_args, | |
4021 | 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, | |
4022 | { 1, Iclass_xt_iclass_wsr_lend_args, | |
4023 | 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, | |
4024 | { 1, Iclass_xt_iclass_xsr_lend_args, | |
4025 | 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, | |
4026 | { 1, Iclass_xt_iclass_rsr_lcount_args, | |
4027 | 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, | |
4028 | { 1, Iclass_xt_iclass_wsr_lcount_args, | |
4029 | 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, | |
4030 | { 1, Iclass_xt_iclass_xsr_lcount_args, | |
4031 | 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, | |
4032 | { 1, Iclass_xt_iclass_rsr_lbeg_args, | |
4033 | 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, | |
4034 | { 1, Iclass_xt_iclass_wsr_lbeg_args, | |
4035 | 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, | |
4036 | { 1, Iclass_xt_iclass_xsr_lbeg_args, | |
4037 | 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, | |
4038 | { 1, Iclass_xt_iclass_rsr_sar_args, | |
4039 | 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, | |
4040 | { 1, Iclass_xt_iclass_wsr_sar_args, | |
4041 | 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, | |
4042 | { 1, Iclass_xt_iclass_xsr_sar_args, | |
4043 | 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, | |
4044 | { 1, Iclass_xt_iclass_rsr_litbase_args, | |
4045 | 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, | |
4046 | { 1, Iclass_xt_iclass_wsr_litbase_args, | |
4047 | 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, | |
4048 | { 1, Iclass_xt_iclass_xsr_litbase_args, | |
4049 | 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, | |
4050 | { 1, Iclass_xt_iclass_rsr_176_args, | |
4051 | 0, 0, 0, 0 }, | |
4052 | { 1, Iclass_xt_iclass_rsr_208_args, | |
4053 | 0, 0, 0, 0 }, | |
4054 | { 1, Iclass_xt_iclass_rsr_ps_args, | |
4055 | 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, | |
4056 | { 1, Iclass_xt_iclass_wsr_ps_args, | |
4057 | 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, | |
4058 | { 1, Iclass_xt_iclass_xsr_ps_args, | |
4059 | 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, | |
4060 | { 1, Iclass_xt_iclass_rsr_epc1_args, | |
4061 | 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, | |
4062 | { 1, Iclass_xt_iclass_wsr_epc1_args, | |
4063 | 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, | |
4064 | { 1, Iclass_xt_iclass_xsr_epc1_args, | |
4065 | 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, | |
4066 | { 1, Iclass_xt_iclass_rsr_excsave1_args, | |
4067 | 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, | |
4068 | { 1, Iclass_xt_iclass_wsr_excsave1_args, | |
4069 | 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, | |
4070 | { 1, Iclass_xt_iclass_xsr_excsave1_args, | |
4071 | 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, | |
4072 | { 1, Iclass_xt_iclass_rsr_epc2_args, | |
4073 | 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, | |
4074 | { 1, Iclass_xt_iclass_wsr_epc2_args, | |
4075 | 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, | |
4076 | { 1, Iclass_xt_iclass_xsr_epc2_args, | |
4077 | 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, | |
4078 | { 1, Iclass_xt_iclass_rsr_excsave2_args, | |
4079 | 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, | |
4080 | { 1, Iclass_xt_iclass_wsr_excsave2_args, | |
4081 | 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, | |
4082 | { 1, Iclass_xt_iclass_xsr_excsave2_args, | |
4083 | 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, | |
4084 | { 1, Iclass_xt_iclass_rsr_epc3_args, | |
4085 | 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, | |
4086 | { 1, Iclass_xt_iclass_wsr_epc3_args, | |
4087 | 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, | |
4088 | { 1, Iclass_xt_iclass_xsr_epc3_args, | |
4089 | 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, | |
4090 | { 1, Iclass_xt_iclass_rsr_excsave3_args, | |
4091 | 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, | |
4092 | { 1, Iclass_xt_iclass_wsr_excsave3_args, | |
4093 | 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, | |
4094 | { 1, Iclass_xt_iclass_xsr_excsave3_args, | |
4095 | 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, | |
4096 | { 1, Iclass_xt_iclass_rsr_epc4_args, | |
4097 | 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, | |
4098 | { 1, Iclass_xt_iclass_wsr_epc4_args, | |
4099 | 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, | |
4100 | { 1, Iclass_xt_iclass_xsr_epc4_args, | |
4101 | 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, | |
4102 | { 1, Iclass_xt_iclass_rsr_excsave4_args, | |
4103 | 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, | |
4104 | { 1, Iclass_xt_iclass_wsr_excsave4_args, | |
4105 | 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, | |
4106 | { 1, Iclass_xt_iclass_xsr_excsave4_args, | |
4107 | 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, | |
4108 | { 1, Iclass_xt_iclass_rsr_eps2_args, | |
4109 | 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, | |
4110 | { 1, Iclass_xt_iclass_wsr_eps2_args, | |
4111 | 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, | |
4112 | { 1, Iclass_xt_iclass_xsr_eps2_args, | |
4113 | 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, | |
4114 | { 1, Iclass_xt_iclass_rsr_eps3_args, | |
4115 | 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, | |
4116 | { 1, Iclass_xt_iclass_wsr_eps3_args, | |
4117 | 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, | |
4118 | { 1, Iclass_xt_iclass_xsr_eps3_args, | |
4119 | 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, | |
4120 | { 1, Iclass_xt_iclass_rsr_eps4_args, | |
4121 | 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, | |
4122 | { 1, Iclass_xt_iclass_wsr_eps4_args, | |
4123 | 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, | |
4124 | { 1, Iclass_xt_iclass_xsr_eps4_args, | |
4125 | 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, | |
4126 | { 1, Iclass_xt_iclass_rsr_excvaddr_args, | |
4127 | 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, | |
4128 | { 1, Iclass_xt_iclass_wsr_excvaddr_args, | |
4129 | 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, | |
4130 | { 1, Iclass_xt_iclass_xsr_excvaddr_args, | |
4131 | 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, | |
4132 | { 1, Iclass_xt_iclass_rsr_depc_args, | |
4133 | 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, | |
4134 | { 1, Iclass_xt_iclass_wsr_depc_args, | |
4135 | 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, | |
4136 | { 1, Iclass_xt_iclass_xsr_depc_args, | |
4137 | 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, | |
4138 | { 1, Iclass_xt_iclass_rsr_exccause_args, | |
4139 | 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, | |
4140 | { 1, Iclass_xt_iclass_wsr_exccause_args, | |
4141 | 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, | |
4142 | { 1, Iclass_xt_iclass_xsr_exccause_args, | |
4143 | 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, | |
4144 | { 1, Iclass_xt_iclass_rsr_misc0_args, | |
4145 | 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, | |
4146 | { 1, Iclass_xt_iclass_wsr_misc0_args, | |
4147 | 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, | |
4148 | { 1, Iclass_xt_iclass_xsr_misc0_args, | |
4149 | 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, | |
4150 | { 1, Iclass_xt_iclass_rsr_misc1_args, | |
4151 | 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, | |
4152 | { 1, Iclass_xt_iclass_wsr_misc1_args, | |
4153 | 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, | |
4154 | { 1, Iclass_xt_iclass_xsr_misc1_args, | |
4155 | 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, | |
4156 | { 1, Iclass_xt_iclass_rsr_prid_args, | |
4157 | 0, 0, 0, 0 }, | |
4158 | { 1, Iclass_xt_iclass_rfi_args, | |
4159 | 14, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, | |
4160 | { 1, Iclass_xt_iclass_wait_args, | |
4161 | 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, | |
4162 | { 1, Iclass_xt_iclass_rsr_interrupt_args, | |
4163 | 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, | |
4164 | { 1, Iclass_xt_iclass_wsr_intset_args, | |
4165 | 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, | |
4166 | { 1, Iclass_xt_iclass_wsr_intclear_args, | |
4167 | 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, | |
4168 | { 1, Iclass_xt_iclass_rsr_intenable_args, | |
4169 | 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, | |
4170 | { 1, Iclass_xt_iclass_wsr_intenable_args, | |
4171 | 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, | |
4172 | { 1, Iclass_xt_iclass_xsr_intenable_args, | |
4173 | 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, | |
4174 | { 2, Iclass_xt_iclass_break_args, | |
4175 | 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, | |
4176 | { 1, Iclass_xt_iclass_break_n_args, | |
4177 | 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, | |
4178 | { 1, Iclass_xt_iclass_rsr_dbreaka0_args, | |
4179 | 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, | |
4180 | { 1, Iclass_xt_iclass_wsr_dbreaka0_args, | |
4181 | 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, | |
4182 | { 1, Iclass_xt_iclass_xsr_dbreaka0_args, | |
4183 | 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, | |
4184 | { 1, Iclass_xt_iclass_rsr_dbreakc0_args, | |
4185 | 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, | |
4186 | { 1, Iclass_xt_iclass_wsr_dbreakc0_args, | |
4187 | 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, | |
4188 | { 1, Iclass_xt_iclass_xsr_dbreakc0_args, | |
4189 | 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, | |
4190 | { 1, Iclass_xt_iclass_rsr_dbreaka1_args, | |
4191 | 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, | |
4192 | { 1, Iclass_xt_iclass_wsr_dbreaka1_args, | |
4193 | 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, | |
4194 | { 1, Iclass_xt_iclass_xsr_dbreaka1_args, | |
4195 | 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, | |
4196 | { 1, Iclass_xt_iclass_rsr_dbreakc1_args, | |
4197 | 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, | |
4198 | { 1, Iclass_xt_iclass_wsr_dbreakc1_args, | |
4199 | 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, | |
4200 | { 1, Iclass_xt_iclass_xsr_dbreakc1_args, | |
4201 | 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, | |
4202 | { 1, Iclass_xt_iclass_rsr_ibreaka0_args, | |
4203 | 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, | |
4204 | { 1, Iclass_xt_iclass_wsr_ibreaka0_args, | |
4205 | 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, | |
4206 | { 1, Iclass_xt_iclass_xsr_ibreaka0_args, | |
4207 | 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, | |
4208 | { 1, Iclass_xt_iclass_rsr_ibreaka1_args, | |
4209 | 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, | |
4210 | { 1, Iclass_xt_iclass_wsr_ibreaka1_args, | |
4211 | 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, | |
4212 | { 1, Iclass_xt_iclass_xsr_ibreaka1_args, | |
4213 | 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, | |
4214 | { 1, Iclass_xt_iclass_rsr_ibreakenable_args, | |
4215 | 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, | |
4216 | { 1, Iclass_xt_iclass_wsr_ibreakenable_args, | |
4217 | 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, | |
4218 | { 1, Iclass_xt_iclass_xsr_ibreakenable_args, | |
4219 | 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, | |
4220 | { 1, Iclass_xt_iclass_rsr_debugcause_args, | |
4221 | 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, | |
4222 | { 1, Iclass_xt_iclass_wsr_debugcause_args, | |
4223 | 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, | |
4224 | { 1, Iclass_xt_iclass_xsr_debugcause_args, | |
4225 | 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, | |
4226 | { 1, Iclass_xt_iclass_rsr_icount_args, | |
4227 | 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, | |
4228 | { 1, Iclass_xt_iclass_wsr_icount_args, | |
4229 | 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, | |
4230 | { 1, Iclass_xt_iclass_xsr_icount_args, | |
4231 | 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, | |
4232 | { 1, Iclass_xt_iclass_rsr_icountlevel_args, | |
4233 | 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, | |
4234 | { 1, Iclass_xt_iclass_wsr_icountlevel_args, | |
4235 | 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, | |
4236 | { 1, Iclass_xt_iclass_xsr_icountlevel_args, | |
4237 | 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, | |
4238 | { 1, Iclass_xt_iclass_rsr_ddr_args, | |
4239 | 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, | |
4240 | { 1, Iclass_xt_iclass_wsr_ddr_args, | |
4241 | 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, | |
4242 | { 1, Iclass_xt_iclass_xsr_ddr_args, | |
4243 | 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, | |
4244 | { 0, 0 /* xt_iclass_rfdo */, | |
4245 | 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, | |
4246 | { 0, 0 /* xt_iclass_rfdd */, | |
4247 | 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, | |
4248 | { 1, Iclass_xt_iclass_rsr_ccount_args, | |
4249 | 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, | |
4250 | { 1, Iclass_xt_iclass_wsr_ccount_args, | |
4251 | 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, | |
4252 | { 1, Iclass_xt_iclass_xsr_ccount_args, | |
4253 | 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, | |
4254 | { 1, Iclass_xt_iclass_rsr_ccompare0_args, | |
4255 | 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, | |
4256 | { 1, Iclass_xt_iclass_wsr_ccompare0_args, | |
4257 | 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, | |
4258 | { 1, Iclass_xt_iclass_xsr_ccompare0_args, | |
4259 | 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, | |
4260 | { 1, Iclass_xt_iclass_rsr_ccompare1_args, | |
4261 | 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, | |
4262 | { 1, Iclass_xt_iclass_wsr_ccompare1_args, | |
4263 | 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, | |
4264 | { 1, Iclass_xt_iclass_xsr_ccompare1_args, | |
4265 | 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, | |
4266 | { 1, Iclass_xt_iclass_rsr_ccompare2_args, | |
4267 | 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, | |
4268 | { 1, Iclass_xt_iclass_wsr_ccompare2_args, | |
4269 | 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, | |
4270 | { 1, Iclass_xt_iclass_xsr_ccompare2_args, | |
4271 | 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, | |
4272 | { 2, Iclass_xt_iclass_icache_args, | |
4273 | 0, 0, 0, 0 }, | |
4274 | { 2, Iclass_xt_iclass_icache_inv_args, | |
4275 | 0, 0, 0, 0 }, | |
4276 | { 2, Iclass_xt_iclass_licx_args, | |
4277 | 0, 0, 0, 0 }, | |
4278 | { 2, Iclass_xt_iclass_sicx_args, | |
4279 | 0, 0, 0, 0 }, | |
4280 | { 2, Iclass_xt_iclass_dcache_args, | |
4281 | 0, 0, 0, 0 }, | |
4282 | { 2, Iclass_xt_iclass_dcache_ind_args, | |
4283 | 0, 0, 0, 0 }, | |
4284 | { 2, Iclass_xt_iclass_dcache_inv_args, | |
4285 | 0, 0, 0, 0 }, | |
4286 | { 2, Iclass_xt_iclass_dpf_args, | |
4287 | 0, 0, 0, 0 }, | |
4288 | { 2, Iclass_xt_iclass_sdct_args, | |
4289 | 0, 0, 0, 0 }, | |
4290 | { 2, Iclass_xt_iclass_ldct_args, | |
4291 | 0, 0, 0, 0 }, | |
4292 | { 1, Iclass_xt_iclass_idtlb_args, | |
4293 | 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, | |
4294 | { 2, Iclass_xt_iclass_rdtlb_args, | |
4295 | 0, 0, 0, 0 }, | |
4296 | { 2, Iclass_xt_iclass_wdtlb_args, | |
4297 | 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, | |
4298 | { 1, Iclass_xt_iclass_iitlb_args, | |
4299 | 0, 0, 0, 0 }, | |
4300 | { 2, Iclass_xt_iclass_ritlb_args, | |
4301 | 0, 0, 0, 0 }, | |
4302 | { 2, Iclass_xt_iclass_witlb_args, | |
4303 | 0, 0, 0, 0 }, | |
4304 | { 2, Iclass_xt_iclass_nsa_args, | |
4305 | 0, 0, 0, 0 } | |
4306 | }; | |
4307 | ||
4308 | \f | |
4309 | /* Opcode encodings. */ | |
4310 | ||
4311 | static void | |
4312 | Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4313 | { | |
4314 | slotbuf[0] = 0x80200; | |
4315 | } | |
4316 | ||
4317 | static void | |
4318 | Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4319 | { | |
4320 | slotbuf[0] = 0x300; | |
4321 | } | |
4322 | ||
4323 | static void | |
4324 | Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4325 | { | |
4326 | slotbuf[0] = 0x2300; | |
4327 | } | |
4328 | ||
4329 | static void | |
4330 | Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4331 | { | |
4332 | slotbuf[0] = 0x500; | |
4333 | } | |
4334 | ||
4335 | static void | |
4336 | Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4337 | { | |
4338 | slotbuf[0] = 0x1500; | |
4339 | } | |
4340 | ||
4341 | static void | |
4342 | Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4343 | { | |
4344 | slotbuf[0] = 0x5c0000; | |
4345 | } | |
4346 | ||
4347 | static void | |
4348 | Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4349 | { | |
4350 | slotbuf[0] = 0x580000; | |
4351 | } | |
4352 | ||
4353 | static void | |
4354 | Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4355 | { | |
4356 | slotbuf[0] = 0x540000; | |
4357 | } | |
4358 | ||
4359 | static void | |
4360 | Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4361 | { | |
4362 | slotbuf[0] = 0xf0000; | |
4363 | } | |
4364 | ||
4365 | static void | |
4366 | Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4367 | { | |
4368 | slotbuf[0] = 0xb0000; | |
4369 | } | |
4370 | ||
4371 | static void | |
4372 | Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4373 | { | |
4374 | slotbuf[0] = 0x70000; | |
4375 | } | |
4376 | ||
4377 | static void | |
4378 | Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4379 | { | |
4380 | slotbuf[0] = 0x6c0000; | |
4381 | } | |
4382 | ||
4383 | static void | |
4384 | Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4385 | { | |
4386 | slotbuf[0] = 0x100; | |
4387 | } | |
4388 | ||
4389 | static void | |
4390 | Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4391 | { | |
4392 | slotbuf[0] = 0x804; | |
4393 | } | |
4394 | ||
4395 | static void | |
4396 | Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4397 | { | |
4398 | slotbuf[0] = 0x60000; | |
4399 | } | |
4400 | ||
4401 | static void | |
4402 | Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) | |
4403 | { | |
4404 | slotbuf[0] = 0xd10f; | |
4405 | } | |
4406 | ||
4407 | static void | |
4408 | Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4409 | { | |
4410 | slotbuf[0] = 0x4300; | |
4411 | } | |
4412 | ||
4413 | static void | |
4414 | Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4415 | { | |
4416 | slotbuf[0] = 0x5300; | |
4417 | } | |
4418 | ||
4419 | static void | |
4420 | Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4421 | { | |
4422 | slotbuf[0] = 0x90; | |
4423 | } | |
4424 | ||
4425 | static void | |
4426 | Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4427 | { | |
4428 | slotbuf[0] = 0x94; | |
4429 | } | |
4430 | ||
4431 | static void | |
4432 | Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4433 | { | |
4434 | slotbuf[0] = 0x4830; | |
4435 | } | |
4436 | ||
4437 | static void | |
4438 | Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4439 | { | |
4440 | slotbuf[0] = 0x4831; | |
4441 | } | |
4442 | ||
4443 | static void | |
4444 | Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4445 | { | |
4446 | slotbuf[0] = 0x4816; | |
4447 | } | |
4448 | ||
4449 | static void | |
4450 | Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4451 | { | |
4452 | slotbuf[0] = 0x4930; | |
4453 | } | |
4454 | ||
4455 | static void | |
4456 | Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4457 | { | |
4458 | slotbuf[0] = 0x4931; | |
4459 | } | |
4460 | ||
4461 | static void | |
4462 | Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4463 | { | |
4464 | slotbuf[0] = 0x4916; | |
4465 | } | |
4466 | ||
4467 | static void | |
4468 | Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) | |
4469 | { | |
4470 | slotbuf[0] = 0xa000; | |
4471 | } | |
4472 | ||
4473 | static void | |
4474 | Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) | |
4475 | { | |
4476 | slotbuf[0] = 0xb000; | |
4477 | } | |
4478 | ||
4479 | static void | |
4480 | Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) | |
4481 | { | |
4482 | slotbuf[0] = 0xc800; | |
4483 | } | |
4484 | ||
4485 | static void | |
4486 | Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) | |
4487 | { | |
4488 | slotbuf[0] = 0xcc00; | |
4489 | } | |
4490 | ||
4491 | static void | |
4492 | Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) | |
4493 | { | |
4494 | slotbuf[0] = 0xd60f; | |
4495 | } | |
4496 | ||
4497 | static void | |
4498 | Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) | |
4499 | { | |
4500 | slotbuf[0] = 0x8000; | |
4501 | } | |
4502 | ||
4503 | static void | |
4504 | Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) | |
4505 | { | |
4506 | slotbuf[0] = 0xd000; | |
4507 | } | |
4508 | ||
4509 | static void | |
4510 | Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) | |
4511 | { | |
4512 | slotbuf[0] = 0xc000; | |
4513 | } | |
4514 | ||
4515 | static void | |
4516 | Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) | |
4517 | { | |
4518 | slotbuf[0] = 0xd30f; | |
4519 | } | |
4520 | ||
4521 | static void | |
4522 | Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) | |
4523 | { | |
4524 | slotbuf[0] = 0xd00f; | |
4525 | } | |
4526 | ||
4527 | static void | |
4528 | Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) | |
4529 | { | |
4530 | slotbuf[0] = 0x9000; | |
4531 | } | |
4532 | ||
4533 | static void | |
4534 | Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4535 | { | |
4536 | slotbuf[0] = 0x200c00; | |
4537 | } | |
4538 | ||
4539 | static void | |
4540 | Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4541 | { | |
4542 | slotbuf[0] = 0x200d00; | |
4543 | } | |
4544 | ||
4545 | static void | |
4546 | Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4547 | { | |
4548 | slotbuf[0] = 0x8; | |
4549 | } | |
4550 | ||
4551 | static void | |
4552 | Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4553 | { | |
4554 | slotbuf[0] = 0xc; | |
4555 | } | |
4556 | ||
4557 | static void | |
4558 | Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4559 | { | |
4560 | slotbuf[0] = 0x9; | |
4561 | } | |
4562 | ||
4563 | static void | |
4564 | Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4565 | { | |
4566 | slotbuf[0] = 0xa; | |
4567 | } | |
4568 | ||
4569 | static void | |
4570 | Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4571 | { | |
4572 | slotbuf[0] = 0xb; | |
4573 | } | |
4574 | ||
4575 | static void | |
4576 | Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4577 | { | |
4578 | slotbuf[0] = 0xd; | |
4579 | } | |
4580 | ||
4581 | static void | |
4582 | Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4583 | { | |
4584 | slotbuf[0] = 0xe; | |
4585 | } | |
4586 | ||
4587 | static void | |
4588 | Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4589 | { | |
4590 | slotbuf[0] = 0xf; | |
4591 | } | |
4592 | ||
4593 | static void | |
4594 | Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4595 | { | |
4596 | slotbuf[0] = 0x1; | |
4597 | } | |
4598 | ||
4599 | static void | |
4600 | Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4601 | { | |
4602 | slotbuf[0] = 0x2; | |
4603 | } | |
4604 | ||
4605 | static void | |
4606 | Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4607 | { | |
4608 | slotbuf[0] = 0x3; | |
4609 | } | |
4610 | ||
4611 | static void | |
4612 | Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4613 | { | |
4614 | slotbuf[0] = 0x680000; | |
4615 | } | |
4616 | ||
4617 | static void | |
4618 | Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4619 | { | |
4620 | slotbuf[0] = 0x690000; | |
4621 | } | |
4622 | ||
4623 | static void | |
4624 | Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4625 | { | |
4626 | slotbuf[0] = 0x6b0000; | |
4627 | } | |
4628 | ||
4629 | static void | |
4630 | Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4631 | { | |
4632 | slotbuf[0] = 0x6a0000; | |
4633 | } | |
4634 | ||
4635 | static void | |
4636 | Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4637 | { | |
4638 | slotbuf[0] = 0x700600; | |
4639 | } | |
4640 | ||
4641 | static void | |
4642 | Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4643 | { | |
4644 | slotbuf[0] = 0x700e00; | |
4645 | } | |
4646 | ||
4647 | static void | |
4648 | Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4649 | { | |
4650 | slotbuf[0] = 0x6f0000; | |
4651 | } | |
4652 | ||
4653 | static void | |
4654 | Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4655 | { | |
4656 | slotbuf[0] = 0x6e0000; | |
4657 | } | |
4658 | ||
4659 | static void | |
4660 | Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4661 | { | |
4662 | slotbuf[0] = 0x700100; | |
4663 | } | |
4664 | ||
4665 | static void | |
4666 | Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4667 | { | |
4668 | slotbuf[0] = 0x700900; | |
4669 | } | |
4670 | ||
4671 | static void | |
4672 | Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4673 | { | |
4674 | slotbuf[0] = 0x700a00; | |
4675 | } | |
4676 | ||
4677 | static void | |
4678 | Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4679 | { | |
4680 | slotbuf[0] = 0x700200; | |
4681 | } | |
4682 | ||
4683 | static void | |
4684 | Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4685 | { | |
4686 | slotbuf[0] = 0x700b00; | |
4687 | } | |
4688 | ||
4689 | static void | |
4690 | Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4691 | { | |
4692 | slotbuf[0] = 0x700300; | |
4693 | } | |
4694 | ||
4695 | static void | |
4696 | Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4697 | { | |
4698 | slotbuf[0] = 0x700800; | |
4699 | } | |
4700 | ||
4701 | static void | |
4702 | Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4703 | { | |
4704 | slotbuf[0] = 0x700000; | |
4705 | } | |
4706 | ||
4707 | static void | |
4708 | Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4709 | { | |
4710 | slotbuf[0] = 0x700400; | |
4711 | } | |
4712 | ||
4713 | static void | |
4714 | Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4715 | { | |
4716 | slotbuf[0] = 0x700c00; | |
4717 | } | |
4718 | ||
4719 | static void | |
4720 | Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4721 | { | |
4722 | slotbuf[0] = 0x700500; | |
4723 | } | |
4724 | ||
4725 | static void | |
4726 | Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4727 | { | |
4728 | slotbuf[0] = 0x700d00; | |
4729 | } | |
4730 | ||
4731 | static void | |
4732 | Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4733 | { | |
4734 | slotbuf[0] = 0x640000; | |
4735 | } | |
4736 | ||
4737 | static void | |
4738 | Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4739 | { | |
4740 | slotbuf[0] = 0x650000; | |
4741 | } | |
4742 | ||
4743 | static void | |
4744 | Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4745 | { | |
4746 | slotbuf[0] = 0x670000; | |
4747 | } | |
4748 | ||
4749 | static void | |
4750 | Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4751 | { | |
4752 | slotbuf[0] = 0x660000; | |
4753 | } | |
4754 | ||
4755 | static void | |
4756 | Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4757 | { | |
4758 | slotbuf[0] = 0x500000; | |
4759 | } | |
4760 | ||
4761 | static void | |
4762 | Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4763 | { | |
4764 | slotbuf[0] = 0x30000; | |
4765 | } | |
4766 | ||
4767 | static void | |
4768 | Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4769 | { | |
4770 | slotbuf[0] = 0x40; | |
4771 | } | |
4772 | ||
4773 | static void | |
4774 | Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4775 | { | |
4776 | slotbuf[0] = 0; | |
4777 | } | |
4778 | ||
4779 | static void | |
4780 | Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4781 | { | |
4782 | slotbuf[0] = 0x600000; | |
4783 | } | |
4784 | ||
4785 | static void | |
4786 | Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4787 | { | |
4788 | slotbuf[0] = 0xa0000; | |
4789 | } | |
4790 | ||
4791 | static void | |
4792 | Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4793 | { | |
4794 | slotbuf[0] = 0x200100; | |
4795 | } | |
4796 | ||
4797 | static void | |
4798 | Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4799 | { | |
4800 | slotbuf[0] = 0x200900; | |
4801 | } | |
4802 | ||
4803 | static void | |
4804 | Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4805 | { | |
4806 | slotbuf[0] = 0x200200; | |
4807 | } | |
4808 | ||
4809 | static void | |
4810 | Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4811 | { | |
4812 | slotbuf[0] = 0x100000; | |
4813 | } | |
4814 | ||
4815 | static void | |
4816 | Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4817 | { | |
4818 | slotbuf[0] = 0x200000; | |
4819 | } | |
4820 | ||
4821 | static void | |
4822 | Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4823 | { | |
4824 | slotbuf[0] = 0x6d0800; | |
4825 | } | |
4826 | ||
4827 | static void | |
4828 | Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4829 | { | |
4830 | slotbuf[0] = 0x6d0900; | |
4831 | } | |
4832 | ||
4833 | static void | |
4834 | Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4835 | { | |
4836 | slotbuf[0] = 0x6d0a00; | |
4837 | } | |
4838 | ||
4839 | static void | |
4840 | Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4841 | { | |
4842 | slotbuf[0] = 0x200a00; | |
4843 | } | |
4844 | ||
4845 | static void | |
4846 | Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4847 | { | |
4848 | slotbuf[0] = 0x38; | |
4849 | } | |
4850 | ||
4851 | static void | |
4852 | Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4853 | { | |
4854 | slotbuf[0] = 0x39; | |
4855 | } | |
4856 | ||
4857 | static void | |
4858 | Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4859 | { | |
4860 | slotbuf[0] = 0x3a; | |
4861 | } | |
4862 | ||
4863 | static void | |
4864 | Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4865 | { | |
4866 | slotbuf[0] = 0x3b; | |
4867 | } | |
4868 | ||
4869 | static void | |
4870 | Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4871 | { | |
4872 | slotbuf[0] = 0x6; | |
4873 | } | |
4874 | ||
4875 | static void | |
4876 | Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4877 | { | |
4878 | slotbuf[0] = 0x1006; | |
4879 | } | |
4880 | ||
4881 | static void | |
4882 | Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4883 | { | |
4884 | slotbuf[0] = 0xf0200; | |
4885 | } | |
4886 | ||
4887 | static void | |
4888 | Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4889 | { | |
4890 | slotbuf[0] = 0x20000; | |
4891 | } | |
4892 | ||
4893 | static void | |
4894 | Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4895 | { | |
4896 | slotbuf[0] = 0x200500; | |
4897 | } | |
4898 | ||
4899 | static void | |
4900 | Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4901 | { | |
4902 | slotbuf[0] = 0x200600; | |
4903 | } | |
4904 | ||
4905 | static void | |
4906 | Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4907 | { | |
4908 | slotbuf[0] = 0x200400; | |
4909 | } | |
4910 | ||
4911 | static void | |
4912 | Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4913 | { | |
4914 | slotbuf[0] = 0x4; | |
4915 | } | |
4916 | ||
4917 | static void | |
4918 | Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4919 | { | |
4920 | slotbuf[0] = 0x104; | |
4921 | } | |
4922 | ||
4923 | static void | |
4924 | Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4925 | { | |
4926 | slotbuf[0] = 0x204; | |
4927 | } | |
4928 | ||
4929 | static void | |
4930 | Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4931 | { | |
4932 | slotbuf[0] = 0x304; | |
4933 | } | |
4934 | ||
4935 | static void | |
4936 | Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4937 | { | |
4938 | slotbuf[0] = 0x404; | |
4939 | } | |
4940 | ||
4941 | static void | |
4942 | Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4943 | { | |
4944 | slotbuf[0] = 0x1a; | |
4945 | } | |
4946 | ||
4947 | static void | |
4948 | Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4949 | { | |
4950 | slotbuf[0] = 0x18; | |
4951 | } | |
4952 | ||
4953 | static void | |
4954 | Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4955 | { | |
4956 | slotbuf[0] = 0x19; | |
4957 | } | |
4958 | ||
4959 | static void | |
4960 | Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4961 | { | |
4962 | slotbuf[0] = 0x1b; | |
4963 | } | |
4964 | ||
4965 | static void | |
4966 | Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4967 | { | |
4968 | slotbuf[0] = 0x10; | |
4969 | } | |
4970 | ||
4971 | static void | |
4972 | Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4973 | { | |
4974 | slotbuf[0] = 0x12; | |
4975 | } | |
4976 | ||
4977 | static void | |
4978 | Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4979 | { | |
4980 | slotbuf[0] = 0x14; | |
4981 | } | |
4982 | ||
4983 | static void | |
4984 | Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4985 | { | |
4986 | slotbuf[0] = 0xc0200; | |
4987 | } | |
4988 | ||
4989 | static void | |
4990 | Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4991 | { | |
4992 | slotbuf[0] = 0xd0200; | |
4993 | } | |
4994 | ||
4995 | static void | |
4996 | Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
4997 | { | |
4998 | slotbuf[0] = 0x200; | |
4999 | } | |
5000 | ||
5001 | static void | |
5002 | Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5003 | { | |
5004 | slotbuf[0] = 0x10200; | |
5005 | } | |
5006 | ||
5007 | static void | |
5008 | Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5009 | { | |
5010 | slotbuf[0] = 0x20200; | |
5011 | } | |
5012 | ||
5013 | static void | |
5014 | Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5015 | { | |
5016 | slotbuf[0] = 0x30200; | |
5017 | } | |
5018 | ||
5019 | static void | |
5020 | Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5021 | { | |
5022 | slotbuf[0] = 0x600; | |
5023 | } | |
5024 | ||
5025 | static void | |
5026 | Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5027 | { | |
5028 | slotbuf[0] = 0x130; | |
5029 | } | |
5030 | ||
5031 | static void | |
5032 | Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5033 | { | |
5034 | slotbuf[0] = 0x131; | |
5035 | } | |
5036 | ||
5037 | static void | |
5038 | Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5039 | { | |
5040 | slotbuf[0] = 0x116; | |
5041 | } | |
5042 | ||
5043 | static void | |
5044 | Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5045 | { | |
5046 | slotbuf[0] = 0x230; | |
5047 | } | |
5048 | ||
5049 | static void | |
5050 | Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5051 | { | |
5052 | slotbuf[0] = 0x231; | |
5053 | } | |
5054 | ||
5055 | static void | |
5056 | Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5057 | { | |
5058 | slotbuf[0] = 0x216; | |
5059 | } | |
5060 | ||
5061 | static void | |
5062 | Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5063 | { | |
5064 | slotbuf[0] = 0x30; | |
5065 | } | |
5066 | ||
5067 | static void | |
5068 | Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5069 | { | |
5070 | slotbuf[0] = 0x31; | |
5071 | } | |
5072 | ||
5073 | static void | |
5074 | Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5075 | { | |
5076 | slotbuf[0] = 0x16; | |
5077 | } | |
5078 | ||
5079 | static void | |
5080 | Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5081 | { | |
5082 | slotbuf[0] = 0x330; | |
5083 | } | |
5084 | ||
5085 | static void | |
5086 | Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5087 | { | |
5088 | slotbuf[0] = 0x331; | |
5089 | } | |
5090 | ||
5091 | static void | |
5092 | Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5093 | { | |
5094 | slotbuf[0] = 0x316; | |
5095 | } | |
5096 | ||
5097 | static void | |
5098 | Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5099 | { | |
5100 | slotbuf[0] = 0x530; | |
5101 | } | |
5102 | ||
5103 | static void | |
5104 | Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5105 | { | |
5106 | slotbuf[0] = 0x531; | |
5107 | } | |
5108 | ||
5109 | static void | |
5110 | Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5111 | { | |
5112 | slotbuf[0] = 0x516; | |
5113 | } | |
5114 | ||
5115 | static void | |
5116 | Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5117 | { | |
5118 | slotbuf[0] = 0xb030; | |
5119 | } | |
5120 | ||
5121 | static void | |
5122 | Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5123 | { | |
5124 | slotbuf[0] = 0xd030; | |
5125 | } | |
5126 | ||
5127 | static void | |
5128 | Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5129 | { | |
5130 | slotbuf[0] = 0xe630; | |
5131 | } | |
5132 | ||
5133 | static void | |
5134 | Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5135 | { | |
5136 | slotbuf[0] = 0xe631; | |
5137 | } | |
5138 | ||
5139 | static void | |
5140 | Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5141 | { | |
5142 | slotbuf[0] = 0xe616; | |
5143 | } | |
5144 | ||
5145 | static void | |
5146 | Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5147 | { | |
5148 | slotbuf[0] = 0xb130; | |
5149 | } | |
5150 | ||
5151 | static void | |
5152 | Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5153 | { | |
5154 | slotbuf[0] = 0xb131; | |
5155 | } | |
5156 | ||
5157 | static void | |
5158 | Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5159 | { | |
5160 | slotbuf[0] = 0xb116; | |
5161 | } | |
5162 | ||
5163 | static void | |
5164 | Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5165 | { | |
5166 | slotbuf[0] = 0xd130; | |
5167 | } | |
5168 | ||
5169 | static void | |
5170 | Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5171 | { | |
5172 | slotbuf[0] = 0xd131; | |
5173 | } | |
5174 | ||
5175 | static void | |
5176 | Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5177 | { | |
5178 | slotbuf[0] = 0xd116; | |
5179 | } | |
5180 | ||
5181 | static void | |
5182 | Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5183 | { | |
5184 | slotbuf[0] = 0xb230; | |
5185 | } | |
5186 | ||
5187 | static void | |
5188 | Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5189 | { | |
5190 | slotbuf[0] = 0xb231; | |
5191 | } | |
5192 | ||
5193 | static void | |
5194 | Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5195 | { | |
5196 | slotbuf[0] = 0xb216; | |
5197 | } | |
5198 | ||
5199 | static void | |
5200 | Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5201 | { | |
5202 | slotbuf[0] = 0xd230; | |
5203 | } | |
5204 | ||
5205 | static void | |
5206 | Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5207 | { | |
5208 | slotbuf[0] = 0xd231; | |
5209 | } | |
5210 | ||
5211 | static void | |
5212 | Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5213 | { | |
5214 | slotbuf[0] = 0xd216; | |
5215 | } | |
5216 | ||
5217 | static void | |
5218 | Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5219 | { | |
5220 | slotbuf[0] = 0xb330; | |
5221 | } | |
5222 | ||
5223 | static void | |
5224 | Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5225 | { | |
5226 | slotbuf[0] = 0xb331; | |
5227 | } | |
5228 | ||
5229 | static void | |
5230 | Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5231 | { | |
5232 | slotbuf[0] = 0xb316; | |
5233 | } | |
5234 | ||
5235 | static void | |
5236 | Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5237 | { | |
5238 | slotbuf[0] = 0xd330; | |
5239 | } | |
5240 | ||
5241 | static void | |
5242 | Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5243 | { | |
5244 | slotbuf[0] = 0xd331; | |
5245 | } | |
5246 | ||
5247 | static void | |
5248 | Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5249 | { | |
5250 | slotbuf[0] = 0xd316; | |
5251 | } | |
5252 | ||
5253 | static void | |
5254 | Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5255 | { | |
5256 | slotbuf[0] = 0xb430; | |
5257 | } | |
5258 | ||
5259 | static void | |
5260 | Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5261 | { | |
5262 | slotbuf[0] = 0xb431; | |
5263 | } | |
5264 | ||
5265 | static void | |
5266 | Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5267 | { | |
5268 | slotbuf[0] = 0xb416; | |
5269 | } | |
5270 | ||
5271 | static void | |
5272 | Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5273 | { | |
5274 | slotbuf[0] = 0xd430; | |
5275 | } | |
5276 | ||
5277 | static void | |
5278 | Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5279 | { | |
5280 | slotbuf[0] = 0xd431; | |
5281 | } | |
5282 | ||
5283 | static void | |
5284 | Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5285 | { | |
5286 | slotbuf[0] = 0xd416; | |
5287 | } | |
5288 | ||
5289 | static void | |
5290 | Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5291 | { | |
5292 | slotbuf[0] = 0xc230; | |
5293 | } | |
5294 | ||
5295 | static void | |
5296 | Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5297 | { | |
5298 | slotbuf[0] = 0xc231; | |
5299 | } | |
5300 | ||
5301 | static void | |
5302 | Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5303 | { | |
5304 | slotbuf[0] = 0xc216; | |
5305 | } | |
5306 | ||
5307 | static void | |
5308 | Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5309 | { | |
5310 | slotbuf[0] = 0xc330; | |
5311 | } | |
5312 | ||
5313 | static void | |
5314 | Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5315 | { | |
5316 | slotbuf[0] = 0xc331; | |
5317 | } | |
5318 | ||
5319 | static void | |
5320 | Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5321 | { | |
5322 | slotbuf[0] = 0xc316; | |
5323 | } | |
5324 | ||
5325 | static void | |
5326 | Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5327 | { | |
5328 | slotbuf[0] = 0xc430; | |
5329 | } | |
5330 | ||
5331 | static void | |
5332 | Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5333 | { | |
5334 | slotbuf[0] = 0xc431; | |
5335 | } | |
5336 | ||
5337 | static void | |
5338 | Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5339 | { | |
5340 | slotbuf[0] = 0xc416; | |
5341 | } | |
5342 | ||
5343 | static void | |
5344 | Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5345 | { | |
5346 | slotbuf[0] = 0xee30; | |
5347 | } | |
5348 | ||
5349 | static void | |
5350 | Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5351 | { | |
5352 | slotbuf[0] = 0xee31; | |
5353 | } | |
5354 | ||
5355 | static void | |
5356 | Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5357 | { | |
5358 | slotbuf[0] = 0xee16; | |
5359 | } | |
5360 | ||
5361 | static void | |
5362 | Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5363 | { | |
5364 | slotbuf[0] = 0xc030; | |
5365 | } | |
5366 | ||
5367 | static void | |
5368 | Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5369 | { | |
5370 | slotbuf[0] = 0xc031; | |
5371 | } | |
5372 | ||
5373 | static void | |
5374 | Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5375 | { | |
5376 | slotbuf[0] = 0xc016; | |
5377 | } | |
5378 | ||
5379 | static void | |
5380 | Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5381 | { | |
5382 | slotbuf[0] = 0xe830; | |
5383 | } | |
5384 | ||
5385 | static void | |
5386 | Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5387 | { | |
5388 | slotbuf[0] = 0xe831; | |
5389 | } | |
5390 | ||
5391 | static void | |
5392 | Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5393 | { | |
5394 | slotbuf[0] = 0xe816; | |
5395 | } | |
5396 | ||
5397 | static void | |
5398 | Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5399 | { | |
5400 | slotbuf[0] = 0xf430; | |
5401 | } | |
5402 | ||
5403 | static void | |
5404 | Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5405 | { | |
5406 | slotbuf[0] = 0xf431; | |
5407 | } | |
5408 | ||
5409 | static void | |
5410 | Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5411 | { | |
5412 | slotbuf[0] = 0xf416; | |
5413 | } | |
5414 | ||
5415 | static void | |
5416 | Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5417 | { | |
5418 | slotbuf[0] = 0xf530; | |
5419 | } | |
5420 | ||
5421 | static void | |
5422 | Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5423 | { | |
5424 | slotbuf[0] = 0xf531; | |
5425 | } | |
5426 | ||
5427 | static void | |
5428 | Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5429 | { | |
5430 | slotbuf[0] = 0xf516; | |
5431 | } | |
5432 | ||
5433 | static void | |
5434 | Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5435 | { | |
5436 | slotbuf[0] = 0xeb30; | |
5437 | } | |
5438 | ||
5439 | static void | |
5440 | Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5441 | { | |
5442 | slotbuf[0] = 0x10300; | |
5443 | } | |
5444 | ||
5445 | static void | |
5446 | Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5447 | { | |
5448 | slotbuf[0] = 0x700; | |
5449 | } | |
5450 | ||
5451 | static void | |
5452 | Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5453 | { | |
5454 | slotbuf[0] = 0xe230; | |
5455 | } | |
5456 | ||
5457 | static void | |
5458 | Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5459 | { | |
5460 | slotbuf[0] = 0xe231; | |
5461 | } | |
5462 | ||
5463 | static void | |
5464 | Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5465 | { | |
5466 | slotbuf[0] = 0xe331; | |
5467 | } | |
5468 | ||
5469 | static void | |
5470 | Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5471 | { | |
5472 | slotbuf[0] = 0xe430; | |
5473 | } | |
5474 | ||
5475 | static void | |
5476 | Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5477 | { | |
5478 | slotbuf[0] = 0xe431; | |
5479 | } | |
5480 | ||
5481 | static void | |
5482 | Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5483 | { | |
5484 | slotbuf[0] = 0xe416; | |
5485 | } | |
5486 | ||
5487 | static void | |
5488 | Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5489 | { |
43cd72b9 | 5490 | slotbuf[0] = 0x400; |
e0001a05 NC |
5491 | } |
5492 | ||
43cd72b9 BW |
5493 | static void |
5494 | Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5495 | { |
43cd72b9 | 5496 | slotbuf[0] = 0xd20f; |
e0001a05 NC |
5497 | } |
5498 | ||
43cd72b9 BW |
5499 | static void |
5500 | Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5501 | { |
43cd72b9 | 5502 | slotbuf[0] = 0x9030; |
e0001a05 NC |
5503 | } |
5504 | ||
43cd72b9 BW |
5505 | static void |
5506 | Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5507 | { |
43cd72b9 | 5508 | slotbuf[0] = 0x9031; |
e0001a05 NC |
5509 | } |
5510 | ||
43cd72b9 BW |
5511 | static void |
5512 | Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5513 | { |
43cd72b9 | 5514 | slotbuf[0] = 0x9016; |
e0001a05 NC |
5515 | } |
5516 | ||
43cd72b9 BW |
5517 | static void |
5518 | Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5519 | { |
43cd72b9 | 5520 | slotbuf[0] = 0xa030; |
e0001a05 NC |
5521 | } |
5522 | ||
43cd72b9 BW |
5523 | static void |
5524 | Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5525 | { |
43cd72b9 | 5526 | slotbuf[0] = 0xa031; |
e0001a05 NC |
5527 | } |
5528 | ||
43cd72b9 BW |
5529 | static void |
5530 | Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5531 | { |
43cd72b9 | 5532 | slotbuf[0] = 0xa016; |
e0001a05 NC |
5533 | } |
5534 | ||
43cd72b9 BW |
5535 | static void |
5536 | Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5537 | { |
43cd72b9 | 5538 | slotbuf[0] = 0x9130; |
e0001a05 NC |
5539 | } |
5540 | ||
43cd72b9 BW |
5541 | static void |
5542 | Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5543 | { |
43cd72b9 | 5544 | slotbuf[0] = 0x9131; |
e0001a05 NC |
5545 | } |
5546 | ||
43cd72b9 BW |
5547 | static void |
5548 | Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5549 | { |
43cd72b9 | 5550 | slotbuf[0] = 0x9116; |
e0001a05 NC |
5551 | } |
5552 | ||
43cd72b9 BW |
5553 | static void |
5554 | Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5555 | { |
43cd72b9 | 5556 | slotbuf[0] = 0xa130; |
e0001a05 NC |
5557 | } |
5558 | ||
43cd72b9 BW |
5559 | static void |
5560 | Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5561 | { |
43cd72b9 | 5562 | slotbuf[0] = 0xa131; |
e0001a05 NC |
5563 | } |
5564 | ||
43cd72b9 BW |
5565 | static void |
5566 | Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5567 | { |
43cd72b9 | 5568 | slotbuf[0] = 0xa116; |
e0001a05 NC |
5569 | } |
5570 | ||
43cd72b9 BW |
5571 | static void |
5572 | Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5573 | { |
43cd72b9 | 5574 | slotbuf[0] = 0x8030; |
e0001a05 NC |
5575 | } |
5576 | ||
43cd72b9 BW |
5577 | static void |
5578 | Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5579 | { |
43cd72b9 | 5580 | slotbuf[0] = 0x8031; |
e0001a05 NC |
5581 | } |
5582 | ||
43cd72b9 BW |
5583 | static void |
5584 | Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5585 | { |
43cd72b9 | 5586 | slotbuf[0] = 0x8016; |
e0001a05 NC |
5587 | } |
5588 | ||
43cd72b9 BW |
5589 | static void |
5590 | Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5591 | { |
43cd72b9 | 5592 | slotbuf[0] = 0x8130; |
e0001a05 NC |
5593 | } |
5594 | ||
43cd72b9 BW |
5595 | static void |
5596 | Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5597 | { |
43cd72b9 | 5598 | slotbuf[0] = 0x8131; |
e0001a05 NC |
5599 | } |
5600 | ||
43cd72b9 BW |
5601 | static void |
5602 | Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5603 | { |
43cd72b9 | 5604 | slotbuf[0] = 0x8116; |
e0001a05 NC |
5605 | } |
5606 | ||
43cd72b9 BW |
5607 | static void |
5608 | Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5609 | { |
43cd72b9 | 5610 | slotbuf[0] = 0x6030; |
e0001a05 NC |
5611 | } |
5612 | ||
43cd72b9 BW |
5613 | static void |
5614 | Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5615 | { |
43cd72b9 | 5616 | slotbuf[0] = 0x6031; |
e0001a05 NC |
5617 | } |
5618 | ||
43cd72b9 BW |
5619 | static void |
5620 | Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5621 | { |
43cd72b9 | 5622 | slotbuf[0] = 0x6016; |
e0001a05 NC |
5623 | } |
5624 | ||
43cd72b9 BW |
5625 | static void |
5626 | Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5627 | { |
43cd72b9 | 5628 | slotbuf[0] = 0xe930; |
e0001a05 NC |
5629 | } |
5630 | ||
43cd72b9 BW |
5631 | static void |
5632 | Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5633 | { |
43cd72b9 | 5634 | slotbuf[0] = 0xe931; |
e0001a05 NC |
5635 | } |
5636 | ||
43cd72b9 BW |
5637 | static void |
5638 | Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5639 | { |
43cd72b9 | 5640 | slotbuf[0] = 0xe916; |
e0001a05 NC |
5641 | } |
5642 | ||
43cd72b9 BW |
5643 | static void |
5644 | Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5645 | { |
43cd72b9 | 5646 | slotbuf[0] = 0xec30; |
e0001a05 NC |
5647 | } |
5648 | ||
43cd72b9 BW |
5649 | static void |
5650 | Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5651 | { |
43cd72b9 | 5652 | slotbuf[0] = 0xec31; |
e0001a05 NC |
5653 | } |
5654 | ||
43cd72b9 BW |
5655 | static void |
5656 | Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5657 | { |
43cd72b9 | 5658 | slotbuf[0] = 0xec16; |
e0001a05 NC |
5659 | } |
5660 | ||
43cd72b9 BW |
5661 | static void |
5662 | Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5663 | { |
43cd72b9 | 5664 | slotbuf[0] = 0xed30; |
e0001a05 NC |
5665 | } |
5666 | ||
43cd72b9 BW |
5667 | static void |
5668 | Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5669 | { |
43cd72b9 | 5670 | slotbuf[0] = 0xed31; |
e0001a05 NC |
5671 | } |
5672 | ||
43cd72b9 BW |
5673 | static void |
5674 | Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5675 | { |
43cd72b9 | 5676 | slotbuf[0] = 0xed16; |
e0001a05 NC |
5677 | } |
5678 | ||
43cd72b9 BW |
5679 | static void |
5680 | Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5681 | { |
43cd72b9 | 5682 | slotbuf[0] = 0x6830; |
e0001a05 NC |
5683 | } |
5684 | ||
43cd72b9 BW |
5685 | static void |
5686 | Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5687 | { |
43cd72b9 | 5688 | slotbuf[0] = 0x6831; |
e0001a05 NC |
5689 | } |
5690 | ||
43cd72b9 BW |
5691 | static void |
5692 | Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5693 | { |
43cd72b9 | 5694 | slotbuf[0] = 0x6816; |
e0001a05 NC |
5695 | } |
5696 | ||
43cd72b9 BW |
5697 | static void |
5698 | Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5699 | { |
43cd72b9 | 5700 | slotbuf[0] = 0xe1f; |
e0001a05 NC |
5701 | } |
5702 | ||
43cd72b9 BW |
5703 | static void |
5704 | Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5705 | { |
43cd72b9 | 5706 | slotbuf[0] = 0x10e1f; |
e0001a05 NC |
5707 | } |
5708 | ||
43cd72b9 BW |
5709 | static void |
5710 | Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5711 | { |
43cd72b9 | 5712 | slotbuf[0] = 0xea30; |
e0001a05 NC |
5713 | } |
5714 | ||
43cd72b9 BW |
5715 | static void |
5716 | Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5717 | { |
43cd72b9 | 5718 | slotbuf[0] = 0xea31; |
e0001a05 NC |
5719 | } |
5720 | ||
43cd72b9 BW |
5721 | static void |
5722 | Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5723 | { |
43cd72b9 | 5724 | slotbuf[0] = 0xea16; |
e0001a05 NC |
5725 | } |
5726 | ||
43cd72b9 BW |
5727 | static void |
5728 | Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5729 | { |
43cd72b9 | 5730 | slotbuf[0] = 0xf030; |
e0001a05 NC |
5731 | } |
5732 | ||
43cd72b9 BW |
5733 | static void |
5734 | Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5735 | { |
43cd72b9 | 5736 | slotbuf[0] = 0xf031; |
e0001a05 NC |
5737 | } |
5738 | ||
43cd72b9 BW |
5739 | static void |
5740 | Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5741 | { |
43cd72b9 | 5742 | slotbuf[0] = 0xf016; |
e0001a05 NC |
5743 | } |
5744 | ||
43cd72b9 BW |
5745 | static void |
5746 | Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5747 | { |
43cd72b9 | 5748 | slotbuf[0] = 0xf130; |
e0001a05 NC |
5749 | } |
5750 | ||
43cd72b9 BW |
5751 | static void |
5752 | Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5753 | { |
43cd72b9 | 5754 | slotbuf[0] = 0xf131; |
e0001a05 NC |
5755 | } |
5756 | ||
43cd72b9 BW |
5757 | static void |
5758 | Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5759 | { |
43cd72b9 | 5760 | slotbuf[0] = 0xf116; |
e0001a05 NC |
5761 | } |
5762 | ||
43cd72b9 BW |
5763 | static void |
5764 | Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5765 | { |
43cd72b9 | 5766 | slotbuf[0] = 0xf230; |
e0001a05 NC |
5767 | } |
5768 | ||
43cd72b9 BW |
5769 | static void |
5770 | Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5771 | { |
43cd72b9 | 5772 | slotbuf[0] = 0xf231; |
e0001a05 NC |
5773 | } |
5774 | ||
43cd72b9 BW |
5775 | static void |
5776 | Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5777 | { |
43cd72b9 | 5778 | slotbuf[0] = 0xf216; |
e0001a05 NC |
5779 | } |
5780 | ||
43cd72b9 BW |
5781 | static void |
5782 | Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5783 | { |
43cd72b9 | 5784 | slotbuf[0] = 0x2c0700; |
e0001a05 NC |
5785 | } |
5786 | ||
43cd72b9 BW |
5787 | static void |
5788 | Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5789 | { |
43cd72b9 | 5790 | slotbuf[0] = 0x2e0700; |
e0001a05 NC |
5791 | } |
5792 | ||
43cd72b9 BW |
5793 | static void |
5794 | Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5795 | { |
43cd72b9 | 5796 | slotbuf[0] = 0x2f0700; |
e0001a05 NC |
5797 | } |
5798 | ||
43cd72b9 BW |
5799 | static void |
5800 | Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5801 | { |
43cd72b9 | 5802 | slotbuf[0] = 0x1f; |
e0001a05 NC |
5803 | } |
5804 | ||
43cd72b9 BW |
5805 | static void |
5806 | Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5807 | { |
43cd72b9 | 5808 | slotbuf[0] = 0x21f; |
e0001a05 NC |
5809 | } |
5810 | ||
43cd72b9 BW |
5811 | static void |
5812 | Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5813 | { |
43cd72b9 | 5814 | slotbuf[0] = 0x11f; |
e0001a05 NC |
5815 | } |
5816 | ||
43cd72b9 BW |
5817 | static void |
5818 | Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5819 | { |
43cd72b9 | 5820 | slotbuf[0] = 0x31f; |
e0001a05 NC |
5821 | } |
5822 | ||
43cd72b9 BW |
5823 | static void |
5824 | Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5825 | { |
43cd72b9 | 5826 | slotbuf[0] = 0x240700; |
e0001a05 NC |
5827 | } |
5828 | ||
43cd72b9 BW |
5829 | static void |
5830 | Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5831 | { |
43cd72b9 | 5832 | slotbuf[0] = 0x250700; |
e0001a05 NC |
5833 | } |
5834 | ||
43cd72b9 BW |
5835 | static void |
5836 | Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5837 | { |
43cd72b9 | 5838 | slotbuf[0] = 0x280740; |
e0001a05 NC |
5839 | } |
5840 | ||
43cd72b9 BW |
5841 | static void |
5842 | Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5843 | { |
43cd72b9 | 5844 | slotbuf[0] = 0x280750; |
e0001a05 NC |
5845 | } |
5846 | ||
43cd72b9 BW |
5847 | static void |
5848 | Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5849 | { |
43cd72b9 | 5850 | slotbuf[0] = 0x260700; |
e0001a05 NC |
5851 | } |
5852 | ||
43cd72b9 BW |
5853 | static void |
5854 | Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5855 | { |
43cd72b9 | 5856 | slotbuf[0] = 0x270700; |
e0001a05 NC |
5857 | } |
5858 | ||
43cd72b9 BW |
5859 | static void |
5860 | Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5861 | { |
43cd72b9 | 5862 | slotbuf[0] = 0x200700; |
e0001a05 NC |
5863 | } |
5864 | ||
43cd72b9 BW |
5865 | static void |
5866 | Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5867 | { |
43cd72b9 | 5868 | slotbuf[0] = 0x210700; |
e0001a05 NC |
5869 | } |
5870 | ||
43cd72b9 BW |
5871 | static void |
5872 | Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5873 | { |
43cd72b9 | 5874 | slotbuf[0] = 0x220700; |
e0001a05 NC |
5875 | } |
5876 | ||
43cd72b9 BW |
5877 | static void |
5878 | Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5879 | { |
43cd72b9 | 5880 | slotbuf[0] = 0x230700; |
e0001a05 NC |
5881 | } |
5882 | ||
43cd72b9 BW |
5883 | static void |
5884 | Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5885 | { |
43cd72b9 | 5886 | slotbuf[0] = 0x91f; |
e0001a05 NC |
5887 | } |
5888 | ||
43cd72b9 BW |
5889 | static void |
5890 | Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5891 | { |
43cd72b9 | 5892 | slotbuf[0] = 0x81f; |
e0001a05 NC |
5893 | } |
5894 | ||
43cd72b9 BW |
5895 | static void |
5896 | Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5897 | { |
43cd72b9 | 5898 | slotbuf[0] = 0xc05; |
e0001a05 NC |
5899 | } |
5900 | ||
43cd72b9 BW |
5901 | static void |
5902 | Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5903 | { |
43cd72b9 | 5904 | slotbuf[0] = 0xd05; |
e0001a05 NC |
5905 | } |
5906 | ||
43cd72b9 BW |
5907 | static void |
5908 | Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5909 | { |
43cd72b9 | 5910 | slotbuf[0] = 0xb05; |
e0001a05 NC |
5911 | } |
5912 | ||
43cd72b9 BW |
5913 | static void |
5914 | Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5915 | { |
43cd72b9 | 5916 | slotbuf[0] = 0xf05; |
e0001a05 NC |
5917 | } |
5918 | ||
43cd72b9 BW |
5919 | static void |
5920 | Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5921 | { |
43cd72b9 | 5922 | slotbuf[0] = 0xe05; |
e0001a05 NC |
5923 | } |
5924 | ||
43cd72b9 BW |
5925 | static void |
5926 | Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5927 | { |
43cd72b9 | 5928 | slotbuf[0] = 0x405; |
e0001a05 NC |
5929 | } |
5930 | ||
43cd72b9 BW |
5931 | static void |
5932 | Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5933 | { |
43cd72b9 | 5934 | slotbuf[0] = 0x505; |
e0001a05 NC |
5935 | } |
5936 | ||
43cd72b9 BW |
5937 | static void |
5938 | Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5939 | { |
43cd72b9 | 5940 | slotbuf[0] = 0x305; |
e0001a05 NC |
5941 | } |
5942 | ||
43cd72b9 BW |
5943 | static void |
5944 | Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5945 | { |
43cd72b9 | 5946 | slotbuf[0] = 0x705; |
e0001a05 NC |
5947 | } |
5948 | ||
43cd72b9 BW |
5949 | static void |
5950 | Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
e0001a05 | 5951 | { |
43cd72b9 | 5952 | slotbuf[0] = 0x605; |
e0001a05 NC |
5953 | } |
5954 | ||
43cd72b9 BW |
5955 | static void |
5956 | Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5957 | { | |
5958 | slotbuf[0] = 0xe04; | |
5959 | } | |
5960 | ||
5961 | static void | |
5962 | Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) | |
5963 | { | |
5964 | slotbuf[0] = 0xf04; | |
5965 | } | |
5966 | ||
5967 | xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { | |
5968 | Opcode_excw_Slot_inst_encode, 0, 0 | |
5969 | }; | |
5970 | ||
5971 | xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { | |
5972 | Opcode_rfe_Slot_inst_encode, 0, 0 | |
5973 | }; | |
5974 | ||
5975 | xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { | |
5976 | Opcode_rfde_Slot_inst_encode, 0, 0 | |
5977 | }; | |
5978 | ||
5979 | xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { | |
5980 | Opcode_syscall_Slot_inst_encode, 0, 0 | |
5981 | }; | |
5982 | ||
5983 | xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { | |
5984 | Opcode_simcall_Slot_inst_encode, 0, 0 | |
5985 | }; | |
5986 | ||
5987 | xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { | |
5988 | Opcode_call12_Slot_inst_encode, 0, 0 | |
5989 | }; | |
5990 | ||
5991 | xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { | |
5992 | Opcode_call8_Slot_inst_encode, 0, 0 | |
5993 | }; | |
5994 | ||
5995 | xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { | |
5996 | Opcode_call4_Slot_inst_encode, 0, 0 | |
5997 | }; | |
5998 | ||
5999 | xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { | |
6000 | Opcode_callx12_Slot_inst_encode, 0, 0 | |
6001 | }; | |
6002 | ||
6003 | xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { | |
6004 | Opcode_callx8_Slot_inst_encode, 0, 0 | |
6005 | }; | |
6006 | ||
6007 | xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { | |
6008 | Opcode_callx4_Slot_inst_encode, 0, 0 | |
6009 | }; | |
6010 | ||
6011 | xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { | |
6012 | Opcode_entry_Slot_inst_encode, 0, 0 | |
6013 | }; | |
6014 | ||
6015 | xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { | |
6016 | Opcode_movsp_Slot_inst_encode, 0, 0 | |
6017 | }; | |
6018 | ||
6019 | xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { | |
6020 | Opcode_rotw_Slot_inst_encode, 0, 0 | |
6021 | }; | |
6022 | ||
6023 | xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { | |
6024 | Opcode_retw_Slot_inst_encode, 0, 0 | |
6025 | }; | |
6026 | ||
6027 | xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { | |
6028 | 0, 0, Opcode_retw_n_Slot_inst16b_encode | |
6029 | }; | |
6030 | ||
6031 | xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { | |
6032 | Opcode_rfwo_Slot_inst_encode, 0, 0 | |
6033 | }; | |
6034 | ||
6035 | xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { | |
6036 | Opcode_rfwu_Slot_inst_encode, 0, 0 | |
6037 | }; | |
6038 | ||
6039 | xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { | |
6040 | Opcode_l32e_Slot_inst_encode, 0, 0 | |
6041 | }; | |
6042 | ||
6043 | xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { | |
6044 | Opcode_s32e_Slot_inst_encode, 0, 0 | |
6045 | }; | |
6046 | ||
6047 | xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { | |
6048 | Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 | |
6049 | }; | |
6050 | ||
6051 | xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { | |
6052 | Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 | |
6053 | }; | |
6054 | ||
6055 | xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { | |
6056 | Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 | |
6057 | }; | |
6058 | ||
6059 | xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { | |
6060 | Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 | |
6061 | }; | |
6062 | ||
6063 | xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { | |
6064 | Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 | |
6065 | }; | |
6066 | ||
6067 | xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { | |
6068 | Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 | |
6069 | }; | |
6070 | ||
6071 | xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { | |
6072 | 0, Opcode_add_n_Slot_inst16a_encode, 0 | |
6073 | }; | |
6074 | ||
6075 | xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { | |
6076 | 0, Opcode_addi_n_Slot_inst16a_encode, 0 | |
6077 | }; | |
6078 | ||
6079 | xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { | |
6080 | 0, 0, Opcode_beqz_n_Slot_inst16b_encode | |
6081 | }; | |
6082 | ||
6083 | xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { | |
6084 | 0, 0, Opcode_bnez_n_Slot_inst16b_encode | |
6085 | }; | |
6086 | ||
6087 | xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { | |
6088 | 0, 0, Opcode_ill_n_Slot_inst16b_encode | |
6089 | }; | |
6090 | ||
6091 | xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { | |
6092 | 0, Opcode_l32i_n_Slot_inst16a_encode, 0 | |
6093 | }; | |
6094 | ||
6095 | xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { | |
6096 | 0, 0, Opcode_mov_n_Slot_inst16b_encode | |
6097 | }; | |
6098 | ||
6099 | xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { | |
6100 | 0, 0, Opcode_movi_n_Slot_inst16b_encode | |
6101 | }; | |
6102 | ||
6103 | xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { | |
6104 | 0, 0, Opcode_nop_n_Slot_inst16b_encode | |
6105 | }; | |
6106 | ||
6107 | xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { | |
6108 | 0, 0, Opcode_ret_n_Slot_inst16b_encode | |
6109 | }; | |
6110 | ||
6111 | xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { | |
6112 | 0, Opcode_s32i_n_Slot_inst16a_encode, 0 | |
6113 | }; | |
6114 | ||
6115 | xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { | |
6116 | Opcode_addi_Slot_inst_encode, 0, 0 | |
6117 | }; | |
6118 | ||
6119 | xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { | |
6120 | Opcode_addmi_Slot_inst_encode, 0, 0 | |
6121 | }; | |
6122 | ||
6123 | xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { | |
6124 | Opcode_add_Slot_inst_encode, 0, 0 | |
6125 | }; | |
6126 | ||
6127 | xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { | |
6128 | Opcode_sub_Slot_inst_encode, 0, 0 | |
6129 | }; | |
6130 | ||
6131 | xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { | |
6132 | Opcode_addx2_Slot_inst_encode, 0, 0 | |
6133 | }; | |
6134 | ||
6135 | xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { | |
6136 | Opcode_addx4_Slot_inst_encode, 0, 0 | |
6137 | }; | |
6138 | ||
6139 | xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { | |
6140 | Opcode_addx8_Slot_inst_encode, 0, 0 | |
6141 | }; | |
6142 | ||
6143 | xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { | |
6144 | Opcode_subx2_Slot_inst_encode, 0, 0 | |
6145 | }; | |
6146 | ||
6147 | xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { | |
6148 | Opcode_subx4_Slot_inst_encode, 0, 0 | |
6149 | }; | |
6150 | ||
6151 | xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { | |
6152 | Opcode_subx8_Slot_inst_encode, 0, 0 | |
6153 | }; | |
6154 | ||
6155 | xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { | |
6156 | Opcode_and_Slot_inst_encode, 0, 0 | |
6157 | }; | |
6158 | ||
6159 | xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { | |
6160 | Opcode_or_Slot_inst_encode, 0, 0 | |
6161 | }; | |
6162 | ||
6163 | xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { | |
6164 | Opcode_xor_Slot_inst_encode, 0, 0 | |
6165 | }; | |
6166 | ||
6167 | xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { | |
6168 | Opcode_beqi_Slot_inst_encode, 0, 0 | |
6169 | }; | |
6170 | ||
6171 | xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { | |
6172 | Opcode_bnei_Slot_inst_encode, 0, 0 | |
6173 | }; | |
6174 | ||
6175 | xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { | |
6176 | Opcode_bgei_Slot_inst_encode, 0, 0 | |
6177 | }; | |
6178 | ||
6179 | xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { | |
6180 | Opcode_blti_Slot_inst_encode, 0, 0 | |
6181 | }; | |
6182 | ||
6183 | xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { | |
6184 | Opcode_bbci_Slot_inst_encode, 0, 0 | |
6185 | }; | |
6186 | ||
6187 | xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { | |
6188 | Opcode_bbsi_Slot_inst_encode, 0, 0 | |
6189 | }; | |
6190 | ||
6191 | xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { | |
6192 | Opcode_bgeui_Slot_inst_encode, 0, 0 | |
6193 | }; | |
6194 | ||
6195 | xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { | |
6196 | Opcode_bltui_Slot_inst_encode, 0, 0 | |
6197 | }; | |
6198 | ||
6199 | xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { | |
6200 | Opcode_beq_Slot_inst_encode, 0, 0 | |
6201 | }; | |
6202 | ||
6203 | xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { | |
6204 | Opcode_bne_Slot_inst_encode, 0, 0 | |
6205 | }; | |
6206 | ||
6207 | xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { | |
6208 | Opcode_bge_Slot_inst_encode, 0, 0 | |
6209 | }; | |
6210 | ||
6211 | xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { | |
6212 | Opcode_blt_Slot_inst_encode, 0, 0 | |
6213 | }; | |
e0001a05 | 6214 | |
43cd72b9 BW |
6215 | xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { |
6216 | Opcode_bgeu_Slot_inst_encode, 0, 0 | |
6217 | }; | |
e0001a05 | 6218 | |
43cd72b9 BW |
6219 | xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { |
6220 | Opcode_bltu_Slot_inst_encode, 0, 0 | |
6221 | }; | |
e0001a05 | 6222 | |
43cd72b9 BW |
6223 | xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { |
6224 | Opcode_bany_Slot_inst_encode, 0, 0 | |
6225 | }; | |
e0001a05 | 6226 | |
43cd72b9 BW |
6227 | xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { |
6228 | Opcode_bnone_Slot_inst_encode, 0, 0 | |
6229 | }; | |
e0001a05 | 6230 | |
43cd72b9 BW |
6231 | xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { |
6232 | Opcode_ball_Slot_inst_encode, 0, 0 | |
6233 | }; | |
e0001a05 | 6234 | |
43cd72b9 BW |
6235 | xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { |
6236 | Opcode_bnall_Slot_inst_encode, 0, 0 | |
6237 | }; | |
e0001a05 | 6238 | |
43cd72b9 BW |
6239 | xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { |
6240 | Opcode_bbc_Slot_inst_encode, 0, 0 | |
6241 | }; | |
e0001a05 | 6242 | |
43cd72b9 BW |
6243 | xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { |
6244 | Opcode_bbs_Slot_inst_encode, 0, 0 | |
6245 | }; | |
e0001a05 | 6246 | |
43cd72b9 BW |
6247 | xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { |
6248 | Opcode_beqz_Slot_inst_encode, 0, 0 | |
6249 | }; | |
e0001a05 | 6250 | |
43cd72b9 BW |
6251 | xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { |
6252 | Opcode_bnez_Slot_inst_encode, 0, 0 | |
6253 | }; | |
e0001a05 | 6254 | |
43cd72b9 BW |
6255 | xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { |
6256 | Opcode_bgez_Slot_inst_encode, 0, 0 | |
6257 | }; | |
e0001a05 | 6258 | |
43cd72b9 BW |
6259 | xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { |
6260 | Opcode_bltz_Slot_inst_encode, 0, 0 | |
6261 | }; | |
e0001a05 | 6262 | |
43cd72b9 BW |
6263 | xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { |
6264 | Opcode_call0_Slot_inst_encode, 0, 0 | |
6265 | }; | |
e0001a05 | 6266 | |
43cd72b9 BW |
6267 | xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { |
6268 | Opcode_callx0_Slot_inst_encode, 0, 0 | |
6269 | }; | |
e0001a05 | 6270 | |
43cd72b9 BW |
6271 | xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { |
6272 | Opcode_extui_Slot_inst_encode, 0, 0 | |
6273 | }; | |
e0001a05 | 6274 | |
43cd72b9 BW |
6275 | xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { |
6276 | Opcode_ill_Slot_inst_encode, 0, 0 | |
6277 | }; | |
e0001a05 | 6278 | |
43cd72b9 BW |
6279 | xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { |
6280 | Opcode_j_Slot_inst_encode, 0, 0 | |
6281 | }; | |
e0001a05 | 6282 | |
43cd72b9 BW |
6283 | xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { |
6284 | Opcode_jx_Slot_inst_encode, 0, 0 | |
6285 | }; | |
e0001a05 | 6286 | |
43cd72b9 BW |
6287 | xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { |
6288 | Opcode_l16ui_Slot_inst_encode, 0, 0 | |
6289 | }; | |
e0001a05 | 6290 | |
43cd72b9 BW |
6291 | xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { |
6292 | Opcode_l16si_Slot_inst_encode, 0, 0 | |
6293 | }; | |
e0001a05 | 6294 | |
43cd72b9 BW |
6295 | xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { |
6296 | Opcode_l32i_Slot_inst_encode, 0, 0 | |
6297 | }; | |
e0001a05 | 6298 | |
43cd72b9 BW |
6299 | xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { |
6300 | Opcode_l32r_Slot_inst_encode, 0, 0 | |
6301 | }; | |
e0001a05 | 6302 | |
43cd72b9 BW |
6303 | xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { |
6304 | Opcode_l8ui_Slot_inst_encode, 0, 0 | |
6305 | }; | |
e0001a05 | 6306 | |
43cd72b9 BW |
6307 | xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { |
6308 | Opcode_loop_Slot_inst_encode, 0, 0 | |
6309 | }; | |
e0001a05 | 6310 | |
43cd72b9 BW |
6311 | xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { |
6312 | Opcode_loopnez_Slot_inst_encode, 0, 0 | |
6313 | }; | |
e0001a05 | 6314 | |
43cd72b9 BW |
6315 | xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { |
6316 | Opcode_loopgtz_Slot_inst_encode, 0, 0 | |
6317 | }; | |
e0001a05 | 6318 | |
43cd72b9 BW |
6319 | xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { |
6320 | Opcode_movi_Slot_inst_encode, 0, 0 | |
6321 | }; | |
e0001a05 | 6322 | |
43cd72b9 BW |
6323 | xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { |
6324 | Opcode_moveqz_Slot_inst_encode, 0, 0 | |
6325 | }; | |
e0001a05 | 6326 | |
43cd72b9 BW |
6327 | xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { |
6328 | Opcode_movnez_Slot_inst_encode, 0, 0 | |
6329 | }; | |
e0001a05 | 6330 | |
43cd72b9 BW |
6331 | xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { |
6332 | Opcode_movltz_Slot_inst_encode, 0, 0 | |
6333 | }; | |
e0001a05 | 6334 | |
43cd72b9 BW |
6335 | xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { |
6336 | Opcode_movgez_Slot_inst_encode, 0, 0 | |
6337 | }; | |
e0001a05 | 6338 | |
43cd72b9 BW |
6339 | xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { |
6340 | Opcode_neg_Slot_inst_encode, 0, 0 | |
6341 | }; | |
e0001a05 | 6342 | |
43cd72b9 BW |
6343 | xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { |
6344 | Opcode_abs_Slot_inst_encode, 0, 0 | |
6345 | }; | |
e0001a05 | 6346 | |
43cd72b9 BW |
6347 | xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { |
6348 | Opcode_nop_Slot_inst_encode, 0, 0 | |
6349 | }; | |
e0001a05 | 6350 | |
43cd72b9 BW |
6351 | xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { |
6352 | Opcode_ret_Slot_inst_encode, 0, 0 | |
6353 | }; | |
e0001a05 | 6354 | |
43cd72b9 BW |
6355 | xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { |
6356 | Opcode_s16i_Slot_inst_encode, 0, 0 | |
6357 | }; | |
e0001a05 | 6358 | |
43cd72b9 BW |
6359 | xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { |
6360 | Opcode_s32i_Slot_inst_encode, 0, 0 | |
6361 | }; | |
e0001a05 | 6362 | |
43cd72b9 BW |
6363 | xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { |
6364 | Opcode_s8i_Slot_inst_encode, 0, 0 | |
6365 | }; | |
e0001a05 | 6366 | |
43cd72b9 BW |
6367 | xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { |
6368 | Opcode_ssr_Slot_inst_encode, 0, 0 | |
6369 | }; | |
e0001a05 | 6370 | |
43cd72b9 BW |
6371 | xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { |
6372 | Opcode_ssl_Slot_inst_encode, 0, 0 | |
6373 | }; | |
e0001a05 | 6374 | |
43cd72b9 BW |
6375 | xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { |
6376 | Opcode_ssa8l_Slot_inst_encode, 0, 0 | |
6377 | }; | |
e0001a05 | 6378 | |
43cd72b9 BW |
6379 | xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { |
6380 | Opcode_ssa8b_Slot_inst_encode, 0, 0 | |
6381 | }; | |
e0001a05 | 6382 | |
43cd72b9 BW |
6383 | xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { |
6384 | Opcode_ssai_Slot_inst_encode, 0, 0 | |
6385 | }; | |
e0001a05 | 6386 | |
43cd72b9 BW |
6387 | xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { |
6388 | Opcode_sll_Slot_inst_encode, 0, 0 | |
6389 | }; | |
e0001a05 | 6390 | |
43cd72b9 BW |
6391 | xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { |
6392 | Opcode_src_Slot_inst_encode, 0, 0 | |
6393 | }; | |
e0001a05 | 6394 | |
43cd72b9 BW |
6395 | xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { |
6396 | Opcode_srl_Slot_inst_encode, 0, 0 | |
6397 | }; | |
e0001a05 | 6398 | |
43cd72b9 BW |
6399 | xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { |
6400 | Opcode_sra_Slot_inst_encode, 0, 0 | |
6401 | }; | |
e0001a05 | 6402 | |
43cd72b9 BW |
6403 | xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { |
6404 | Opcode_slli_Slot_inst_encode, 0, 0 | |
6405 | }; | |
e0001a05 | 6406 | |
43cd72b9 BW |
6407 | xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { |
6408 | Opcode_srai_Slot_inst_encode, 0, 0 | |
6409 | }; | |
e0001a05 | 6410 | |
43cd72b9 BW |
6411 | xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { |
6412 | Opcode_srli_Slot_inst_encode, 0, 0 | |
6413 | }; | |
e0001a05 | 6414 | |
43cd72b9 BW |
6415 | xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { |
6416 | Opcode_memw_Slot_inst_encode, 0, 0 | |
6417 | }; | |
e0001a05 | 6418 | |
43cd72b9 BW |
6419 | xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { |
6420 | Opcode_extw_Slot_inst_encode, 0, 0 | |
6421 | }; | |
e0001a05 | 6422 | |
43cd72b9 BW |
6423 | xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { |
6424 | Opcode_isync_Slot_inst_encode, 0, 0 | |
6425 | }; | |
e0001a05 | 6426 | |
43cd72b9 BW |
6427 | xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { |
6428 | Opcode_rsync_Slot_inst_encode, 0, 0 | |
6429 | }; | |
e0001a05 | 6430 | |
43cd72b9 BW |
6431 | xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { |
6432 | Opcode_esync_Slot_inst_encode, 0, 0 | |
6433 | }; | |
e0001a05 | 6434 | |
43cd72b9 BW |
6435 | xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { |
6436 | Opcode_dsync_Slot_inst_encode, 0, 0 | |
6437 | }; | |
e0001a05 | 6438 | |
43cd72b9 BW |
6439 | xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { |
6440 | Opcode_rsil_Slot_inst_encode, 0, 0 | |
6441 | }; | |
e0001a05 | 6442 | |
43cd72b9 BW |
6443 | xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { |
6444 | Opcode_rsr_lend_Slot_inst_encode, 0, 0 | |
6445 | }; | |
e0001a05 | 6446 | |
43cd72b9 BW |
6447 | xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { |
6448 | Opcode_wsr_lend_Slot_inst_encode, 0, 0 | |
6449 | }; | |
e0001a05 | 6450 | |
43cd72b9 BW |
6451 | xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { |
6452 | Opcode_xsr_lend_Slot_inst_encode, 0, 0 | |
6453 | }; | |
e0001a05 | 6454 | |
43cd72b9 BW |
6455 | xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { |
6456 | Opcode_rsr_lcount_Slot_inst_encode, 0, 0 | |
6457 | }; | |
e0001a05 | 6458 | |
43cd72b9 BW |
6459 | xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { |
6460 | Opcode_wsr_lcount_Slot_inst_encode, 0, 0 | |
6461 | }; | |
e0001a05 | 6462 | |
43cd72b9 BW |
6463 | xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { |
6464 | Opcode_xsr_lcount_Slot_inst_encode, 0, 0 | |
6465 | }; | |
e0001a05 | 6466 | |
43cd72b9 BW |
6467 | xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { |
6468 | Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 | |
6469 | }; | |
e0001a05 | 6470 | |
43cd72b9 BW |
6471 | xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { |
6472 | Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 | |
6473 | }; | |
e0001a05 | 6474 | |
43cd72b9 BW |
6475 | xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { |
6476 | Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6477 | }; |
6478 | ||
43cd72b9 BW |
6479 | xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { |
6480 | Opcode_rsr_sar_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6481 | }; |
6482 | ||
43cd72b9 BW |
6483 | xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { |
6484 | Opcode_wsr_sar_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6485 | }; |
6486 | ||
43cd72b9 BW |
6487 | xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { |
6488 | Opcode_xsr_sar_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6489 | }; |
6490 | ||
43cd72b9 BW |
6491 | xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { |
6492 | Opcode_rsr_litbase_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6493 | }; |
6494 | ||
43cd72b9 BW |
6495 | xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { |
6496 | Opcode_wsr_litbase_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6497 | }; |
6498 | ||
43cd72b9 BW |
6499 | xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { |
6500 | Opcode_xsr_litbase_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6501 | }; |
6502 | ||
43cd72b9 BW |
6503 | xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { |
6504 | Opcode_rsr_176_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6505 | }; |
6506 | ||
43cd72b9 BW |
6507 | xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { |
6508 | Opcode_rsr_208_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6509 | }; |
6510 | ||
43cd72b9 BW |
6511 | xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { |
6512 | Opcode_rsr_ps_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6513 | }; |
6514 | ||
43cd72b9 BW |
6515 | xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { |
6516 | Opcode_wsr_ps_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6517 | }; |
6518 | ||
43cd72b9 BW |
6519 | xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { |
6520 | Opcode_xsr_ps_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6521 | }; |
6522 | ||
43cd72b9 BW |
6523 | xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { |
6524 | Opcode_rsr_epc1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6525 | }; |
6526 | ||
43cd72b9 BW |
6527 | xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { |
6528 | Opcode_wsr_epc1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6529 | }; |
6530 | ||
43cd72b9 BW |
6531 | xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { |
6532 | Opcode_xsr_epc1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6533 | }; |
6534 | ||
43cd72b9 BW |
6535 | xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { |
6536 | Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6537 | }; |
6538 | ||
43cd72b9 BW |
6539 | xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { |
6540 | Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6541 | }; |
6542 | ||
43cd72b9 BW |
6543 | xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { |
6544 | Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6545 | }; |
6546 | ||
43cd72b9 BW |
6547 | xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { |
6548 | Opcode_rsr_epc2_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6549 | }; |
6550 | ||
43cd72b9 BW |
6551 | xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { |
6552 | Opcode_wsr_epc2_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6553 | }; |
6554 | ||
43cd72b9 BW |
6555 | xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { |
6556 | Opcode_xsr_epc2_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6557 | }; |
6558 | ||
43cd72b9 BW |
6559 | xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { |
6560 | Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6561 | }; |
6562 | ||
43cd72b9 BW |
6563 | xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { |
6564 | Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6565 | }; |
6566 | ||
43cd72b9 BW |
6567 | xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { |
6568 | Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6569 | }; |
6570 | ||
43cd72b9 BW |
6571 | xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { |
6572 | Opcode_rsr_epc3_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6573 | }; |
6574 | ||
43cd72b9 BW |
6575 | xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { |
6576 | Opcode_wsr_epc3_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6577 | }; |
6578 | ||
43cd72b9 BW |
6579 | xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { |
6580 | Opcode_xsr_epc3_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6581 | }; |
6582 | ||
43cd72b9 BW |
6583 | xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { |
6584 | Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6585 | }; |
6586 | ||
43cd72b9 BW |
6587 | xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { |
6588 | Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6589 | }; |
6590 | ||
43cd72b9 BW |
6591 | xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { |
6592 | Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6593 | }; |
6594 | ||
43cd72b9 BW |
6595 | xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { |
6596 | Opcode_rsr_epc4_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6597 | }; |
6598 | ||
43cd72b9 BW |
6599 | xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { |
6600 | Opcode_wsr_epc4_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6601 | }; |
6602 | ||
43cd72b9 BW |
6603 | xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { |
6604 | Opcode_xsr_epc4_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6605 | }; |
6606 | ||
43cd72b9 BW |
6607 | xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { |
6608 | Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6609 | }; |
6610 | ||
43cd72b9 BW |
6611 | xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { |
6612 | Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6613 | }; |
6614 | ||
43cd72b9 BW |
6615 | xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { |
6616 | Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6617 | }; |
6618 | ||
43cd72b9 BW |
6619 | xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { |
6620 | Opcode_rsr_eps2_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6621 | }; |
6622 | ||
43cd72b9 BW |
6623 | xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { |
6624 | Opcode_wsr_eps2_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6625 | }; |
6626 | ||
43cd72b9 BW |
6627 | xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { |
6628 | Opcode_xsr_eps2_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6629 | }; |
6630 | ||
43cd72b9 BW |
6631 | xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { |
6632 | Opcode_rsr_eps3_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6633 | }; |
6634 | ||
43cd72b9 BW |
6635 | xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { |
6636 | Opcode_wsr_eps3_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6637 | }; |
6638 | ||
43cd72b9 BW |
6639 | xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { |
6640 | Opcode_xsr_eps3_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6641 | }; |
6642 | ||
43cd72b9 BW |
6643 | xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { |
6644 | Opcode_rsr_eps4_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6645 | }; |
6646 | ||
43cd72b9 BW |
6647 | xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { |
6648 | Opcode_wsr_eps4_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6649 | }; |
6650 | ||
43cd72b9 BW |
6651 | xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { |
6652 | Opcode_xsr_eps4_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6653 | }; |
6654 | ||
43cd72b9 BW |
6655 | xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { |
6656 | Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6657 | }; |
6658 | ||
43cd72b9 BW |
6659 | xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { |
6660 | Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6661 | }; |
6662 | ||
43cd72b9 BW |
6663 | xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { |
6664 | Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6665 | }; |
6666 | ||
43cd72b9 BW |
6667 | xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { |
6668 | Opcode_rsr_depc_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6669 | }; |
6670 | ||
43cd72b9 BW |
6671 | xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { |
6672 | Opcode_wsr_depc_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6673 | }; |
6674 | ||
43cd72b9 BW |
6675 | xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { |
6676 | Opcode_xsr_depc_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6677 | }; |
6678 | ||
43cd72b9 BW |
6679 | xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { |
6680 | Opcode_rsr_exccause_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6681 | }; |
6682 | ||
43cd72b9 BW |
6683 | xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { |
6684 | Opcode_wsr_exccause_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6685 | }; |
6686 | ||
43cd72b9 BW |
6687 | xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { |
6688 | Opcode_xsr_exccause_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6689 | }; |
6690 | ||
43cd72b9 BW |
6691 | xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { |
6692 | Opcode_rsr_misc0_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6693 | }; |
6694 | ||
43cd72b9 BW |
6695 | xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { |
6696 | Opcode_wsr_misc0_Slot_inst_encode, 0, 0 | |
6697 | }; | |
6698 | ||
6699 | xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { | |
6700 | Opcode_xsr_misc0_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6701 | }; |
6702 | ||
43cd72b9 BW |
6703 | xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { |
6704 | Opcode_rsr_misc1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6705 | }; |
6706 | ||
43cd72b9 BW |
6707 | xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { |
6708 | Opcode_wsr_misc1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6709 | }; |
6710 | ||
43cd72b9 BW |
6711 | xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { |
6712 | Opcode_xsr_misc1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6713 | }; |
6714 | ||
43cd72b9 BW |
6715 | xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { |
6716 | Opcode_rsr_prid_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6717 | }; |
6718 | ||
43cd72b9 BW |
6719 | xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { |
6720 | Opcode_rfi_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6721 | }; |
6722 | ||
43cd72b9 BW |
6723 | xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { |
6724 | Opcode_waiti_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6725 | }; |
6726 | ||
43cd72b9 BW |
6727 | xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { |
6728 | Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6729 | }; |
6730 | ||
43cd72b9 BW |
6731 | xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { |
6732 | Opcode_wsr_intset_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6733 | }; |
6734 | ||
43cd72b9 BW |
6735 | xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { |
6736 | Opcode_wsr_intclear_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6737 | }; |
6738 | ||
43cd72b9 BW |
6739 | xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { |
6740 | Opcode_rsr_intenable_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6741 | }; |
6742 | ||
43cd72b9 BW |
6743 | xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { |
6744 | Opcode_wsr_intenable_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6745 | }; |
6746 | ||
43cd72b9 BW |
6747 | xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { |
6748 | Opcode_xsr_intenable_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6749 | }; |
6750 | ||
43cd72b9 BW |
6751 | xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { |
6752 | Opcode_break_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6753 | }; |
6754 | ||
43cd72b9 BW |
6755 | xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { |
6756 | 0, 0, Opcode_break_n_Slot_inst16b_encode | |
e0001a05 NC |
6757 | }; |
6758 | ||
43cd72b9 BW |
6759 | xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { |
6760 | Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6761 | }; |
6762 | ||
43cd72b9 BW |
6763 | xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { |
6764 | Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6765 | }; |
6766 | ||
43cd72b9 BW |
6767 | xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { |
6768 | Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6769 | }; |
6770 | ||
43cd72b9 BW |
6771 | xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { |
6772 | Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6773 | }; |
6774 | ||
43cd72b9 BW |
6775 | xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { |
6776 | Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6777 | }; |
6778 | ||
43cd72b9 BW |
6779 | xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { |
6780 | Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6781 | }; |
6782 | ||
43cd72b9 BW |
6783 | xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { |
6784 | Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6785 | }; |
6786 | ||
43cd72b9 BW |
6787 | xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { |
6788 | Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6789 | }; |
6790 | ||
43cd72b9 BW |
6791 | xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { |
6792 | Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6793 | }; |
6794 | ||
43cd72b9 BW |
6795 | xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { |
6796 | Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6797 | }; |
6798 | ||
43cd72b9 BW |
6799 | xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { |
6800 | Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6801 | }; |
6802 | ||
43cd72b9 BW |
6803 | xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { |
6804 | Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6805 | }; |
6806 | ||
43cd72b9 BW |
6807 | xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { |
6808 | Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6809 | }; |
6810 | ||
43cd72b9 BW |
6811 | xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { |
6812 | Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6813 | }; |
6814 | ||
43cd72b9 BW |
6815 | xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { |
6816 | Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6817 | }; |
6818 | ||
43cd72b9 BW |
6819 | xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { |
6820 | Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6821 | }; |
6822 | ||
43cd72b9 BW |
6823 | xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { |
6824 | Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6825 | }; |
6826 | ||
43cd72b9 BW |
6827 | xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { |
6828 | Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6829 | }; |
6830 | ||
43cd72b9 BW |
6831 | xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { |
6832 | Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6833 | }; |
6834 | ||
43cd72b9 BW |
6835 | xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { |
6836 | Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6837 | }; |
6838 | ||
43cd72b9 BW |
6839 | xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { |
6840 | Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6841 | }; |
6842 | ||
43cd72b9 BW |
6843 | xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { |
6844 | Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6845 | }; |
6846 | ||
43cd72b9 BW |
6847 | xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { |
6848 | Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6849 | }; |
6850 | ||
43cd72b9 BW |
6851 | xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { |
6852 | Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6853 | }; |
6854 | ||
43cd72b9 BW |
6855 | xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { |
6856 | Opcode_rsr_icount_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6857 | }; |
6858 | ||
43cd72b9 BW |
6859 | xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { |
6860 | Opcode_wsr_icount_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6861 | }; |
6862 | ||
43cd72b9 BW |
6863 | xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { |
6864 | Opcode_xsr_icount_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6865 | }; |
6866 | ||
43cd72b9 BW |
6867 | xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { |
6868 | Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6869 | }; |
6870 | ||
43cd72b9 BW |
6871 | xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { |
6872 | Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6873 | }; |
6874 | ||
43cd72b9 BW |
6875 | xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { |
6876 | Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6877 | }; |
6878 | ||
43cd72b9 BW |
6879 | xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { |
6880 | Opcode_rsr_ddr_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6881 | }; |
6882 | ||
43cd72b9 BW |
6883 | xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { |
6884 | Opcode_wsr_ddr_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6885 | }; |
6886 | ||
43cd72b9 BW |
6887 | xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { |
6888 | Opcode_xsr_ddr_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6889 | }; |
6890 | ||
43cd72b9 BW |
6891 | xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { |
6892 | Opcode_rfdo_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6893 | }; |
6894 | ||
43cd72b9 BW |
6895 | xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { |
6896 | Opcode_rfdd_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6897 | }; |
6898 | ||
43cd72b9 BW |
6899 | xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { |
6900 | Opcode_rsr_ccount_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6901 | }; |
6902 | ||
43cd72b9 BW |
6903 | xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { |
6904 | Opcode_wsr_ccount_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6905 | }; |
6906 | ||
43cd72b9 BW |
6907 | xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { |
6908 | Opcode_xsr_ccount_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6909 | }; |
6910 | ||
43cd72b9 BW |
6911 | xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { |
6912 | Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6913 | }; |
6914 | ||
43cd72b9 BW |
6915 | xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { |
6916 | Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6917 | }; |
6918 | ||
43cd72b9 BW |
6919 | xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { |
6920 | Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6921 | }; |
6922 | ||
43cd72b9 BW |
6923 | xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { |
6924 | Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6925 | }; |
6926 | ||
43cd72b9 BW |
6927 | xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { |
6928 | Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6929 | }; |
6930 | ||
43cd72b9 BW |
6931 | xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { |
6932 | Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6933 | }; |
6934 | ||
43cd72b9 BW |
6935 | xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { |
6936 | Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6937 | }; |
6938 | ||
43cd72b9 BW |
6939 | xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { |
6940 | Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6941 | }; |
6942 | ||
43cd72b9 BW |
6943 | xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { |
6944 | Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6945 | }; |
6946 | ||
43cd72b9 BW |
6947 | xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { |
6948 | Opcode_ipf_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6949 | }; |
6950 | ||
43cd72b9 BW |
6951 | xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { |
6952 | Opcode_ihi_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6953 | }; |
6954 | ||
43cd72b9 BW |
6955 | xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { |
6956 | Opcode_iii_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6957 | }; |
6958 | ||
43cd72b9 BW |
6959 | xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { |
6960 | Opcode_lict_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6961 | }; |
6962 | ||
43cd72b9 BW |
6963 | xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { |
6964 | Opcode_licw_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6965 | }; |
6966 | ||
43cd72b9 BW |
6967 | xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { |
6968 | Opcode_sict_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6969 | }; |
6970 | ||
43cd72b9 BW |
6971 | xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { |
6972 | Opcode_sicw_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6973 | }; |
6974 | ||
43cd72b9 BW |
6975 | xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { |
6976 | Opcode_dhwb_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6977 | }; |
6978 | ||
43cd72b9 BW |
6979 | xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { |
6980 | Opcode_dhwbi_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6981 | }; |
6982 | ||
43cd72b9 BW |
6983 | xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { |
6984 | Opcode_diwb_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6985 | }; |
6986 | ||
43cd72b9 BW |
6987 | xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { |
6988 | Opcode_diwbi_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6989 | }; |
6990 | ||
43cd72b9 BW |
6991 | xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { |
6992 | Opcode_dhi_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6993 | }; |
6994 | ||
43cd72b9 BW |
6995 | xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { |
6996 | Opcode_dii_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
6997 | }; |
6998 | ||
43cd72b9 BW |
6999 | xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { |
7000 | Opcode_dpfr_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
7001 | }; |
7002 | ||
43cd72b9 BW |
7003 | xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { |
7004 | Opcode_dpfw_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
7005 | }; |
7006 | ||
43cd72b9 BW |
7007 | xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { |
7008 | Opcode_dpfro_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
7009 | }; |
7010 | ||
43cd72b9 BW |
7011 | xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { |
7012 | Opcode_dpfwo_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
7013 | }; |
7014 | ||
43cd72b9 BW |
7015 | xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { |
7016 | Opcode_sdct_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
7017 | }; |
7018 | ||
43cd72b9 BW |
7019 | xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { |
7020 | Opcode_ldct_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
7021 | }; |
7022 | ||
43cd72b9 BW |
7023 | xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { |
7024 | Opcode_idtlb_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
7025 | }; |
7026 | ||
43cd72b9 BW |
7027 | xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { |
7028 | Opcode_pdtlb_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
7029 | }; |
7030 | ||
43cd72b9 BW |
7031 | xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { |
7032 | Opcode_rdtlb0_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
7033 | }; |
7034 | ||
43cd72b9 BW |
7035 | xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { |
7036 | Opcode_rdtlb1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
7037 | }; |
7038 | ||
43cd72b9 BW |
7039 | xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { |
7040 | Opcode_wdtlb_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
7041 | }; |
7042 | ||
43cd72b9 BW |
7043 | xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { |
7044 | Opcode_iitlb_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
7045 | }; |
7046 | ||
43cd72b9 BW |
7047 | xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { |
7048 | Opcode_pitlb_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
7049 | }; |
7050 | ||
43cd72b9 BW |
7051 | xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { |
7052 | Opcode_ritlb0_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
7053 | }; |
7054 | ||
43cd72b9 BW |
7055 | xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { |
7056 | Opcode_ritlb1_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
7057 | }; |
7058 | ||
43cd72b9 BW |
7059 | xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { |
7060 | Opcode_witlb_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
7061 | }; |
7062 | ||
43cd72b9 BW |
7063 | xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { |
7064 | Opcode_nsa_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
7065 | }; |
7066 | ||
43cd72b9 BW |
7067 | xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { |
7068 | Opcode_nsau_Slot_inst_encode, 0, 0 | |
e0001a05 NC |
7069 | }; |
7070 | ||
43cd72b9 BW |
7071 | \f |
7072 | /* Opcode table. */ | |
7073 | ||
7074 | static xtensa_opcode_internal opcodes[] = { | |
7075 | { "excw", 0 /* xt_iclass_excw */, | |
7076 | 0, | |
7077 | Opcode_excw_encode_fns, 0, 0 }, | |
7078 | { "rfe", 1 /* xt_iclass_rfe */, | |
7079 | XTENSA_OPCODE_IS_JUMP, | |
7080 | Opcode_rfe_encode_fns, 0, 0 }, | |
7081 | { "rfde", 2 /* xt_iclass_rfde */, | |
7082 | XTENSA_OPCODE_IS_JUMP, | |
7083 | Opcode_rfde_encode_fns, 0, 0 }, | |
7084 | { "syscall", 3 /* xt_iclass_syscall */, | |
7085 | 0, | |
7086 | Opcode_syscall_encode_fns, 0, 0 }, | |
7087 | { "simcall", 4 /* xt_iclass_simcall */, | |
7088 | 0, | |
7089 | Opcode_simcall_encode_fns, 0, 0 }, | |
7090 | { "call12", 5 /* xt_iclass_call12 */, | |
7091 | XTENSA_OPCODE_IS_CALL, | |
7092 | Opcode_call12_encode_fns, 0, 0 }, | |
7093 | { "call8", 6 /* xt_iclass_call8 */, | |
7094 | XTENSA_OPCODE_IS_CALL, | |
7095 | Opcode_call8_encode_fns, 0, 0 }, | |
7096 | { "call4", 7 /* xt_iclass_call4 */, | |
7097 | XTENSA_OPCODE_IS_CALL, | |
7098 | Opcode_call4_encode_fns, 0, 0 }, | |
7099 | { "callx12", 8 /* xt_iclass_callx12 */, | |
7100 | XTENSA_OPCODE_IS_CALL, | |
7101 | Opcode_callx12_encode_fns, 0, 0 }, | |
7102 | { "callx8", 9 /* xt_iclass_callx8 */, | |
7103 | XTENSA_OPCODE_IS_CALL, | |
7104 | Opcode_callx8_encode_fns, 0, 0 }, | |
7105 | { "callx4", 10 /* xt_iclass_callx4 */, | |
7106 | XTENSA_OPCODE_IS_CALL, | |
7107 | Opcode_callx4_encode_fns, 0, 0 }, | |
7108 | { "entry", 11 /* xt_iclass_entry */, | |
7109 | 0, | |
7110 | Opcode_entry_encode_fns, 0, 0 }, | |
7111 | { "movsp", 12 /* xt_iclass_movsp */, | |
7112 | 0, | |
7113 | Opcode_movsp_encode_fns, 0, 0 }, | |
7114 | { "rotw", 13 /* xt_iclass_rotw */, | |
7115 | 0, | |
7116 | Opcode_rotw_encode_fns, 0, 0 }, | |
7117 | { "retw", 14 /* xt_iclass_retw */, | |
7118 | XTENSA_OPCODE_IS_JUMP, | |
7119 | Opcode_retw_encode_fns, 0, 0 }, | |
7120 | { "retw.n", 14 /* xt_iclass_retw */, | |
7121 | XTENSA_OPCODE_IS_JUMP, | |
7122 | Opcode_retw_n_encode_fns, 0, 0 }, | |
7123 | { "rfwo", 15 /* xt_iclass_rfwou */, | |
7124 | XTENSA_OPCODE_IS_JUMP, | |
7125 | Opcode_rfwo_encode_fns, 0, 0 }, | |
7126 | { "rfwu", 15 /* xt_iclass_rfwou */, | |
7127 | XTENSA_OPCODE_IS_JUMP, | |
7128 | Opcode_rfwu_encode_fns, 0, 0 }, | |
7129 | { "l32e", 16 /* xt_iclass_l32e */, | |
7130 | 0, | |
7131 | Opcode_l32e_encode_fns, 0, 0 }, | |
7132 | { "s32e", 17 /* xt_iclass_s32e */, | |
7133 | 0, | |
7134 | Opcode_s32e_encode_fns, 0, 0 }, | |
7135 | { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */, | |
7136 | 0, | |
7137 | Opcode_rsr_windowbase_encode_fns, 0, 0 }, | |
7138 | { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */, | |
7139 | 0, | |
7140 | Opcode_wsr_windowbase_encode_fns, 0, 0 }, | |
7141 | { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */, | |
7142 | 0, | |
7143 | Opcode_xsr_windowbase_encode_fns, 0, 0 }, | |
7144 | { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */, | |
7145 | 0, | |
7146 | Opcode_rsr_windowstart_encode_fns, 0, 0 }, | |
7147 | { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */, | |
7148 | 0, | |
7149 | Opcode_wsr_windowstart_encode_fns, 0, 0 }, | |
7150 | { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */, | |
7151 | 0, | |
7152 | Opcode_xsr_windowstart_encode_fns, 0, 0 }, | |
7153 | { "add.n", 24 /* xt_iclass_add.n */, | |
7154 | 0, | |
7155 | Opcode_add_n_encode_fns, 0, 0 }, | |
7156 | { "addi.n", 25 /* xt_iclass_addi.n */, | |
7157 | 0, | |
7158 | Opcode_addi_n_encode_fns, 0, 0 }, | |
7159 | { "beqz.n", 26 /* xt_iclass_bz6 */, | |
7160 | XTENSA_OPCODE_IS_BRANCH, | |
7161 | Opcode_beqz_n_encode_fns, 0, 0 }, | |
7162 | { "bnez.n", 26 /* xt_iclass_bz6 */, | |
7163 | XTENSA_OPCODE_IS_BRANCH, | |
7164 | Opcode_bnez_n_encode_fns, 0, 0 }, | |
7165 | { "ill.n", 27 /* xt_iclass_ill.n */, | |
7166 | 0, | |
7167 | Opcode_ill_n_encode_fns, 0, 0 }, | |
7168 | { "l32i.n", 28 /* xt_iclass_loadi4 */, | |
7169 | 0, | |
7170 | Opcode_l32i_n_encode_fns, 0, 0 }, | |
7171 | { "mov.n", 29 /* xt_iclass_mov.n */, | |
7172 | 0, | |
7173 | Opcode_mov_n_encode_fns, 0, 0 }, | |
7174 | { "movi.n", 30 /* xt_iclass_movi.n */, | |
7175 | 0, | |
7176 | Opcode_movi_n_encode_fns, 0, 0 }, | |
7177 | { "nop.n", 31 /* xt_iclass_nopn */, | |
7178 | 0, | |
7179 | Opcode_nop_n_encode_fns, 0, 0 }, | |
7180 | { "ret.n", 32 /* xt_iclass_retn */, | |
7181 | XTENSA_OPCODE_IS_JUMP, | |
7182 | Opcode_ret_n_encode_fns, 0, 0 }, | |
7183 | { "s32i.n", 33 /* xt_iclass_storei4 */, | |
7184 | 0, | |
7185 | Opcode_s32i_n_encode_fns, 0, 0 }, | |
7186 | { "addi", 34 /* xt_iclass_addi */, | |
7187 | 0, | |
7188 | Opcode_addi_encode_fns, 0, 0 }, | |
7189 | { "addmi", 35 /* xt_iclass_addmi */, | |
7190 | 0, | |
7191 | Opcode_addmi_encode_fns, 0, 0 }, | |
7192 | { "add", 36 /* xt_iclass_addsub */, | |
7193 | 0, | |
7194 | Opcode_add_encode_fns, 0, 0 }, | |
7195 | { "sub", 36 /* xt_iclass_addsub */, | |
7196 | 0, | |
7197 | Opcode_sub_encode_fns, 0, 0 }, | |
7198 | { "addx2", 36 /* xt_iclass_addsub */, | |
7199 | 0, | |
7200 | Opcode_addx2_encode_fns, 0, 0 }, | |
7201 | { "addx4", 36 /* xt_iclass_addsub */, | |
7202 | 0, | |
7203 | Opcode_addx4_encode_fns, 0, 0 }, | |
7204 | { "addx8", 36 /* xt_iclass_addsub */, | |
7205 | 0, | |
7206 | Opcode_addx8_encode_fns, 0, 0 }, | |
7207 | { "subx2", 36 /* xt_iclass_addsub */, | |
7208 | 0, | |
7209 | Opcode_subx2_encode_fns, 0, 0 }, | |
7210 | { "subx4", 36 /* xt_iclass_addsub */, | |
7211 | 0, | |
7212 | Opcode_subx4_encode_fns, 0, 0 }, | |
7213 | { "subx8", 36 /* xt_iclass_addsub */, | |
7214 | 0, | |
7215 | Opcode_subx8_encode_fns, 0, 0 }, | |
7216 | { "and", 37 /* xt_iclass_bit */, | |
7217 | 0, | |
7218 | Opcode_and_encode_fns, 0, 0 }, | |
7219 | { "or", 37 /* xt_iclass_bit */, | |
7220 | 0, | |
7221 | Opcode_or_encode_fns, 0, 0 }, | |
7222 | { "xor", 37 /* xt_iclass_bit */, | |
7223 | 0, | |
7224 | Opcode_xor_encode_fns, 0, 0 }, | |
7225 | { "beqi", 38 /* xt_iclass_bsi8 */, | |
7226 | XTENSA_OPCODE_IS_BRANCH, | |
7227 | Opcode_beqi_encode_fns, 0, 0 }, | |
7228 | { "bnei", 38 /* xt_iclass_bsi8 */, | |
7229 | XTENSA_OPCODE_IS_BRANCH, | |
7230 | Opcode_bnei_encode_fns, 0, 0 }, | |
7231 | { "bgei", 38 /* xt_iclass_bsi8 */, | |
7232 | XTENSA_OPCODE_IS_BRANCH, | |
7233 | Opcode_bgei_encode_fns, 0, 0 }, | |
7234 | { "blti", 38 /* xt_iclass_bsi8 */, | |
7235 | XTENSA_OPCODE_IS_BRANCH, | |
7236 | Opcode_blti_encode_fns, 0, 0 }, | |
7237 | { "bbci", 39 /* xt_iclass_bsi8b */, | |
7238 | XTENSA_OPCODE_IS_BRANCH, | |
7239 | Opcode_bbci_encode_fns, 0, 0 }, | |
7240 | { "bbsi", 39 /* xt_iclass_bsi8b */, | |
7241 | XTENSA_OPCODE_IS_BRANCH, | |
7242 | Opcode_bbsi_encode_fns, 0, 0 }, | |
7243 | { "bgeui", 40 /* xt_iclass_bsi8u */, | |
7244 | XTENSA_OPCODE_IS_BRANCH, | |
7245 | Opcode_bgeui_encode_fns, 0, 0 }, | |
7246 | { "bltui", 40 /* xt_iclass_bsi8u */, | |
7247 | XTENSA_OPCODE_IS_BRANCH, | |
7248 | Opcode_bltui_encode_fns, 0, 0 }, | |
7249 | { "beq", 41 /* xt_iclass_bst8 */, | |
7250 | XTENSA_OPCODE_IS_BRANCH, | |
7251 | Opcode_beq_encode_fns, 0, 0 }, | |
7252 | { "bne", 41 /* xt_iclass_bst8 */, | |
7253 | XTENSA_OPCODE_IS_BRANCH, | |
7254 | Opcode_bne_encode_fns, 0, 0 }, | |
7255 | { "bge", 41 /* xt_iclass_bst8 */, | |
7256 | XTENSA_OPCODE_IS_BRANCH, | |
7257 | Opcode_bge_encode_fns, 0, 0 }, | |
7258 | { "blt", 41 /* xt_iclass_bst8 */, | |
7259 | XTENSA_OPCODE_IS_BRANCH, | |
7260 | Opcode_blt_encode_fns, 0, 0 }, | |
7261 | { "bgeu", 41 /* xt_iclass_bst8 */, | |
7262 | XTENSA_OPCODE_IS_BRANCH, | |
7263 | Opcode_bgeu_encode_fns, 0, 0 }, | |
7264 | { "bltu", 41 /* xt_iclass_bst8 */, | |
7265 | XTENSA_OPCODE_IS_BRANCH, | |
7266 | Opcode_bltu_encode_fns, 0, 0 }, | |
7267 | { "bany", 41 /* xt_iclass_bst8 */, | |
7268 | XTENSA_OPCODE_IS_BRANCH, | |
7269 | Opcode_bany_encode_fns, 0, 0 }, | |
7270 | { "bnone", 41 /* xt_iclass_bst8 */, | |
7271 | XTENSA_OPCODE_IS_BRANCH, | |
7272 | Opcode_bnone_encode_fns, 0, 0 }, | |
7273 | { "ball", 41 /* xt_iclass_bst8 */, | |
7274 | XTENSA_OPCODE_IS_BRANCH, | |
7275 | Opcode_ball_encode_fns, 0, 0 }, | |
7276 | { "bnall", 41 /* xt_iclass_bst8 */, | |
7277 | XTENSA_OPCODE_IS_BRANCH, | |
7278 | Opcode_bnall_encode_fns, 0, 0 }, | |
7279 | { "bbc", 41 /* xt_iclass_bst8 */, | |
7280 | XTENSA_OPCODE_IS_BRANCH, | |
7281 | Opcode_bbc_encode_fns, 0, 0 }, | |
7282 | { "bbs", 41 /* xt_iclass_bst8 */, | |
7283 | XTENSA_OPCODE_IS_BRANCH, | |
7284 | Opcode_bbs_encode_fns, 0, 0 }, | |
7285 | { "beqz", 42 /* xt_iclass_bsz12 */, | |
7286 | XTENSA_OPCODE_IS_BRANCH, | |
7287 | Opcode_beqz_encode_fns, 0, 0 }, | |
7288 | { "bnez", 42 /* xt_iclass_bsz12 */, | |
7289 | XTENSA_OPCODE_IS_BRANCH, | |
7290 | Opcode_bnez_encode_fns, 0, 0 }, | |
7291 | { "bgez", 42 /* xt_iclass_bsz12 */, | |
7292 | XTENSA_OPCODE_IS_BRANCH, | |
7293 | Opcode_bgez_encode_fns, 0, 0 }, | |
7294 | { "bltz", 42 /* xt_iclass_bsz12 */, | |
7295 | XTENSA_OPCODE_IS_BRANCH, | |
7296 | Opcode_bltz_encode_fns, 0, 0 }, | |
7297 | { "call0", 43 /* xt_iclass_call0 */, | |
7298 | XTENSA_OPCODE_IS_CALL, | |
7299 | Opcode_call0_encode_fns, 0, 0 }, | |
7300 | { "callx0", 44 /* xt_iclass_callx0 */, | |
7301 | XTENSA_OPCODE_IS_CALL, | |
7302 | Opcode_callx0_encode_fns, 0, 0 }, | |
7303 | { "extui", 45 /* xt_iclass_exti */, | |
7304 | 0, | |
7305 | Opcode_extui_encode_fns, 0, 0 }, | |
7306 | { "ill", 46 /* xt_iclass_ill */, | |
7307 | 0, | |
7308 | Opcode_ill_encode_fns, 0, 0 }, | |
7309 | { "j", 47 /* xt_iclass_jump */, | |
7310 | XTENSA_OPCODE_IS_JUMP, | |
7311 | Opcode_j_encode_fns, 0, 0 }, | |
7312 | { "jx", 48 /* xt_iclass_jumpx */, | |
7313 | XTENSA_OPCODE_IS_JUMP, | |
7314 | Opcode_jx_encode_fns, 0, 0 }, | |
7315 | { "l16ui", 49 /* xt_iclass_l16ui */, | |
7316 | 0, | |
7317 | Opcode_l16ui_encode_fns, 0, 0 }, | |
7318 | { "l16si", 50 /* xt_iclass_l16si */, | |
7319 | 0, | |
7320 | Opcode_l16si_encode_fns, 0, 0 }, | |
7321 | { "l32i", 51 /* xt_iclass_l32i */, | |
7322 | 0, | |
7323 | Opcode_l32i_encode_fns, 0, 0 }, | |
7324 | { "l32r", 52 /* xt_iclass_l32r */, | |
7325 | 0, | |
7326 | Opcode_l32r_encode_fns, 0, 0 }, | |
7327 | { "l8ui", 53 /* xt_iclass_l8i */, | |
7328 | 0, | |
7329 | Opcode_l8ui_encode_fns, 0, 0 }, | |
7330 | { "loop", 54 /* xt_iclass_loop */, | |
7331 | XTENSA_OPCODE_IS_LOOP, | |
7332 | Opcode_loop_encode_fns, 0, 0 }, | |
7333 | { "loopnez", 55 /* xt_iclass_loopz */, | |
7334 | XTENSA_OPCODE_IS_LOOP, | |
7335 | Opcode_loopnez_encode_fns, 0, 0 }, | |
7336 | { "loopgtz", 55 /* xt_iclass_loopz */, | |
7337 | XTENSA_OPCODE_IS_LOOP, | |
7338 | Opcode_loopgtz_encode_fns, 0, 0 }, | |
7339 | { "movi", 56 /* xt_iclass_movi */, | |
7340 | 0, | |
7341 | Opcode_movi_encode_fns, 0, 0 }, | |
7342 | { "moveqz", 57 /* xt_iclass_movz */, | |
7343 | 0, | |
7344 | Opcode_moveqz_encode_fns, 0, 0 }, | |
7345 | { "movnez", 57 /* xt_iclass_movz */, | |
7346 | 0, | |
7347 | Opcode_movnez_encode_fns, 0, 0 }, | |
7348 | { "movltz", 57 /* xt_iclass_movz */, | |
7349 | 0, | |
7350 | Opcode_movltz_encode_fns, 0, 0 }, | |
7351 | { "movgez", 57 /* xt_iclass_movz */, | |
7352 | 0, | |
7353 | Opcode_movgez_encode_fns, 0, 0 }, | |
7354 | { "neg", 58 /* xt_iclass_neg */, | |
7355 | 0, | |
7356 | Opcode_neg_encode_fns, 0, 0 }, | |
7357 | { "abs", 58 /* xt_iclass_neg */, | |
7358 | 0, | |
7359 | Opcode_abs_encode_fns, 0, 0 }, | |
7360 | { "nop", 59 /* xt_iclass_nop */, | |
7361 | 0, | |
7362 | Opcode_nop_encode_fns, 0, 0 }, | |
7363 | { "ret", 60 /* xt_iclass_return */, | |
7364 | XTENSA_OPCODE_IS_JUMP, | |
7365 | Opcode_ret_encode_fns, 0, 0 }, | |
7366 | { "s16i", 61 /* xt_iclass_s16i */, | |
7367 | 0, | |
7368 | Opcode_s16i_encode_fns, 0, 0 }, | |
7369 | { "s32i", 62 /* xt_iclass_s32i */, | |
7370 | 0, | |
7371 | Opcode_s32i_encode_fns, 0, 0 }, | |
7372 | { "s8i", 63 /* xt_iclass_s8i */, | |
7373 | 0, | |
7374 | Opcode_s8i_encode_fns, 0, 0 }, | |
7375 | { "ssr", 64 /* xt_iclass_sar */, | |
7376 | 0, | |
7377 | Opcode_ssr_encode_fns, 0, 0 }, | |
7378 | { "ssl", 64 /* xt_iclass_sar */, | |
7379 | 0, | |
7380 | Opcode_ssl_encode_fns, 0, 0 }, | |
7381 | { "ssa8l", 64 /* xt_iclass_sar */, | |
7382 | 0, | |
7383 | Opcode_ssa8l_encode_fns, 0, 0 }, | |
7384 | { "ssa8b", 64 /* xt_iclass_sar */, | |
7385 | 0, | |
7386 | Opcode_ssa8b_encode_fns, 0, 0 }, | |
7387 | { "ssai", 65 /* xt_iclass_sari */, | |
7388 | 0, | |
7389 | Opcode_ssai_encode_fns, 0, 0 }, | |
7390 | { "sll", 66 /* xt_iclass_shifts */, | |
7391 | 0, | |
7392 | Opcode_sll_encode_fns, 0, 0 }, | |
7393 | { "src", 67 /* xt_iclass_shiftst */, | |
7394 | 0, | |
7395 | Opcode_src_encode_fns, 0, 0 }, | |
7396 | { "srl", 68 /* xt_iclass_shiftt */, | |
7397 | 0, | |
7398 | Opcode_srl_encode_fns, 0, 0 }, | |
7399 | { "sra", 68 /* xt_iclass_shiftt */, | |
7400 | 0, | |
7401 | Opcode_sra_encode_fns, 0, 0 }, | |
7402 | { "slli", 69 /* xt_iclass_slli */, | |
7403 | 0, | |
7404 | Opcode_slli_encode_fns, 0, 0 }, | |
7405 | { "srai", 70 /* xt_iclass_srai */, | |
7406 | 0, | |
7407 | Opcode_srai_encode_fns, 0, 0 }, | |
7408 | { "srli", 71 /* xt_iclass_srli */, | |
7409 | 0, | |
7410 | Opcode_srli_encode_fns, 0, 0 }, | |
7411 | { "memw", 72 /* xt_iclass_memw */, | |
7412 | 0, | |
7413 | Opcode_memw_encode_fns, 0, 0 }, | |
7414 | { "extw", 73 /* xt_iclass_extw */, | |
7415 | 0, | |
7416 | Opcode_extw_encode_fns, 0, 0 }, | |
7417 | { "isync", 74 /* xt_iclass_isync */, | |
7418 | 0, | |
7419 | Opcode_isync_encode_fns, 0, 0 }, | |
7420 | { "rsync", 75 /* xt_iclass_sync */, | |
7421 | 0, | |
7422 | Opcode_rsync_encode_fns, 0, 0 }, | |
7423 | { "esync", 75 /* xt_iclass_sync */, | |
7424 | 0, | |
7425 | Opcode_esync_encode_fns, 0, 0 }, | |
7426 | { "dsync", 75 /* xt_iclass_sync */, | |
7427 | 0, | |
7428 | Opcode_dsync_encode_fns, 0, 0 }, | |
7429 | { "rsil", 76 /* xt_iclass_rsil */, | |
7430 | 0, | |
7431 | Opcode_rsil_encode_fns, 0, 0 }, | |
7432 | { "rsr.lend", 77 /* xt_iclass_rsr.lend */, | |
7433 | 0, | |
7434 | Opcode_rsr_lend_encode_fns, 0, 0 }, | |
7435 | { "wsr.lend", 78 /* xt_iclass_wsr.lend */, | |
7436 | 0, | |
7437 | Opcode_wsr_lend_encode_fns, 0, 0 }, | |
7438 | { "xsr.lend", 79 /* xt_iclass_xsr.lend */, | |
7439 | 0, | |
7440 | Opcode_xsr_lend_encode_fns, 0, 0 }, | |
7441 | { "rsr.lcount", 80 /* xt_iclass_rsr.lcount */, | |
7442 | 0, | |
7443 | Opcode_rsr_lcount_encode_fns, 0, 0 }, | |
7444 | { "wsr.lcount", 81 /* xt_iclass_wsr.lcount */, | |
7445 | 0, | |
7446 | Opcode_wsr_lcount_encode_fns, 0, 0 }, | |
7447 | { "xsr.lcount", 82 /* xt_iclass_xsr.lcount */, | |
7448 | 0, | |
7449 | Opcode_xsr_lcount_encode_fns, 0, 0 }, | |
7450 | { "rsr.lbeg", 83 /* xt_iclass_rsr.lbeg */, | |
7451 | 0, | |
7452 | Opcode_rsr_lbeg_encode_fns, 0, 0 }, | |
7453 | { "wsr.lbeg", 84 /* xt_iclass_wsr.lbeg */, | |
7454 | 0, | |
7455 | Opcode_wsr_lbeg_encode_fns, 0, 0 }, | |
7456 | { "xsr.lbeg", 85 /* xt_iclass_xsr.lbeg */, | |
7457 | 0, | |
7458 | Opcode_xsr_lbeg_encode_fns, 0, 0 }, | |
7459 | { "rsr.sar", 86 /* xt_iclass_rsr.sar */, | |
7460 | 0, | |
7461 | Opcode_rsr_sar_encode_fns, 0, 0 }, | |
7462 | { "wsr.sar", 87 /* xt_iclass_wsr.sar */, | |
7463 | 0, | |
7464 | Opcode_wsr_sar_encode_fns, 0, 0 }, | |
7465 | { "xsr.sar", 88 /* xt_iclass_xsr.sar */, | |
7466 | 0, | |
7467 | Opcode_xsr_sar_encode_fns, 0, 0 }, | |
7468 | { "rsr.litbase", 89 /* xt_iclass_rsr.litbase */, | |
7469 | 0, | |
7470 | Opcode_rsr_litbase_encode_fns, 0, 0 }, | |
7471 | { "wsr.litbase", 90 /* xt_iclass_wsr.litbase */, | |
7472 | 0, | |
7473 | Opcode_wsr_litbase_encode_fns, 0, 0 }, | |
7474 | { "xsr.litbase", 91 /* xt_iclass_xsr.litbase */, | |
7475 | 0, | |
7476 | Opcode_xsr_litbase_encode_fns, 0, 0 }, | |
7477 | { "rsr.176", 92 /* xt_iclass_rsr.176 */, | |
7478 | 0, | |
7479 | Opcode_rsr_176_encode_fns, 0, 0 }, | |
7480 | { "rsr.208", 93 /* xt_iclass_rsr.208 */, | |
7481 | 0, | |
7482 | Opcode_rsr_208_encode_fns, 0, 0 }, | |
7483 | { "rsr.ps", 94 /* xt_iclass_rsr.ps */, | |
7484 | 0, | |
7485 | Opcode_rsr_ps_encode_fns, 0, 0 }, | |
7486 | { "wsr.ps", 95 /* xt_iclass_wsr.ps */, | |
7487 | 0, | |
7488 | Opcode_wsr_ps_encode_fns, 0, 0 }, | |
7489 | { "xsr.ps", 96 /* xt_iclass_xsr.ps */, | |
7490 | 0, | |
7491 | Opcode_xsr_ps_encode_fns, 0, 0 }, | |
7492 | { "rsr.epc1", 97 /* xt_iclass_rsr.epc1 */, | |
7493 | 0, | |
7494 | Opcode_rsr_epc1_encode_fns, 0, 0 }, | |
7495 | { "wsr.epc1", 98 /* xt_iclass_wsr.epc1 */, | |
7496 | 0, | |
7497 | Opcode_wsr_epc1_encode_fns, 0, 0 }, | |
7498 | { "xsr.epc1", 99 /* xt_iclass_xsr.epc1 */, | |
7499 | 0, | |
7500 | Opcode_xsr_epc1_encode_fns, 0, 0 }, | |
7501 | { "rsr.excsave1", 100 /* xt_iclass_rsr.excsave1 */, | |
7502 | 0, | |
7503 | Opcode_rsr_excsave1_encode_fns, 0, 0 }, | |
7504 | { "wsr.excsave1", 101 /* xt_iclass_wsr.excsave1 */, | |
7505 | 0, | |
7506 | Opcode_wsr_excsave1_encode_fns, 0, 0 }, | |
7507 | { "xsr.excsave1", 102 /* xt_iclass_xsr.excsave1 */, | |
7508 | 0, | |
7509 | Opcode_xsr_excsave1_encode_fns, 0, 0 }, | |
7510 | { "rsr.epc2", 103 /* xt_iclass_rsr.epc2 */, | |
7511 | 0, | |
7512 | Opcode_rsr_epc2_encode_fns, 0, 0 }, | |
7513 | { "wsr.epc2", 104 /* xt_iclass_wsr.epc2 */, | |
7514 | 0, | |
7515 | Opcode_wsr_epc2_encode_fns, 0, 0 }, | |
7516 | { "xsr.epc2", 105 /* xt_iclass_xsr.epc2 */, | |
7517 | 0, | |
7518 | Opcode_xsr_epc2_encode_fns, 0, 0 }, | |
7519 | { "rsr.excsave2", 106 /* xt_iclass_rsr.excsave2 */, | |
7520 | 0, | |
7521 | Opcode_rsr_excsave2_encode_fns, 0, 0 }, | |
7522 | { "wsr.excsave2", 107 /* xt_iclass_wsr.excsave2 */, | |
7523 | 0, | |
7524 | Opcode_wsr_excsave2_encode_fns, 0, 0 }, | |
7525 | { "xsr.excsave2", 108 /* xt_iclass_xsr.excsave2 */, | |
7526 | 0, | |
7527 | Opcode_xsr_excsave2_encode_fns, 0, 0 }, | |
7528 | { "rsr.epc3", 109 /* xt_iclass_rsr.epc3 */, | |
7529 | 0, | |
7530 | Opcode_rsr_epc3_encode_fns, 0, 0 }, | |
7531 | { "wsr.epc3", 110 /* xt_iclass_wsr.epc3 */, | |
7532 | 0, | |
7533 | Opcode_wsr_epc3_encode_fns, 0, 0 }, | |
7534 | { "xsr.epc3", 111 /* xt_iclass_xsr.epc3 */, | |
7535 | 0, | |
7536 | Opcode_xsr_epc3_encode_fns, 0, 0 }, | |
7537 | { "rsr.excsave3", 112 /* xt_iclass_rsr.excsave3 */, | |
7538 | 0, | |
7539 | Opcode_rsr_excsave3_encode_fns, 0, 0 }, | |
7540 | { "wsr.excsave3", 113 /* xt_iclass_wsr.excsave3 */, | |
7541 | 0, | |
7542 | Opcode_wsr_excsave3_encode_fns, 0, 0 }, | |
7543 | { "xsr.excsave3", 114 /* xt_iclass_xsr.excsave3 */, | |
7544 | 0, | |
7545 | Opcode_xsr_excsave3_encode_fns, 0, 0 }, | |
7546 | { "rsr.epc4", 115 /* xt_iclass_rsr.epc4 */, | |
7547 | 0, | |
7548 | Opcode_rsr_epc4_encode_fns, 0, 0 }, | |
7549 | { "wsr.epc4", 116 /* xt_iclass_wsr.epc4 */, | |
7550 | 0, | |
7551 | Opcode_wsr_epc4_encode_fns, 0, 0 }, | |
7552 | { "xsr.epc4", 117 /* xt_iclass_xsr.epc4 */, | |
7553 | 0, | |
7554 | Opcode_xsr_epc4_encode_fns, 0, 0 }, | |
7555 | { "rsr.excsave4", 118 /* xt_iclass_rsr.excsave4 */, | |
7556 | 0, | |
7557 | Opcode_rsr_excsave4_encode_fns, 0, 0 }, | |
7558 | { "wsr.excsave4", 119 /* xt_iclass_wsr.excsave4 */, | |
7559 | 0, | |
7560 | Opcode_wsr_excsave4_encode_fns, 0, 0 }, | |
7561 | { "xsr.excsave4", 120 /* xt_iclass_xsr.excsave4 */, | |
7562 | 0, | |
7563 | Opcode_xsr_excsave4_encode_fns, 0, 0 }, | |
7564 | { "rsr.eps2", 121 /* xt_iclass_rsr.eps2 */, | |
7565 | 0, | |
7566 | Opcode_rsr_eps2_encode_fns, 0, 0 }, | |
7567 | { "wsr.eps2", 122 /* xt_iclass_wsr.eps2 */, | |
7568 | 0, | |
7569 | Opcode_wsr_eps2_encode_fns, 0, 0 }, | |
7570 | { "xsr.eps2", 123 /* xt_iclass_xsr.eps2 */, | |
7571 | 0, | |
7572 | Opcode_xsr_eps2_encode_fns, 0, 0 }, | |
7573 | { "rsr.eps3", 124 /* xt_iclass_rsr.eps3 */, | |
7574 | 0, | |
7575 | Opcode_rsr_eps3_encode_fns, 0, 0 }, | |
7576 | { "wsr.eps3", 125 /* xt_iclass_wsr.eps3 */, | |
7577 | 0, | |
7578 | Opcode_wsr_eps3_encode_fns, 0, 0 }, | |
7579 | { "xsr.eps3", 126 /* xt_iclass_xsr.eps3 */, | |
7580 | 0, | |
7581 | Opcode_xsr_eps3_encode_fns, 0, 0 }, | |
7582 | { "rsr.eps4", 127 /* xt_iclass_rsr.eps4 */, | |
7583 | 0, | |
7584 | Opcode_rsr_eps4_encode_fns, 0, 0 }, | |
7585 | { "wsr.eps4", 128 /* xt_iclass_wsr.eps4 */, | |
7586 | 0, | |
7587 | Opcode_wsr_eps4_encode_fns, 0, 0 }, | |
7588 | { "xsr.eps4", 129 /* xt_iclass_xsr.eps4 */, | |
7589 | 0, | |
7590 | Opcode_xsr_eps4_encode_fns, 0, 0 }, | |
7591 | { "rsr.excvaddr", 130 /* xt_iclass_rsr.excvaddr */, | |
7592 | 0, | |
7593 | Opcode_rsr_excvaddr_encode_fns, 0, 0 }, | |
7594 | { "wsr.excvaddr", 131 /* xt_iclass_wsr.excvaddr */, | |
7595 | 0, | |
7596 | Opcode_wsr_excvaddr_encode_fns, 0, 0 }, | |
7597 | { "xsr.excvaddr", 132 /* xt_iclass_xsr.excvaddr */, | |
7598 | 0, | |
7599 | Opcode_xsr_excvaddr_encode_fns, 0, 0 }, | |
7600 | { "rsr.depc", 133 /* xt_iclass_rsr.depc */, | |
7601 | 0, | |
7602 | Opcode_rsr_depc_encode_fns, 0, 0 }, | |
7603 | { "wsr.depc", 134 /* xt_iclass_wsr.depc */, | |
7604 | 0, | |
7605 | Opcode_wsr_depc_encode_fns, 0, 0 }, | |
7606 | { "xsr.depc", 135 /* xt_iclass_xsr.depc */, | |
7607 | 0, | |
7608 | Opcode_xsr_depc_encode_fns, 0, 0 }, | |
7609 | { "rsr.exccause", 136 /* xt_iclass_rsr.exccause */, | |
7610 | 0, | |
7611 | Opcode_rsr_exccause_encode_fns, 0, 0 }, | |
7612 | { "wsr.exccause", 137 /* xt_iclass_wsr.exccause */, | |
7613 | 0, | |
7614 | Opcode_wsr_exccause_encode_fns, 0, 0 }, | |
7615 | { "xsr.exccause", 138 /* xt_iclass_xsr.exccause */, | |
7616 | 0, | |
7617 | Opcode_xsr_exccause_encode_fns, 0, 0 }, | |
7618 | { "rsr.misc0", 139 /* xt_iclass_rsr.misc0 */, | |
7619 | 0, | |
7620 | Opcode_rsr_misc0_encode_fns, 0, 0 }, | |
7621 | { "wsr.misc0", 140 /* xt_iclass_wsr.misc0 */, | |
7622 | 0, | |
7623 | Opcode_wsr_misc0_encode_fns, 0, 0 }, | |
7624 | { "xsr.misc0", 141 /* xt_iclass_xsr.misc0 */, | |
7625 | 0, | |
7626 | Opcode_xsr_misc0_encode_fns, 0, 0 }, | |
7627 | { "rsr.misc1", 142 /* xt_iclass_rsr.misc1 */, | |
7628 | 0, | |
7629 | Opcode_rsr_misc1_encode_fns, 0, 0 }, | |
7630 | { "wsr.misc1", 143 /* xt_iclass_wsr.misc1 */, | |
7631 | 0, | |
7632 | Opcode_wsr_misc1_encode_fns, 0, 0 }, | |
7633 | { "xsr.misc1", 144 /* xt_iclass_xsr.misc1 */, | |
7634 | 0, | |
7635 | Opcode_xsr_misc1_encode_fns, 0, 0 }, | |
7636 | { "rsr.prid", 145 /* xt_iclass_rsr.prid */, | |
7637 | 0, | |
7638 | Opcode_rsr_prid_encode_fns, 0, 0 }, | |
7639 | { "rfi", 146 /* xt_iclass_rfi */, | |
7640 | XTENSA_OPCODE_IS_JUMP, | |
7641 | Opcode_rfi_encode_fns, 0, 0 }, | |
7642 | { "waiti", 147 /* xt_iclass_wait */, | |
7643 | 0, | |
7644 | Opcode_waiti_encode_fns, 0, 0 }, | |
7645 | { "rsr.interrupt", 148 /* xt_iclass_rsr.interrupt */, | |
7646 | 0, | |
7647 | Opcode_rsr_interrupt_encode_fns, 0, 0 }, | |
7648 | { "wsr.intset", 149 /* xt_iclass_wsr.intset */, | |
7649 | 0, | |
7650 | Opcode_wsr_intset_encode_fns, 0, 0 }, | |
7651 | { "wsr.intclear", 150 /* xt_iclass_wsr.intclear */, | |
7652 | 0, | |
7653 | Opcode_wsr_intclear_encode_fns, 0, 0 }, | |
7654 | { "rsr.intenable", 151 /* xt_iclass_rsr.intenable */, | |
7655 | 0, | |
7656 | Opcode_rsr_intenable_encode_fns, 0, 0 }, | |
7657 | { "wsr.intenable", 152 /* xt_iclass_wsr.intenable */, | |
7658 | 0, | |
7659 | Opcode_wsr_intenable_encode_fns, 0, 0 }, | |
7660 | { "xsr.intenable", 153 /* xt_iclass_xsr.intenable */, | |
7661 | 0, | |
7662 | Opcode_xsr_intenable_encode_fns, 0, 0 }, | |
7663 | { "break", 154 /* xt_iclass_break */, | |
7664 | 0, | |
7665 | Opcode_break_encode_fns, 0, 0 }, | |
7666 | { "break.n", 155 /* xt_iclass_break.n */, | |
7667 | 0, | |
7668 | Opcode_break_n_encode_fns, 0, 0 }, | |
7669 | { "rsr.dbreaka0", 156 /* xt_iclass_rsr.dbreaka0 */, | |
7670 | 0, | |
7671 | Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, | |
7672 | { "wsr.dbreaka0", 157 /* xt_iclass_wsr.dbreaka0 */, | |
7673 | 0, | |
7674 | Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, | |
7675 | { "xsr.dbreaka0", 158 /* xt_iclass_xsr.dbreaka0 */, | |
7676 | 0, | |
7677 | Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, | |
7678 | { "rsr.dbreakc0", 159 /* xt_iclass_rsr.dbreakc0 */, | |
7679 | 0, | |
7680 | Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, | |
7681 | { "wsr.dbreakc0", 160 /* xt_iclass_wsr.dbreakc0 */, | |
7682 | 0, | |
7683 | Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, | |
7684 | { "xsr.dbreakc0", 161 /* xt_iclass_xsr.dbreakc0 */, | |
7685 | 0, | |
7686 | Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, | |
7687 | { "rsr.dbreaka1", 162 /* xt_iclass_rsr.dbreaka1 */, | |
7688 | 0, | |
7689 | Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, | |
7690 | { "wsr.dbreaka1", 163 /* xt_iclass_wsr.dbreaka1 */, | |
7691 | 0, | |
7692 | Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, | |
7693 | { "xsr.dbreaka1", 164 /* xt_iclass_xsr.dbreaka1 */, | |
7694 | 0, | |
7695 | Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, | |
7696 | { "rsr.dbreakc1", 165 /* xt_iclass_rsr.dbreakc1 */, | |
7697 | 0, | |
7698 | Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, | |
7699 | { "wsr.dbreakc1", 166 /* xt_iclass_wsr.dbreakc1 */, | |
7700 | 0, | |
7701 | Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, | |
7702 | { "xsr.dbreakc1", 167 /* xt_iclass_xsr.dbreakc1 */, | |
7703 | 0, | |
7704 | Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, | |
7705 | { "rsr.ibreaka0", 168 /* xt_iclass_rsr.ibreaka0 */, | |
7706 | 0, | |
7707 | Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, | |
7708 | { "wsr.ibreaka0", 169 /* xt_iclass_wsr.ibreaka0 */, | |
7709 | 0, | |
7710 | Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, | |
7711 | { "xsr.ibreaka0", 170 /* xt_iclass_xsr.ibreaka0 */, | |
7712 | 0, | |
7713 | Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, | |
7714 | { "rsr.ibreaka1", 171 /* xt_iclass_rsr.ibreaka1 */, | |
7715 | 0, | |
7716 | Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, | |
7717 | { "wsr.ibreaka1", 172 /* xt_iclass_wsr.ibreaka1 */, | |
7718 | 0, | |
7719 | Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, | |
7720 | { "xsr.ibreaka1", 173 /* xt_iclass_xsr.ibreaka1 */, | |
7721 | 0, | |
7722 | Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, | |
7723 | { "rsr.ibreakenable", 174 /* xt_iclass_rsr.ibreakenable */, | |
7724 | 0, | |
7725 | Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, | |
7726 | { "wsr.ibreakenable", 175 /* xt_iclass_wsr.ibreakenable */, | |
7727 | 0, | |
7728 | Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, | |
7729 | { "xsr.ibreakenable", 176 /* xt_iclass_xsr.ibreakenable */, | |
7730 | 0, | |
7731 | Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, | |
7732 | { "rsr.debugcause", 177 /* xt_iclass_rsr.debugcause */, | |
7733 | 0, | |
7734 | Opcode_rsr_debugcause_encode_fns, 0, 0 }, | |
7735 | { "wsr.debugcause", 178 /* xt_iclass_wsr.debugcause */, | |
7736 | 0, | |
7737 | Opcode_wsr_debugcause_encode_fns, 0, 0 }, | |
7738 | { "xsr.debugcause", 179 /* xt_iclass_xsr.debugcause */, | |
7739 | 0, | |
7740 | Opcode_xsr_debugcause_encode_fns, 0, 0 }, | |
7741 | { "rsr.icount", 180 /* xt_iclass_rsr.icount */, | |
7742 | 0, | |
7743 | Opcode_rsr_icount_encode_fns, 0, 0 }, | |
7744 | { "wsr.icount", 181 /* xt_iclass_wsr.icount */, | |
7745 | 0, | |
7746 | Opcode_wsr_icount_encode_fns, 0, 0 }, | |
7747 | { "xsr.icount", 182 /* xt_iclass_xsr.icount */, | |
7748 | 0, | |
7749 | Opcode_xsr_icount_encode_fns, 0, 0 }, | |
7750 | { "rsr.icountlevel", 183 /* xt_iclass_rsr.icountlevel */, | |
7751 | 0, | |
7752 | Opcode_rsr_icountlevel_encode_fns, 0, 0 }, | |
7753 | { "wsr.icountlevel", 184 /* xt_iclass_wsr.icountlevel */, | |
7754 | 0, | |
7755 | Opcode_wsr_icountlevel_encode_fns, 0, 0 }, | |
7756 | { "xsr.icountlevel", 185 /* xt_iclass_xsr.icountlevel */, | |
7757 | 0, | |
7758 | Opcode_xsr_icountlevel_encode_fns, 0, 0 }, | |
7759 | { "rsr.ddr", 186 /* xt_iclass_rsr.ddr */, | |
7760 | 0, | |
7761 | Opcode_rsr_ddr_encode_fns, 0, 0 }, | |
7762 | { "wsr.ddr", 187 /* xt_iclass_wsr.ddr */, | |
7763 | 0, | |
7764 | Opcode_wsr_ddr_encode_fns, 0, 0 }, | |
7765 | { "xsr.ddr", 188 /* xt_iclass_xsr.ddr */, | |
7766 | 0, | |
7767 | Opcode_xsr_ddr_encode_fns, 0, 0 }, | |
7768 | { "rfdo", 189 /* xt_iclass_rfdo */, | |
7769 | XTENSA_OPCODE_IS_JUMP, | |
7770 | Opcode_rfdo_encode_fns, 0, 0 }, | |
7771 | { "rfdd", 190 /* xt_iclass_rfdd */, | |
7772 | XTENSA_OPCODE_IS_JUMP, | |
7773 | Opcode_rfdd_encode_fns, 0, 0 }, | |
7774 | { "rsr.ccount", 191 /* xt_iclass_rsr.ccount */, | |
7775 | 0, | |
7776 | Opcode_rsr_ccount_encode_fns, 0, 0 }, | |
7777 | { "wsr.ccount", 192 /* xt_iclass_wsr.ccount */, | |
7778 | 0, | |
7779 | Opcode_wsr_ccount_encode_fns, 0, 0 }, | |
7780 | { "xsr.ccount", 193 /* xt_iclass_xsr.ccount */, | |
7781 | 0, | |
7782 | Opcode_xsr_ccount_encode_fns, 0, 0 }, | |
7783 | { "rsr.ccompare0", 194 /* xt_iclass_rsr.ccompare0 */, | |
7784 | 0, | |
7785 | Opcode_rsr_ccompare0_encode_fns, 0, 0 }, | |
7786 | { "wsr.ccompare0", 195 /* xt_iclass_wsr.ccompare0 */, | |
7787 | 0, | |
7788 | Opcode_wsr_ccompare0_encode_fns, 0, 0 }, | |
7789 | { "xsr.ccompare0", 196 /* xt_iclass_xsr.ccompare0 */, | |
7790 | 0, | |
7791 | Opcode_xsr_ccompare0_encode_fns, 0, 0 }, | |
7792 | { "rsr.ccompare1", 197 /* xt_iclass_rsr.ccompare1 */, | |
7793 | 0, | |
7794 | Opcode_rsr_ccompare1_encode_fns, 0, 0 }, | |
7795 | { "wsr.ccompare1", 198 /* xt_iclass_wsr.ccompare1 */, | |
7796 | 0, | |
7797 | Opcode_wsr_ccompare1_encode_fns, 0, 0 }, | |
7798 | { "xsr.ccompare1", 199 /* xt_iclass_xsr.ccompare1 */, | |
7799 | 0, | |
7800 | Opcode_xsr_ccompare1_encode_fns, 0, 0 }, | |
7801 | { "rsr.ccompare2", 200 /* xt_iclass_rsr.ccompare2 */, | |
7802 | 0, | |
7803 | Opcode_rsr_ccompare2_encode_fns, 0, 0 }, | |
7804 | { "wsr.ccompare2", 201 /* xt_iclass_wsr.ccompare2 */, | |
7805 | 0, | |
7806 | Opcode_wsr_ccompare2_encode_fns, 0, 0 }, | |
7807 | { "xsr.ccompare2", 202 /* xt_iclass_xsr.ccompare2 */, | |
7808 | 0, | |
7809 | Opcode_xsr_ccompare2_encode_fns, 0, 0 }, | |
7810 | { "ipf", 203 /* xt_iclass_icache */, | |
7811 | 0, | |
7812 | Opcode_ipf_encode_fns, 0, 0 }, | |
7813 | { "ihi", 203 /* xt_iclass_icache */, | |
7814 | 0, | |
7815 | Opcode_ihi_encode_fns, 0, 0 }, | |
7816 | { "iii", 204 /* xt_iclass_icache_inv */, | |
7817 | 0, | |
7818 | Opcode_iii_encode_fns, 0, 0 }, | |
7819 | { "lict", 205 /* xt_iclass_licx */, | |
7820 | 0, | |
7821 | Opcode_lict_encode_fns, 0, 0 }, | |
7822 | { "licw", 205 /* xt_iclass_licx */, | |
7823 | 0, | |
7824 | Opcode_licw_encode_fns, 0, 0 }, | |
7825 | { "sict", 206 /* xt_iclass_sicx */, | |
7826 | 0, | |
7827 | Opcode_sict_encode_fns, 0, 0 }, | |
7828 | { "sicw", 206 /* xt_iclass_sicx */, | |
7829 | 0, | |
7830 | Opcode_sicw_encode_fns, 0, 0 }, | |
7831 | { "dhwb", 207 /* xt_iclass_dcache */, | |
7832 | 0, | |
7833 | Opcode_dhwb_encode_fns, 0, 0 }, | |
7834 | { "dhwbi", 207 /* xt_iclass_dcache */, | |
7835 | 0, | |
7836 | Opcode_dhwbi_encode_fns, 0, 0 }, | |
7837 | { "diwb", 208 /* xt_iclass_dcache_ind */, | |
7838 | 0, | |
7839 | Opcode_diwb_encode_fns, 0, 0 }, | |
7840 | { "diwbi", 208 /* xt_iclass_dcache_ind */, | |
7841 | 0, | |
7842 | Opcode_diwbi_encode_fns, 0, 0 }, | |
7843 | { "dhi", 209 /* xt_iclass_dcache_inv */, | |
7844 | 0, | |
7845 | Opcode_dhi_encode_fns, 0, 0 }, | |
7846 | { "dii", 209 /* xt_iclass_dcache_inv */, | |
7847 | 0, | |
7848 | Opcode_dii_encode_fns, 0, 0 }, | |
7849 | { "dpfr", 210 /* xt_iclass_dpf */, | |
7850 | 0, | |
7851 | Opcode_dpfr_encode_fns, 0, 0 }, | |
7852 | { "dpfw", 210 /* xt_iclass_dpf */, | |
7853 | 0, | |
7854 | Opcode_dpfw_encode_fns, 0, 0 }, | |
7855 | { "dpfro", 210 /* xt_iclass_dpf */, | |
7856 | 0, | |
7857 | Opcode_dpfro_encode_fns, 0, 0 }, | |
7858 | { "dpfwo", 210 /* xt_iclass_dpf */, | |
7859 | 0, | |
7860 | Opcode_dpfwo_encode_fns, 0, 0 }, | |
7861 | { "sdct", 211 /* xt_iclass_sdct */, | |
7862 | 0, | |
7863 | Opcode_sdct_encode_fns, 0, 0 }, | |
7864 | { "ldct", 212 /* xt_iclass_ldct */, | |
7865 | 0, | |
7866 | Opcode_ldct_encode_fns, 0, 0 }, | |
7867 | { "idtlb", 213 /* xt_iclass_idtlb */, | |
7868 | 0, | |
7869 | Opcode_idtlb_encode_fns, 0, 0 }, | |
7870 | { "pdtlb", 214 /* xt_iclass_rdtlb */, | |
7871 | 0, | |
7872 | Opcode_pdtlb_encode_fns, 0, 0 }, | |
7873 | { "rdtlb0", 214 /* xt_iclass_rdtlb */, | |
7874 | 0, | |
7875 | Opcode_rdtlb0_encode_fns, 0, 0 }, | |
7876 | { "rdtlb1", 214 /* xt_iclass_rdtlb */, | |
7877 | 0, | |
7878 | Opcode_rdtlb1_encode_fns, 0, 0 }, | |
7879 | { "wdtlb", 215 /* xt_iclass_wdtlb */, | |
7880 | 0, | |
7881 | Opcode_wdtlb_encode_fns, 0, 0 }, | |
7882 | { "iitlb", 216 /* xt_iclass_iitlb */, | |
7883 | 0, | |
7884 | Opcode_iitlb_encode_fns, 0, 0 }, | |
7885 | { "pitlb", 217 /* xt_iclass_ritlb */, | |
7886 | 0, | |
7887 | Opcode_pitlb_encode_fns, 0, 0 }, | |
7888 | { "ritlb0", 217 /* xt_iclass_ritlb */, | |
7889 | 0, | |
7890 | Opcode_ritlb0_encode_fns, 0, 0 }, | |
7891 | { "ritlb1", 217 /* xt_iclass_ritlb */, | |
7892 | 0, | |
7893 | Opcode_ritlb1_encode_fns, 0, 0 }, | |
7894 | { "witlb", 218 /* xt_iclass_witlb */, | |
7895 | 0, | |
7896 | Opcode_witlb_encode_fns, 0, 0 }, | |
7897 | { "nsa", 219 /* xt_iclass_nsa */, | |
7898 | 0, | |
7899 | Opcode_nsa_encode_fns, 0, 0 }, | |
7900 | { "nsau", 219 /* xt_iclass_nsa */, | |
7901 | 0, | |
7902 | Opcode_nsau_encode_fns, 0, 0 } | |
7903 | }; | |
7904 | ||
7905 | \f | |
7906 | /* Slot-specific opcode decode functions. */ | |
7907 | ||
7908 | static int | |
7909 | Slot_inst_decode (const xtensa_insnbuf insn) | |
7910 | { | |
7911 | switch (Field_op0_Slot_inst_get (insn)) | |
7912 | { | |
7913 | case 0: | |
7914 | switch (Field_op1_Slot_inst_get (insn)) | |
7915 | { | |
7916 | case 0: | |
7917 | switch (Field_op2_Slot_inst_get (insn)) | |
7918 | { | |
7919 | case 0: | |
7920 | switch (Field_r_Slot_inst_get (insn)) | |
7921 | { | |
7922 | case 0: | |
7923 | switch (Field_m_Slot_inst_get (insn)) | |
7924 | { | |
7925 | case 0: | |
7926 | return 77; /* ill */ | |
7927 | case 2: | |
7928 | switch (Field_n_Slot_inst_get (insn)) | |
7929 | { | |
7930 | case 0: | |
7931 | return 96; /* ret */ | |
7932 | case 1: | |
7933 | return 14; /* retw */ | |
7934 | case 2: | |
7935 | return 79; /* jx */ | |
7936 | } | |
7937 | break; | |
7938 | case 3: | |
7939 | switch (Field_n_Slot_inst_get (insn)) | |
7940 | { | |
7941 | case 0: | |
7942 | return 75; /* callx0 */ | |
7943 | case 1: | |
7944 | return 10; /* callx4 */ | |
7945 | case 2: | |
7946 | return 9; /* callx8 */ | |
7947 | case 3: | |
7948 | return 8; /* callx12 */ | |
7949 | } | |
7950 | break; | |
7951 | } | |
7952 | break; | |
7953 | case 1: | |
7954 | return 12; /* movsp */ | |
7955 | case 2: | |
7956 | if (Field_s_Slot_inst_get (insn) == 0) | |
7957 | { | |
7958 | switch (Field_t_Slot_inst_get (insn)) | |
7959 | { | |
7960 | case 0: | |
7961 | return 114; /* isync */ | |
7962 | case 1: | |
7963 | return 115; /* rsync */ | |
7964 | case 2: | |
7965 | return 116; /* esync */ | |
7966 | case 3: | |
7967 | return 117; /* dsync */ | |
7968 | case 8: | |
7969 | return 0; /* excw */ | |
7970 | case 12: | |
7971 | return 112; /* memw */ | |
7972 | case 13: | |
7973 | return 113; /* extw */ | |
7974 | case 15: | |
7975 | return 95; /* nop */ | |
7976 | } | |
7977 | } | |
7978 | break; | |
7979 | case 3: | |
7980 | switch (Field_t_Slot_inst_get (insn)) | |
7981 | { | |
7982 | case 0: | |
7983 | switch (Field_s_Slot_inst_get (insn)) | |
7984 | { | |
7985 | case 0: | |
7986 | return 1; /* rfe */ | |
7987 | case 2: | |
7988 | return 2; /* rfde */ | |
7989 | case 4: | |
7990 | return 16; /* rfwo */ | |
7991 | case 5: | |
7992 | return 17; /* rfwu */ | |
7993 | } | |
7994 | break; | |
7995 | case 1: | |
7996 | return 188; /* rfi */ | |
7997 | } | |
7998 | break; | |
7999 | case 4: | |
8000 | return 196; /* break */ | |
8001 | case 5: | |
8002 | switch (Field_s_Slot_inst_get (insn)) | |
8003 | { | |
8004 | case 0: | |
8005 | if (Field_t_Slot_inst_get (insn) == 0) | |
8006 | return 3; /* syscall */ | |
8007 | break; | |
8008 | case 1: | |
8009 | if (Field_t_Slot_inst_get (insn) == 0) | |
8010 | return 4; /* simcall */ | |
8011 | break; | |
8012 | } | |
8013 | break; | |
8014 | case 6: | |
8015 | return 118; /* rsil */ | |
8016 | case 7: | |
8017 | if (Field_t_Slot_inst_get (insn) == 0) | |
8018 | return 189; /* waiti */ | |
8019 | break; | |
8020 | } | |
8021 | break; | |
8022 | case 1: | |
8023 | return 47; /* and */ | |
8024 | case 2: | |
8025 | return 48; /* or */ | |
8026 | case 3: | |
8027 | return 49; /* xor */ | |
8028 | case 4: | |
8029 | switch (Field_r_Slot_inst_get (insn)) | |
8030 | { | |
8031 | case 0: | |
8032 | if (Field_t_Slot_inst_get (insn) == 0) | |
8033 | return 100; /* ssr */ | |
8034 | break; | |
8035 | case 1: | |
8036 | if (Field_t_Slot_inst_get (insn) == 0) | |
8037 | return 101; /* ssl */ | |
8038 | break; | |
8039 | case 2: | |
8040 | if (Field_t_Slot_inst_get (insn) == 0) | |
8041 | return 102; /* ssa8l */ | |
8042 | break; | |
8043 | case 3: | |
8044 | if (Field_t_Slot_inst_get (insn) == 0) | |
8045 | return 103; /* ssa8b */ | |
8046 | break; | |
8047 | case 4: | |
8048 | if (Field_thi3_Slot_inst_get (insn) == 0) | |
8049 | return 104; /* ssai */ | |
8050 | break; | |
8051 | case 8: | |
8052 | if (Field_s_Slot_inst_get (insn) == 0) | |
8053 | return 13; /* rotw */ | |
8054 | break; | |
8055 | case 14: | |
8056 | return 274; /* nsa */ | |
8057 | case 15: | |
8058 | return 275; /* nsau */ | |
8059 | } | |
8060 | break; | |
8061 | case 5: | |
8062 | switch (Field_r_Slot_inst_get (insn)) | |
8063 | { | |
8064 | case 3: | |
8065 | return 271; /* ritlb0 */ | |
8066 | case 4: | |
8067 | return 269; /* iitlb */ | |
8068 | case 5: | |
8069 | return 270; /* pitlb */ | |
8070 | case 6: | |
8071 | return 273; /* witlb */ | |
8072 | case 7: | |
8073 | return 272; /* ritlb1 */ | |
8074 | case 11: | |
8075 | return 266; /* rdtlb0 */ | |
8076 | case 12: | |
8077 | return 264; /* idtlb */ | |
8078 | case 13: | |
8079 | return 265; /* pdtlb */ | |
8080 | case 14: | |
8081 | return 268; /* wdtlb */ | |
8082 | case 15: | |
8083 | return 267; /* rdtlb1 */ | |
8084 | } | |
8085 | break; | |
8086 | case 6: | |
8087 | switch (Field_s_Slot_inst_get (insn)) | |
8088 | { | |
8089 | case 0: | |
8090 | return 93; /* neg */ | |
8091 | case 1: | |
8092 | return 94; /* abs */ | |
8093 | } | |
8094 | break; | |
8095 | case 8: | |
8096 | return 39; /* add */ | |
8097 | case 9: | |
8098 | return 41; /* addx2 */ | |
8099 | case 10: | |
8100 | return 42; /* addx4 */ | |
8101 | case 11: | |
8102 | return 43; /* addx8 */ | |
8103 | case 12: | |
8104 | return 40; /* sub */ | |
8105 | case 13: | |
8106 | return 44; /* subx2 */ | |
8107 | case 14: | |
8108 | return 45; /* subx4 */ | |
8109 | case 15: | |
8110 | return 46; /* subx8 */ | |
8111 | } | |
8112 | break; | |
8113 | case 1: | |
8114 | switch (Field_op2_Slot_inst_get (insn)) | |
8115 | { | |
8116 | case 0: | |
8117 | case 1: | |
8118 | return 109; /* slli */ | |
8119 | case 2: | |
8120 | case 3: | |
8121 | return 110; /* srai */ | |
8122 | case 4: | |
8123 | return 111; /* srli */ | |
8124 | case 6: | |
8125 | switch (Field_sr_Slot_inst_get (insn)) | |
8126 | { | |
8127 | case 0: | |
8128 | return 127; /* xsr.lbeg */ | |
8129 | case 1: | |
8130 | return 121; /* xsr.lend */ | |
8131 | case 2: | |
8132 | return 124; /* xsr.lcount */ | |
8133 | case 3: | |
8134 | return 130; /* xsr.sar */ | |
8135 | case 5: | |
8136 | return 133; /* xsr.litbase */ | |
8137 | case 72: | |
8138 | return 22; /* xsr.windowbase */ | |
8139 | case 73: | |
8140 | return 25; /* xsr.windowstart */ | |
8141 | case 96: | |
8142 | return 218; /* xsr.ibreakenable */ | |
8143 | case 104: | |
8144 | return 230; /* xsr.ddr */ | |
8145 | case 128: | |
8146 | return 212; /* xsr.ibreaka0 */ | |
8147 | case 129: | |
8148 | return 215; /* xsr.ibreaka1 */ | |
8149 | case 144: | |
8150 | return 200; /* xsr.dbreaka0 */ | |
8151 | case 145: | |
8152 | return 206; /* xsr.dbreaka1 */ | |
8153 | case 160: | |
8154 | return 203; /* xsr.dbreakc0 */ | |
8155 | case 161: | |
8156 | return 209; /* xsr.dbreakc1 */ | |
8157 | case 177: | |
8158 | return 141; /* xsr.epc1 */ | |
8159 | case 178: | |
8160 | return 147; /* xsr.epc2 */ | |
8161 | case 179: | |
8162 | return 153; /* xsr.epc3 */ | |
8163 | case 180: | |
8164 | return 159; /* xsr.epc4 */ | |
8165 | case 192: | |
8166 | return 177; /* xsr.depc */ | |
8167 | case 194: | |
8168 | return 165; /* xsr.eps2 */ | |
8169 | case 195: | |
8170 | return 168; /* xsr.eps3 */ | |
8171 | case 196: | |
8172 | return 171; /* xsr.eps4 */ | |
8173 | case 209: | |
8174 | return 144; /* xsr.excsave1 */ | |
8175 | case 210: | |
8176 | return 150; /* xsr.excsave2 */ | |
8177 | case 211: | |
8178 | return 156; /* xsr.excsave3 */ | |
8179 | case 212: | |
8180 | return 162; /* xsr.excsave4 */ | |
8181 | case 228: | |
8182 | return 195; /* xsr.intenable */ | |
8183 | case 230: | |
8184 | return 138; /* xsr.ps */ | |
8185 | case 232: | |
8186 | return 180; /* xsr.exccause */ | |
8187 | case 233: | |
8188 | return 221; /* xsr.debugcause */ | |
8189 | case 234: | |
8190 | return 235; /* xsr.ccount */ | |
8191 | case 236: | |
8192 | return 224; /* xsr.icount */ | |
8193 | case 237: | |
8194 | return 227; /* xsr.icountlevel */ | |
8195 | case 238: | |
8196 | return 174; /* xsr.excvaddr */ | |
8197 | case 240: | |
8198 | return 238; /* xsr.ccompare0 */ | |
8199 | case 241: | |
8200 | return 241; /* xsr.ccompare1 */ | |
8201 | case 242: | |
8202 | return 244; /* xsr.ccompare2 */ | |
8203 | case 244: | |
8204 | return 183; /* xsr.misc0 */ | |
8205 | case 245: | |
8206 | return 186; /* xsr.misc1 */ | |
8207 | } | |
8208 | break; | |
8209 | case 8: | |
8210 | return 106; /* src */ | |
8211 | case 9: | |
8212 | if (Field_s_Slot_inst_get (insn) == 0) | |
8213 | return 107; /* srl */ | |
8214 | break; | |
8215 | case 10: | |
8216 | if (Field_t_Slot_inst_get (insn) == 0) | |
8217 | return 105; /* sll */ | |
8218 | break; | |
8219 | case 11: | |
8220 | if (Field_s_Slot_inst_get (insn) == 0) | |
8221 | return 108; /* sra */ | |
8222 | break; | |
8223 | case 15: | |
8224 | switch (Field_r_Slot_inst_get (insn)) | |
8225 | { | |
8226 | case 0: | |
8227 | return 248; /* lict */ | |
8228 | case 1: | |
8229 | return 250; /* sict */ | |
8230 | case 2: | |
8231 | return 249; /* licw */ | |
8232 | case 3: | |
8233 | return 251; /* sicw */ | |
8234 | case 8: | |
8235 | return 263; /* ldct */ | |
8236 | case 9: | |
8237 | return 262; /* sdct */ | |
8238 | case 14: | |
8239 | if (Field_t_Slot_inst_get (insn) == 0) | |
8240 | return 231; /* rfdo */ | |
8241 | if (Field_t_Slot_inst_get (insn) == 1) | |
8242 | return 232; /* rfdd */ | |
8243 | break; | |
8244 | } | |
8245 | break; | |
8246 | } | |
8247 | break; | |
8248 | case 3: | |
8249 | switch (Field_op2_Slot_inst_get (insn)) | |
8250 | { | |
8251 | case 0: | |
8252 | switch (Field_sr_Slot_inst_get (insn)) | |
8253 | { | |
8254 | case 0: | |
8255 | return 125; /* rsr.lbeg */ | |
8256 | case 1: | |
8257 | return 119; /* rsr.lend */ | |
8258 | case 2: | |
8259 | return 122; /* rsr.lcount */ | |
8260 | case 3: | |
8261 | return 128; /* rsr.sar */ | |
8262 | case 5: | |
8263 | return 131; /* rsr.litbase */ | |
8264 | case 72: | |
8265 | return 20; /* rsr.windowbase */ | |
8266 | case 73: | |
8267 | return 23; /* rsr.windowstart */ | |
8268 | case 96: | |
8269 | return 216; /* rsr.ibreakenable */ | |
8270 | case 104: | |
8271 | return 228; /* rsr.ddr */ | |
8272 | case 128: | |
8273 | return 210; /* rsr.ibreaka0 */ | |
8274 | case 129: | |
8275 | return 213; /* rsr.ibreaka1 */ | |
8276 | case 144: | |
8277 | return 198; /* rsr.dbreaka0 */ | |
8278 | case 145: | |
8279 | return 204; /* rsr.dbreaka1 */ | |
8280 | case 160: | |
8281 | return 201; /* rsr.dbreakc0 */ | |
8282 | case 161: | |
8283 | return 207; /* rsr.dbreakc1 */ | |
8284 | case 176: | |
8285 | return 134; /* rsr.176 */ | |
8286 | case 177: | |
8287 | return 139; /* rsr.epc1 */ | |
8288 | case 178: | |
8289 | return 145; /* rsr.epc2 */ | |
8290 | case 179: | |
8291 | return 151; /* rsr.epc3 */ | |
8292 | case 180: | |
8293 | return 157; /* rsr.epc4 */ | |
8294 | case 192: | |
8295 | return 175; /* rsr.depc */ | |
8296 | case 194: | |
8297 | return 163; /* rsr.eps2 */ | |
8298 | case 195: | |
8299 | return 166; /* rsr.eps3 */ | |
8300 | case 196: | |
8301 | return 169; /* rsr.eps4 */ | |
8302 | case 208: | |
8303 | return 135; /* rsr.208 */ | |
8304 | case 209: | |
8305 | return 142; /* rsr.excsave1 */ | |
8306 | case 210: | |
8307 | return 148; /* rsr.excsave2 */ | |
8308 | case 211: | |
8309 | return 154; /* rsr.excsave3 */ | |
8310 | case 212: | |
8311 | return 160; /* rsr.excsave4 */ | |
8312 | case 226: | |
8313 | return 190; /* rsr.interrupt */ | |
8314 | case 228: | |
8315 | return 193; /* rsr.intenable */ | |
8316 | case 230: | |
8317 | return 136; /* rsr.ps */ | |
8318 | case 232: | |
8319 | return 178; /* rsr.exccause */ | |
8320 | case 233: | |
8321 | return 219; /* rsr.debugcause */ | |
8322 | case 234: | |
8323 | return 233; /* rsr.ccount */ | |
8324 | case 235: | |
8325 | return 187; /* rsr.prid */ | |
8326 | case 236: | |
8327 | return 222; /* rsr.icount */ | |
8328 | case 237: | |
8329 | return 225; /* rsr.icountlevel */ | |
8330 | case 238: | |
8331 | return 172; /* rsr.excvaddr */ | |
8332 | case 240: | |
8333 | return 236; /* rsr.ccompare0 */ | |
8334 | case 241: | |
8335 | return 239; /* rsr.ccompare1 */ | |
8336 | case 242: | |
8337 | return 242; /* rsr.ccompare2 */ | |
8338 | case 244: | |
8339 | return 181; /* rsr.misc0 */ | |
8340 | case 245: | |
8341 | return 184; /* rsr.misc1 */ | |
8342 | } | |
8343 | break; | |
8344 | case 1: | |
8345 | switch (Field_sr_Slot_inst_get (insn)) | |
8346 | { | |
8347 | case 0: | |
8348 | return 126; /* wsr.lbeg */ | |
8349 | case 1: | |
8350 | return 120; /* wsr.lend */ | |
8351 | case 2: | |
8352 | return 123; /* wsr.lcount */ | |
8353 | case 3: | |
8354 | return 129; /* wsr.sar */ | |
8355 | case 5: | |
8356 | return 132; /* wsr.litbase */ | |
8357 | case 72: | |
8358 | return 21; /* wsr.windowbase */ | |
8359 | case 73: | |
8360 | return 24; /* wsr.windowstart */ | |
8361 | case 96: | |
8362 | return 217; /* wsr.ibreakenable */ | |
8363 | case 104: | |
8364 | return 229; /* wsr.ddr */ | |
8365 | case 128: | |
8366 | return 211; /* wsr.ibreaka0 */ | |
8367 | case 129: | |
8368 | return 214; /* wsr.ibreaka1 */ | |
8369 | case 144: | |
8370 | return 199; /* wsr.dbreaka0 */ | |
8371 | case 145: | |
8372 | return 205; /* wsr.dbreaka1 */ | |
8373 | case 160: | |
8374 | return 202; /* wsr.dbreakc0 */ | |
8375 | case 161: | |
8376 | return 208; /* wsr.dbreakc1 */ | |
8377 | case 177: | |
8378 | return 140; /* wsr.epc1 */ | |
8379 | case 178: | |
8380 | return 146; /* wsr.epc2 */ | |
8381 | case 179: | |
8382 | return 152; /* wsr.epc3 */ | |
8383 | case 180: | |
8384 | return 158; /* wsr.epc4 */ | |
8385 | case 192: | |
8386 | return 176; /* wsr.depc */ | |
8387 | case 194: | |
8388 | return 164; /* wsr.eps2 */ | |
8389 | case 195: | |
8390 | return 167; /* wsr.eps3 */ | |
8391 | case 196: | |
8392 | return 170; /* wsr.eps4 */ | |
8393 | case 209: | |
8394 | return 143; /* wsr.excsave1 */ | |
8395 | case 210: | |
8396 | return 149; /* wsr.excsave2 */ | |
8397 | case 211: | |
8398 | return 155; /* wsr.excsave3 */ | |
8399 | case 212: | |
8400 | return 161; /* wsr.excsave4 */ | |
8401 | case 226: | |
8402 | return 191; /* wsr.intset */ | |
8403 | case 227: | |
8404 | return 192; /* wsr.intclear */ | |
8405 | case 228: | |
8406 | return 194; /* wsr.intenable */ | |
8407 | case 230: | |
8408 | return 137; /* wsr.ps */ | |
8409 | case 232: | |
8410 | return 179; /* wsr.exccause */ | |
8411 | case 233: | |
8412 | return 220; /* wsr.debugcause */ | |
8413 | case 234: | |
8414 | return 234; /* wsr.ccount */ | |
8415 | case 236: | |
8416 | return 223; /* wsr.icount */ | |
8417 | case 237: | |
8418 | return 226; /* wsr.icountlevel */ | |
8419 | case 238: | |
8420 | return 173; /* wsr.excvaddr */ | |
8421 | case 240: | |
8422 | return 237; /* wsr.ccompare0 */ | |
8423 | case 241: | |
8424 | return 240; /* wsr.ccompare1 */ | |
8425 | case 242: | |
8426 | return 243; /* wsr.ccompare2 */ | |
8427 | case 244: | |
8428 | return 182; /* wsr.misc0 */ | |
8429 | case 245: | |
8430 | return 185; /* wsr.misc1 */ | |
8431 | } | |
8432 | break; | |
8433 | case 8: | |
8434 | return 89; /* moveqz */ | |
8435 | case 9: | |
8436 | return 90; /* movnez */ | |
8437 | case 10: | |
8438 | return 91; /* movltz */ | |
8439 | case 11: | |
8440 | return 92; /* movgez */ | |
8441 | } | |
8442 | break; | |
8443 | case 4: | |
8444 | case 5: | |
8445 | return 76; /* extui */ | |
8446 | case 9: | |
8447 | switch (Field_op2_Slot_inst_get (insn)) | |
8448 | { | |
8449 | case 0: | |
8450 | return 18; /* l32e */ | |
8451 | case 4: | |
8452 | return 19; /* s32e */ | |
8453 | } | |
8454 | break; | |
8455 | } | |
e0001a05 | 8456 | break; |
43cd72b9 BW |
8457 | case 1: |
8458 | return 83; /* l32r */ | |
8459 | case 2: | |
8460 | switch (Field_r_Slot_inst_get (insn)) | |
8461 | { | |
8462 | case 0: | |
8463 | return 84; /* l8ui */ | |
8464 | case 1: | |
8465 | return 80; /* l16ui */ | |
8466 | case 2: | |
8467 | return 82; /* l32i */ | |
8468 | case 4: | |
8469 | return 99; /* s8i */ | |
8470 | case 5: | |
8471 | return 97; /* s16i */ | |
8472 | case 6: | |
8473 | return 98; /* s32i */ | |
8474 | case 7: | |
8475 | switch (Field_t_Slot_inst_get (insn)) | |
8476 | { | |
8477 | case 0: | |
8478 | return 258; /* dpfr */ | |
8479 | case 1: | |
8480 | return 259; /* dpfw */ | |
8481 | case 2: | |
8482 | return 260; /* dpfro */ | |
8483 | case 3: | |
8484 | return 261; /* dpfwo */ | |
8485 | case 4: | |
8486 | return 252; /* dhwb */ | |
8487 | case 5: | |
8488 | return 253; /* dhwbi */ | |
8489 | case 6: | |
8490 | return 256; /* dhi */ | |
8491 | case 7: | |
8492 | return 257; /* dii */ | |
8493 | case 8: | |
8494 | switch (Field_op1_Slot_inst_get (insn)) | |
8495 | { | |
8496 | case 4: | |
8497 | return 254; /* diwb */ | |
8498 | case 5: | |
8499 | return 255; /* diwbi */ | |
8500 | } | |
8501 | break; | |
8502 | case 12: | |
8503 | return 245; /* ipf */ | |
8504 | case 14: | |
8505 | return 246; /* ihi */ | |
8506 | case 15: | |
8507 | return 247; /* iii */ | |
8508 | } | |
8509 | break; | |
8510 | case 9: | |
8511 | return 81; /* l16si */ | |
8512 | case 10: | |
8513 | return 88; /* movi */ | |
8514 | case 12: | |
8515 | return 37; /* addi */ | |
8516 | case 13: | |
8517 | return 38; /* addmi */ | |
8518 | } | |
e0001a05 | 8519 | break; |
43cd72b9 BW |
8520 | case 5: |
8521 | switch (Field_n_Slot_inst_get (insn)) | |
8522 | { | |
8523 | case 0: | |
8524 | return 74; /* call0 */ | |
8525 | case 1: | |
8526 | return 7; /* call4 */ | |
8527 | case 2: | |
8528 | return 6; /* call8 */ | |
8529 | case 3: | |
8530 | return 5; /* call12 */ | |
8531 | } | |
e0001a05 | 8532 | break; |
43cd72b9 BW |
8533 | case 6: |
8534 | switch (Field_n_Slot_inst_get (insn)) | |
8535 | { | |
8536 | case 0: | |
8537 | return 78; /* j */ | |
8538 | case 1: | |
8539 | switch (Field_m_Slot_inst_get (insn)) | |
8540 | { | |
8541 | case 0: | |
8542 | return 70; /* beqz */ | |
8543 | case 1: | |
8544 | return 71; /* bnez */ | |
8545 | case 2: | |
8546 | return 73; /* bltz */ | |
8547 | case 3: | |
8548 | return 72; /* bgez */ | |
8549 | } | |
8550 | break; | |
8551 | case 2: | |
8552 | switch (Field_m_Slot_inst_get (insn)) | |
8553 | { | |
8554 | case 0: | |
8555 | return 50; /* beqi */ | |
8556 | case 1: | |
8557 | return 51; /* bnei */ | |
8558 | case 2: | |
8559 | return 53; /* blti */ | |
8560 | case 3: | |
8561 | return 52; /* bgei */ | |
8562 | } | |
8563 | break; | |
8564 | case 3: | |
8565 | switch (Field_m_Slot_inst_get (insn)) | |
8566 | { | |
8567 | case 0: | |
8568 | return 11; /* entry */ | |
8569 | case 1: | |
8570 | switch (Field_r_Slot_inst_get (insn)) | |
8571 | { | |
8572 | case 8: | |
8573 | return 85; /* loop */ | |
8574 | case 9: | |
8575 | return 86; /* loopnez */ | |
8576 | case 10: | |
8577 | return 87; /* loopgtz */ | |
8578 | } | |
8579 | break; | |
8580 | case 2: | |
8581 | return 57; /* bltui */ | |
8582 | case 3: | |
8583 | return 56; /* bgeui */ | |
8584 | } | |
8585 | break; | |
8586 | } | |
e0001a05 | 8587 | break; |
43cd72b9 BW |
8588 | case 7: |
8589 | switch (Field_r_Slot_inst_get (insn)) | |
8590 | { | |
8591 | case 0: | |
8592 | return 65; /* bnone */ | |
8593 | case 1: | |
8594 | return 58; /* beq */ | |
8595 | case 2: | |
8596 | return 61; /* blt */ | |
8597 | case 3: | |
8598 | return 63; /* bltu */ | |
8599 | case 4: | |
8600 | return 66; /* ball */ | |
8601 | case 5: | |
8602 | return 68; /* bbc */ | |
8603 | case 6: | |
8604 | case 7: | |
8605 | return 54; /* bbci */ | |
8606 | case 8: | |
8607 | return 64; /* bany */ | |
8608 | case 9: | |
8609 | return 59; /* bne */ | |
8610 | case 10: | |
8611 | return 60; /* bge */ | |
8612 | case 11: | |
8613 | return 62; /* bgeu */ | |
8614 | case 12: | |
8615 | return 67; /* bnall */ | |
8616 | case 13: | |
8617 | return 69; /* bbs */ | |
8618 | case 14: | |
8619 | case 15: | |
8620 | return 55; /* bbsi */ | |
8621 | } | |
e0001a05 | 8622 | break; |
e0001a05 | 8623 | } |
43cd72b9 BW |
8624 | return 0; |
8625 | } | |
8626 | ||
8627 | static int | |
8628 | Slot_inst16b_decode (const xtensa_insnbuf insn) | |
8629 | { | |
8630 | switch (Field_op0_Slot_inst16b_get (insn)) | |
8631 | { | |
8632 | case 12: | |
8633 | switch (Field_i_Slot_inst16b_get (insn)) | |
8634 | { | |
8635 | case 0: | |
8636 | return 33; /* movi.n */ | |
8637 | case 1: | |
8638 | switch (Field_z_Slot_inst16b_get (insn)) | |
8639 | { | |
8640 | case 0: | |
8641 | return 28; /* beqz.n */ | |
8642 | case 1: | |
8643 | return 29; /* bnez.n */ | |
8644 | } | |
8645 | break; | |
8646 | } | |
e0001a05 | 8647 | break; |
43cd72b9 BW |
8648 | case 13: |
8649 | switch (Field_r_Slot_inst16b_get (insn)) | |
8650 | { | |
8651 | case 0: | |
8652 | return 32; /* mov.n */ | |
8653 | case 15: | |
8654 | switch (Field_t_Slot_inst16b_get (insn)) | |
8655 | { | |
8656 | case 0: | |
8657 | return 35; /* ret.n */ | |
8658 | case 1: | |
8659 | return 15; /* retw.n */ | |
8660 | case 2: | |
8661 | return 197; /* break.n */ | |
8662 | case 3: | |
8663 | if (Field_s_Slot_inst16b_get (insn) == 0) | |
8664 | return 34; /* nop.n */ | |
8665 | break; | |
8666 | case 6: | |
8667 | return 30; /* ill.n */ | |
8668 | } | |
8669 | break; | |
8670 | } | |
e0001a05 NC |
8671 | break; |
8672 | } | |
43cd72b9 BW |
8673 | return 0; |
8674 | } | |
8675 | ||
8676 | static int | |
8677 | Slot_inst16a_decode (const xtensa_insnbuf insn) | |
8678 | { | |
8679 | switch (Field_op0_Slot_inst16a_get (insn)) | |
8680 | { | |
8681 | case 8: | |
8682 | return 31; /* l32i.n */ | |
8683 | case 9: | |
8684 | return 36; /* s32i.n */ | |
8685 | case 10: | |
8686 | return 26; /* add.n */ | |
8687 | case 11: | |
8688 | return 27; /* addi.n */ | |
e0001a05 | 8689 | } |
43cd72b9 BW |
8690 | return 0; |
8691 | } | |
8692 | ||
8693 | \f | |
8694 | /* Instruction slots. */ | |
8695 | ||
8696 | static void | |
8697 | Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, | |
8698 | xtensa_insnbuf slotbuf) | |
8699 | { | |
8700 | slotbuf[0] = (insn[0] & 0xffffff); | |
8701 | } | |
8702 | ||
8703 | static void | |
8704 | Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, | |
8705 | const xtensa_insnbuf slotbuf) | |
8706 | { | |
8707 | insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); | |
8708 | } | |
8709 | ||
8710 | static void | |
8711 | Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, | |
8712 | xtensa_insnbuf slotbuf) | |
8713 | { | |
8714 | slotbuf[0] = ((insn[0] & 0xffff00) >> 8); | |
8715 | } | |
8716 | ||
8717 | static void | |
8718 | Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, | |
8719 | const xtensa_insnbuf slotbuf) | |
8720 | { | |
8721 | insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8); | |
8722 | } | |
8723 | ||
8724 | static void | |
8725 | Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, | |
8726 | xtensa_insnbuf slotbuf) | |
8727 | { | |
8728 | slotbuf[0] = ((insn[0] & 0xffff00) >> 8); | |
8729 | } | |
8730 | ||
8731 | static void | |
8732 | Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, | |
8733 | const xtensa_insnbuf slotbuf) | |
8734 | { | |
8735 | insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8); | |
8736 | } | |
8737 | ||
8738 | static xtensa_get_field_fn | |
8739 | Slot_inst_get_field_fns[] = { | |
8740 | Field_t_Slot_inst_get, | |
8741 | Field_bbi4_Slot_inst_get, | |
8742 | Field_bbi_Slot_inst_get, | |
8743 | Field_imm12_Slot_inst_get, | |
8744 | Field_imm8_Slot_inst_get, | |
8745 | Field_s_Slot_inst_get, | |
8746 | Field_imm12b_Slot_inst_get, | |
8747 | Field_imm16_Slot_inst_get, | |
8748 | Field_m_Slot_inst_get, | |
8749 | Field_n_Slot_inst_get, | |
8750 | Field_offset_Slot_inst_get, | |
8751 | Field_op0_Slot_inst_get, | |
8752 | Field_op1_Slot_inst_get, | |
8753 | Field_op2_Slot_inst_get, | |
8754 | Field_r_Slot_inst_get, | |
8755 | Field_sa4_Slot_inst_get, | |
8756 | Field_sae4_Slot_inst_get, | |
8757 | Field_sae_Slot_inst_get, | |
8758 | Field_sal_Slot_inst_get, | |
8759 | Field_sargt_Slot_inst_get, | |
8760 | Field_sas4_Slot_inst_get, | |
8761 | Field_sas_Slot_inst_get, | |
8762 | Field_sr_Slot_inst_get, | |
8763 | Field_st_Slot_inst_get, | |
8764 | Field_thi3_Slot_inst_get, | |
8765 | Field_imm4_Slot_inst_get, | |
8766 | Field_mn_Slot_inst_get, | |
8767 | 0, | |
8768 | 0, | |
8769 | 0, | |
8770 | 0, | |
8771 | 0, | |
8772 | 0, | |
8773 | 0, | |
8774 | 0, | |
8775 | Implicit_Field_ar0_get, | |
8776 | Implicit_Field_ar4_get, | |
8777 | Implicit_Field_ar8_get, | |
8778 | Implicit_Field_ar12_get | |
8779 | }; | |
8780 | ||
8781 | static xtensa_set_field_fn | |
8782 | Slot_inst_set_field_fns[] = { | |
8783 | Field_t_Slot_inst_set, | |
8784 | Field_bbi4_Slot_inst_set, | |
8785 | Field_bbi_Slot_inst_set, | |
8786 | Field_imm12_Slot_inst_set, | |
8787 | Field_imm8_Slot_inst_set, | |
8788 | Field_s_Slot_inst_set, | |
8789 | Field_imm12b_Slot_inst_set, | |
8790 | Field_imm16_Slot_inst_set, | |
8791 | Field_m_Slot_inst_set, | |
8792 | Field_n_Slot_inst_set, | |
8793 | Field_offset_Slot_inst_set, | |
8794 | Field_op0_Slot_inst_set, | |
8795 | Field_op1_Slot_inst_set, | |
8796 | Field_op2_Slot_inst_set, | |
8797 | Field_r_Slot_inst_set, | |
8798 | Field_sa4_Slot_inst_set, | |
8799 | Field_sae4_Slot_inst_set, | |
8800 | Field_sae_Slot_inst_set, | |
8801 | Field_sal_Slot_inst_set, | |
8802 | Field_sargt_Slot_inst_set, | |
8803 | Field_sas4_Slot_inst_set, | |
8804 | Field_sas_Slot_inst_set, | |
8805 | Field_sr_Slot_inst_set, | |
8806 | Field_st_Slot_inst_set, | |
8807 | Field_thi3_Slot_inst_set, | |
8808 | Field_imm4_Slot_inst_set, | |
8809 | Field_mn_Slot_inst_set, | |
8810 | 0, | |
8811 | 0, | |
8812 | 0, | |
8813 | 0, | |
8814 | 0, | |
8815 | 0, | |
8816 | 0, | |
8817 | 0, | |
8818 | Implicit_Field_set, | |
8819 | Implicit_Field_set, | |
8820 | Implicit_Field_set, | |
8821 | Implicit_Field_set | |
8822 | }; | |
8823 | ||
8824 | static xtensa_get_field_fn | |
8825 | Slot_inst16a_get_field_fns[] = { | |
8826 | Field_t_Slot_inst16a_get, | |
8827 | 0, | |
8828 | 0, | |
8829 | 0, | |
8830 | 0, | |
8831 | Field_s_Slot_inst16a_get, | |
8832 | 0, | |
8833 | 0, | |
8834 | 0, | |
8835 | 0, | |
8836 | 0, | |
8837 | Field_op0_Slot_inst16a_get, | |
8838 | 0, | |
8839 | 0, | |
8840 | Field_r_Slot_inst16a_get, | |
8841 | 0, | |
8842 | 0, | |
8843 | 0, | |
8844 | 0, | |
8845 | 0, | |
8846 | 0, | |
8847 | 0, | |
8848 | Field_sr_Slot_inst16a_get, | |
8849 | Field_st_Slot_inst16a_get, | |
8850 | 0, | |
8851 | Field_imm4_Slot_inst16a_get, | |
8852 | 0, | |
8853 | Field_i_Slot_inst16a_get, | |
8854 | Field_imm6lo_Slot_inst16a_get, | |
8855 | Field_imm6hi_Slot_inst16a_get, | |
8856 | Field_imm7lo_Slot_inst16a_get, | |
8857 | Field_imm7hi_Slot_inst16a_get, | |
8858 | Field_z_Slot_inst16a_get, | |
8859 | Field_imm6_Slot_inst16a_get, | |
8860 | Field_imm7_Slot_inst16a_get, | |
8861 | Implicit_Field_ar0_get, | |
8862 | Implicit_Field_ar4_get, | |
8863 | Implicit_Field_ar8_get, | |
8864 | Implicit_Field_ar12_get | |
8865 | }; | |
8866 | ||
8867 | static xtensa_set_field_fn | |
8868 | Slot_inst16a_set_field_fns[] = { | |
8869 | Field_t_Slot_inst16a_set, | |
8870 | 0, | |
8871 | 0, | |
8872 | 0, | |
8873 | 0, | |
8874 | Field_s_Slot_inst16a_set, | |
8875 | 0, | |
8876 | 0, | |
8877 | 0, | |
8878 | 0, | |
8879 | 0, | |
8880 | Field_op0_Slot_inst16a_set, | |
8881 | 0, | |
8882 | 0, | |
8883 | Field_r_Slot_inst16a_set, | |
8884 | 0, | |
8885 | 0, | |
8886 | 0, | |
8887 | 0, | |
8888 | 0, | |
8889 | 0, | |
8890 | 0, | |
8891 | Field_sr_Slot_inst16a_set, | |
8892 | Field_st_Slot_inst16a_set, | |
8893 | 0, | |
8894 | Field_imm4_Slot_inst16a_set, | |
8895 | 0, | |
8896 | Field_i_Slot_inst16a_set, | |
8897 | Field_imm6lo_Slot_inst16a_set, | |
8898 | Field_imm6hi_Slot_inst16a_set, | |
8899 | Field_imm7lo_Slot_inst16a_set, | |
8900 | Field_imm7hi_Slot_inst16a_set, | |
8901 | Field_z_Slot_inst16a_set, | |
8902 | Field_imm6_Slot_inst16a_set, | |
8903 | Field_imm7_Slot_inst16a_set, | |
8904 | Implicit_Field_set, | |
8905 | Implicit_Field_set, | |
8906 | Implicit_Field_set, | |
8907 | Implicit_Field_set | |
8908 | }; | |
8909 | ||
8910 | static xtensa_get_field_fn | |
8911 | Slot_inst16b_get_field_fns[] = { | |
8912 | Field_t_Slot_inst16b_get, | |
8913 | 0, | |
8914 | 0, | |
8915 | 0, | |
8916 | 0, | |
8917 | Field_s_Slot_inst16b_get, | |
8918 | 0, | |
8919 | 0, | |
8920 | 0, | |
8921 | 0, | |
8922 | 0, | |
8923 | Field_op0_Slot_inst16b_get, | |
8924 | 0, | |
8925 | 0, | |
8926 | Field_r_Slot_inst16b_get, | |
8927 | 0, | |
8928 | 0, | |
8929 | 0, | |
8930 | 0, | |
8931 | 0, | |
8932 | 0, | |
8933 | 0, | |
8934 | Field_sr_Slot_inst16b_get, | |
8935 | Field_st_Slot_inst16b_get, | |
8936 | 0, | |
8937 | Field_imm4_Slot_inst16b_get, | |
8938 | 0, | |
8939 | Field_i_Slot_inst16b_get, | |
8940 | Field_imm6lo_Slot_inst16b_get, | |
8941 | Field_imm6hi_Slot_inst16b_get, | |
8942 | Field_imm7lo_Slot_inst16b_get, | |
8943 | Field_imm7hi_Slot_inst16b_get, | |
8944 | Field_z_Slot_inst16b_get, | |
8945 | Field_imm6_Slot_inst16b_get, | |
8946 | Field_imm7_Slot_inst16b_get, | |
8947 | Implicit_Field_ar0_get, | |
8948 | Implicit_Field_ar4_get, | |
8949 | Implicit_Field_ar8_get, | |
8950 | Implicit_Field_ar12_get | |
8951 | }; | |
8952 | ||
8953 | static xtensa_set_field_fn | |
8954 | Slot_inst16b_set_field_fns[] = { | |
8955 | Field_t_Slot_inst16b_set, | |
8956 | 0, | |
8957 | 0, | |
8958 | 0, | |
8959 | 0, | |
8960 | Field_s_Slot_inst16b_set, | |
8961 | 0, | |
8962 | 0, | |
8963 | 0, | |
8964 | 0, | |
8965 | 0, | |
8966 | Field_op0_Slot_inst16b_set, | |
8967 | 0, | |
8968 | 0, | |
8969 | Field_r_Slot_inst16b_set, | |
8970 | 0, | |
8971 | 0, | |
8972 | 0, | |
8973 | 0, | |
8974 | 0, | |
8975 | 0, | |
8976 | 0, | |
8977 | Field_sr_Slot_inst16b_set, | |
8978 | Field_st_Slot_inst16b_set, | |
8979 | 0, | |
8980 | Field_imm4_Slot_inst16b_set, | |
8981 | 0, | |
8982 | Field_i_Slot_inst16b_set, | |
8983 | Field_imm6lo_Slot_inst16b_set, | |
8984 | Field_imm6hi_Slot_inst16b_set, | |
8985 | Field_imm7lo_Slot_inst16b_set, | |
8986 | Field_imm7hi_Slot_inst16b_set, | |
8987 | Field_z_Slot_inst16b_set, | |
8988 | Field_imm6_Slot_inst16b_set, | |
8989 | Field_imm7_Slot_inst16b_set, | |
8990 | Implicit_Field_set, | |
8991 | Implicit_Field_set, | |
8992 | Implicit_Field_set, | |
8993 | Implicit_Field_set | |
8994 | }; | |
8995 | ||
8996 | static xtensa_slot_internal slots[] = { | |
8997 | { "Inst", "x24", 0, | |
8998 | Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, | |
8999 | Slot_inst_get_field_fns, Slot_inst_set_field_fns, | |
9000 | Slot_inst_decode, "nop" }, | |
9001 | { "Inst16a", "x16a", 0, | |
9002 | Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, | |
9003 | Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, | |
9004 | Slot_inst16a_decode, "" }, | |
9005 | { "Inst16b", "x16b", 0, | |
9006 | Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, | |
9007 | Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, | |
9008 | Slot_inst16b_decode, "nop.n" } | |
9009 | }; | |
9010 | ||
9011 | \f | |
9012 | /* Instruction formats. */ | |
9013 | ||
9014 | static void | |
9015 | Format_x24_encode (xtensa_insnbuf insn) | |
9016 | { | |
9017 | insn[0] = 0; | |
9018 | } | |
9019 | ||
9020 | static void | |
9021 | Format_x16a_encode (xtensa_insnbuf insn) | |
9022 | { | |
9023 | insn[0] = 0x800000; | |
e0001a05 NC |
9024 | } |
9025 | ||
43cd72b9 BW |
9026 | static void |
9027 | Format_x16b_encode (xtensa_insnbuf insn) | |
e0001a05 | 9028 | { |
43cd72b9 | 9029 | insn[0] = 0xc00000; |
e0001a05 NC |
9030 | } |
9031 | ||
43cd72b9 BW |
9032 | static int Format_x24_slots[] = { 0 }; |
9033 | ||
9034 | static int Format_x16a_slots[] = { 1 }; | |
9035 | ||
9036 | static int Format_x16b_slots[] = { 2 }; | |
9037 | ||
9038 | static xtensa_format_internal formats[] = { | |
9039 | { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, | |
9040 | { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, | |
9041 | { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } | |
e0001a05 NC |
9042 | }; |
9043 | ||
e0001a05 | 9044 | |
43cd72b9 BW |
9045 | static int |
9046 | format_decoder (const xtensa_insnbuf insn) | |
e0001a05 | 9047 | { |
43cd72b9 BW |
9048 | if ((insn[0] & 0x800000) == 0) |
9049 | return 0; /* x24 */ | |
9050 | if ((insn[0] & 0xc00000) == 0x800000) | |
9051 | return 1; /* x16a */ | |
9052 | if ((insn[0] & 0xe00000) == 0xc00000) | |
9053 | return 2; /* x16b */ | |
9054 | return -1; | |
e0001a05 NC |
9055 | } |
9056 | ||
43cd72b9 BW |
9057 | static int length_table[16] = { |
9058 | 3, | |
9059 | 3, | |
9060 | 3, | |
9061 | 3, | |
9062 | 3, | |
9063 | 3, | |
9064 | 3, | |
9065 | 3, | |
9066 | 2, | |
9067 | 2, | |
9068 | 2, | |
9069 | 2, | |
9070 | 2, | |
9071 | 2, | |
9072 | -1, | |
9073 | -1 | |
9074 | }; | |
9075 | ||
9076 | static int | |
9077 | length_decoder (const char *insn) | |
9078 | { | |
9079 | int op0 = (insn[0] >> 4) & 0xf; | |
9080 | return length_table[op0]; | |
9081 | } | |
9082 | ||
9083 | \f | |
9084 | /* Top-level ISA structure. */ | |
9085 | ||
9086 | xtensa_isa_internal xtensa_modules = { | |
9087 | 1 /* big-endian */, | |
9088 | 3 /* insn_size */, 0, | |
9089 | 3, formats, format_decoder, length_decoder, | |
9090 | 3, slots, | |
9091 | 39 /* num_fields */, | |
9092 | 70, operands, | |
9093 | 220, iclasses, | |
9094 | 276, opcodes, 0, | |
9095 | 1, regfiles, | |
9096 | NUM_STATES, states, 0, | |
9097 | NUM_SYSREGS, sysregs, 0, | |
9098 | { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, | |
9099 | 0, interfaces, 0, | |
9100 | 0, funcUnits, 0 | |
e0001a05 | 9101 | }; |