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e0001a05 NC |
1 | /* Xtensa configuration-specific ISA information. |
2 | Copyright 2003 Free Software Foundation, Inc. | |
3 | ||
4 | This file is part of BFD, the Binary File Descriptor library. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
19 | ||
e0001a05 NC |
20 | #include <xtensa-isa.h> |
21 | #include "xtensa-isa-internal.h" | |
22 | #include "ansidecl.h" | |
23 | ||
24 | #define BPW 32 | |
25 | #define WINDEX(_n) ((_n) / BPW) | |
26 | #define BINDEX(_n) ((_n) %% BPW) | |
27 | ||
28 | static uint32 tie_do_reloc_l (uint32, uint32) ATTRIBUTE_UNUSED; | |
29 | static uint32 tie_undo_reloc_l (uint32, uint32) ATTRIBUTE_UNUSED; | |
30 | ||
31 | static uint32 | |
32 | tie_do_reloc_l (uint32 addr, uint32 pc) | |
33 | { | |
34 | return (addr - pc); | |
35 | } | |
36 | ||
37 | static uint32 | |
38 | tie_undo_reloc_l (uint32 offset, uint32 pc) | |
39 | { | |
40 | return (pc + offset); | |
41 | } | |
42 | ||
43 | xtensa_opcode_internal** get_opcodes (void); | |
44 | const int get_num_opcodes (void); | |
45 | int decode_insn (const xtensa_insnbuf); | |
46 | int interface_version (void); | |
47 | ||
48 | uint32 get_bbi_field (const xtensa_insnbuf); | |
49 | void set_bbi_field (xtensa_insnbuf, uint32); | |
50 | uint32 get_bbi4_field (const xtensa_insnbuf); | |
51 | void set_bbi4_field (xtensa_insnbuf, uint32); | |
52 | uint32 get_i_field (const xtensa_insnbuf); | |
53 | void set_i_field (xtensa_insnbuf, uint32); | |
54 | uint32 get_imm12_field (const xtensa_insnbuf); | |
55 | void set_imm12_field (xtensa_insnbuf, uint32); | |
56 | uint32 get_imm12b_field (const xtensa_insnbuf); | |
57 | void set_imm12b_field (xtensa_insnbuf, uint32); | |
58 | uint32 get_imm16_field (const xtensa_insnbuf); | |
59 | void set_imm16_field (xtensa_insnbuf, uint32); | |
60 | uint32 get_imm4_field (const xtensa_insnbuf); | |
61 | void set_imm4_field (xtensa_insnbuf, uint32); | |
62 | uint32 get_imm6_field (const xtensa_insnbuf); | |
63 | void set_imm6_field (xtensa_insnbuf, uint32); | |
64 | uint32 get_imm6hi_field (const xtensa_insnbuf); | |
65 | void set_imm6hi_field (xtensa_insnbuf, uint32); | |
66 | uint32 get_imm6lo_field (const xtensa_insnbuf); | |
67 | void set_imm6lo_field (xtensa_insnbuf, uint32); | |
68 | uint32 get_imm7_field (const xtensa_insnbuf); | |
69 | void set_imm7_field (xtensa_insnbuf, uint32); | |
70 | uint32 get_imm7hi_field (const xtensa_insnbuf); | |
71 | void set_imm7hi_field (xtensa_insnbuf, uint32); | |
72 | uint32 get_imm7lo_field (const xtensa_insnbuf); | |
73 | void set_imm7lo_field (xtensa_insnbuf, uint32); | |
74 | uint32 get_imm8_field (const xtensa_insnbuf); | |
75 | void set_imm8_field (xtensa_insnbuf, uint32); | |
76 | uint32 get_m_field (const xtensa_insnbuf); | |
77 | void set_m_field (xtensa_insnbuf, uint32); | |
78 | uint32 get_mn_field (const xtensa_insnbuf); | |
79 | void set_mn_field (xtensa_insnbuf, uint32); | |
80 | uint32 get_n_field (const xtensa_insnbuf); | |
81 | void set_n_field (xtensa_insnbuf, uint32); | |
82 | uint32 get_none_field (const xtensa_insnbuf); | |
83 | void set_none_field (xtensa_insnbuf, uint32); | |
84 | uint32 get_offset_field (const xtensa_insnbuf); | |
85 | void set_offset_field (xtensa_insnbuf, uint32); | |
86 | uint32 get_op0_field (const xtensa_insnbuf); | |
87 | void set_op0_field (xtensa_insnbuf, uint32); | |
88 | uint32 get_op1_field (const xtensa_insnbuf); | |
89 | void set_op1_field (xtensa_insnbuf, uint32); | |
90 | uint32 get_op2_field (const xtensa_insnbuf); | |
91 | void set_op2_field (xtensa_insnbuf, uint32); | |
92 | uint32 get_r_field (const xtensa_insnbuf); | |
93 | void set_r_field (xtensa_insnbuf, uint32); | |
94 | uint32 get_s_field (const xtensa_insnbuf); | |
95 | void set_s_field (xtensa_insnbuf, uint32); | |
96 | uint32 get_sa4_field (const xtensa_insnbuf); | |
97 | void set_sa4_field (xtensa_insnbuf, uint32); | |
98 | uint32 get_sae_field (const xtensa_insnbuf); | |
99 | void set_sae_field (xtensa_insnbuf, uint32); | |
100 | uint32 get_sae4_field (const xtensa_insnbuf); | |
101 | void set_sae4_field (xtensa_insnbuf, uint32); | |
102 | uint32 get_sal_field (const xtensa_insnbuf); | |
103 | void set_sal_field (xtensa_insnbuf, uint32); | |
104 | uint32 get_sar_field (const xtensa_insnbuf); | |
105 | void set_sar_field (xtensa_insnbuf, uint32); | |
106 | uint32 get_sas_field (const xtensa_insnbuf); | |
107 | void set_sas_field (xtensa_insnbuf, uint32); | |
108 | uint32 get_sas4_field (const xtensa_insnbuf); | |
109 | void set_sas4_field (xtensa_insnbuf, uint32); | |
110 | uint32 get_sr_field (const xtensa_insnbuf); | |
111 | void set_sr_field (xtensa_insnbuf, uint32); | |
112 | uint32 get_t_field (const xtensa_insnbuf); | |
113 | void set_t_field (xtensa_insnbuf, uint32); | |
114 | uint32 get_thi3_field (const xtensa_insnbuf); | |
115 | void set_thi3_field (xtensa_insnbuf, uint32); | |
116 | uint32 get_z_field (const xtensa_insnbuf); | |
117 | void set_z_field (xtensa_insnbuf, uint32); | |
118 | ||
119 | ||
120 | uint32 | |
121 | get_bbi_field (const xtensa_insnbuf insn) | |
122 | { | |
123 | return ((insn[0] & 0xf0000) >> 16) | | |
124 | ((insn[0] & 0x100) >> 4); | |
125 | } | |
126 | ||
127 | void | |
128 | set_bbi_field (xtensa_insnbuf insn, uint32 val) | |
129 | { | |
130 | insn[0] = (insn[0] & 0xfff0ffff) | ((val << 16) & 0xf0000); | |
131 | insn[0] = (insn[0] & 0xfffffeff) | ((val << 4) & 0x100); | |
132 | } | |
133 | ||
134 | uint32 | |
135 | get_bbi4_field (const xtensa_insnbuf insn) | |
136 | { | |
137 | return ((insn[0] & 0x100) >> 8); | |
138 | } | |
139 | ||
140 | void | |
141 | set_bbi4_field (xtensa_insnbuf insn, uint32 val) | |
142 | { | |
143 | insn[0] = (insn[0] & 0xfffffeff) | ((val << 8) & 0x100); | |
144 | } | |
145 | ||
146 | uint32 | |
147 | get_i_field (const xtensa_insnbuf insn) | |
148 | { | |
149 | return ((insn[0] & 0x80000) >> 19); | |
150 | } | |
151 | ||
152 | void | |
153 | set_i_field (xtensa_insnbuf insn, uint32 val) | |
154 | { | |
155 | insn[0] = (insn[0] & 0xfff7ffff) | ((val << 19) & 0x80000); | |
156 | } | |
157 | ||
158 | uint32 | |
159 | get_imm12_field (const xtensa_insnbuf insn) | |
160 | { | |
161 | return ((insn[0] & 0xfff)); | |
162 | } | |
163 | ||
164 | void | |
165 | set_imm12_field (xtensa_insnbuf insn, uint32 val) | |
166 | { | |
167 | insn[0] = (insn[0] & 0xfffff000) | (val & 0xfff); | |
168 | } | |
169 | ||
170 | uint32 | |
171 | get_imm12b_field (const xtensa_insnbuf insn) | |
172 | { | |
173 | return ((insn[0] & 0xff)) | | |
174 | ((insn[0] & 0xf000) >> 4); | |
175 | } | |
176 | ||
177 | void | |
178 | set_imm12b_field (xtensa_insnbuf insn, uint32 val) | |
179 | { | |
180 | insn[0] = (insn[0] & 0xffffff00) | (val & 0xff); | |
181 | insn[0] = (insn[0] & 0xffff0fff) | ((val << 4) & 0xf000); | |
182 | } | |
183 | ||
184 | uint32 | |
185 | get_imm16_field (const xtensa_insnbuf insn) | |
186 | { | |
187 | return ((insn[0] & 0xffff)); | |
188 | } | |
189 | ||
190 | void | |
191 | set_imm16_field (xtensa_insnbuf insn, uint32 val) | |
192 | { | |
193 | insn[0] = (insn[0] & 0xffff0000) | (val & 0xffff); | |
194 | } | |
195 | ||
196 | uint32 | |
197 | get_imm4_field (const xtensa_insnbuf insn) | |
198 | { | |
199 | return ((insn[0] & 0xf00) >> 8); | |
200 | } | |
201 | ||
202 | void | |
203 | set_imm4_field (xtensa_insnbuf insn, uint32 val) | |
204 | { | |
205 | insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00); | |
206 | } | |
207 | ||
208 | uint32 | |
209 | get_imm6_field (const xtensa_insnbuf insn) | |
210 | { | |
211 | return ((insn[0] & 0xf00) >> 8) | | |
212 | ((insn[0] & 0x30000) >> 12); | |
213 | } | |
214 | ||
215 | void | |
216 | set_imm6_field (xtensa_insnbuf insn, uint32 val) | |
217 | { | |
218 | insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00); | |
219 | insn[0] = (insn[0] & 0xfffcffff) | ((val << 12) & 0x30000); | |
220 | } | |
221 | ||
222 | uint32 | |
223 | get_imm6hi_field (const xtensa_insnbuf insn) | |
224 | { | |
225 | return ((insn[0] & 0x30000) >> 16); | |
226 | } | |
227 | ||
228 | void | |
229 | set_imm6hi_field (xtensa_insnbuf insn, uint32 val) | |
230 | { | |
231 | insn[0] = (insn[0] & 0xfffcffff) | ((val << 16) & 0x30000); | |
232 | } | |
233 | ||
234 | uint32 | |
235 | get_imm6lo_field (const xtensa_insnbuf insn) | |
236 | { | |
237 | return ((insn[0] & 0xf00) >> 8); | |
238 | } | |
239 | ||
240 | void | |
241 | set_imm6lo_field (xtensa_insnbuf insn, uint32 val) | |
242 | { | |
243 | insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00); | |
244 | } | |
245 | ||
246 | uint32 | |
247 | get_imm7_field (const xtensa_insnbuf insn) | |
248 | { | |
249 | return ((insn[0] & 0xf00) >> 8) | | |
250 | ((insn[0] & 0x70000) >> 12); | |
251 | } | |
252 | ||
253 | void | |
254 | set_imm7_field (xtensa_insnbuf insn, uint32 val) | |
255 | { | |
256 | insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00); | |
257 | insn[0] = (insn[0] & 0xfff8ffff) | ((val << 12) & 0x70000); | |
258 | } | |
259 | ||
260 | uint32 | |
261 | get_imm7hi_field (const xtensa_insnbuf insn) | |
262 | { | |
263 | return ((insn[0] & 0x70000) >> 16); | |
264 | } | |
265 | ||
266 | void | |
267 | set_imm7hi_field (xtensa_insnbuf insn, uint32 val) | |
268 | { | |
269 | insn[0] = (insn[0] & 0xfff8ffff) | ((val << 16) & 0x70000); | |
270 | } | |
271 | ||
272 | uint32 | |
273 | get_imm7lo_field (const xtensa_insnbuf insn) | |
274 | { | |
275 | return ((insn[0] & 0xf00) >> 8); | |
276 | } | |
277 | ||
278 | void | |
279 | set_imm7lo_field (xtensa_insnbuf insn, uint32 val) | |
280 | { | |
281 | insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00); | |
282 | } | |
283 | ||
284 | uint32 | |
285 | get_imm8_field (const xtensa_insnbuf insn) | |
286 | { | |
287 | return ((insn[0] & 0xff)); | |
288 | } | |
289 | ||
290 | void | |
291 | set_imm8_field (xtensa_insnbuf insn, uint32 val) | |
292 | { | |
293 | insn[0] = (insn[0] & 0xffffff00) | (val & 0xff); | |
294 | } | |
295 | ||
296 | uint32 | |
297 | get_m_field (const xtensa_insnbuf insn) | |
298 | { | |
299 | return ((insn[0] & 0x30000) >> 16); | |
300 | } | |
301 | ||
302 | void | |
303 | set_m_field (xtensa_insnbuf insn, uint32 val) | |
304 | { | |
305 | insn[0] = (insn[0] & 0xfffcffff) | ((val << 16) & 0x30000); | |
306 | } | |
307 | ||
308 | uint32 | |
309 | get_mn_field (const xtensa_insnbuf insn) | |
310 | { | |
311 | return ((insn[0] & 0x30000) >> 16) | | |
312 | ((insn[0] & 0xc0000) >> 16); | |
313 | } | |
314 | ||
315 | void | |
316 | set_mn_field (xtensa_insnbuf insn, uint32 val) | |
317 | { | |
318 | insn[0] = (insn[0] & 0xfffcffff) | ((val << 16) & 0x30000); | |
319 | insn[0] = (insn[0] & 0xfff3ffff) | ((val << 16) & 0xc0000); | |
320 | } | |
321 | ||
322 | uint32 | |
323 | get_n_field (const xtensa_insnbuf insn) | |
324 | { | |
325 | return ((insn[0] & 0xc0000) >> 18); | |
326 | } | |
327 | ||
328 | void | |
329 | set_n_field (xtensa_insnbuf insn, uint32 val) | |
330 | { | |
331 | insn[0] = (insn[0] & 0xfff3ffff) | ((val << 18) & 0xc0000); | |
332 | } | |
333 | ||
334 | uint32 | |
335 | get_none_field (const xtensa_insnbuf insn) | |
336 | { | |
337 | return ((insn[0] & 0x0)); | |
338 | } | |
339 | ||
340 | void | |
341 | set_none_field (xtensa_insnbuf insn, uint32 val) | |
342 | { | |
343 | insn[0] = (insn[0] & 0xffffffff) | (val & 0x0); | |
344 | } | |
345 | ||
346 | uint32 | |
347 | get_offset_field (const xtensa_insnbuf insn) | |
348 | { | |
349 | return ((insn[0] & 0x3ffff)); | |
350 | } | |
351 | ||
352 | void | |
353 | set_offset_field (xtensa_insnbuf insn, uint32 val) | |
354 | { | |
355 | insn[0] = (insn[0] & 0xfffc0000) | (val & 0x3ffff); | |
356 | } | |
357 | ||
358 | uint32 | |
359 | get_op0_field (const xtensa_insnbuf insn) | |
360 | { | |
361 | return ((insn[0] & 0xf00000) >> 20); | |
362 | } | |
363 | ||
364 | void | |
365 | set_op0_field (xtensa_insnbuf insn, uint32 val) | |
366 | { | |
367 | insn[0] = (insn[0] & 0xff0fffff) | ((val << 20) & 0xf00000); | |
368 | } | |
369 | ||
370 | uint32 | |
371 | get_op1_field (const xtensa_insnbuf insn) | |
372 | { | |
373 | return ((insn[0] & 0xf0) >> 4); | |
374 | } | |
375 | ||
376 | void | |
377 | set_op1_field (xtensa_insnbuf insn, uint32 val) | |
378 | { | |
379 | insn[0] = (insn[0] & 0xffffff0f) | ((val << 4) & 0xf0); | |
380 | } | |
381 | ||
382 | uint32 | |
383 | get_op2_field (const xtensa_insnbuf insn) | |
384 | { | |
385 | return ((insn[0] & 0xf)); | |
386 | } | |
387 | ||
388 | void | |
389 | set_op2_field (xtensa_insnbuf insn, uint32 val) | |
390 | { | |
391 | insn[0] = (insn[0] & 0xfffffff0) | (val & 0xf); | |
392 | } | |
393 | ||
394 | uint32 | |
395 | get_r_field (const xtensa_insnbuf insn) | |
396 | { | |
397 | return ((insn[0] & 0xf00) >> 8); | |
398 | } | |
399 | ||
400 | void | |
401 | set_r_field (xtensa_insnbuf insn, uint32 val) | |
402 | { | |
403 | insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00); | |
404 | } | |
405 | ||
406 | uint32 | |
407 | get_s_field (const xtensa_insnbuf insn) | |
408 | { | |
409 | return ((insn[0] & 0xf000) >> 12); | |
410 | } | |
411 | ||
412 | void | |
413 | set_s_field (xtensa_insnbuf insn, uint32 val) | |
414 | { | |
415 | insn[0] = (insn[0] & 0xffff0fff) | ((val << 12) & 0xf000); | |
416 | } | |
417 | ||
418 | uint32 | |
419 | get_sa4_field (const xtensa_insnbuf insn) | |
420 | { | |
421 | return ((insn[0] & 0x1)); | |
422 | } | |
423 | ||
424 | void | |
425 | set_sa4_field (xtensa_insnbuf insn, uint32 val) | |
426 | { | |
427 | insn[0] = (insn[0] & 0xfffffffe) | (val & 0x1); | |
428 | } | |
429 | ||
430 | uint32 | |
431 | get_sae_field (const xtensa_insnbuf insn) | |
432 | { | |
433 | return ((insn[0] & 0xf000) >> 12) | | |
434 | ((insn[0] & 0x10)); | |
435 | } | |
436 | ||
437 | void | |
438 | set_sae_field (xtensa_insnbuf insn, uint32 val) | |
439 | { | |
440 | insn[0] = (insn[0] & 0xffff0fff) | ((val << 12) & 0xf000); | |
441 | insn[0] = (insn[0] & 0xffffffef) | (val & 0x10); | |
442 | } | |
443 | ||
444 | uint32 | |
445 | get_sae4_field (const xtensa_insnbuf insn) | |
446 | { | |
447 | return ((insn[0] & 0x10) >> 4); | |
448 | } | |
449 | ||
450 | void | |
451 | set_sae4_field (xtensa_insnbuf insn, uint32 val) | |
452 | { | |
453 | insn[0] = (insn[0] & 0xffffffef) | ((val << 4) & 0x10); | |
454 | } | |
455 | ||
456 | uint32 | |
457 | get_sal_field (const xtensa_insnbuf insn) | |
458 | { | |
459 | return ((insn[0] & 0xf0000) >> 16) | | |
460 | ((insn[0] & 0x1) << 4); | |
461 | } | |
462 | ||
463 | void | |
464 | set_sal_field (xtensa_insnbuf insn, uint32 val) | |
465 | { | |
466 | insn[0] = (insn[0] & 0xfff0ffff) | ((val << 16) & 0xf0000); | |
467 | insn[0] = (insn[0] & 0xfffffffe) | ((val >> 4) & 0x1); | |
468 | } | |
469 | ||
470 | uint32 | |
471 | get_sar_field (const xtensa_insnbuf insn) | |
472 | { | |
473 | return ((insn[0] & 0xf000) >> 12) | | |
474 | ((insn[0] & 0x1) << 4); | |
475 | } | |
476 | ||
477 | void | |
478 | set_sar_field (xtensa_insnbuf insn, uint32 val) | |
479 | { | |
480 | insn[0] = (insn[0] & 0xffff0fff) | ((val << 12) & 0xf000); | |
481 | insn[0] = (insn[0] & 0xfffffffe) | ((val >> 4) & 0x1); | |
482 | } | |
483 | ||
484 | uint32 | |
485 | get_sas_field (const xtensa_insnbuf insn) | |
486 | { | |
487 | return ((insn[0] & 0xf000) >> 12) | | |
488 | ((insn[0] & 0x10000) >> 12); | |
489 | } | |
490 | ||
491 | void | |
492 | set_sas_field (xtensa_insnbuf insn, uint32 val) | |
493 | { | |
494 | insn[0] = (insn[0] & 0xffff0fff) | ((val << 12) & 0xf000); | |
495 | insn[0] = (insn[0] & 0xfffeffff) | ((val << 12) & 0x10000); | |
496 | } | |
497 | ||
498 | uint32 | |
499 | get_sas4_field (const xtensa_insnbuf insn) | |
500 | { | |
501 | return ((insn[0] & 0x10000) >> 16); | |
502 | } | |
503 | ||
504 | void | |
505 | set_sas4_field (xtensa_insnbuf insn, uint32 val) | |
506 | { | |
507 | insn[0] = (insn[0] & 0xfffeffff) | ((val << 16) & 0x10000); | |
508 | } | |
509 | ||
510 | uint32 | |
511 | get_sr_field (const xtensa_insnbuf insn) | |
512 | { | |
513 | return ((insn[0] & 0xf00) >> 8) | | |
514 | ((insn[0] & 0xf000) >> 8); | |
515 | } | |
516 | ||
517 | void | |
518 | set_sr_field (xtensa_insnbuf insn, uint32 val) | |
519 | { | |
520 | insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00); | |
521 | insn[0] = (insn[0] & 0xffff0fff) | ((val << 8) & 0xf000); | |
522 | } | |
523 | ||
524 | uint32 | |
525 | get_t_field (const xtensa_insnbuf insn) | |
526 | { | |
527 | return ((insn[0] & 0xf0000) >> 16); | |
528 | } | |
529 | ||
530 | void | |
531 | set_t_field (xtensa_insnbuf insn, uint32 val) | |
532 | { | |
533 | insn[0] = (insn[0] & 0xfff0ffff) | ((val << 16) & 0xf0000); | |
534 | } | |
535 | ||
536 | uint32 | |
537 | get_thi3_field (const xtensa_insnbuf insn) | |
538 | { | |
539 | return ((insn[0] & 0xe0000) >> 17); | |
540 | } | |
541 | ||
542 | void | |
543 | set_thi3_field (xtensa_insnbuf insn, uint32 val) | |
544 | { | |
545 | insn[0] = (insn[0] & 0xfff1ffff) | ((val << 17) & 0xe0000); | |
546 | } | |
547 | ||
548 | uint32 | |
549 | get_z_field (const xtensa_insnbuf insn) | |
550 | { | |
551 | return ((insn[0] & 0x40000) >> 18); | |
552 | } | |
553 | ||
554 | void | |
555 | set_z_field (xtensa_insnbuf insn, uint32 val) | |
556 | { | |
557 | insn[0] = (insn[0] & 0xfffbffff) | ((val << 18) & 0x40000); | |
558 | } | |
559 | ||
560 | uint32 decode_b4constu (uint32); | |
561 | xtensa_encode_result encode_b4constu (uint32 *); | |
562 | uint32 decode_simm8x256 (uint32); | |
563 | xtensa_encode_result encode_simm8x256 (uint32 *); | |
564 | uint32 decode_soffset (uint32); | |
565 | xtensa_encode_result encode_soffset (uint32 *); | |
566 | uint32 decode_imm4 (uint32); | |
567 | xtensa_encode_result encode_imm4 (uint32 *); | |
568 | uint32 decode_op0 (uint32); | |
569 | xtensa_encode_result encode_op0 (uint32 *); | |
570 | uint32 decode_op1 (uint32); | |
571 | xtensa_encode_result encode_op1 (uint32 *); | |
572 | uint32 decode_imm6 (uint32); | |
573 | xtensa_encode_result encode_imm6 (uint32 *); | |
574 | uint32 decode_op2 (uint32); | |
575 | xtensa_encode_result encode_op2 (uint32 *); | |
576 | uint32 decode_imm7 (uint32); | |
577 | xtensa_encode_result encode_imm7 (uint32 *); | |
578 | uint32 decode_simm4 (uint32); | |
579 | xtensa_encode_result encode_simm4 (uint32 *); | |
580 | uint32 decode_ai4const (uint32); | |
581 | xtensa_encode_result encode_ai4const (uint32 *); | |
582 | uint32 decode_imm8 (uint32); | |
583 | xtensa_encode_result encode_imm8 (uint32 *); | |
584 | uint32 decode_sae (uint32); | |
585 | xtensa_encode_result encode_sae (uint32 *); | |
586 | uint32 decode_imm7lo (uint32); | |
587 | xtensa_encode_result encode_imm7lo (uint32 *); | |
588 | uint32 decode_simm7 (uint32); | |
589 | xtensa_encode_result encode_simm7 (uint32 *); | |
590 | uint32 decode_simm8 (uint32); | |
591 | xtensa_encode_result encode_simm8 (uint32 *); | |
592 | uint32 decode_uimm12x8 (uint32); | |
593 | xtensa_encode_result encode_uimm12x8 (uint32 *); | |
594 | uint32 decode_sal (uint32); | |
595 | xtensa_encode_result encode_sal (uint32 *); | |
596 | uint32 decode_uimm6 (uint32); | |
597 | xtensa_encode_result encode_uimm6 (uint32 *); | |
598 | uint32 decode_sas4 (uint32); | |
599 | xtensa_encode_result encode_sas4 (uint32 *); | |
600 | uint32 decode_uimm8 (uint32); | |
601 | xtensa_encode_result encode_uimm8 (uint32 *); | |
602 | uint32 decode_uimm16x4 (uint32); | |
603 | xtensa_encode_result encode_uimm16x4 (uint32 *); | |
604 | uint32 decode_sar (uint32); | |
605 | xtensa_encode_result encode_sar (uint32 *); | |
606 | uint32 decode_sa4 (uint32); | |
607 | xtensa_encode_result encode_sa4 (uint32 *); | |
608 | uint32 decode_sas (uint32); | |
609 | xtensa_encode_result encode_sas (uint32 *); | |
610 | uint32 decode_imm6hi (uint32); | |
611 | xtensa_encode_result encode_imm6hi (uint32 *); | |
612 | uint32 decode_bbi (uint32); | |
613 | xtensa_encode_result encode_bbi (uint32 *); | |
614 | uint32 decode_uimm8x2 (uint32); | |
615 | xtensa_encode_result encode_uimm8x2 (uint32 *); | |
616 | uint32 decode_uimm8x4 (uint32); | |
617 | xtensa_encode_result encode_uimm8x4 (uint32 *); | |
618 | uint32 decode_msalp32 (uint32); | |
619 | xtensa_encode_result encode_msalp32 (uint32 *); | |
620 | uint32 decode_bbi4 (uint32); | |
621 | xtensa_encode_result encode_bbi4 (uint32 *); | |
622 | uint32 decode_op2p1 (uint32); | |
623 | xtensa_encode_result encode_op2p1 (uint32 *); | |
624 | uint32 decode_soffsetx4 (uint32); | |
625 | xtensa_encode_result encode_soffsetx4 (uint32 *); | |
626 | uint32 decode_imm6lo (uint32); | |
627 | xtensa_encode_result encode_imm6lo (uint32 *); | |
628 | uint32 decode_imm12 (uint32); | |
629 | xtensa_encode_result encode_imm12 (uint32 *); | |
630 | uint32 decode_b4const (uint32); | |
631 | xtensa_encode_result encode_b4const (uint32 *); | |
632 | uint32 decode_i (uint32); | |
633 | xtensa_encode_result encode_i (uint32 *); | |
634 | uint32 decode_imm16 (uint32); | |
635 | xtensa_encode_result encode_imm16 (uint32 *); | |
636 | uint32 decode_mn (uint32); | |
637 | xtensa_encode_result encode_mn (uint32 *); | |
638 | uint32 decode_m (uint32); | |
639 | xtensa_encode_result encode_m (uint32 *); | |
640 | uint32 decode_n (uint32); | |
641 | xtensa_encode_result encode_n (uint32 *); | |
642 | uint32 decode_none (uint32); | |
643 | xtensa_encode_result encode_none (uint32 *); | |
644 | uint32 decode_imm12b (uint32); | |
645 | xtensa_encode_result encode_imm12b (uint32 *); | |
646 | uint32 decode_r (uint32); | |
647 | xtensa_encode_result encode_r (uint32 *); | |
648 | uint32 decode_s (uint32); | |
649 | xtensa_encode_result encode_s (uint32 *); | |
650 | uint32 decode_t (uint32); | |
651 | xtensa_encode_result encode_t (uint32 *); | |
652 | uint32 decode_thi3 (uint32); | |
653 | xtensa_encode_result encode_thi3 (uint32 *); | |
654 | uint32 decode_sae4 (uint32); | |
655 | xtensa_encode_result encode_sae4 (uint32 *); | |
656 | uint32 decode_offset (uint32); | |
657 | xtensa_encode_result encode_offset (uint32 *); | |
658 | uint32 decode_imm7hi (uint32); | |
659 | xtensa_encode_result encode_imm7hi (uint32 *); | |
660 | uint32 decode_uimm4x16 (uint32); | |
661 | xtensa_encode_result encode_uimm4x16 (uint32 *); | |
662 | uint32 decode_simm12b (uint32); | |
663 | xtensa_encode_result encode_simm12b (uint32 *); | |
664 | uint32 decode_lsi4x4 (uint32); | |
665 | xtensa_encode_result encode_lsi4x4 (uint32 *); | |
666 | uint32 decode_z (uint32); | |
667 | xtensa_encode_result encode_z (uint32 *); | |
668 | uint32 decode_simm12 (uint32); | |
669 | xtensa_encode_result encode_simm12 (uint32 *); | |
670 | uint32 decode_sr (uint32); | |
671 | xtensa_encode_result encode_sr (uint32 *); | |
672 | uint32 decode_nimm4x2 (uint32); | |
673 | xtensa_encode_result encode_nimm4x2 (uint32 *); | |
674 | ||
675 | ||
676 | static const uint32 b4constu_table[] = { | |
677 | 32768, | |
678 | 65536, | |
679 | 2, | |
680 | 3, | |
681 | 4, | |
682 | 5, | |
683 | 6, | |
684 | 7, | |
685 | 8, | |
686 | 10, | |
687 | 12, | |
688 | 16, | |
689 | 32, | |
690 | 64, | |
691 | 128, | |
692 | 256 | |
693 | }; | |
694 | ||
695 | uint32 | |
696 | decode_b4constu (uint32 val) | |
697 | { | |
698 | val = b4constu_table[val]; | |
699 | return val; | |
700 | } | |
701 | ||
702 | xtensa_encode_result | |
703 | encode_b4constu (uint32 *valp) | |
704 | { | |
705 | uint32 val = *valp; | |
706 | unsigned i; | |
707 | for (i = 0; i < (1 << 4); i += 1) | |
708 | if (b4constu_table[i] == val) goto found; | |
709 | return xtensa_encode_result_not_in_table; | |
710 | found: | |
711 | val = i; | |
712 | *valp = val; | |
713 | return xtensa_encode_result_ok; | |
714 | } | |
715 | ||
716 | uint32 | |
717 | decode_simm8x256 (uint32 val) | |
718 | { | |
719 | val = (val ^ 0x80) - 0x80; | |
720 | val <<= 8; | |
721 | return val; | |
722 | } | |
723 | ||
724 | xtensa_encode_result | |
725 | encode_simm8x256 (uint32 *valp) | |
726 | { | |
727 | uint32 val = *valp; | |
728 | if ((val & ((1 << 8) - 1)) != 0) | |
729 | return xtensa_encode_result_align; | |
730 | val = (signed int) val >> 8; | |
731 | if (((val + (1 << 7)) >> 8) != 0) | |
732 | { | |
733 | if ((signed int) val > 0) | |
734 | return xtensa_encode_result_too_high; | |
735 | else | |
736 | return xtensa_encode_result_too_low; | |
737 | } | |
738 | *valp = val; | |
739 | return xtensa_encode_result_ok; | |
740 | } | |
741 | ||
742 | uint32 | |
743 | decode_soffset (uint32 val) | |
744 | { | |
745 | val = (val ^ 0x20000) - 0x20000; | |
746 | return val; | |
747 | } | |
748 | ||
749 | xtensa_encode_result | |
750 | encode_soffset (uint32 *valp) | |
751 | { | |
752 | uint32 val = *valp; | |
753 | if (((val + (1 << 17)) >> 18) != 0) | |
754 | { | |
755 | if ((signed int) val > 0) | |
756 | return xtensa_encode_result_too_high; | |
757 | else | |
758 | return xtensa_encode_result_too_low; | |
759 | } | |
760 | *valp = val; | |
761 | return xtensa_encode_result_ok; | |
762 | } | |
763 | ||
764 | uint32 | |
765 | decode_imm4 (uint32 val) | |
766 | { | |
767 | return val; | |
768 | } | |
769 | ||
770 | xtensa_encode_result | |
771 | encode_imm4 (uint32 *valp) | |
772 | { | |
773 | uint32 val = *valp; | |
774 | if ((val >> 4) != 0) | |
775 | return xtensa_encode_result_too_high; | |
776 | *valp = val; | |
777 | return xtensa_encode_result_ok; | |
778 | } | |
779 | ||
780 | uint32 | |
781 | decode_op0 (uint32 val) | |
782 | { | |
783 | return val; | |
784 | } | |
785 | ||
786 | xtensa_encode_result | |
787 | encode_op0 (uint32 *valp) | |
788 | { | |
789 | uint32 val = *valp; | |
790 | if ((val >> 4) != 0) | |
791 | return xtensa_encode_result_too_high; | |
792 | *valp = val; | |
793 | return xtensa_encode_result_ok; | |
794 | } | |
795 | ||
796 | uint32 | |
797 | decode_op1 (uint32 val) | |
798 | { | |
799 | return val; | |
800 | } | |
801 | ||
802 | xtensa_encode_result | |
803 | encode_op1 (uint32 *valp) | |
804 | { | |
805 | uint32 val = *valp; | |
806 | if ((val >> 4) != 0) | |
807 | return xtensa_encode_result_too_high; | |
808 | *valp = val; | |
809 | return xtensa_encode_result_ok; | |
810 | } | |
811 | ||
812 | uint32 | |
813 | decode_imm6 (uint32 val) | |
814 | { | |
815 | return val; | |
816 | } | |
817 | ||
818 | xtensa_encode_result | |
819 | encode_imm6 (uint32 *valp) | |
820 | { | |
821 | uint32 val = *valp; | |
822 | if ((val >> 6) != 0) | |
823 | return xtensa_encode_result_too_high; | |
824 | *valp = val; | |
825 | return xtensa_encode_result_ok; | |
826 | } | |
827 | ||
828 | uint32 | |
829 | decode_op2 (uint32 val) | |
830 | { | |
831 | return val; | |
832 | } | |
833 | ||
834 | xtensa_encode_result | |
835 | encode_op2 (uint32 *valp) | |
836 | { | |
837 | uint32 val = *valp; | |
838 | if ((val >> 4) != 0) | |
839 | return xtensa_encode_result_too_high; | |
840 | *valp = val; | |
841 | return xtensa_encode_result_ok; | |
842 | } | |
843 | ||
844 | uint32 | |
845 | decode_imm7 (uint32 val) | |
846 | { | |
847 | return val; | |
848 | } | |
849 | ||
850 | xtensa_encode_result | |
851 | encode_imm7 (uint32 *valp) | |
852 | { | |
853 | uint32 val = *valp; | |
854 | if ((val >> 7) != 0) | |
855 | return xtensa_encode_result_too_high; | |
856 | *valp = val; | |
857 | return xtensa_encode_result_ok; | |
858 | } | |
859 | ||
860 | uint32 | |
861 | decode_simm4 (uint32 val) | |
862 | { | |
863 | val = (val ^ 0x8) - 0x8; | |
864 | return val; | |
865 | } | |
866 | ||
867 | xtensa_encode_result | |
868 | encode_simm4 (uint32 *valp) | |
869 | { | |
870 | uint32 val = *valp; | |
871 | if (((val + (1 << 3)) >> 4) != 0) | |
872 | { | |
873 | if ((signed int) val > 0) | |
874 | return xtensa_encode_result_too_high; | |
875 | else | |
876 | return xtensa_encode_result_too_low; | |
877 | } | |
878 | *valp = val; | |
879 | return xtensa_encode_result_ok; | |
880 | } | |
881 | ||
882 | static const uint32 ai4const_table[] = { | |
883 | -1, | |
884 | 1, | |
885 | 2, | |
886 | 3, | |
887 | 4, | |
888 | 5, | |
889 | 6, | |
890 | 7, | |
891 | 8, | |
892 | 9, | |
893 | 10, | |
894 | 11, | |
895 | 12, | |
896 | 13, | |
897 | 14, | |
898 | 15 | |
899 | }; | |
900 | ||
901 | uint32 | |
902 | decode_ai4const (uint32 val) | |
903 | { | |
904 | val = ai4const_table[val]; | |
905 | return val; | |
906 | } | |
907 | ||
908 | xtensa_encode_result | |
909 | encode_ai4const (uint32 *valp) | |
910 | { | |
911 | uint32 val = *valp; | |
912 | unsigned i; | |
913 | for (i = 0; i < (1 << 4); i += 1) | |
914 | if (ai4const_table[i] == val) goto found; | |
915 | return xtensa_encode_result_not_in_table; | |
916 | found: | |
917 | val = i; | |
918 | *valp = val; | |
919 | return xtensa_encode_result_ok; | |
920 | } | |
921 | ||
922 | uint32 | |
923 | decode_imm8 (uint32 val) | |
924 | { | |
925 | return val; | |
926 | } | |
927 | ||
928 | xtensa_encode_result | |
929 | encode_imm8 (uint32 *valp) | |
930 | { | |
931 | uint32 val = *valp; | |
932 | if ((val >> 8) != 0) | |
933 | return xtensa_encode_result_too_high; | |
934 | *valp = val; | |
935 | return xtensa_encode_result_ok; | |
936 | } | |
937 | ||
938 | uint32 | |
939 | decode_sae (uint32 val) | |
940 | { | |
941 | return val; | |
942 | } | |
943 | ||
944 | xtensa_encode_result | |
945 | encode_sae (uint32 *valp) | |
946 | { | |
947 | uint32 val = *valp; | |
948 | if ((val >> 5) != 0) | |
949 | return xtensa_encode_result_too_high; | |
950 | *valp = val; | |
951 | return xtensa_encode_result_ok; | |
952 | } | |
953 | ||
954 | uint32 | |
955 | decode_imm7lo (uint32 val) | |
956 | { | |
957 | return val; | |
958 | } | |
959 | ||
960 | xtensa_encode_result | |
961 | encode_imm7lo (uint32 *valp) | |
962 | { | |
963 | uint32 val = *valp; | |
964 | if ((val >> 4) != 0) | |
965 | return xtensa_encode_result_too_high; | |
966 | *valp = val; | |
967 | return xtensa_encode_result_ok; | |
968 | } | |
969 | ||
970 | uint32 | |
971 | decode_simm7 (uint32 val) | |
972 | { | |
973 | if (val > 95) | |
974 | val |= -32; | |
975 | return val; | |
976 | } | |
977 | ||
978 | xtensa_encode_result | |
979 | encode_simm7 (uint32 *valp) | |
980 | { | |
981 | uint32 val = *valp; | |
982 | if ((signed int) val < -32) | |
983 | return xtensa_encode_result_too_low; | |
984 | if ((signed int) val > 95) | |
985 | return xtensa_encode_result_too_high; | |
986 | *valp = val; | |
987 | return xtensa_encode_result_ok; | |
988 | } | |
989 | ||
990 | uint32 | |
991 | decode_simm8 (uint32 val) | |
992 | { | |
993 | val = (val ^ 0x80) - 0x80; | |
994 | return val; | |
995 | } | |
996 | ||
997 | xtensa_encode_result | |
998 | encode_simm8 (uint32 *valp) | |
999 | { | |
1000 | uint32 val = *valp; | |
1001 | if (((val + (1 << 7)) >> 8) != 0) | |
1002 | { | |
1003 | if ((signed int) val > 0) | |
1004 | return xtensa_encode_result_too_high; | |
1005 | else | |
1006 | return xtensa_encode_result_too_low; | |
1007 | } | |
1008 | *valp = val; | |
1009 | return xtensa_encode_result_ok; | |
1010 | } | |
1011 | ||
1012 | uint32 | |
1013 | decode_uimm12x8 (uint32 val) | |
1014 | { | |
1015 | val <<= 3; | |
1016 | return val; | |
1017 | } | |
1018 | ||
1019 | xtensa_encode_result | |
1020 | encode_uimm12x8 (uint32 *valp) | |
1021 | { | |
1022 | uint32 val = *valp; | |
1023 | if ((val & ((1 << 3) - 1)) != 0) | |
1024 | return xtensa_encode_result_align; | |
1025 | val = (signed int) val >> 3; | |
1026 | if ((val >> 12) != 0) | |
1027 | return xtensa_encode_result_too_high; | |
1028 | *valp = val; | |
1029 | return xtensa_encode_result_ok; | |
1030 | } | |
1031 | ||
1032 | uint32 | |
1033 | decode_sal (uint32 val) | |
1034 | { | |
1035 | return val; | |
1036 | } | |
1037 | ||
1038 | xtensa_encode_result | |
1039 | encode_sal (uint32 *valp) | |
1040 | { | |
1041 | uint32 val = *valp; | |
1042 | if ((val >> 5) != 0) | |
1043 | return xtensa_encode_result_too_high; | |
1044 | *valp = val; | |
1045 | return xtensa_encode_result_ok; | |
1046 | } | |
1047 | ||
1048 | uint32 | |
1049 | decode_uimm6 (uint32 val) | |
1050 | { | |
1051 | return val; | |
1052 | } | |
1053 | ||
1054 | xtensa_encode_result | |
1055 | encode_uimm6 (uint32 *valp) | |
1056 | { | |
1057 | uint32 val = *valp; | |
1058 | if ((val >> 6) != 0) | |
1059 | return xtensa_encode_result_too_high; | |
1060 | *valp = val; | |
1061 | return xtensa_encode_result_ok; | |
1062 | } | |
1063 | ||
1064 | uint32 | |
1065 | decode_sas4 (uint32 val) | |
1066 | { | |
1067 | return val; | |
1068 | } | |
1069 | ||
1070 | xtensa_encode_result | |
1071 | encode_sas4 (uint32 *valp) | |
1072 | { | |
1073 | uint32 val = *valp; | |
1074 | if ((val >> 1) != 0) | |
1075 | return xtensa_encode_result_too_high; | |
1076 | *valp = val; | |
1077 | return xtensa_encode_result_ok; | |
1078 | } | |
1079 | ||
1080 | uint32 | |
1081 | decode_uimm8 (uint32 val) | |
1082 | { | |
1083 | return val; | |
1084 | } | |
1085 | ||
1086 | xtensa_encode_result | |
1087 | encode_uimm8 (uint32 *valp) | |
1088 | { | |
1089 | uint32 val = *valp; | |
1090 | if ((val >> 8) != 0) | |
1091 | return xtensa_encode_result_too_high; | |
1092 | *valp = val; | |
1093 | return xtensa_encode_result_ok; | |
1094 | } | |
1095 | ||
1096 | uint32 | |
1097 | decode_uimm16x4 (uint32 val) | |
1098 | { | |
1099 | val |= -1 << 16; | |
1100 | val <<= 2; | |
1101 | return val; | |
1102 | } | |
1103 | ||
1104 | xtensa_encode_result | |
1105 | encode_uimm16x4 (uint32 *valp) | |
1106 | { | |
1107 | uint32 val = *valp; | |
1108 | if ((val & ((1 << 2) - 1)) != 0) | |
1109 | return xtensa_encode_result_align; | |
1110 | val = (signed int) val >> 2; | |
1111 | if ((signed int) val >> 16 != -1) | |
1112 | { | |
1113 | if ((signed int) val >= 0) | |
1114 | return xtensa_encode_result_too_high; | |
1115 | else | |
1116 | return xtensa_encode_result_too_low; | |
1117 | } | |
1118 | *valp = val; | |
1119 | return xtensa_encode_result_ok; | |
1120 | } | |
1121 | ||
1122 | uint32 | |
1123 | decode_sar (uint32 val) | |
1124 | { | |
1125 | return val; | |
1126 | } | |
1127 | ||
1128 | xtensa_encode_result | |
1129 | encode_sar (uint32 *valp) | |
1130 | { | |
1131 | uint32 val = *valp; | |
1132 | if ((val >> 5) != 0) | |
1133 | return xtensa_encode_result_too_high; | |
1134 | *valp = val; | |
1135 | return xtensa_encode_result_ok; | |
1136 | } | |
1137 | ||
1138 | uint32 | |
1139 | decode_sa4 (uint32 val) | |
1140 | { | |
1141 | return val; | |
1142 | } | |
1143 | ||
1144 | xtensa_encode_result | |
1145 | encode_sa4 (uint32 *valp) | |
1146 | { | |
1147 | uint32 val = *valp; | |
1148 | if ((val >> 1) != 0) | |
1149 | return xtensa_encode_result_too_high; | |
1150 | *valp = val; | |
1151 | return xtensa_encode_result_ok; | |
1152 | } | |
1153 | ||
1154 | uint32 | |
1155 | decode_sas (uint32 val) | |
1156 | { | |
1157 | return val; | |
1158 | } | |
1159 | ||
1160 | xtensa_encode_result | |
1161 | encode_sas (uint32 *valp) | |
1162 | { | |
1163 | uint32 val = *valp; | |
1164 | if ((val >> 5) != 0) | |
1165 | return xtensa_encode_result_too_high; | |
1166 | *valp = val; | |
1167 | return xtensa_encode_result_ok; | |
1168 | } | |
1169 | ||
1170 | uint32 | |
1171 | decode_imm6hi (uint32 val) | |
1172 | { | |
1173 | return val; | |
1174 | } | |
1175 | ||
1176 | xtensa_encode_result | |
1177 | encode_imm6hi (uint32 *valp) | |
1178 | { | |
1179 | uint32 val = *valp; | |
1180 | if ((val >> 2) != 0) | |
1181 | return xtensa_encode_result_too_high; | |
1182 | *valp = val; | |
1183 | return xtensa_encode_result_ok; | |
1184 | } | |
1185 | ||
1186 | uint32 | |
1187 | decode_bbi (uint32 val) | |
1188 | { | |
1189 | return val; | |
1190 | } | |
1191 | ||
1192 | xtensa_encode_result | |
1193 | encode_bbi (uint32 *valp) | |
1194 | { | |
1195 | uint32 val = *valp; | |
1196 | if ((val >> 5) != 0) | |
1197 | return xtensa_encode_result_too_high; | |
1198 | *valp = val; | |
1199 | return xtensa_encode_result_ok; | |
1200 | } | |
1201 | ||
1202 | uint32 | |
1203 | decode_uimm8x2 (uint32 val) | |
1204 | { | |
1205 | val <<= 1; | |
1206 | return val; | |
1207 | } | |
1208 | ||
1209 | xtensa_encode_result | |
1210 | encode_uimm8x2 (uint32 *valp) | |
1211 | { | |
1212 | uint32 val = *valp; | |
1213 | if ((val & ((1 << 1) - 1)) != 0) | |
1214 | return xtensa_encode_result_align; | |
1215 | val = (signed int) val >> 1; | |
1216 | if ((val >> 8) != 0) | |
1217 | return xtensa_encode_result_too_high; | |
1218 | *valp = val; | |
1219 | return xtensa_encode_result_ok; | |
1220 | } | |
1221 | ||
1222 | uint32 | |
1223 | decode_uimm8x4 (uint32 val) | |
1224 | { | |
1225 | val <<= 2; | |
1226 | return val; | |
1227 | } | |
1228 | ||
1229 | xtensa_encode_result | |
1230 | encode_uimm8x4 (uint32 *valp) | |
1231 | { | |
1232 | uint32 val = *valp; | |
1233 | if ((val & ((1 << 2) - 1)) != 0) | |
1234 | return xtensa_encode_result_align; | |
1235 | val = (signed int) val >> 2; | |
1236 | if ((val >> 8) != 0) | |
1237 | return xtensa_encode_result_too_high; | |
1238 | *valp = val; | |
1239 | return xtensa_encode_result_ok; | |
1240 | } | |
1241 | ||
1242 | static const uint32 mip32const_table[] = { | |
1243 | 32, | |
1244 | 31, | |
1245 | 30, | |
1246 | 29, | |
1247 | 28, | |
1248 | 27, | |
1249 | 26, | |
1250 | 25, | |
1251 | 24, | |
1252 | 23, | |
1253 | 22, | |
1254 | 21, | |
1255 | 20, | |
1256 | 19, | |
1257 | 18, | |
1258 | 17, | |
1259 | 16, | |
1260 | 15, | |
1261 | 14, | |
1262 | 13, | |
1263 | 12, | |
1264 | 11, | |
1265 | 10, | |
1266 | 9, | |
1267 | 8, | |
1268 | 7, | |
1269 | 6, | |
1270 | 5, | |
1271 | 4, | |
1272 | 3, | |
1273 | 2, | |
1274 | 1 | |
1275 | }; | |
1276 | ||
1277 | uint32 | |
1278 | decode_msalp32 (uint32 val) | |
1279 | { | |
1280 | val = mip32const_table[val]; | |
1281 | return val; | |
1282 | } | |
1283 | ||
1284 | xtensa_encode_result | |
1285 | encode_msalp32 (uint32 *valp) | |
1286 | { | |
1287 | uint32 val = *valp; | |
1288 | unsigned i; | |
1289 | for (i = 0; i < (1 << 5); i += 1) | |
1290 | if (mip32const_table[i] == val) goto found; | |
1291 | return xtensa_encode_result_not_in_table; | |
1292 | found: | |
1293 | val = i; | |
1294 | *valp = val; | |
1295 | return xtensa_encode_result_ok; | |
1296 | } | |
1297 | ||
1298 | uint32 | |
1299 | decode_bbi4 (uint32 val) | |
1300 | { | |
1301 | return val; | |
1302 | } | |
1303 | ||
1304 | xtensa_encode_result | |
1305 | encode_bbi4 (uint32 *valp) | |
1306 | { | |
1307 | uint32 val = *valp; | |
1308 | if ((val >> 1) != 0) | |
1309 | return xtensa_encode_result_too_high; | |
1310 | *valp = val; | |
1311 | return xtensa_encode_result_ok; | |
1312 | } | |
1313 | ||
1314 | static const uint32 i4p1const_table[] = { | |
1315 | 1, | |
1316 | 2, | |
1317 | 3, | |
1318 | 4, | |
1319 | 5, | |
1320 | 6, | |
1321 | 7, | |
1322 | 8, | |
1323 | 9, | |
1324 | 10, | |
1325 | 11, | |
1326 | 12, | |
1327 | 13, | |
1328 | 14, | |
1329 | 15, | |
1330 | 16 | |
1331 | }; | |
1332 | ||
1333 | uint32 | |
1334 | decode_op2p1 (uint32 val) | |
1335 | { | |
1336 | val = i4p1const_table[val]; | |
1337 | return val; | |
1338 | } | |
1339 | ||
1340 | xtensa_encode_result | |
1341 | encode_op2p1 (uint32 *valp) | |
1342 | { | |
1343 | uint32 val = *valp; | |
1344 | unsigned i; | |
1345 | for (i = 0; i < (1 << 4); i += 1) | |
1346 | if (i4p1const_table[i] == val) goto found; | |
1347 | return xtensa_encode_result_not_in_table; | |
1348 | found: | |
1349 | val = i; | |
1350 | *valp = val; | |
1351 | return xtensa_encode_result_ok; | |
1352 | } | |
1353 | ||
1354 | uint32 | |
1355 | decode_soffsetx4 (uint32 val) | |
1356 | { | |
1357 | val = (val ^ 0x20000) - 0x20000; | |
1358 | val <<= 2; | |
1359 | return val; | |
1360 | } | |
1361 | ||
1362 | xtensa_encode_result | |
1363 | encode_soffsetx4 (uint32 *valp) | |
1364 | { | |
1365 | uint32 val = *valp; | |
1366 | if ((val & ((1 << 2) - 1)) != 0) | |
1367 | return xtensa_encode_result_align; | |
1368 | val = (signed int) val >> 2; | |
1369 | if (((val + (1 << 17)) >> 18) != 0) | |
1370 | { | |
1371 | if ((signed int) val > 0) | |
1372 | return xtensa_encode_result_too_high; | |
1373 | else | |
1374 | return xtensa_encode_result_too_low; | |
1375 | } | |
1376 | *valp = val; | |
1377 | return xtensa_encode_result_ok; | |
1378 | } | |
1379 | ||
1380 | uint32 | |
1381 | decode_imm6lo (uint32 val) | |
1382 | { | |
1383 | return val; | |
1384 | } | |
1385 | ||
1386 | xtensa_encode_result | |
1387 | encode_imm6lo (uint32 *valp) | |
1388 | { | |
1389 | uint32 val = *valp; | |
1390 | if ((val >> 4) != 0) | |
1391 | return xtensa_encode_result_too_high; | |
1392 | *valp = val; | |
1393 | return xtensa_encode_result_ok; | |
1394 | } | |
1395 | ||
1396 | uint32 | |
1397 | decode_imm12 (uint32 val) | |
1398 | { | |
1399 | return val; | |
1400 | } | |
1401 | ||
1402 | xtensa_encode_result | |
1403 | encode_imm12 (uint32 *valp) | |
1404 | { | |
1405 | uint32 val = *valp; | |
1406 | if ((val >> 12) != 0) | |
1407 | return xtensa_encode_result_too_high; | |
1408 | *valp = val; | |
1409 | return xtensa_encode_result_ok; | |
1410 | } | |
1411 | ||
1412 | static const uint32 b4const_table[] = { | |
1413 | -1, | |
1414 | 1, | |
1415 | 2, | |
1416 | 3, | |
1417 | 4, | |
1418 | 5, | |
1419 | 6, | |
1420 | 7, | |
1421 | 8, | |
1422 | 10, | |
1423 | 12, | |
1424 | 16, | |
1425 | 32, | |
1426 | 64, | |
1427 | 128, | |
1428 | 256 | |
1429 | }; | |
1430 | ||
1431 | uint32 | |
1432 | decode_b4const (uint32 val) | |
1433 | { | |
1434 | val = b4const_table[val]; | |
1435 | return val; | |
1436 | } | |
1437 | ||
1438 | xtensa_encode_result | |
1439 | encode_b4const (uint32 *valp) | |
1440 | { | |
1441 | uint32 val = *valp; | |
1442 | unsigned i; | |
1443 | for (i = 0; i < (1 << 4); i += 1) | |
1444 | if (b4const_table[i] == val) goto found; | |
1445 | return xtensa_encode_result_not_in_table; | |
1446 | found: | |
1447 | val = i; | |
1448 | *valp = val; | |
1449 | return xtensa_encode_result_ok; | |
1450 | } | |
1451 | ||
1452 | uint32 | |
1453 | decode_i (uint32 val) | |
1454 | { | |
1455 | return val; | |
1456 | } | |
1457 | ||
1458 | xtensa_encode_result | |
1459 | encode_i (uint32 *valp) | |
1460 | { | |
1461 | uint32 val = *valp; | |
1462 | if ((val >> 1) != 0) | |
1463 | return xtensa_encode_result_too_high; | |
1464 | *valp = val; | |
1465 | return xtensa_encode_result_ok; | |
1466 | } | |
1467 | ||
1468 | uint32 | |
1469 | decode_imm16 (uint32 val) | |
1470 | { | |
1471 | return val; | |
1472 | } | |
1473 | ||
1474 | xtensa_encode_result | |
1475 | encode_imm16 (uint32 *valp) | |
1476 | { | |
1477 | uint32 val = *valp; | |
1478 | if ((val >> 16) != 0) | |
1479 | return xtensa_encode_result_too_high; | |
1480 | *valp = val; | |
1481 | return xtensa_encode_result_ok; | |
1482 | } | |
1483 | ||
1484 | uint32 | |
1485 | decode_mn (uint32 val) | |
1486 | { | |
1487 | return val; | |
1488 | } | |
1489 | ||
1490 | xtensa_encode_result | |
1491 | encode_mn (uint32 *valp) | |
1492 | { | |
1493 | uint32 val = *valp; | |
1494 | if ((val >> 4) != 0) | |
1495 | return xtensa_encode_result_too_high; | |
1496 | *valp = val; | |
1497 | return xtensa_encode_result_ok; | |
1498 | } | |
1499 | ||
1500 | uint32 | |
1501 | decode_m (uint32 val) | |
1502 | { | |
1503 | return val; | |
1504 | } | |
1505 | ||
1506 | xtensa_encode_result | |
1507 | encode_m (uint32 *valp) | |
1508 | { | |
1509 | uint32 val = *valp; | |
1510 | if ((val >> 2) != 0) | |
1511 | return xtensa_encode_result_too_high; | |
1512 | *valp = val; | |
1513 | return xtensa_encode_result_ok; | |
1514 | } | |
1515 | ||
1516 | uint32 | |
1517 | decode_n (uint32 val) | |
1518 | { | |
1519 | return val; | |
1520 | } | |
1521 | ||
1522 | xtensa_encode_result | |
1523 | encode_n (uint32 *valp) | |
1524 | { | |
1525 | uint32 val = *valp; | |
1526 | if ((val >> 2) != 0) | |
1527 | return xtensa_encode_result_too_high; | |
1528 | *valp = val; | |
1529 | return xtensa_encode_result_ok; | |
1530 | } | |
1531 | ||
1532 | uint32 | |
1533 | decode_none (uint32 val) | |
1534 | { | |
1535 | return val; | |
1536 | } | |
1537 | ||
1538 | xtensa_encode_result | |
1539 | encode_none (uint32 *valp) | |
1540 | { | |
1541 | uint32 val = *valp; | |
1542 | if ((val >> 0) != 0) | |
1543 | return xtensa_encode_result_too_high; | |
1544 | *valp = val; | |
1545 | return xtensa_encode_result_ok; | |
1546 | } | |
1547 | ||
1548 | uint32 | |
1549 | decode_imm12b (uint32 val) | |
1550 | { | |
1551 | return val; | |
1552 | } | |
1553 | ||
1554 | xtensa_encode_result | |
1555 | encode_imm12b (uint32 *valp) | |
1556 | { | |
1557 | uint32 val = *valp; | |
1558 | if ((val >> 12) != 0) | |
1559 | return xtensa_encode_result_too_high; | |
1560 | *valp = val; | |
1561 | return xtensa_encode_result_ok; | |
1562 | } | |
1563 | ||
1564 | uint32 | |
1565 | decode_r (uint32 val) | |
1566 | { | |
1567 | return val; | |
1568 | } | |
1569 | ||
1570 | xtensa_encode_result | |
1571 | encode_r (uint32 *valp) | |
1572 | { | |
1573 | uint32 val = *valp; | |
1574 | if ((val >> 4) != 0) | |
1575 | return xtensa_encode_result_too_high; | |
1576 | *valp = val; | |
1577 | return xtensa_encode_result_ok; | |
1578 | } | |
1579 | ||
1580 | uint32 | |
1581 | decode_s (uint32 val) | |
1582 | { | |
1583 | return val; | |
1584 | } | |
1585 | ||
1586 | xtensa_encode_result | |
1587 | encode_s (uint32 *valp) | |
1588 | { | |
1589 | uint32 val = *valp; | |
1590 | if ((val >> 4) != 0) | |
1591 | return xtensa_encode_result_too_high; | |
1592 | *valp = val; | |
1593 | return xtensa_encode_result_ok; | |
1594 | } | |
1595 | ||
1596 | uint32 | |
1597 | decode_t (uint32 val) | |
1598 | { | |
1599 | return val; | |
1600 | } | |
1601 | ||
1602 | xtensa_encode_result | |
1603 | encode_t (uint32 *valp) | |
1604 | { | |
1605 | uint32 val = *valp; | |
1606 | if ((val >> 4) != 0) | |
1607 | return xtensa_encode_result_too_high; | |
1608 | *valp = val; | |
1609 | return xtensa_encode_result_ok; | |
1610 | } | |
1611 | ||
1612 | uint32 | |
1613 | decode_thi3 (uint32 val) | |
1614 | { | |
1615 | return val; | |
1616 | } | |
1617 | ||
1618 | xtensa_encode_result | |
1619 | encode_thi3 (uint32 *valp) | |
1620 | { | |
1621 | uint32 val = *valp; | |
1622 | if ((val >> 3) != 0) | |
1623 | return xtensa_encode_result_too_high; | |
1624 | *valp = val; | |
1625 | return xtensa_encode_result_ok; | |
1626 | } | |
1627 | ||
1628 | uint32 | |
1629 | decode_sae4 (uint32 val) | |
1630 | { | |
1631 | return val; | |
1632 | } | |
1633 | ||
1634 | xtensa_encode_result | |
1635 | encode_sae4 (uint32 *valp) | |
1636 | { | |
1637 | uint32 val = *valp; | |
1638 | if ((val >> 1) != 0) | |
1639 | return xtensa_encode_result_too_high; | |
1640 | *valp = val; | |
1641 | return xtensa_encode_result_ok; | |
1642 | } | |
1643 | ||
1644 | uint32 | |
1645 | decode_offset (uint32 val) | |
1646 | { | |
1647 | return val; | |
1648 | } | |
1649 | ||
1650 | xtensa_encode_result | |
1651 | encode_offset (uint32 *valp) | |
1652 | { | |
1653 | uint32 val = *valp; | |
1654 | if ((val >> 18) != 0) | |
1655 | return xtensa_encode_result_too_high; | |
1656 | *valp = val; | |
1657 | return xtensa_encode_result_ok; | |
1658 | } | |
1659 | ||
1660 | uint32 | |
1661 | decode_imm7hi (uint32 val) | |
1662 | { | |
1663 | return val; | |
1664 | } | |
1665 | ||
1666 | xtensa_encode_result | |
1667 | encode_imm7hi (uint32 *valp) | |
1668 | { | |
1669 | uint32 val = *valp; | |
1670 | if ((val >> 3) != 0) | |
1671 | return xtensa_encode_result_too_high; | |
1672 | *valp = val; | |
1673 | return xtensa_encode_result_ok; | |
1674 | } | |
1675 | ||
1676 | uint32 | |
1677 | decode_uimm4x16 (uint32 val) | |
1678 | { | |
1679 | val <<= 4; | |
1680 | return val; | |
1681 | } | |
1682 | ||
1683 | xtensa_encode_result | |
1684 | encode_uimm4x16 (uint32 *valp) | |
1685 | { | |
1686 | uint32 val = *valp; | |
1687 | if ((val & ((1 << 4) - 1)) != 0) | |
1688 | return xtensa_encode_result_align; | |
1689 | val = (signed int) val >> 4; | |
1690 | if ((val >> 4) != 0) | |
1691 | return xtensa_encode_result_too_high; | |
1692 | *valp = val; | |
1693 | return xtensa_encode_result_ok; | |
1694 | } | |
1695 | ||
1696 | uint32 | |
1697 | decode_simm12b (uint32 val) | |
1698 | { | |
1699 | val = (val ^ 0x800) - 0x800; | |
1700 | return val; | |
1701 | } | |
1702 | ||
1703 | xtensa_encode_result | |
1704 | encode_simm12b (uint32 *valp) | |
1705 | { | |
1706 | uint32 val = *valp; | |
1707 | if (((val + (1 << 11)) >> 12) != 0) | |
1708 | { | |
1709 | if ((signed int) val > 0) | |
1710 | return xtensa_encode_result_too_high; | |
1711 | else | |
1712 | return xtensa_encode_result_too_low; | |
1713 | } | |
1714 | *valp = val; | |
1715 | return xtensa_encode_result_ok; | |
1716 | } | |
1717 | ||
1718 | uint32 | |
1719 | decode_lsi4x4 (uint32 val) | |
1720 | { | |
1721 | val <<= 2; | |
1722 | return val; | |
1723 | } | |
1724 | ||
1725 | xtensa_encode_result | |
1726 | encode_lsi4x4 (uint32 *valp) | |
1727 | { | |
1728 | uint32 val = *valp; | |
1729 | if ((val & ((1 << 2) - 1)) != 0) | |
1730 | return xtensa_encode_result_align; | |
1731 | val = (signed int) val >> 2; | |
1732 | if ((val >> 4) != 0) | |
1733 | return xtensa_encode_result_too_high; | |
1734 | *valp = val; | |
1735 | return xtensa_encode_result_ok; | |
1736 | } | |
1737 | ||
1738 | uint32 | |
1739 | decode_z (uint32 val) | |
1740 | { | |
1741 | return val; | |
1742 | } | |
1743 | ||
1744 | xtensa_encode_result | |
1745 | encode_z (uint32 *valp) | |
1746 | { | |
1747 | uint32 val = *valp; | |
1748 | if ((val >> 1) != 0) | |
1749 | return xtensa_encode_result_too_high; | |
1750 | *valp = val; | |
1751 | return xtensa_encode_result_ok; | |
1752 | } | |
1753 | ||
1754 | uint32 | |
1755 | decode_simm12 (uint32 val) | |
1756 | { | |
1757 | val = (val ^ 0x800) - 0x800; | |
1758 | return val; | |
1759 | } | |
1760 | ||
1761 | xtensa_encode_result | |
1762 | encode_simm12 (uint32 *valp) | |
1763 | { | |
1764 | uint32 val = *valp; | |
1765 | if (((val + (1 << 11)) >> 12) != 0) | |
1766 | { | |
1767 | if ((signed int) val > 0) | |
1768 | return xtensa_encode_result_too_high; | |
1769 | else | |
1770 | return xtensa_encode_result_too_low; | |
1771 | } | |
1772 | *valp = val; | |
1773 | return xtensa_encode_result_ok; | |
1774 | } | |
1775 | ||
1776 | uint32 | |
1777 | decode_sr (uint32 val) | |
1778 | { | |
1779 | return val; | |
1780 | } | |
1781 | ||
1782 | xtensa_encode_result | |
1783 | encode_sr (uint32 *valp) | |
1784 | { | |
1785 | uint32 val = *valp; | |
1786 | if ((val >> 8) != 0) | |
1787 | return xtensa_encode_result_too_high; | |
1788 | *valp = val; | |
1789 | return xtensa_encode_result_ok; | |
1790 | } | |
1791 | ||
1792 | uint32 | |
1793 | decode_nimm4x2 (uint32 val) | |
1794 | { | |
1795 | val |= -1 << 4; | |
1796 | val <<= 2; | |
1797 | return val; | |
1798 | } | |
1799 | ||
1800 | xtensa_encode_result | |
1801 | encode_nimm4x2 (uint32 *valp) | |
1802 | { | |
1803 | uint32 val = *valp; | |
1804 | if ((val & ((1 << 2) - 1)) != 0) | |
1805 | return xtensa_encode_result_align; | |
1806 | val = (signed int) val >> 2; | |
1807 | if ((signed int) val >> 4 != -1) | |
1808 | { | |
1809 | if ((signed int) val >= 0) | |
1810 | return xtensa_encode_result_too_high; | |
1811 | else | |
1812 | return xtensa_encode_result_too_low; | |
1813 | } | |
1814 | *valp = val; | |
1815 | return xtensa_encode_result_ok; | |
1816 | } | |
1817 | ||
1818 | ||
1819 | ||
1820 | uint32 do_reloc_l (uint32, uint32); | |
1821 | uint32 undo_reloc_l (uint32, uint32); | |
1822 | uint32 do_reloc_L (uint32, uint32); | |
1823 | uint32 undo_reloc_L (uint32, uint32); | |
1824 | uint32 do_reloc_r (uint32, uint32); | |
1825 | uint32 undo_reloc_r (uint32, uint32); | |
1826 | ||
1827 | ||
1828 | uint32 | |
1829 | do_reloc_l (uint32 addr, uint32 pc) | |
1830 | { | |
1831 | return addr - pc - 4; | |
1832 | } | |
1833 | ||
1834 | uint32 | |
1835 | undo_reloc_l (uint32 offset, uint32 pc) | |
1836 | { | |
1837 | return pc + offset + 4; | |
1838 | } | |
1839 | ||
1840 | uint32 | |
1841 | do_reloc_L (uint32 addr, uint32 pc) | |
1842 | { | |
1843 | return addr - (pc & -4) - 4; | |
1844 | } | |
1845 | ||
1846 | uint32 | |
1847 | undo_reloc_L (uint32 offset, uint32 pc) | |
1848 | { | |
1849 | return (pc & -4) + offset + 4; | |
1850 | } | |
1851 | ||
1852 | uint32 | |
1853 | do_reloc_r (uint32 addr, uint32 pc) | |
1854 | { | |
1855 | return addr - ((pc+3) & -4); | |
1856 | } | |
1857 | ||
1858 | uint32 | |
1859 | undo_reloc_r (uint32 offset, uint32 pc) | |
1860 | { | |
1861 | return ((pc+3) & -4) + offset; | |
1862 | } | |
1863 | ||
1864 | static xtensa_operand_internal iib4const_operand = { | |
1865 | "i", | |
1866 | '<', | |
1867 | 0, | |
1868 | get_r_field, | |
1869 | set_r_field, | |
1870 | encode_b4const, | |
1871 | decode_b4const, | |
1872 | 0, | |
1873 | 0 | |
1874 | }; | |
1875 | ||
1876 | static xtensa_operand_internal iiuimm8_operand = { | |
1877 | "i", | |
1878 | '<', | |
1879 | 0, | |
1880 | get_imm8_field, | |
1881 | set_imm8_field, | |
1882 | encode_uimm8, | |
1883 | decode_uimm8, | |
1884 | 0, | |
1885 | 0 | |
1886 | }; | |
1887 | ||
1888 | static xtensa_operand_internal lisoffsetx4_operand = { | |
1889 | "L", | |
1890 | '<', | |
1891 | 1, | |
1892 | get_offset_field, | |
1893 | set_offset_field, | |
1894 | encode_soffsetx4, | |
1895 | decode_soffsetx4, | |
1896 | do_reloc_L, | |
1897 | undo_reloc_L, | |
1898 | }; | |
1899 | ||
1900 | static xtensa_operand_internal iisimm8x256_operand = { | |
1901 | "i", | |
1902 | '<', | |
1903 | 0, | |
1904 | get_imm8_field, | |
1905 | set_imm8_field, | |
1906 | encode_simm8x256, | |
1907 | decode_simm8x256, | |
1908 | 0, | |
1909 | 0 | |
1910 | }; | |
1911 | ||
1912 | static xtensa_operand_internal lisimm12_operand = { | |
1913 | "l", | |
1914 | '<', | |
1915 | 1, | |
1916 | get_imm12_field, | |
1917 | set_imm12_field, | |
1918 | encode_simm12, | |
1919 | decode_simm12, | |
1920 | do_reloc_l, | |
1921 | undo_reloc_l, | |
1922 | }; | |
1923 | ||
1924 | static xtensa_operand_internal iiop2p1_operand = { | |
1925 | "i", | |
1926 | '<', | |
1927 | 0, | |
1928 | get_op2_field, | |
1929 | set_op2_field, | |
1930 | encode_op2p1, | |
1931 | decode_op2p1, | |
1932 | 0, | |
1933 | 0 | |
1934 | }; | |
1935 | ||
1936 | static xtensa_operand_internal iisae_operand = { | |
1937 | "i", | |
1938 | '<', | |
1939 | 0, | |
1940 | get_sae_field, | |
1941 | set_sae_field, | |
1942 | encode_sae, | |
1943 | decode_sae, | |
1944 | 0, | |
1945 | 0 | |
1946 | }; | |
1947 | ||
1948 | static xtensa_operand_internal iis_operand = { | |
1949 | "i", | |
1950 | '<', | |
1951 | 0, | |
1952 | get_s_field, | |
1953 | set_s_field, | |
1954 | encode_s, | |
1955 | decode_s, | |
1956 | 0, | |
1957 | 0 | |
1958 | }; | |
1959 | ||
1960 | static xtensa_operand_internal iit_operand = { | |
1961 | "i", | |
1962 | '<', | |
1963 | 0, | |
1964 | get_t_field, | |
1965 | set_t_field, | |
1966 | encode_t, | |
1967 | decode_t, | |
1968 | 0, | |
1969 | 0 | |
1970 | }; | |
1971 | ||
1972 | static xtensa_operand_internal iisimm12b_operand = { | |
1973 | "i", | |
1974 | '<', | |
1975 | 0, | |
1976 | get_imm12b_field, | |
1977 | set_imm12b_field, | |
1978 | encode_simm12b, | |
1979 | decode_simm12b, | |
1980 | 0, | |
1981 | 0 | |
1982 | }; | |
1983 | ||
1984 | static xtensa_operand_internal iinimm4x2_operand = { | |
1985 | "i", | |
1986 | '<', | |
1987 | 0, | |
1988 | get_imm4_field, | |
1989 | set_imm4_field, | |
1990 | encode_nimm4x2, | |
1991 | decode_nimm4x2, | |
1992 | 0, | |
1993 | 0 | |
1994 | }; | |
1995 | ||
1996 | static xtensa_operand_internal iiuimm4x16_operand = { | |
1997 | "i", | |
1998 | '<', | |
1999 | 0, | |
2000 | get_op2_field, | |
2001 | set_op2_field, | |
2002 | encode_uimm4x16, | |
2003 | decode_uimm4x16, | |
2004 | 0, | |
2005 | 0 | |
2006 | }; | |
2007 | ||
2008 | static xtensa_operand_internal abs_operand = { | |
2009 | "a", | |
2010 | '=', | |
2011 | 0, | |
2012 | get_s_field, | |
2013 | set_s_field, | |
2014 | encode_s, | |
2015 | decode_s, | |
2016 | 0, | |
2017 | 0 | |
2018 | }; | |
2019 | ||
2020 | static xtensa_operand_internal iisar_operand = { | |
2021 | "i", | |
2022 | '<', | |
2023 | 0, | |
2024 | get_sar_field, | |
2025 | set_sar_field, | |
2026 | encode_sar, | |
2027 | decode_sar, | |
2028 | 0, | |
2029 | 0 | |
2030 | }; | |
2031 | ||
2032 | static xtensa_operand_internal abt_operand = { | |
2033 | "a", | |
2034 | '=', | |
2035 | 0, | |
2036 | get_t_field, | |
2037 | set_t_field, | |
2038 | encode_t, | |
2039 | decode_t, | |
2040 | 0, | |
2041 | 0 | |
2042 | }; | |
2043 | ||
2044 | static xtensa_operand_internal iisas_operand = { | |
2045 | "i", | |
2046 | '<', | |
2047 | 0, | |
2048 | get_sas_field, | |
2049 | set_sas_field, | |
2050 | encode_sas, | |
2051 | decode_sas, | |
2052 | 0, | |
2053 | 0 | |
2054 | }; | |
2055 | ||
2056 | static xtensa_operand_internal amr_operand = { | |
2057 | "a", | |
2058 | '=', | |
2059 | 0, | |
2060 | get_r_field, | |
2061 | set_r_field, | |
2062 | encode_r, | |
2063 | decode_r, | |
2064 | 0, | |
2065 | 0 | |
2066 | }; | |
2067 | ||
2068 | static xtensa_operand_internal iib4constu_operand = { | |
2069 | "i", | |
2070 | '<', | |
2071 | 0, | |
2072 | get_r_field, | |
2073 | set_r_field, | |
2074 | encode_b4constu, | |
2075 | decode_b4constu, | |
2076 | 0, | |
2077 | 0 | |
2078 | }; | |
2079 | ||
2080 | static xtensa_operand_internal iisr_operand = { | |
2081 | "i", | |
2082 | '<', | |
2083 | 0, | |
2084 | get_sr_field, | |
2085 | set_sr_field, | |
2086 | encode_sr, | |
2087 | decode_sr, | |
2088 | 0, | |
2089 | 0 | |
2090 | }; | |
2091 | ||
2092 | static xtensa_operand_internal iibbi_operand = { | |
2093 | "i", | |
2094 | '<', | |
2095 | 0, | |
2096 | get_bbi_field, | |
2097 | set_bbi_field, | |
2098 | encode_bbi, | |
2099 | decode_bbi, | |
2100 | 0, | |
2101 | 0 | |
2102 | }; | |
2103 | ||
2104 | static xtensa_operand_internal iiai4const_operand = { | |
2105 | "i", | |
2106 | '<', | |
2107 | 0, | |
2108 | get_t_field, | |
2109 | set_t_field, | |
2110 | encode_ai4const, | |
2111 | decode_ai4const, | |
2112 | 0, | |
2113 | 0 | |
2114 | }; | |
2115 | ||
2116 | static xtensa_operand_internal iiuimm12x8_operand = { | |
2117 | "i", | |
2118 | '<', | |
2119 | 0, | |
2120 | get_imm12_field, | |
2121 | set_imm12_field, | |
2122 | encode_uimm12x8, | |
2123 | decode_uimm12x8, | |
2124 | 0, | |
2125 | 0 | |
2126 | }; | |
2127 | ||
2128 | static xtensa_operand_internal riuimm16x4_operand = { | |
2129 | "r", | |
2130 | '<', | |
2131 | 1, | |
2132 | get_imm16_field, | |
2133 | set_imm16_field, | |
2134 | encode_uimm16x4, | |
2135 | decode_uimm16x4, | |
2136 | do_reloc_r, | |
2137 | undo_reloc_r, | |
2138 | }; | |
2139 | ||
2140 | static xtensa_operand_internal lisimm8_operand = { | |
2141 | "l", | |
2142 | '<', | |
2143 | 1, | |
2144 | get_imm8_field, | |
2145 | set_imm8_field, | |
2146 | encode_simm8, | |
2147 | decode_simm8, | |
2148 | do_reloc_l, | |
2149 | undo_reloc_l, | |
2150 | }; | |
2151 | ||
2152 | static xtensa_operand_internal iilsi4x4_operand = { | |
2153 | "i", | |
2154 | '<', | |
2155 | 0, | |
2156 | get_r_field, | |
2157 | set_r_field, | |
2158 | encode_lsi4x4, | |
2159 | decode_lsi4x4, | |
2160 | 0, | |
2161 | 0 | |
2162 | }; | |
2163 | ||
2164 | static xtensa_operand_internal iiuimm8x2_operand = { | |
2165 | "i", | |
2166 | '<', | |
2167 | 0, | |
2168 | get_imm8_field, | |
2169 | set_imm8_field, | |
2170 | encode_uimm8x2, | |
2171 | decode_uimm8x2, | |
2172 | 0, | |
2173 | 0 | |
2174 | }; | |
2175 | ||
2176 | static xtensa_operand_internal iisimm4_operand = { | |
2177 | "i", | |
2178 | '<', | |
2179 | 0, | |
2180 | get_mn_field, | |
2181 | set_mn_field, | |
2182 | encode_simm4, | |
2183 | decode_simm4, | |
2184 | 0, | |
2185 | 0 | |
2186 | }; | |
2187 | ||
2188 | static xtensa_operand_internal iimsalp32_operand = { | |
2189 | "i", | |
2190 | '<', | |
2191 | 0, | |
2192 | get_sal_field, | |
2193 | set_sal_field, | |
2194 | encode_msalp32, | |
2195 | decode_msalp32, | |
2196 | 0, | |
2197 | 0 | |
2198 | }; | |
2199 | ||
2200 | static xtensa_operand_internal liuimm6_operand = { | |
2201 | "l", | |
2202 | '<', | |
2203 | 1, | |
2204 | get_imm6_field, | |
2205 | set_imm6_field, | |
2206 | encode_uimm6, | |
2207 | decode_uimm6, | |
2208 | do_reloc_l, | |
2209 | undo_reloc_l, | |
2210 | }; | |
2211 | ||
2212 | static xtensa_operand_internal iiuimm8x4_operand = { | |
2213 | "i", | |
2214 | '<', | |
2215 | 0, | |
2216 | get_imm8_field, | |
2217 | set_imm8_field, | |
2218 | encode_uimm8x4, | |
2219 | decode_uimm8x4, | |
2220 | 0, | |
2221 | 0 | |
2222 | }; | |
2223 | ||
2224 | static xtensa_operand_internal lisoffset_operand = { | |
2225 | "l", | |
2226 | '<', | |
2227 | 1, | |
2228 | get_offset_field, | |
2229 | set_offset_field, | |
2230 | encode_soffset, | |
2231 | decode_soffset, | |
2232 | do_reloc_l, | |
2233 | undo_reloc_l, | |
2234 | }; | |
2235 | ||
2236 | static xtensa_operand_internal iisimm7_operand = { | |
2237 | "i", | |
2238 | '<', | |
2239 | 0, | |
2240 | get_imm7_field, | |
2241 | set_imm7_field, | |
2242 | encode_simm7, | |
2243 | decode_simm7, | |
2244 | 0, | |
2245 | 0 | |
2246 | }; | |
2247 | ||
2248 | static xtensa_operand_internal ais_operand = { | |
2249 | "a", | |
2250 | '<', | |
2251 | 0, | |
2252 | get_s_field, | |
2253 | set_s_field, | |
2254 | encode_s, | |
2255 | decode_s, | |
2256 | 0, | |
2257 | 0 | |
2258 | }; | |
2259 | ||
2260 | static xtensa_operand_internal liuimm8_operand = { | |
2261 | "l", | |
2262 | '<', | |
2263 | 1, | |
2264 | get_imm8_field, | |
2265 | set_imm8_field, | |
2266 | encode_uimm8, | |
2267 | decode_uimm8, | |
2268 | do_reloc_l, | |
2269 | undo_reloc_l, | |
2270 | }; | |
2271 | ||
2272 | static xtensa_operand_internal ait_operand = { | |
2273 | "a", | |
2274 | '<', | |
2275 | 0, | |
2276 | get_t_field, | |
2277 | set_t_field, | |
2278 | encode_t, | |
2279 | decode_t, | |
2280 | 0, | |
2281 | 0 | |
2282 | }; | |
2283 | ||
2284 | static xtensa_operand_internal iisimm8_operand = { | |
2285 | "i", | |
2286 | '<', | |
2287 | 0, | |
2288 | get_imm8_field, | |
2289 | set_imm8_field, | |
2290 | encode_simm8, | |
2291 | decode_simm8, | |
2292 | 0, | |
2293 | 0 | |
2294 | }; | |
2295 | ||
2296 | static xtensa_operand_internal aor_operand = { | |
2297 | "a", | |
2298 | '>', | |
2299 | 0, | |
2300 | get_r_field, | |
2301 | set_r_field, | |
2302 | encode_r, | |
2303 | decode_r, | |
2304 | 0, | |
2305 | 0 | |
2306 | }; | |
2307 | ||
2308 | static xtensa_operand_internal aos_operand = { | |
2309 | "a", | |
2310 | '>', | |
2311 | 0, | |
2312 | get_s_field, | |
2313 | set_s_field, | |
2314 | encode_s, | |
2315 | decode_s, | |
2316 | 0, | |
2317 | 0 | |
2318 | }; | |
2319 | ||
2320 | static xtensa_operand_internal aot_operand = { | |
2321 | "a", | |
2322 | '>', | |
2323 | 0, | |
2324 | get_t_field, | |
2325 | set_t_field, | |
2326 | encode_t, | |
2327 | decode_t, | |
2328 | 0, | |
2329 | 0 | |
2330 | }; | |
2331 | ||
2332 | static xtensa_iclass_internal nopn_iclass = { | |
2333 | 0, | |
2334 | 0 | |
2335 | }; | |
2336 | ||
2337 | static xtensa_operand_internal *movi_operand_list[] = { | |
2338 | &aot_operand, | |
2339 | &iisimm12b_operand | |
2340 | }; | |
2341 | ||
2342 | static xtensa_iclass_internal movi_iclass = { | |
2343 | 2, | |
2344 | &movi_operand_list[0] | |
2345 | }; | |
2346 | ||
2347 | static xtensa_operand_internal *bsi8u_operand_list[] = { | |
2348 | &ais_operand, | |
2349 | &iib4constu_operand, | |
2350 | &lisimm8_operand | |
2351 | }; | |
2352 | ||
2353 | static xtensa_iclass_internal bsi8u_iclass = { | |
2354 | 3, | |
2355 | &bsi8u_operand_list[0] | |
2356 | }; | |
2357 | ||
2358 | static xtensa_operand_internal *itlb_operand_list[] = { | |
2359 | &ais_operand | |
2360 | }; | |
2361 | ||
2362 | static xtensa_iclass_internal itlb_iclass = { | |
2363 | 1, | |
2364 | &itlb_operand_list[0] | |
2365 | }; | |
2366 | ||
2367 | static xtensa_operand_internal *shiftst_operand_list[] = { | |
2368 | &aor_operand, | |
2369 | &ais_operand, | |
2370 | &ait_operand | |
2371 | }; | |
2372 | ||
2373 | static xtensa_iclass_internal shiftst_iclass = { | |
2374 | 3, | |
2375 | &shiftst_operand_list[0] | |
2376 | }; | |
2377 | ||
2378 | static xtensa_operand_internal *l32r_operand_list[] = { | |
2379 | &aot_operand, | |
2380 | &riuimm16x4_operand | |
2381 | }; | |
2382 | ||
2383 | static xtensa_iclass_internal l32r_iclass = { | |
2384 | 2, | |
2385 | &l32r_operand_list[0] | |
2386 | }; | |
2387 | ||
2388 | static xtensa_iclass_internal rfe_iclass = { | |
2389 | 0, | |
2390 | 0 | |
2391 | }; | |
2392 | ||
2393 | static xtensa_operand_internal *wait_operand_list[] = { | |
2394 | &iis_operand | |
2395 | }; | |
2396 | ||
2397 | static xtensa_iclass_internal wait_iclass = { | |
2398 | 1, | |
2399 | &wait_operand_list[0] | |
2400 | }; | |
2401 | ||
2402 | static xtensa_operand_internal *rfi_operand_list[] = { | |
2403 | &iis_operand | |
2404 | }; | |
2405 | ||
2406 | static xtensa_iclass_internal rfi_iclass = { | |
2407 | 1, | |
2408 | &rfi_operand_list[0] | |
2409 | }; | |
2410 | ||
2411 | static xtensa_operand_internal *movz_operand_list[] = { | |
2412 | &amr_operand, | |
2413 | &ais_operand, | |
2414 | &ait_operand | |
2415 | }; | |
2416 | ||
2417 | static xtensa_iclass_internal movz_iclass = { | |
2418 | 3, | |
2419 | &movz_operand_list[0] | |
2420 | }; | |
2421 | ||
2422 | static xtensa_operand_internal *callx_operand_list[] = { | |
2423 | &ais_operand | |
2424 | }; | |
2425 | ||
2426 | static xtensa_iclass_internal callx_iclass = { | |
2427 | 1, | |
2428 | &callx_operand_list[0] | |
2429 | }; | |
2430 | ||
2431 | static xtensa_operand_internal *mov_n_operand_list[] = { | |
2432 | &aot_operand, | |
2433 | &ais_operand | |
2434 | }; | |
2435 | ||
2436 | static xtensa_iclass_internal mov_n_iclass = { | |
2437 | 2, | |
2438 | &mov_n_operand_list[0] | |
2439 | }; | |
2440 | ||
2441 | static xtensa_operand_internal *loadi4_operand_list[] = { | |
2442 | &aot_operand, | |
2443 | &ais_operand, | |
2444 | &iilsi4x4_operand | |
2445 | }; | |
2446 | ||
2447 | static xtensa_iclass_internal loadi4_iclass = { | |
2448 | 3, | |
2449 | &loadi4_operand_list[0] | |
2450 | }; | |
2451 | ||
2452 | static xtensa_operand_internal *exti_operand_list[] = { | |
2453 | &aor_operand, | |
2454 | &ait_operand, | |
2455 | &iisae_operand, | |
2456 | &iiop2p1_operand | |
2457 | }; | |
2458 | ||
2459 | static xtensa_iclass_internal exti_iclass = { | |
2460 | 4, | |
2461 | &exti_operand_list[0] | |
2462 | }; | |
2463 | ||
2464 | static xtensa_operand_internal *break_operand_list[] = { | |
2465 | &iis_operand, | |
2466 | &iit_operand | |
2467 | }; | |
2468 | ||
2469 | static xtensa_iclass_internal break_iclass = { | |
2470 | 2, | |
2471 | &break_operand_list[0] | |
2472 | }; | |
2473 | ||
2474 | static xtensa_operand_internal *slli_operand_list[] = { | |
2475 | &aor_operand, | |
2476 | &ais_operand, | |
2477 | &iimsalp32_operand | |
2478 | }; | |
2479 | ||
2480 | static xtensa_iclass_internal slli_iclass = { | |
2481 | 3, | |
2482 | &slli_operand_list[0] | |
2483 | }; | |
2484 | ||
2485 | static xtensa_operand_internal *s16i_operand_list[] = { | |
2486 | &ait_operand, | |
2487 | &ais_operand, | |
2488 | &iiuimm8x2_operand | |
2489 | }; | |
2490 | ||
2491 | static xtensa_iclass_internal s16i_iclass = { | |
2492 | 3, | |
2493 | &s16i_operand_list[0] | |
2494 | }; | |
2495 | ||
2496 | static xtensa_operand_internal *call_operand_list[] = { | |
2497 | &lisoffsetx4_operand | |
2498 | }; | |
2499 | ||
2500 | static xtensa_iclass_internal call_iclass = { | |
2501 | 1, | |
2502 | &call_operand_list[0] | |
2503 | }; | |
2504 | ||
2505 | static xtensa_operand_internal *shifts_operand_list[] = { | |
2506 | &aor_operand, | |
2507 | &ais_operand | |
2508 | }; | |
2509 | ||
2510 | static xtensa_iclass_internal shifts_iclass = { | |
2511 | 2, | |
2512 | &shifts_operand_list[0] | |
2513 | }; | |
2514 | ||
2515 | static xtensa_operand_internal *shiftt_operand_list[] = { | |
2516 | &aor_operand, | |
2517 | &ait_operand | |
2518 | }; | |
2519 | ||
2520 | static xtensa_iclass_internal shiftt_iclass = { | |
2521 | 2, | |
2522 | &shiftt_operand_list[0] | |
2523 | }; | |
2524 | ||
2525 | static xtensa_operand_internal *rotw_operand_list[] = { | |
2526 | &iisimm4_operand | |
2527 | }; | |
2528 | ||
2529 | static xtensa_iclass_internal rotw_iclass = { | |
2530 | 1, | |
2531 | &rotw_operand_list[0] | |
2532 | }; | |
2533 | ||
2534 | static xtensa_operand_internal *addsub_operand_list[] = { | |
2535 | &aor_operand, | |
2536 | &ais_operand, | |
2537 | &ait_operand | |
2538 | }; | |
2539 | ||
2540 | static xtensa_iclass_internal addsub_iclass = { | |
2541 | 3, | |
2542 | &addsub_operand_list[0] | |
2543 | }; | |
2544 | ||
2545 | static xtensa_operand_internal *l8i_operand_list[] = { | |
2546 | &aot_operand, | |
2547 | &ais_operand, | |
2548 | &iiuimm8_operand | |
2549 | }; | |
2550 | ||
2551 | static xtensa_iclass_internal l8i_iclass = { | |
2552 | 3, | |
2553 | &l8i_operand_list[0] | |
2554 | }; | |
2555 | ||
2556 | static xtensa_operand_internal *sari_operand_list[] = { | |
2557 | &iisas_operand | |
2558 | }; | |
2559 | ||
2560 | static xtensa_iclass_internal sari_iclass = { | |
2561 | 1, | |
2562 | &sari_operand_list[0] | |
2563 | }; | |
2564 | ||
2565 | static xtensa_operand_internal *xsr_operand_list[] = { | |
2566 | &abt_operand, | |
2567 | &iisr_operand | |
2568 | }; | |
2569 | ||
2570 | static xtensa_iclass_internal xsr_iclass = { | |
2571 | 2, | |
2572 | &xsr_operand_list[0] | |
2573 | }; | |
2574 | ||
2575 | static xtensa_operand_internal *rsil_operand_list[] = { | |
2576 | &aot_operand, | |
2577 | &iis_operand | |
2578 | }; | |
2579 | ||
2580 | static xtensa_iclass_internal rsil_iclass = { | |
2581 | 2, | |
2582 | &rsil_operand_list[0] | |
2583 | }; | |
2584 | ||
2585 | static xtensa_operand_internal *bst8_operand_list[] = { | |
2586 | &ais_operand, | |
2587 | &ait_operand, | |
2588 | &lisimm8_operand | |
2589 | }; | |
2590 | ||
2591 | static xtensa_iclass_internal bst8_iclass = { | |
2592 | 3, | |
2593 | &bst8_operand_list[0] | |
2594 | }; | |
2595 | ||
2596 | static xtensa_operand_internal *addi_operand_list[] = { | |
2597 | &aot_operand, | |
2598 | &ais_operand, | |
2599 | &iisimm8_operand | |
2600 | }; | |
2601 | ||
2602 | static xtensa_iclass_internal addi_iclass = { | |
2603 | 3, | |
2604 | &addi_operand_list[0] | |
2605 | }; | |
2606 | ||
2607 | static xtensa_operand_internal *callx12_operand_list[] = { | |
2608 | &ais_operand | |
2609 | }; | |
2610 | ||
2611 | static xtensa_iclass_internal callx12_iclass = { | |
2612 | 1, | |
2613 | &callx12_operand_list[0] | |
2614 | }; | |
2615 | ||
2616 | static xtensa_operand_internal *bsi8_operand_list[] = { | |
2617 | &ais_operand, | |
2618 | &iib4const_operand, | |
2619 | &lisimm8_operand | |
2620 | }; | |
2621 | ||
2622 | static xtensa_iclass_internal bsi8_iclass = { | |
2623 | 3, | |
2624 | &bsi8_operand_list[0] | |
2625 | }; | |
2626 | ||
2627 | static xtensa_operand_internal *jumpx_operand_list[] = { | |
2628 | &ais_operand | |
2629 | }; | |
2630 | ||
2631 | static xtensa_iclass_internal jumpx_iclass = { | |
2632 | 1, | |
2633 | &jumpx_operand_list[0] | |
2634 | }; | |
2635 | ||
2636 | static xtensa_iclass_internal retn_iclass = { | |
2637 | 0, | |
2638 | 0 | |
2639 | }; | |
2640 | ||
2641 | static xtensa_operand_internal *nsa_operand_list[] = { | |
2642 | &aot_operand, | |
2643 | &ais_operand | |
2644 | }; | |
2645 | ||
2646 | static xtensa_iclass_internal nsa_iclass = { | |
2647 | 2, | |
2648 | &nsa_operand_list[0] | |
2649 | }; | |
2650 | ||
2651 | static xtensa_operand_internal *storei4_operand_list[] = { | |
2652 | &ait_operand, | |
2653 | &ais_operand, | |
2654 | &iilsi4x4_operand | |
2655 | }; | |
2656 | ||
2657 | static xtensa_iclass_internal storei4_iclass = { | |
2658 | 3, | |
2659 | &storei4_operand_list[0] | |
2660 | }; | |
2661 | ||
2662 | static xtensa_operand_internal *wtlb_operand_list[] = { | |
2663 | &ait_operand, | |
2664 | &ais_operand | |
2665 | }; | |
2666 | ||
2667 | static xtensa_iclass_internal wtlb_iclass = { | |
2668 | 2, | |
2669 | &wtlb_operand_list[0] | |
2670 | }; | |
2671 | ||
2672 | static xtensa_operand_internal *dce_operand_list[] = { | |
2673 | &ais_operand, | |
2674 | &iiuimm4x16_operand | |
2675 | }; | |
2676 | ||
2677 | static xtensa_iclass_internal dce_iclass = { | |
2678 | 2, | |
2679 | &dce_operand_list[0] | |
2680 | }; | |
2681 | ||
2682 | static xtensa_operand_internal *l16i_operand_list[] = { | |
2683 | &aot_operand, | |
2684 | &ais_operand, | |
2685 | &iiuimm8x2_operand | |
2686 | }; | |
2687 | ||
2688 | static xtensa_iclass_internal l16i_iclass = { | |
2689 | 3, | |
2690 | &l16i_operand_list[0] | |
2691 | }; | |
2692 | ||
2693 | static xtensa_operand_internal *callx4_operand_list[] = { | |
2694 | &ais_operand | |
2695 | }; | |
2696 | ||
2697 | static xtensa_iclass_internal callx4_iclass = { | |
2698 | 1, | |
2699 | &callx4_operand_list[0] | |
2700 | }; | |
2701 | ||
2702 | static xtensa_operand_internal *callx8_operand_list[] = { | |
2703 | &ais_operand | |
2704 | }; | |
2705 | ||
2706 | static xtensa_iclass_internal callx8_iclass = { | |
2707 | 1, | |
2708 | &callx8_operand_list[0] | |
2709 | }; | |
2710 | ||
2711 | static xtensa_operand_internal *movsp_operand_list[] = { | |
2712 | &aot_operand, | |
2713 | &ais_operand | |
2714 | }; | |
2715 | ||
2716 | static xtensa_iclass_internal movsp_iclass = { | |
2717 | 2, | |
2718 | &movsp_operand_list[0] | |
2719 | }; | |
2720 | ||
2721 | static xtensa_operand_internal *wsr_operand_list[] = { | |
2722 | &ait_operand, | |
2723 | &iisr_operand | |
2724 | }; | |
2725 | ||
2726 | static xtensa_iclass_internal wsr_iclass = { | |
2727 | 2, | |
2728 | &wsr_operand_list[0] | |
2729 | }; | |
2730 | ||
2731 | static xtensa_operand_internal *call12_operand_list[] = { | |
2732 | &lisoffsetx4_operand | |
2733 | }; | |
2734 | ||
2735 | static xtensa_iclass_internal call12_iclass = { | |
2736 | 1, | |
2737 | &call12_operand_list[0] | |
2738 | }; | |
2739 | ||
2740 | static xtensa_operand_internal *call4_operand_list[] = { | |
2741 | &lisoffsetx4_operand | |
2742 | }; | |
2743 | ||
2744 | static xtensa_iclass_internal call4_iclass = { | |
2745 | 1, | |
2746 | &call4_operand_list[0] | |
2747 | }; | |
2748 | ||
2749 | static xtensa_operand_internal *addmi_operand_list[] = { | |
2750 | &aot_operand, | |
2751 | &ais_operand, | |
2752 | &iisimm8x256_operand | |
2753 | }; | |
2754 | ||
2755 | static xtensa_iclass_internal addmi_iclass = { | |
2756 | 3, | |
2757 | &addmi_operand_list[0] | |
2758 | }; | |
2759 | ||
2760 | static xtensa_operand_internal *bit_operand_list[] = { | |
2761 | &aor_operand, | |
2762 | &ais_operand, | |
2763 | &ait_operand | |
2764 | }; | |
2765 | ||
2766 | static xtensa_iclass_internal bit_iclass = { | |
2767 | 3, | |
2768 | &bit_operand_list[0] | |
2769 | }; | |
2770 | ||
2771 | static xtensa_operand_internal *call8_operand_list[] = { | |
2772 | &lisoffsetx4_operand | |
2773 | }; | |
2774 | ||
2775 | static xtensa_iclass_internal call8_iclass = { | |
2776 | 1, | |
2777 | &call8_operand_list[0] | |
2778 | }; | |
2779 | ||
2780 | static xtensa_iclass_internal itlba_iclass = { | |
2781 | 0, | |
2782 | 0 | |
2783 | }; | |
2784 | ||
2785 | static xtensa_operand_internal *break_n_operand_list[] = { | |
2786 | &iis_operand | |
2787 | }; | |
2788 | ||
2789 | static xtensa_iclass_internal break_n_iclass = { | |
2790 | 1, | |
2791 | &break_n_operand_list[0] | |
2792 | }; | |
2793 | ||
2794 | static xtensa_operand_internal *sar_operand_list[] = { | |
2795 | &ais_operand | |
2796 | }; | |
2797 | ||
2798 | static xtensa_iclass_internal sar_iclass = { | |
2799 | 1, | |
2800 | &sar_operand_list[0] | |
2801 | }; | |
2802 | ||
2803 | static xtensa_operand_internal *s32e_operand_list[] = { | |
2804 | &ait_operand, | |
2805 | &ais_operand, | |
2806 | &iinimm4x2_operand | |
2807 | }; | |
2808 | ||
2809 | static xtensa_iclass_internal s32e_iclass = { | |
2810 | 3, | |
2811 | &s32e_operand_list[0] | |
2812 | }; | |
2813 | ||
2814 | static xtensa_operand_internal *bz6_operand_list[] = { | |
2815 | &ais_operand, | |
2816 | &liuimm6_operand | |
2817 | }; | |
2818 | ||
2819 | static xtensa_iclass_internal bz6_iclass = { | |
2820 | 2, | |
2821 | &bz6_operand_list[0] | |
2822 | }; | |
2823 | ||
2824 | static xtensa_operand_internal *loop_operand_list[] = { | |
2825 | &ais_operand, | |
2826 | &liuimm8_operand | |
2827 | }; | |
2828 | ||
2829 | static xtensa_iclass_internal loop_iclass = { | |
2830 | 2, | |
2831 | &loop_operand_list[0] | |
2832 | }; | |
2833 | ||
2834 | static xtensa_operand_internal *rsr_operand_list[] = { | |
2835 | &aot_operand, | |
2836 | &iisr_operand | |
2837 | }; | |
2838 | ||
2839 | static xtensa_iclass_internal rsr_iclass = { | |
2840 | 2, | |
2841 | &rsr_operand_list[0] | |
2842 | }; | |
2843 | ||
2844 | static xtensa_operand_internal *icache_operand_list[] = { | |
2845 | &ais_operand, | |
2846 | &iiuimm8x4_operand | |
2847 | }; | |
2848 | ||
2849 | static xtensa_iclass_internal icache_iclass = { | |
2850 | 2, | |
2851 | &icache_operand_list[0] | |
2852 | }; | |
2853 | ||
2854 | static xtensa_operand_internal *s8i_operand_list[] = { | |
2855 | &ait_operand, | |
2856 | &ais_operand, | |
2857 | &iiuimm8_operand | |
2858 | }; | |
2859 | ||
2860 | static xtensa_iclass_internal s8i_iclass = { | |
2861 | 3, | |
2862 | &s8i_operand_list[0] | |
2863 | }; | |
2864 | ||
2865 | static xtensa_iclass_internal return_iclass = { | |
2866 | 0, | |
2867 | 0 | |
2868 | }; | |
2869 | ||
2870 | static xtensa_operand_internal *dcache_operand_list[] = { | |
2871 | &ais_operand, | |
2872 | &iiuimm8x4_operand | |
2873 | }; | |
2874 | ||
2875 | static xtensa_iclass_internal dcache_iclass = { | |
2876 | 2, | |
2877 | &dcache_operand_list[0] | |
2878 | }; | |
2879 | ||
2880 | static xtensa_operand_internal *s32i_operand_list[] = { | |
2881 | &ait_operand, | |
2882 | &ais_operand, | |
2883 | &iiuimm8x4_operand | |
2884 | }; | |
2885 | ||
2886 | static xtensa_iclass_internal s32i_iclass = { | |
2887 | 3, | |
2888 | &s32i_operand_list[0] | |
2889 | }; | |
2890 | ||
2891 | static xtensa_operand_internal *jump_operand_list[] = { | |
2892 | &lisoffset_operand | |
2893 | }; | |
2894 | ||
2895 | static xtensa_iclass_internal jump_iclass = { | |
2896 | 1, | |
2897 | &jump_operand_list[0] | |
2898 | }; | |
2899 | ||
2900 | static xtensa_operand_internal *addi_n_operand_list[] = { | |
2901 | &aor_operand, | |
2902 | &ais_operand, | |
2903 | &iiai4const_operand | |
2904 | }; | |
2905 | ||
2906 | static xtensa_iclass_internal addi_n_iclass = { | |
2907 | 3, | |
2908 | &addi_n_operand_list[0] | |
2909 | }; | |
2910 | ||
2911 | static xtensa_iclass_internal sync_iclass = { | |
2912 | 0, | |
2913 | 0 | |
2914 | }; | |
2915 | ||
2916 | static xtensa_operand_internal *neg_operand_list[] = { | |
2917 | &aor_operand, | |
2918 | &ait_operand | |
2919 | }; | |
2920 | ||
2921 | static xtensa_iclass_internal neg_iclass = { | |
2922 | 2, | |
2923 | &neg_operand_list[0] | |
2924 | }; | |
2925 | ||
2926 | static xtensa_iclass_internal syscall_iclass = { | |
2927 | 0, | |
2928 | 0 | |
2929 | }; | |
2930 | ||
2931 | static xtensa_operand_internal *bsz12_operand_list[] = { | |
2932 | &ais_operand, | |
2933 | &lisimm12_operand | |
2934 | }; | |
2935 | ||
2936 | static xtensa_iclass_internal bsz12_iclass = { | |
2937 | 2, | |
2938 | &bsz12_operand_list[0] | |
2939 | }; | |
2940 | ||
2941 | static xtensa_iclass_internal excw_iclass = { | |
2942 | 0, | |
2943 | 0 | |
2944 | }; | |
2945 | ||
2946 | static xtensa_operand_internal *movi_n_operand_list[] = { | |
2947 | &aos_operand, | |
2948 | &iisimm7_operand | |
2949 | }; | |
2950 | ||
2951 | static xtensa_iclass_internal movi_n_iclass = { | |
2952 | 2, | |
2953 | &movi_n_operand_list[0] | |
2954 | }; | |
2955 | ||
2956 | static xtensa_operand_internal *rtlb_operand_list[] = { | |
2957 | &aot_operand, | |
2958 | &ais_operand | |
2959 | }; | |
2960 | ||
2961 | static xtensa_iclass_internal rtlb_iclass = { | |
2962 | 2, | |
2963 | &rtlb_operand_list[0] | |
2964 | }; | |
2965 | ||
2966 | static xtensa_operand_internal *actl_operand_list[] = { | |
2967 | &aot_operand, | |
2968 | &ais_operand | |
2969 | }; | |
2970 | ||
2971 | static xtensa_iclass_internal actl_iclass = { | |
2972 | 2, | |
2973 | &actl_operand_list[0] | |
2974 | }; | |
2975 | ||
2976 | static xtensa_operand_internal *srli_operand_list[] = { | |
2977 | &aor_operand, | |
2978 | &ait_operand, | |
2979 | &iis_operand | |
2980 | }; | |
2981 | ||
2982 | static xtensa_iclass_internal srli_iclass = { | |
2983 | 3, | |
2984 | &srli_operand_list[0] | |
2985 | }; | |
2986 | ||
2987 | static xtensa_operand_internal *bsi8b_operand_list[] = { | |
2988 | &ais_operand, | |
2989 | &iibbi_operand, | |
2990 | &lisimm8_operand | |
2991 | }; | |
2992 | ||
2993 | static xtensa_iclass_internal bsi8b_iclass = { | |
2994 | 3, | |
2995 | &bsi8b_operand_list[0] | |
2996 | }; | |
2997 | ||
2998 | static xtensa_operand_internal *acts_operand_list[] = { | |
2999 | &ait_operand, | |
3000 | &ais_operand | |
3001 | }; | |
3002 | ||
3003 | static xtensa_iclass_internal acts_iclass = { | |
3004 | 2, | |
3005 | &acts_operand_list[0] | |
3006 | }; | |
3007 | ||
3008 | static xtensa_operand_internal *add_n_operand_list[] = { | |
3009 | &aor_operand, | |
3010 | &ais_operand, | |
3011 | &ait_operand | |
3012 | }; | |
3013 | ||
3014 | static xtensa_iclass_internal add_n_iclass = { | |
3015 | 3, | |
3016 | &add_n_operand_list[0] | |
3017 | }; | |
3018 | ||
3019 | static xtensa_operand_internal *srai_operand_list[] = { | |
3020 | &aor_operand, | |
3021 | &ait_operand, | |
3022 | &iisar_operand | |
3023 | }; | |
3024 | ||
3025 | static xtensa_iclass_internal srai_iclass = { | |
3026 | 3, | |
3027 | &srai_operand_list[0] | |
3028 | }; | |
3029 | ||
3030 | static xtensa_operand_internal *entry_operand_list[] = { | |
3031 | &abs_operand, | |
3032 | &iiuimm12x8_operand | |
3033 | }; | |
3034 | ||
3035 | static xtensa_iclass_internal entry_iclass = { | |
3036 | 2, | |
3037 | &entry_operand_list[0] | |
3038 | }; | |
3039 | ||
3040 | static xtensa_operand_internal *l32e_operand_list[] = { | |
3041 | &aot_operand, | |
3042 | &ais_operand, | |
3043 | &iinimm4x2_operand | |
3044 | }; | |
3045 | ||
3046 | static xtensa_iclass_internal l32e_iclass = { | |
3047 | 3, | |
3048 | &l32e_operand_list[0] | |
3049 | }; | |
3050 | ||
3051 | static xtensa_operand_internal *dpf_operand_list[] = { | |
3052 | &ais_operand, | |
3053 | &iiuimm8x4_operand | |
3054 | }; | |
3055 | ||
3056 | static xtensa_iclass_internal dpf_iclass = { | |
3057 | 2, | |
3058 | &dpf_operand_list[0] | |
3059 | }; | |
3060 | ||
3061 | static xtensa_operand_internal *l32i_operand_list[] = { | |
3062 | &aot_operand, | |
3063 | &ais_operand, | |
3064 | &iiuimm8x4_operand | |
3065 | }; | |
3066 | ||
3067 | static xtensa_iclass_internal l32i_iclass = { | |
3068 | 3, | |
3069 | &l32i_operand_list[0] | |
3070 | }; | |
3071 | ||
3072 | static xtensa_insnbuf abs_template (void); | |
3073 | static xtensa_insnbuf add_template (void); | |
3074 | static xtensa_insnbuf add_n_template (void); | |
3075 | static xtensa_insnbuf addi_template (void); | |
3076 | static xtensa_insnbuf addi_n_template (void); | |
3077 | static xtensa_insnbuf addmi_template (void); | |
3078 | static xtensa_insnbuf addx2_template (void); | |
3079 | static xtensa_insnbuf addx4_template (void); | |
3080 | static xtensa_insnbuf addx8_template (void); | |
3081 | static xtensa_insnbuf and_template (void); | |
3082 | static xtensa_insnbuf ball_template (void); | |
3083 | static xtensa_insnbuf bany_template (void); | |
3084 | static xtensa_insnbuf bbc_template (void); | |
3085 | static xtensa_insnbuf bbci_template (void); | |
3086 | static xtensa_insnbuf bbs_template (void); | |
3087 | static xtensa_insnbuf bbsi_template (void); | |
3088 | static xtensa_insnbuf beq_template (void); | |
3089 | static xtensa_insnbuf beqi_template (void); | |
3090 | static xtensa_insnbuf beqz_template (void); | |
3091 | static xtensa_insnbuf beqz_n_template (void); | |
3092 | static xtensa_insnbuf bge_template (void); | |
3093 | static xtensa_insnbuf bgei_template (void); | |
3094 | static xtensa_insnbuf bgeu_template (void); | |
3095 | static xtensa_insnbuf bgeui_template (void); | |
3096 | static xtensa_insnbuf bgez_template (void); | |
3097 | static xtensa_insnbuf blt_template (void); | |
3098 | static xtensa_insnbuf blti_template (void); | |
3099 | static xtensa_insnbuf bltu_template (void); | |
3100 | static xtensa_insnbuf bltui_template (void); | |
3101 | static xtensa_insnbuf bltz_template (void); | |
3102 | static xtensa_insnbuf bnall_template (void); | |
3103 | static xtensa_insnbuf bne_template (void); | |
3104 | static xtensa_insnbuf bnei_template (void); | |
3105 | static xtensa_insnbuf bnez_template (void); | |
3106 | static xtensa_insnbuf bnez_n_template (void); | |
3107 | static xtensa_insnbuf bnone_template (void); | |
3108 | static xtensa_insnbuf break_template (void); | |
3109 | static xtensa_insnbuf break_n_template (void); | |
3110 | static xtensa_insnbuf call0_template (void); | |
3111 | static xtensa_insnbuf call12_template (void); | |
3112 | static xtensa_insnbuf call4_template (void); | |
3113 | static xtensa_insnbuf call8_template (void); | |
3114 | static xtensa_insnbuf callx0_template (void); | |
3115 | static xtensa_insnbuf callx12_template (void); | |
3116 | static xtensa_insnbuf callx4_template (void); | |
3117 | static xtensa_insnbuf callx8_template (void); | |
3118 | static xtensa_insnbuf dhi_template (void); | |
3119 | static xtensa_insnbuf dhwb_template (void); | |
3120 | static xtensa_insnbuf dhwbi_template (void); | |
3121 | static xtensa_insnbuf dii_template (void); | |
3122 | static xtensa_insnbuf diwb_template (void); | |
3123 | static xtensa_insnbuf diwbi_template (void); | |
3124 | static xtensa_insnbuf dpfr_template (void); | |
3125 | static xtensa_insnbuf dpfro_template (void); | |
3126 | static xtensa_insnbuf dpfw_template (void); | |
3127 | static xtensa_insnbuf dpfwo_template (void); | |
3128 | static xtensa_insnbuf dsync_template (void); | |
3129 | static xtensa_insnbuf entry_template (void); | |
3130 | static xtensa_insnbuf esync_template (void); | |
3131 | static xtensa_insnbuf excw_template (void); | |
3132 | static xtensa_insnbuf extui_template (void); | |
3133 | static xtensa_insnbuf idtlb_template (void); | |
3134 | static xtensa_insnbuf idtlba_template (void); | |
3135 | static xtensa_insnbuf ihi_template (void); | |
3136 | static xtensa_insnbuf iii_template (void); | |
3137 | static xtensa_insnbuf iitlb_template (void); | |
3138 | static xtensa_insnbuf iitlba_template (void); | |
3139 | static xtensa_insnbuf ipf_template (void); | |
3140 | static xtensa_insnbuf isync_template (void); | |
3141 | static xtensa_insnbuf j_template (void); | |
3142 | static xtensa_insnbuf jx_template (void); | |
3143 | static xtensa_insnbuf l16si_template (void); | |
3144 | static xtensa_insnbuf l16ui_template (void); | |
3145 | static xtensa_insnbuf l32e_template (void); | |
3146 | static xtensa_insnbuf l32i_template (void); | |
3147 | static xtensa_insnbuf l32i_n_template (void); | |
3148 | static xtensa_insnbuf l32r_template (void); | |
3149 | static xtensa_insnbuf l8ui_template (void); | |
3150 | static xtensa_insnbuf ldct_template (void); | |
3151 | static xtensa_insnbuf lict_template (void); | |
3152 | static xtensa_insnbuf licw_template (void); | |
3153 | static xtensa_insnbuf loop_template (void); | |
3154 | static xtensa_insnbuf loopgtz_template (void); | |
3155 | static xtensa_insnbuf loopnez_template (void); | |
3156 | static xtensa_insnbuf memw_template (void); | |
3157 | static xtensa_insnbuf mov_n_template (void); | |
3158 | static xtensa_insnbuf moveqz_template (void); | |
3159 | static xtensa_insnbuf movgez_template (void); | |
3160 | static xtensa_insnbuf movi_template (void); | |
3161 | static xtensa_insnbuf movi_n_template (void); | |
3162 | static xtensa_insnbuf movltz_template (void); | |
3163 | static xtensa_insnbuf movnez_template (void); | |
3164 | static xtensa_insnbuf movsp_template (void); | |
3165 | static xtensa_insnbuf neg_template (void); | |
3166 | static xtensa_insnbuf nop_n_template (void); | |
3167 | static xtensa_insnbuf nsa_template (void); | |
3168 | static xtensa_insnbuf nsau_template (void); | |
3169 | static xtensa_insnbuf or_template (void); | |
3170 | static xtensa_insnbuf pdtlb_template (void); | |
3171 | static xtensa_insnbuf pitlb_template (void); | |
3172 | static xtensa_insnbuf rdtlb0_template (void); | |
3173 | static xtensa_insnbuf rdtlb1_template (void); | |
3174 | static xtensa_insnbuf ret_template (void); | |
3175 | static xtensa_insnbuf ret_n_template (void); | |
3176 | static xtensa_insnbuf retw_template (void); | |
3177 | static xtensa_insnbuf retw_n_template (void); | |
3178 | static xtensa_insnbuf rfde_template (void); | |
3179 | static xtensa_insnbuf rfe_template (void); | |
3180 | static xtensa_insnbuf rfi_template (void); | |
3181 | static xtensa_insnbuf rfwo_template (void); | |
3182 | static xtensa_insnbuf rfwu_template (void); | |
3183 | static xtensa_insnbuf ritlb0_template (void); | |
3184 | static xtensa_insnbuf ritlb1_template (void); | |
3185 | static xtensa_insnbuf rotw_template (void); | |
3186 | static xtensa_insnbuf rsil_template (void); | |
3187 | static xtensa_insnbuf rsr_template (void); | |
3188 | static xtensa_insnbuf rsync_template (void); | |
3189 | static xtensa_insnbuf s16i_template (void); | |
3190 | static xtensa_insnbuf s32e_template (void); | |
3191 | static xtensa_insnbuf s32i_template (void); | |
3192 | static xtensa_insnbuf s32i_n_template (void); | |
3193 | static xtensa_insnbuf s8i_template (void); | |
3194 | static xtensa_insnbuf sdct_template (void); | |
3195 | static xtensa_insnbuf sict_template (void); | |
3196 | static xtensa_insnbuf sicw_template (void); | |
3197 | static xtensa_insnbuf simcall_template (void); | |
3198 | static xtensa_insnbuf sll_template (void); | |
3199 | static xtensa_insnbuf slli_template (void); | |
3200 | static xtensa_insnbuf sra_template (void); | |
3201 | static xtensa_insnbuf srai_template (void); | |
3202 | static xtensa_insnbuf src_template (void); | |
3203 | static xtensa_insnbuf srl_template (void); | |
3204 | static xtensa_insnbuf srli_template (void); | |
3205 | static xtensa_insnbuf ssa8b_template (void); | |
3206 | static xtensa_insnbuf ssa8l_template (void); | |
3207 | static xtensa_insnbuf ssai_template (void); | |
3208 | static xtensa_insnbuf ssl_template (void); | |
3209 | static xtensa_insnbuf ssr_template (void); | |
3210 | static xtensa_insnbuf sub_template (void); | |
3211 | static xtensa_insnbuf subx2_template (void); | |
3212 | static xtensa_insnbuf subx4_template (void); | |
3213 | static xtensa_insnbuf subx8_template (void); | |
3214 | static xtensa_insnbuf syscall_template (void); | |
3215 | static xtensa_insnbuf waiti_template (void); | |
3216 | static xtensa_insnbuf wdtlb_template (void); | |
3217 | static xtensa_insnbuf witlb_template (void); | |
3218 | static xtensa_insnbuf wsr_template (void); | |
3219 | static xtensa_insnbuf xor_template (void); | |
3220 | static xtensa_insnbuf xsr_template (void); | |
3221 | ||
3222 | static xtensa_insnbuf | |
3223 | abs_template (void) | |
3224 | { | |
3225 | static xtensa_insnbuf_word template[] = { 0x00001006 }; | |
3226 | return &template[0]; | |
3227 | } | |
3228 | ||
3229 | static xtensa_insnbuf | |
3230 | add_template (void) | |
3231 | { | |
3232 | static xtensa_insnbuf_word template[] = { 0x00000008 }; | |
3233 | return &template[0]; | |
3234 | } | |
3235 | ||
3236 | static xtensa_insnbuf | |
3237 | add_n_template (void) | |
3238 | { | |
3239 | static xtensa_insnbuf_word template[] = { 0x00a00000 }; | |
3240 | return &template[0]; | |
3241 | } | |
3242 | ||
3243 | static xtensa_insnbuf | |
3244 | addi_template (void) | |
3245 | { | |
3246 | static xtensa_insnbuf_word template[] = { 0x00200c00 }; | |
3247 | return &template[0]; | |
3248 | } | |
3249 | ||
3250 | static xtensa_insnbuf | |
3251 | addi_n_template (void) | |
3252 | { | |
3253 | static xtensa_insnbuf_word template[] = { 0x00b00000 }; | |
3254 | return &template[0]; | |
3255 | } | |
3256 | ||
3257 | static xtensa_insnbuf | |
3258 | addmi_template (void) | |
3259 | { | |
3260 | static xtensa_insnbuf_word template[] = { 0x00200d00 }; | |
3261 | return &template[0]; | |
3262 | } | |
3263 | ||
3264 | static xtensa_insnbuf | |
3265 | addx2_template (void) | |
3266 | { | |
3267 | static xtensa_insnbuf_word template[] = { 0x00000009 }; | |
3268 | return &template[0]; | |
3269 | } | |
3270 | ||
3271 | static xtensa_insnbuf | |
3272 | addx4_template (void) | |
3273 | { | |
3274 | static xtensa_insnbuf_word template[] = { 0x0000000a }; | |
3275 | return &template[0]; | |
3276 | } | |
3277 | ||
3278 | static xtensa_insnbuf | |
3279 | addx8_template (void) | |
3280 | { | |
3281 | static xtensa_insnbuf_word template[] = { 0x0000000b }; | |
3282 | return &template[0]; | |
3283 | } | |
3284 | ||
3285 | static xtensa_insnbuf | |
3286 | and_template (void) | |
3287 | { | |
3288 | static xtensa_insnbuf_word template[] = { 0x00000001 }; | |
3289 | return &template[0]; | |
3290 | } | |
3291 | ||
3292 | static xtensa_insnbuf | |
3293 | ball_template (void) | |
3294 | { | |
3295 | static xtensa_insnbuf_word template[] = { 0x00700400 }; | |
3296 | return &template[0]; | |
3297 | } | |
3298 | ||
3299 | static xtensa_insnbuf | |
3300 | bany_template (void) | |
3301 | { | |
3302 | static xtensa_insnbuf_word template[] = { 0x00700800 }; | |
3303 | return &template[0]; | |
3304 | } | |
3305 | ||
3306 | static xtensa_insnbuf | |
3307 | bbc_template (void) | |
3308 | { | |
3309 | static xtensa_insnbuf_word template[] = { 0x00700500 }; | |
3310 | return &template[0]; | |
3311 | } | |
3312 | ||
3313 | static xtensa_insnbuf | |
3314 | bbci_template (void) | |
3315 | { | |
3316 | static xtensa_insnbuf_word template[] = { 0x00700600 }; | |
3317 | return &template[0]; | |
3318 | } | |
3319 | ||
3320 | static xtensa_insnbuf | |
3321 | bbs_template (void) | |
3322 | { | |
3323 | static xtensa_insnbuf_word template[] = { 0x00700d00 }; | |
3324 | return &template[0]; | |
3325 | } | |
3326 | ||
3327 | static xtensa_insnbuf | |
3328 | bbsi_template (void) | |
3329 | { | |
3330 | static xtensa_insnbuf_word template[] = { 0x00700e00 }; | |
3331 | return &template[0]; | |
3332 | } | |
3333 | ||
3334 | static xtensa_insnbuf | |
3335 | beq_template (void) | |
3336 | { | |
3337 | static xtensa_insnbuf_word template[] = { 0x00700100 }; | |
3338 | return &template[0]; | |
3339 | } | |
3340 | ||
3341 | static xtensa_insnbuf | |
3342 | beqi_template (void) | |
3343 | { | |
3344 | static xtensa_insnbuf_word template[] = { 0x00680000 }; | |
3345 | return &template[0]; | |
3346 | } | |
3347 | ||
3348 | static xtensa_insnbuf | |
3349 | beqz_template (void) | |
3350 | { | |
3351 | static xtensa_insnbuf_word template[] = { 0x00640000 }; | |
3352 | return &template[0]; | |
3353 | } | |
3354 | ||
3355 | static xtensa_insnbuf | |
3356 | beqz_n_template (void) | |
3357 | { | |
3358 | static xtensa_insnbuf_word template[] = { 0x00c80000 }; | |
3359 | return &template[0]; | |
3360 | } | |
3361 | ||
3362 | static xtensa_insnbuf | |
3363 | bge_template (void) | |
3364 | { | |
3365 | static xtensa_insnbuf_word template[] = { 0x00700a00 }; | |
3366 | return &template[0]; | |
3367 | } | |
3368 | ||
3369 | static xtensa_insnbuf | |
3370 | bgei_template (void) | |
3371 | { | |
3372 | static xtensa_insnbuf_word template[] = { 0x006b0000 }; | |
3373 | return &template[0]; | |
3374 | } | |
3375 | ||
3376 | static xtensa_insnbuf | |
3377 | bgeu_template (void) | |
3378 | { | |
3379 | static xtensa_insnbuf_word template[] = { 0x00700b00 }; | |
3380 | return &template[0]; | |
3381 | } | |
3382 | ||
3383 | static xtensa_insnbuf | |
3384 | bgeui_template (void) | |
3385 | { | |
3386 | static xtensa_insnbuf_word template[] = { 0x006f0000 }; | |
3387 | return &template[0]; | |
3388 | } | |
3389 | ||
3390 | static xtensa_insnbuf | |
3391 | bgez_template (void) | |
3392 | { | |
3393 | static xtensa_insnbuf_word template[] = { 0x00670000 }; | |
3394 | return &template[0]; | |
3395 | } | |
3396 | ||
3397 | static xtensa_insnbuf | |
3398 | blt_template (void) | |
3399 | { | |
3400 | static xtensa_insnbuf_word template[] = { 0x00700200 }; | |
3401 | return &template[0]; | |
3402 | } | |
3403 | ||
3404 | static xtensa_insnbuf | |
3405 | blti_template (void) | |
3406 | { | |
3407 | static xtensa_insnbuf_word template[] = { 0x006a0000 }; | |
3408 | return &template[0]; | |
3409 | } | |
3410 | ||
3411 | static xtensa_insnbuf | |
3412 | bltu_template (void) | |
3413 | { | |
3414 | static xtensa_insnbuf_word template[] = { 0x00700300 }; | |
3415 | return &template[0]; | |
3416 | } | |
3417 | ||
3418 | static xtensa_insnbuf | |
3419 | bltui_template (void) | |
3420 | { | |
3421 | static xtensa_insnbuf_word template[] = { 0x006e0000 }; | |
3422 | return &template[0]; | |
3423 | } | |
3424 | ||
3425 | static xtensa_insnbuf | |
3426 | bltz_template (void) | |
3427 | { | |
3428 | static xtensa_insnbuf_word template[] = { 0x00660000 }; | |
3429 | return &template[0]; | |
3430 | } | |
3431 | ||
3432 | static xtensa_insnbuf | |
3433 | bnall_template (void) | |
3434 | { | |
3435 | static xtensa_insnbuf_word template[] = { 0x00700c00 }; | |
3436 | return &template[0]; | |
3437 | } | |
3438 | ||
3439 | static xtensa_insnbuf | |
3440 | bne_template (void) | |
3441 | { | |
3442 | static xtensa_insnbuf_word template[] = { 0x00700900 }; | |
3443 | return &template[0]; | |
3444 | } | |
3445 | ||
3446 | static xtensa_insnbuf | |
3447 | bnei_template (void) | |
3448 | { | |
3449 | static xtensa_insnbuf_word template[] = { 0x00690000 }; | |
3450 | return &template[0]; | |
3451 | } | |
3452 | ||
3453 | static xtensa_insnbuf | |
3454 | bnez_template (void) | |
3455 | { | |
3456 | static xtensa_insnbuf_word template[] = { 0x00650000 }; | |
3457 | return &template[0]; | |
3458 | } | |
3459 | ||
3460 | static xtensa_insnbuf | |
3461 | bnez_n_template (void) | |
3462 | { | |
3463 | static xtensa_insnbuf_word template[] = { 0x00cc0000 }; | |
3464 | return &template[0]; | |
3465 | } | |
3466 | ||
3467 | static xtensa_insnbuf | |
3468 | bnone_template (void) | |
3469 | { | |
3470 | static xtensa_insnbuf_word template[] = { 0x00700000 }; | |
3471 | return &template[0]; | |
3472 | } | |
3473 | ||
3474 | static xtensa_insnbuf | |
3475 | break_template (void) | |
3476 | { | |
3477 | static xtensa_insnbuf_word template[] = { 0x00000400 }; | |
3478 | return &template[0]; | |
3479 | } | |
3480 | ||
3481 | static xtensa_insnbuf | |
3482 | break_n_template (void) | |
3483 | { | |
3484 | static xtensa_insnbuf_word template[] = { 0x00d20f00 }; | |
3485 | return &template[0]; | |
3486 | } | |
3487 | ||
3488 | static xtensa_insnbuf | |
3489 | call0_template (void) | |
3490 | { | |
3491 | static xtensa_insnbuf_word template[] = { 0x00500000 }; | |
3492 | return &template[0]; | |
3493 | } | |
3494 | ||
3495 | static xtensa_insnbuf | |
3496 | call12_template (void) | |
3497 | { | |
3498 | static xtensa_insnbuf_word template[] = { 0x005c0000 }; | |
3499 | return &template[0]; | |
3500 | } | |
3501 | ||
3502 | static xtensa_insnbuf | |
3503 | call4_template (void) | |
3504 | { | |
3505 | static xtensa_insnbuf_word template[] = { 0x00540000 }; | |
3506 | return &template[0]; | |
3507 | } | |
3508 | ||
3509 | static xtensa_insnbuf | |
3510 | call8_template (void) | |
3511 | { | |
3512 | static xtensa_insnbuf_word template[] = { 0x00580000 }; | |
3513 | return &template[0]; | |
3514 | } | |
3515 | ||
3516 | static xtensa_insnbuf | |
3517 | callx0_template (void) | |
3518 | { | |
3519 | static xtensa_insnbuf_word template[] = { 0x00030000 }; | |
3520 | return &template[0]; | |
3521 | } | |
3522 | ||
3523 | static xtensa_insnbuf | |
3524 | callx12_template (void) | |
3525 | { | |
3526 | static xtensa_insnbuf_word template[] = { 0x000f0000 }; | |
3527 | return &template[0]; | |
3528 | } | |
3529 | ||
3530 | static xtensa_insnbuf | |
3531 | callx4_template (void) | |
3532 | { | |
3533 | static xtensa_insnbuf_word template[] = { 0x00070000 }; | |
3534 | return &template[0]; | |
3535 | } | |
3536 | ||
3537 | static xtensa_insnbuf | |
3538 | callx8_template (void) | |
3539 | { | |
3540 | static xtensa_insnbuf_word template[] = { 0x000b0000 }; | |
3541 | return &template[0]; | |
3542 | } | |
3543 | ||
3544 | static xtensa_insnbuf | |
3545 | dhi_template (void) | |
3546 | { | |
3547 | static xtensa_insnbuf_word template[] = { 0x00260700 }; | |
3548 | return &template[0]; | |
3549 | } | |
3550 | ||
3551 | static xtensa_insnbuf | |
3552 | dhwb_template (void) | |
3553 | { | |
3554 | static xtensa_insnbuf_word template[] = { 0x00240700 }; | |
3555 | return &template[0]; | |
3556 | } | |
3557 | ||
3558 | static xtensa_insnbuf | |
3559 | dhwbi_template (void) | |
3560 | { | |
3561 | static xtensa_insnbuf_word template[] = { 0x00250700 }; | |
3562 | return &template[0]; | |
3563 | } | |
3564 | ||
3565 | static xtensa_insnbuf | |
3566 | dii_template (void) | |
3567 | { | |
3568 | static xtensa_insnbuf_word template[] = { 0x00270700 }; | |
3569 | return &template[0]; | |
3570 | } | |
3571 | ||
3572 | static xtensa_insnbuf | |
3573 | diwb_template (void) | |
3574 | { | |
3575 | static xtensa_insnbuf_word template[] = { 0x00280740 }; | |
3576 | return &template[0]; | |
3577 | } | |
3578 | ||
3579 | static xtensa_insnbuf | |
3580 | diwbi_template (void) | |
3581 | { | |
3582 | static xtensa_insnbuf_word template[] = { 0x00280750 }; | |
3583 | return &template[0]; | |
3584 | } | |
3585 | ||
3586 | static xtensa_insnbuf | |
3587 | dpfr_template (void) | |
3588 | { | |
3589 | static xtensa_insnbuf_word template[] = { 0x00200700 }; | |
3590 | return &template[0]; | |
3591 | } | |
3592 | ||
3593 | static xtensa_insnbuf | |
3594 | dpfro_template (void) | |
3595 | { | |
3596 | static xtensa_insnbuf_word template[] = { 0x00220700 }; | |
3597 | return &template[0]; | |
3598 | } | |
3599 | ||
3600 | static xtensa_insnbuf | |
3601 | dpfw_template (void) | |
3602 | { | |
3603 | static xtensa_insnbuf_word template[] = { 0x00210700 }; | |
3604 | return &template[0]; | |
3605 | } | |
3606 | ||
3607 | static xtensa_insnbuf | |
3608 | dpfwo_template (void) | |
3609 | { | |
3610 | static xtensa_insnbuf_word template[] = { 0x00230700 }; | |
3611 | return &template[0]; | |
3612 | } | |
3613 | ||
3614 | static xtensa_insnbuf | |
3615 | dsync_template (void) | |
3616 | { | |
3617 | static xtensa_insnbuf_word template[] = { 0x00030200 }; | |
3618 | return &template[0]; | |
3619 | } | |
3620 | ||
3621 | static xtensa_insnbuf | |
3622 | entry_template (void) | |
3623 | { | |
3624 | static xtensa_insnbuf_word template[] = { 0x006c0000 }; | |
3625 | return &template[0]; | |
3626 | } | |
3627 | ||
3628 | static xtensa_insnbuf | |
3629 | esync_template (void) | |
3630 | { | |
3631 | static xtensa_insnbuf_word template[] = { 0x00020200 }; | |
3632 | return &template[0]; | |
3633 | } | |
3634 | ||
3635 | static xtensa_insnbuf | |
3636 | excw_template (void) | |
3637 | { | |
3638 | static xtensa_insnbuf_word template[] = { 0x00080200 }; | |
3639 | return &template[0]; | |
3640 | } | |
3641 | ||
3642 | static xtensa_insnbuf | |
3643 | extui_template (void) | |
3644 | { | |
3645 | static xtensa_insnbuf_word template[] = { 0x00000040 }; | |
3646 | return &template[0]; | |
3647 | } | |
3648 | ||
3649 | static xtensa_insnbuf | |
3650 | idtlb_template (void) | |
3651 | { | |
3652 | static xtensa_insnbuf_word template[] = { 0x00000c05 }; | |
3653 | return &template[0]; | |
3654 | } | |
3655 | ||
3656 | static xtensa_insnbuf | |
3657 | idtlba_template (void) | |
3658 | { | |
3659 | static xtensa_insnbuf_word template[] = { 0x00000805 }; | |
3660 | return &template[0]; | |
3661 | } | |
3662 | ||
3663 | static xtensa_insnbuf | |
3664 | ihi_template (void) | |
3665 | { | |
3666 | static xtensa_insnbuf_word template[] = { 0x002e0700 }; | |
3667 | return &template[0]; | |
3668 | } | |
3669 | ||
3670 | static xtensa_insnbuf | |
3671 | iii_template (void) | |
3672 | { | |
3673 | static xtensa_insnbuf_word template[] = { 0x002f0700 }; | |
3674 | return &template[0]; | |
3675 | } | |
3676 | ||
3677 | static xtensa_insnbuf | |
3678 | iitlb_template (void) | |
3679 | { | |
3680 | static xtensa_insnbuf_word template[] = { 0x00000405 }; | |
3681 | return &template[0]; | |
3682 | } | |
3683 | ||
3684 | static xtensa_insnbuf | |
3685 | iitlba_template (void) | |
3686 | { | |
3687 | static xtensa_insnbuf_word template[] = { 0x00000005 }; | |
3688 | return &template[0]; | |
3689 | } | |
3690 | ||
3691 | static xtensa_insnbuf | |
3692 | ipf_template (void) | |
3693 | { | |
3694 | static xtensa_insnbuf_word template[] = { 0x002c0700 }; | |
3695 | return &template[0]; | |
3696 | } | |
3697 | ||
3698 | static xtensa_insnbuf | |
3699 | isync_template (void) | |
3700 | { | |
3701 | static xtensa_insnbuf_word template[] = { 0x00000200 }; | |
3702 | return &template[0]; | |
3703 | } | |
3704 | ||
3705 | static xtensa_insnbuf | |
3706 | j_template (void) | |
3707 | { | |
3708 | static xtensa_insnbuf_word template[] = { 0x00600000 }; | |
3709 | return &template[0]; | |
3710 | } | |
3711 | ||
3712 | static xtensa_insnbuf | |
3713 | jx_template (void) | |
3714 | { | |
3715 | static xtensa_insnbuf_word template[] = { 0x000a0000 }; | |
3716 | return &template[0]; | |
3717 | } | |
3718 | ||
3719 | static xtensa_insnbuf | |
3720 | l16si_template (void) | |
3721 | { | |
3722 | static xtensa_insnbuf_word template[] = { 0x00200900 }; | |
3723 | return &template[0]; | |
3724 | } | |
3725 | ||
3726 | static xtensa_insnbuf | |
3727 | l16ui_template (void) | |
3728 | { | |
3729 | static xtensa_insnbuf_word template[] = { 0x00200100 }; | |
3730 | return &template[0]; | |
3731 | } | |
3732 | ||
3733 | static xtensa_insnbuf | |
3734 | l32e_template (void) | |
3735 | { | |
3736 | static xtensa_insnbuf_word template[] = { 0x00000090 }; | |
3737 | return &template[0]; | |
3738 | } | |
3739 | ||
3740 | static xtensa_insnbuf | |
3741 | l32i_template (void) | |
3742 | { | |
3743 | static xtensa_insnbuf_word template[] = { 0x00200200 }; | |
3744 | return &template[0]; | |
3745 | } | |
3746 | ||
3747 | static xtensa_insnbuf | |
3748 | l32i_n_template (void) | |
3749 | { | |
3750 | static xtensa_insnbuf_word template[] = { 0x00800000 }; | |
3751 | return &template[0]; | |
3752 | } | |
3753 | ||
3754 | static xtensa_insnbuf | |
3755 | l32r_template (void) | |
3756 | { | |
3757 | static xtensa_insnbuf_word template[] = { 0x00100000 }; | |
3758 | return &template[0]; | |
3759 | } | |
3760 | ||
3761 | static xtensa_insnbuf | |
3762 | l8ui_template (void) | |
3763 | { | |
3764 | static xtensa_insnbuf_word template[] = { 0x00200000 }; | |
3765 | return &template[0]; | |
3766 | } | |
3767 | ||
3768 | static xtensa_insnbuf | |
3769 | ldct_template (void) | |
3770 | { | |
3771 | static xtensa_insnbuf_word template[] = { 0x0000081f }; | |
3772 | return &template[0]; | |
3773 | } | |
3774 | ||
3775 | static xtensa_insnbuf | |
3776 | lict_template (void) | |
3777 | { | |
3778 | static xtensa_insnbuf_word template[] = { 0x0000001f }; | |
3779 | return &template[0]; | |
3780 | } | |
3781 | ||
3782 | static xtensa_insnbuf | |
3783 | licw_template (void) | |
3784 | { | |
3785 | static xtensa_insnbuf_word template[] = { 0x0000021f }; | |
3786 | return &template[0]; | |
3787 | } | |
3788 | ||
3789 | static xtensa_insnbuf | |
3790 | loop_template (void) | |
3791 | { | |
3792 | static xtensa_insnbuf_word template[] = { 0x006d0800 }; | |
3793 | return &template[0]; | |
3794 | } | |
3795 | ||
3796 | static xtensa_insnbuf | |
3797 | loopgtz_template (void) | |
3798 | { | |
3799 | static xtensa_insnbuf_word template[] = { 0x006d0a00 }; | |
3800 | return &template[0]; | |
3801 | } | |
3802 | ||
3803 | static xtensa_insnbuf | |
3804 | loopnez_template (void) | |
3805 | { | |
3806 | static xtensa_insnbuf_word template[] = { 0x006d0900 }; | |
3807 | return &template[0]; | |
3808 | } | |
3809 | ||
3810 | static xtensa_insnbuf | |
3811 | memw_template (void) | |
3812 | { | |
3813 | static xtensa_insnbuf_word template[] = { 0x000c0200 }; | |
3814 | return &template[0]; | |
3815 | } | |
3816 | ||
3817 | static xtensa_insnbuf | |
3818 | mov_n_template (void) | |
3819 | { | |
3820 | static xtensa_insnbuf_word template[] = { 0x00d00000 }; | |
3821 | return &template[0]; | |
3822 | } | |
3823 | ||
3824 | static xtensa_insnbuf | |
3825 | moveqz_template (void) | |
3826 | { | |
3827 | static xtensa_insnbuf_word template[] = { 0x00000038 }; | |
3828 | return &template[0]; | |
3829 | } | |
3830 | ||
3831 | static xtensa_insnbuf | |
3832 | movgez_template (void) | |
3833 | { | |
3834 | static xtensa_insnbuf_word template[] = { 0x0000003b }; | |
3835 | return &template[0]; | |
3836 | } | |
3837 | ||
3838 | static xtensa_insnbuf | |
3839 | movi_template (void) | |
3840 | { | |
3841 | static xtensa_insnbuf_word template[] = { 0x00200a00 }; | |
3842 | return &template[0]; | |
3843 | } | |
3844 | ||
3845 | static xtensa_insnbuf | |
3846 | movi_n_template (void) | |
3847 | { | |
3848 | static xtensa_insnbuf_word template[] = { 0x00c00000 }; | |
3849 | return &template[0]; | |
3850 | } | |
3851 | ||
3852 | static xtensa_insnbuf | |
3853 | movltz_template (void) | |
3854 | { | |
3855 | static xtensa_insnbuf_word template[] = { 0x0000003a }; | |
3856 | return &template[0]; | |
3857 | } | |
3858 | ||
3859 | static xtensa_insnbuf | |
3860 | movnez_template (void) | |
3861 | { | |
3862 | static xtensa_insnbuf_word template[] = { 0x00000039 }; | |
3863 | return &template[0]; | |
3864 | } | |
3865 | ||
3866 | static xtensa_insnbuf | |
3867 | movsp_template (void) | |
3868 | { | |
3869 | static xtensa_insnbuf_word template[] = { 0x00000100 }; | |
3870 | return &template[0]; | |
3871 | } | |
3872 | ||
3873 | static xtensa_insnbuf | |
3874 | neg_template (void) | |
3875 | { | |
3876 | static xtensa_insnbuf_word template[] = { 0x00000006 }; | |
3877 | return &template[0]; | |
3878 | } | |
3879 | ||
3880 | static xtensa_insnbuf | |
3881 | nop_n_template (void) | |
3882 | { | |
3883 | static xtensa_insnbuf_word template[] = { 0x00d30f00 }; | |
3884 | return &template[0]; | |
3885 | } | |
3886 | ||
3887 | static xtensa_insnbuf | |
3888 | nsa_template (void) | |
3889 | { | |
3890 | static xtensa_insnbuf_word template[] = { 0x00000e04 }; | |
3891 | return &template[0]; | |
3892 | } | |
3893 | ||
3894 | static xtensa_insnbuf | |
3895 | nsau_template (void) | |
3896 | { | |
3897 | static xtensa_insnbuf_word template[] = { 0x00000f04 }; | |
3898 | return &template[0]; | |
3899 | } | |
3900 | ||
3901 | static xtensa_insnbuf | |
3902 | or_template (void) | |
3903 | { | |
3904 | static xtensa_insnbuf_word template[] = { 0x00000002 }; | |
3905 | return &template[0]; | |
3906 | } | |
3907 | ||
3908 | static xtensa_insnbuf | |
3909 | pdtlb_template (void) | |
3910 | { | |
3911 | static xtensa_insnbuf_word template[] = { 0x00000d05 }; | |
3912 | return &template[0]; | |
3913 | } | |
3914 | ||
3915 | static xtensa_insnbuf | |
3916 | pitlb_template (void) | |
3917 | { | |
3918 | static xtensa_insnbuf_word template[] = { 0x00000505 }; | |
3919 | return &template[0]; | |
3920 | } | |
3921 | ||
3922 | static xtensa_insnbuf | |
3923 | rdtlb0_template (void) | |
3924 | { | |
3925 | static xtensa_insnbuf_word template[] = { 0x00000b05 }; | |
3926 | return &template[0]; | |
3927 | } | |
3928 | ||
3929 | static xtensa_insnbuf | |
3930 | rdtlb1_template (void) | |
3931 | { | |
3932 | static xtensa_insnbuf_word template[] = { 0x00000f05 }; | |
3933 | return &template[0]; | |
3934 | } | |
3935 | ||
3936 | static xtensa_insnbuf | |
3937 | ret_template (void) | |
3938 | { | |
3939 | static xtensa_insnbuf_word template[] = { 0x00020000 }; | |
3940 | return &template[0]; | |
3941 | } | |
3942 | ||
3943 | static xtensa_insnbuf | |
3944 | ret_n_template (void) | |
3945 | { | |
3946 | static xtensa_insnbuf_word template[] = { 0x00d00f00 }; | |
3947 | return &template[0]; | |
3948 | } | |
3949 | ||
3950 | static xtensa_insnbuf | |
3951 | retw_template (void) | |
3952 | { | |
3953 | static xtensa_insnbuf_word template[] = { 0x00060000 }; | |
3954 | return &template[0]; | |
3955 | } | |
3956 | ||
3957 | static xtensa_insnbuf | |
3958 | retw_n_template (void) | |
3959 | { | |
3960 | static xtensa_insnbuf_word template[] = { 0x00d10f00 }; | |
3961 | return &template[0]; | |
3962 | } | |
3963 | ||
3964 | static xtensa_insnbuf | |
3965 | rfde_template (void) | |
3966 | { | |
3967 | static xtensa_insnbuf_word template[] = { 0x00002300 }; | |
3968 | return &template[0]; | |
3969 | } | |
3970 | ||
3971 | static xtensa_insnbuf | |
3972 | rfe_template (void) | |
3973 | { | |
3974 | static xtensa_insnbuf_word template[] = { 0x00000300 }; | |
3975 | return &template[0]; | |
3976 | } | |
3977 | ||
3978 | static xtensa_insnbuf | |
3979 | rfi_template (void) | |
3980 | { | |
3981 | static xtensa_insnbuf_word template[] = { 0x00010300 }; | |
3982 | return &template[0]; | |
3983 | } | |
3984 | ||
3985 | static xtensa_insnbuf | |
3986 | rfwo_template (void) | |
3987 | { | |
3988 | static xtensa_insnbuf_word template[] = { 0x00004300 }; | |
3989 | return &template[0]; | |
3990 | } | |
3991 | ||
3992 | static xtensa_insnbuf | |
3993 | rfwu_template (void) | |
3994 | { | |
3995 | static xtensa_insnbuf_word template[] = { 0x00005300 }; | |
3996 | return &template[0]; | |
3997 | } | |
3998 | ||
3999 | static xtensa_insnbuf | |
4000 | ritlb0_template (void) | |
4001 | { | |
4002 | static xtensa_insnbuf_word template[] = { 0x00000305 }; | |
4003 | return &template[0]; | |
4004 | } | |
4005 | ||
4006 | static xtensa_insnbuf | |
4007 | ritlb1_template (void) | |
4008 | { | |
4009 | static xtensa_insnbuf_word template[] = { 0x00000705 }; | |
4010 | return &template[0]; | |
4011 | } | |
4012 | ||
4013 | static xtensa_insnbuf | |
4014 | rotw_template (void) | |
4015 | { | |
4016 | static xtensa_insnbuf_word template[] = { 0x00000804 }; | |
4017 | return &template[0]; | |
4018 | } | |
4019 | ||
4020 | static xtensa_insnbuf | |
4021 | rsil_template (void) | |
4022 | { | |
4023 | static xtensa_insnbuf_word template[] = { 0x00000600 }; | |
4024 | return &template[0]; | |
4025 | } | |
4026 | ||
4027 | static xtensa_insnbuf | |
4028 | rsr_template (void) | |
4029 | { | |
4030 | static xtensa_insnbuf_word template[] = { 0x00000030 }; | |
4031 | return &template[0]; | |
4032 | } | |
4033 | ||
4034 | static xtensa_insnbuf | |
4035 | rsync_template (void) | |
4036 | { | |
4037 | static xtensa_insnbuf_word template[] = { 0x00010200 }; | |
4038 | return &template[0]; | |
4039 | } | |
4040 | ||
4041 | static xtensa_insnbuf | |
4042 | s16i_template (void) | |
4043 | { | |
4044 | static xtensa_insnbuf_word template[] = { 0x00200500 }; | |
4045 | return &template[0]; | |
4046 | } | |
4047 | ||
4048 | static xtensa_insnbuf | |
4049 | s32e_template (void) | |
4050 | { | |
4051 | static xtensa_insnbuf_word template[] = { 0x00000094 }; | |
4052 | return &template[0]; | |
4053 | } | |
4054 | ||
4055 | static xtensa_insnbuf | |
4056 | s32i_template (void) | |
4057 | { | |
4058 | static xtensa_insnbuf_word template[] = { 0x00200600 }; | |
4059 | return &template[0]; | |
4060 | } | |
4061 | ||
4062 | static xtensa_insnbuf | |
4063 | s32i_n_template (void) | |
4064 | { | |
4065 | static xtensa_insnbuf_word template[] = { 0x00900000 }; | |
4066 | return &template[0]; | |
4067 | } | |
4068 | ||
4069 | static xtensa_insnbuf | |
4070 | s8i_template (void) | |
4071 | { | |
4072 | static xtensa_insnbuf_word template[] = { 0x00200400 }; | |
4073 | return &template[0]; | |
4074 | } | |
4075 | ||
4076 | static xtensa_insnbuf | |
4077 | sdct_template (void) | |
4078 | { | |
4079 | static xtensa_insnbuf_word template[] = { 0x0000091f }; | |
4080 | return &template[0]; | |
4081 | } | |
4082 | ||
4083 | static xtensa_insnbuf | |
4084 | sict_template (void) | |
4085 | { | |
4086 | static xtensa_insnbuf_word template[] = { 0x0000011f }; | |
4087 | return &template[0]; | |
4088 | } | |
4089 | ||
4090 | static xtensa_insnbuf | |
4091 | sicw_template (void) | |
4092 | { | |
4093 | static xtensa_insnbuf_word template[] = { 0x0000031f }; | |
4094 | return &template[0]; | |
4095 | } | |
4096 | ||
4097 | static xtensa_insnbuf | |
4098 | simcall_template (void) | |
4099 | { | |
4100 | static xtensa_insnbuf_word template[] = { 0x00001500 }; | |
4101 | return &template[0]; | |
4102 | } | |
4103 | ||
4104 | static xtensa_insnbuf | |
4105 | sll_template (void) | |
4106 | { | |
4107 | static xtensa_insnbuf_word template[] = { 0x0000001a }; | |
4108 | return &template[0]; | |
4109 | } | |
4110 | ||
4111 | static xtensa_insnbuf | |
4112 | slli_template (void) | |
4113 | { | |
4114 | static xtensa_insnbuf_word template[] = { 0x00000010 }; | |
4115 | return &template[0]; | |
4116 | } | |
4117 | ||
4118 | static xtensa_insnbuf | |
4119 | sra_template (void) | |
4120 | { | |
4121 | static xtensa_insnbuf_word template[] = { 0x0000001b }; | |
4122 | return &template[0]; | |
4123 | } | |
4124 | ||
4125 | static xtensa_insnbuf | |
4126 | srai_template (void) | |
4127 | { | |
4128 | static xtensa_insnbuf_word template[] = { 0x00000012 }; | |
4129 | return &template[0]; | |
4130 | } | |
4131 | ||
4132 | static xtensa_insnbuf | |
4133 | src_template (void) | |
4134 | { | |
4135 | static xtensa_insnbuf_word template[] = { 0x00000018 }; | |
4136 | return &template[0]; | |
4137 | } | |
4138 | ||
4139 | static xtensa_insnbuf | |
4140 | srl_template (void) | |
4141 | { | |
4142 | static xtensa_insnbuf_word template[] = { 0x00000019 }; | |
4143 | return &template[0]; | |
4144 | } | |
4145 | ||
4146 | static xtensa_insnbuf | |
4147 | srli_template (void) | |
4148 | { | |
4149 | static xtensa_insnbuf_word template[] = { 0x00000014 }; | |
4150 | return &template[0]; | |
4151 | } | |
4152 | ||
4153 | static xtensa_insnbuf | |
4154 | ssa8b_template (void) | |
4155 | { | |
4156 | static xtensa_insnbuf_word template[] = { 0x00000304 }; | |
4157 | return &template[0]; | |
4158 | } | |
4159 | ||
4160 | static xtensa_insnbuf | |
4161 | ssa8l_template (void) | |
4162 | { | |
4163 | static xtensa_insnbuf_word template[] = { 0x00000204 }; | |
4164 | return &template[0]; | |
4165 | } | |
4166 | ||
4167 | static xtensa_insnbuf | |
4168 | ssai_template (void) | |
4169 | { | |
4170 | static xtensa_insnbuf_word template[] = { 0x00000404 }; | |
4171 | return &template[0]; | |
4172 | } | |
4173 | ||
4174 | static xtensa_insnbuf | |
4175 | ssl_template (void) | |
4176 | { | |
4177 | static xtensa_insnbuf_word template[] = { 0x00000104 }; | |
4178 | return &template[0]; | |
4179 | } | |
4180 | ||
4181 | static xtensa_insnbuf | |
4182 | ssr_template (void) | |
4183 | { | |
4184 | static xtensa_insnbuf_word template[] = { 0x00000004 }; | |
4185 | return &template[0]; | |
4186 | } | |
4187 | ||
4188 | static xtensa_insnbuf | |
4189 | sub_template (void) | |
4190 | { | |
4191 | static xtensa_insnbuf_word template[] = { 0x0000000c }; | |
4192 | return &template[0]; | |
4193 | } | |
4194 | ||
4195 | static xtensa_insnbuf | |
4196 | subx2_template (void) | |
4197 | { | |
4198 | static xtensa_insnbuf_word template[] = { 0x0000000d }; | |
4199 | return &template[0]; | |
4200 | } | |
4201 | ||
4202 | static xtensa_insnbuf | |
4203 | subx4_template (void) | |
4204 | { | |
4205 | static xtensa_insnbuf_word template[] = { 0x0000000e }; | |
4206 | return &template[0]; | |
4207 | } | |
4208 | ||
4209 | static xtensa_insnbuf | |
4210 | subx8_template (void) | |
4211 | { | |
4212 | static xtensa_insnbuf_word template[] = { 0x0000000f }; | |
4213 | return &template[0]; | |
4214 | } | |
4215 | ||
4216 | static xtensa_insnbuf | |
4217 | syscall_template (void) | |
4218 | { | |
4219 | static xtensa_insnbuf_word template[] = { 0x00000500 }; | |
4220 | return &template[0]; | |
4221 | } | |
4222 | ||
4223 | static xtensa_insnbuf | |
4224 | waiti_template (void) | |
4225 | { | |
4226 | static xtensa_insnbuf_word template[] = { 0x00000700 }; | |
4227 | return &template[0]; | |
4228 | } | |
4229 | ||
4230 | static xtensa_insnbuf | |
4231 | wdtlb_template (void) | |
4232 | { | |
4233 | static xtensa_insnbuf_word template[] = { 0x00000e05 }; | |
4234 | return &template[0]; | |
4235 | } | |
4236 | ||
4237 | static xtensa_insnbuf | |
4238 | witlb_template (void) | |
4239 | { | |
4240 | static xtensa_insnbuf_word template[] = { 0x00000605 }; | |
4241 | return &template[0]; | |
4242 | } | |
4243 | ||
4244 | static xtensa_insnbuf | |
4245 | wsr_template (void) | |
4246 | { | |
4247 | static xtensa_insnbuf_word template[] = { 0x00000031 }; | |
4248 | return &template[0]; | |
4249 | } | |
4250 | ||
4251 | static xtensa_insnbuf | |
4252 | xor_template (void) | |
4253 | { | |
4254 | static xtensa_insnbuf_word template[] = { 0x00000003 }; | |
4255 | return &template[0]; | |
4256 | } | |
4257 | ||
4258 | static xtensa_insnbuf | |
4259 | xsr_template (void) | |
4260 | { | |
4261 | static xtensa_insnbuf_word template[] = { 0x00000016 }; | |
4262 | return &template[0]; | |
4263 | } | |
4264 | ||
4265 | static xtensa_opcode_internal abs_opcode = { | |
4266 | "abs", | |
4267 | 3, | |
4268 | abs_template, | |
4269 | &neg_iclass | |
4270 | }; | |
4271 | ||
4272 | static xtensa_opcode_internal add_opcode = { | |
4273 | "add", | |
4274 | 3, | |
4275 | add_template, | |
4276 | &addsub_iclass | |
4277 | }; | |
4278 | ||
4279 | static xtensa_opcode_internal add_n_opcode = { | |
4280 | "add.n", | |
4281 | 2, | |
4282 | add_n_template, | |
4283 | &add_n_iclass | |
4284 | }; | |
4285 | ||
4286 | static xtensa_opcode_internal addi_opcode = { | |
4287 | "addi", | |
4288 | 3, | |
4289 | addi_template, | |
4290 | &addi_iclass | |
4291 | }; | |
4292 | ||
4293 | static xtensa_opcode_internal addi_n_opcode = { | |
4294 | "addi.n", | |
4295 | 2, | |
4296 | addi_n_template, | |
4297 | &addi_n_iclass | |
4298 | }; | |
4299 | ||
4300 | static xtensa_opcode_internal addmi_opcode = { | |
4301 | "addmi", | |
4302 | 3, | |
4303 | addmi_template, | |
4304 | &addmi_iclass | |
4305 | }; | |
4306 | ||
4307 | static xtensa_opcode_internal addx2_opcode = { | |
4308 | "addx2", | |
4309 | 3, | |
4310 | addx2_template, | |
4311 | &addsub_iclass | |
4312 | }; | |
4313 | ||
4314 | static xtensa_opcode_internal addx4_opcode = { | |
4315 | "addx4", | |
4316 | 3, | |
4317 | addx4_template, | |
4318 | &addsub_iclass | |
4319 | }; | |
4320 | ||
4321 | static xtensa_opcode_internal addx8_opcode = { | |
4322 | "addx8", | |
4323 | 3, | |
4324 | addx8_template, | |
4325 | &addsub_iclass | |
4326 | }; | |
4327 | ||
4328 | static xtensa_opcode_internal and_opcode = { | |
4329 | "and", | |
4330 | 3, | |
4331 | and_template, | |
4332 | &bit_iclass | |
4333 | }; | |
4334 | ||
4335 | static xtensa_opcode_internal ball_opcode = { | |
4336 | "ball", | |
4337 | 3, | |
4338 | ball_template, | |
4339 | &bst8_iclass | |
4340 | }; | |
4341 | ||
4342 | static xtensa_opcode_internal bany_opcode = { | |
4343 | "bany", | |
4344 | 3, | |
4345 | bany_template, | |
4346 | &bst8_iclass | |
4347 | }; | |
4348 | ||
4349 | static xtensa_opcode_internal bbc_opcode = { | |
4350 | "bbc", | |
4351 | 3, | |
4352 | bbc_template, | |
4353 | &bst8_iclass | |
4354 | }; | |
4355 | ||
4356 | static xtensa_opcode_internal bbci_opcode = { | |
4357 | "bbci", | |
4358 | 3, | |
4359 | bbci_template, | |
4360 | &bsi8b_iclass | |
4361 | }; | |
4362 | ||
4363 | static xtensa_opcode_internal bbs_opcode = { | |
4364 | "bbs", | |
4365 | 3, | |
4366 | bbs_template, | |
4367 | &bst8_iclass | |
4368 | }; | |
4369 | ||
4370 | static xtensa_opcode_internal bbsi_opcode = { | |
4371 | "bbsi", | |
4372 | 3, | |
4373 | bbsi_template, | |
4374 | &bsi8b_iclass | |
4375 | }; | |
4376 | ||
4377 | static xtensa_opcode_internal beq_opcode = { | |
4378 | "beq", | |
4379 | 3, | |
4380 | beq_template, | |
4381 | &bst8_iclass | |
4382 | }; | |
4383 | ||
4384 | static xtensa_opcode_internal beqi_opcode = { | |
4385 | "beqi", | |
4386 | 3, | |
4387 | beqi_template, | |
4388 | &bsi8_iclass | |
4389 | }; | |
4390 | ||
4391 | static xtensa_opcode_internal beqz_opcode = { | |
4392 | "beqz", | |
4393 | 3, | |
4394 | beqz_template, | |
4395 | &bsz12_iclass | |
4396 | }; | |
4397 | ||
4398 | static xtensa_opcode_internal beqz_n_opcode = { | |
4399 | "beqz.n", | |
4400 | 2, | |
4401 | beqz_n_template, | |
4402 | &bz6_iclass | |
4403 | }; | |
4404 | ||
4405 | static xtensa_opcode_internal bge_opcode = { | |
4406 | "bge", | |
4407 | 3, | |
4408 | bge_template, | |
4409 | &bst8_iclass | |
4410 | }; | |
4411 | ||
4412 | static xtensa_opcode_internal bgei_opcode = { | |
4413 | "bgei", | |
4414 | 3, | |
4415 | bgei_template, | |
4416 | &bsi8_iclass | |
4417 | }; | |
4418 | ||
4419 | static xtensa_opcode_internal bgeu_opcode = { | |
4420 | "bgeu", | |
4421 | 3, | |
4422 | bgeu_template, | |
4423 | &bst8_iclass | |
4424 | }; | |
4425 | ||
4426 | static xtensa_opcode_internal bgeui_opcode = { | |
4427 | "bgeui", | |
4428 | 3, | |
4429 | bgeui_template, | |
4430 | &bsi8u_iclass | |
4431 | }; | |
4432 | ||
4433 | static xtensa_opcode_internal bgez_opcode = { | |
4434 | "bgez", | |
4435 | 3, | |
4436 | bgez_template, | |
4437 | &bsz12_iclass | |
4438 | }; | |
4439 | ||
4440 | static xtensa_opcode_internal blt_opcode = { | |
4441 | "blt", | |
4442 | 3, | |
4443 | blt_template, | |
4444 | &bst8_iclass | |
4445 | }; | |
4446 | ||
4447 | static xtensa_opcode_internal blti_opcode = { | |
4448 | "blti", | |
4449 | 3, | |
4450 | blti_template, | |
4451 | &bsi8_iclass | |
4452 | }; | |
4453 | ||
4454 | static xtensa_opcode_internal bltu_opcode = { | |
4455 | "bltu", | |
4456 | 3, | |
4457 | bltu_template, | |
4458 | &bst8_iclass | |
4459 | }; | |
4460 | ||
4461 | static xtensa_opcode_internal bltui_opcode = { | |
4462 | "bltui", | |
4463 | 3, | |
4464 | bltui_template, | |
4465 | &bsi8u_iclass | |
4466 | }; | |
4467 | ||
4468 | static xtensa_opcode_internal bltz_opcode = { | |
4469 | "bltz", | |
4470 | 3, | |
4471 | bltz_template, | |
4472 | &bsz12_iclass | |
4473 | }; | |
4474 | ||
4475 | static xtensa_opcode_internal bnall_opcode = { | |
4476 | "bnall", | |
4477 | 3, | |
4478 | bnall_template, | |
4479 | &bst8_iclass | |
4480 | }; | |
4481 | ||
4482 | static xtensa_opcode_internal bne_opcode = { | |
4483 | "bne", | |
4484 | 3, | |
4485 | bne_template, | |
4486 | &bst8_iclass | |
4487 | }; | |
4488 | ||
4489 | static xtensa_opcode_internal bnei_opcode = { | |
4490 | "bnei", | |
4491 | 3, | |
4492 | bnei_template, | |
4493 | &bsi8_iclass | |
4494 | }; | |
4495 | ||
4496 | static xtensa_opcode_internal bnez_opcode = { | |
4497 | "bnez", | |
4498 | 3, | |
4499 | bnez_template, | |
4500 | &bsz12_iclass | |
4501 | }; | |
4502 | ||
4503 | static xtensa_opcode_internal bnez_n_opcode = { | |
4504 | "bnez.n", | |
4505 | 2, | |
4506 | bnez_n_template, | |
4507 | &bz6_iclass | |
4508 | }; | |
4509 | ||
4510 | static xtensa_opcode_internal bnone_opcode = { | |
4511 | "bnone", | |
4512 | 3, | |
4513 | bnone_template, | |
4514 | &bst8_iclass | |
4515 | }; | |
4516 | ||
4517 | static xtensa_opcode_internal break_opcode = { | |
4518 | "break", | |
4519 | 3, | |
4520 | break_template, | |
4521 | &break_iclass | |
4522 | }; | |
4523 | ||
4524 | static xtensa_opcode_internal break_n_opcode = { | |
4525 | "break.n", | |
4526 | 2, | |
4527 | break_n_template, | |
4528 | &break_n_iclass | |
4529 | }; | |
4530 | ||
4531 | static xtensa_opcode_internal call0_opcode = { | |
4532 | "call0", | |
4533 | 3, | |
4534 | call0_template, | |
4535 | &call_iclass | |
4536 | }; | |
4537 | ||
4538 | static xtensa_opcode_internal call12_opcode = { | |
4539 | "call12", | |
4540 | 3, | |
4541 | call12_template, | |
4542 | &call12_iclass | |
4543 | }; | |
4544 | ||
4545 | static xtensa_opcode_internal call4_opcode = { | |
4546 | "call4", | |
4547 | 3, | |
4548 | call4_template, | |
4549 | &call4_iclass | |
4550 | }; | |
4551 | ||
4552 | static xtensa_opcode_internal call8_opcode = { | |
4553 | "call8", | |
4554 | 3, | |
4555 | call8_template, | |
4556 | &call8_iclass | |
4557 | }; | |
4558 | ||
4559 | static xtensa_opcode_internal callx0_opcode = { | |
4560 | "callx0", | |
4561 | 3, | |
4562 | callx0_template, | |
4563 | &callx_iclass | |
4564 | }; | |
4565 | ||
4566 | static xtensa_opcode_internal callx12_opcode = { | |
4567 | "callx12", | |
4568 | 3, | |
4569 | callx12_template, | |
4570 | &callx12_iclass | |
4571 | }; | |
4572 | ||
4573 | static xtensa_opcode_internal callx4_opcode = { | |
4574 | "callx4", | |
4575 | 3, | |
4576 | callx4_template, | |
4577 | &callx4_iclass | |
4578 | }; | |
4579 | ||
4580 | static xtensa_opcode_internal callx8_opcode = { | |
4581 | "callx8", | |
4582 | 3, | |
4583 | callx8_template, | |
4584 | &callx8_iclass | |
4585 | }; | |
4586 | ||
4587 | static xtensa_opcode_internal dhi_opcode = { | |
4588 | "dhi", | |
4589 | 3, | |
4590 | dhi_template, | |
4591 | &dcache_iclass | |
4592 | }; | |
4593 | ||
4594 | static xtensa_opcode_internal dhwb_opcode = { | |
4595 | "dhwb", | |
4596 | 3, | |
4597 | dhwb_template, | |
4598 | &dcache_iclass | |
4599 | }; | |
4600 | ||
4601 | static xtensa_opcode_internal dhwbi_opcode = { | |
4602 | "dhwbi", | |
4603 | 3, | |
4604 | dhwbi_template, | |
4605 | &dcache_iclass | |
4606 | }; | |
4607 | ||
4608 | static xtensa_opcode_internal dii_opcode = { | |
4609 | "dii", | |
4610 | 3, | |
4611 | dii_template, | |
4612 | &dcache_iclass | |
4613 | }; | |
4614 | ||
4615 | static xtensa_opcode_internal diwb_opcode = { | |
4616 | "diwb", | |
4617 | 3, | |
4618 | diwb_template, | |
4619 | &dce_iclass | |
4620 | }; | |
4621 | ||
4622 | static xtensa_opcode_internal diwbi_opcode = { | |
4623 | "diwbi", | |
4624 | 3, | |
4625 | diwbi_template, | |
4626 | &dce_iclass | |
4627 | }; | |
4628 | ||
4629 | static xtensa_opcode_internal dpfr_opcode = { | |
4630 | "dpfr", | |
4631 | 3, | |
4632 | dpfr_template, | |
4633 | &dpf_iclass | |
4634 | }; | |
4635 | ||
4636 | static xtensa_opcode_internal dpfro_opcode = { | |
4637 | "dpfro", | |
4638 | 3, | |
4639 | dpfro_template, | |
4640 | &dpf_iclass | |
4641 | }; | |
4642 | ||
4643 | static xtensa_opcode_internal dpfw_opcode = { | |
4644 | "dpfw", | |
4645 | 3, | |
4646 | dpfw_template, | |
4647 | &dpf_iclass | |
4648 | }; | |
4649 | ||
4650 | static xtensa_opcode_internal dpfwo_opcode = { | |
4651 | "dpfwo", | |
4652 | 3, | |
4653 | dpfwo_template, | |
4654 | &dpf_iclass | |
4655 | }; | |
4656 | ||
4657 | static xtensa_opcode_internal dsync_opcode = { | |
4658 | "dsync", | |
4659 | 3, | |
4660 | dsync_template, | |
4661 | &sync_iclass | |
4662 | }; | |
4663 | ||
4664 | static xtensa_opcode_internal entry_opcode = { | |
4665 | "entry", | |
4666 | 3, | |
4667 | entry_template, | |
4668 | &entry_iclass | |
4669 | }; | |
4670 | ||
4671 | static xtensa_opcode_internal esync_opcode = { | |
4672 | "esync", | |
4673 | 3, | |
4674 | esync_template, | |
4675 | &sync_iclass | |
4676 | }; | |
4677 | ||
4678 | static xtensa_opcode_internal excw_opcode = { | |
4679 | "excw", | |
4680 | 3, | |
4681 | excw_template, | |
4682 | &excw_iclass | |
4683 | }; | |
4684 | ||
4685 | static xtensa_opcode_internal extui_opcode = { | |
4686 | "extui", | |
4687 | 3, | |
4688 | extui_template, | |
4689 | &exti_iclass | |
4690 | }; | |
4691 | ||
4692 | static xtensa_opcode_internal idtlb_opcode = { | |
4693 | "idtlb", | |
4694 | 3, | |
4695 | idtlb_template, | |
4696 | &itlb_iclass | |
4697 | }; | |
4698 | ||
4699 | static xtensa_opcode_internal idtlba_opcode = { | |
4700 | "idtlba", | |
4701 | 3, | |
4702 | idtlba_template, | |
4703 | &itlba_iclass | |
4704 | }; | |
4705 | ||
4706 | static xtensa_opcode_internal ihi_opcode = { | |
4707 | "ihi", | |
4708 | 3, | |
4709 | ihi_template, | |
4710 | &icache_iclass | |
4711 | }; | |
4712 | ||
4713 | static xtensa_opcode_internal iii_opcode = { | |
4714 | "iii", | |
4715 | 3, | |
4716 | iii_template, | |
4717 | &icache_iclass | |
4718 | }; | |
4719 | ||
4720 | static xtensa_opcode_internal iitlb_opcode = { | |
4721 | "iitlb", | |
4722 | 3, | |
4723 | iitlb_template, | |
4724 | &itlb_iclass | |
4725 | }; | |
4726 | ||
4727 | static xtensa_opcode_internal iitlba_opcode = { | |
4728 | "iitlba", | |
4729 | 3, | |
4730 | iitlba_template, | |
4731 | &itlba_iclass | |
4732 | }; | |
4733 | ||
4734 | static xtensa_opcode_internal ipf_opcode = { | |
4735 | "ipf", | |
4736 | 3, | |
4737 | ipf_template, | |
4738 | &icache_iclass | |
4739 | }; | |
4740 | ||
4741 | static xtensa_opcode_internal isync_opcode = { | |
4742 | "isync", | |
4743 | 3, | |
4744 | isync_template, | |
4745 | &sync_iclass | |
4746 | }; | |
4747 | ||
4748 | static xtensa_opcode_internal j_opcode = { | |
4749 | "j", | |
4750 | 3, | |
4751 | j_template, | |
4752 | &jump_iclass | |
4753 | }; | |
4754 | ||
4755 | static xtensa_opcode_internal jx_opcode = { | |
4756 | "jx", | |
4757 | 3, | |
4758 | jx_template, | |
4759 | &jumpx_iclass | |
4760 | }; | |
4761 | ||
4762 | static xtensa_opcode_internal l16si_opcode = { | |
4763 | "l16si", | |
4764 | 3, | |
4765 | l16si_template, | |
4766 | &l16i_iclass | |
4767 | }; | |
4768 | ||
4769 | static xtensa_opcode_internal l16ui_opcode = { | |
4770 | "l16ui", | |
4771 | 3, | |
4772 | l16ui_template, | |
4773 | &l16i_iclass | |
4774 | }; | |
4775 | ||
4776 | static xtensa_opcode_internal l32e_opcode = { | |
4777 | "l32e", | |
4778 | 3, | |
4779 | l32e_template, | |
4780 | &l32e_iclass | |
4781 | }; | |
4782 | ||
4783 | static xtensa_opcode_internal l32i_opcode = { | |
4784 | "l32i", | |
4785 | 3, | |
4786 | l32i_template, | |
4787 | &l32i_iclass | |
4788 | }; | |
4789 | ||
4790 | static xtensa_opcode_internal l32i_n_opcode = { | |
4791 | "l32i.n", | |
4792 | 2, | |
4793 | l32i_n_template, | |
4794 | &loadi4_iclass | |
4795 | }; | |
4796 | ||
4797 | static xtensa_opcode_internal l32r_opcode = { | |
4798 | "l32r", | |
4799 | 3, | |
4800 | l32r_template, | |
4801 | &l32r_iclass | |
4802 | }; | |
4803 | ||
4804 | static xtensa_opcode_internal l8ui_opcode = { | |
4805 | "l8ui", | |
4806 | 3, | |
4807 | l8ui_template, | |
4808 | &l8i_iclass | |
4809 | }; | |
4810 | ||
4811 | static xtensa_opcode_internal ldct_opcode = { | |
4812 | "ldct", | |
4813 | 3, | |
4814 | ldct_template, | |
4815 | &actl_iclass | |
4816 | }; | |
4817 | ||
4818 | static xtensa_opcode_internal lict_opcode = { | |
4819 | "lict", | |
4820 | 3, | |
4821 | lict_template, | |
4822 | &actl_iclass | |
4823 | }; | |
4824 | ||
4825 | static xtensa_opcode_internal licw_opcode = { | |
4826 | "licw", | |
4827 | 3, | |
4828 | licw_template, | |
4829 | &actl_iclass | |
4830 | }; | |
4831 | ||
4832 | static xtensa_opcode_internal loop_opcode = { | |
4833 | "loop", | |
4834 | 3, | |
4835 | loop_template, | |
4836 | &loop_iclass | |
4837 | }; | |
4838 | ||
4839 | static xtensa_opcode_internal loopgtz_opcode = { | |
4840 | "loopgtz", | |
4841 | 3, | |
4842 | loopgtz_template, | |
4843 | &loop_iclass | |
4844 | }; | |
4845 | ||
4846 | static xtensa_opcode_internal loopnez_opcode = { | |
4847 | "loopnez", | |
4848 | 3, | |
4849 | loopnez_template, | |
4850 | &loop_iclass | |
4851 | }; | |
4852 | ||
4853 | static xtensa_opcode_internal memw_opcode = { | |
4854 | "memw", | |
4855 | 3, | |
4856 | memw_template, | |
4857 | &sync_iclass | |
4858 | }; | |
4859 | ||
4860 | static xtensa_opcode_internal mov_n_opcode = { | |
4861 | "mov.n", | |
4862 | 2, | |
4863 | mov_n_template, | |
4864 | &mov_n_iclass | |
4865 | }; | |
4866 | ||
4867 | static xtensa_opcode_internal moveqz_opcode = { | |
4868 | "moveqz", | |
4869 | 3, | |
4870 | moveqz_template, | |
4871 | &movz_iclass | |
4872 | }; | |
4873 | ||
4874 | static xtensa_opcode_internal movgez_opcode = { | |
4875 | "movgez", | |
4876 | 3, | |
4877 | movgez_template, | |
4878 | &movz_iclass | |
4879 | }; | |
4880 | ||
4881 | static xtensa_opcode_internal movi_opcode = { | |
4882 | "movi", | |
4883 | 3, | |
4884 | movi_template, | |
4885 | &movi_iclass | |
4886 | }; | |
4887 | ||
4888 | static xtensa_opcode_internal movi_n_opcode = { | |
4889 | "movi.n", | |
4890 | 2, | |
4891 | movi_n_template, | |
4892 | &movi_n_iclass | |
4893 | }; | |
4894 | ||
4895 | static xtensa_opcode_internal movltz_opcode = { | |
4896 | "movltz", | |
4897 | 3, | |
4898 | movltz_template, | |
4899 | &movz_iclass | |
4900 | }; | |
4901 | ||
4902 | static xtensa_opcode_internal movnez_opcode = { | |
4903 | "movnez", | |
4904 | 3, | |
4905 | movnez_template, | |
4906 | &movz_iclass | |
4907 | }; | |
4908 | ||
4909 | static xtensa_opcode_internal movsp_opcode = { | |
4910 | "movsp", | |
4911 | 3, | |
4912 | movsp_template, | |
4913 | &movsp_iclass | |
4914 | }; | |
4915 | ||
4916 | static xtensa_opcode_internal neg_opcode = { | |
4917 | "neg", | |
4918 | 3, | |
4919 | neg_template, | |
4920 | &neg_iclass | |
4921 | }; | |
4922 | ||
4923 | static xtensa_opcode_internal nop_n_opcode = { | |
4924 | "nop.n", | |
4925 | 2, | |
4926 | nop_n_template, | |
4927 | &nopn_iclass | |
4928 | }; | |
4929 | ||
4930 | static xtensa_opcode_internal nsa_opcode = { | |
4931 | "nsa", | |
4932 | 3, | |
4933 | nsa_template, | |
4934 | &nsa_iclass | |
4935 | }; | |
4936 | ||
4937 | static xtensa_opcode_internal nsau_opcode = { | |
4938 | "nsau", | |
4939 | 3, | |
4940 | nsau_template, | |
4941 | &nsa_iclass | |
4942 | }; | |
4943 | ||
4944 | static xtensa_opcode_internal or_opcode = { | |
4945 | "or", | |
4946 | 3, | |
4947 | or_template, | |
4948 | &bit_iclass | |
4949 | }; | |
4950 | ||
4951 | static xtensa_opcode_internal pdtlb_opcode = { | |
4952 | "pdtlb", | |
4953 | 3, | |
4954 | pdtlb_template, | |
4955 | &rtlb_iclass | |
4956 | }; | |
4957 | ||
4958 | static xtensa_opcode_internal pitlb_opcode = { | |
4959 | "pitlb", | |
4960 | 3, | |
4961 | pitlb_template, | |
4962 | &rtlb_iclass | |
4963 | }; | |
4964 | ||
4965 | static xtensa_opcode_internal rdtlb0_opcode = { | |
4966 | "rdtlb0", | |
4967 | 3, | |
4968 | rdtlb0_template, | |
4969 | &rtlb_iclass | |
4970 | }; | |
4971 | ||
4972 | static xtensa_opcode_internal rdtlb1_opcode = { | |
4973 | "rdtlb1", | |
4974 | 3, | |
4975 | rdtlb1_template, | |
4976 | &rtlb_iclass | |
4977 | }; | |
4978 | ||
4979 | static xtensa_opcode_internal ret_opcode = { | |
4980 | "ret", | |
4981 | 3, | |
4982 | ret_template, | |
4983 | &return_iclass | |
4984 | }; | |
4985 | ||
4986 | static xtensa_opcode_internal ret_n_opcode = { | |
4987 | "ret.n", | |
4988 | 2, | |
4989 | ret_n_template, | |
4990 | &retn_iclass | |
4991 | }; | |
4992 | ||
4993 | static xtensa_opcode_internal retw_opcode = { | |
4994 | "retw", | |
4995 | 3, | |
4996 | retw_template, | |
4997 | &return_iclass | |
4998 | }; | |
4999 | ||
5000 | static xtensa_opcode_internal retw_n_opcode = { | |
5001 | "retw.n", | |
5002 | 2, | |
5003 | retw_n_template, | |
5004 | &retn_iclass | |
5005 | }; | |
5006 | ||
5007 | static xtensa_opcode_internal rfde_opcode = { | |
5008 | "rfde", | |
5009 | 3, | |
5010 | rfde_template, | |
5011 | &rfe_iclass | |
5012 | }; | |
5013 | ||
5014 | static xtensa_opcode_internal rfe_opcode = { | |
5015 | "rfe", | |
5016 | 3, | |
5017 | rfe_template, | |
5018 | &rfe_iclass | |
5019 | }; | |
5020 | ||
5021 | static xtensa_opcode_internal rfi_opcode = { | |
5022 | "rfi", | |
5023 | 3, | |
5024 | rfi_template, | |
5025 | &rfi_iclass | |
5026 | }; | |
5027 | ||
5028 | static xtensa_opcode_internal rfwo_opcode = { | |
5029 | "rfwo", | |
5030 | 3, | |
5031 | rfwo_template, | |
5032 | &rfe_iclass | |
5033 | }; | |
5034 | ||
5035 | static xtensa_opcode_internal rfwu_opcode = { | |
5036 | "rfwu", | |
5037 | 3, | |
5038 | rfwu_template, | |
5039 | &rfe_iclass | |
5040 | }; | |
5041 | ||
5042 | static xtensa_opcode_internal ritlb0_opcode = { | |
5043 | "ritlb0", | |
5044 | 3, | |
5045 | ritlb0_template, | |
5046 | &rtlb_iclass | |
5047 | }; | |
5048 | ||
5049 | static xtensa_opcode_internal ritlb1_opcode = { | |
5050 | "ritlb1", | |
5051 | 3, | |
5052 | ritlb1_template, | |
5053 | &rtlb_iclass | |
5054 | }; | |
5055 | ||
5056 | static xtensa_opcode_internal rotw_opcode = { | |
5057 | "rotw", | |
5058 | 3, | |
5059 | rotw_template, | |
5060 | &rotw_iclass | |
5061 | }; | |
5062 | ||
5063 | static xtensa_opcode_internal rsil_opcode = { | |
5064 | "rsil", | |
5065 | 3, | |
5066 | rsil_template, | |
5067 | &rsil_iclass | |
5068 | }; | |
5069 | ||
5070 | static xtensa_opcode_internal rsr_opcode = { | |
5071 | "rsr", | |
5072 | 3, | |
5073 | rsr_template, | |
5074 | &rsr_iclass | |
5075 | }; | |
5076 | ||
5077 | static xtensa_opcode_internal rsync_opcode = { | |
5078 | "rsync", | |
5079 | 3, | |
5080 | rsync_template, | |
5081 | &sync_iclass | |
5082 | }; | |
5083 | ||
5084 | static xtensa_opcode_internal s16i_opcode = { | |
5085 | "s16i", | |
5086 | 3, | |
5087 | s16i_template, | |
5088 | &s16i_iclass | |
5089 | }; | |
5090 | ||
5091 | static xtensa_opcode_internal s32e_opcode = { | |
5092 | "s32e", | |
5093 | 3, | |
5094 | s32e_template, | |
5095 | &s32e_iclass | |
5096 | }; | |
5097 | ||
5098 | static xtensa_opcode_internal s32i_opcode = { | |
5099 | "s32i", | |
5100 | 3, | |
5101 | s32i_template, | |
5102 | &s32i_iclass | |
5103 | }; | |
5104 | ||
5105 | static xtensa_opcode_internal s32i_n_opcode = { | |
5106 | "s32i.n", | |
5107 | 2, | |
5108 | s32i_n_template, | |
5109 | &storei4_iclass | |
5110 | }; | |
5111 | ||
5112 | static xtensa_opcode_internal s8i_opcode = { | |
5113 | "s8i", | |
5114 | 3, | |
5115 | s8i_template, | |
5116 | &s8i_iclass | |
5117 | }; | |
5118 | ||
5119 | static xtensa_opcode_internal sdct_opcode = { | |
5120 | "sdct", | |
5121 | 3, | |
5122 | sdct_template, | |
5123 | &acts_iclass | |
5124 | }; | |
5125 | ||
5126 | static xtensa_opcode_internal sict_opcode = { | |
5127 | "sict", | |
5128 | 3, | |
5129 | sict_template, | |
5130 | &acts_iclass | |
5131 | }; | |
5132 | ||
5133 | static xtensa_opcode_internal sicw_opcode = { | |
5134 | "sicw", | |
5135 | 3, | |
5136 | sicw_template, | |
5137 | &acts_iclass | |
5138 | }; | |
5139 | ||
5140 | static xtensa_opcode_internal simcall_opcode = { | |
5141 | "simcall", | |
5142 | 3, | |
5143 | simcall_template, | |
5144 | &syscall_iclass | |
5145 | }; | |
5146 | ||
5147 | static xtensa_opcode_internal sll_opcode = { | |
5148 | "sll", | |
5149 | 3, | |
5150 | sll_template, | |
5151 | &shifts_iclass | |
5152 | }; | |
5153 | ||
5154 | static xtensa_opcode_internal slli_opcode = { | |
5155 | "slli", | |
5156 | 3, | |
5157 | slli_template, | |
5158 | &slli_iclass | |
5159 | }; | |
5160 | ||
5161 | static xtensa_opcode_internal sra_opcode = { | |
5162 | "sra", | |
5163 | 3, | |
5164 | sra_template, | |
5165 | &shiftt_iclass | |
5166 | }; | |
5167 | ||
5168 | static xtensa_opcode_internal srai_opcode = { | |
5169 | "srai", | |
5170 | 3, | |
5171 | srai_template, | |
5172 | &srai_iclass | |
5173 | }; | |
5174 | ||
5175 | static xtensa_opcode_internal src_opcode = { | |
5176 | "src", | |
5177 | 3, | |
5178 | src_template, | |
5179 | &shiftst_iclass | |
5180 | }; | |
5181 | ||
5182 | static xtensa_opcode_internal srl_opcode = { | |
5183 | "srl", | |
5184 | 3, | |
5185 | srl_template, | |
5186 | &shiftt_iclass | |
5187 | }; | |
5188 | ||
5189 | static xtensa_opcode_internal srli_opcode = { | |
5190 | "srli", | |
5191 | 3, | |
5192 | srli_template, | |
5193 | &srli_iclass | |
5194 | }; | |
5195 | ||
5196 | static xtensa_opcode_internal ssa8b_opcode = { | |
5197 | "ssa8b", | |
5198 | 3, | |
5199 | ssa8b_template, | |
5200 | &sar_iclass | |
5201 | }; | |
5202 | ||
5203 | static xtensa_opcode_internal ssa8l_opcode = { | |
5204 | "ssa8l", | |
5205 | 3, | |
5206 | ssa8l_template, | |
5207 | &sar_iclass | |
5208 | }; | |
5209 | ||
5210 | static xtensa_opcode_internal ssai_opcode = { | |
5211 | "ssai", | |
5212 | 3, | |
5213 | ssai_template, | |
5214 | &sari_iclass | |
5215 | }; | |
5216 | ||
5217 | static xtensa_opcode_internal ssl_opcode = { | |
5218 | "ssl", | |
5219 | 3, | |
5220 | ssl_template, | |
5221 | &sar_iclass | |
5222 | }; | |
5223 | ||
5224 | static xtensa_opcode_internal ssr_opcode = { | |
5225 | "ssr", | |
5226 | 3, | |
5227 | ssr_template, | |
5228 | &sar_iclass | |
5229 | }; | |
5230 | ||
5231 | static xtensa_opcode_internal sub_opcode = { | |
5232 | "sub", | |
5233 | 3, | |
5234 | sub_template, | |
5235 | &addsub_iclass | |
5236 | }; | |
5237 | ||
5238 | static xtensa_opcode_internal subx2_opcode = { | |
5239 | "subx2", | |
5240 | 3, | |
5241 | subx2_template, | |
5242 | &addsub_iclass | |
5243 | }; | |
5244 | ||
5245 | static xtensa_opcode_internal subx4_opcode = { | |
5246 | "subx4", | |
5247 | 3, | |
5248 | subx4_template, | |
5249 | &addsub_iclass | |
5250 | }; | |
5251 | ||
5252 | static xtensa_opcode_internal subx8_opcode = { | |
5253 | "subx8", | |
5254 | 3, | |
5255 | subx8_template, | |
5256 | &addsub_iclass | |
5257 | }; | |
5258 | ||
5259 | static xtensa_opcode_internal syscall_opcode = { | |
5260 | "syscall", | |
5261 | 3, | |
5262 | syscall_template, | |
5263 | &syscall_iclass | |
5264 | }; | |
5265 | ||
5266 | static xtensa_opcode_internal waiti_opcode = { | |
5267 | "waiti", | |
5268 | 3, | |
5269 | waiti_template, | |
5270 | &wait_iclass | |
5271 | }; | |
5272 | ||
5273 | static xtensa_opcode_internal wdtlb_opcode = { | |
5274 | "wdtlb", | |
5275 | 3, | |
5276 | wdtlb_template, | |
5277 | &wtlb_iclass | |
5278 | }; | |
5279 | ||
5280 | static xtensa_opcode_internal witlb_opcode = { | |
5281 | "witlb", | |
5282 | 3, | |
5283 | witlb_template, | |
5284 | &wtlb_iclass | |
5285 | }; | |
5286 | ||
5287 | static xtensa_opcode_internal wsr_opcode = { | |
5288 | "wsr", | |
5289 | 3, | |
5290 | wsr_template, | |
5291 | &wsr_iclass | |
5292 | }; | |
5293 | ||
5294 | static xtensa_opcode_internal xor_opcode = { | |
5295 | "xor", | |
5296 | 3, | |
5297 | xor_template, | |
5298 | &bit_iclass | |
5299 | }; | |
5300 | ||
5301 | static xtensa_opcode_internal xsr_opcode = { | |
5302 | "xsr", | |
5303 | 3, | |
5304 | xsr_template, | |
5305 | &xsr_iclass | |
5306 | }; | |
5307 | ||
5308 | static xtensa_opcode_internal * opcodes[149] = { | |
5309 | &abs_opcode, | |
5310 | &add_opcode, | |
5311 | &add_n_opcode, | |
5312 | &addi_opcode, | |
5313 | &addi_n_opcode, | |
5314 | &addmi_opcode, | |
5315 | &addx2_opcode, | |
5316 | &addx4_opcode, | |
5317 | &addx8_opcode, | |
5318 | &and_opcode, | |
5319 | &ball_opcode, | |
5320 | &bany_opcode, | |
5321 | &bbc_opcode, | |
5322 | &bbci_opcode, | |
5323 | &bbs_opcode, | |
5324 | &bbsi_opcode, | |
5325 | &beq_opcode, | |
5326 | &beqi_opcode, | |
5327 | &beqz_opcode, | |
5328 | &beqz_n_opcode, | |
5329 | &bge_opcode, | |
5330 | &bgei_opcode, | |
5331 | &bgeu_opcode, | |
5332 | &bgeui_opcode, | |
5333 | &bgez_opcode, | |
5334 | &blt_opcode, | |
5335 | &blti_opcode, | |
5336 | &bltu_opcode, | |
5337 | &bltui_opcode, | |
5338 | &bltz_opcode, | |
5339 | &bnall_opcode, | |
5340 | &bne_opcode, | |
5341 | &bnei_opcode, | |
5342 | &bnez_opcode, | |
5343 | &bnez_n_opcode, | |
5344 | &bnone_opcode, | |
5345 | &break_opcode, | |
5346 | &break_n_opcode, | |
5347 | &call0_opcode, | |
5348 | &call12_opcode, | |
5349 | &call4_opcode, | |
5350 | &call8_opcode, | |
5351 | &callx0_opcode, | |
5352 | &callx12_opcode, | |
5353 | &callx4_opcode, | |
5354 | &callx8_opcode, | |
5355 | &dhi_opcode, | |
5356 | &dhwb_opcode, | |
5357 | &dhwbi_opcode, | |
5358 | &dii_opcode, | |
5359 | &diwb_opcode, | |
5360 | &diwbi_opcode, | |
5361 | &dpfr_opcode, | |
5362 | &dpfro_opcode, | |
5363 | &dpfw_opcode, | |
5364 | &dpfwo_opcode, | |
5365 | &dsync_opcode, | |
5366 | &entry_opcode, | |
5367 | &esync_opcode, | |
5368 | &excw_opcode, | |
5369 | &extui_opcode, | |
5370 | &idtlb_opcode, | |
5371 | &idtlba_opcode, | |
5372 | &ihi_opcode, | |
5373 | &iii_opcode, | |
5374 | &iitlb_opcode, | |
5375 | &iitlba_opcode, | |
5376 | &ipf_opcode, | |
5377 | &isync_opcode, | |
5378 | &j_opcode, | |
5379 | &jx_opcode, | |
5380 | &l16si_opcode, | |
5381 | &l16ui_opcode, | |
5382 | &l32e_opcode, | |
5383 | &l32i_opcode, | |
5384 | &l32i_n_opcode, | |
5385 | &l32r_opcode, | |
5386 | &l8ui_opcode, | |
5387 | &ldct_opcode, | |
5388 | &lict_opcode, | |
5389 | &licw_opcode, | |
5390 | &loop_opcode, | |
5391 | &loopgtz_opcode, | |
5392 | &loopnez_opcode, | |
5393 | &memw_opcode, | |
5394 | &mov_n_opcode, | |
5395 | &moveqz_opcode, | |
5396 | &movgez_opcode, | |
5397 | &movi_opcode, | |
5398 | &movi_n_opcode, | |
5399 | &movltz_opcode, | |
5400 | &movnez_opcode, | |
5401 | &movsp_opcode, | |
5402 | &neg_opcode, | |
5403 | &nop_n_opcode, | |
5404 | &nsa_opcode, | |
5405 | &nsau_opcode, | |
5406 | &or_opcode, | |
5407 | &pdtlb_opcode, | |
5408 | &pitlb_opcode, | |
5409 | &rdtlb0_opcode, | |
5410 | &rdtlb1_opcode, | |
5411 | &ret_opcode, | |
5412 | &ret_n_opcode, | |
5413 | &retw_opcode, | |
5414 | &retw_n_opcode, | |
5415 | &rfde_opcode, | |
5416 | &rfe_opcode, | |
5417 | &rfi_opcode, | |
5418 | &rfwo_opcode, | |
5419 | &rfwu_opcode, | |
5420 | &ritlb0_opcode, | |
5421 | &ritlb1_opcode, | |
5422 | &rotw_opcode, | |
5423 | &rsil_opcode, | |
5424 | &rsr_opcode, | |
5425 | &rsync_opcode, | |
5426 | &s16i_opcode, | |
5427 | &s32e_opcode, | |
5428 | &s32i_opcode, | |
5429 | &s32i_n_opcode, | |
5430 | &s8i_opcode, | |
5431 | &sdct_opcode, | |
5432 | &sict_opcode, | |
5433 | &sicw_opcode, | |
5434 | &simcall_opcode, | |
5435 | &sll_opcode, | |
5436 | &slli_opcode, | |
5437 | &sra_opcode, | |
5438 | &srai_opcode, | |
5439 | &src_opcode, | |
5440 | &srl_opcode, | |
5441 | &srli_opcode, | |
5442 | &ssa8b_opcode, | |
5443 | &ssa8l_opcode, | |
5444 | &ssai_opcode, | |
5445 | &ssl_opcode, | |
5446 | &ssr_opcode, | |
5447 | &sub_opcode, | |
5448 | &subx2_opcode, | |
5449 | &subx4_opcode, | |
5450 | &subx8_opcode, | |
5451 | &syscall_opcode, | |
5452 | &waiti_opcode, | |
5453 | &wdtlb_opcode, | |
5454 | &witlb_opcode, | |
5455 | &wsr_opcode, | |
5456 | &xor_opcode, | |
5457 | &xsr_opcode | |
5458 | }; | |
5459 | ||
5460 | xtensa_opcode_internal ** | |
5461 | get_opcodes (void) | |
5462 | { | |
5463 | return &opcodes[0]; | |
5464 | } | |
5465 | ||
5466 | const int | |
5467 | get_num_opcodes (void) | |
5468 | { | |
5469 | return 149; | |
5470 | } | |
5471 | ||
5472 | #define xtensa_abs_op 0 | |
5473 | #define xtensa_add_op 1 | |
5474 | #define xtensa_add_n_op 2 | |
5475 | #define xtensa_addi_op 3 | |
5476 | #define xtensa_addi_n_op 4 | |
5477 | #define xtensa_addmi_op 5 | |
5478 | #define xtensa_addx2_op 6 | |
5479 | #define xtensa_addx4_op 7 | |
5480 | #define xtensa_addx8_op 8 | |
5481 | #define xtensa_and_op 9 | |
5482 | #define xtensa_ball_op 10 | |
5483 | #define xtensa_bany_op 11 | |
5484 | #define xtensa_bbc_op 12 | |
5485 | #define xtensa_bbci_op 13 | |
5486 | #define xtensa_bbs_op 14 | |
5487 | #define xtensa_bbsi_op 15 | |
5488 | #define xtensa_beq_op 16 | |
5489 | #define xtensa_beqi_op 17 | |
5490 | #define xtensa_beqz_op 18 | |
5491 | #define xtensa_beqz_n_op 19 | |
5492 | #define xtensa_bge_op 20 | |
5493 | #define xtensa_bgei_op 21 | |
5494 | #define xtensa_bgeu_op 22 | |
5495 | #define xtensa_bgeui_op 23 | |
5496 | #define xtensa_bgez_op 24 | |
5497 | #define xtensa_blt_op 25 | |
5498 | #define xtensa_blti_op 26 | |
5499 | #define xtensa_bltu_op 27 | |
5500 | #define xtensa_bltui_op 28 | |
5501 | #define xtensa_bltz_op 29 | |
5502 | #define xtensa_bnall_op 30 | |
5503 | #define xtensa_bne_op 31 | |
5504 | #define xtensa_bnei_op 32 | |
5505 | #define xtensa_bnez_op 33 | |
5506 | #define xtensa_bnez_n_op 34 | |
5507 | #define xtensa_bnone_op 35 | |
5508 | #define xtensa_break_op 36 | |
5509 | #define xtensa_break_n_op 37 | |
5510 | #define xtensa_call0_op 38 | |
5511 | #define xtensa_call12_op 39 | |
5512 | #define xtensa_call4_op 40 | |
5513 | #define xtensa_call8_op 41 | |
5514 | #define xtensa_callx0_op 42 | |
5515 | #define xtensa_callx12_op 43 | |
5516 | #define xtensa_callx4_op 44 | |
5517 | #define xtensa_callx8_op 45 | |
5518 | #define xtensa_dhi_op 46 | |
5519 | #define xtensa_dhwb_op 47 | |
5520 | #define xtensa_dhwbi_op 48 | |
5521 | #define xtensa_dii_op 49 | |
5522 | #define xtensa_diwb_op 50 | |
5523 | #define xtensa_diwbi_op 51 | |
5524 | #define xtensa_dpfr_op 52 | |
5525 | #define xtensa_dpfro_op 53 | |
5526 | #define xtensa_dpfw_op 54 | |
5527 | #define xtensa_dpfwo_op 55 | |
5528 | #define xtensa_dsync_op 56 | |
5529 | #define xtensa_entry_op 57 | |
5530 | #define xtensa_esync_op 58 | |
5531 | #define xtensa_excw_op 59 | |
5532 | #define xtensa_extui_op 60 | |
5533 | #define xtensa_idtlb_op 61 | |
5534 | #define xtensa_idtlba_op 62 | |
5535 | #define xtensa_ihi_op 63 | |
5536 | #define xtensa_iii_op 64 | |
5537 | #define xtensa_iitlb_op 65 | |
5538 | #define xtensa_iitlba_op 66 | |
5539 | #define xtensa_ipf_op 67 | |
5540 | #define xtensa_isync_op 68 | |
5541 | #define xtensa_j_op 69 | |
5542 | #define xtensa_jx_op 70 | |
5543 | #define xtensa_l16si_op 71 | |
5544 | #define xtensa_l16ui_op 72 | |
5545 | #define xtensa_l32e_op 73 | |
5546 | #define xtensa_l32i_op 74 | |
5547 | #define xtensa_l32i_n_op 75 | |
5548 | #define xtensa_l32r_op 76 | |
5549 | #define xtensa_l8ui_op 77 | |
5550 | #define xtensa_ldct_op 78 | |
5551 | #define xtensa_lict_op 79 | |
5552 | #define xtensa_licw_op 80 | |
5553 | #define xtensa_loop_op 81 | |
5554 | #define xtensa_loopgtz_op 82 | |
5555 | #define xtensa_loopnez_op 83 | |
5556 | #define xtensa_memw_op 84 | |
5557 | #define xtensa_mov_n_op 85 | |
5558 | #define xtensa_moveqz_op 86 | |
5559 | #define xtensa_movgez_op 87 | |
5560 | #define xtensa_movi_op 88 | |
5561 | #define xtensa_movi_n_op 89 | |
5562 | #define xtensa_movltz_op 90 | |
5563 | #define xtensa_movnez_op 91 | |
5564 | #define xtensa_movsp_op 92 | |
5565 | #define xtensa_neg_op 93 | |
5566 | #define xtensa_nop_n_op 94 | |
5567 | #define xtensa_nsa_op 95 | |
5568 | #define xtensa_nsau_op 96 | |
5569 | #define xtensa_or_op 97 | |
5570 | #define xtensa_pdtlb_op 98 | |
5571 | #define xtensa_pitlb_op 99 | |
5572 | #define xtensa_rdtlb0_op 100 | |
5573 | #define xtensa_rdtlb1_op 101 | |
5574 | #define xtensa_ret_op 102 | |
5575 | #define xtensa_ret_n_op 103 | |
5576 | #define xtensa_retw_op 104 | |
5577 | #define xtensa_retw_n_op 105 | |
5578 | #define xtensa_rfde_op 106 | |
5579 | #define xtensa_rfe_op 107 | |
5580 | #define xtensa_rfi_op 108 | |
5581 | #define xtensa_rfwo_op 109 | |
5582 | #define xtensa_rfwu_op 110 | |
5583 | #define xtensa_ritlb0_op 111 | |
5584 | #define xtensa_ritlb1_op 112 | |
5585 | #define xtensa_rotw_op 113 | |
5586 | #define xtensa_rsil_op 114 | |
5587 | #define xtensa_rsr_op 115 | |
5588 | #define xtensa_rsync_op 116 | |
5589 | #define xtensa_s16i_op 117 | |
5590 | #define xtensa_s32e_op 118 | |
5591 | #define xtensa_s32i_op 119 | |
5592 | #define xtensa_s32i_n_op 120 | |
5593 | #define xtensa_s8i_op 121 | |
5594 | #define xtensa_sdct_op 122 | |
5595 | #define xtensa_sict_op 123 | |
5596 | #define xtensa_sicw_op 124 | |
5597 | #define xtensa_simcall_op 125 | |
5598 | #define xtensa_sll_op 126 | |
5599 | #define xtensa_slli_op 127 | |
5600 | #define xtensa_sra_op 128 | |
5601 | #define xtensa_srai_op 129 | |
5602 | #define xtensa_src_op 130 | |
5603 | #define xtensa_srl_op 131 | |
5604 | #define xtensa_srli_op 132 | |
5605 | #define xtensa_ssa8b_op 133 | |
5606 | #define xtensa_ssa8l_op 134 | |
5607 | #define xtensa_ssai_op 135 | |
5608 | #define xtensa_ssl_op 136 | |
5609 | #define xtensa_ssr_op 137 | |
5610 | #define xtensa_sub_op 138 | |
5611 | #define xtensa_subx2_op 139 | |
5612 | #define xtensa_subx4_op 140 | |
5613 | #define xtensa_subx8_op 141 | |
5614 | #define xtensa_syscall_op 142 | |
5615 | #define xtensa_waiti_op 143 | |
5616 | #define xtensa_wdtlb_op 144 | |
5617 | #define xtensa_witlb_op 145 | |
5618 | #define xtensa_wsr_op 146 | |
5619 | #define xtensa_xor_op 147 | |
5620 | #define xtensa_xsr_op 148 | |
5621 | ||
5622 | int | |
5623 | decode_insn (const xtensa_insnbuf insn) | |
5624 | { | |
5625 | switch (get_op0_field (insn)) { | |
5626 | case 0: /* QRST: op0=0000 */ | |
5627 | switch (get_op1_field (insn)) { | |
5628 | case 3: /* RST3: op1=0011 */ | |
5629 | switch (get_op2_field (insn)) { | |
5630 | case 8: /* MOVEQZ: op2=1000 */ | |
5631 | return xtensa_moveqz_op; | |
5632 | case 9: /* MOVNEZ: op2=1001 */ | |
5633 | return xtensa_movnez_op; | |
5634 | case 10: /* MOVLTZ: op2=1010 */ | |
5635 | return xtensa_movltz_op; | |
5636 | case 11: /* MOVGEZ: op2=1011 */ | |
5637 | return xtensa_movgez_op; | |
5638 | case 0: /* RSR: op2=0000 */ | |
5639 | return xtensa_rsr_op; | |
5640 | case 1: /* WSR: op2=0001 */ | |
5641 | return xtensa_wsr_op; | |
5642 | } | |
5643 | break; | |
5644 | case 9: /* LSI4: op1=1001 */ | |
5645 | switch (get_op2_field (insn)) { | |
5646 | case 4: /* S32E: op2=0100 */ | |
5647 | return xtensa_s32e_op; | |
5648 | case 0: /* L32E: op2=0000 */ | |
5649 | return xtensa_l32e_op; | |
5650 | } | |
5651 | break; | |
5652 | case 4: /* EXTUI: op1=010x */ | |
5653 | case 5: /* EXTUI: op1=010x */ | |
5654 | return xtensa_extui_op; | |
5655 | case 0: /* RST0: op1=0000 */ | |
5656 | switch (get_op2_field (insn)) { | |
5657 | case 15: /* SUBX8: op2=1111 */ | |
5658 | return xtensa_subx8_op; | |
5659 | case 0: /* ST0: op2=0000 */ | |
5660 | switch (get_r_field (insn)) { | |
5661 | case 0: /* SNM0: r=0000 */ | |
5662 | switch (get_m_field (insn)) { | |
5663 | case 2: /* JR: m=10 */ | |
5664 | switch (get_n_field (insn)) { | |
5665 | case 0: /* RET: n=00 */ | |
5666 | return xtensa_ret_op; | |
5667 | case 1: /* RETW: n=01 */ | |
5668 | return xtensa_retw_op; | |
5669 | case 2: /* JX: n=10 */ | |
5670 | return xtensa_jx_op; | |
5671 | } | |
5672 | break; | |
5673 | case 3: /* CALLX: m=11 */ | |
5674 | switch (get_n_field (insn)) { | |
5675 | case 0: /* CALLX0: n=00 */ | |
5676 | return xtensa_callx0_op; | |
5677 | case 1: /* CALLX4: n=01 */ | |
5678 | return xtensa_callx4_op; | |
5679 | case 2: /* CALLX8: n=10 */ | |
5680 | return xtensa_callx8_op; | |
5681 | case 3: /* CALLX12: n=11 */ | |
5682 | return xtensa_callx12_op; | |
5683 | } | |
5684 | break; | |
5685 | } | |
5686 | break; | |
5687 | case 1: /* MOVSP: r=0001 */ | |
5688 | return xtensa_movsp_op; | |
5689 | case 2: /* SYNC: r=0010 */ | |
5690 | switch (get_s_field (insn)) { | |
5691 | case 0: /* SYNCT: s=0000 */ | |
5692 | switch (get_t_field (insn)) { | |
5693 | case 2: /* ESYNC: t=0010 */ | |
5694 | return xtensa_esync_op; | |
5695 | case 3: /* DSYNC: t=0011 */ | |
5696 | return xtensa_dsync_op; | |
5697 | case 8: /* EXCW: t=1000 */ | |
5698 | return xtensa_excw_op; | |
5699 | case 12: /* MEMW: t=1100 */ | |
5700 | return xtensa_memw_op; | |
5701 | case 0: /* ISYNC: t=0000 */ | |
5702 | return xtensa_isync_op; | |
5703 | case 1: /* RSYNC: t=0001 */ | |
5704 | return xtensa_rsync_op; | |
5705 | } | |
5706 | break; | |
5707 | } | |
5708 | break; | |
5709 | case 4: /* BREAK: r=0100 */ | |
5710 | return xtensa_break_op; | |
5711 | case 3: /* RFEI: r=0011 */ | |
5712 | switch (get_t_field (insn)) { | |
5713 | case 0: /* RFET: t=0000 */ | |
5714 | switch (get_s_field (insn)) { | |
5715 | case 2: /* RFDE: s=0010 */ | |
5716 | return xtensa_rfde_op; | |
5717 | case 4: /* RFWO: s=0100 */ | |
5718 | return xtensa_rfwo_op; | |
5719 | case 5: /* RFWU: s=0101 */ | |
5720 | return xtensa_rfwu_op; | |
5721 | case 0: /* RFE: s=0000 */ | |
5722 | return xtensa_rfe_op; | |
5723 | } | |
5724 | break; | |
5725 | case 1: /* RFI: t=0001 */ | |
5726 | return xtensa_rfi_op; | |
5727 | } | |
5728 | break; | |
5729 | case 5: /* SCALL: r=0101 */ | |
5730 | switch (get_s_field (insn)) { | |
5731 | case 0: /* SYSCALL: s=0000 */ | |
5732 | return xtensa_syscall_op; | |
5733 | case 1: /* SIMCALL: s=0001 */ | |
5734 | return xtensa_simcall_op; | |
5735 | } | |
5736 | break; | |
5737 | case 6: /* RSIL: r=0110 */ | |
5738 | return xtensa_rsil_op; | |
5739 | case 7: /* WAITI: r=0111 */ | |
5740 | return xtensa_waiti_op; | |
5741 | } | |
5742 | break; | |
5743 | case 1: /* AND: op2=0001 */ | |
5744 | return xtensa_and_op; | |
5745 | case 2: /* OR: op2=0010 */ | |
5746 | return xtensa_or_op; | |
5747 | case 3: /* XOR: op2=0011 */ | |
5748 | return xtensa_xor_op; | |
5749 | case 4: /* ST1: op2=0100 */ | |
5750 | switch (get_r_field (insn)) { | |
5751 | case 15: /* NSAU: r=1111 */ | |
5752 | return xtensa_nsau_op; | |
5753 | case 0: /* SSR: r=0000 */ | |
5754 | return xtensa_ssr_op; | |
5755 | case 1: /* SSL: r=0001 */ | |
5756 | return xtensa_ssl_op; | |
5757 | case 2: /* SSA8L: r=0010 */ | |
5758 | return xtensa_ssa8l_op; | |
5759 | case 3: /* SSA8B: r=0011 */ | |
5760 | return xtensa_ssa8b_op; | |
5761 | case 4: /* SSAI: r=0100 */ | |
5762 | return xtensa_ssai_op; | |
5763 | case 8: /* ROTW: r=1000 */ | |
5764 | return xtensa_rotw_op; | |
5765 | case 14: /* NSA: r=1110 */ | |
5766 | return xtensa_nsa_op; | |
5767 | } | |
5768 | break; | |
5769 | case 8: /* ADD: op2=1000 */ | |
5770 | return xtensa_add_op; | |
5771 | case 5: /* ST4: op2=0101 */ | |
5772 | switch (get_r_field (insn)) { | |
5773 | case 15: /* RDTLB1: r=1111 */ | |
5774 | return xtensa_rdtlb1_op; | |
5775 | case 0: /* IITLBA: r=0000 */ | |
5776 | return xtensa_iitlba_op; | |
5777 | case 3: /* RITLB0: r=0011 */ | |
5778 | return xtensa_ritlb0_op; | |
5779 | case 4: /* IITLB: r=0100 */ | |
5780 | return xtensa_iitlb_op; | |
5781 | case 8: /* IDTLBA: r=1000 */ | |
5782 | return xtensa_idtlba_op; | |
5783 | case 5: /* PITLB: r=0101 */ | |
5784 | return xtensa_pitlb_op; | |
5785 | case 6: /* WITLB: r=0110 */ | |
5786 | return xtensa_witlb_op; | |
5787 | case 7: /* RITLB1: r=0111 */ | |
5788 | return xtensa_ritlb1_op; | |
5789 | case 11: /* RDTLB0: r=1011 */ | |
5790 | return xtensa_rdtlb0_op; | |
5791 | case 12: /* IDTLB: r=1100 */ | |
5792 | return xtensa_idtlb_op; | |
5793 | case 13: /* PDTLB: r=1101 */ | |
5794 | return xtensa_pdtlb_op; | |
5795 | case 14: /* WDTLB: r=1110 */ | |
5796 | return xtensa_wdtlb_op; | |
5797 | } | |
5798 | break; | |
5799 | case 6: /* RT0: op2=0110 */ | |
5800 | switch (get_s_field (insn)) { | |
5801 | case 0: /* NEG: s=0000 */ | |
5802 | return xtensa_neg_op; | |
5803 | case 1: /* ABS: s=0001 */ | |
5804 | return xtensa_abs_op; | |
5805 | } | |
5806 | break; | |
5807 | case 9: /* ADDX2: op2=1001 */ | |
5808 | return xtensa_addx2_op; | |
5809 | case 10: /* ADDX4: op2=1010 */ | |
5810 | return xtensa_addx4_op; | |
5811 | case 11: /* ADDX8: op2=1011 */ | |
5812 | return xtensa_addx8_op; | |
5813 | case 12: /* SUB: op2=1100 */ | |
5814 | return xtensa_sub_op; | |
5815 | case 13: /* SUBX2: op2=1101 */ | |
5816 | return xtensa_subx2_op; | |
5817 | case 14: /* SUBX4: op2=1110 */ | |
5818 | return xtensa_subx4_op; | |
5819 | } | |
5820 | break; | |
5821 | case 1: /* RST1: op1=0001 */ | |
5822 | switch (get_op2_field (insn)) { | |
5823 | case 15: /* IMP: op2=1111 */ | |
5824 | switch (get_r_field (insn)) { | |
5825 | case 0: /* LICT: r=0000 */ | |
5826 | return xtensa_lict_op; | |
5827 | case 1: /* SICT: r=0001 */ | |
5828 | return xtensa_sict_op; | |
5829 | case 2: /* LICW: r=0010 */ | |
5830 | return xtensa_licw_op; | |
5831 | case 3: /* SICW: r=0011 */ | |
5832 | return xtensa_sicw_op; | |
5833 | case 8: /* LDCT: r=1000 */ | |
5834 | return xtensa_ldct_op; | |
5835 | case 9: /* SDCT: r=1001 */ | |
5836 | return xtensa_sdct_op; | |
5837 | } | |
5838 | break; | |
5839 | case 0: /* SLLI: op2=000x */ | |
5840 | case 1: /* SLLI: op2=000x */ | |
5841 | return xtensa_slli_op; | |
5842 | case 2: /* SRAI: op2=001x */ | |
5843 | case 3: /* SRAI: op2=001x */ | |
5844 | return xtensa_srai_op; | |
5845 | case 4: /* SRLI: op2=0100 */ | |
5846 | return xtensa_srli_op; | |
5847 | case 8: /* SRC: op2=1000 */ | |
5848 | return xtensa_src_op; | |
5849 | case 9: /* SRL: op2=1001 */ | |
5850 | return xtensa_srl_op; | |
5851 | case 6: /* XSR: op2=0110 */ | |
5852 | return xtensa_xsr_op; | |
5853 | case 10: /* SLL: op2=1010 */ | |
5854 | return xtensa_sll_op; | |
5855 | case 11: /* SRA: op2=1011 */ | |
5856 | return xtensa_sra_op; | |
5857 | } | |
5858 | break; | |
5859 | } | |
5860 | break; | |
5861 | case 1: /* L32R: op0=0001 */ | |
5862 | return xtensa_l32r_op; | |
5863 | case 2: /* LSAI: op0=0010 */ | |
5864 | switch (get_r_field (insn)) { | |
5865 | case 0: /* L8UI: r=0000 */ | |
5866 | return xtensa_l8ui_op; | |
5867 | case 1: /* L16UI: r=0001 */ | |
5868 | return xtensa_l16ui_op; | |
5869 | case 2: /* L32I: r=0010 */ | |
5870 | return xtensa_l32i_op; | |
5871 | case 4: /* S8I: r=0100 */ | |
5872 | return xtensa_s8i_op; | |
5873 | case 5: /* S16I: r=0101 */ | |
5874 | return xtensa_s16i_op; | |
5875 | case 9: /* L16SI: r=1001 */ | |
5876 | return xtensa_l16si_op; | |
5877 | case 6: /* S32I: r=0110 */ | |
5878 | return xtensa_s32i_op; | |
5879 | case 7: /* CACHE: r=0111 */ | |
5880 | switch (get_t_field (insn)) { | |
5881 | case 15: /* III: t=1111 */ | |
5882 | return xtensa_iii_op; | |
5883 | case 0: /* DPFR: t=0000 */ | |
5884 | return xtensa_dpfr_op; | |
5885 | case 1: /* DPFW: t=0001 */ | |
5886 | return xtensa_dpfw_op; | |
5887 | case 2: /* DPFRO: t=0010 */ | |
5888 | return xtensa_dpfro_op; | |
5889 | case 4: /* DHWB: t=0100 */ | |
5890 | return xtensa_dhwb_op; | |
5891 | case 3: /* DPFWO: t=0011 */ | |
5892 | return xtensa_dpfwo_op; | |
5893 | case 8: /* DCE: t=1000 */ | |
5894 | switch (get_op1_field (insn)) { | |
5895 | case 4: /* DIWB: op1=0100 */ | |
5896 | return xtensa_diwb_op; | |
5897 | case 5: /* DIWBI: op1=0101 */ | |
5898 | return xtensa_diwbi_op; | |
5899 | } | |
5900 | break; | |
5901 | case 5: /* DHWBI: t=0101 */ | |
5902 | return xtensa_dhwbi_op; | |
5903 | case 6: /* DHI: t=0110 */ | |
5904 | return xtensa_dhi_op; | |
5905 | case 7: /* DII: t=0111 */ | |
5906 | return xtensa_dii_op; | |
5907 | case 12: /* IPF: t=1100 */ | |
5908 | return xtensa_ipf_op; | |
5909 | case 14: /* IHI: t=1110 */ | |
5910 | return xtensa_ihi_op; | |
5911 | } | |
5912 | break; | |
5913 | case 10: /* MOVI: r=1010 */ | |
5914 | return xtensa_movi_op; | |
5915 | case 12: /* ADDI: r=1100 */ | |
5916 | return xtensa_addi_op; | |
5917 | case 13: /* ADDMI: r=1101 */ | |
5918 | return xtensa_addmi_op; | |
5919 | } | |
5920 | break; | |
5921 | case 8: /* L32I.N: op0=1000 */ | |
5922 | return xtensa_l32i_n_op; | |
5923 | case 5: /* CALL: op0=0101 */ | |
5924 | switch (get_n_field (insn)) { | |
5925 | case 0: /* CALL0: n=00 */ | |
5926 | return xtensa_call0_op; | |
5927 | case 1: /* CALL4: n=01 */ | |
5928 | return xtensa_call4_op; | |
5929 | case 2: /* CALL8: n=10 */ | |
5930 | return xtensa_call8_op; | |
5931 | case 3: /* CALL12: n=11 */ | |
5932 | return xtensa_call12_op; | |
5933 | } | |
5934 | break; | |
5935 | case 6: /* SI: op0=0110 */ | |
5936 | switch (get_n_field (insn)) { | |
5937 | case 0: /* J: n=00 */ | |
5938 | return xtensa_j_op; | |
5939 | case 1: /* BZ: n=01 */ | |
5940 | switch (get_m_field (insn)) { | |
5941 | case 0: /* BEQZ: m=00 */ | |
5942 | return xtensa_beqz_op; | |
5943 | case 1: /* BNEZ: m=01 */ | |
5944 | return xtensa_bnez_op; | |
5945 | case 2: /* BLTZ: m=10 */ | |
5946 | return xtensa_bltz_op; | |
5947 | case 3: /* BGEZ: m=11 */ | |
5948 | return xtensa_bgez_op; | |
5949 | } | |
5950 | break; | |
5951 | case 2: /* BI0: n=10 */ | |
5952 | switch (get_m_field (insn)) { | |
5953 | case 0: /* BEQI: m=00 */ | |
5954 | return xtensa_beqi_op; | |
5955 | case 1: /* BNEI: m=01 */ | |
5956 | return xtensa_bnei_op; | |
5957 | case 2: /* BLTI: m=10 */ | |
5958 | return xtensa_blti_op; | |
5959 | case 3: /* BGEI: m=11 */ | |
5960 | return xtensa_bgei_op; | |
5961 | } | |
5962 | break; | |
5963 | case 3: /* BI1: n=11 */ | |
5964 | switch (get_m_field (insn)) { | |
5965 | case 0: /* ENTRY: m=00 */ | |
5966 | return xtensa_entry_op; | |
5967 | case 1: /* B1: m=01 */ | |
5968 | switch (get_r_field (insn)) { | |
5969 | case 8: /* LOOP: r=1000 */ | |
5970 | return xtensa_loop_op; | |
5971 | case 9: /* LOOPNEZ: r=1001 */ | |
5972 | return xtensa_loopnez_op; | |
5973 | case 10: /* LOOPGTZ: r=1010 */ | |
5974 | return xtensa_loopgtz_op; | |
5975 | } | |
5976 | break; | |
5977 | case 2: /* BLTUI: m=10 */ | |
5978 | return xtensa_bltui_op; | |
5979 | case 3: /* BGEUI: m=11 */ | |
5980 | return xtensa_bgeui_op; | |
5981 | } | |
5982 | break; | |
5983 | } | |
5984 | break; | |
5985 | case 9: /* S32I.N: op0=1001 */ | |
5986 | return xtensa_s32i_n_op; | |
5987 | case 10: /* ADD.N: op0=1010 */ | |
5988 | return xtensa_add_n_op; | |
5989 | case 7: /* B: op0=0111 */ | |
5990 | switch (get_r_field (insn)) { | |
5991 | case 6: /* BBCI: r=011x */ | |
5992 | case 7: /* BBCI: r=011x */ | |
5993 | return xtensa_bbci_op; | |
5994 | case 0: /* BNONE: r=0000 */ | |
5995 | return xtensa_bnone_op; | |
5996 | case 1: /* BEQ: r=0001 */ | |
5997 | return xtensa_beq_op; | |
5998 | case 2: /* BLT: r=0010 */ | |
5999 | return xtensa_blt_op; | |
6000 | case 4: /* BALL: r=0100 */ | |
6001 | return xtensa_ball_op; | |
6002 | case 14: /* BBSI: r=111x */ | |
6003 | case 15: /* BBSI: r=111x */ | |
6004 | return xtensa_bbsi_op; | |
6005 | case 3: /* BLTU: r=0011 */ | |
6006 | return xtensa_bltu_op; | |
6007 | case 5: /* BBC: r=0101 */ | |
6008 | return xtensa_bbc_op; | |
6009 | case 8: /* BANY: r=1000 */ | |
6010 | return xtensa_bany_op; | |
6011 | case 9: /* BNE: r=1001 */ | |
6012 | return xtensa_bne_op; | |
6013 | case 10: /* BGE: r=1010 */ | |
6014 | return xtensa_bge_op; | |
6015 | case 11: /* BGEU: r=1011 */ | |
6016 | return xtensa_bgeu_op; | |
6017 | case 12: /* BNALL: r=1100 */ | |
6018 | return xtensa_bnall_op; | |
6019 | case 13: /* BBS: r=1101 */ | |
6020 | return xtensa_bbs_op; | |
6021 | } | |
6022 | break; | |
6023 | case 11: /* ADDI.N: op0=1011 */ | |
6024 | return xtensa_addi_n_op; | |
6025 | case 12: /* ST2: op0=1100 */ | |
6026 | switch (get_i_field (insn)) { | |
6027 | case 0: /* MOVI.N: i=0 */ | |
6028 | return xtensa_movi_n_op; | |
6029 | case 1: /* BZ6: i=1 */ | |
6030 | switch (get_z_field (insn)) { | |
6031 | case 0: /* BEQZ.N: z=0 */ | |
6032 | return xtensa_beqz_n_op; | |
6033 | case 1: /* BNEZ.N: z=1 */ | |
6034 | return xtensa_bnez_n_op; | |
6035 | } | |
6036 | break; | |
6037 | } | |
6038 | break; | |
6039 | case 13: /* ST3: op0=1101 */ | |
6040 | switch (get_r_field (insn)) { | |
6041 | case 15: /* S3: r=1111 */ | |
6042 | switch (get_t_field (insn)) { | |
6043 | case 0: /* RET.N: t=0000 */ | |
6044 | return xtensa_ret_n_op; | |
6045 | case 1: /* RETW.N: t=0001 */ | |
6046 | return xtensa_retw_n_op; | |
6047 | case 2: /* BREAK.N: t=0010 */ | |
6048 | return xtensa_break_n_op; | |
6049 | case 3: /* NOP.N: t=0011 */ | |
6050 | return xtensa_nop_n_op; | |
6051 | } | |
6052 | break; | |
6053 | case 0: /* MOV.N: r=0000 */ | |
6054 | return xtensa_mov_n_op; | |
6055 | } | |
6056 | break; | |
6057 | } | |
6058 | return XTENSA_UNDEFINED; | |
6059 | } | |
6060 | ||
6061 | int | |
6062 | interface_version (void) | |
6063 | { | |
6064 | return 3; | |
6065 | } | |
6066 | ||
6067 | static struct config_struct config_table[] = { | |
6068 | {"IsaMemoryOrder", "BigEndian"}, | |
6069 | {"PIFReadDataBits", "128"}, | |
6070 | {"PIFWriteDataBits", "128"}, | |
6071 | {"IsaCoprocessorCount", "0"}, | |
6072 | {"IsaUseBooleans", "0"}, | |
6073 | {"IsaUseDensityInstruction", "1"}, | |
6074 | {0, 0} | |
6075 | }; | |
6076 | ||
6077 | struct config_struct * get_config_table (void); | |
6078 | ||
6079 | struct config_struct * | |
6080 | get_config_table (void) | |
6081 | { | |
6082 | return config_table; | |
6083 | } | |
6084 | ||
6085 | xtensa_isa_module xtensa_isa_modules[] = { | |
6086 | { get_num_opcodes, get_opcodes, decode_insn, get_config_table }, | |
6087 | { 0, 0, 0, 0 } | |
6088 | }; |