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2fa0b342 DHW |
1 | /* disassemble sparc instructions for objdump |
2 | Copyright (C) 1986, 1987, 1989 Free Software Foundation, Inc. | |
3 | ||
4 | ||
5 | This file is part of the binutils. | |
6 | ||
7 | The binutils are free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 1, or (at your option) | |
10 | any later version. | |
11 | ||
12 | The binutils are distributed in the hope that they will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with the binutils; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
20 | ||
21 | /* $Id$ | |
22 | $Log$ | |
23 | Revision 1.1 1991/03/21 21:26:55 gumby | |
24 | Initial revision | |
25 | ||
26 | * Revision 1.1 1991/03/13 00:34:40 chrisb | |
27 | * Initial revision | |
28 | * | |
29 | * Revision 1.3 1991/03/09 04:36:31 rich | |
30 | * Modified Files: | |
31 | * sparc-pinsn.c ostrip.c objdump.c m68k-pinsn.c i960-pinsn.c | |
32 | * binutils.h | |
33 | * | |
34 | * Pulled sysdep.h out of bfd.h. | |
35 | * | |
36 | * Revision 1.2 1991/03/08 21:54:53 rich | |
37 | * Modified Files: | |
38 | * Makefile ar.c binutils.h bucomm.c copy.c cplus-dem.c getopt.c | |
39 | * i960-pinsn.c m68k-pinsn.c nm.c objdump.c sparc-opcode.h | |
40 | * sparc-pinsn.c strip.c | |
41 | * | |
42 | * Verifying Portland tree with steve's last changes. Also, some partial | |
43 | * porting. | |
44 | * | |
45 | * Revision 1.1 1991/02/22 16:48:04 sac | |
46 | * Initial revision | |
47 | * | |
48 | */ | |
49 | ||
50 | #include <stdio.h> | |
51 | #include "sysdep.h" | |
52 | #include "bfd.h" | |
53 | #include "sparc-opcode.h" | |
54 | ||
55 | extern int fputs(); | |
56 | extern int print_address(); | |
57 | ||
58 | static char *reg_names[] = | |
59 | { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", | |
60 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
61 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
62 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
63 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
64 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
65 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
66 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
67 | "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" }; | |
68 | ||
69 | #define freg_names (®_names[4 * 8]) | |
70 | ||
71 | union sparc_insn | |
72 | { | |
73 | unsigned long int code; | |
74 | struct | |
75 | { | |
76 | unsigned int OP:2; | |
77 | #define op ldst.OP | |
78 | unsigned int RD:5; | |
79 | #define rd ldst.RD | |
80 | unsigned int op3:6; | |
81 | unsigned int RS1:5; | |
82 | #define rs1 ldst.RS1 | |
83 | unsigned int i:1; | |
84 | unsigned int ASI:8; | |
85 | #define asi ldst.ASI | |
86 | unsigned int RS2:5; | |
87 | #define rs2 ldst.RS2 | |
88 | #define shcnt rs2 | |
89 | } ldst; | |
90 | struct | |
91 | { | |
92 | unsigned int OP:2, RD:5, op3:6, RS1:5, i:1; | |
93 | unsigned int IMM13:13; | |
94 | #define imm13 IMM13.IMM13 | |
95 | } IMM13; | |
96 | struct | |
97 | { | |
98 | unsigned int OP:2; | |
99 | unsigned int a:1; | |
100 | unsigned int cond:4; | |
101 | unsigned int op2:3; | |
102 | unsigned int DISP22:22; | |
103 | #define disp22 branch.DISP22 | |
104 | } branch; | |
105 | #define imm22 disp22 | |
106 | struct | |
107 | { | |
108 | unsigned int OP:2; | |
109 | unsigned int DISP30:30; | |
110 | #define disp30 call.DISP30 | |
111 | } call; | |
112 | }; | |
113 | ||
114 | /* Nonzero if INSN is the opcode for a delayed branch. */ | |
115 | static int | |
116 | is_delayed_branch (insn) | |
117 | union sparc_insn insn; | |
118 | { | |
119 | unsigned int i; | |
120 | ||
121 | for (i = 0; i < NUMOPCODES; ++i) | |
122 | { | |
123 | const struct sparc_opcode *opcode = &sparc_opcodes[i]; | |
124 | if ((opcode->match & insn.code) == opcode->match | |
125 | && (opcode->lose & insn.code) == 0 | |
126 | && (opcode->delayed)) | |
127 | return 1; | |
128 | } | |
129 | return 0; | |
130 | } | |
131 | ||
132 | static int opcodes_sorted = 0; | |
133 | ||
134 | /* Print one instruction from MEMADDR on STREAM. */ | |
135 | int | |
136 | print_insn_sparc (memaddr, buffer, stream) | |
137 | bfd_vma memaddr; | |
138 | bfd_byte *buffer; | |
139 | FILE *stream; | |
140 | ||
141 | { | |
142 | union sparc_insn insn; | |
143 | ||
144 | register unsigned int i; | |
145 | ||
146 | if (!opcodes_sorted) | |
147 | { | |
148 | static int compare_opcodes (); | |
149 | qsort ((char *) sparc_opcodes, NUMOPCODES, | |
150 | sizeof (sparc_opcodes[0]), compare_opcodes); | |
151 | opcodes_sorted = 1; | |
152 | } | |
153 | ||
154 | memcpy(&insn,buffer, sizeof (insn)); | |
155 | ||
156 | for (i = 0; i < NUMOPCODES; ++i) | |
157 | { | |
158 | const struct sparc_opcode *opcode = &sparc_opcodes[i]; | |
159 | if ((opcode->match & insn.code) == opcode->match | |
160 | && (opcode->lose & insn.code) == 0) | |
161 | { | |
162 | /* Nonzero means that we have found an instruction which has | |
163 | the effect of adding or or'ing the imm13 field to rs1. */ | |
164 | int imm_added_to_rs1 = 0; | |
165 | ||
166 | /* Nonzero means that we have found a plus sign in the args | |
167 | field of the opcode table. */ | |
168 | int found_plus = 0; | |
169 | ||
170 | /* Do we have an 'or' instruction where rs1 is the same | |
171 | as rsd, and which has the i bit set? */ | |
172 | if (opcode->match == 0x80102000 | |
173 | && insn.rs1 == insn.rd) | |
174 | imm_added_to_rs1 = 1; | |
175 | ||
176 | if (index (opcode->args, 'S') != 0) | |
177 | /* Reject the special case for `set'. | |
178 | The real `sethi' will match. */ | |
179 | continue; | |
180 | if (insn.rs1 != insn.rd | |
181 | && index (opcode->args, 'r') != 0) | |
182 | /* Can't do simple format if source and dest are different. */ | |
183 | continue; | |
184 | ||
185 | fputs (opcode->name, stream); | |
186 | ||
187 | { | |
188 | register const char *s; | |
189 | ||
190 | if (opcode->args[0] != ',') | |
191 | fputs (" ", stream); | |
192 | for (s = opcode->args; *s != '\0'; ++s) | |
193 | { | |
194 | if (*s == ',') | |
195 | { | |
196 | fputs (",", stream); | |
197 | ++s; | |
198 | if (*s == 'a') | |
199 | { | |
200 | fputs ("a", stream); | |
201 | ++s; | |
202 | } | |
203 | fputs (" ", stream); | |
204 | } | |
205 | ||
206 | switch (*s) | |
207 | { | |
208 | case '+': | |
209 | found_plus = 1; | |
210 | ||
211 | /* note fall-through */ | |
212 | default: | |
213 | fprintf (stream, "%c", *s); | |
214 | break; | |
215 | ||
216 | case '#': | |
217 | fputs ("0", stream); | |
218 | break; | |
219 | ||
220 | #define reg(n) fprintf (stream, "%%%s", reg_names[n]) | |
221 | case '1': | |
222 | case 'r': | |
223 | reg (insn.rs1); | |
224 | break; | |
225 | ||
226 | case '2': | |
227 | reg (insn.rs2); | |
228 | break; | |
229 | ||
230 | case 'd': | |
231 | reg (insn.rd); | |
232 | break; | |
233 | #undef reg | |
234 | ||
235 | #define freg(n) fprintf (stream, "%%%s", freg_names[n]) | |
236 | case 'e': | |
237 | freg (insn.rs1); | |
238 | break; | |
239 | ||
240 | case 'f': | |
241 | freg (insn.rs2); | |
242 | break; | |
243 | ||
244 | case 'g': | |
245 | freg (insn.rd); | |
246 | break; | |
247 | #undef freg | |
248 | ||
249 | #define creg(n) fprintf (stream, "%%c%u", (unsigned int) (n)) | |
250 | case 'b': | |
251 | creg (insn.rs1); | |
252 | break; | |
253 | ||
254 | case 'c': | |
255 | creg (insn.rs2); | |
256 | break; | |
257 | ||
258 | case 'D': | |
259 | creg (insn.rd); | |
260 | break; | |
261 | #undef creg | |
262 | ||
263 | case 'h': | |
264 | fprintf (stream, "%%hi(%#x)", | |
265 | (unsigned int) insn.imm22 << 10); | |
266 | break; | |
267 | ||
268 | case 'i': | |
269 | { | |
270 | /* We cannot trust the compiler to sign-extend | |
271 | when extracting the bitfield, hence the shifts. */ | |
272 | int imm = ((int) insn.imm13 << 19) >> 19; | |
273 | ||
274 | /* Check to see whether we have a 1+i, and take | |
275 | note of that fact. | |
276 | ||
277 | Note: because of the way we sort the table, | |
278 | we will be matching 1+i rather than i+1, | |
279 | so it is OK to assume that i is after +, | |
280 | not before it. */ | |
281 | if (found_plus) | |
282 | imm_added_to_rs1 = 1; | |
283 | ||
284 | if (imm <= 9) | |
285 | fprintf (stream, "%d", imm); | |
286 | else | |
287 | fprintf (stream, "%#x", (unsigned) imm); | |
288 | } | |
289 | break; | |
290 | ||
291 | case 'L': | |
292 | print_address ((bfd_vma) memaddr + insn.disp30 * 4, | |
293 | stream); | |
294 | break; | |
295 | ||
296 | case 'l': | |
297 | if ((insn.code >> 22) == 0) | |
298 | /* Special case for `unimp'. Don't try to turn | |
299 | it's operand into a function offset. */ | |
300 | fprintf (stream, "%#x", | |
301 | (unsigned) (((int) insn.disp22 << 10) >> 10)); | |
302 | else | |
303 | /* We cannot trust the compiler to sign-extend | |
304 | when extracting the bitfield, hence the shifts. */ | |
305 | print_address ((bfd_vma) | |
306 | (memaddr | |
307 | + (((int) insn.disp22 << 10) >> 10) * 4), | |
308 | stream); | |
309 | break; | |
310 | ||
311 | case 'A': | |
312 | fprintf (stream, "(%d)", (int) insn.asi); | |
313 | break; | |
314 | ||
315 | case 'C': | |
316 | fputs ("%csr", stream); | |
317 | break; | |
318 | ||
319 | case 'F': | |
320 | fputs ("%fsr", stream); | |
321 | break; | |
322 | ||
323 | case 'p': | |
324 | fputs ("%psr", stream); | |
325 | break; | |
326 | ||
327 | case 'q': | |
328 | fputs ("%fq", stream); | |
329 | break; | |
330 | ||
331 | case 'Q': | |
332 | fputs ("%cq", stream); | |
333 | break; | |
334 | ||
335 | case 't': | |
336 | fputs ("%tbr", stream); | |
337 | break; | |
338 | ||
339 | case 'w': | |
340 | fputs ("%wim", stream); | |
341 | break; | |
342 | ||
343 | case 'y': | |
344 | fputs ("%y", stream); | |
345 | break; | |
346 | } | |
347 | } | |
348 | } | |
349 | ||
350 | /* If we are adding or or'ing something to rs1, then | |
351 | check to see whether the previous instruction was | |
352 | a sethi to the same register as in the sethi. | |
353 | If so, attempt to print the result of the add or | |
354 | or (in this context add and or do the same thing) | |
355 | and its symbolic value. */ | |
356 | if (imm_added_to_rs1) | |
357 | { | |
358 | union sparc_insn prev_insn; | |
359 | int errcode; | |
360 | ||
361 | memcpy(&prev_insn, buffer -4, sizeof (prev_insn)); | |
362 | ||
363 | if (errcode == 0) | |
364 | { | |
365 | /* If it is a delayed branch, we need to look at the | |
366 | instruction before the delayed branch. This handles | |
367 | sequences such as | |
368 | ||
369 | sethi %o1, %hi(_foo), %o1 | |
370 | call _printf | |
371 | or %o1, %lo(_foo), %o1 | |
372 | */ | |
373 | ||
374 | if (is_delayed_branch (prev_insn)) | |
375 | memcpy(&prev_insn, buffer - 8, sizeof(prev_insn)); | |
376 | ||
377 | } | |
378 | ||
379 | /* If there was a problem reading memory, then assume | |
380 | the previous instruction was not sethi. */ | |
381 | if (errcode == 0) | |
382 | { | |
383 | /* Is it sethi to the same register? */ | |
384 | if ((prev_insn.code & 0xc1c00000) == 0x01000000 | |
385 | && prev_insn.rd == insn.rs1) | |
386 | { | |
387 | fprintf (stream, "\t! "); | |
388 | /* We cannot trust the compiler to sign-extend | |
389 | when extracting the bitfield, hence the shifts. */ | |
390 | print_address (((int) prev_insn.imm22 << 10) | |
391 | | (insn.imm13 << 19) >> 19, stream); | |
392 | } | |
393 | } | |
394 | } | |
395 | ||
396 | return sizeof (insn); | |
397 | } | |
398 | } | |
399 | ||
400 | fprintf ("%#8x", insn.code); | |
401 | return sizeof (insn); | |
402 | } | |
403 | ||
404 | ||
405 | /* Compare opcodes A and B. */ | |
406 | ||
407 | static int | |
408 | compare_opcodes (a, b) | |
409 | char *a, *b; | |
410 | { | |
411 | struct sparc_opcode *op0 = (struct sparc_opcode *) a; | |
412 | struct sparc_opcode *op1 = (struct sparc_opcode *) b; | |
413 | unsigned long int match0 = op0->match, match1 = op1->match; | |
414 | unsigned long int lose0 = op0->lose, lose1 = op1->lose; | |
415 | register unsigned int i; | |
416 | ||
417 | /* If a bit is set in both match and lose, there is something | |
418 | wrong with the opcode table. */ | |
419 | if (match0 & lose0) | |
420 | { | |
421 | fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n", | |
422 | op0->name, match0, lose0); | |
423 | op0->lose &= ~op0->match; | |
424 | lose0 = op0->lose; | |
425 | } | |
426 | ||
427 | if (match1 & lose1) | |
428 | { | |
429 | fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n", | |
430 | op1->name, match1, lose1); | |
431 | op1->lose &= ~op1->match; | |
432 | lose1 = op1->lose; | |
433 | } | |
434 | ||
435 | /* Because the bits that are variable in one opcode are constant in | |
436 | another, it is important to order the opcodes in the right order. */ | |
437 | for (i = 0; i < 32; ++i) | |
438 | { | |
439 | unsigned long int x = 1 << i; | |
440 | int x0 = (match0 & x) != 0; | |
441 | int x1 = (match1 & x) != 0; | |
442 | ||
443 | if (x0 != x1) | |
444 | return x1 - x0; | |
445 | } | |
446 | ||
447 | for (i = 0; i < 32; ++i) | |
448 | { | |
449 | unsigned long int x = 1 << i; | |
450 | int x0 = (lose0 & x) != 0; | |
451 | int x1 = (lose1 & x) != 0; | |
452 | ||
453 | if (x0 != x1) | |
454 | return x1 - x0; | |
455 | } | |
456 | ||
457 | /* They are functionally equal. So as long as the opcode table is | |
458 | valid, we can put whichever one first we want, on aesthetic grounds. */ | |
459 | { | |
460 | int length_diff = strlen (op0->args) - strlen (op1->args); | |
461 | if (length_diff != 0) | |
462 | /* Put the one with fewer arguments first. */ | |
463 | return length_diff; | |
464 | } | |
465 | ||
466 | /* Put 1+i before i+1. */ | |
467 | { | |
468 | char *p0 = (char *) index(op0->args, '+'); | |
469 | char *p1 = (char *) index(op1->args, '+'); | |
470 | ||
471 | if (p0 && p1) | |
472 | { | |
473 | /* There is a plus in both operands. Note that a plus | |
474 | sign cannot be the first character in args, | |
475 | so the following [-1]'s are valid. */ | |
476 | if (p0[-1] == 'i' && p1[1] == 'i') | |
477 | /* op0 is i+1 and op1 is 1+i, so op1 goes first. */ | |
478 | return 1; | |
479 | if (p0[1] == 'i' && p1[-1] == 'i') | |
480 | /* op0 is 1+i and op1 is i+1, so op0 goes first. */ | |
481 | return -1; | |
482 | } | |
483 | } | |
484 | ||
485 | /* They are, as far as we can tell, identical. | |
486 | Since qsort may have rearranged the table partially, there is | |
487 | no way to tell which one was first in the opcode table as | |
488 | written, so just say there are equal. */ | |
489 | return 0; | |
490 | } |