AArch64: Fix disassembler bug with out-of-order sections
[deliverable/binutils-gdb.git] / binutils / testsuite / binutils-all / strip-15rela.s
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1 .text
2foo:
3 .dc.l 0x12345678
4
8c9604b6 5 .section .rela.text,""
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6 .ifdef ELF64
7
8 .dc.a 0
9 .dc.a RELOC
10 .dc.a 0x00000000000055aa
11
12 .dc.a 0
13 .dc.a 0
14 .dc.a 0
15 .else
16
17 # Some targets, such as `h8300-*' or `ip2k-*', use 16-bit addresses.
18 # With them `.dc.a' emits 16-bit quantities, so we need to use
19 # `.dc.l' for 32-bit relocation data.
20 .dc.l 0
21 .dc.l RELOC
22 .dc.l 0x000055aa
23
24 .dc.l 0
25 .dc.l 0
26 .dc.l 0
27 .endif
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