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8ee9a8b2 | 1 | ; Renesas M32R CPU description. -*- Scheme -*- |
e866a257 AC |
2 | ; |
3 | ; Copyright 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. | |
4 | ; | |
5 | ; Contributed by Red Hat Inc; developed under contract from Mitsubishi | |
6 | ; Electric Corporation. | |
7 | ; | |
8 | ; This file is part of the GNU Binutils. | |
9 | ; | |
10 | ; This program is free software; you can redistribute it and/or modify | |
11 | ; it under the terms of the GNU General Public License as published by | |
12 | ; the Free Software Foundation; either version 2 of the License, or | |
13 | ; (at your option) any later version. | |
14 | ; | |
15 | ; This program is distributed in the hope that it will be useful, | |
16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | ; GNU General Public License for more details. | |
19 | ; | |
20 | ; You should have received a copy of the GNU General Public License | |
21 | ; along with this program; if not, write to the Free Software | |
22 | ; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
23 | ||
24 | (include "simplify.inc") | |
25 | ||
26 | ; FIXME: Delete sign extension of accumulator results. | |
27 | ; Sign extension is done when accumulator is read. | |
28 | ||
29 | ; define-arch must appear first | |
30 | ||
31 | (define-arch | |
32 | (name m32r) ; name of cpu family | |
8ee9a8b2 | 33 | (comment "Renesas M32R") |
e866a257 AC |
34 | (default-alignment aligned) |
35 | (insn-lsb0? #f) | |
8ee9a8b2 | 36 | (machs m32r m32rx m32r2) |
e866a257 AC |
37 | (isas m32r) |
38 | ) | |
39 | ||
40 | ; Attributes. | |
41 | ||
42 | ; An attribute to describe which pipeline an insn runs in. | |
8ee9a8b2 NC |
43 | ; O_OS is a special attribute for sll, sra, sla, slli, srai, slai. |
44 | ; These instructions have O attribute for m32rx and OS attribute for m32r2. | |
e866a257 AC |
45 | |
46 | (define-attr | |
47 | (for insn) | |
48 | (type enum) | |
49 | (name PIPE) | |
50 | (comment "parallel execution pipeline selection") | |
8ee9a8b2 | 51 | (values NONE O S OS O_OS) |
e866a257 AC |
52 | ) |
53 | ||
54 | ; A derived attribute that says which insns can be executed in parallel | |
55 | ; with others. This is a required attribute for architectures with | |
56 | ; parallel execution. | |
57 | ||
58 | (define-attr | |
59 | (for insn) | |
60 | (type enum) | |
61 | (name PARALLEL) | |
62 | (attrs META) ; do not define in any generated file for now | |
63 | (values NO YES) | |
64 | (default (if (eq-attr (current-insn) PIPE NONE) (symbol NO) (symbol YES))) | |
65 | ) | |
66 | ||
67 | ; Instruction set parameters. | |
68 | ||
69 | (define-isa | |
70 | (name m32r) | |
71 | ||
72 | ; This is 32 because 16 bit insns always appear as pairs. | |
73 | ; ??? See if this can go away. It's only used by the disassembler (right?) | |
74 | ; to decide how long an unknown insn is. One value isn't sufficient (e.g. if | |
75 | ; on a 16 bit (and not 32 bit) boundary, will only want to advance pc by 16.) | |
76 | (default-insn-bitsize 32) | |
77 | ||
78 | ; Number of bytes of insn we can initially fetch. | |
79 | ; The M32R is tricky in that insns are either two 16-bit insns | |
80 | ; (executed sequentially or in parallel) or one 32-bit insn. | |
81 | ; So on one hand the base insn size is 16 bits, but on another it's 32. | |
82 | ; 32 is chosen because: | |
83 | ; - if the chip were ever bi-endian it is believed that the byte order would | |
84 | ; be based on 32 bit quantities | |
85 | ; - 32 bit insns are always aligned on 32 bit boundaries | |
86 | ; - the pc will never stop on a 16 bit (and not 32 bit) boundary | |
87 | ; [well actually it can, but there are no branches to such places] | |
88 | (base-insn-bitsize 32) | |
89 | ||
90 | ; Used in computing bit numbers. | |
91 | (default-insn-word-bitsize 32) | |
92 | ||
93 | ; The m32r fetches 2 insns at a time. | |
94 | (liw-insns 2) | |
95 | ||
96 | ; While the m32r can execute insns in parallel, the base mach can't | |
97 | ; (other than nop). The base mach is greatly handicapped by this, but | |
98 | ; we still need to cleanly handle it. | |
99 | (parallel-insns 2) | |
100 | ||
101 | ; Initial bitnumbers to decode insns by. | |
102 | (decode-assist (0 1 2 3 8 9 10 11)) | |
103 | ||
104 | ; Classification of instructions that fit in the various frames. | |
105 | ; wip, not currently used | |
106 | (insn-types (long ; name | |
107 | 31 ; length | |
108 | (eq-attr (current-insn) LENGTH 31) ; matching insns | |
109 | (0 1 2 7 8 9 10) ; decode-assist | |
110 | ) | |
111 | (short | |
112 | 15 | |
113 | (eq-attr (current-insn) LENGTH 15) ; matching insns | |
114 | (0 1 2 7 8 9 10) | |
115 | ) | |
116 | ) | |
117 | ||
118 | ; Instruction framing. | |
119 | ; Each m32r insn is either one 32 bit insn, two 16 bit insns executed | |
120 | ; serially (left->right), or two 16 bit insns executed parallelly. | |
121 | ; wip, not currently used | |
122 | (frame long32 ; name | |
123 | ((long)) ; list of insns in frame, plus constraint | |
124 | "$0" ; assembler | |
125 | (+ (1 1) (31 $0)) ; value | |
126 | (sequence () (execute $0)) ; action | |
127 | ) | |
128 | (frame serial2x16 | |
129 | ((short) | |
130 | (short)) | |
131 | "$0 -> $1" | |
132 | (+ (1 0) (15 $0) (1 0) (15 $1)) | |
133 | (sequence () | |
134 | (execute $0) | |
135 | (execute $1)) | |
136 | ) | |
137 | (frame parallel2x16 | |
138 | ((short (eq-attr (current-insn) PIPE "O,BOTH")) | |
139 | (short (eq-attr (current-insn) PIPE "S,BOTH"))) | |
140 | "$0 || $1" | |
141 | (+ (1 0) (15 $0) (1 1) (15 $1)) | |
142 | (parallel () | |
143 | (execute $0) | |
144 | (execute $1)) | |
145 | ) | |
146 | ) | |
147 | \f | |
148 | ; Cpu family definitions. | |
149 | ||
150 | ; ??? define-cpu-family [and in general "cpu-family"] might be clearer than | |
151 | ; define-cpu. | |
152 | ; ??? Have define-arch provide defaults for architecture that define-cpu can | |
153 | ; then override [reduces duplication in define-cpu]. | |
154 | ; ??? Another way to go is to delete cpu-families entirely and have one mach | |
155 | ; able to inherit things from another mach (would also need the ability to | |
156 | ; not only override specific inherited things but also disable some, | |
157 | ; e.g. if an insn wasn't supported). | |
158 | ||
159 | (define-cpu | |
160 | ; cpu names must be distinct from the architecture name and machine names. | |
161 | ; The "b" suffix stands for "base" and is the convention. | |
162 | ; The "f" suffix stands for "family" and is the convention. | |
163 | (name m32rbf) | |
8ee9a8b2 NC |
164 | (comment "Renesas M32R base family") |
165 | (endian either) | |
e866a257 AC |
166 | (word-bitsize 32) |
167 | ; Override isa spec (??? keeps things simpler, though it was more true | |
168 | ; in the early days and not so much now). | |
169 | (parallel-insns 1) | |
170 | ) | |
171 | ||
172 | (define-cpu | |
173 | (name m32rxf) | |
8ee9a8b2 NC |
174 | (comment "Renesas M32Rx family") |
175 | (endian either) | |
e866a257 AC |
176 | (word-bitsize 32) |
177 | ; Generated files have an "x" suffix. | |
178 | (file-transform "x") | |
179 | ) | |
180 | ||
8ee9a8b2 NC |
181 | (define-cpu |
182 | (name m32r2f) | |
183 | (comment "Renesas M32R2 family") | |
184 | (endian either) | |
185 | (word-bitsize 32) | |
186 | ; Generated files have an "2" suffix. | |
187 | (file-transform "2") | |
188 | ) | |
189 | ||
e866a257 AC |
190 | (define-mach |
191 | (name m32r) | |
192 | (comment "Generic M32R cpu") | |
193 | (cpu m32rbf) | |
194 | ) | |
195 | ||
196 | (define-mach | |
197 | (name m32rx) | |
198 | (comment "M32RX cpu") | |
199 | (cpu m32rxf) | |
200 | ) | |
8ee9a8b2 NC |
201 | |
202 | (define-mach | |
203 | (name m32r2) | |
204 | (comment "M32R2 cpu") | |
205 | (cpu m32r2f) | |
206 | ) | |
e866a257 AC |
207 | \f |
208 | ; Model descriptions. | |
209 | ||
210 | ; The meaning of this value is wip but at the moment it's intended to describe | |
211 | ; the implementation (i.e. what -mtune=foo does in sparc gcc). | |
212 | ; | |
213 | ; Notes while wip: | |
214 | ; - format of pipeline entry: | |
215 | ; (pipeline name (stage1-name ...) (stage2-name ...) ...) | |
216 | ; The contents of a stage description is wip. | |
217 | ; - each mach must have at least one model | |
218 | ; - the default model must be the first one | |
219 | ;- maybe have `retire' support update total cycle count to handle current | |
220 | ; parallel insn cycle counting problems | |
221 | ||
222 | (define-model | |
223 | (name m32r/d) (comment "m32r/d") (attrs) | |
224 | (mach m32r) | |
225 | ||
226 | ;(prefetch) | |
227 | ;(retire) | |
228 | ||
229 | (pipeline p-non-mem "" () ((fetch) (decode) (execute) (writeback))) | |
230 | (pipeline p-mem "" () ((fetch) (decode) (execute) (memory) (writeback))) | |
231 | ||
232 | ; `state' is a list of variables for recording model state | |
233 | (state | |
234 | ; bit mask of h-gr registers, =1 means value being loaded from memory | |
235 | (h-gr UINT) | |
236 | ) | |
237 | ||
238 | (unit u-exec "Execution Unit" () | |
239 | 1 1 ; issue done | |
240 | () ; state | |
241 | ((sr INT -1) (dr INT -1)) ; inputs | |
242 | ((dr INT -1)) ; outputs | |
243 | () ; profile action (default) | |
244 | ) | |
245 | (unit u-cmp "Compare Unit" () | |
246 | 1 1 ; issue done | |
247 | () ; state | |
248 | ((src1 INT -1) (src2 INT -1)) ; inputs | |
249 | () ; outputs | |
250 | () ; profile action (default) | |
251 | ) | |
252 | (unit u-mac "Multiply/Accumulate Unit" () | |
253 | 1 1 ; issue done | |
254 | () ; state | |
255 | ((src1 INT -1) (src2 INT -1)) ; inputs | |
256 | () ; outputs | |
257 | () ; profile action (default) | |
258 | ) | |
259 | (unit u-cti "Branch Unit" () | |
260 | 1 1 ; issue done | |
261 | () ; state | |
262 | ((sr INT -1)) ; inputs | |
263 | ((pc)) ; outputs | |
264 | () ; profile action (default) | |
265 | ) | |
266 | (unit u-load "Memory Load Unit" () | |
267 | 1 1 ; issue done | |
268 | () ; state | |
269 | ((sr INT) | |
270 | ;(ld-mem AI) | |
271 | ) ; inputs | |
272 | ((dr INT)) ; outputs | |
273 | () ; profile action (default) | |
274 | ) | |
275 | (unit u-store "Memory Store Unit" () | |
276 | 1 1 ; issue done | |
277 | () ; state | |
278 | ((src1 INT) (src2 INT)) ; inputs | |
279 | () ; ((st-mem AI)) ; outputs | |
280 | () ; profile action (default) | |
281 | ) | |
282 | ) | |
283 | ||
284 | (define-model | |
285 | (name test) (comment "test") (attrs) | |
286 | (mach m32r) | |
287 | (pipeline all "" () ((fetch) (decode) (execute) (writeback))) | |
288 | (unit u-exec "Execution Unit" () | |
289 | 1 1 ; issue done | |
290 | () () () ()) | |
291 | ) | |
292 | ||
293 | ; Each mach must have at least one model. | |
294 | ||
295 | (define-model | |
296 | (name m32rx) (comment "m32rx") (attrs) | |
297 | (mach m32rx) | |
298 | ||
299 | ; ??? It's 6 stages but I forget the details right now. | |
300 | (pipeline p-o "" () ((fetch) (decode) (execute) (writeback))) | |
301 | (pipeline p-s "" () ((fetch) (decode) (execute) (writeback))) | |
302 | (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback))) | |
303 | ||
304 | (unit u-exec "Execution Unit" () | |
305 | 1 1 ; issue done | |
306 | () ; state | |
307 | ((sr INT -1) (dr INT -1)) ; inputs | |
308 | ((dr INT -1)) ; outputs | |
309 | () ; profile action (default) | |
310 | ) | |
311 | (unit u-cmp "Compare Unit" () | |
312 | 1 1 ; issue done | |
313 | () ; state | |
314 | ((src1 INT -1) (src2 INT -1)) ; inputs | |
315 | () ; outputs | |
316 | () ; profile action (default) | |
317 | ) | |
318 | (unit u-mac "Multiply/Accumulate Unit" () | |
319 | 1 1 ; issue done | |
320 | () ; state | |
321 | ((src1 INT -1) (src2 INT -1)) ; inputs | |
322 | () ; outputs | |
323 | () ; profile action (default) | |
324 | ) | |
325 | (unit u-cti "Branch Unit" () | |
326 | 1 1 ; issue done | |
327 | () ; state | |
328 | ((sr INT -1)) ; inputs | |
329 | ((pc)) ; outputs | |
330 | () ; profile action (default) | |
331 | ) | |
332 | (unit u-load "Memory Load Unit" () | |
333 | 1 1 ; issue done | |
334 | () ; state | |
335 | ((sr INT)) ; inputs | |
336 | ((dr INT)) ; outputs | |
337 | () ; profile action (default) | |
338 | ) | |
339 | (unit u-store "Memory Store Unit" () | |
340 | 1 1 ; issue done | |
341 | () ; state | |
342 | ((src1 INT) (src2 INT)) ; inputs | |
343 | () ; outputs | |
344 | () ; profile action (default) | |
345 | ) | |
346 | ) | |
8ee9a8b2 NC |
347 | |
348 | (define-model | |
349 | (name m32r2) (comment "m32r2") (attrs) | |
350 | (mach m32r2) | |
351 | ||
352 | ; ??? It's 6 stages but I forget the details right now. | |
353 | (pipeline p-o "" () ((fetch) (decode) (execute) (writeback))) | |
354 | (pipeline p-s "" () ((fetch) (decode) (execute) (writeback))) | |
355 | (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback))) | |
356 | ||
357 | (unit u-exec "Execution Unit" () | |
358 | 1 1 ; issue done | |
359 | () ; state | |
360 | ((sr INT -1) (dr INT -1)) ; inputs | |
361 | ((dr INT -1)) ; outputs | |
362 | () ; profile action (default) | |
363 | ) | |
364 | (unit u-cmp "Compare Unit" () | |
365 | 1 1 ; issue done | |
366 | () ; state | |
367 | ((src1 INT -1) (src2 INT -1)) ; inputs | |
368 | () ; outputs | |
369 | () ; profile action (default) | |
370 | ) | |
371 | (unit u-mac "Multiply/Accumulate Unit" () | |
372 | 1 1 ; issue done | |
373 | () ; state | |
374 | ((src1 INT -1) (src2 INT -1)) ; inputs | |
375 | () ; outputs | |
376 | () ; profile action (default) | |
377 | ) | |
378 | (unit u-cti "Branch Unit" () | |
379 | 1 1 ; issue done | |
380 | () ; state | |
381 | ((sr INT -1)) ; inputs | |
382 | ((pc)) ; outputs | |
383 | () ; profile action (default) | |
384 | ) | |
385 | (unit u-load "Memory Load Unit" () | |
386 | 1 1 ; issue done | |
387 | () ; state | |
388 | ((sr INT)) ; inputs | |
389 | ((dr INT)) ; outputs | |
390 | () ; profile action (default) | |
391 | ) | |
392 | (unit u-store "Memory Store Unit" () | |
393 | 1 1 ; issue done | |
394 | () ; state | |
395 | ((src1 INT) (src2 INT)) ; inputs | |
396 | () ; outputs | |
397 | () ; profile action (default) | |
398 | ) | |
399 | ) | |
e866a257 AC |
400 | \f |
401 | ; The instruction fetch/execute cycle. | |
402 | ; This is split into two parts as sometimes more than one instruction is | |
403 | ; decoded at once. | |
404 | ; The `const SI' argument to decode/execute is used to distinguish | |
405 | ; multiple instructions processed at the same time (e.g. m32r). | |
406 | ; | |
407 | ; ??? This is wip, and not currently used. | |
408 | ; ??? Needs to be moved to define-isa. | |
409 | ||
410 | ; This is how to fetch and decode an instruction. | |
411 | ||
412 | ;(define-extract | |
413 | ; (sequence VOID | |
414 | ; (if VOID (ne AI (and AI pc (const AI 3)) (const AI 0)) | |
415 | ; (sequence VOID | |
416 | ; (set-quiet USI (scratch UHI insn1) (ifetch UHI pc)) | |
417 | ; (decode VOID pc (and UHI insn1 (const UHI #x7fff)) | |
418 | ; (const SI 0))) | |
419 | ; (sequence VOID | |
420 | ; (set-quiet USI (scratch USI insn) (ifetch USI pc)) | |
421 | ; (if VOID (ne USI (and USI insn (const USI #x80000000)) | |
422 | ; (const USI 0)) | |
423 | ; (decode VOID pc (srl USI insn (const WI 16)) (const SI 0)) | |
424 | ; (sequence VOID | |
425 | ; ; ??? parallel support | |
426 | ; (decode VOID pc (srl USI insn (const WI 16)) | |
427 | ; (const SI 0)) | |
428 | ; (decode VOID (add AI pc (const AI 2)) | |
429 | ; (and USI insn (const WI #x7fff)) | |
430 | ; (const SI 1)))))) | |
431 | ; ) | |
432 | ;) | |
433 | ||
434 | ; This is how to execute a decoded instruction. | |
435 | ||
436 | ;(define-execute | |
437 | ; (sequence VOID () ; () is empty option list | |
438 | ; ((AI new_pc)) | |
439 | ; (set AI new_pc (execute: AI (const 0)) #:quiet) | |
440 | ; (set AI pc new_pc #:direct) | |
441 | ; ) | |
442 | ;) | |
443 | ||
444 | ; FIXME: It might simplify things to separate the execute process from the | |
445 | ; one that updates the PC. | |
446 | \f | |
447 | ; Instruction fields. | |
448 | ; | |
449 | ; Attributes: | |
450 | ; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) | |
451 | ; ABS-ADDR: absolute address (for reloc and disassembly purposes?) | |
452 | ; RESERVED: bits are not used to decode insn, must be all 0 | |
453 | ; RELOC: there is a relocation associated with this field (experiment) | |
454 | ||
455 | (define-attr | |
456 | (for ifield operand) | |
457 | (type boolean) | |
458 | (name RELOC) | |
459 | (comment "there is a reloc associated with this field (experiment)") | |
460 | ) | |
461 | ||
462 | (dnf f-op1 "op1" () 0 4) | |
463 | (dnf f-op2 "op2" () 8 4) | |
464 | (dnf f-cond "cond" () 4 4) | |
465 | (dnf f-r1 "r1" () 4 4) | |
466 | (dnf f-r2 "r2" () 12 4) | |
467 | (df f-simm8 "simm8" () 8 8 INT #f #f) | |
468 | (df f-simm16 "simm16" () 16 16 INT #f #f) | |
469 | (dnf f-shift-op2 "shift op2" () 8 3) | |
8ee9a8b2 | 470 | (dnf f-uimm3 "uimm3" () 5 3) |
e866a257 AC |
471 | (dnf f-uimm4 "uimm4" () 12 4) |
472 | (dnf f-uimm5 "uimm5" () 11 5) | |
8ee9a8b2 | 473 | (dnf f-uimm8 "uimm8" () 8 8) |
e866a257 AC |
474 | (dnf f-uimm16 "uimm16" () 16 16) |
475 | (dnf f-uimm24 "uimm24" (ABS-ADDR RELOC) 8 24) | |
476 | (dnf f-hi16 "high 16 bits" (SIGN-OPT) 16 16) | |
477 | (df f-disp8 "disp8, slot unknown" (PCREL-ADDR RELOC) 8 8 INT | |
478 | ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 2))) | |
479 | ((value pc) (add WI (sll WI value (const 2)) (and WI pc (const -4))))) | |
480 | (df f-disp16 "disp16" (PCREL-ADDR RELOC) 16 16 INT | |
481 | ((value pc) (sra WI (sub WI value pc) (const 2))) | |
482 | ((value pc) (add WI (sll WI value (const 2)) pc))) | |
483 | (df f-disp24 "disp24" (PCREL-ADDR RELOC) 8 24 INT | |
484 | ((value pc) (sra WI (sub WI value pc) (const 2))) | |
485 | ((value pc) (add WI (sll WI value (const 2)) pc))) | |
486 | ||
487 | (dnf f-op23 "op2.3" () 9 3) | |
488 | (dnf f-op3 "op3" () 14 2) | |
489 | (dnf f-acc "acc" () 8 1) | |
490 | (dnf f-accs "accs" () 12 2) | |
491 | (dnf f-accd "accd" () 4 2) | |
492 | (dnf f-bits67 "bits67" () 6 2) | |
8ee9a8b2 | 493 | (dnf f-bit4 "bit4" () 4 1) |
e866a257 AC |
494 | (dnf f-bit14 "bit14" () 14 1) |
495 | ||
496 | (define-ifield (name f-imm1) (comment "1 bit immediate, 0->1 1->2") | |
497 | (attrs) | |
498 | (start 15) (length 1) | |
499 | (encode (value pc) (sub WI value (const WI 1))) | |
500 | (decode (value pc) (add WI value (const WI 1))) | |
501 | ) | |
502 | \f | |
503 | ; Enums. | |
504 | ||
505 | ; insn-op1: bits 0-3 | |
506 | ; FIXME: should use die macro or some such | |
507 | (define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1 | |
508 | ("0" "1" "2" "3" "4" "5" "6" "7" | |
509 | "8" "9" "10" "11" "12" "13" "14" "15") | |
510 | ) | |
511 | ||
512 | ; insn-op2: bits 8-11 | |
513 | ; FIXME: should use die macro or some such | |
514 | (define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2 | |
515 | ("0" "1" "2" "3" "4" "5" "6" "7" | |
516 | "8" "9" "10" "11" "12" "13" "14" "15") | |
517 | ) | |
518 | \f | |
519 | ; Hardware pieces. | |
520 | ; These entries list the elements of the raw hardware. | |
521 | ; They're also used to provide tables and other elements of the assembly | |
522 | ; language. | |
523 | ||
524 | (dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) | |
525 | ||
526 | (dnh h-hi16 "high 16 bits" () | |
527 | (immediate (UINT 16)) | |
528 | () () () | |
529 | ) | |
530 | ||
531 | ; These two aren't technically needed. | |
532 | ; They're here for illustration sake mostly. | |
533 | ; Plus they cause the value to be stored in the extraction buffers to only | |
534 | ; be 16 bits wide (vs 32 or 64). Whoopie ding. But it's fun. | |
535 | (dnh h-slo16 "signed low 16 bits" () | |
536 | (immediate (INT 16)) | |
537 | () () () | |
538 | ) | |
539 | (dnh h-ulo16 "unsigned low 16 bits" () | |
540 | (immediate (UINT 16)) | |
541 | () () () | |
542 | ) | |
543 | ||
544 | (define-keyword | |
545 | (name gr-names) | |
546 | (print-name h-gr) | |
547 | (prefix "") | |
548 | (values (fp 13) (lr 14) (sp 15) | |
549 | (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7) | |
550 | (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15)) | |
551 | ) | |
552 | ||
553 | (define-hardware | |
554 | (name h-gr) | |
555 | (comment "general registers") | |
556 | (attrs PROFILE CACHE-ADDR) | |
557 | (type register WI (16)) | |
558 | (indices extern-keyword gr-names) | |
559 | ) | |
560 | ||
561 | (define-keyword | |
562 | (name cr-names) | |
563 | (print-name h-cr) | |
564 | (prefix "") | |
565 | (values (psw 0) (cbr 1) (spi 2) (spu 3) | |
8ee9a8b2 | 566 | (bpc 6) (bbpsw 8) (bbpc 14) (evb 5) |
e866a257 AC |
567 | (cr0 0) (cr1 1) (cr2 2) (cr3 3) |
568 | (cr4 4) (cr5 5) (cr6 6) (cr7 7) | |
569 | (cr8 8) (cr9 9) (cr10 10) (cr11 11) | |
570 | (cr12 12) (cr13 13) (cr14 14) (cr15 15)) | |
571 | ) | |
572 | ||
573 | (define-hardware | |
574 | (name h-cr) | |
575 | (comment "control registers") | |
576 | (type register UWI (16)) | |
577 | (indices extern-keyword cr-names) | |
578 | (get (index) (c-call UWI "@cpu@_h_cr_get_handler" index)) | |
579 | (set (index newval) (c-call VOID "@cpu@_h_cr_set_handler" index newval)) | |
580 | ) | |
581 | ||
582 | ; The actual accumulator is only 56 bits. | |
583 | ; The top 8 bits are sign extended from bit 8 (when counting msb = bit 0). | |
584 | ; To simplify the accumulator instructions, no attempt is made to keep the | |
585 | ; top 8 bits properly sign extended (currently there's no point since they | |
586 | ; all ignore them). When the value is read it is properly sign extended | |
587 | ; [in the `get' handler]. | |
588 | (define-hardware | |
589 | (name h-accum) | |
590 | (comment "accumulator") | |
591 | (type register DI) | |
592 | (get () (c-call DI "@cpu@_h_accum_get_handler")) | |
593 | (set (newval) (c-call VOID "@cpu@_h_accum_set_handler" newval)) | |
594 | ) | |
595 | ||
596 | ; FIXME: Revisit after sanitization can be removed. Remove h-accum. | |
597 | (define-hardware | |
598 | (name h-accums) | |
599 | (comment "accumulators") | |
8ee9a8b2 | 600 | (attrs (MACH m32rx,m32r2)) |
e866a257 AC |
601 | (type register DI (2)) |
602 | (indices keyword "" ((a0 0) (a1 1))) | |
603 | ; get/set so a0 accesses are redirected to h-accum. | |
604 | ; They're also so reads can properly sign extend the value. | |
605 | ; FIXME: Needn't be a function call. | |
606 | (get (index) (c-call DI "@cpu@_h_accums_get_handler" index)) | |
607 | (set (index newval) (c-call VOID "@cpu@_h_accums_set_handler" index newval)) | |
608 | ) | |
609 | ||
610 | ; For condbit operand. FIXME: Need to allow spec of get/set of operands. | |
611 | ; Having this separate from h-psw keeps the parts that use it simpler | |
612 | ; [since they greatly outnumber those that use h-psw]. | |
613 | (dsh h-cond "condition bit" () (register BI)) | |
614 | ||
615 | ; The actual values of psw,bpsw,bbpsw are recorded here to allow access | |
616 | ; to them as a unit. | |
617 | (define-hardware | |
618 | (name h-psw) | |
619 | (comment "psw part of psw") | |
620 | (type register UQI) | |
621 | ; get/set to handle cond bit. | |
622 | ; FIXME: missing: use's and clobber's | |
623 | ; FIXME: remove c-call? | |
624 | (get () (c-call UQI "@cpu@_h_psw_get_handler")) | |
625 | (set (newval) (c-call VOID "@cpu@_h_psw_set_handler" newval)) | |
626 | ) | |
627 | (dsh h-bpsw "backup psw" () (register UQI)) | |
628 | (dsh h-bbpsw "backup bpsw" () (register UQI)) | |
629 | ||
630 | ; FIXME: Later make add get/set specs and support SMP. | |
631 | (dsh h-lock "lock" () (register BI)) | |
632 | \f | |
633 | ; Instruction Operands. | |
634 | ; These entries provide a layer between the assembler and the raw hardware | |
635 | ; description, and are used to refer to hardware elements in the semantic | |
636 | ; code. Usually there's a bit of over-specification, but in more complicated | |
637 | ; instruction sets there isn't. | |
638 | ||
639 | ; M32R specific operand attributes: | |
640 | ||
641 | (define-attr | |
642 | (for operand) | |
643 | (type boolean) | |
644 | (name HASH-PREFIX) | |
645 | (comment "immediates have an optional '#' prefix") | |
646 | ) | |
647 | ||
648 | ; ??? Convention says this should be o-sr, but then the insn definitions | |
649 | ; should refer to o-sr which is clumsy. The "o-" could be implicit, but | |
650 | ; then it should be implicit for all the symbols here, but then there would | |
651 | ; be confusion between (f-)simm8 and (h-)simm8. | |
652 | ; So for now the rule is exactly as it appears here. | |
653 | ||
654 | (dnop sr "source register" () h-gr f-r2) | |
655 | (dnop dr "destination register" () h-gr f-r1) | |
656 | ;; The assembler relies upon the fact that dr and src1 are the same field. | |
657 | ;; FIXME: Revisit. | |
658 | (dnop src1 "source register 1" () h-gr f-r1) | |
659 | (dnop src2 "source register 2" () h-gr f-r2) | |
660 | (dnop scr "source control register" () h-cr f-r2) | |
661 | (dnop dcr "destination control register" () h-cr f-r1) | |
662 | ||
663 | (dnop simm8 "8 bit signed immediate" (HASH-PREFIX) h-sint f-simm8) | |
664 | (dnop simm16 "16 bit signed immediate" (HASH-PREFIX) h-sint f-simm16) | |
8ee9a8b2 | 665 | (dnop uimm3 "3 bit unsigned number" (HASH-PREFIX) h-uint f-uimm3) |
e866a257 AC |
666 | (dnop uimm4 "4 bit trap number" (HASH-PREFIX) h-uint f-uimm4) |
667 | (dnop uimm5 "5 bit shift count" (HASH-PREFIX) h-uint f-uimm5) | |
8ee9a8b2 | 668 | (dnop uimm8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm8) |
e866a257 AC |
669 | (dnop uimm16 "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm16) |
670 | ||
8ee9a8b2 NC |
671 | (dnop imm1 "1 bit immediate" ((MACH m32rx,m32r2) HASH-PREFIX) h-uint f-imm1) |
672 | (dnop accd "accumulator destination register" ((MACH m32rx,m32r2)) h-accums f-accd) | |
673 | (dnop accs "accumulator source register" ((MACH m32rx,m32r2)) h-accums f-accs) | |
674 | (dnop acc "accumulator reg (d)" ((MACH m32rx,m32r2)) h-accums f-acc) | |
e866a257 AC |
675 | |
676 | ; slo16,ulo16 are used in both with-hash-prefix/no-hash-prefix cases. | |
677 | ; e.g. add3 r3,r3,#1 and ld r3,@(4,r4). We could use HASH-PREFIX. | |
678 | ; Instead we create a fake operand `hash'. The m32r is an illustration port, | |
679 | ; so we often try out various ways of doing things. | |
680 | ||
681 | (define-operand (name hash) (comment "# prefix") (attrs) | |
682 | (type h-sint) ; doesn't really matter | |
683 | (index f-nil) | |
684 | (handlers (parse "hash") (print "hash")) | |
685 | ) | |
686 | ||
687 | ; For high(foo),shigh(foo). | |
688 | (define-operand | |
689 | (name hi16) | |
690 | (comment "high 16 bit immediate, sign optional") | |
691 | (attrs) | |
692 | (type h-hi16) | |
693 | (index f-hi16) | |
694 | (handlers (parse "hi16")) | |
695 | ) | |
696 | ||
697 | ; For low(foo),sda(foo). | |
698 | (define-operand | |
699 | (name slo16) | |
700 | (comment "16 bit signed immediate, for low()") | |
701 | (attrs) | |
702 | (type h-slo16) | |
703 | (index f-simm16) | |
704 | (handlers (parse "slo16")) | |
705 | ) | |
706 | ||
707 | ; For low(foo). | |
708 | (define-operand | |
709 | (name ulo16) | |
710 | (comment "16 bit unsigned immediate, for low()") | |
711 | (attrs) | |
712 | (type h-ulo16) | |
713 | (index f-uimm16) | |
714 | (handlers (parse "ulo16")) | |
715 | ) | |
716 | ||
717 | (dnop uimm24 "24 bit address" (HASH-PREFIX) h-addr f-uimm24) | |
718 | ||
719 | (define-operand | |
720 | (name disp8) | |
721 | (comment "8 bit displacement") | |
722 | (attrs RELAX) | |
723 | (type h-iaddr) | |
724 | (index f-disp8) | |
725 | ; ??? Early experiments had insert/extract fields here. | |
726 | ; Moving these to f-disp8 made things cleaner, but may wish to re-introduce | |
727 | ; fields here to handle more complicated cases. | |
728 | ) | |
729 | ||
730 | (dnop disp16 "16 bit displacement" () h-iaddr f-disp16) | |
731 | (dnop disp24 "24 bit displacement" (RELAX) h-iaddr f-disp24) | |
732 | ||
733 | ; These hardware elements are refered to frequently. | |
734 | ||
735 | (dnop condbit "condition bit" (SEM-ONLY) h-cond f-nil) | |
736 | (dnop accum "accumulator" (SEM-ONLY) h-accum f-nil) | |
737 | \f | |
738 | ; Instruction definitions. | |
739 | ; | |
740 | ; Notes while wip: | |
741 | ; - dni is a cover macro to the real "this is an instruction" keyword. | |
742 | ; The syntax of the real one is yet to be determined. | |
743 | ; At the lowest level (i.e. the "real" one) it will probably take a variable | |
744 | ; list of arguments where each argument [perhaps after the standard three of | |
745 | ; name, comment, attrs] is "(keyword arg-to-keyword)". This syntax is simple | |
746 | ; and yet completely upward extensible. And given the macro facility, one | |
747 | ; needn't code at that low a level so even though it'll be more verbose than | |
748 | ; necessary it won't matter. This same reasoning can be applied to most | |
749 | ; types of entries in this file. | |
750 | ||
751 | ; M32R specific instruction attributes: | |
752 | ||
753 | ; FILL-SLOT: Need next insn to begin on 32 bit boundary. | |
754 | ; (A "slot" as used here is a 32 bit quantity that can either be filled with | |
755 | ; one 32 bit insn or two 16 bit insns which go in the "left bin" and "right | |
756 | ; bin" where the left bin is the one with a lower address). | |
757 | ||
758 | (define-attr | |
759 | (for insn) | |
760 | (type boolean) | |
761 | (name FILL-SLOT) | |
762 | (comment "fill right bin with `nop' if insn is in left bin") | |
763 | ) | |
764 | ||
765 | (define-attr | |
766 | (for insn) | |
767 | (type boolean) | |
768 | (name SPECIAL) | |
769 | (comment "non-public m32rx insn") | |
770 | ) | |
771 | ||
8ee9a8b2 NC |
772 | (define-attr |
773 | (for insn) | |
774 | (type boolean) | |
775 | (name SPECIAL_M32R) | |
776 | (comment "non-public m32r insn") | |
777 | ) | |
778 | ||
779 | (define-attr | |
780 | (for insn) | |
781 | (type boolean) | |
782 | (name SPECIAL_FLOAT) | |
783 | (comment "floating point insn") | |
784 | ) | |
785 | ||
e866a257 AC |
786 | ; IDOC attribute for instruction documentation. |
787 | ||
788 | (define-attr | |
789 | (for insn) | |
790 | (type enum) | |
791 | (name IDOC) | |
792 | (comment "insn kind for documentation") | |
793 | (attrs META) | |
794 | (values | |
795 | (MEM - () "Memory") | |
796 | (ALU - () "ALU") | |
797 | (BR - () "Branch") | |
798 | (ACCUM - () "Accumulator") | |
799 | (MAC - () "Multiply/Accumulate") | |
800 | (MISC - () "Miscellaneous") | |
801 | ) | |
802 | ) | |
803 | ||
804 | (define-pmacro (bin-op mnemonic op2-op sem-op imm-prefix imm) | |
805 | (begin | |
806 | (dni mnemonic | |
807 | (.str mnemonic " reg/reg") | |
808 | ((PIPE OS) (IDOC ALU)) | |
809 | (.str mnemonic " $dr,$sr") | |
810 | (+ OP1_0 op2-op dr sr) | |
811 | (set dr (sem-op dr sr)) | |
812 | () | |
813 | ) | |
814 | (dni (.sym mnemonic "3") | |
815 | (.str mnemonic " reg/" imm) | |
816 | ((IDOC ALU)) | |
817 | (.str mnemonic "3 $dr,$sr," imm-prefix "$" imm) | |
818 | (+ OP1_8 op2-op dr sr imm) | |
819 | (set dr (sem-op sr imm)) | |
820 | () | |
821 | ) | |
822 | ) | |
823 | ) | |
824 | (bin-op add OP2_10 add "$hash" slo16) | |
825 | ; sub isn't present because sub3 doesn't exist. | |
826 | (bin-op and OP2_12 and "" uimm16) | |
827 | (bin-op or OP2_14 or "$hash" ulo16) | |
828 | (bin-op xor OP2_13 xor "" uimm16) | |
829 | ||
830 | (dni addi "addi" | |
831 | ((PIPE OS) (IDOC ALU)) | |
832 | ;#.(string-append "addi " "$dr,$simm8") ; #. experiment | |
833 | "addi $dr,$simm8" | |
834 | (+ OP1_4 dr simm8) | |
835 | (set dr (add dr simm8)) | |
836 | ((m32r/d (unit u-exec)) | |
8ee9a8b2 NC |
837 | (m32rx (unit u-exec)) |
838 | (m32r2 (unit u-exec))) | |
e866a257 AC |
839 | ) |
840 | ||
841 | (dni addv "addv" | |
842 | ((PIPE OS) (IDOC ALU)) | |
843 | "addv $dr,$sr" | |
844 | (+ OP1_0 OP2_8 dr sr) | |
845 | (parallel () | |
846 | (set dr (add dr sr)) | |
847 | (set condbit (add-oflag dr sr (const 0)))) | |
848 | () | |
849 | ) | |
850 | ||
851 | (dni addv3 "addv3" | |
852 | ((IDOC ALU)) | |
853 | "addv3 $dr,$sr,$simm16" | |
854 | (+ OP1_8 OP2_8 dr sr simm16) | |
855 | (parallel () | |
856 | (set dr (add sr simm16)) | |
857 | (set condbit (add-oflag sr simm16 (const 0)))) | |
858 | () | |
859 | ) | |
860 | ||
861 | (dni addx "addx" | |
862 | ((PIPE OS) (IDOC ALU)) | |
863 | "addx $dr,$sr" | |
864 | (+ OP1_0 OP2_9 dr sr) | |
865 | (parallel () | |
866 | (set dr (addc dr sr condbit)) | |
867 | (set condbit (add-cflag dr sr condbit))) | |
868 | () | |
869 | ) | |
870 | ||
871 | (dni bc8 "bc with 8 bit displacement" | |
872 | (COND-CTI (PIPE O) (IDOC BR)) | |
873 | "bc.s $disp8" | |
874 | (+ OP1_7 (f-r1 12) disp8) | |
875 | (if condbit (set pc disp8)) | |
876 | ((m32r/d (unit u-cti)) | |
8ee9a8b2 NC |
877 | (m32rx (unit u-cti)) |
878 | (m32r2 (unit u-cti))) | |
e866a257 AC |
879 | ) |
880 | ||
881 | (dnmi bc8r "relaxable bc8" | |
882 | (COND-CTI RELAXABLE (PIPE O) (IDOC BR)) | |
883 | "bc $disp8" | |
884 | (emit bc8 disp8) | |
885 | ) | |
886 | ||
887 | (dni bc24 "bc with 24 bit displacement" | |
888 | (COND-CTI (IDOC BR)) | |
889 | "bc.l $disp24" | |
890 | (+ OP1_15 (f-r1 12) disp24) | |
891 | (if condbit (set pc disp24)) | |
892 | ((m32r/d (unit u-cti)) | |
8ee9a8b2 NC |
893 | (m32rx (unit u-cti)) |
894 | (m32r2 (unit u-cti))) | |
e866a257 AC |
895 | ) |
896 | ||
897 | (dnmi bc24r "relaxable bc24" | |
898 | (COND-CTI RELAXED (IDOC BR)) | |
899 | "bc $disp24" | |
900 | (emit bc24 disp24) | |
901 | ) | |
902 | ||
903 | (dni beq "beq" | |
904 | (COND-CTI (IDOC BR)) | |
905 | "beq $src1,$src2,$disp16" | |
906 | (+ OP1_11 OP2_0 src1 src2 disp16) | |
907 | (if (eq src1 src2) (set pc disp16)) | |
908 | ((m32r/d (unit u-cti) (unit u-cmp (cycles 0))) | |
8ee9a8b2 NC |
909 | (m32rx (unit u-cti) (unit u-cmp (cycles 0))) |
910 | (m32r2 (unit u-cti) (unit u-cmp (cycles 0)))) | |
e866a257 AC |
911 | ) |
912 | ||
913 | (define-pmacro (cbranch sym comment op2-op comp-op) | |
914 | (dni sym comment (COND-CTI (IDOC BR)) | |
915 | (.str sym " $src2,$disp16") | |
916 | (+ OP1_11 op2-op (f-r1 0) src2 disp16) | |
917 | (if (comp-op src2 (const WI 0)) (set pc disp16)) | |
918 | ((m32r/d (unit u-cti) (unit u-cmp (cycles 0))) | |
8ee9a8b2 NC |
919 | (m32rx (unit u-cti) (unit u-cmp (cycles 0))) |
920 | (m32r2 (unit u-cti) (unit u-cmp (cycles 0)))) | |
e866a257 AC |
921 | ) |
922 | ) | |
923 | (cbranch beqz "beqz" OP2_8 eq) | |
924 | (cbranch bgez "bgez" OP2_11 ge) | |
925 | (cbranch bgtz "bgtz" OP2_13 gt) | |
926 | (cbranch blez "blez" OP2_12 le) | |
927 | (cbranch bltz "bltz" OP2_10 lt) | |
928 | (cbranch bnez "bnez" OP2_9 ne) | |
929 | ||
930 | (dni bl8 "bl with 8 bit displacement" | |
931 | (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR)) | |
932 | "bl.s $disp8" | |
933 | (+ OP1_7 (f-r1 14) disp8) | |
934 | (sequence () | |
935 | (set (reg h-gr 14) | |
936 | (add (and pc (const -4)) (const 4))) | |
937 | (set pc disp8)) | |
938 | ((m32r/d (unit u-cti)) | |
8ee9a8b2 NC |
939 | (m32rx (unit u-cti)) |
940 | (m32r2 (unit u-cti))) | |
e866a257 AC |
941 | ) |
942 | ||
943 | (dnmi bl8r "relaxable bl8" | |
944 | (UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR)) | |
945 | "bl $disp8" | |
946 | (emit bl8 disp8) | |
947 | ) | |
948 | ||
949 | (dni bl24 "bl with 24 bit displacement" | |
950 | (UNCOND-CTI (IDOC BR)) | |
951 | "bl.l $disp24" | |
952 | (+ OP1_15 (f-r1 14) disp24) | |
953 | (sequence () | |
954 | (set (reg h-gr 14) (add pc (const 4))) | |
955 | (set pc disp24)) | |
956 | ((m32r/d (unit u-cti)) | |
8ee9a8b2 NC |
957 | (m32rx (unit u-cti)) |
958 | (m32r2 (unit u-cti))) | |
e866a257 AC |
959 | ) |
960 | ||
961 | (dnmi bl24r "relaxable bl24" | |
962 | (UNCOND-CTI RELAXED (IDOC BR)) | |
963 | "bl $disp24" | |
964 | (emit bl24 disp24) | |
965 | ) | |
966 | ||
967 | (dni bcl8 "bcl with 8 bit displacement" | |
8ee9a8b2 | 968 | (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR)) |
e866a257 AC |
969 | "bcl.s $disp8" |
970 | (+ OP1_7 (f-r1 8) disp8) | |
971 | (if condbit | |
972 | (sequence () | |
973 | (set (reg h-gr 14) | |
974 | (add (and pc (const -4)) | |
975 | (const 4))) | |
976 | (set pc disp8))) | |
8ee9a8b2 NC |
977 | ((m32rx (unit u-cti)) |
978 | (m32r2 (unit u-cti))) | |
e866a257 AC |
979 | ) |
980 | ||
981 | (dnmi bcl8r "relaxable bcl8" | |
8ee9a8b2 | 982 | (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR)) |
e866a257 AC |
983 | "bcl $disp8" |
984 | (emit bcl8 disp8) | |
985 | ) | |
986 | ||
987 | (dni bcl24 "bcl with 24 bit displacement" | |
8ee9a8b2 | 988 | (COND-CTI (MACH m32rx,m32r2) (IDOC BR)) |
e866a257 AC |
989 | "bcl.l $disp24" |
990 | (+ OP1_15 (f-r1 8) disp24) | |
991 | (if condbit | |
992 | (sequence () | |
993 | (set (reg h-gr 14) (add pc (const 4))) | |
994 | (set pc disp24))) | |
8ee9a8b2 NC |
995 | ((m32rx (unit u-cti)) |
996 | (m32r2 (unit u-cti))) | |
e866a257 AC |
997 | ) |
998 | ||
999 | (dnmi bcl24r "relaxable bcl24" | |
8ee9a8b2 | 1000 | (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR)) |
e866a257 AC |
1001 | "bcl $disp24" |
1002 | (emit bcl24 disp24) | |
1003 | ) | |
1004 | ||
1005 | (dni bnc8 "bnc with 8 bit displacement" | |
1006 | (COND-CTI (PIPE O) (IDOC BR)) | |
1007 | "bnc.s $disp8" | |
1008 | (+ OP1_7 (f-r1 13) disp8) | |
1009 | (if (not condbit) (set pc disp8)) | |
1010 | ((m32r/d (unit u-cti)) | |
8ee9a8b2 NC |
1011 | (m32rx (unit u-cti)) |
1012 | (m32r2 (unit u-cti))) | |
e866a257 AC |
1013 | ) |
1014 | ||
1015 | (dnmi bnc8r "relaxable bnc8" | |
1016 | (COND-CTI RELAXABLE (PIPE O) (IDOC BR)) | |
1017 | "bnc $disp8" | |
1018 | (emit bnc8 disp8) | |
1019 | ) | |
1020 | ||
1021 | (dni bnc24 "bnc with 24 bit displacement" | |
1022 | (COND-CTI (IDOC BR)) | |
1023 | "bnc.l $disp24" | |
1024 | (+ OP1_15 (f-r1 13) disp24) | |
1025 | (if (not condbit) (set pc disp24)) | |
1026 | ((m32r/d (unit u-cti)) | |
8ee9a8b2 NC |
1027 | (m32rx (unit u-cti)) |
1028 | (m32r2 (unit u-cti))) | |
e866a257 AC |
1029 | ) |
1030 | ||
1031 | (dnmi bnc24r "relaxable bnc24" | |
1032 | (COND-CTI RELAXED (IDOC BR)) | |
1033 | "bnc $disp24" | |
1034 | (emit bnc24 disp24) | |
1035 | ) | |
1036 | ||
1037 | (dni bne "bne" | |
1038 | (COND-CTI (IDOC BR)) | |
1039 | "bne $src1,$src2,$disp16" | |
1040 | (+ OP1_11 OP2_1 src1 src2 disp16) | |
1041 | (if (ne src1 src2) (set pc disp16)) | |
1042 | ((m32r/d (unit u-cti) (unit u-cmp (cycles 0))) | |
8ee9a8b2 NC |
1043 | (m32rx (unit u-cti) (unit u-cmp (cycles 0))) |
1044 | (m32r2 (unit u-cti) (unit u-cmp (cycles 0)))) | |
e866a257 AC |
1045 | ) |
1046 | ||
1047 | (dni bra8 "bra with 8 bit displacement" | |
1048 | (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR)) | |
1049 | "bra.s $disp8" | |
1050 | (+ OP1_7 (f-r1 15) disp8) | |
1051 | (set pc disp8) | |
1052 | ((m32r/d (unit u-cti)) | |
8ee9a8b2 NC |
1053 | (m32rx (unit u-cti)) |
1054 | (m32r2 (unit u-cti))) | |
e866a257 AC |
1055 | ) |
1056 | ||
1057 | (dnmi bra8r "relaxable bra8" | |
1058 | (UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR)) | |
1059 | "bra $disp8" | |
1060 | (emit bra8 disp8) | |
1061 | ) | |
1062 | ||
1063 | (dni bra24 "bra with 24 displacement" | |
1064 | (UNCOND-CTI (IDOC BR)) | |
1065 | "bra.l $disp24" | |
1066 | (+ OP1_15 (f-r1 15) disp24) | |
1067 | (set pc disp24) | |
1068 | ((m32r/d (unit u-cti)) | |
8ee9a8b2 NC |
1069 | (m32rx (unit u-cti)) |
1070 | (m32r2 (unit u-cti))) | |
e866a257 AC |
1071 | ) |
1072 | ||
1073 | (dnmi bra24r "relaxable bra24" | |
1074 | (UNCOND-CTI RELAXED (IDOC BR)) | |
1075 | "bra $disp24" | |
1076 | (emit bra24 disp24) | |
1077 | ) | |
1078 | ||
1079 | (dni bncl8 "bncl with 8 bit displacement" | |
8ee9a8b2 | 1080 | (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR)) |
e866a257 AC |
1081 | "bncl.s $disp8" |
1082 | (+ OP1_7 (f-r1 9) disp8) | |
1083 | (if (not condbit) | |
1084 | (sequence () | |
1085 | (set (reg h-gr 14) | |
1086 | (add (and pc (const -4)) | |
1087 | (const 4))) | |
1088 | (set pc disp8))) | |
8ee9a8b2 NC |
1089 | ((m32rx (unit u-cti)) |
1090 | (m32r2 (unit u-cti))) | |
e866a257 AC |
1091 | ) |
1092 | ||
1093 | (dnmi bncl8r "relaxable bncl8" | |
8ee9a8b2 | 1094 | (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR)) |
e866a257 AC |
1095 | "bncl $disp8" |
1096 | (emit bncl8 disp8) | |
1097 | ) | |
1098 | ||
1099 | (dni bncl24 "bncl with 24 bit displacement" | |
8ee9a8b2 | 1100 | (COND-CTI (MACH m32rx,m32r2) (IDOC BR)) |
e866a257 AC |
1101 | "bncl.l $disp24" |
1102 | (+ OP1_15 (f-r1 9) disp24) | |
1103 | (if (not condbit) | |
1104 | (sequence () | |
1105 | (set (reg h-gr 14) (add pc (const 4))) | |
1106 | (set pc disp24))) | |
8ee9a8b2 NC |
1107 | ((m32rx (unit u-cti)) |
1108 | (m32r2 (unit u-cti))) | |
e866a257 AC |
1109 | ) |
1110 | ||
1111 | (dnmi bncl24r "relaxable bncl24" | |
8ee9a8b2 | 1112 | (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR)) |
e866a257 AC |
1113 | "bncl $disp24" |
1114 | (emit bncl24 disp24) | |
1115 | ) | |
1116 | ||
1117 | (dni cmp "cmp" | |
1118 | ((PIPE OS) (IDOC ALU)) | |
1119 | "cmp $src1,$src2" | |
1120 | (+ OP1_0 OP2_4 src1 src2) | |
1121 | (set condbit (lt src1 src2)) | |
1122 | ((m32r/d (unit u-cmp)) | |
8ee9a8b2 NC |
1123 | (m32rx (unit u-cmp)) |
1124 | (m32r2 (unit u-cmp))) | |
e866a257 AC |
1125 | ) |
1126 | ||
1127 | (dni cmpi "cmpi" | |
1128 | ((IDOC ALU)) | |
1129 | "cmpi $src2,$simm16" | |
1130 | (+ OP1_8 (f-r1 0) OP2_4 src2 simm16) | |
1131 | (set condbit (lt src2 simm16)) | |
1132 | ((m32r/d (unit u-cmp)) | |
8ee9a8b2 NC |
1133 | (m32rx (unit u-cmp)) |
1134 | (m32r2 (unit u-cmp))) | |
e866a257 AC |
1135 | ) |
1136 | ||
1137 | (dni cmpu "cmpu" | |
1138 | ((PIPE OS) (IDOC ALU)) | |
1139 | "cmpu $src1,$src2" | |
1140 | (+ OP1_0 OP2_5 src1 src2) | |
1141 | (set condbit (ltu src1 src2)) | |
1142 | ((m32r/d (unit u-cmp)) | |
8ee9a8b2 NC |
1143 | (m32rx (unit u-cmp)) |
1144 | (m32r2 (unit u-cmp))) | |
e866a257 AC |
1145 | ) |
1146 | ||
1147 | (dni cmpui "cmpui" | |
1148 | ((IDOC ALU)) | |
1149 | "cmpui $src2,$simm16" | |
1150 | (+ OP1_8 (f-r1 0) OP2_5 src2 simm16) | |
1151 | (set condbit (ltu src2 simm16)) | |
1152 | ((m32r/d (unit u-cmp)) | |
8ee9a8b2 NC |
1153 | (m32rx (unit u-cmp)) |
1154 | (m32r2 (unit u-cmp))) | |
e866a257 AC |
1155 | ) |
1156 | ||
1157 | (dni cmpeq "cmpeq" | |
8ee9a8b2 | 1158 | ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU)) |
e866a257 AC |
1159 | "cmpeq $src1,$src2" |
1160 | (+ OP1_0 OP2_6 src1 src2) | |
1161 | (set condbit (eq src1 src2)) | |
8ee9a8b2 NC |
1162 | ((m32rx (unit u-cmp)) |
1163 | (m32r2 (unit u-cmp))) | |
e866a257 AC |
1164 | ) |
1165 | ||
1166 | (dni cmpz "cmpz" | |
8ee9a8b2 | 1167 | ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU)) |
e866a257 AC |
1168 | "cmpz $src2" |
1169 | (+ OP1_0 OP2_7 (f-r1 0) src2) | |
1170 | (set condbit (eq src2 (const 0))) | |
8ee9a8b2 NC |
1171 | ((m32rx (unit u-cmp)) |
1172 | (m32r2 (unit u-cmp))) | |
e866a257 AC |
1173 | ) |
1174 | ||
1175 | (dni div "div" | |
1176 | ((IDOC ALU)) | |
1177 | "div $dr,$sr" | |
1178 | (+ OP1_9 OP2_0 dr sr (f-simm16 0)) | |
1179 | (if (ne sr (const 0)) (set dr (div dr sr))) | |
1180 | ((m32r/d (unit u-exec (cycles 37))) | |
8ee9a8b2 NC |
1181 | (m32rx (unit u-exec (cycles 37))) |
1182 | (m32r2 (unit u-exec (cycles 37)))) | |
e866a257 AC |
1183 | ) |
1184 | ||
1185 | (dni divu "divu" | |
1186 | ((IDOC ALU)) | |
1187 | "divu $dr,$sr" | |
1188 | (+ OP1_9 OP2_1 dr sr (f-simm16 0)) | |
1189 | (if (ne sr (const 0)) (set dr (udiv dr sr))) | |
1190 | ((m32r/d (unit u-exec (cycles 37))) | |
8ee9a8b2 NC |
1191 | (m32rx (unit u-exec (cycles 37))) |
1192 | (m32r2 (unit u-exec (cycles 37)))) | |
e866a257 AC |
1193 | ) |
1194 | ||
1195 | (dni rem "rem" | |
1196 | ((IDOC ALU)) | |
1197 | "rem $dr,$sr" | |
1198 | (+ OP1_9 OP2_2 dr sr (f-simm16 0)) | |
1199 | ; FIXME: Check rounding direction. | |
1200 | (if (ne sr (const 0)) (set dr (mod dr sr))) | |
1201 | ((m32r/d (unit u-exec (cycles 37))) | |
8ee9a8b2 NC |
1202 | (m32rx (unit u-exec (cycles 37))) |
1203 | (m32r2 (unit u-exec (cycles 37)))) | |
e866a257 AC |
1204 | ) |
1205 | ||
1206 | (dni remu "remu" | |
1207 | ((IDOC ALU)) | |
1208 | "remu $dr,$sr" | |
1209 | (+ OP1_9 OP2_3 dr sr (f-simm16 0)) | |
1210 | ; FIXME: Check rounding direction. | |
1211 | (if (ne sr (const 0)) (set dr (umod dr sr))) | |
1212 | ((m32r/d (unit u-exec (cycles 37))) | |
8ee9a8b2 NC |
1213 | (m32rx (unit u-exec (cycles 37))) |
1214 | (m32r2 (unit u-exec (cycles 37)))) | |
1215 | ) | |
1216 | ||
1217 | (dni remh "remh" | |
1218 | ((MACH m32r2)) | |
1219 | "remh $dr,$sr" | |
1220 | (+ OP1_9 OP2_2 dr sr (f-simm16 #x10)) | |
1221 | ; FIXME: Check rounding direction. | |
1222 | (if (ne sr (const 0)) (set dr (mod (ext WI (trunc HI dr)) sr))) | |
1223 | ((m32r2 (unit u-exec (cycles 21)))) | |
1224 | ) | |
1225 | ||
1226 | (dni remuh "remuh" | |
1227 | ((MACH m32r2)) | |
1228 | "remuh $dr,$sr" | |
1229 | (+ OP1_9 OP2_3 dr sr (f-simm16 #x10)) | |
1230 | ; FIXME: Check rounding direction. | |
1231 | (if (ne sr (const 0)) (set dr (umod dr sr))) | |
1232 | ((m32r2 (unit u-exec (cycles 21)))) | |
1233 | ) | |
1234 | ||
1235 | (dni remb "remb" | |
1236 | ((MACH m32r2)) | |
1237 | "remb $dr,$sr" | |
1238 | (+ OP1_9 OP2_2 dr sr (f-simm16 #x18)) | |
1239 | ; FIXME: Check rounding direction. | |
1240 | (if (ne sr (const 0)) (set dr (mod (ext WI (trunc BI dr)) sr))) | |
1241 | ((m32r2 (unit u-exec (cycles 21)))) | |
1242 | ) | |
1243 | ||
1244 | (dni remub "remub" | |
1245 | ((MACH m32r2)) | |
1246 | "remub $dr,$sr" | |
1247 | (+ OP1_9 OP2_3 dr sr (f-simm16 #x18)) | |
1248 | ; FIXME: Check rounding direction. | |
1249 | (if (ne sr (const 0)) (set dr (umod dr sr))) | |
1250 | ((m32r2 (unit u-exec (cycles 21)))) | |
1251 | ) | |
1252 | ||
1253 | (dni divuh "divuh" | |
1254 | ((MACH m32r2)) | |
1255 | "divuh $dr,$sr" | |
1256 | (+ OP1_9 OP2_1 dr sr (f-simm16 #x10)) | |
1257 | (if (ne sr (const 0)) (set dr (udiv dr sr))) | |
1258 | ((m32r2 (unit u-exec (cycles 21)))) | |
1259 | ) | |
1260 | ||
1261 | (dni divb "divb" | |
1262 | ((MACH m32r2)) | |
1263 | "divb $dr,$sr" | |
1264 | (+ OP1_9 OP2_0 dr sr (f-simm16 #x18)) | |
1265 | (if (ne sr (const 0)) (set dr (div (ext WI (trunc BI dr)) sr))) | |
1266 | ((m32r2 (unit u-exec (cycles 21)))) | |
1267 | ) | |
1268 | ||
1269 | (dni divub "divub" | |
1270 | ((MACH m32r2)) | |
1271 | "divub $dr,$sr" | |
1272 | (+ OP1_9 OP2_1 dr sr (f-simm16 #x18)) | |
1273 | (if (ne sr (const 0)) (set dr (udiv dr sr))) | |
1274 | ((m32r2 (unit u-exec (cycles 21)))) | |
e866a257 AC |
1275 | ) |
1276 | ||
1277 | (dni divh "divh" | |
8ee9a8b2 | 1278 | ((MACH m32rx,m32r2) (IDOC ALU)) |
e866a257 AC |
1279 | "divh $dr,$sr" |
1280 | (+ OP1_9 OP2_0 dr sr (f-simm16 #x10)) | |
1281 | (if (ne sr (const 0)) (set dr (div (ext WI (trunc HI dr)) sr))) | |
8ee9a8b2 NC |
1282 | ((m32rx (unit u-exec (cycles 21))) |
1283 | (m32r2 (unit u-exec (cycles 21)))) | |
e866a257 AC |
1284 | ) |
1285 | ||
1286 | (dni jc "jc" | |
8ee9a8b2 | 1287 | (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR)) |
e866a257 AC |
1288 | "jc $sr" |
1289 | (+ OP1_1 (f-r1 12) OP2_12 sr) | |
1290 | (if condbit (set pc (and sr (const -4)))) | |
8ee9a8b2 NC |
1291 | ((m32rx (unit u-cti)) |
1292 | (m32r2 (unit u-cti))) | |
e866a257 AC |
1293 | ) |
1294 | ||
1295 | (dni jnc "jnc" | |
8ee9a8b2 | 1296 | (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR)) |
e866a257 AC |
1297 | "jnc $sr" |
1298 | (+ OP1_1 (f-r1 13) OP2_12 sr) | |
1299 | (if (not condbit) (set pc (and sr (const -4)))) | |
8ee9a8b2 NC |
1300 | ((m32rx (unit u-cti)) |
1301 | (m32r2 (unit u-cti))) | |
e866a257 AC |
1302 | ) |
1303 | ||
1304 | (dni jl "jl" | |
1305 | (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR)) | |
1306 | "jl $sr" | |
1307 | (+ OP1_1 (f-r1 14) OP2_12 sr) | |
1308 | (parallel () | |
1309 | (set (reg h-gr 14) | |
1310 | (add (and pc (const -4)) (const 4))) | |
1311 | (set pc (and sr (const -4)))) | |
1312 | ((m32r/d (unit u-cti)) | |
8ee9a8b2 NC |
1313 | (m32rx (unit u-cti)) |
1314 | (m32r2 (unit u-cti))) | |
e866a257 AC |
1315 | ) |
1316 | ||
1317 | (dni jmp "jmp" | |
1318 | (UNCOND-CTI (PIPE O) (IDOC BR)) | |
1319 | "jmp $sr" | |
1320 | (+ OP1_1 (f-r1 15) OP2_12 sr) | |
1321 | (set pc (and sr (const -4))) | |
1322 | ; The above works now so this kludge has been commented out. | |
1323 | ; It's kept around because the f-r1 reference in the semantic part | |
1324 | ; should work. | |
1325 | ; FIXME: kludge, instruction decoding not finished. | |
1326 | ; But this should work, so that's another FIXME. | |
1327 | ;(sequence VOID (if VOID (eq SI f-r1 (const SI 14)) | |
1328 | ; FIXME: abuf->insn should be a macro of some sort. | |
1329 | ;(sequence VOID | |
1330 | ; (if VOID (eq SI (c-code SI "((abuf->insn >> 8) & 15)") | |
1331 | ; (const SI 14)) | |
1332 | ; (set WI (reg WI h-gr 14) | |
1333 | ; (add WI (and WI pc (const WI -4)) (const WI 4)))) | |
1334 | ; (set WI pc sr)) | |
1335 | ((m32r/d (unit u-cti)) | |
8ee9a8b2 NC |
1336 | (m32rx (unit u-cti)) |
1337 | (m32r2 (unit u-cti))) | |
e866a257 AC |
1338 | ) |
1339 | ||
1340 | (define-pmacro (no-ext-expr mode expr) expr) | |
1341 | (define-pmacro (ext-expr mode expr) (ext mode expr)) | |
1342 | (define-pmacro (zext-expr mode expr) (zext mode expr)) | |
1343 | ||
1344 | (define-pmacro (load-op suffix op2-op mode ext-op) | |
1345 | (begin | |
1346 | (dni (.sym ld suffix) (.str "ld" suffix) | |
1347 | ((PIPE O) (IDOC MEM)) | |
1348 | (.str "ld" suffix " $dr,@$sr") | |
1349 | (+ OP1_2 op2-op dr sr) | |
1350 | (set dr (ext-op WI (mem mode sr))) | |
1351 | ((m32r/d (unit u-load)) | |
8ee9a8b2 NC |
1352 | (m32rx (unit u-load)) |
1353 | (m32r2 (unit u-load))) | |
e866a257 AC |
1354 | ) |
1355 | (dnmi (.sym ld suffix "-2") (.str "ld" suffix "-2") | |
1356 | (NO-DIS (PIPE O) (IDOC MEM)) | |
1357 | (.str "ld" suffix " $dr,@($sr)") | |
1358 | (emit (.sym ld suffix) dr sr)) | |
1359 | (dni (.sym ld suffix -d) (.str "ld" suffix "-d") | |
1360 | ((IDOC MEM)) | |
1361 | (.str "ld" suffix " $dr,@($slo16,$sr)") | |
1362 | (+ OP1_10 op2-op dr sr slo16) | |
1363 | (set dr (ext-op WI (mem mode (add sr slo16)))) | |
1364 | ((m32r/d (unit u-load (cycles 2))) | |
8ee9a8b2 NC |
1365 | (m32rx (unit u-load (cycles 2))) |
1366 | (m32r2 (unit u-load (cycles 2)))) | |
e866a257 AC |
1367 | ) |
1368 | (dnmi (.sym ld suffix -d2) (.str "ld" suffix "-d2") | |
1369 | (NO-DIS (IDOC MEM)) | |
1370 | (.str "ld" suffix " $dr,@($sr,$slo16)") | |
1371 | (emit (.sym ld suffix -d) dr sr slo16)) | |
1372 | ) | |
1373 | ) | |
1374 | (load-op "" OP2_12 WI no-ext-expr) | |
1375 | (load-op b OP2_8 QI ext-expr) | |
1376 | (load-op h OP2_10 HI ext-expr) | |
1377 | (load-op ub OP2_9 QI zext-expr) | |
1378 | (load-op uh OP2_11 HI zext-expr) | |
1379 | ||
1380 | (dni ld-plus "ld+" | |
1381 | ((PIPE O) (IDOC MEM)) | |
1382 | "ld $dr,@$sr+" | |
1383 | (+ OP1_2 dr OP2_14 sr) | |
1384 | (parallel () | |
1385 | ; wip: memory addresses in profiling support | |
1386 | ;(set dr (name ld-mem (mem WI sr))) | |
1387 | (set dr (mem WI sr)) | |
1388 | (set sr (add sr (const 4)))) | |
1389 | ; Note: `pred' is the constraint. Also useful here is (ref name) | |
1390 | ; and returns true if operand <name> was referenced | |
1391 | ; (where "referenced" means _read_ if input operand and _written_ if | |
1392 | ; output operand). | |
1393 | ; args to unit are "unit-name (name1 value1) ..." | |
1394 | ; - cycles(done),issue,pred are also specified this way | |
1395 | ; - if unspecified, default is used | |
1396 | ; - for ins/outs, extra arg is passed that says what was specified | |
1397 | ; - this is AND'd with `written' for outs | |
1398 | ((m32r/d (unit u-load (pred (const 1))) | |
1399 | (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1)))) | |
1400 | (m32rx (unit u-load) | |
1401 | (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1)))) | |
8ee9a8b2 NC |
1402 | (m32r2 (unit u-load) |
1403 | (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1)))) | |
e866a257 AC |
1404 | ) |
1405 | ) | |
1406 | ||
1407 | (dnmi pop "pop" | |
8ee9a8b2 | 1408 | ((PIPE O) (IDOC MEM)) |
e866a257 AC |
1409 | "pop $dr" |
1410 | (emit ld-plus dr (sr 15)) ; "ld %0,@sp+" | |
1411 | ) | |
1412 | ||
1413 | (dni ld24 "ld24" | |
1414 | ((IDOC MEM)) | |
1415 | "ld24 $dr,$uimm24" | |
1416 | (+ OP1_14 dr uimm24) | |
1417 | (set dr uimm24) | |
1418 | () | |
1419 | ) | |
1420 | ||
1421 | ; ldi8 appears before ldi16 so we try the shorter version first | |
1422 | ||
1423 | (dni ldi8 "ldi8" | |
1424 | ((PIPE OS) (IDOC ALU)) | |
1425 | "ldi8 $dr,$simm8" | |
1426 | (+ OP1_6 dr simm8) | |
1427 | (set dr simm8) | |
1428 | () | |
1429 | ) | |
1430 | ||
1431 | (dnmi ldi8a "ldi8 alias" | |
1432 | ((PIPE OS) (IDOC ALU)) | |
1433 | "ldi $dr,$simm8" | |
1434 | (emit ldi8 dr simm8) | |
1435 | ) | |
1436 | ||
1437 | (dni ldi16 "ldi16" | |
1438 | ((IDOC ALU)) | |
1439 | "ldi16 $dr,$hash$slo16" | |
1440 | (+ OP1_9 OP2_15 (f-r2 0) dr slo16) | |
1441 | (set dr slo16) | |
1442 | () | |
1443 | ) | |
1444 | ||
1445 | (dnmi ldi16a "ldi16 alias" | |
1446 | ((IDOC ALU)) | |
1447 | "ldi $dr,$hash$slo16" | |
1448 | (emit ldi16 dr slo16) | |
1449 | ) | |
1450 | ||
1451 | (dni lock "lock" | |
1452 | ((PIPE O) (IDOC MISC)) | |
1453 | "lock $dr,@$sr" | |
1454 | (+ OP1_2 OP2_13 dr sr) | |
1455 | (sequence () | |
1456 | (set (reg h-lock) (const BI 1)) | |
1457 | (set dr (mem WI sr))) | |
1458 | ((m32r/d (unit u-load)) | |
8ee9a8b2 NC |
1459 | (m32rx (unit u-load)) |
1460 | (m32r2 (unit u-load))) | |
e866a257 AC |
1461 | ) |
1462 | ||
1463 | (dni machi "machi" | |
1464 | ( | |
1465 | ; (MACH m32r) is a temporary hack. This insn collides with machi-a | |
1466 | ; in the simulator so disable it for m32rx. | |
1467 | (MACH m32r) (PIPE S) (IDOC MAC) | |
1468 | ) | |
1469 | "machi $src1,$src2" | |
1470 | (+ OP1_3 OP2_4 src1 src2) | |
1471 | ; FIXME: TRACE_RESULT will print the wrong thing since we | |
1472 | ; alter one of the arguments. | |
1473 | (set accum | |
1474 | (sra DI | |
1475 | (sll DI | |
1476 | (add DI | |
1477 | accum | |
1478 | (mul DI | |
1479 | (ext DI (and WI src1 (const #xffff0000))) | |
1480 | (ext DI (trunc HI (sra WI src2 (const 16)))))) | |
1481 | (const 8)) | |
1482 | (const 8))) | |
1483 | ((m32r/d (unit u-mac))) | |
1484 | ) | |
1485 | ||
1486 | (dni machi-a "machi-a" | |
8ee9a8b2 | 1487 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
e866a257 AC |
1488 | "machi $src1,$src2,$acc" |
1489 | (+ OP1_3 src1 acc (f-op23 4) src2) | |
1490 | (set acc | |
1491 | (sra DI | |
1492 | (sll DI | |
1493 | (add DI | |
1494 | acc | |
1495 | (mul DI | |
1496 | (ext DI (and WI src1 (const #xffff0000))) | |
1497 | (ext DI (trunc HI (sra WI src2 (const 16)))))) | |
1498 | (const 8)) | |
1499 | (const 8))) | |
8ee9a8b2 NC |
1500 | ((m32rx (unit u-mac)) |
1501 | (m32r2 (unit u-mac))) | |
e866a257 AC |
1502 | ) |
1503 | ||
1504 | (dni maclo "maclo" | |
1505 | ((MACH m32r) (PIPE S) (IDOC MAC)) | |
1506 | "maclo $src1,$src2" | |
1507 | (+ OP1_3 OP2_5 src1 src2) | |
1508 | (set accum | |
1509 | (sra DI | |
1510 | (sll DI | |
1511 | (add DI | |
1512 | accum | |
1513 | (mul DI | |
1514 | (ext DI (sll WI src1 (const 16))) | |
1515 | (ext DI (trunc HI src2)))) | |
1516 | (const 8)) | |
1517 | (const 8))) | |
1518 | ((m32r/d (unit u-mac))) | |
1519 | ) | |
1520 | ||
1521 | (dni maclo-a "maclo-a" | |
8ee9a8b2 | 1522 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
e866a257 AC |
1523 | "maclo $src1,$src2,$acc" |
1524 | (+ OP1_3 src1 acc (f-op23 5) src2) | |
1525 | (set acc | |
1526 | (sra DI | |
1527 | (sll DI | |
1528 | (add DI | |
1529 | acc | |
1530 | (mul DI | |
1531 | (ext DI (sll WI src1 (const 16))) | |
1532 | (ext DI (trunc HI src2)))) | |
1533 | (const 8)) | |
1534 | (const 8))) | |
8ee9a8b2 NC |
1535 | ((m32rx (unit u-mac)) |
1536 | (m32r2 (unit u-mac))) | |
e866a257 AC |
1537 | ) |
1538 | ||
1539 | (dni macwhi "macwhi" | |
1540 | ((MACH m32r) (PIPE S) (IDOC MAC)) | |
1541 | "macwhi $src1,$src2" | |
1542 | (+ OP1_3 OP2_6 src1 src2) | |
1543 | (set accum | |
1544 | (sra DI | |
1545 | (sll DI | |
1546 | (add DI | |
1547 | accum | |
1548 | (mul DI | |
1549 | (ext DI src1) | |
1550 | (ext DI (trunc HI (sra WI src2 (const 16)))))) | |
1551 | (const 8)) | |
1552 | (const 8))) | |
1553 | ((m32r/d (unit u-mac))) | |
1554 | ) | |
1555 | ||
1556 | (dni macwhi-a "macwhi-a" | |
8ee9a8b2 | 1557 | ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC)) |
e866a257 AC |
1558 | "macwhi $src1,$src2,$acc" |
1559 | (+ OP1_3 src1 acc (f-op23 6) src2) | |
1560 | ; Note that this doesn't do the sign extension, which is correct. | |
1561 | (set acc | |
1562 | (add acc | |
1563 | (mul (ext DI src1) | |
1564 | (ext DI (trunc HI (sra src2 (const 16))))))) | |
8ee9a8b2 NC |
1565 | ((m32rx (unit u-mac)) |
1566 | (m32r2 (unit u-mac))) | |
e866a257 AC |
1567 | ) |
1568 | ||
1569 | (dni macwlo "macwlo" | |
1570 | ((MACH m32r) (PIPE S) (IDOC MAC)) | |
1571 | "macwlo $src1,$src2" | |
1572 | (+ OP1_3 OP2_7 src1 src2) | |
1573 | (set accum | |
1574 | (sra DI | |
1575 | (sll DI | |
1576 | (add DI | |
1577 | accum | |
1578 | (mul DI | |
1579 | (ext DI src1) | |
1580 | (ext DI (trunc HI src2)))) | |
1581 | (const 8)) | |
1582 | (const 8))) | |
1583 | ((m32r/d (unit u-mac))) | |
1584 | ) | |
1585 | ||
1586 | (dni macwlo-a "macwlo-a" | |
8ee9a8b2 | 1587 | ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC)) |
e866a257 AC |
1588 | "macwlo $src1,$src2,$acc" |
1589 | (+ OP1_3 src1 acc (f-op23 7) src2) | |
1590 | ; Note that this doesn't do the sign extension, which is correct. | |
1591 | (set acc | |
1592 | (add acc | |
1593 | (mul (ext DI src1) | |
1594 | (ext DI (trunc HI src2))))) | |
8ee9a8b2 NC |
1595 | ((m32rx (unit u-mac)) |
1596 | (m32r2 (unit u-mac))) | |
e866a257 AC |
1597 | ) |
1598 | ||
1599 | (dni mul "mul" | |
1600 | ((PIPE S) (IDOC ALU)) | |
1601 | "mul $dr,$sr" | |
1602 | (+ OP1_1 OP2_6 dr sr) | |
1603 | (set dr (mul dr sr)) | |
1604 | ((m32r/d (unit u-exec (cycles 4))) | |
8ee9a8b2 NC |
1605 | (m32rx (unit u-exec (cycles 4))) |
1606 | (m32r2 (unit u-exec (cycles 4)))) | |
e866a257 AC |
1607 | ) |
1608 | ||
1609 | (dni mulhi "mulhi" | |
1610 | ((MACH m32r) (PIPE S) (IDOC ACCUM)) | |
1611 | "mulhi $src1,$src2" | |
1612 | (+ OP1_3 OP2_0 src1 src2) | |
1613 | (set accum | |
1614 | (sra DI | |
1615 | (sll DI | |
1616 | (mul DI | |
1617 | (ext DI (and WI src1 (const #xffff0000))) | |
1618 | (ext DI (trunc HI (sra WI src2 (const 16))))) | |
1619 | (const 16)) | |
1620 | (const 16))) | |
1621 | ((m32r/d (unit u-mac))) | |
1622 | ) | |
1623 | ||
1624 | (dni mulhi-a "mulhi-a" | |
8ee9a8b2 | 1625 | ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) |
e866a257 AC |
1626 | "mulhi $src1,$src2,$acc" |
1627 | (+ OP1_3 (f-op23 0) src1 acc src2) | |
1628 | (set acc | |
1629 | (sra DI | |
1630 | (sll DI | |
1631 | (mul DI | |
1632 | (ext DI (and WI src1 (const #xffff0000))) | |
1633 | (ext DI (trunc HI (sra WI src2 (const 16))))) | |
1634 | (const 16)) | |
1635 | (const 16))) | |
8ee9a8b2 NC |
1636 | ((m32rx (unit u-mac)) |
1637 | (m32r2 (unit u-mac))) | |
e866a257 AC |
1638 | ) |
1639 | ||
1640 | (dni mullo "mullo" | |
1641 | ((MACH m32r) (PIPE S) (IDOC ACCUM)) | |
1642 | "mullo $src1,$src2" | |
1643 | (+ OP1_3 OP2_1 src1 src2) | |
1644 | (set accum | |
1645 | (sra DI | |
1646 | (sll DI | |
1647 | (mul DI | |
1648 | (ext DI (sll WI src1 (const 16))) | |
1649 | (ext DI (trunc HI src2))) | |
1650 | (const 16)) | |
1651 | (const 16))) | |
1652 | ((m32r/d (unit u-mac))) | |
1653 | ) | |
1654 | ||
1655 | (dni mullo-a "mullo-a" | |
8ee9a8b2 | 1656 | ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) |
e866a257 AC |
1657 | "mullo $src1,$src2,$acc" |
1658 | (+ OP1_3 src1 acc (f-op23 1) src2) | |
1659 | (set acc | |
1660 | (sra DI | |
1661 | (sll DI | |
1662 | (mul DI | |
1663 | (ext DI (sll WI src1 (const 16))) | |
1664 | (ext DI (trunc HI src2))) | |
1665 | (const 16)) | |
1666 | (const 16))) | |
8ee9a8b2 NC |
1667 | ((m32rx (unit u-mac)) |
1668 | (m32r2 (unit u-mac))) | |
e866a257 AC |
1669 | ) |
1670 | ||
1671 | (dni mulwhi "mulwhi" | |
1672 | ((MACH m32r) (PIPE S) (IDOC ACCUM)) | |
1673 | "mulwhi $src1,$src2" | |
1674 | (+ OP1_3 OP2_2 src1 src2) | |
1675 | (set accum | |
1676 | (sra DI | |
1677 | (sll DI | |
1678 | (mul DI | |
1679 | (ext DI src1) | |
1680 | (ext DI (trunc HI (sra WI src2 (const 16))))) | |
1681 | (const 8)) | |
1682 | (const 8))) | |
1683 | ((m32r/d (unit u-mac))) | |
1684 | ) | |
1685 | ||
1686 | (dni mulwhi-a "mulwhi-a" | |
8ee9a8b2 | 1687 | ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM)) |
e866a257 AC |
1688 | "mulwhi $src1,$src2,$acc" |
1689 | (+ OP1_3 src1 acc (f-op23 2) src2) | |
1690 | ; Note that this doesn't do the sign extension, which is correct. | |
1691 | (set acc | |
1692 | (mul (ext DI src1) | |
1693 | (ext DI (trunc HI (sra src2 (const 16)))))) | |
8ee9a8b2 NC |
1694 | ((m32rx (unit u-mac)) |
1695 | (m32r2 (unit u-mac))) | |
e866a257 AC |
1696 | ) |
1697 | ||
1698 | (dni mulwlo "mulwlo" | |
1699 | ((MACH m32r) (PIPE S) (IDOC ACCUM)) | |
1700 | "mulwlo $src1,$src2" | |
1701 | (+ OP1_3 OP2_3 src1 src2) | |
1702 | (set accum | |
1703 | (sra DI | |
1704 | (sll DI | |
1705 | (mul DI | |
1706 | (ext DI src1) | |
1707 | (ext DI (trunc HI src2))) | |
1708 | (const 8)) | |
1709 | (const 8))) | |
1710 | ((m32r/d (unit u-mac))) | |
1711 | ) | |
1712 | ||
1713 | (dni mulwlo-a "mulwlo-a" | |
8ee9a8b2 | 1714 | ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM)) |
e866a257 AC |
1715 | "mulwlo $src1,$src2,$acc" |
1716 | (+ OP1_3 src1 acc (f-op23 3) src2) | |
1717 | ; Note that this doesn't do the sign extension, which is correct. | |
1718 | (set acc | |
1719 | (mul (ext DI src1) | |
1720 | (ext DI (trunc HI src2)))) | |
8ee9a8b2 NC |
1721 | ((m32rx (unit u-mac)) |
1722 | (m32r2 (unit u-mac))) | |
e866a257 AC |
1723 | ) |
1724 | ||
1725 | (dni mv "mv" | |
1726 | ((PIPE OS) (IDOC ALU)) | |
1727 | "mv $dr,$sr" | |
1728 | (+ OP1_1 OP2_8 dr sr) | |
1729 | (set dr sr) | |
1730 | () | |
1731 | ) | |
1732 | ||
1733 | (dni mvfachi "mvfachi" | |
1734 | ((MACH m32r) (PIPE S) (IDOC ACCUM)) | |
1735 | "mvfachi $dr" | |
1736 | (+ OP1_5 OP2_15 (f-r2 0) dr) | |
1737 | (set dr (trunc WI (sra DI accum (const 32)))) | |
1738 | ((m32r/d (unit u-exec (cycles 2)))) | |
1739 | ) | |
1740 | ||
1741 | (dni mvfachi-a "mvfachi-a" | |
8ee9a8b2 | 1742 | ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) |
e866a257 AC |
1743 | "mvfachi $dr,$accs" |
1744 | (+ OP1_5 dr OP2_15 accs (f-op3 0)) | |
1745 | (set dr (trunc WI (sra DI accs (const 32)))) | |
8ee9a8b2 NC |
1746 | ((m32rx (unit u-exec (cycles 2))) |
1747 | (m32r2 (unit u-exec (cycles 2)))) | |
e866a257 AC |
1748 | ) |
1749 | ||
1750 | (dni mvfaclo "mvfaclo" | |
1751 | ((MACH m32r) (PIPE S) (IDOC ACCUM)) | |
1752 | "mvfaclo $dr" | |
1753 | (+ OP1_5 OP2_15 (f-r2 1) dr) | |
1754 | (set dr (trunc WI accum)) | |
1755 | ((m32r/d (unit u-exec (cycles 2)))) | |
1756 | ) | |
1757 | ||
1758 | (dni mvfaclo-a "mvfaclo-a" | |
8ee9a8b2 | 1759 | ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) |
e866a257 AC |
1760 | "mvfaclo $dr,$accs" |
1761 | (+ OP1_5 dr OP2_15 accs (f-op3 1)) | |
1762 | (set dr (trunc WI accs)) | |
8ee9a8b2 NC |
1763 | ((m32rx (unit u-exec (cycles 2))) |
1764 | (m32r2 (unit u-exec (cycles 2)))) | |
e866a257 AC |
1765 | ) |
1766 | ||
1767 | (dni mvfacmi "mvfacmi" | |
1768 | ((MACH m32r) (PIPE S) (IDOC ACCUM)) | |
1769 | "mvfacmi $dr" | |
1770 | (+ OP1_5 OP2_15 (f-r2 2) dr) | |
1771 | (set dr (trunc WI (sra DI accum (const 16)))) | |
1772 | ((m32r/d (unit u-exec (cycles 2)))) | |
1773 | ) | |
1774 | ||
1775 | (dni mvfacmi-a "mvfacmi-a" | |
8ee9a8b2 | 1776 | ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) |
e866a257 AC |
1777 | "mvfacmi $dr,$accs" |
1778 | (+ OP1_5 dr OP2_15 accs (f-op3 2)) | |
1779 | (set dr (trunc WI (sra DI accs (const 16)))) | |
8ee9a8b2 NC |
1780 | ((m32rx (unit u-exec (cycles 2))) |
1781 | (m32r2 (unit u-exec (cycles 2)))) | |
e866a257 AC |
1782 | ) |
1783 | ||
1784 | (dni mvfc "mvfc" | |
1785 | ((PIPE O) (IDOC MISC)) | |
1786 | "mvfc $dr,$scr" | |
1787 | (+ OP1_1 OP2_9 dr scr) | |
1788 | (set dr scr) | |
1789 | () | |
1790 | ) | |
1791 | ||
1792 | (dni mvtachi "mvtachi" | |
1793 | ((MACH m32r) (PIPE S) (IDOC ACCUM)) | |
1794 | "mvtachi $src1" | |
1795 | (+ OP1_5 OP2_7 (f-r2 0) src1) | |
1796 | (set accum | |
1797 | (or DI | |
1798 | (and DI accum (const DI #xffffffff)) | |
1799 | (sll DI (ext DI src1) (const 32)))) | |
1800 | ((m32r/d (unit u-exec (in sr src1)))) | |
1801 | ) | |
1802 | ||
1803 | (dni mvtachi-a "mvtachi-a" | |
8ee9a8b2 | 1804 | ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) |
e866a257 AC |
1805 | "mvtachi $src1,$accs" |
1806 | (+ OP1_5 src1 OP2_7 accs (f-op3 0)) | |
1807 | (set accs | |
1808 | (or DI | |
1809 | (and DI accs (const DI #xffffffff)) | |
1810 | (sll DI (ext DI src1) (const 32)))) | |
8ee9a8b2 NC |
1811 | ((m32rx (unit u-exec (in sr src1))) |
1812 | (m32r2 (unit u-exec (in sr src1)))) | |
e866a257 AC |
1813 | ) |
1814 | ||
1815 | (dni mvtaclo "mvtaclo" | |
1816 | ((MACH m32r) (PIPE S) (IDOC ACCUM)) | |
1817 | "mvtaclo $src1" | |
1818 | (+ OP1_5 OP2_7 (f-r2 1) src1) | |
1819 | (set accum | |
1820 | (or DI | |
1821 | (and DI accum (const DI #xffffffff00000000)) | |
1822 | (zext DI src1))) | |
1823 | ((m32r/d (unit u-exec (in sr src1)))) | |
1824 | ) | |
1825 | ||
1826 | (dni mvtaclo-a "mvtaclo-a" | |
8ee9a8b2 | 1827 | ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) |
e866a257 AC |
1828 | "mvtaclo $src1,$accs" |
1829 | (+ OP1_5 src1 OP2_7 accs (f-op3 1)) | |
1830 | (set accs | |
1831 | (or DI | |
1832 | (and DI accs (const DI #xffffffff00000000)) | |
1833 | (zext DI src1))) | |
8ee9a8b2 NC |
1834 | ((m32rx (unit u-exec (in sr src1))) |
1835 | (m32r2 (unit u-exec (in sr src1)))) | |
e866a257 AC |
1836 | ) |
1837 | ||
1838 | (dni mvtc "mvtc" | |
1839 | ((PIPE O) (IDOC MISC)) | |
1840 | "mvtc $sr,$dcr" | |
1841 | (+ OP1_1 OP2_10 dcr sr) | |
1842 | (set dcr sr) | |
1843 | () | |
1844 | ) | |
1845 | ||
1846 | (dni neg "neg" | |
1847 | ((PIPE OS) (IDOC ALU)) | |
1848 | "neg $dr,$sr" | |
1849 | (+ OP1_0 OP2_3 dr sr) | |
1850 | (set dr (neg sr)) | |
1851 | () | |
1852 | ) | |
1853 | ||
1854 | (dni nop "nop" | |
1855 | ((PIPE OS) (IDOC MISC)) | |
1856 | "nop" | |
1857 | (+ OP1_7 OP2_0 (f-r1 0) (f-r2 0)) | |
1858 | (c-code VOID "PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);\n") | |
1859 | ; FIXME: quick hack: parallel nops don't contribute to cycle count. | |
1860 | ; Other kinds of nops do however (which we currently ignore). | |
1861 | ((m32r/d (unit u-exec (cycles 0))) | |
8ee9a8b2 NC |
1862 | (m32rx (unit u-exec (cycles 0))) |
1863 | (m32r2 (unit u-exec (cycles 0)))) | |
e866a257 AC |
1864 | ) |
1865 | ||
1866 | (dni not "not" | |
1867 | ((PIPE OS) (IDOC ALU)) | |
1868 | "not $dr,$sr" | |
1869 | (+ OP1_0 OP2_11 dr sr) | |
1870 | (set dr (inv sr)) | |
1871 | () | |
1872 | ) | |
1873 | ||
1874 | (dni rac "rac" | |
1875 | ((MACH m32r) (PIPE S) (IDOC MAC)) | |
1876 | "rac" | |
1877 | (+ OP1_5 OP2_9 (f-r1 0) (f-r2 0)) | |
1878 | (sequence ((DI tmp1)) | |
1879 | (set tmp1 (sll DI accum (const 1))) | |
1880 | (set tmp1 (add DI tmp1 (const DI #x8000))) | |
1881 | (set accum | |
1882 | (cond DI | |
1883 | ((gt tmp1 (const DI #x00007fffffff0000)) | |
1884 | (const DI #x00007fffffff0000)) | |
1885 | ((lt tmp1 (const DI #xffff800000000000)) | |
1886 | (const DI #xffff800000000000)) | |
1887 | (else (and tmp1 (const DI #xffffffffffff0000))))) | |
1888 | ) | |
1889 | ((m32r/d (unit u-mac))) | |
1890 | ) | |
1891 | ||
1892 | (dni rac-dsi "rac-dsi" | |
8ee9a8b2 | 1893 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
e866a257 AC |
1894 | "rac $accd,$accs,$imm1" |
1895 | (+ OP1_5 accd (f-bits67 0) OP2_9 accs (f-bit14 0) imm1) | |
1896 | (sequence ((DI tmp1)) | |
1897 | (set tmp1 (sll accs imm1)) | |
1898 | (set tmp1 (add tmp1 (const DI #x8000))) | |
1899 | (set accd | |
1900 | (cond DI | |
1901 | ((gt tmp1 (const DI #x00007fffffff0000)) | |
1902 | (const DI #x00007fffffff0000)) | |
1903 | ((lt tmp1 (const DI #xffff800000000000)) | |
1904 | (const DI #xffff800000000000)) | |
1905 | (else (and tmp1 (const DI #xffffffffffff0000))))) | |
1906 | ) | |
8ee9a8b2 NC |
1907 | ((m32rx (unit u-mac)) |
1908 | (m32r2 (unit u-mac))) | |
e866a257 AC |
1909 | ) |
1910 | ||
1911 | (dnmi rac-d "rac-d" | |
8ee9a8b2 | 1912 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
e866a257 AC |
1913 | "rac $accd" |
1914 | (emit rac-dsi accd (f-accs 0) (f-imm1 0)) | |
1915 | ) | |
1916 | ||
1917 | (dnmi rac-ds "rac-ds" | |
8ee9a8b2 | 1918 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
e866a257 AC |
1919 | "rac $accd,$accs" |
1920 | (emit rac-dsi accd accs (f-imm1 0)) | |
1921 | ) | |
1922 | ||
1923 | ||
1924 | (dni rach "rach" | |
1925 | ((MACH m32r) (PIPE S) (IDOC MAC)) | |
1926 | "rach" | |
1927 | (+ OP1_5 OP2_8 (f-r1 0) (f-r2 0)) | |
1928 | (sequence ((DI tmp1)) | |
1929 | ; Lop off top 8 bits. | |
1930 | ; The sign bit we want to use is bit 55 so the 64 bit value | |
1931 | ; isn't properly signed which we deal with in the if's below. | |
1932 | (set tmp1 (and accum (const DI #xffffffffffffff))) | |
1933 | (if (andif (ge tmp1 (const DI #x003fff80000000)) | |
1934 | (le tmp1 (const DI #x7fffffffffffff))) | |
1935 | (set tmp1 (const DI #x003fff80000000)) | |
1936 | ; else part | |
1937 | (if (andif (ge tmp1 (const DI #x80000000000000)) | |
1938 | (le tmp1 (const DI #xffc00000000000))) | |
1939 | (set tmp1 (const DI #xffc00000000000)) | |
1940 | (set tmp1 (and (add accum (const DI #x40000000)) | |
1941 | (const DI #xffffffff80000000))))) | |
1942 | (set tmp1 (sll tmp1 (const 1))) | |
1943 | ; Sign extend top 8 bits. | |
1944 | (set accum | |
1945 | ; FIXME: 7? | |
1946 | (sra DI (sll DI tmp1 (const 7)) (const 7))) | |
1947 | ) | |
1948 | ((m32r/d (unit u-mac))) | |
1949 | ) | |
1950 | ||
1951 | (dni rach-dsi "rach-dsi" | |
8ee9a8b2 | 1952 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
e866a257 AC |
1953 | "rach $accd,$accs,$imm1" |
1954 | (+ OP1_5 accd (f-bits67 0) OP2_8 accs (f-bit14 0) imm1) | |
1955 | (sequence ((DI tmp1)) | |
1956 | (set tmp1 (sll accs imm1)) | |
1957 | (set tmp1 (add tmp1 (const DI #x80000000))) | |
1958 | (set accd | |
1959 | (cond DI | |
1960 | ((gt tmp1 (const DI #x00007fff00000000)) | |
1961 | (const DI #x00007fff00000000)) | |
1962 | ((lt tmp1 (const DI #xffff800000000000)) | |
1963 | (const DI #xffff800000000000)) | |
1964 | (else (and tmp1 (const DI #xffffffff00000000))))) | |
1965 | ) | |
8ee9a8b2 NC |
1966 | ((m32rx (unit u-mac)) |
1967 | (m32r2 (unit u-mac))) | |
e866a257 AC |
1968 | ) |
1969 | ||
1970 | (dnmi rach-d "rach-d" | |
8ee9a8b2 | 1971 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
e866a257 AC |
1972 | "rach $accd" |
1973 | (emit rach-dsi accd (f-accs 0) (f-imm1 0)) | |
1974 | ) | |
1975 | ||
1976 | (dnmi rach-ds "rach-ds" | |
8ee9a8b2 | 1977 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
e866a257 AC |
1978 | "rach $accd,$accs" |
1979 | (emit rach-dsi accd accs (f-imm1 0)) | |
1980 | ) | |
1981 | ||
1982 | (dni rte "rte" | |
1983 | (UNCOND-CTI (PIPE O) (IDOC BR)) | |
1984 | "rte" | |
1985 | (+ OP1_1 OP2_13 (f-r1 0) (f-r2 6)) | |
1986 | (sequence () | |
1987 | ; pc = bpc & -4 | |
1988 | (set pc (and (reg h-cr 6) (const -4))) | |
1989 | ; bpc = bbpc | |
1990 | (set (reg h-cr 6) (reg h-cr 14)) | |
1991 | ; psw = bpsw | |
1992 | (set (reg h-psw) (reg h-bpsw)) | |
1993 | ; bpsw = bbpsw | |
1994 | (set (reg h-bpsw) (reg h-bbpsw)) | |
1995 | ) | |
1996 | () | |
1997 | ) | |
1998 | ||
1999 | (dni seth "seth" | |
2000 | ((IDOC ALU)) | |
2001 | "seth $dr,$hash$hi16" | |
2002 | (+ OP1_13 OP2_12 dr (f-r2 0) hi16) | |
2003 | (set dr (sll WI hi16 (const 16))) | |
2004 | () | |
2005 | ) | |
2006 | ||
2007 | (define-pmacro (shift-op sym op2-r-op op2-3-op op2-i-op sem-op) | |
2008 | (begin | |
8ee9a8b2 | 2009 | (dni sym sym ((PIPE O_OS) (IDOC ALU)) |
e866a257 AC |
2010 | (.str sym " $dr,$sr") |
2011 | (+ OP1_1 op2-r-op dr sr) | |
2012 | (set dr (sem-op dr (and sr (const 31)))) | |
2013 | () | |
2014 | ) | |
2015 | (dni (.sym sym "3") sym ((IDOC ALU)) | |
2016 | (.str sym "3 $dr,$sr,$simm16") | |
2017 | (+ OP1_9 op2-3-op dr sr simm16) | |
2018 | (set dr (sem-op sr (and WI simm16 (const 31)))) | |
2019 | () | |
2020 | ) | |
8ee9a8b2 | 2021 | (dni (.sym sym "i") sym ((PIPE O_OS) (IDOC ALU)) |
e866a257 AC |
2022 | (.str sym "i $dr,$uimm5") |
2023 | (+ OP1_5 (f-shift-op2 op2-i-op) dr uimm5) | |
2024 | (set dr (sem-op dr uimm5)) | |
2025 | () | |
2026 | ) | |
2027 | ) | |
2028 | ) | |
2029 | (shift-op sll OP2_4 OP2_12 2 sll) | |
2030 | (shift-op sra OP2_2 OP2_10 1 sra) | |
2031 | (shift-op srl OP2_0 OP2_8 0 srl) | |
2032 | ||
2033 | (define-pmacro (store-op suffix op2-op mode) | |
2034 | (begin | |
2035 | (dni (.sym st suffix) (.str "st" suffix) | |
2036 | ((PIPE O) (IDOC MEM)) | |
2037 | (.str "st" suffix " $src1,@$src2") | |
2038 | (+ OP1_2 op2-op src1 src2) | |
2039 | (set mode (mem mode src2) src1) | |
2040 | ((m32r/d (unit u-store (cycles 1))) | |
8ee9a8b2 NC |
2041 | (m32rx (unit u-store (cycles 1))) |
2042 | (m32r2 (unit u-store (cycles 1)))) | |
e866a257 AC |
2043 | ) |
2044 | (dnmi (.sym st suffix "-2") (.str "st" suffix "-2") | |
2045 | (NO-DIS (PIPE O) (IDOC MEM)) | |
2046 | (.str "st" suffix " $src1,@($src2)") | |
2047 | (emit (.sym st suffix) src1 src2)) | |
2048 | (dni (.sym st suffix -d) (.str "st" suffix "-d") | |
2049 | ((IDOC MEM)) | |
2050 | (.str "st" suffix " $src1,@($slo16,$src2)") | |
2051 | (+ OP1_10 op2-op src1 src2 slo16) | |
2052 | (set mode (mem mode (add src2 slo16)) src1) | |
2053 | ((m32r/d (unit u-store (cycles 2))) | |
8ee9a8b2 NC |
2054 | (m32rx (unit u-store (cycles 2))) |
2055 | (m32r2 (unit u-store (cycles 2)))) | |
e866a257 AC |
2056 | ) |
2057 | (dnmi (.sym st suffix -d2) (.str "st" suffix "-d2") | |
2058 | (NO-DIS (IDOC MEM)) | |
2059 | (.str "st" suffix " $src1,@($src2,$slo16)") | |
2060 | (emit (.sym st suffix -d) src1 src2 slo16)) | |
2061 | ) | |
2062 | ) | |
2063 | (store-op "" OP2_4 WI) | |
2064 | (store-op b OP2_0 QI) | |
2065 | (store-op h OP2_2 HI) | |
2066 | ||
2067 | (dni st-plus "st+" | |
2068 | ((PIPE O) (IDOC MEM)) | |
2069 | "st $src1,@+$src2" | |
2070 | (+ OP1_2 OP2_6 src1 src2) | |
2071 | ; This has to be coded carefully to avoid an "earlyclobber" of src2. | |
2072 | (sequence ((WI new-src2)) | |
2073 | (set new-src2 (add WI src2 (const WI 4))) | |
2074 | (set (mem WI new-src2) src1) | |
2075 | (set src2 new-src2)) | |
2076 | ((m32r/d (unit u-store) | |
2077 | (unit u-exec (in dr src2) (out dr src2) (cycles 0))) | |
2078 | (m32rx (unit u-store) | |
2079 | (unit u-exec (in dr src2) (out dr src2) (cycles 0))) | |
8ee9a8b2 NC |
2080 | (m32r2 (unit u-store) |
2081 | (unit u-exec (in dr src2) (out dr src2) (cycles 0))) | |
2082 | ) | |
2083 | ) | |
2084 | ||
2085 | (dni sth-plus "sth+" | |
2086 | ((MACH m32rx,m32r2) (PIPE O) SPECIAL) | |
2087 | "sth $src1,@$src2+" | |
2088 | (+ OP1_2 OP2_3 src1 src2) | |
2089 | ; This has to be coded carefully to avoid an "earlyclobber" of src2. | |
2090 | (sequence ((HI new-src2)) | |
2091 | (set (mem HI new-src2) src1) | |
2092 | (set new-src2 (add src2 (const 2))) | |
2093 | (set src2 new-src2)) | |
2094 | ((m32rx (unit u-store) | |
2095 | (unit u-exec (in dr src2) (out dr src2) (cycles 0))) | |
2096 | (m32r2 (unit u-store) | |
2097 | (unit u-exec (in dr src2) (out dr src2) (cycles 0))) | |
2098 | ) | |
2099 | ) | |
2100 | ||
2101 | (dni stb-plus "stb+" | |
2102 | ((MACH m32rx,m32r2) (PIPE O) SPECIAL) | |
2103 | "stb $src1,@$src2+" | |
2104 | (+ OP1_2 OP2_1 src1 src2) | |
2105 | ; This has to be coded carefully to avoid an "earlyclobber" of src2. | |
2106 | (sequence ((QI new-src2)) | |
2107 | (set (mem QI new-src2) src1) | |
2108 | (set new-src2 (add src2 (const 1))) | |
2109 | (set src2 new-src2)) | |
2110 | ((m32rx (unit u-store) | |
2111 | (unit u-exec (in dr src2) (out dr src2) (cycles 0))) | |
2112 | (m32r2 (unit u-store) | |
2113 | (unit u-exec (in dr src2) (out dr src2) (cycles 0))) | |
e866a257 AC |
2114 | ) |
2115 | ) | |
2116 | ||
2117 | (dni st-minus "st-" | |
2118 | ((PIPE O) (IDOC MEM)) | |
2119 | "st $src1,@-$src2" | |
2120 | (+ OP1_2 OP2_7 src1 src2) | |
2121 | ; This is the original way. It doesn't work for parallel execution | |
2122 | ; because of the earlyclobber of src2. | |
2123 | ;(sequence () | |
2124 | ; (set src2 (sub src2 (const 4))) | |
2125 | ; (set (mem WI src2) src1)) | |
2126 | (sequence ((WI new-src2)) | |
2127 | (set new-src2 (sub src2 (const 4))) | |
2128 | (set (mem WI new-src2) src1) | |
2129 | (set src2 new-src2)) | |
2130 | ((m32r/d (unit u-store) | |
2131 | (unit u-exec (in dr src2) (out dr src2) (cycles 0))) | |
2132 | (m32rx (unit u-store) | |
2133 | (unit u-exec (in dr src2) (out dr src2) (cycles 0))) | |
8ee9a8b2 NC |
2134 | (m32r2 (unit u-store) |
2135 | (unit u-exec (in dr src2) (out dr src2) (cycles 0))) | |
e866a257 AC |
2136 | ) |
2137 | ) | |
2138 | ||
8ee9a8b2 | 2139 | (dnmi push "push" ((PIPE O) (IDOC MEM)) |
e866a257 AC |
2140 | "push $src1" |
2141 | (emit st-minus src1 (src2 15)) ; "st %0,@-sp" | |
2142 | ) | |
2143 | ||
2144 | (dni sub "sub" | |
2145 | ((PIPE OS) (IDOC ALU)) | |
2146 | "sub $dr,$sr" | |
2147 | (+ OP1_0 OP2_2 dr sr) | |
2148 | (set dr (sub dr sr)) | |
2149 | () | |
2150 | ) | |
2151 | ||
2152 | (dni subv "sub:rv" | |
2153 | ((PIPE OS) (IDOC ALU)) | |
2154 | "subv $dr,$sr" | |
2155 | (+ OP1_0 OP2_0 dr sr) | |
2156 | (parallel () | |
2157 | (set dr (sub dr sr)) | |
2158 | (set condbit (sub-oflag dr sr (const 0)))) | |
2159 | () | |
2160 | ) | |
2161 | ||
2162 | (dni subx "sub:rx" | |
2163 | ((PIPE OS) (IDOC ALU)) | |
2164 | "subx $dr,$sr" | |
2165 | (+ OP1_0 OP2_1 dr sr) | |
2166 | (parallel () | |
2167 | (set dr (subc dr sr condbit)) | |
2168 | (set condbit (sub-cflag dr sr condbit))) | |
2169 | () | |
2170 | ) | |
2171 | ||
2172 | (dni trap "trap" | |
2173 | (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC MISC)) | |
2174 | "trap $uimm4" | |
2175 | (+ OP1_1 OP2_15 (f-r1 0) uimm4) | |
2176 | (sequence () | |
2177 | ; bbpc = bpc | |
2178 | (set (reg h-cr 14) (reg h-cr 6)) | |
2179 | ; Set bpc to the return address. Actually it's not quite the | |
2180 | ; return address as RTE rounds the address down to a word | |
2181 | ; boundary. | |
2182 | (set (reg h-cr 6) (add pc (const 4))) | |
2183 | ; bbpsw = bpsw | |
2184 | (set (reg h-bbpsw) (reg h-bpsw)) | |
2185 | ; bpsw = psw | |
2186 | (set (reg h-bpsw) (reg h-psw)) | |
2187 | ; sm is unchanged, ie,c are set to zero. | |
2188 | (set (reg h-psw) (and (reg h-psw) (const #x80))) | |
2189 | ; m32r_trap handles operating vs user mode | |
2190 | (set WI pc (c-call WI "m32r_trap" pc uimm4)) | |
2191 | ) | |
2192 | () | |
2193 | ) | |
2194 | ||
2195 | (dni unlock "unlock" | |
2196 | ((PIPE O) (IDOC MISC)) | |
2197 | "unlock $src1,@$src2" | |
2198 | (+ OP1_2 OP2_5 src1 src2) | |
2199 | (sequence () | |
2200 | (if (reg h-lock) | |
2201 | (set (mem WI src2) src1)) | |
2202 | (set (reg h-lock) (const BI 0))) | |
2203 | ((m32r/d (unit u-load)) | |
8ee9a8b2 NC |
2204 | (m32rx (unit u-load)) |
2205 | (m32r2 (unit u-load))) | |
e866a257 AC |
2206 | ) |
2207 | ||
2208 | ; Saturate into byte. | |
2209 | (dni satb "satb" | |
8ee9a8b2 | 2210 | ((MACH m32rx,m32r2) (IDOC ALU)) |
e866a257 AC |
2211 | "satb $dr,$sr" |
2212 | (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0300)) | |
2213 | (set dr | |
2214 | ; FIXME: min/max would simplify this nicely of course. | |
2215 | (cond WI | |
2216 | ((ge sr (const 127)) (const 127)) | |
2217 | ((le sr (const -128)) (const -128)) | |
2218 | (else sr))) | |
2219 | () | |
2220 | ) | |
2221 | ||
2222 | ; Saturate into half word. | |
2223 | (dni sath "sath" | |
8ee9a8b2 | 2224 | ((MACH m32rx,m32r2) (IDOC ALU)) |
e866a257 AC |
2225 | "sath $dr,$sr" |
2226 | (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0200)) | |
2227 | (set dr | |
2228 | (cond WI | |
2229 | ((ge sr (const 32767)) (const 32767)) | |
2230 | ((le sr (const -32768)) (const -32768)) | |
2231 | (else sr))) | |
2232 | () | |
2233 | ) | |
2234 | ||
2235 | ; Saturate word. | |
2236 | (dni sat "sat" | |
8ee9a8b2 | 2237 | ((MACH m32rx,m32r2) SPECIAL (IDOC ALU)) |
e866a257 AC |
2238 | "sat $dr,$sr" |
2239 | (+ OP1_8 dr OP2_6 sr (f-uimm16 0)) | |
2240 | (set dr | |
2241 | (if WI condbit | |
2242 | (if WI (lt sr (const 0)) | |
2243 | (const #x7fffffff) | |
2244 | (const #x80000000)) | |
2245 | sr)) | |
2246 | () | |
2247 | ) | |
2248 | ||
2249 | ; Parallel compare byte zeros. | |
2250 | ; Set C bit in condition register if any byte in source register is zero. | |
2251 | (dni pcmpbz "pcmpbz" | |
8ee9a8b2 | 2252 | ((MACH m32rx,m32r2) (PIPE OS) SPECIAL (IDOC ALU)) |
e866a257 AC |
2253 | "pcmpbz $src2" |
2254 | (+ OP1_0 (f-r1 3) OP2_7 src2) | |
2255 | (set condbit | |
2256 | (cond BI | |
2257 | ((eq (and src2 (const #xff)) (const 0)) (const BI 1)) | |
2258 | ((eq (and src2 (const #xff00)) (const 0)) (const BI 1)) | |
2259 | ((eq (and src2 (const #xff0000)) (const 0)) (const BI 1)) | |
2260 | ((eq (and src2 (const #xff000000)) (const 0)) (const BI 1)) | |
2261 | (else (const BI 0)))) | |
8ee9a8b2 NC |
2262 | ((m32rx (unit u-cmp)) |
2263 | (m32r2 (unit u-cmp))) | |
e866a257 AC |
2264 | ) |
2265 | ||
2266 | ; Add accumulators | |
2267 | (dni sadd "sadd" | |
8ee9a8b2 | 2268 | ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) |
e866a257 AC |
2269 | "sadd" |
2270 | (+ OP1_5 (f-r1 0) OP2_14 (f-r2 4)) | |
2271 | (set (reg h-accums 0) | |
2272 | (add (sra (reg h-accums 1) (const 16)) | |
2273 | (reg h-accums 0))) | |
8ee9a8b2 NC |
2274 | ((m32rx (unit u-mac)) |
2275 | (m32r2 (unit u-mac))) | |
e866a257 AC |
2276 | ) |
2277 | ||
2278 | ; Multiply and add into accumulator 1 | |
2279 | (dni macwu1 "macwu1" | |
8ee9a8b2 | 2280 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
e866a257 AC |
2281 | "macwu1 $src1,$src2" |
2282 | (+ OP1_5 src1 OP2_11 src2) | |
2283 | (set (reg h-accums 1) | |
2284 | (sra DI | |
2285 | (sll DI | |
2286 | (add DI | |
2287 | (reg h-accums 1) | |
2288 | (mul DI | |
2289 | (ext DI src1) | |
2290 | (ext DI (and src2 (const #xffff))))) | |
2291 | (const 8)) | |
2292 | (const 8))) | |
8ee9a8b2 NC |
2293 | ((m32rx (unit u-mac)) |
2294 | (m32r2 (unit u-mac))) | |
e866a257 AC |
2295 | ) |
2296 | ||
2297 | ; Multiply and subtract from accumulator 0 | |
2298 | (dni msblo "msblo" | |
8ee9a8b2 | 2299 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
e866a257 AC |
2300 | "msblo $src1,$src2" |
2301 | (+ OP1_5 src1 OP2_13 src2) | |
2302 | (set accum | |
2303 | (sra DI | |
2304 | (sll DI | |
2305 | (sub accum | |
2306 | (sra DI | |
2307 | (sll DI | |
2308 | (mul DI | |
2309 | (ext DI (trunc HI src1)) | |
2310 | (ext DI (trunc HI src2))) | |
2311 | (const 32)) | |
2312 | (const 16))) | |
2313 | (const 8)) | |
2314 | (const 8))) | |
8ee9a8b2 NC |
2315 | ((m32rx (unit u-mac)) |
2316 | (m32r2 (unit u-mac))) | |
e866a257 AC |
2317 | ) |
2318 | ||
2319 | ; Multiply into accumulator 1 | |
2320 | (dni mulwu1 "mulwu1" | |
8ee9a8b2 | 2321 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
e866a257 AC |
2322 | "mulwu1 $src1,$src2" |
2323 | (+ OP1_5 src1 OP2_10 src2) | |
2324 | (set (reg h-accums 1) | |
2325 | (sra DI | |
2326 | (sll DI | |
2327 | (mul DI | |
2328 | (ext DI src1) | |
2329 | (ext DI (and src2 (const #xffff)))) | |
2330 | (const 16)) | |
2331 | (const 16))) | |
8ee9a8b2 NC |
2332 | ((m32rx (unit u-mac)) |
2333 | (m32r2 (unit u-mac))) | |
e866a257 AC |
2334 | ) |
2335 | ||
2336 | ; Multiply and add into accumulator 1 | |
2337 | (dni maclh1 "maclh1" | |
8ee9a8b2 | 2338 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
e866a257 AC |
2339 | "maclh1 $src1,$src2" |
2340 | (+ OP1_5 src1 OP2_12 src2) | |
2341 | (set (reg h-accums 1) | |
2342 | (sra DI | |
2343 | (sll DI | |
2344 | (add DI | |
2345 | (reg h-accums 1) | |
2346 | (sll DI | |
2347 | (ext DI | |
2348 | (mul SI | |
2349 | (ext SI (trunc HI src1)) | |
2350 | (sra SI src2 (const SI 16)))) | |
2351 | (const 16))) | |
2352 | (const 8)) | |
2353 | (const 8))) | |
8ee9a8b2 NC |
2354 | ((m32rx (unit u-mac)) |
2355 | (m32r2 (unit u-mac))) | |
e866a257 AC |
2356 | ) |
2357 | ||
2358 | ; skip instruction if C | |
2359 | (dni sc "sc" | |
8ee9a8b2 | 2360 | ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR)) |
e866a257 AC |
2361 | "sc" |
2362 | (+ OP1_7 (f-r1 4) OP2_0 (f-r2 1)) | |
2363 | (skip (zext INT condbit)) | |
2364 | () | |
2365 | ) | |
2366 | ||
2367 | ; skip instruction if not C | |
2368 | (dni snc "snc" | |
8ee9a8b2 | 2369 | ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR)) |
e866a257 AC |
2370 | "snc" |
2371 | (+ OP1_7 (f-r1 5) OP2_0 (f-r2 1)) | |
2372 | (skip (zext INT (not condbit))) | |
2373 | () | |
2374 | ) | |
8ee9a8b2 NC |
2375 | |
2376 | ; PSW &= ~((unsigned char) uimm8 | 0x000ff00) | |
2377 | (dni clrpsw "clrpsw" | |
2378 | ((PIPE O) SPECIAL_M32R) | |
2379 | "clrpsw $uimm8" | |
2380 | (+ OP1_7 (f-r1 2) uimm8) | |
2381 | (set USI (reg h-cr 0) | |
2382 | (and USI (reg h-cr 0) | |
2383 | (or USI (inv BI uimm8) (const #xff00)))) | |
2384 | () | |
2385 | ) | |
2386 | ||
2387 | ; PSW |= (unsigned char) uimm8 | |
2388 | (dni setpsw "setpsw" | |
2389 | ((PIPE O) SPECIAL_M32R) | |
2390 | "setpsw $uimm8" | |
2391 | (+ OP1_7 (f-r1 1) uimm8) | |
2392 | (set USI (reg h-cr 0) uimm8) | |
2393 | () | |
2394 | ) | |
2395 | ||
2396 | ; bset | |
2397 | (dni bset "bset" | |
2398 | (SPECIAL_M32R) | |
2399 | "bset $uimm3,@($slo16,$sr)" | |
2400 | (+ OP1_10 (f-bit4 0) uimm3 OP2_6 sr slo16) | |
2401 | (set QI (mem QI (add sr slo16)) | |
2402 | (or QI (mem QI (add sr slo16)) | |
2403 | (sll USI (const 1) (sub (const 7) uimm3)))) | |
2404 | () | |
2405 | ) | |
2406 | ||
2407 | ; bclr | |
2408 | (dni bclr "bclr" | |
2409 | (SPECIAL_M32R) | |
2410 | "bclr $uimm3,@($slo16,$sr)" | |
2411 | (+ OP1_10 (f-bit4 0) uimm3 OP2_7 sr slo16) | |
2412 | (set QI (mem QI (add sr slo16)) | |
2413 | (and QI (mem QI (add sr slo16)) | |
2414 | (inv QI (sll USI (const 1) (sub (const 7) uimm3))))) | |
2415 | () | |
2416 | ) | |
2417 | ||
2418 | ; btst | |
2419 | (dni btst "btst" | |
2420 | (SPECIAL_M32R (PIPE O)) | |
2421 | "btst $uimm3,$sr" | |
2422 | (+ OP1_0 (f-bit4 0) uimm3 OP2_15 sr) | |
2423 | (set condbit (and QI (srl USI sr (sub (const 7) uimm3)) (const 1))) | |
2424 | () | |
2425 | ) | |
2426 |