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1 | ; Hitachi SHcompact instruction set description. -*- Scheme -*- |
2 | ; | |
3 | ; Copyright 2000 Free Software Foundation, Inc. | |
4 | ; | |
5 | ; Contributed by Red Hat Inc; developed under contract from Hitachi | |
6 | ; Semiconductor (America) Inc. | |
7 | ; | |
8 | ; This file is part of the GNU Binutils. | |
9 | ; | |
10 | ; This program is free software; you can redistribute it and/or modify | |
11 | ; it under the terms of the GNU General Public License as published by | |
12 | ; the Free Software Foundation; either version 2 of the License, or | |
13 | ; (at your option) any later version. | |
14 | ; | |
15 | ; This program is distributed in the hope that it will be useful, | |
16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | ; GNU General Public License for more details. | |
19 | ; | |
20 | ; You should have received a copy of the GNU General Public License | |
21 | ; along with this program; if not, write to the Free Software | |
22 | ; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
23 | \f | |
24 | ; dshcf -- define-normal-sh-compact-field | |
25 | ||
26 | (define-pmacro (dshcf xname xcomment ignored xstart xlength) | |
27 | (dnf xname xcomment ((ISA compact)) xstart xlength)) | |
28 | ||
29 | ; dshcop -- define-normal-sh-compact-operand | |
30 | ||
31 | (define-pmacro (dshcop xname xcomment ignored xhardware xfield) | |
32 | (dnop xname xcomment ((ISA compact)) xhardware xfield)) | |
33 | ||
34 | \f | |
35 | ; SHcompact-specific attributes. | |
36 | ||
37 | (define-attr | |
38 | (for insn) | |
39 | (type boolean) | |
40 | (name ILLSLOT) | |
41 | (comment "instruction may not appear in a delay slot") | |
42 | ) | |
43 | ||
44 | (define-attr | |
45 | (for insn) | |
46 | (type boolean) | |
47 | (name FP-INSN) | |
48 | (comment "floating point instruction") | |
49 | ) | |
50 | ||
51 | (define-keyword | |
52 | (name frc-names) | |
53 | (attrs (ISA compact)) | |
54 | (print-name h-frc) | |
55 | (values (fr0 0) (fr1 1) (fr2 2) (fr3 3) (fr4 4) (fr5 5) | |
56 | (fr6 6) (fr7 7) (fr8 8) (fr9 9) (fr10 10) (fr11 11) | |
57 | (fr12 12) (fr13 13) (fr14 14) (fr15 15)) | |
58 | ) | |
59 | ||
60 | (define-keyword | |
61 | (name drc-names) | |
62 | (attrs (ISA compact)) | |
63 | (print-name h-drc) | |
64 | (values (dr0 0) (dr2 2) (dr4 4) (dr6 6) (dr8 8) (dr10 10) (dr12 12) (dr14 14)) | |
65 | ) | |
66 | ||
67 | (define-keyword | |
68 | (name xf-names) | |
69 | (attrs (ISA compact)) | |
70 | (print-name h-xf) | |
71 | (values (xf0 0) (xf1 1) (xf2 2) (xf3 3) (xf4 4) (xf5 5) | |
72 | (xf6 6) (xf7 7) (xf8 8) (xf9 9) (xf10 10) (xf11 11) | |
73 | (xf12 12) (xf13 13) (xf14 14) (xf15 15)) | |
74 | ) | |
75 | ||
76 | ; Hardware specific to the SHcompact mode. | |
77 | ||
78 | (define-pmacro (front) (mul 16 frbit)) | |
79 | (define-pmacro (back) (mul 16 (not frbit))) | |
80 | ||
81 | (define-hardware | |
82 | (name h-frc) | |
83 | (comment "Single precision floating point registers") | |
84 | (attrs VIRTUAL (ISA compact)) | |
85 | (indices extern-keyword frc-names) | |
86 | (type register SF (16)) | |
87 | (get (index) (reg h-fr (add (front) index))) | |
88 | (set (index newval) (set (reg h-fr (add (front) index)) newval)) | |
89 | ) | |
90 | ||
91 | (define-hardware | |
92 | (name h-drc) | |
93 | (comment "Double precision floating point registers") | |
94 | (attrs VIRTUAL (ISA compact)) | |
95 | (indices extern-keyword drc-names) | |
96 | (type register DF (8)) | |
97 | (get (index) (reg h-dr (add (front) index))) | |
98 | (set (index newval) (set (reg h-dr (add (front) index)) newval)) | |
99 | ) | |
100 | ||
101 | (define-hardware | |
102 | (name h-xf) | |
103 | (comment "Extended single precision floating point registers") | |
104 | (attrs VIRTUAL (ISA compact)) | |
105 | (indices extern-keyword xf-names) | |
106 | (type register SF (16)) | |
107 | (get (index) (reg h-fr (add (back) index))) | |
108 | (set (index newval) (set (reg h-fr (add (back) index)) newval)) | |
109 | ) | |
110 | ||
111 | (define-hardware | |
112 | (name h-xd) | |
113 | (comment "Extended double precision floating point registers") | |
114 | (attrs VIRTUAL (ISA compact)) | |
115 | (indices extern-keyword frc-names) | |
116 | (type register DF (8)) | |
117 | (get (index) (reg h-dr (add (back) index))) | |
118 | (set (index newval) (set (reg h-dr (add (back) index)) newval)) | |
119 | ) | |
120 | ||
121 | (define-hardware | |
122 | (name h-fvc) | |
123 | (comment "Single precision floating point vectors") | |
124 | (attrs VIRTUAL (ISA compact)) | |
125 | (indices keyword "" ((fv0 0) (fv4 4) (fv8 8) (fv12 12))) | |
126 | (type register SF (4)) | |
127 | (get (index) (reg h-fr (add (front) index))) | |
128 | (set (index newval) (set (reg h-fr (add (front) index)) newval)) | |
129 | ) | |
130 | ||
131 | (define-hardware | |
132 | (name h-fpccr) | |
133 | (comment "SHcompact floating point status/control register") | |
134 | (attrs VIRTUAL (ISA compact)) | |
135 | (type register SI) | |
136 | (get () (or (or (or (raw-reg h-fpscr) (sll SI prbit 19)) (sll SI szbit 20)) (sll SI frbit 21))) | |
137 | (set (newvalue) (sequence () | |
138 | (set (reg h-fpscr) newvalue) | |
139 | (set prbit (and (srl newvalue 19) 1)) | |
140 | (set szbit (and (srl newvalue 20) 1)) | |
141 | (set frbit (and (srl newvalue 21) 1)))) | |
142 | ) | |
143 | ||
144 | (define-hardware | |
145 | (name h-gbr) | |
146 | (comment "Global base register") | |
147 | (attrs VIRTUAL (ISA compact)) | |
148 | (type register SI) | |
149 | (get () (subword SI (raw-reg h-gr 16) 1)) | |
150 | (set (newval) (set (raw-reg h-gr 16) (ext DI newval))) | |
151 | ) | |
152 | ||
153 | (define-hardware | |
154 | (name h-pr) | |
155 | (comment "Procedure link register") | |
156 | (attrs VIRTUAL (ISA compact)) | |
157 | (type register SI) | |
158 | (get () (subword SI (raw-reg h-gr 18) 1)) | |
159 | (set (newval) (set (raw-reg h-gr 18) (ext DI newval))) | |
160 | ) | |
161 | ||
162 | (define-hardware | |
163 | (name h-macl) | |
164 | (comment "Multiple-accumulate low register") | |
165 | (attrs VIRTUAL (ISA compact)) | |
166 | (type register SI) | |
167 | (get () (subword SI (raw-reg h-gr 17) 1)) | |
168 | (set (newval) (set (raw-reg h-gr 17) (-join-si (subword SI (raw-reg h-gr 17) 0) newval))) | |
169 | ) | |
170 | ||
171 | (define-hardware | |
172 | (name h-mach) | |
173 | (comment "Multiply-accumulate high register") | |
174 | (attrs VIRTUAL (ISA compact)) | |
175 | (type register SI) | |
176 | (get () (subword SI (raw-reg h-gr 17) 0)) | |
177 | (set (newval) (set (raw-reg h-gr 17) (-join-si newval (subword SI (raw-reg h-gr 17) 1)))) | |
178 | ) | |
179 | ||
180 | (define-hardware | |
181 | (name h-tbit) | |
182 | (comment "Condition code flag") | |
183 | (attrs VIRTUAL (ISA compact)) | |
184 | (type register BI) | |
185 | (get () (and BI (raw-reg h-gr 19) 1)) | |
186 | (set (newval) (set (raw-reg h-gr 19) (or (and (raw-reg h-gr 19) (inv DI 1)) (zext DI newval)))) | |
187 | ) | |
188 | ||
189 | \f | |
190 | (dshcf f-op4 "Opcode (4 bits)" () 15 4) | |
191 | (dshcf f-op8 "Opcode (8 bits)" () 15 8) | |
192 | (dshcf f-op16 "Opcode (16 bits)" () 15 16) | |
193 | ||
194 | (dshcf f-sub4 "Sub opcode (4 bits)" () 3 4) | |
195 | (dshcf f-sub8 "Sub opcode (8 bits)" () 7 8) | |
196 | (dshcf f-sub10 "Sub opcode (10 bits)" () 9 10) | |
197 | ||
198 | (dshcf f-rn "Register selector n" () 11 4) | |
199 | (dshcf f-rm "Register selector m" () 7 4) | |
200 | ||
201 | (dshcf f-8-1 "One bit at bit 8" () 8 1) | |
202 | ||
203 | (df f-disp8 "Displacement (8 bits)" ((ISA compact) PCREL-ADDR) 7 8 INT | |
204 | ((value pc) (sra SI value 1)) | |
205 | ((value pc) (add SI (sll SI value 1) (add pc 4)))) | |
206 | ||
207 | (df f-disp12 "Displacement (12 bits)" ((ISA compact) PCREL-ADDR) 11 12 INT | |
208 | ((value pc) (sra SI value 1)) | |
209 | ((value pc) (add SI (sll SI value 1) (add pc 4)))) | |
210 | ||
211 | (dshcf f-imm8 "Immediate (8 bits)" () 7 8) | |
212 | (dshcf f-imm4 "Immediate (4 bits)" () 3 4) | |
213 | ||
214 | (df f-imm4x2 "Immediate (4 bits)" ((ISA compact)) 3 4 UINT | |
215 | ((value pc) (srl SI value 1)) | |
216 | ((value pc) (sll SI value 1))) | |
217 | ||
218 | (df f-imm4x4 "Immediate (4 bits)" ((ISA compact)) 3 4 UINT | |
219 | ((value pc) (srl SI value 2)) | |
220 | ((value pc) (sll SI value 2))) | |
221 | ||
222 | (df f-imm8x2 "Immediate (8 bits)" ((ISA compact)) 7 8 UINT | |
223 | ((value pc) (sra SI value 1)) | |
224 | ((value pc) (sll SI value 1))) | |
225 | ||
226 | (df f-imm8x4 "Immediate (8 bits)" ((ISA compact)) 7 8 UINT | |
227 | ((value pc) (sra SI value 2)) | |
228 | ((value pc) (sll SI value 2))) | |
229 | ||
230 | (df f-dn "Double selector n" ((ISA compact)) 11 3 UINT | |
231 | ((value pc) (srl SI value 1)) | |
232 | ((value pc) (sll SI value 1))) | |
233 | ||
234 | (df f-dm "Double selector m" ((ISA compact)) 7 3 UINT | |
235 | ((value pc) (srl SI value 1)) | |
236 | ((value pc) (sll SI value 1))) | |
237 | ||
238 | (df f-vn "Vector selector n" ((ISA compact)) 11 2 UINT | |
239 | ((value pc) (srl SI value 2)) | |
240 | ((value pc) (sll SI value 2))) | |
241 | ||
242 | (df f-vm "Vector selector m" ((ISA compact)) 9 2 UINT | |
243 | ((value pc) (srl SI value 2)) | |
244 | ((value pc) (sll SI value 2))) | |
245 | ||
246 | (df f-xn "Extended selector n" ((ISA compact)) 11 3 UINT | |
247 | ((value pc) (srl SI value 1)) | |
248 | ((value pc) (add SI (sll SI value 1) 1))) | |
249 | ||
250 | (df f-xm "Extended selector m" ((ISA compact)) 7 3 UINT | |
251 | ((value pc) (srl SI value 1)) | |
252 | ((value pc) (add SI (sll SI value 1) 1))) | |
253 | ||
254 | \f | |
255 | ; Operands. | |
256 | ||
257 | (dshcop rm "Left general purpose register" () h-grc f-rm) | |
258 | (dshcop rn "Right general purpose register" () h-grc f-rn) | |
259 | (dshcop r0 "Register 0" () h-grc 0) | |
260 | ||
261 | (dshcop frn "Single precision register" () h-frc f-rn) | |
262 | (dshcop frm "Single precision register" () h-frc f-rm) | |
263 | ||
264 | (dshcop fvn "Left floating point vector" () h-fvc f-vn) | |
265 | (dshcop fvm "Right floating point vector" () h-fvc f-vm) | |
266 | ||
267 | (dshcop drn "Left double precision register" () h-drc f-dn) | |
268 | (dshcop drm "Right double precision register" () h-drc f-dm) | |
269 | ||
270 | (dshcop imm4 "Immediate value (4 bits)" () h-sint f-imm4) | |
271 | (dshcop imm8 "Immediate value (8 bits)" () h-sint f-imm8) | |
272 | (dshcop uimm8 "Immediate value (8 bits unsigned)" () h-uint f-imm8) | |
273 | ||
274 | (dshcop imm4x2 "Immediate value (4 bits, 2x scale)" () h-uint f-imm4x2) | |
275 | (dshcop imm4x4 "Immediate value (4 bits, 4x scale)" () h-uint f-imm4x4) | |
276 | (dshcop imm8x2 "Immediate value (8 bits, 2x scale)" () h-uint f-imm8x2) | |
277 | (dshcop imm8x4 "Immediate value (8 bits, 4x scale)" () h-uint f-imm8x4) | |
278 | ||
279 | (dshcop disp8 "Displacement (8 bits)" () h-iaddr f-disp8) | |
280 | (dshcop disp12 "Displacement (12 bits)" () h-iaddr f-disp12) | |
281 | ||
282 | (dshcop rm64 "Register m (64 bits)" () h-gr f-rm) | |
283 | (dshcop rn64 "Register n (64 bits)" () h-gr f-rn) | |
284 | ||
285 | (dshcop gbr "Global base register" () h-gbr f-nil) | |
286 | (dshcop pr "Procedure link register" () h-pr f-nil) | |
287 | ||
288 | (dshcop fpscr "Floating point status/control register" () h-fpccr f-nil) | |
289 | ||
290 | (dshcop tbit "Condition code flag" () h-tbit f-nil) | |
291 | (dshcop sbit "Multiply-accumulate saturation flag" () h-sbit f-nil) | |
292 | (dshcop mbit "Divide-step M flag" () h-mbit f-nil) | |
293 | (dshcop qbit "Divide-step Q flag" () h-qbit f-nil) | |
294 | (dshcop fpul "Floating point ???" () h-fr 32) | |
295 | ||
296 | (dshcop frbit "Floating point register bank bit" () h-frbit f-nil) | |
297 | (dshcop szbit "Floating point transfer size bit" () h-szbit f-nil) | |
298 | (dshcop prbit "Floating point precision bit" () h-prbit f-nil) | |
299 | ||
300 | (dshcop macl "Multiply-accumulate low register" () h-macl f-nil) | |
301 | (dshcop mach "Multiply-accumulate high register" () h-mach f-nil) | |
302 | ||
303 | ||
304 | (define-operand (name fsdm) (comment "bar") | |
305 | (attrs (ISA compact)) (type h-frc) (index f-rm) (handlers (parse "fsd"))) | |
306 | ||
307 | (define-operand (name fsdn) (comment "bar") | |
308 | (attrs (ISA compact)) (type h-frc) (index f-rn)) | |
309 | \f | |
310 | ||
311 | ; Cover macro to dni to indicate these are all SHcompact instructions. | |
312 | ; dshmi: define-normal-sh-compact-insn | |
313 | ||
314 | (define-pmacro (dshci xname xcomment xattrs xsyntax xformat xsemantics) | |
315 | (define-insn | |
316 | (name (.sym xname -compact)) | |
317 | (comment xcomment) | |
318 | (.splice attrs (.unsplice xattrs) (ISA compact)) | |
319 | (syntax xsyntax) | |
320 | (format xformat) | |
321 | (semantics xsemantics))) | |
322 | ||
323 | (define-pmacro (dr operand) (reg h-dr (index-of operand))) | |
324 | (define-pmacro (xd x) (reg h-xd (and (index-of x) (inv QI 1)))) | |
325 | \f | |
326 | (dshci add "Add" | |
327 | () | |
328 | "add $rm, $rn" | |
329 | (+ (f-op4 3) rn rm (f-sub4 12)) | |
330 | (set rn (add rn rm))) | |
331 | ||
332 | (dshci addi "Add immediate" | |
333 | () | |
334 | "add #$imm8, $rn" | |
335 | (+ (f-op4 7) rn imm8) | |
336 | (set rn (add rn (ext SI (and QI imm8 255))))) | |
337 | ||
338 | (dshci addc "Add with carry" | |
339 | () | |
340 | "addc $rm, $rn" | |
341 | (+ (f-op4 3) rn rm (f-sub4 14)) | |
342 | (sequence ((BI flag)) | |
343 | (set flag (add-cflag rn rm tbit)) | |
344 | (set rn (addc rn rm tbit)) | |
345 | (set tbit flag))) | |
346 | ||
347 | (dshci addv "Add with overflow" | |
348 | () | |
349 | "addv $rm, $rn" | |
350 | (+ (f-op4 3) rn rm (f-sub4 15)) | |
351 | (sequence ((BI t)) | |
352 | (set t (add-oflag rn rm 0)) | |
353 | (set rn (add rn rm)) | |
354 | (set tbit t))) | |
355 | ||
356 | (dshci and "Bitwise AND" | |
357 | () | |
358 | "and $rm64, $rn64" | |
359 | (+ (f-op4 2) rn64 rm64 (f-sub4 9)) | |
360 | (set rn64 (and rm64 rn64))) | |
361 | ||
362 | (dshci andi "Bitwise AND immediate" | |
363 | () | |
364 | "and #$uimm8, r0" | |
365 | (+ (f-op8 #xc9) uimm8) | |
366 | (set r0 (and r0 (zext DI uimm8)))) | |
367 | ||
368 | (dshci andb "Bitwise AND memory byte" | |
369 | () | |
370 | "and.b #$imm8, @(r0, gbr)" | |
371 | (+ (f-op8 #xcd) imm8) | |
372 | (sequence ((DI addr) (UQI data)) | |
373 | (set addr (add r0 gbr)) | |
374 | (set data (and (mem UQI addr) imm8)) | |
375 | (set (mem UQI addr) data))) | |
376 | ||
377 | (dshci bf "Conditional branch" | |
378 | () | |
379 | "bf $disp8" | |
380 | (+ (f-op8 #x8b) disp8) | |
381 | (if (not tbit) | |
382 | (set pc disp8))) | |
383 | ||
384 | (dshci bfs "Conditional branch with delay slot" | |
385 | () | |
386 | "bf/s $disp8" | |
387 | (+ (f-op8 #x8f) disp8) | |
388 | (if (not tbit) | |
389 | (delay 1 (set pc disp8)))) | |
390 | ||
391 | (dshci bra "Branch" | |
392 | () | |
393 | "bra $disp12" | |
394 | (+ (f-op4 10) disp12) | |
395 | (delay 1 (set pc disp12))) | |
396 | ||
397 | (dshci braf "Branch far" | |
398 | () | |
399 | "braf $rn" | |
400 | (+ (f-op4 0) rn (f-sub8 35)) | |
401 | (delay 1 (set pc (add (ext DI rn) (add pc 4))))) | |
402 | ||
403 | (dshci brk "Breakpoint" | |
404 | () | |
405 | "brk" | |
406 | (+ (f-op16 59)) | |
407 | (c-call "sh64_break" pc)) | |
408 | ||
409 | (dshci bsr "Branch to subroutine" | |
410 | () | |
411 | "bsr $disp12" | |
412 | (+ (f-op4 11) disp12) | |
413 | (delay 1 (sequence () | |
414 | (set pr (add pc 4)) | |
415 | (set pc disp12)))) | |
416 | ||
417 | (dshci bsrf "Branch to far subroutine" | |
418 | () | |
419 | "bsrf $rn" | |
420 | (+ (f-op4 0) rn (f-sub8 3)) | |
421 | (delay 1 (sequence () | |
422 | (set pr (add pc 4)) | |
423 | (set pc (add (ext DI rn) (add pc 4)))))) | |
424 | ||
425 | (dshci bt "Conditional branch" | |
426 | () | |
427 | "bt $disp8" | |
428 | (+ (f-op8 #x89) disp8) | |
429 | (if tbit | |
430 | (set pc disp8))) | |
431 | ||
432 | (dshci bts "Conditional branch with delay slot" | |
433 | () | |
434 | "bt/s $disp8" | |
435 | (+ (f-op8 #x8d) disp8) | |
436 | (if tbit | |
437 | (delay 1 (set pc disp8)))) | |
438 | ||
439 | (dshci clrmac "Clear MACL and MACH" | |
440 | () | |
441 | "clrmac" | |
442 | (+ (f-op16 40)) | |
443 | (sequence () | |
444 | (set macl 0) | |
445 | (set mach 0))) | |
446 | ||
447 | (dshci clrs "Clear S-bit" | |
448 | () | |
449 | "clrs" | |
450 | (+ (f-op16 72)) | |
451 | (set sbit 0)) | |
452 | ||
453 | (dshci clrt "Clear T-bit" | |
454 | () | |
455 | "clrt" | |
456 | (+ (f-op16 8)) | |
457 | (set tbit 0)) | |
458 | ||
459 | (dshci cmpeq "Compare if equal" | |
460 | () | |
461 | "cmp/eq $rm, $rn" | |
462 | (+ (f-op4 3) rn rm (f-sub4 0)) | |
463 | (set tbit (eq rm rn))) | |
464 | ||
465 | (dshci cmpeqi "Compare if equal (immediate)" | |
466 | () | |
467 | "cmp/eq #$imm8, r0" | |
468 | (+ (f-op8 #x88) imm8) | |
469 | (set tbit (eq r0 (ext SI (and QI imm8 255))))) | |
470 | ||
471 | (dshci cmpge "Compare if greater than or equal" | |
472 | () | |
473 | "cmp/ge $rm, $rn" | |
474 | (+ (f-op4 3) rn rm (f-sub4 3)) | |
475 | (set tbit (ge rn rm))) | |
476 | ||
477 | (dshci cmpgt "Compare if greater than" | |
478 | () | |
479 | "cmp/gt $rm, $rn" | |
480 | (+ (f-op4 3) rn rm (f-sub4 7)) | |
481 | (set tbit (gt rn rm))) | |
482 | ||
483 | (dshci cmphi "Compare if greater than (unsigned)" | |
484 | () | |
485 | "cmp/hi $rm, $rn" | |
486 | (+ (f-op4 3) rn rm (f-sub4 6)) | |
487 | (set tbit (gtu rn rm))) | |
488 | ||
489 | (dshci cmphs "Compare if greater than or equal (unsigned)" | |
490 | () | |
491 | "cmp/hs $rm, $rn" | |
492 | (+ (f-op4 3) rn rm (f-sub4 2)) | |
493 | (set tbit (geu rn rm))) | |
494 | ||
495 | (dshci cmppl "Compare if greater than zero" | |
496 | () | |
497 | "cmp/pl $rn" | |
498 | (+ (f-op4 4) rn (f-sub8 21)) | |
499 | (set tbit (gt rn 0))) | |
500 | ||
501 | (dshci cmppz "Compare if greater than or equal zero" | |
502 | () | |
503 | "cmp/pz $rn" | |
504 | (+ (f-op4 4) rn (f-sub8 17)) | |
505 | (set tbit (ge rn 0))) | |
506 | ||
507 | (dshci cmpstr "Compare bytes" | |
508 | () | |
509 | "cmp/str $rm, $rn" | |
510 | (+ (f-op4 2) rn rm (f-sub4 12)) | |
511 | (sequence ((BI t) (SI temp)) | |
512 | (set temp (xor rm rn)) | |
513 | (set t (eq (and temp #xff000000) 0)) | |
514 | (set t (or (eq (and temp #xff0000) 0) t)) | |
515 | (set t (or (eq (and temp #xff00) 0) t)) | |
516 | (set t (or (eq (and temp #xff) 0) t)) | |
517 | (set tbit (if BI (gtu t 0) 1 0)))) | |
518 | ||
519 | (dshci div0s "Initialise divide-step state for signed division" | |
520 | () | |
521 | "div0s $rm, $rn" | |
522 | (+ (f-op4 2) rn rm (f-sub4 7)) | |
523 | (sequence () | |
524 | (set qbit (srl rn 31)) | |
525 | (set mbit (srl rm 31)) | |
526 | (set tbit (if BI (eq (srl rm 31) (srl rn 31)) 0 1)))) | |
527 | ||
528 | (dshci div0u "Initialise divide-step state for unsigned division" | |
529 | () | |
530 | "div0u" | |
531 | (+ (f-op16 25)) | |
532 | (sequence () | |
533 | (set tbit 0) | |
534 | (set qbit 0) | |
535 | (set mbit 0))) | |
536 | ||
537 | (dshci div1 "Divide step" | |
538 | () | |
539 | "div1 $rm, $rn" | |
540 | (+ (f-op4 3) rn rm (f-sub4 4)) | |
541 | (sequence ((BI oldq) (SI tmp0) (UQI tmp1)) | |
542 | (set oldq qbit) | |
543 | (set qbit (srl rn 31)) | |
544 | (set rn (or (sll rn 1) (zext SI tbit))) | |
545 | (if (not oldq) | |
546 | (if (not mbit) | |
547 | (sequence () | |
548 | (set tmp0 rn) | |
549 | (set rn (sub rn rm)) | |
550 | (set tmp1 (gtu rn tmp0)) | |
551 | (if (not qbit) | |
552 | (set qbit (if BI tmp1 1 0)) | |
553 | (set qbit (if BI (eq tmp1 0) 1 0)))) | |
554 | (sequence () | |
555 | (set tmp0 rn) | |
556 | (set rn (add rn rm)) | |
557 | (set tmp1 (ltu rn tmp0)) | |
558 | (if (not qbit) | |
559 | (set qbit (if BI (eq tmp1 0) 1 0)) | |
560 | (set qbit (if BI tmp1 1 0))))) | |
561 | (if (not mbit) | |
562 | (sequence () | |
563 | (set tmp0 rn) | |
564 | (set rn (add rm rn)) | |
565 | (set tmp1 (ltu rn tmp0)) | |
566 | (if (not qbit) | |
567 | (set qbit (if BI tmp1 1 0)) | |
568 | (set qbit (if BI (eq tmp1 0) 1 0)))) | |
569 | (sequence () | |
570 | (set tmp0 rn) | |
571 | (set rn (sub rn rm)) | |
572 | (set tmp1 (gtu rn tmp0)) | |
573 | (if (not qbit) | |
574 | (set qbit (if BI (eq tmp1 0) 1 0)) | |
575 | (set qbit (if BI tmp1 1 0)))))) | |
576 | (set tbit (if BI (eq qbit mbit) 1 0)))) | |
577 | ||
578 | (dshci dmulsl "Multiply long (signed)" | |
579 | () | |
580 | "dmuls.l $rm, $rn" | |
581 | (+ (f-op4 3) rn rm (f-sub4 13)) | |
582 | (sequence ((DI result)) | |
583 | (set result (mul (ext DI rm) (ext DI rn))) | |
584 | (set mach (subword SI result 0)) | |
585 | (set macl (subword SI result 1)))) | |
586 | ||
587 | (dshci dmulul "Multiply long (unsigned)" | |
588 | () | |
589 | "dmulu.l $rm, $rn" | |
590 | (+ (f-op4 3) rn rm (f-sub4 5)) | |
591 | (sequence ((DI result)) | |
592 | (set result (mul (zext DI rm) (zext DI rn))) | |
593 | (set mach (subword SI result 0)) | |
594 | (set macl (subword SI result 1)))) | |
595 | ||
596 | (dshci dt "Decrement and set" | |
597 | () | |
598 | "dt $rn" | |
599 | (+ (f-op4 4) rn (f-sub8 16)) | |
600 | (sequence () | |
601 | (set rn (sub rn 1)) | |
602 | (set tbit (eq rn 0)))) | |
603 | ||
604 | (dshci extsb "Sign extend byte" | |
605 | () | |
606 | "exts.b $rm, $rn" | |
607 | (+ (f-op4 6) rn rm (f-sub4 14)) | |
608 | (set rn (ext SI (subword QI rm 3)))) | |
609 | ||
610 | (dshci extsw "Sign extend word" | |
611 | () | |
612 | "exts.w $rm, $rn" | |
613 | (+ (f-op4 6) rn rm (f-sub4 15)) | |
614 | (set rn (ext SI (subword HI rm 1)))) | |
615 | ||
616 | (dshci extub "Zero extend byte" | |
617 | () | |
618 | "extu.b $rm, $rn" | |
619 | (+ (f-op4 6) rn rm (f-sub4 12)) | |
620 | (set rn (zext SI (subword QI rm 3)))) | |
621 | ||
622 | (dshci extuw "Zero etxend word" | |
623 | () | |
624 | "extu.w $rm, $rn" | |
625 | (+ (f-op4 6) rn rm (f-sub4 13)) | |
626 | (set rn (zext SI (subword HI rm 1)))) | |
627 | ||
628 | (dshci fabs "Floating point absolute" | |
629 | (FP-INSN) | |
630 | "fabs $fsdn" | |
631 | (+ (f-op4 15) fsdn (f-sub8 #x5d)) | |
632 | (if prbit | |
633 | (set (dr fsdn) (c-call DF "sh64_fabsd" (dr fsdn))) | |
634 | (set fsdn (c-call SF "sh64_fabss" fsdn)))) | |
635 | ||
636 | (dshci fadd "Floating point add" | |
637 | (FP-INSN) | |
638 | "fadd $fsdm, $fsdn" | |
639 | (+ (f-op4 15) fsdn fsdm (f-sub4 0)) | |
640 | (if prbit | |
641 | (set (dr fsdn) (c-call DF "sh64_faddd" (dr fsdm) (dr fsdn))) | |
642 | (set fsdn (c-call SF "sh64_fadds" fsdm fsdn)))) | |
643 | ||
644 | (dshci fcmpeq "Floating point compare equal" | |
645 | (FP-INSN) | |
646 | "fcmp/eq $fsdm, $fsdn" | |
647 | (+ (f-op4 15) fsdn fsdm (f-sub4 4)) | |
648 | (if prbit | |
649 | (set tbit (c-call BI "sh64_fcmpeqd" (dr fsdm) (dr fsdn))) | |
650 | (set tbit (c-call BI "sh64_fcmpeqs" fsdm fsdn)))) | |
651 | ||
652 | (dshci fcmpgt "Floating point compare greater than" | |
653 | (FP-INSN) | |
654 | "fcmp/gt $fsdm, $fsdn" | |
655 | (+ (f-op4 15) fsdn fsdm (f-sub4 5)) | |
656 | (if prbit | |
657 | (set tbit (c-call BI "sh64_fcmpgtd" (dr fsdn) (dr fsdm))) | |
658 | (set tbit (c-call BI "sh64_fcmpgts" fsdn fsdm)))) | |
659 | ||
660 | (dshci fcnvds "Floating point convert (double to single)" | |
661 | (FP-INSN) | |
662 | "fcnvds $drn, fpul" | |
663 | (+ (f-op4 15) drn (f-8-1 10) (f-sub8 #xbd)) | |
664 | (set fpul (c-call SF "sh64_fcnvds" drn))) | |
665 | ||
666 | (dshci fcnvsd "Floating point convert (single to double)" | |
667 | (FP-INSN) | |
668 | "fcnvsd fpul, $drn" | |
669 | (+ (f-op4 15) drn (f-8-1 0) (f-sub8 #xad)) | |
670 | (set drn (c-call DF "sh64_fcnvsd" fpul))) | |
671 | ||
672 | (dshci fdiv "Floating point divide" | |
673 | (FP-INSN) | |
674 | "fdiv $fsdm, $fsdn" | |
675 | (+ (f-op4 15) fsdn fsdm (f-sub4 3)) | |
676 | (if prbit | |
677 | (set (dr fsdn) (c-call DF "sh64_fdivd" (dr fsdn) (dr fsdm))) | |
678 | (set fsdn (c-call SF "sh64_fdivs" fsdn fsdm)))) | |
679 | ||
680 | (dshci fipr "Floating point inner product" | |
681 | (FP-INSN) | |
682 | "fipr $fvm, $fvn" | |
683 | (+ (f-op4 15) fvn fvm (f-sub8 #xed)) | |
684 | (sequence ((QI m) (QI n) (SF res)) | |
685 | (set m (index-of fvm)) | |
686 | (set n (index-of fvn)) | |
687 | (set res (c-call SF "sh64_fmuls" fvm fvn)) | |
688 | (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-frc (add m 1)) (reg h-frc (add n 1))))) | |
689 | (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-frc (add m 2)) (reg h-frc (add n 2))))) | |
690 | (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-frc (add m 3)) (reg h-frc (add n 3))))) | |
691 | (set (reg h-frc (add n 3)) res))) | |
692 | ||
693 | (dshci flds "Floating point load status register" | |
694 | (FP-INSN) | |
695 | "flds $frn" | |
696 | (+ (f-op4 15) frn (f-sub8 #x1d)) | |
697 | (set fpul frn)) | |
698 | ||
699 | (dshci fldi0 "Floating point load immediate 0.0" | |
700 | (FP-INSN) | |
701 | "fldi0 $frn" | |
702 | (+ (f-op4 15) frn (f-sub8 #x8d)) | |
703 | (set frn (c-call SF "sh64_fldi0"))) | |
704 | ||
705 | (dshci fldi1 "Floating point load immediate 1.0" | |
706 | (FP-INSN) | |
707 | "fldi1 $frn" | |
708 | (+ (f-op4 15) frn (f-sub8 #x9d)) | |
709 | (set frn (c-call SF "sh64_fldi1"))) | |
710 | ||
711 | (dshci float "Floating point integer conversion" | |
712 | (FP-INSN) | |
713 | "float fpul, $fsdn" | |
714 | (+ (f-op4 15) fsdn (f-sub8 #x2d)) | |
715 | (if prbit | |
716 | (set (dr fsdn) (c-call DF "sh64_floatld" fpul)) | |
717 | (set fsdn (c-call SF "sh64_floatls" fpul)))) | |
718 | ||
719 | (dshci fmac "Floating point multiply and accumulate" | |
720 | (FP-INSN) | |
721 | "fmac fr0, $frm, $frn" | |
722 | (+ (f-op4 15) frn frm (f-sub4 14)) | |
723 | (set frn (c-call SF "sh64_fmacs" (reg h-frc 0) frm frn))) | |
724 | ||
725 | (define-pmacro (even x) (eq (and x 1) 0)) | |
726 | (define-pmacro (odd x) (eq (and x 1) 1)) | |
727 | (define-pmacro (extd x) (odd (index-of x))) | |
728 | ||
729 | (dshci fmov1 "Floating point move (register to register)" | |
730 | (FP-INSN) | |
731 | "fmov $frm, $frn" | |
732 | (+ (f-op4 15) frn frm (f-sub4 12)) | |
733 | (if (not szbit) | |
734 | ; single precision operation | |
735 | (set frn frm) | |
736 | ; double or extended operation | |
737 | (if (extd frm) | |
738 | (if (extd frn) | |
739 | (set (xd frn) (xd frm)) | |
740 | (set (dr frn) (xd frm))) | |
741 | (if (extd frn) | |
742 | (set (xd frn) (dr frm)) | |
743 | (set (dr frn) (dr frm)))))) | |
744 | ||
745 | (dshci fmov2 "Floating point load" | |
746 | (FP-INSN) | |
747 | "fmov @$rm, $frn" | |
748 | (+ (f-op4 15) frn rm (f-sub4 8)) | |
749 | (if (not szbit) | |
750 | ; single precision operation | |
751 | (set frn (mem SF rm)) | |
752 | ; double or extended operation | |
753 | (if (extd frn) | |
754 | (set (xd frn) (mem DF rm)) | |
755 | (set (dr frn) (mem DF rm))))) | |
756 | ||
757 | (dshci fmov3 "Floating point load (post-increment)" | |
758 | (FP-INSN) | |
759 | "fmov @${rm}+, frn" | |
760 | (+ (f-op4 15) frn rm (f-sub4 9)) | |
761 | (if (not szbit) | |
762 | ; single precision operation | |
763 | (sequence () | |
764 | (set frn (mem SF rm)) | |
765 | (set rm (add rm 4))) | |
766 | ; double or extended operation | |
767 | (sequence () | |
768 | (if (extd frn) | |
769 | (set (xd frn) (mem DF rm)) | |
770 | (set (dr frn) (mem DF rm))) | |
771 | (set rm (add rm 8))))) | |
772 | ||
773 | (dshci fmov4 "Floating point load (register/register indirect)" | |
774 | (FP-INSN) | |
775 | "fmov @(r0, $rm), $frn" | |
776 | (+ (f-op4 15) frn rm (f-sub4 6)) | |
777 | (if (not szbit) | |
778 | ; single precision operation | |
779 | (set frn (mem SF (add r0 rm))) | |
780 | ; double or extended operation | |
781 | (if (extd frn) | |
782 | (set (xd frn) (mem DF (add r0 rm))) | |
783 | (set (dr frn) (mem DF (add r0 rm)))))) | |
784 | ||
785 | (dshci fmov5 "Floating point store" | |
786 | (FP-INSN) | |
787 | "fmov $frm, @$rn" | |
788 | (+ (f-op4 15) rn frm (f-sub4 10)) | |
789 | (if (not szbit) | |
790 | ; single precision operation | |
791 | (set (mem SF rn) frm) | |
792 | ; double or extended operation | |
793 | (if (extd frm) | |
794 | (set (mem DF rn) (xd frm)) | |
795 | (set (mem DF rn) (dr frm))))) | |
796 | ||
797 | (dshci fmov6 "Floating point store (pre-decrement)" | |
798 | (FP-INSN) | |
799 | "fmov $frm, @-$rn" | |
800 | (+ (f-op4 15) rn frm (f-sub4 11)) | |
801 | (if (not szbit) | |
802 | ; single precision operation | |
803 | (sequence () | |
804 | (set rn (sub rn 4)) | |
805 | (set (mem SF rn) frm)) | |
806 | ; double or extended operation | |
807 | (sequence () | |
808 | (set rn (sub rn 8)) | |
809 | (if (extd frm) | |
810 | (set (mem DF rn) (xd frm)) | |
811 | (set (mem DF rn) (dr frm)))))) | |
812 | ||
813 | (dshci fmov7 "Floating point store (register/register indirect)" | |
814 | (FP-INSN) | |
815 | "fmov $frm, @(r0, $rn)" | |
816 | (+ (f-op4 15) rn frm (f-sub4 7)) | |
817 | (if (not szbit) | |
818 | ; single precision operation | |
819 | (set (mem SF (add r0 rn)) frm) | |
820 | ; double or extended operation | |
821 | (if (extd frm) | |
822 | (set (mem DF (add r0 rn)) (xd frm)) | |
823 | (set (mem DF (add r0 rn)) (dr frm))))) | |
824 | ||
825 | (dshci fmul "Floating point multiply" | |
826 | (FP-INSN) | |
827 | "fmul $fsdm, $fsdn" | |
828 | (+ (f-op4 15) fsdn fsdm (f-sub4 2)) | |
829 | (if prbit | |
830 | (set (dr fsdn) (c-call DF "sh64_fmuld" (dr fsdm) (dr fsdn))) | |
831 | (set fsdn (c-call SF "sh64_fmuls" fsdm fsdn)))) | |
832 | ||
833 | (dshci fneg "Floating point negate" | |
834 | (FP-INSN) | |
835 | "fneg $fsdn" | |
836 | (+ (f-op4 15) fsdn (f-sub8 #x4d)) | |
837 | (if prbit | |
838 | (set (dr fsdn) (c-call DF "sh64_fnegd" (dr fsdn))) | |
839 | (set fsdn (c-call SF "sh64_fnegs" fsdn)))) | |
840 | ||
841 | (dshci frchg "Toggle floating point register banks" | |
842 | (FP-INSN) | |
843 | "frchg" | |
844 | (+ (f-op16 #xfbfd)) | |
845 | (set frbit (not frbit))) | |
846 | ||
847 | (dshci fschg "Set size of floating point transfers" | |
848 | (FP-INSN) | |
849 | "fschg" | |
850 | (+ (f-op16 #xf3fd)) | |
851 | (set szbit (not szbit))) | |
852 | ||
853 | (dshci fsqrt "Floating point square root" | |
854 | (FP-INSN) | |
855 | "fsqrt $fsdn" | |
856 | (+ (f-op4 15) fsdn (f-sub8 #x6d)) | |
857 | (if prbit | |
858 | (set (dr fsdn) (c-call DF "sh64_fsqrtd" (dr fsdn))) | |
859 | (set fsdn (c-call SF "sh64_fsqrts" fsdn)))) | |
860 | ||
861 | (dshci fsts "Floating point store status register" | |
862 | (FP-INSN) | |
863 | "fsts fpul, $frn" | |
864 | (+ (f-op4 15) frn (f-sub8 13)) | |
865 | (set frn fpul)) | |
866 | ||
867 | (dshci fsub "Floating point subtract" | |
868 | (FP-INSN) | |
869 | "fsub $fsdm, $fsdn" | |
870 | (+ (f-op4 15) fsdn fsdm (f-sub4 1)) | |
871 | (if prbit | |
872 | (set (dr fsdn) (c-call DF "sh64_fsubd" (dr fsdn) (dr fsdm))) | |
873 | (set fsdn (c-call SF "sh64_fsubs" fsdn fsdm)))) | |
874 | ||
875 | (dshci ftrc "Floating point truncate" | |
876 | (FP-INSN) | |
877 | "ftrc $fsdn, fpul" | |
878 | (+ (f-op4 15) fsdn (f-sub8 #x3d)) | |
879 | (set fpul (if SF prbit | |
880 | (c-call SF "sh64_ftrcdl" (dr fsdn)) | |
881 | (c-call SF "sh64_ftrcsl" fsdn)))) | |
882 | ||
883 | (dshci ftrv "Floating point transform vector" | |
884 | (FP-INSN) | |
885 | "ftrv xmtrx, $fvn" | |
886 | (+ (f-op4 15) fvn (f-sub10 #x1fd)) | |
887 | (sequence ((QI n) (SF res)) | |
888 | (set n (index-of fvn)) | |
889 | (set res (c-call SF "sh64_fmuls" (reg h-xf 0) (reg h-frc n))) | |
890 | (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 4) (reg h-frc (add n 1))))) | |
891 | (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 8) (reg h-frc (add n 2))))) | |
892 | (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 12) (reg h-frc (add n 3))))) | |
893 | (set (reg h-frc n) res) | |
894 | (set res (c-call SF "sh64_fmuls" (reg h-xf 1) (reg h-frc n))) | |
895 | (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 5) (reg h-frc (add n 1))))) | |
896 | (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 9) (reg h-frc (add n 2))))) | |
897 | (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 13) (reg h-frc (add n 3))))) | |
898 | (set (reg h-frc (add n 1)) res) | |
899 | (set res (c-call SF "sh64_fmuls" (reg h-xf 2) (reg h-frc n))) | |
900 | (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 6) (reg h-frc (add n 1))))) | |
901 | (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 10) (reg h-frc (add n 2))))) | |
902 | (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 14) (reg h-frc (add n 3))))) | |
903 | (set (reg h-frc (add n 2)) res) | |
904 | (set res (c-call SF "sh64_fmuls" (reg h-xf 3) (reg h-frc n))) | |
905 | (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 7) (reg h-frc (add n 1))))) | |
906 | (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 11) (reg h-frc (add n 2))))) | |
907 | (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 15) (reg h-frc (add n 3))))) | |
908 | (set (reg h-frc (add n 3)) res))) | |
909 | ||
910 | (dshci jmp "Jump" | |
911 | () | |
912 | "jmp @$rn" | |
913 | (+ (f-op4 4) rn (f-sub8 43)) | |
914 | (delay 1 (set pc rn))) | |
915 | ||
916 | (dshci jsr "Jump to subroutine" | |
917 | () | |
918 | "jsr @$rn" | |
919 | (+ (f-op4 4) rn (f-sub8 11)) | |
920 | (delay 1 (sequence () | |
921 | (set pr (add pc 4)) | |
922 | (set pc rn)))) | |
923 | ||
924 | (dshci ldc "Load control register (GBR)" | |
925 | () | |
926 | "ldc $rn, gbr" | |
927 | (+ (f-op4 4) rn (f-sub8 30)) | |
928 | (set gbr rn)) | |
929 | ||
930 | (dshci ldcl "Load control register (GBR)" | |
931 | () | |
932 | "ldc.l @${rn}+, gbr" | |
933 | (+ (f-op4 4) rn (f-sub8 39)) | |
934 | (sequence () | |
935 | (set gbr (mem SI rn)) | |
936 | (set rn (add rn 4)))) | |
937 | ||
938 | (dshci lds-fpscr "Load status register (FPSCR)" | |
939 | () | |
940 | "lds $rn, fpscr" | |
941 | (+ (f-op4 4) rn (f-sub8 106)) | |
942 | (set fpscr rn)) | |
943 | ||
944 | (dshci ldsl-fpscr "Load status register (FPSCR)" | |
945 | () | |
946 | "lds.l @${rn}+, fpscr" | |
947 | (+ (f-op4 4) rn (f-sub8 102)) | |
948 | (sequence () | |
949 | (set fpscr (mem SI rn)) | |
950 | (set rn (add rn 4)))) | |
951 | ||
952 | (dshci lds-fpul "Load status register (FPUL)" | |
953 | () | |
954 | "lds $rn, fpul" | |
955 | (+ (f-op4 4) rn (f-sub8 90)) | |
956 | ; Use subword to convert rn's mode. | |
957 | (set fpul (subword SF rn 0))) | |
958 | ||
959 | (dshci ldsl-fpul "Load status register (FPUL)" | |
960 | () | |
961 | "lds.l @${rn}+, fpul" | |
962 | (+ (f-op4 4) rn (f-sub8 86)) | |
963 | (sequence () | |
964 | (set fpul (mem SF rn)) | |
965 | (set rn (add rn 4)))) | |
966 | ||
967 | (dshci lds-mach "Load status register (MACH)" | |
968 | () | |
969 | "lds $rn, mach" | |
970 | (+ (f-op4 4) rn (f-sub8 10)) | |
971 | (set mach rn)) | |
972 | ||
973 | (dshci ldsl-mach "Load status register (MACH), post-increment" | |
974 | () | |
975 | "lds.l @${rn}+, mach" | |
976 | (+ (f-op4 4) rn (f-sub8 6)) | |
977 | (sequence () | |
978 | (set mach (mem SI rn)) | |
979 | (set rn (add rn 4)))) | |
980 | ||
981 | (dshci lds-macl "Load status register (MACL)" | |
982 | () | |
983 | "lds $rn, macl" | |
984 | (+ (f-op4 4) rn (f-sub8 26)) | |
985 | (set macl rn)) | |
986 | ||
987 | (dshci ldsl-macl "Load status register (MACL), post-increment" | |
988 | () | |
989 | "lds.l @${rn}+, macl" | |
990 | (+ (f-op4 4) rn (f-sub8 22)) | |
991 | (sequence () | |
992 | (set macl (mem SI rn)) | |
993 | (set rn (add rn 4)))) | |
994 | ||
995 | (dshci lds-pr "Load status register (PR)" | |
996 | () | |
997 | "lds $rn, pr" | |
998 | (+ (f-op4 4) rn (f-sub8 42)) | |
999 | (set pr rn)) | |
1000 | ||
1001 | (dshci ldsl-pr "Load status register (PR), post-increment" | |
1002 | () | |
1003 | "lds.l @${rn}+, pr" | |
1004 | (+ (f-op4 4) rn (f-sub8 38)) | |
1005 | (sequence () | |
1006 | (set pr (mem SI rn)) | |
1007 | (set rn (add rn 4)))) | |
1008 | ||
1009 | (dshci macl "Multiply and accumulate (long)" | |
1010 | () | |
1011 | "mac.l @${rm}+, @${rn}+" | |
1012 | (+ (f-op4 0) rn rm (f-sub4 15)) | |
1013 | (sequence ((DI tmpry) (DI mac) (DI result) (SI x) (SI y)) | |
1014 | (set x (mem SI rn)) | |
1015 | (set rn (add rn 4)) | |
1016 | (if (eq (index-of rn) (index-of rm)) | |
1017 | (sequence () | |
1018 | (set rn (add rn 4)) | |
1019 | (set rm (add rm 4)))) | |
1020 | (set y (mem SI rm)) | |
1021 | (set rm (add rm 4)) | |
1022 | (set tmpry (mul (zext DI x) (zext DI y))) | |
1023 | (set mac (or DI (sll (zext DI mach) 32) (zext DI macl))) | |
1024 | (set result (add mac tmpry)) | |
1025 | (sequence () | |
1026 | (if sbit | |
1027 | (sequence ((SI min) (SI max)) | |
1028 | (set max (srl (inv DI 0) 16)) | |
1029 | ; Preserve bit 48 for sign. | |
1030 | (set min (srl (inv DI 0) 15)) | |
1031 | (if (gt result max) | |
1032 | (set result max) | |
1033 | (if (lt result min) | |
1034 | (set result min))))) | |
1035 | (set mach (subword SI result 0)) | |
1036 | (set macl (subword SI result 1))))) | |
1037 | ||
1038 | (dshci macw "Multiply and accumulate (word)" | |
1039 | () | |
1040 | "mac.w @${rm}+, @${rn}+" | |
1041 | (+ (f-op4 4) rn rm (f-sub4 15)) | |
1042 | (sequence ((SI tmpry) (DI mac) (DI result) (HI x) (HI y)) | |
1043 | (set x (mem HI rn)) | |
1044 | (set rn (add rn 2)) | |
1045 | (if (eq (index-of rn) (index-of rm)) | |
1046 | (sequence () | |
1047 | (set rn (add rn 2)) | |
1048 | (set rm (add rm 2)))) | |
1049 | (set y (mem HI rm)) | |
1050 | (set rm (add rm 2)) | |
1051 | (set tmpry (mul (zext SI x) (zext SI y))) | |
1052 | (if sbit | |
1053 | (sequence () | |
1054 | (if (add-oflag tmpry macl 0) | |
1055 | (set mach 1)) | |
1056 | (set macl (add tmpry macl))) | |
1057 | (sequence () | |
1058 | (set mac (or DI (sll (zext DI mach) 32) (zext DI macl))) | |
1059 | (set result (add mac (ext DI tmpry))) | |
1060 | (set mach (subword SI result 0)) | |
1061 | (set macl (subword SI result 1)))))) | |
1062 | ||
1063 | (dshci mov "Move" | |
1064 | () | |
1065 | "mov $rm64, $rn64" | |
1066 | (+ (f-op4 6) rn64 rm64 (f-sub4 3)) | |
1067 | (set rn64 rm64)) | |
1068 | ||
1069 | (dshci movi "Move immediate" | |
1070 | () | |
1071 | "mov #$imm8, $rn" | |
1072 | (+ (f-op4 14) rn imm8) | |
1073 | (set rn (ext DI (and QI imm8 255)))) | |
1074 | ||
1075 | (dshci movb1 "Store byte to memory (register indirect w/ zero displacement)" | |
1076 | () | |
1077 | "mov.b $rm, @$rn" | |
1078 | (+ (f-op4 2) rn rm (f-sub4 0)) | |
1079 | (set (mem UQI rn) (subword UQI rm 3))) | |
1080 | ||
1081 | (dshci movb2 "Store byte to memory (register indirect w/ pre-decrement)" | |
1082 | () | |
1083 | "mov.b $rm, @-$rn" | |
1084 | (+ (f-op4 2) rn rm (f-sub4 4)) | |
1085 | (sequence ((DI addr)) | |
1086 | (set addr (sub rn 1)) | |
1087 | (set (mem UQI addr) (subword UQI rm 3)) | |
1088 | (set rn addr))) | |
1089 | ||
1090 | (dshci movb3 "Store byte to memory (register/register indirect)" | |
1091 | () | |
1092 | "mov.b $rm, @(r0,$rn)" | |
1093 | (+ (f-op4 0) rn rm (f-sub4 4)) | |
1094 | (set (mem UQI (add r0 rn)) (subword UQI rm 3))) | |
1095 | ||
1096 | (dshci movb4 "Store byte to memory (GBR-relative w/ displacement)" | |
1097 | () | |
1098 | "mov.b r0, @($imm8, gbr)" | |
1099 | (+ (f-op8 #xc0) imm8) | |
1100 | (sequence ((DI addr)) | |
1101 | (set addr (add gbr imm8)) | |
1102 | (set (mem UQI addr) (subword UQI r0 3)))) | |
1103 | ||
1104 | (dshci movb5 "Store byte to memory (register indirect w/ displacement)" | |
1105 | () | |
1106 | "mov.b r0, @($imm4, $rm)" | |
1107 | (+ (f-op8 #x80) rm imm4) | |
1108 | (sequence ((DI addr)) | |
1109 | (set addr (add rm imm4)) | |
1110 | (set (mem UQI addr) (subword UQI r0 3)))) | |
1111 | ||
1112 | (dshci movb6 "Load byte from memory (register indirect w/ zero displacement)" | |
1113 | () | |
1114 | "mov.b @$rm, $rn" | |
1115 | (+ (f-op4 6) rn rm (f-sub4 0)) | |
1116 | (set rn (ext SI (mem QI rm)))) | |
1117 | ||
1118 | (dshci movb7 "Load byte from memory (register indirect w/ post-increment)" | |
1119 | () | |
1120 | "mov.b @${rm}+, $rn" | |
1121 | (+ (f-op4 6) rn rm (f-sub4 4)) | |
1122 | (sequence ((QI data)) | |
1123 | (set data (mem QI rm)) | |
1124 | (if (eq (index-of rm) (index-of rn)) | |
1125 | (set rm (ext SI data)) | |
1126 | (set rm (add rm 1))) | |
1127 | (set rn (ext SI data)))) | |
1128 | ||
1129 | (dshci movb8 "Load byte from memory (register/register indirect)" | |
1130 | () | |
1131 | "mov.b @(r0, $rm), $rn" | |
1132 | (+ (f-op4 0) rn rm (f-sub4 12)) | |
1133 | (set rn (ext SI (mem QI (add r0 rm))))) | |
1134 | ||
1135 | (dshci movb9 "Load byte from memory (GBR-relative with displacement)" | |
1136 | () | |
1137 | "mov.b @($imm8, gbr), r0" | |
1138 | (+ (f-op8 #xc4) imm8) | |
1139 | (set r0 (ext SI (mem QI (add gbr imm8))))) | |
1140 | ||
1141 | (dshci movb10 "Load byte from memory (register indirect w/ displacement)" | |
1142 | () | |
1143 | "mov.b @($imm4, $rm), r0" | |
1144 | (+ (f-op8 #x84) rm imm4) | |
1145 | (set r0 (ext SI (mem QI (add rm imm4))))) | |
1146 | ||
1147 | (dshci movl1 "Store long word to memory (register indirect w/ zero displacement)" | |
1148 | () | |
1149 | "mov.l $rm, @$rn" | |
1150 | (+ (f-op4 2) rn rm (f-sub4 2)) | |
1151 | (set (mem SI rn) rm)) | |
1152 | ||
1153 | (dshci movl2 "Store long word to memory (register indirect w/ pre-decrement)" | |
1154 | () | |
1155 | "mov.l $rm, @-$rn" | |
1156 | (+ (f-op4 2) rn rm (f-sub4 6)) | |
1157 | (sequence ((SI addr)) | |
1158 | (set addr (sub rn 4)) | |
1159 | (set (mem SI addr) rm) | |
1160 | (set rn addr))) | |
1161 | ||
1162 | (dshci movl3 "Store long word to memory (register/register indirect)" | |
1163 | () | |
1164 | "mov.l $rm, @(r0, $rn)" | |
1165 | (+ (f-op4 0) rn rm (f-sub4 6)) | |
1166 | (set (mem SI (add r0 rn)) rm)) | |
1167 | ||
1168 | (dshci movl4 "Store long word to memory (GBR-relative w/ displacement)" | |
1169 | () | |
1170 | "mov.l r0, @($imm8x4, gbr)" | |
1171 | (+ (f-op8 #xc2) imm8x4) | |
1172 | (set (mem SI (add gbr imm8x4)) r0)) | |
1173 | ||
1174 | (dshci movl5 "Store long word to memory (register indirect w/ displacement)" | |
1175 | () | |
1176 | "mov.l $rm, @($imm4x4, $rn)" | |
1177 | (+ (f-op4 1) rn rm imm4x4) | |
1178 | (set (mem SI (add rn imm4x4)) rm)) | |
1179 | ||
1180 | (dshci movl6 "Load long word to memory (register indirect w/ zero displacement)" | |
1181 | () | |
1182 | "mov.l @$rm, $rn" | |
1183 | (+ (f-op4 6) rn rm (f-sub4 2)) | |
1184 | (set rn (mem SI rm))) | |
1185 | ||
1186 | (dshci movl7 "Load long word from memory (register indirect w/ post-increment)" | |
1187 | () | |
1188 | "mov.l @${rm}+, $rn" | |
1189 | (+ (f-op4 6) rn rm (f-sub4 6)) | |
1190 | (sequence () | |
1191 | (set rn (mem SI rm)) | |
1192 | (if (eq (index-of rm) (index-of rn)) | |
1193 | (set rm rn) | |
1194 | (set rm (add rm 4))))) | |
1195 | ||
1196 | (dshci movl8 "Load long word from memory (register/register indirect)" | |
1197 | () | |
1198 | "mov.l @(r0, $rm), $rn" | |
1199 | (+ (f-op4 0) rn rm (f-sub4 14)) | |
1200 | (set rn (mem SI (add r0 rm)))) | |
1201 | ||
1202 | (dshci movl9 "Load long word from memory (GBR-relative w/ displacement)" | |
1203 | () | |
1204 | "mov.l @($imm8x4, gbr), r0" | |
1205 | (+ (f-op8 #xc6) imm8x4) | |
1206 | (set r0 (mem SI (add gbr imm8x4)))) | |
1207 | ||
1208 | (dshci movl10 "Load long word from memory (PC-relative w/ displacement)" | |
1209 | (ILLSLOT) | |
1210 | "mov.l @($imm8x4, pc), $rn" | |
1211 | (+ (f-op4 13) rn imm8x4) | |
1212 | (set rn (mem SI (add imm8x4 (and (add pc 4) (inv 3)))))) | |
1213 | ||
1214 | (dshci movl11 "Load long word from memory (register indirect w/ displacement)" | |
1215 | () | |
1216 | "mov.l @($imm4x4, $rm), $rn" | |
1217 | (+ (f-op4 5) rn rm imm4x4) | |
1218 | (set rn (mem SI (add rm imm4x4)))) | |
1219 | ||
1220 | (dshci movw1 "Store word to memory (register indirect w/ zero displacement)" | |
1221 | () | |
1222 | "mov.w $rm, @$rn" | |
1223 | (+ (f-op4 2) rn rm (f-sub4 1)) | |
1224 | (set (mem HI rn) (subword HI rm 1))) | |
1225 | ||
1226 | (dshci movw2 "Store word to memory (register indirect w/ pre-decrement)" | |
1227 | () | |
1228 | "mov.w $rm, @-$rn" | |
1229 | (+ (f-op4 2) rn rm (f-sub4 5)) | |
1230 | (sequence ((DI addr)) | |
1231 | (set addr (sub rn 2)) | |
1232 | (set (mem HI addr) (subword HI rm 1)) | |
1233 | (set rn addr))) | |
1234 | ||
1235 | (dshci movw3 "Store word to memory (register/register indirect)" | |
1236 | () | |
1237 | "mov.w $rm, @(r0, $rn)" | |
1238 | (+ (f-op4 0) rn rm (f-sub4 5)) | |
1239 | (set (mem HI (add r0 rn)) (subword HI rm 1))) | |
1240 | ||
1241 | (dshci movw4 "Store word to memory (GBR-relative w/ displacement)" | |
1242 | () | |
1243 | "mov.w r0, @($imm8x2, gbr)" | |
1244 | (+ (f-op8 #xc1) imm8x2) | |
1245 | (set (mem HI (add gbr imm8x2)) (subword HI r0 1))) | |
1246 | ||
1247 | (dshci movw5 "Store word to memory (register indirect w/ displacement)" | |
1248 | () | |
1249 | "mov.w r0, @($imm4x2, $rn)" | |
1250 | (+ (f-op8 #x81) rn imm4x2) | |
1251 | (set (mem HI (add rn imm4x2)) (subword HI r0 1))) | |
1252 | ||
1253 | (dshci movw6 "Load word from memory (register indirect w/ zero displacement)" | |
1254 | () | |
1255 | "mov.w @$rm, $rn" | |
1256 | (+ (f-op4 6) rn rm (f-sub4 1)) | |
1257 | (set rn (ext SI (mem HI rm)))) | |
1258 | ||
1259 | (dshci movw7 "Load word from memory (register indirect w/ post-increment)" | |
1260 | () | |
1261 | "mov.w @${rm}+, $rn" | |
1262 | (+ (f-op4 6) rn rm (f-sub4 5)) | |
1263 | (sequence ((HI data)) | |
1264 | (set data (mem HI rm)) | |
1265 | (if (eq (index-of rm) (index-of rn)) | |
1266 | (set rm (ext SI data)) | |
1267 | (set rm (add rm 2))) | |
1268 | (set rn (ext SI data)))) | |
1269 | ||
1270 | (dshci movw8 "Load word from memory (register/register indirect)" | |
1271 | () | |
1272 | "mov.w @(r0, $rm), $rn" | |
1273 | (+ (f-op4 0) rn rm (f-sub4 13)) | |
1274 | (set rn (ext SI (mem HI (add r0 rm))))) | |
1275 | ||
1276 | (dshci movw9 "Load word from memory (GBR-relative w/ displacement)" | |
1277 | () | |
1278 | "mov.w @($imm8x2, gbr), r0" | |
1279 | (+ (f-op8 #xc5) imm8x2) | |
1280 | (set r0 (ext SI (mem HI (add gbr imm8x2))))) | |
1281 | ||
1282 | (dshci movw10 "Load word from memory (PC-relative w/ displacement)" | |
1283 | (ILLSLOT) | |
1284 | "mov.w @($imm8x2, pc), $rn" | |
1285 | (+ (f-op4 9) rn imm8x2) | |
1286 | (set rn (ext SI (mem HI (add (add pc 4) imm8x2))))) | |
1287 | ||
1288 | (dshci movw11 "Load word from memory (register indirect w/ displacement)" | |
1289 | () | |
1290 | "mov.w @($imm4x2, $rm), r0" | |
1291 | (+ (f-op8 #x85) rm imm4x2) | |
1292 | (set r0 (ext SI (mem HI (add rm imm4x2))))) | |
1293 | ||
1294 | (dshci mova "Move effective address" | |
1295 | (ILLSLOT) | |
1296 | "mova @($imm8x4, pc), r0" | |
1297 | (+ (f-op8 #xc7) imm8x4) | |
1298 | (set r0 (add (and (add pc 4) (inv 3)) imm8x4))) | |
1299 | ||
1300 | (dshci movcal "Move with cache block allocation" | |
1301 | () | |
1302 | "movca.l r0, @$rn" | |
1303 | (+ (f-op4 0) rn (f-sub8 #xc3)) | |
1304 | (set (mem SI rn) r0)) | |
1305 | ||
1306 | (dshci movt "Move t-bit" | |
1307 | () | |
1308 | "movt $rn" | |
1309 | (+ (f-op4 0) rn (f-sub8 41)) | |
1310 | (set rn (zext SI tbit))) | |
1311 | ||
1312 | (dshci mull "Multiply" | |
1313 | () | |
1314 | "mul.l $rm, $rn" | |
1315 | (+ (f-op4 0) rn rm (f-sub4 7)) | |
1316 | (set macl (mul rm rn))) | |
1317 | ||
1318 | (dshci mulsw "Multiply words (signed)" | |
1319 | () | |
1320 | "muls.w $rm, $rn" | |
1321 | (+ (f-op4 2) rn rm (f-sub4 15)) | |
1322 | (set macl (mul (ext SI (subword HI rm 1)) (ext SI (subword HI rn 1))))) | |
1323 | ||
1324 | (dshci muluw "Multiply words (unsigned)" | |
1325 | () | |
1326 | "mulu.w $rm, $rn" | |
1327 | (+ (f-op4 2) rn rm (f-sub4 14)) | |
1328 | (set macl (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1))))) | |
1329 | ||
1330 | (dshci neg "Negate" | |
1331 | () | |
1332 | "neg $rm, $rn" | |
1333 | (+ (f-op4 6) rn rm (f-sub4 11)) | |
1334 | (set rn (neg rm))) | |
1335 | ||
1336 | (dshci negc "Negate with carry" | |
1337 | () | |
1338 | "negc $rm, $rn" | |
1339 | (+ (f-op4 6) rn rm (f-sub4 10)) | |
1340 | (sequence ((BI flag)) | |
1341 | (set flag (sub-cflag 0 rm tbit)) | |
1342 | (set rn (subc 0 rm tbit)) | |
1343 | (set tbit flag))) | |
1344 | ||
1345 | (dshci nop "No operation" | |
1346 | () | |
1347 | "nop" | |
1348 | (+ (f-op16 9)) | |
1349 | (nop)) | |
1350 | ||
1351 | (dshci not "Bitwise NOT" | |
1352 | () | |
1353 | "not $rm64, $rn64" | |
1354 | (+ (f-op4 6) rn64 rm64 (f-sub4 7)) | |
1355 | (set rn64 (inv rm64))) | |
1356 | ||
1357 | (dshci ocbi "Invalidate operand cache block" | |
1358 | () | |
1359 | "ocbi @$rn" | |
1360 | (+ (f-op4 0) rn (f-sub8 147)) | |
1361 | (unimp "ocbi")) | |
1362 | ||
1363 | (dshci ocbp "Purge operand cache block" | |
1364 | () | |
1365 | "ocbp @$rn" | |
1366 | (+ (f-op4 0) rn (f-sub8 163)) | |
1367 | (unimp "ocbp")) | |
1368 | ||
1369 | (dshci ocbwb "Write back operand cache block" | |
1370 | () | |
1371 | "ocbwb @$rn" | |
1372 | (+ (f-op4 0) rn (f-sub8 179)) | |
1373 | (unimp "ocbwb")) | |
1374 | ||
1375 | (dshci or "Bitwise OR" | |
1376 | () | |
1377 | "or $rm64, $rn64" | |
1378 | (+ (f-op4 2) rn64 rm64 (f-sub4 11)) | |
1379 | (set rn64 (or rm64 rn64))) | |
1380 | ||
1381 | (dshci ori "Bitwise OR immediate" | |
1382 | () | |
1383 | "or #$uimm8, r0" | |
1384 | (+ (f-op8 #xcb) uimm8) | |
1385 | (set r0 (or r0 (zext DI uimm8)))) | |
1386 | ||
1387 | (dshci orb "Bitwise OR immediate" | |
1388 | () | |
1389 | "or.b #$imm8, @(r0, gbr)" | |
1390 | (+ (f-op8 #xcf) imm8) | |
1391 | (sequence ((DI addr) (UQI data)) | |
1392 | (set addr (add r0 gbr)) | |
1393 | (set data (or (mem UQI addr) imm8)) | |
1394 | (set (mem UQI addr) data))) | |
1395 | ||
1396 | (dshci pref "Prefetch data" | |
1397 | () | |
1398 | "pref @$rn" | |
1399 | (+ (f-op4 0) rn (f-sub8 131)) | |
1400 | (unimp "pref")) | |
1401 | ||
1402 | (dshci rotcl "Rotate with carry left" | |
1403 | () | |
1404 | "rotcl $rn" | |
1405 | (+ (f-op4 4) rn (f-sub8 36)) | |
1406 | (sequence ((BI temp)) | |
1407 | (set temp (srl rn 31)) | |
1408 | (set rn (or (sll rn 1) tbit)) | |
1409 | (set tbit (if BI temp 1 0)))) | |
1410 | ||
1411 | (dshci rotcr "Rotate with carry right" | |
1412 | () | |
1413 | "rotcr $rn" | |
1414 | (+ (f-op4 4) rn (f-sub8 37)) | |
1415 | (sequence ((BI lsbit) (SI temp)) | |
1416 | (set lsbit (if BI (eq (and rn 1) 0) 0 1)) | |
1417 | (set temp tbit) | |
1418 | (set rn (or (srl rn 1) (sll temp 31))) | |
1419 | (set tbit (if BI lsbit 1 0)))) | |
1420 | ||
1421 | (dshci rotl "Rotate left" | |
1422 | () | |
1423 | "rotl $rn" | |
1424 | (+ (f-op4 4) rn (f-sub8 4)) | |
1425 | (sequence ((BI temp)) | |
1426 | (set temp (srl rn 31)) | |
1427 | (set rn (or (sll rn 1) temp)) | |
1428 | (set tbit (if BI temp 1 0)))) | |
1429 | ||
1430 | (dshci rotr "Rotate right" | |
1431 | () | |
1432 | "rotr $rn" | |
1433 | (+ (f-op4 4) rn (f-sub8 5)) | |
1434 | (sequence ((BI lsbit) (SI temp)) | |
1435 | (set lsbit (if BI (eq (and rn 1) 0) 0 1)) | |
1436 | (set temp lsbit) | |
1437 | (set rn (or (srl rn 1) (sll temp 31))) | |
1438 | (set tbit (if BI lsbit 1 0)))) | |
1439 | ||
1440 | (dshci rts "Return from subroutine" | |
1441 | () | |
1442 | "rts" | |
1443 | (+ (f-op16 11)) | |
1444 | (delay 1 (set pc pr))) | |
1445 | ||
1446 | (dshci sets "Set S-bit" | |
1447 | () | |
1448 | "sets" | |
1449 | (+ (f-op16 88)) | |
1450 | (set sbit 1)) | |
1451 | ||
1452 | (dshci sett "Set T-bit" | |
1453 | () | |
1454 | "sett" | |
1455 | (+ (f-op16 24)) | |
1456 | (set tbit 1)) | |
1457 | ||
1458 | (dshci shad "Shift arithmetic dynamic" | |
1459 | () | |
1460 | "shad $rm, $rn" | |
1461 | (+ (f-op4 4) rn rm (f-sub4 12)) | |
1462 | (sequence ((QI shamt)) | |
1463 | (set shamt (and QI rm 31)) | |
1464 | (if (ge rm 0) | |
1465 | (set rn (sll rn shamt)) | |
1466 | (if (ne shamt 0) | |
1467 | (set rn (sra rn (sub 32 shamt))) | |
1468 | (if (lt rn 0) | |
1469 | (set rn (neg 1)) | |
1470 | (set rn 0)))))) | |
1471 | ||
1472 | (dshci shal "Shift left arithmetic one bit" | |
1473 | () | |
1474 | "shal $rn" | |
1475 | (+ (f-op4 4) rn (f-sub8 32)) | |
1476 | (sequence ((BI t)) | |
1477 | (set t (srl rn 31)) | |
1478 | (set rn (sll rn 1)) | |
1479 | (set tbit (if BI t 1 0)))) | |
1480 | ||
1481 | (dshci shar "Shift right arithmetic one bit" | |
1482 | () | |
1483 | "shar $rn" | |
1484 | (+ (f-op4 4) rn (f-sub8 33)) | |
1485 | (sequence ((BI t)) | |
1486 | (set t (and rn 1)) | |
1487 | (set rn (sra rn 1)) | |
1488 | (set tbit (if BI t 1 0)))) | |
1489 | ||
1490 | (dshci shld "Shift logical dynamic" | |
1491 | () | |
1492 | "shld $rm, $rn" | |
1493 | (+ (f-op4 4) rn rm (f-sub4 13)) | |
1494 | (sequence ((QI shamt)) | |
1495 | (set shamt (and QI rm 31)) | |
1496 | (if (ge rm 0) | |
1497 | (set rn (sll rn shamt)) | |
1498 | (if (ne shamt 0) | |
1499 | (set rn (srl rn (sub 32 shamt))) | |
1500 | (set rn 0))))) | |
1501 | ||
1502 | (dshci shll "Shift left logical one bit" | |
1503 | () | |
1504 | "shll $rn" | |
1505 | (+ (f-op4 4) rn (f-sub8 0)) | |
1506 | (sequence ((BI t)) | |
1507 | (set t (srl rn 31)) | |
1508 | (set rn (sll rn 1)) | |
1509 | (set tbit (if BI t 1 0)))) | |
1510 | ||
1511 | (dshci shll2 "Shift left logical two bits" | |
1512 | () | |
1513 | "shll2 $rn" | |
1514 | (+ (f-op4 4) rn (f-sub8 8)) | |
1515 | (set rn (sll rn 2))) | |
1516 | ||
1517 | (dshci shll8 "Shift left logical eight bits" | |
1518 | () | |
1519 | "shll8 $rn" | |
1520 | (+ (f-op4 4) rn (f-sub8 24)) | |
1521 | (set rn (sll rn 8))) | |
1522 | ||
1523 | (dshci shll16 "Shift left logical sixteen bits" | |
1524 | () | |
1525 | "shll16 $rn" | |
1526 | (+ (f-op4 4) rn (f-sub8 40)) | |
1527 | (set rn (sll rn 16))) | |
1528 | ||
1529 | (dshci shlr "Shift right logical one bit" | |
1530 | () | |
1531 | "shlr $rn" | |
1532 | (+ (f-op4 4) rn (f-sub8 1)) | |
1533 | (sequence ((BI t)) | |
1534 | (set t (and rn 1)) | |
1535 | (set rn (srl rn 1)) | |
1536 | (set tbit (if BI t 1 0)))) | |
1537 | ||
1538 | (dshci shlr2 "Shift right logical two bits" | |
1539 | () | |
1540 | "shlr2 $rn" | |
1541 | (+ (f-op4 4) rn (f-sub8 9)) | |
1542 | (set rn (srl rn 2))) | |
1543 | ||
1544 | (dshci shlr8 "Shift right logical eight bits" | |
1545 | () | |
1546 | "shlr8 $rn" | |
1547 | (+ (f-op4 4) rn (f-sub8 25)) | |
1548 | (set rn (srl rn 8))) | |
1549 | ||
1550 | (dshci shlr16 "Shift right logical sixteen bits" | |
1551 | () | |
1552 | "shlr16 $rn" | |
1553 | (+ (f-op4 4) rn (f-sub8 41)) | |
1554 | (set rn (srl rn 16))) | |
1555 | ||
1556 | (dshci stc-gbr "Store control register (GBR)" | |
1557 | () | |
1558 | "stc gbr, $rn" | |
1559 | (+ (f-op4 0) rn (f-sub8 18)) | |
1560 | (set rn gbr)) | |
1561 | ||
1562 | (dshci stcl-gbr "Store control register (GBR)" | |
1563 | () | |
1564 | "stc.l gbr, @-$rn" | |
1565 | (+ (f-op4 4) rn (f-sub8 19)) | |
1566 | (sequence ((DI addr)) | |
1567 | (set addr (sub rn 4)) | |
1568 | (set (mem SI addr) gbr) | |
1569 | (set rn addr))) | |
1570 | ||
1571 | (dshci sts-fpscr "Store status register (FPSCR)" | |
1572 | () | |
1573 | "sts fpscr, $rn" | |
1574 | (+ (f-op4 0) rn (f-sub8 106)) | |
1575 | (set rn fpscr)) | |
1576 | ||
1577 | (dshci stsl-fpscr "Store status register (FPSCR)" | |
1578 | () | |
1579 | "sts.l fpscr, @-$rn" | |
1580 | (+ (f-op4 4) rn (f-sub8 98)) | |
1581 | (sequence ((DI addr)) | |
1582 | (set addr (sub rn 4)) | |
1583 | (set (mem SI addr) fpscr) | |
1584 | (set rn addr))) | |
1585 | ||
1586 | (dshci sts-fpul "Store status register (FPUL)" | |
1587 | () | |
1588 | "sts fpul, $rn" | |
1589 | (+ (f-op4 0) rn (f-sub8 90)) | |
1590 | (set rn (subword SI fpul 0))) | |
1591 | ||
1592 | (dshci stsl-fpul "Store status register (FPUL)" | |
1593 | () | |
1594 | "sts.l fpul, @-$rn" | |
1595 | (+ (f-op4 4) rn (f-sub8 82)) | |
1596 | (sequence ((DI addr)) | |
1597 | (set addr (sub rn 4)) | |
1598 | (set (mem SF addr) fpul) | |
1599 | (set rn addr))) | |
1600 | ||
1601 | (dshci sts-mach "Store status register (MACH)" | |
1602 | () | |
1603 | "sts mach, $rn" | |
1604 | (+ (f-op4 0) rn (f-sub8 10)) | |
1605 | (set rn mach)) | |
1606 | ||
1607 | (dshci stsl-mach "Store status register (MACH)" | |
1608 | () | |
1609 | "sts.l mach, @-$rn" | |
1610 | (+ (f-op4 4) rn (f-sub8 2)) | |
1611 | (sequence ((DI addr)) | |
1612 | (set addr (sub rn 4)) | |
1613 | (set (mem SI addr) mach) | |
1614 | (set rn addr))) | |
1615 | ||
1616 | (dshci sts-macl "Store status register (MACL)" | |
1617 | () | |
1618 | "sts macl, $rn" | |
1619 | (+ (f-op4 0) rn (f-sub8 26)) | |
1620 | (set rn macl)) | |
1621 | ||
1622 | (dshci stsl-macl "Store status register (MACL)" | |
1623 | () | |
1624 | "sts.l macl, @-$rn" | |
1625 | (+ (f-op4 4) rn (f-sub8 18)) | |
1626 | (sequence ((DI addr)) | |
1627 | (set addr (sub rn 4)) | |
1628 | (set (mem SI addr) macl) | |
1629 | (set rn addr))) | |
1630 | ||
1631 | (dshci sts-pr "Store status register (PR)" | |
1632 | () | |
1633 | "sts pr, $rn" | |
1634 | (+ (f-op4 0) rn (f-sub8 42)) | |
1635 | (set rn pr)) | |
1636 | ||
1637 | (dshci stsl-pr "Store status register (PR)" | |
1638 | () | |
1639 | "sts.l pr, @-$rn" | |
1640 | (+ (f-op4 4) rn (f-sub8 34)) | |
1641 | (sequence ((DI addr)) | |
1642 | (set addr (sub rn 4)) | |
1643 | (set (mem SI addr) pr) | |
1644 | (set rn addr))) | |
1645 | ||
1646 | (dshci sub "Subtract" | |
1647 | () | |
1648 | "sub $rm, $rn" | |
1649 | (+ (f-op4 3) rn rm (f-sub4 8)) | |
1650 | (set rn (sub rn rm))) | |
1651 | ||
1652 | (dshci subc "Subtract and detect carry" | |
1653 | () | |
1654 | "subc $rm, $rn" | |
1655 | (+ (f-op4 3) rn rm (f-sub4 10)) | |
1656 | (sequence ((BI flag)) | |
1657 | (set flag (sub-cflag rn rm tbit)) | |
1658 | (set rn (subc rn rm tbit)) | |
1659 | (set tbit flag))) | |
1660 | ||
1661 | (dshci subv "Subtract and detect overflow" | |
1662 | () | |
1663 | "subv $rm, $rn" | |
1664 | (+ (f-op4 3) rn rm (f-sub4 11)) | |
1665 | (sequence ((BI t)) | |
1666 | (set t (sub-oflag rn rm 0)) | |
1667 | (set rn (sub rn rm)) | |
1668 | (set tbit (if BI t 1 0)))) | |
1669 | ||
1670 | (dshci swapb "Swap bytes" | |
1671 | () | |
1672 | "swap.b $rm, $rn" | |
1673 | (+ (f-op4 6) rn rm (f-sub4 8)) | |
1674 | (sequence ((UHI top-half) (UQI byte1) (UQI byte0)) | |
1675 | (set top-half (subword HI rm 0)) | |
1676 | (set byte1 (subword QI rm 2)) | |
1677 | (set byte0 (subword QI rm 3)) | |
1678 | (set rn (or SI (sll SI top-half 16) (or SI (sll SI byte0 8) byte1))))) | |
1679 | ||
1680 | (dshci swapw "Swap words" | |
1681 | () | |
1682 | "swap.w $rm, $rn" | |
1683 | (+ (f-op4 6) rn rm (f-sub4 9)) | |
1684 | (set rn (or (srl rm 16) (sll rm 16)))) | |
1685 | ||
1686 | (dshci tasb "Test and set byte" | |
1687 | () | |
1688 | "tas.b @$rn" | |
1689 | (+ (f-op4 4) rn (f-sub8 27)) | |
1690 | (sequence ((UQI byte)) | |
1691 | (set byte (mem UQI rn)) | |
1692 | (set tbit (if BI (eq byte 0) 1 0)) | |
1693 | (set byte (or byte 128)) | |
1694 | (set (mem UQI rn) byte))) | |
1695 | ||
1696 | (dshci trapa "Trap" | |
1697 | (ILLSLOT) | |
1698 | "trapa #$uimm8" | |
1699 | (+ (f-op8 #xc3) uimm8) | |
1700 | (c-call "sh64_compact_trapa" uimm8 pc)) | |
1701 | ||
1702 | (dshci tst "Test and set t-bit" | |
1703 | () | |
1704 | "tst $rm, $rn" | |
1705 | (+ (f-op4 2) rn rm (f-sub4 8)) | |
1706 | (set tbit (if BI (eq (and rm rn) 0) 1 0))) | |
1707 | ||
1708 | (dshci tsti "Test and set t-bit immediate" | |
1709 | () | |
1710 | "tst #$uimm8, r0" | |
1711 | (+ (f-op8 #xc8) uimm8) | |
1712 | (set tbit (if BI (eq (and r0 (zext SI uimm8)) 0) 1 0))) | |
1713 | ||
1714 | (dshci tstb "Test and set t-bit immedate with memory byte" | |
1715 | () | |
1716 | "tst.b #$imm8, @(r0, gbr)" | |
1717 | (+ (f-op8 #xcc) imm8) | |
1718 | (sequence ((DI addr)) | |
1719 | (set addr (add r0 gbr)) | |
1720 | (set tbit (if BI (eq (and (mem UQI addr) imm8) 0) 1 0)))) | |
1721 | ||
1722 | (dshci xor "Exclusive OR" | |
1723 | () | |
1724 | "xor $rm64, $rn64" | |
1725 | (+ (f-op4 2) rn64 rm64 (f-sub4 10)) | |
1726 | (set rn64 (xor rn64 rm64))) | |
1727 | ||
1728 | (dshci xori "Exclusive OR immediate" | |
1729 | () | |
1730 | "xor #$uimm8, r0" | |
1731 | (+ (f-op8 #xca) uimm8) | |
1732 | (set (reg h-gr 0) (xor (reg h-gr 0) (zext DI uimm8)))) | |
1733 | ||
1734 | (dshci xorb "Exclusive OR immediate with memory byte" | |
1735 | () | |
1736 | "xor.b #$imm8, @(r0, gbr)" | |
1737 | (+ (f-op8 #xce) imm8) | |
1738 | (sequence ((DI addr) (UQI data)) | |
1739 | (set addr (add r0 gbr)) | |
1740 | (set data (xor (mem UQI addr) imm8)) | |
1741 | (set (mem UQI addr) data))) | |
1742 | ||
1743 | (dshci xtrct "Extract" | |
1744 | () | |
1745 | "xtrct $rm, $rn" | |
1746 | (+ (f-op4 2) rn rm (f-sub4 13)) | |
1747 | (set rn (or (sll rm 16) (srl rn 16)))) |