Commit | Line | Data |
---|---|---|
f58b082a RW |
1 | /* |
2 | * ACPI support for Intel Lynxpoint LPSS. | |
3 | * | |
4 | * Copyright (C) 2013, Intel Corporation | |
5 | * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> | |
6 | * Rafael J. Wysocki <rafael.j.wysocki@intel.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/acpi.h> | |
14 | #include <linux/clk.h> | |
15 | #include <linux/clkdev.h> | |
16 | #include <linux/clk-provider.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/platform_data/clk-lpss.h> | |
2e0f8822 | 21 | #include <linux/pm_runtime.h> |
c78b0830 | 22 | #include <linux/delay.h> |
f58b082a RW |
23 | |
24 | #include "internal.h" | |
25 | ||
26 | ACPI_MODULE_NAME("acpi_lpss"); | |
27 | ||
d6ddaaac RW |
28 | #ifdef CONFIG_X86_INTEL_LPSS |
29 | ||
30 | #define LPSS_ADDR(desc) ((unsigned long)&desc) | |
31 | ||
f58b082a | 32 | #define LPSS_CLK_SIZE 0x04 |
2e0f8822 RW |
33 | #define LPSS_LTR_SIZE 0x18 |
34 | ||
35 | /* Offsets relative to LPSS_PRIVATE_OFFSET */ | |
ed3a872e | 36 | #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) |
765bdd4e MW |
37 | #define LPSS_RESETS 0x04 |
38 | #define LPSS_RESETS_RESET_FUNC BIT(0) | |
39 | #define LPSS_RESETS_RESET_APB BIT(1) | |
2e0f8822 RW |
40 | #define LPSS_GENERAL 0x08 |
41 | #define LPSS_GENERAL_LTR_MODE_SW BIT(2) | |
088f1fd2 | 42 | #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) |
2e0f8822 RW |
43 | #define LPSS_SW_LTR 0x10 |
44 | #define LPSS_AUTO_LTR 0x14 | |
1a8f8351 RW |
45 | #define LPSS_LTR_SNOOP_REQ BIT(15) |
46 | #define LPSS_LTR_SNOOP_MASK 0x0000FFFF | |
47 | #define LPSS_LTR_SNOOP_LAT_1US 0x800 | |
48 | #define LPSS_LTR_SNOOP_LAT_32US 0xC00 | |
49 | #define LPSS_LTR_SNOOP_LAT_SHIFT 5 | |
50 | #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 | |
51 | #define LPSS_LTR_MAX_VAL 0x3FF | |
06d86415 HK |
52 | #define LPSS_TX_INT 0x20 |
53 | #define LPSS_TX_INT_MASK BIT(1) | |
f58b082a | 54 | |
c78b0830 HK |
55 | #define LPSS_PRV_REG_COUNT 9 |
56 | ||
f6272170 MW |
57 | struct lpss_shared_clock { |
58 | const char *name; | |
59 | unsigned long rate; | |
60 | struct clk *clk; | |
61 | }; | |
62 | ||
06d86415 | 63 | struct lpss_private_data; |
f58b082a RW |
64 | |
65 | struct lpss_device_desc { | |
66 | bool clk_required; | |
b59cc200 | 67 | const char *clkdev_name; |
2e0f8822 RW |
68 | bool ltr_required; |
69 | unsigned int prv_offset; | |
958c4eb2 | 70 | size_t prv_size_override; |
ed3a872e | 71 | bool clk_divider; |
f6272170 | 72 | bool clk_gate; |
c78b0830 | 73 | bool save_ctx; |
f6272170 | 74 | struct lpss_shared_clock *shared_clock; |
06d86415 | 75 | void (*setup)(struct lpss_private_data *pdata); |
f58b082a RW |
76 | }; |
77 | ||
b59cc200 RW |
78 | static struct lpss_device_desc lpss_dma_desc = { |
79 | .clk_required = true, | |
80 | .clkdev_name = "hclk", | |
81 | }; | |
82 | ||
f58b082a RW |
83 | struct lpss_private_data { |
84 | void __iomem *mmio_base; | |
85 | resource_size_t mmio_size; | |
86 | struct clk *clk; | |
87 | const struct lpss_device_desc *dev_desc; | |
c78b0830 | 88 | u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; |
f58b082a RW |
89 | }; |
90 | ||
06d86415 HK |
91 | static void lpss_uart_setup(struct lpss_private_data *pdata) |
92 | { | |
088f1fd2 | 93 | unsigned int offset; |
06d86415 HK |
94 | u32 reg; |
95 | ||
088f1fd2 HK |
96 | offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; |
97 | reg = readl(pdata->mmio_base + offset); | |
98 | writel(reg | LPSS_TX_INT_MASK, pdata->mmio_base + offset); | |
99 | ||
100 | offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; | |
101 | reg = readl(pdata->mmio_base + offset); | |
102 | writel(reg | LPSS_GENERAL_UART_RTS_OVRD, pdata->mmio_base + offset); | |
06d86415 HK |
103 | } |
104 | ||
765bdd4e MW |
105 | static void lpss_i2c_setup(struct lpss_private_data *pdata) |
106 | { | |
107 | unsigned int offset; | |
108 | u32 val; | |
109 | ||
110 | offset = pdata->dev_desc->prv_offset + LPSS_RESETS; | |
111 | val = readl(pdata->mmio_base + offset); | |
112 | val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; | |
113 | writel(val, pdata->mmio_base + offset); | |
114 | } | |
115 | ||
43218a1b JY |
116 | static struct lpss_device_desc wpt_dev_desc = { |
117 | .clk_required = true, | |
118 | .prv_offset = 0x800, | |
119 | .ltr_required = true, | |
120 | .clk_divider = true, | |
121 | .clk_gate = true, | |
122 | }; | |
123 | ||
f58b082a | 124 | static struct lpss_device_desc lpt_dev_desc = { |
ed3a872e HK |
125 | .clk_required = true, |
126 | .prv_offset = 0x800, | |
127 | .ltr_required = true, | |
128 | .clk_divider = true, | |
129 | .clk_gate = true, | |
130 | }; | |
131 | ||
132 | static struct lpss_device_desc lpt_i2c_dev_desc = { | |
f58b082a | 133 | .clk_required = true, |
2e0f8822 RW |
134 | .prv_offset = 0x800, |
135 | .ltr_required = true, | |
f6272170 | 136 | .clk_gate = true, |
2e0f8822 RW |
137 | }; |
138 | ||
06d86415 HK |
139 | static struct lpss_device_desc lpt_uart_dev_desc = { |
140 | .clk_required = true, | |
141 | .prv_offset = 0x800, | |
142 | .ltr_required = true, | |
ed3a872e | 143 | .clk_divider = true, |
06d86415 HK |
144 | .clk_gate = true, |
145 | .setup = lpss_uart_setup, | |
2e0f8822 RW |
146 | }; |
147 | ||
148 | static struct lpss_device_desc lpt_sdio_dev_desc = { | |
149 | .prv_offset = 0x1000, | |
958c4eb2 | 150 | .prv_size_override = 0x1018, |
2e0f8822 | 151 | .ltr_required = true, |
f58b082a RW |
152 | }; |
153 | ||
e1c74817 CCE |
154 | static struct lpss_shared_clock pwm_clock = { |
155 | .name = "pwm_clk", | |
156 | .rate = 25000000, | |
157 | }; | |
158 | ||
159 | static struct lpss_device_desc byt_pwm_dev_desc = { | |
160 | .clk_required = true, | |
c78b0830 | 161 | .save_ctx = true, |
e1c74817 CCE |
162 | .shared_clock = &pwm_clock, |
163 | }; | |
164 | ||
f6272170 MW |
165 | static struct lpss_device_desc byt_uart_dev_desc = { |
166 | .clk_required = true, | |
167 | .prv_offset = 0x800, | |
ed3a872e | 168 | .clk_divider = true, |
f6272170 | 169 | .clk_gate = true, |
c78b0830 | 170 | .save_ctx = true, |
06d86415 | 171 | .setup = lpss_uart_setup, |
f6272170 MW |
172 | }; |
173 | ||
f6272170 MW |
174 | static struct lpss_device_desc byt_spi_dev_desc = { |
175 | .clk_required = true, | |
176 | .prv_offset = 0x400, | |
ed3a872e | 177 | .clk_divider = true, |
f6272170 | 178 | .clk_gate = true, |
c78b0830 | 179 | .save_ctx = true, |
f6272170 MW |
180 | }; |
181 | ||
182 | static struct lpss_device_desc byt_sdio_dev_desc = { | |
183 | .clk_required = true, | |
184 | }; | |
185 | ||
186 | static struct lpss_shared_clock i2c_clock = { | |
187 | .name = "i2c_clk", | |
188 | .rate = 100000000, | |
189 | }; | |
190 | ||
191 | static struct lpss_device_desc byt_i2c_dev_desc = { | |
192 | .clk_required = true, | |
193 | .prv_offset = 0x800, | |
c78b0830 | 194 | .save_ctx = true, |
f6272170 | 195 | .shared_clock = &i2c_clock, |
765bdd4e | 196 | .setup = lpss_i2c_setup, |
f6272170 MW |
197 | }; |
198 | ||
1bfbd8eb AC |
199 | static struct lpss_shared_clock bsw_pwm_clock = { |
200 | .name = "pwm_clk", | |
201 | .rate = 19200000, | |
202 | }; | |
203 | ||
204 | static struct lpss_device_desc bsw_pwm_dev_desc = { | |
205 | .clk_required = true, | |
206 | .save_ctx = true, | |
207 | .shared_clock = &bsw_pwm_clock, | |
208 | }; | |
209 | ||
d6ddaaac RW |
210 | #else |
211 | ||
212 | #define LPSS_ADDR(desc) (0UL) | |
213 | ||
214 | #endif /* CONFIG_X86_INTEL_LPSS */ | |
215 | ||
f58b082a | 216 | static const struct acpi_device_id acpi_lpss_device_ids[] = { |
b59cc200 | 217 | /* Generic LPSS devices */ |
d6ddaaac | 218 | { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, |
b59cc200 | 219 | |
f58b082a | 220 | /* Lynxpoint LPSS devices */ |
d6ddaaac RW |
221 | { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, |
222 | { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, | |
223 | { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
224 | { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
225 | { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, | |
226 | { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, | |
227 | { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
f58b082a RW |
228 | { "INT33C7", }, |
229 | ||
f6272170 | 230 | /* BayTrail LPSS devices */ |
d6ddaaac RW |
231 | { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, |
232 | { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, | |
233 | { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, | |
234 | { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, | |
235 | { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, | |
f6272170 | 236 | { "INT33B2", }, |
20482d32 | 237 | { "INT33FC", }, |
f6272170 | 238 | |
1bfbd8eb AC |
239 | /* Braswell LPSS devices */ |
240 | { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, | |
241 | { "8086228A", LPSS_ADDR(byt_uart_dev_desc) }, | |
242 | { "8086228E", LPSS_ADDR(byt_spi_dev_desc) }, | |
243 | { "808622C1", LPSS_ADDR(byt_i2c_dev_desc) }, | |
244 | ||
d6ddaaac RW |
245 | { "INT3430", LPSS_ADDR(lpt_dev_desc) }, |
246 | { "INT3431", LPSS_ADDR(lpt_dev_desc) }, | |
247 | { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
248 | { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
249 | { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, | |
250 | { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, | |
251 | { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
a4d97536 MW |
252 | { "INT3437", }, |
253 | ||
43218a1b JY |
254 | { "INT3438", LPSS_ADDR(wpt_dev_desc) }, |
255 | ||
f58b082a RW |
256 | { } |
257 | }; | |
258 | ||
d6ddaaac RW |
259 | #ifdef CONFIG_X86_INTEL_LPSS |
260 | ||
f58b082a RW |
261 | static int is_memory(struct acpi_resource *res, void *not_used) |
262 | { | |
263 | struct resource r; | |
264 | return !acpi_dev_resource_memory(res, &r); | |
265 | } | |
266 | ||
267 | /* LPSS main clock device. */ | |
268 | static struct platform_device *lpss_clk_dev; | |
269 | ||
270 | static inline void lpt_register_clock_device(void) | |
271 | { | |
272 | lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0); | |
273 | } | |
274 | ||
275 | static int register_device_clock(struct acpi_device *adev, | |
276 | struct lpss_private_data *pdata) | |
277 | { | |
278 | const struct lpss_device_desc *dev_desc = pdata->dev_desc; | |
f6272170 | 279 | struct lpss_shared_clock *shared_clock = dev_desc->shared_clock; |
ed3a872e | 280 | const char *devname = dev_name(&adev->dev); |
f6272170 | 281 | struct clk *clk = ERR_PTR(-ENODEV); |
b59cc200 | 282 | struct lpss_clk_data *clk_data; |
ed3a872e HK |
283 | const char *parent, *clk_name; |
284 | void __iomem *prv_base; | |
f58b082a RW |
285 | |
286 | if (!lpss_clk_dev) | |
287 | lpt_register_clock_device(); | |
288 | ||
b59cc200 RW |
289 | clk_data = platform_get_drvdata(lpss_clk_dev); |
290 | if (!clk_data) | |
291 | return -ENODEV; | |
292 | ||
293 | if (dev_desc->clkdev_name) { | |
294 | clk_register_clkdev(clk_data->clk, dev_desc->clkdev_name, | |
ed3a872e | 295 | devname); |
b59cc200 RW |
296 | return 0; |
297 | } | |
298 | ||
299 | if (!pdata->mmio_base | |
2e0f8822 | 300 | || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) |
f58b082a RW |
301 | return -ENODATA; |
302 | ||
f6272170 | 303 | parent = clk_data->name; |
ed3a872e | 304 | prv_base = pdata->mmio_base + dev_desc->prv_offset; |
f6272170 MW |
305 | |
306 | if (shared_clock) { | |
307 | clk = shared_clock->clk; | |
308 | if (!clk) { | |
309 | clk = clk_register_fixed_rate(NULL, shared_clock->name, | |
310 | "lpss_clk", 0, | |
311 | shared_clock->rate); | |
312 | shared_clock->clk = clk; | |
313 | } | |
314 | parent = shared_clock->name; | |
315 | } | |
316 | ||
317 | if (dev_desc->clk_gate) { | |
ed3a872e HK |
318 | clk = clk_register_gate(NULL, devname, parent, 0, |
319 | prv_base, 0, 0, NULL); | |
320 | parent = devname; | |
321 | } | |
322 | ||
323 | if (dev_desc->clk_divider) { | |
324 | /* Prevent division by zero */ | |
325 | if (!readl(prv_base)) | |
326 | writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); | |
327 | ||
328 | clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); | |
329 | if (!clk_name) | |
330 | return -ENOMEM; | |
331 | clk = clk_register_fractional_divider(NULL, clk_name, parent, | |
332 | 0, prv_base, | |
333 | 1, 15, 16, 15, 0, NULL); | |
334 | parent = clk_name; | |
335 | ||
336 | clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); | |
337 | if (!clk_name) { | |
338 | kfree(parent); | |
339 | return -ENOMEM; | |
340 | } | |
341 | clk = clk_register_gate(NULL, clk_name, parent, | |
342 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, | |
343 | prv_base, 31, 0, NULL); | |
344 | kfree(parent); | |
345 | kfree(clk_name); | |
f6272170 | 346 | } |
f58b082a | 347 | |
f6272170 MW |
348 | if (IS_ERR(clk)) |
349 | return PTR_ERR(clk); | |
f58b082a | 350 | |
ed3a872e HK |
351 | pdata->clk = clk; |
352 | clk_register_clkdev(clk, NULL, devname); | |
f58b082a RW |
353 | return 0; |
354 | } | |
355 | ||
356 | static int acpi_lpss_create_device(struct acpi_device *adev, | |
357 | const struct acpi_device_id *id) | |
358 | { | |
359 | struct lpss_device_desc *dev_desc; | |
360 | struct lpss_private_data *pdata; | |
361 | struct resource_list_entry *rentry; | |
362 | struct list_head resource_list; | |
8ce62f85 | 363 | struct platform_device *pdev; |
f58b082a RW |
364 | int ret; |
365 | ||
366 | dev_desc = (struct lpss_device_desc *)id->driver_data; | |
8ce62f85 RW |
367 | if (!dev_desc) { |
368 | pdev = acpi_create_platform_device(adev); | |
369 | return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; | |
370 | } | |
f58b082a RW |
371 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); |
372 | if (!pdata) | |
373 | return -ENOMEM; | |
374 | ||
375 | INIT_LIST_HEAD(&resource_list); | |
376 | ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); | |
377 | if (ret < 0) | |
378 | goto err_out; | |
379 | ||
380 | list_for_each_entry(rentry, &resource_list, node) | |
381 | if (resource_type(&rentry->res) == IORESOURCE_MEM) { | |
958c4eb2 MW |
382 | if (dev_desc->prv_size_override) |
383 | pdata->mmio_size = dev_desc->prv_size_override; | |
384 | else | |
385 | pdata->mmio_size = resource_size(&rentry->res); | |
f58b082a RW |
386 | pdata->mmio_base = ioremap(rentry->res.start, |
387 | pdata->mmio_size); | |
f58b082a RW |
388 | break; |
389 | } | |
390 | ||
391 | acpi_dev_free_resource_list(&resource_list); | |
392 | ||
af65cfe9 MW |
393 | pdata->dev_desc = dev_desc; |
394 | ||
f58b082a RW |
395 | if (dev_desc->clk_required) { |
396 | ret = register_device_clock(adev, pdata); | |
397 | if (ret) { | |
b9e95fc6 RW |
398 | /* Skip the device, but continue the namespace scan. */ |
399 | ret = 0; | |
400 | goto err_out; | |
f58b082a RW |
401 | } |
402 | } | |
403 | ||
b9e95fc6 RW |
404 | /* |
405 | * This works around a known issue in ACPI tables where LPSS devices | |
406 | * have _PS0 and _PS3 without _PSC (and no power resources), so | |
407 | * acpi_bus_init_power() will assume that the BIOS has put them into D0. | |
408 | */ | |
409 | ret = acpi_device_fix_up_power(adev); | |
410 | if (ret) { | |
411 | /* Skip the device, but continue the namespace scan. */ | |
412 | ret = 0; | |
413 | goto err_out; | |
414 | } | |
415 | ||
06d86415 HK |
416 | if (dev_desc->setup) |
417 | dev_desc->setup(pdata); | |
418 | ||
f58b082a | 419 | adev->driver_data = pdata; |
8ce62f85 RW |
420 | pdev = acpi_create_platform_device(adev); |
421 | if (!IS_ERR_OR_NULL(pdev)) { | |
422 | device_enable_async_suspend(&pdev->dev); | |
423 | return 1; | |
424 | } | |
f58b082a | 425 | |
8ce62f85 | 426 | ret = PTR_ERR(pdev); |
f58b082a RW |
427 | adev->driver_data = NULL; |
428 | ||
429 | err_out: | |
430 | kfree(pdata); | |
431 | return ret; | |
432 | } | |
433 | ||
1a8f8351 RW |
434 | static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) |
435 | { | |
436 | return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
437 | } | |
438 | ||
439 | static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, | |
440 | unsigned int reg) | |
441 | { | |
442 | writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
443 | } | |
444 | ||
2e0f8822 RW |
445 | static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) |
446 | { | |
447 | struct acpi_device *adev; | |
448 | struct lpss_private_data *pdata; | |
449 | unsigned long flags; | |
450 | int ret; | |
451 | ||
452 | ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); | |
453 | if (WARN_ON(ret)) | |
454 | return ret; | |
455 | ||
456 | spin_lock_irqsave(&dev->power.lock, flags); | |
457 | if (pm_runtime_suspended(dev)) { | |
458 | ret = -EAGAIN; | |
459 | goto out; | |
460 | } | |
461 | pdata = acpi_driver_data(adev); | |
462 | if (WARN_ON(!pdata || !pdata->mmio_base)) { | |
463 | ret = -ENODEV; | |
464 | goto out; | |
465 | } | |
1a8f8351 | 466 | *val = __lpss_reg_read(pdata, reg); |
2e0f8822 RW |
467 | |
468 | out: | |
469 | spin_unlock_irqrestore(&dev->power.lock, flags); | |
470 | return ret; | |
471 | } | |
472 | ||
473 | static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, | |
474 | char *buf) | |
475 | { | |
476 | u32 ltr_value = 0; | |
477 | unsigned int reg; | |
478 | int ret; | |
479 | ||
480 | reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; | |
481 | ret = lpss_reg_read(dev, reg, <r_value); | |
482 | if (ret) | |
483 | return ret; | |
484 | ||
485 | return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); | |
486 | } | |
487 | ||
488 | static ssize_t lpss_ltr_mode_show(struct device *dev, | |
489 | struct device_attribute *attr, char *buf) | |
490 | { | |
491 | u32 ltr_mode = 0; | |
492 | char *outstr; | |
493 | int ret; | |
494 | ||
495 | ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); | |
496 | if (ret) | |
497 | return ret; | |
498 | ||
499 | outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; | |
500 | return sprintf(buf, "%s\n", outstr); | |
501 | } | |
502 | ||
503 | static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
504 | static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
505 | static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); | |
506 | ||
507 | static struct attribute *lpss_attrs[] = { | |
508 | &dev_attr_auto_ltr.attr, | |
509 | &dev_attr_sw_ltr.attr, | |
510 | &dev_attr_ltr_mode.attr, | |
511 | NULL, | |
512 | }; | |
513 | ||
514 | static struct attribute_group lpss_attr_group = { | |
515 | .attrs = lpss_attrs, | |
516 | .name = "lpss_ltr", | |
517 | }; | |
518 | ||
1a8f8351 RW |
519 | static void acpi_lpss_set_ltr(struct device *dev, s32 val) |
520 | { | |
521 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
522 | u32 ltr_mode, ltr_val; | |
523 | ||
524 | ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); | |
525 | if (val < 0) { | |
526 | if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { | |
527 | ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; | |
528 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
529 | } | |
530 | return; | |
531 | } | |
532 | ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; | |
533 | if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { | |
534 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US; | |
535 | val = LPSS_LTR_MAX_VAL; | |
536 | } else if (val > LPSS_LTR_MAX_VAL) { | |
537 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; | |
538 | val >>= LPSS_LTR_SNOOP_LAT_SHIFT; | |
539 | } else { | |
540 | ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; | |
541 | } | |
542 | ltr_val |= val; | |
543 | __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); | |
544 | if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { | |
545 | ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; | |
546 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
547 | } | |
548 | } | |
549 | ||
c78b0830 HK |
550 | #ifdef CONFIG_PM |
551 | /** | |
552 | * acpi_lpss_save_ctx() - Save the private registers of LPSS device | |
553 | * @dev: LPSS device | |
554 | * | |
555 | * Most LPSS devices have private registers which may loose their context when | |
556 | * the device is powered down. acpi_lpss_save_ctx() saves those registers into | |
557 | * prv_reg_ctx array. | |
558 | */ | |
559 | static void acpi_lpss_save_ctx(struct device *dev) | |
560 | { | |
561 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
562 | unsigned int i; | |
563 | ||
564 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
565 | unsigned long offset = i * sizeof(u32); | |
566 | ||
567 | pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); | |
568 | dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", | |
569 | pdata->prv_reg_ctx[i], offset); | |
570 | } | |
571 | } | |
572 | ||
573 | /** | |
574 | * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device | |
575 | * @dev: LPSS device | |
576 | * | |
577 | * Restores the registers that were previously stored with acpi_lpss_save_ctx(). | |
578 | */ | |
579 | static void acpi_lpss_restore_ctx(struct device *dev) | |
580 | { | |
581 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
582 | unsigned int i; | |
583 | ||
584 | /* | |
585 | * The following delay is needed or the subsequent write operations may | |
586 | * fail. The LPSS devices are actually PCI devices and the PCI spec | |
587 | * expects 10ms delay before the device can be accessed after D3 to D0 | |
588 | * transition. | |
589 | */ | |
590 | msleep(10); | |
591 | ||
592 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
593 | unsigned long offset = i * sizeof(u32); | |
594 | ||
595 | __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); | |
596 | dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", | |
597 | pdata->prv_reg_ctx[i], offset); | |
598 | } | |
599 | } | |
600 | ||
601 | #ifdef CONFIG_PM_SLEEP | |
602 | static int acpi_lpss_suspend_late(struct device *dev) | |
603 | { | |
604 | int ret = pm_generic_suspend_late(dev); | |
605 | ||
606 | if (ret) | |
607 | return ret; | |
608 | ||
609 | acpi_lpss_save_ctx(dev); | |
610 | return acpi_dev_suspend_late(dev); | |
611 | } | |
612 | ||
613 | static int acpi_lpss_restore_early(struct device *dev) | |
614 | { | |
615 | int ret = acpi_dev_resume_early(dev); | |
616 | ||
617 | if (ret) | |
618 | return ret; | |
619 | ||
620 | acpi_lpss_restore_ctx(dev); | |
621 | return pm_generic_resume_early(dev); | |
622 | } | |
623 | #endif /* CONFIG_PM_SLEEP */ | |
624 | ||
625 | #ifdef CONFIG_PM_RUNTIME | |
626 | static int acpi_lpss_runtime_suspend(struct device *dev) | |
627 | { | |
628 | int ret = pm_generic_runtime_suspend(dev); | |
629 | ||
630 | if (ret) | |
631 | return ret; | |
632 | ||
633 | acpi_lpss_save_ctx(dev); | |
634 | return acpi_dev_runtime_suspend(dev); | |
635 | } | |
636 | ||
637 | static int acpi_lpss_runtime_resume(struct device *dev) | |
638 | { | |
639 | int ret = acpi_dev_runtime_resume(dev); | |
640 | ||
641 | if (ret) | |
642 | return ret; | |
643 | ||
644 | acpi_lpss_restore_ctx(dev); | |
645 | return pm_generic_runtime_resume(dev); | |
646 | } | |
647 | #endif /* CONFIG_PM_RUNTIME */ | |
648 | #endif /* CONFIG_PM */ | |
649 | ||
650 | static struct dev_pm_domain acpi_lpss_pm_domain = { | |
651 | .ops = { | |
652 | #ifdef CONFIG_PM_SLEEP | |
653 | .suspend_late = acpi_lpss_suspend_late, | |
654 | .restore_early = acpi_lpss_restore_early, | |
655 | .prepare = acpi_subsys_prepare, | |
656 | .complete = acpi_subsys_complete, | |
657 | .suspend = acpi_subsys_suspend, | |
658 | .resume_early = acpi_subsys_resume_early, | |
659 | .freeze = acpi_subsys_freeze, | |
660 | .poweroff = acpi_subsys_suspend, | |
661 | .poweroff_late = acpi_subsys_suspend_late, | |
662 | #endif | |
663 | #ifdef CONFIG_PM_RUNTIME | |
664 | .runtime_suspend = acpi_lpss_runtime_suspend, | |
665 | .runtime_resume = acpi_lpss_runtime_resume, | |
666 | #endif | |
667 | }, | |
668 | }; | |
669 | ||
2e0f8822 RW |
670 | static int acpi_lpss_platform_notify(struct notifier_block *nb, |
671 | unsigned long action, void *data) | |
672 | { | |
673 | struct platform_device *pdev = to_platform_device(data); | |
674 | struct lpss_private_data *pdata; | |
675 | struct acpi_device *adev; | |
676 | const struct acpi_device_id *id; | |
2e0f8822 RW |
677 | |
678 | id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); | |
679 | if (!id || !id->driver_data) | |
680 | return 0; | |
681 | ||
682 | if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
683 | return 0; | |
684 | ||
685 | pdata = acpi_driver_data(adev); | |
c78b0830 | 686 | if (!pdata || !pdata->mmio_base) |
2e0f8822 RW |
687 | return 0; |
688 | ||
689 | if (pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { | |
690 | dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); | |
691 | return 0; | |
692 | } | |
693 | ||
c78b0830 HK |
694 | switch (action) { |
695 | case BUS_NOTIFY_BOUND_DRIVER: | |
696 | if (pdata->dev_desc->save_ctx) | |
697 | pdev->dev.pm_domain = &acpi_lpss_pm_domain; | |
698 | break; | |
699 | case BUS_NOTIFY_UNBOUND_DRIVER: | |
700 | if (pdata->dev_desc->save_ctx) | |
701 | pdev->dev.pm_domain = NULL; | |
702 | break; | |
703 | case BUS_NOTIFY_ADD_DEVICE: | |
704 | if (pdata->dev_desc->ltr_required) | |
705 | return sysfs_create_group(&pdev->dev.kobj, | |
706 | &lpss_attr_group); | |
707 | case BUS_NOTIFY_DEL_DEVICE: | |
708 | if (pdata->dev_desc->ltr_required) | |
709 | sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); | |
710 | default: | |
711 | break; | |
712 | } | |
2e0f8822 | 713 | |
c78b0830 | 714 | return 0; |
2e0f8822 RW |
715 | } |
716 | ||
717 | static struct notifier_block acpi_lpss_nb = { | |
718 | .notifier_call = acpi_lpss_platform_notify, | |
719 | }; | |
720 | ||
1a8f8351 RW |
721 | static void acpi_lpss_bind(struct device *dev) |
722 | { | |
723 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
724 | ||
725 | if (!pdata || !pdata->mmio_base || !pdata->dev_desc->ltr_required) | |
726 | return; | |
727 | ||
728 | if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) | |
729 | dev->power.set_latency_tolerance = acpi_lpss_set_ltr; | |
730 | else | |
731 | dev_err(dev, "MMIO size insufficient to access LTR\n"); | |
732 | } | |
733 | ||
734 | static void acpi_lpss_unbind(struct device *dev) | |
735 | { | |
736 | dev->power.set_latency_tolerance = NULL; | |
737 | } | |
738 | ||
f58b082a RW |
739 | static struct acpi_scan_handler lpss_handler = { |
740 | .ids = acpi_lpss_device_ids, | |
741 | .attach = acpi_lpss_create_device, | |
1a8f8351 RW |
742 | .bind = acpi_lpss_bind, |
743 | .unbind = acpi_lpss_unbind, | |
f58b082a RW |
744 | }; |
745 | ||
746 | void __init acpi_lpss_init(void) | |
747 | { | |
2e0f8822 RW |
748 | if (!lpt_clk_init()) { |
749 | bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); | |
f58b082a | 750 | acpi_scan_add_handler(&lpss_handler); |
2e0f8822 | 751 | } |
f58b082a | 752 | } |
d6ddaaac RW |
753 | |
754 | #else | |
755 | ||
756 | static struct acpi_scan_handler lpss_handler = { | |
757 | .ids = acpi_lpss_device_ids, | |
758 | }; | |
759 | ||
760 | void __init acpi_lpss_init(void) | |
761 | { | |
762 | acpi_scan_add_handler(&lpss_handler); | |
763 | } | |
764 | ||
765 | #endif /* CONFIG_X86_INTEL_LPSS */ |