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nfit: in acpi_nfit_init, break on a 0-length table
[deliverable/linux.git] / drivers / acpi / nfit.c
CommitLineData
b94d5230
DW		 1/*
2 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of version 2 of the GNU General Public License as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13#include <linux/list_sort.h>
14#include <linux/libnvdimm.h>
15#include <linux/module.h>
047fc8a1 16#include <linux/mutex.h>
62232e45 17#include <linux/ndctl.h>
b94d5230
DW		 18#include <linux/list.h>
19#include <linux/acpi.h>
eaf96153 20#include <linux/sort.h>
c2ad2954 21#include <linux/pmem.h>
047fc8a1 22#include <linux/io.h>
96601adb 23#include <asm/cacheflush.h>
b94d5230
DW		 24#include "nfit.h"
25
047fc8a1
RZ		 26/*
27 * For readq() and writeq() on 32-bit builds, the hi-lo, lo-hi order is
28 * irrelevant.
29 */
30#include <asm-generic/io-64-nonatomic-hi-lo.h>
31
4d88a97a
DW		 32static bool force_enable_dimms;
33module_param(force_enable_dimms, bool, S_IRUGO|S_IWUSR);
34MODULE_PARM_DESC(force_enable_dimms, "Ignore _STA (ACPI DIMM device) status");
35
b94d5230
DW		 36static u8 nfit_uuid[NFIT_UUID_MAX][16];
37
6bc75619 38const u8 *to_nfit_uuid(enum nfit_uuids id)
b94d5230
DW		 39{
40 return nfit_uuid[id];
41}
6bc75619 42EXPORT_SYMBOL(to_nfit_uuid);
b94d5230 43
62232e45
DW		 44static struct acpi_nfit_desc *to_acpi_nfit_desc(
45 struct nvdimm_bus_descriptor *nd_desc)
46{
47 return container_of(nd_desc, struct acpi_nfit_desc, nd_desc);
48}
49
50static struct acpi_device *to_acpi_dev(struct acpi_nfit_desc *acpi_desc)
51{
52 struct nvdimm_bus_descriptor *nd_desc = &acpi_desc->nd_desc;
53
54 /*
55 * If provider == 'ACPI.NFIT' we can assume 'dev' is a struct
56 * acpi_device.
57 */
58 if (!nd_desc->provider_name
59 || strcmp(nd_desc->provider_name, "ACPI.NFIT") != 0)
60 return NULL;
61
62 return to_acpi_device(acpi_desc->dev);
63}
64
b94d5230
DW		 65static int acpi_nfit_ctl(struct nvdimm_bus_descriptor *nd_desc,
66 struct nvdimm *nvdimm, unsigned int cmd, void *buf,
67 unsigned int buf_len)
68{
62232e45
DW		 69 struct acpi_nfit_desc *acpi_desc = to_acpi_nfit_desc(nd_desc);
70 const struct nd_cmd_desc *desc = NULL;
71 union acpi_object in_obj, in_buf, *out_obj;
72 struct device *dev = acpi_desc->dev;
73 const char *cmd_name, *dimm_name;
74 unsigned long dsm_mask;
75 acpi_handle handle;
76 const u8 *uuid;
77 u32 offset;
78 int rc, i;
79
80 if (nvdimm) {
81 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
82 struct acpi_device *adev = nfit_mem->adev;
83
84 if (!adev)
85 return -ENOTTY;
047fc8a1 86 dimm_name = nvdimm_name(nvdimm);
62232e45
DW		 87 cmd_name = nvdimm_cmd_name(cmd);
88 dsm_mask = nfit_mem->dsm_mask;
89 desc = nd_cmd_dimm_desc(cmd);
90 uuid = to_nfit_uuid(NFIT_DEV_DIMM);
91 handle = adev->handle;
92 } else {
93 struct acpi_device *adev = to_acpi_dev(acpi_desc);
94
95 cmd_name = nvdimm_bus_cmd_name(cmd);
96 dsm_mask = nd_desc->dsm_mask;
97 desc = nd_cmd_bus_desc(cmd);
98 uuid = to_nfit_uuid(NFIT_DEV_BUS);
99 handle = adev->handle;
100 dimm_name = "bus";
101 }
102
103 if (!desc || (cmd && (desc->out_num + desc->in_num == 0)))
104 return -ENOTTY;
105
106 if (!test_bit(cmd, &dsm_mask))
107 return -ENOTTY;
108
109 in_obj.type = ACPI_TYPE_PACKAGE;
110 in_obj.package.count = 1;
111 in_obj.package.elements = &in_buf;
112 in_buf.type = ACPI_TYPE_BUFFER;
113 in_buf.buffer.pointer = buf;
114 in_buf.buffer.length = 0;
115
116 /* libnvdimm has already validated the input envelope */
117 for (i = 0; i < desc->in_num; i++)
118 in_buf.buffer.length += nd_cmd_in_size(nvdimm, cmd, desc,
119 i, buf);
120
121 if (IS_ENABLED(CONFIG_ACPI_NFIT_DEBUG)) {
122 dev_dbg(dev, "%s:%s cmd: %s input length: %d\n", __func__,
123 dimm_name, cmd_name, in_buf.buffer.length);
124 print_hex_dump_debug(cmd_name, DUMP_PREFIX_OFFSET, 4,
125 4, in_buf.buffer.pointer, min_t(u32, 128,
126 in_buf.buffer.length), true);
127 }
128
129 out_obj = acpi_evaluate_dsm(handle, uuid, 1, cmd, &in_obj);
130 if (!out_obj) {
131 dev_dbg(dev, "%s:%s _DSM failed cmd: %s\n", __func__, dimm_name,
132 cmd_name);
133 return -EINVAL;
134 }
135
136 if (out_obj->package.type != ACPI_TYPE_BUFFER) {
137 dev_dbg(dev, "%s:%s unexpected output object type cmd: %s type: %d\n",
138 __func__, dimm_name, cmd_name, out_obj->type);
139 rc = -EINVAL;
140 goto out;
141 }
142
143 if (IS_ENABLED(CONFIG_ACPI_NFIT_DEBUG)) {
144 dev_dbg(dev, "%s:%s cmd: %s output length: %d\n", __func__,
145 dimm_name, cmd_name, out_obj->buffer.length);
146 print_hex_dump_debug(cmd_name, DUMP_PREFIX_OFFSET, 4,
147 4, out_obj->buffer.pointer, min_t(u32, 128,
148 out_obj->buffer.length), true);
149 }
150
151 for (i = 0, offset = 0; i < desc->out_num; i++) {
152 u32 out_size = nd_cmd_out_size(nvdimm, cmd, desc, i, buf,
153 (u32 *) out_obj->buffer.pointer);
154
155 if (offset + out_size > out_obj->buffer.length) {
156 dev_dbg(dev, "%s:%s output object underflow cmd: %s field: %d\n",
157 __func__, dimm_name, cmd_name, i);
158 break;
159 }
160
161 if (in_buf.buffer.length + offset + out_size > buf_len) {
162 dev_dbg(dev, "%s:%s output overrun cmd: %s field: %d\n",
163 __func__, dimm_name, cmd_name, i);
164 rc = -ENXIO;
165 goto out;
166 }
167 memcpy(buf + in_buf.buffer.length + offset,
168 out_obj->buffer.pointer + offset, out_size);
169 offset += out_size;
170 }
171 if (offset + in_buf.buffer.length < buf_len) {
172 if (i >= 1) {
173 /*
174 * status valid, return the number of bytes left
175 * unfilled in the output buffer
176 */
177 rc = buf_len - offset - in_buf.buffer.length;
178 } else {
179 dev_err(dev, "%s:%s underrun cmd: %s buf_len: %d out_len: %d\n",
180 __func__, dimm_name, cmd_name, buf_len,
181 offset);
182 rc = -ENXIO;
183 }
184 } else
185 rc = 0;
186
187 out:
188 ACPI_FREE(out_obj);
189
190 return rc;
b94d5230
DW		 191}
192
193static const char *spa_type_name(u16 type)
194{
195 static const char *to_name[] = {
196 [NFIT_SPA_VOLATILE] = "volatile",
197 [NFIT_SPA_PM] = "pmem",
198 [NFIT_SPA_DCR] = "dimm-control-region",
199 [NFIT_SPA_BDW] = "block-data-window",
200 [NFIT_SPA_VDISK] = "volatile-disk",
201 [NFIT_SPA_VCD] = "volatile-cd",
202 [NFIT_SPA_PDISK] = "persistent-disk",
203 [NFIT_SPA_PCD] = "persistent-cd",
204
205 };
206
207 if (type > NFIT_SPA_PCD)
208 return "unknown";
209
210 return to_name[type];
211}
212
213static int nfit_spa_type(struct acpi_nfit_system_address *spa)
214{
215 int i;
216
217 for (i = 0; i < NFIT_UUID_MAX; i++)
218 if (memcmp(to_nfit_uuid(i), spa->range_guid, 16) == 0)
219 return i;
220 return -1;
221}
222
223static bool add_spa(struct acpi_nfit_desc *acpi_desc,
224 struct acpi_nfit_system_address *spa)
225{
226 struct device *dev = acpi_desc->dev;
227 struct nfit_spa *nfit_spa = devm_kzalloc(dev, sizeof(*nfit_spa),
228 GFP_KERNEL);
229
230 if (!nfit_spa)
231 return false;
232 INIT_LIST_HEAD(&nfit_spa->list);
233 nfit_spa->spa = spa;
234 list_add_tail(&nfit_spa->list, &acpi_desc->spas);
235 dev_dbg(dev, "%s: spa index: %d type: %s\n", __func__,
236 spa->range_index,
237 spa_type_name(nfit_spa_type(spa)));
238 return true;
239}
240
241static bool add_memdev(struct acpi_nfit_desc *acpi_desc,
242 struct acpi_nfit_memory_map *memdev)
243{
244 struct device *dev = acpi_desc->dev;
245 struct nfit_memdev *nfit_memdev = devm_kzalloc(dev,
246 sizeof(*nfit_memdev), GFP_KERNEL);
247
248 if (!nfit_memdev)
249 return false;
250 INIT_LIST_HEAD(&nfit_memdev->list);
251 nfit_memdev->memdev = memdev;
252 list_add_tail(&nfit_memdev->list, &acpi_desc->memdevs);
253 dev_dbg(dev, "%s: memdev handle: %#x spa: %d dcr: %d\n",
254 __func__, memdev->device_handle, memdev->range_index,
255 memdev->region_index);
256 return true;
257}
258
259static bool add_dcr(struct acpi_nfit_desc *acpi_desc,
260 struct acpi_nfit_control_region *dcr)
261{
262 struct device *dev = acpi_desc->dev;
263 struct nfit_dcr *nfit_dcr = devm_kzalloc(dev, sizeof(*nfit_dcr),
264 GFP_KERNEL);
265
266 if (!nfit_dcr)
267 return false;
268 INIT_LIST_HEAD(&nfit_dcr->list);
269 nfit_dcr->dcr = dcr;
270 list_add_tail(&nfit_dcr->list, &acpi_desc->dcrs);
271 dev_dbg(dev, "%s: dcr index: %d windows: %d\n", __func__,
272 dcr->region_index, dcr->windows);
273 return true;
274}
275
276static bool add_bdw(struct acpi_nfit_desc *acpi_desc,
277 struct acpi_nfit_data_region *bdw)
278{
279 struct device *dev = acpi_desc->dev;
280 struct nfit_bdw *nfit_bdw = devm_kzalloc(dev, sizeof(*nfit_bdw),
281 GFP_KERNEL);
282
283 if (!nfit_bdw)
284 return false;
285 INIT_LIST_HEAD(&nfit_bdw->list);
286 nfit_bdw->bdw = bdw;
287 list_add_tail(&nfit_bdw->list, &acpi_desc->bdws);
288 dev_dbg(dev, "%s: bdw dcr: %d windows: %d\n", __func__,
289 bdw->region_index, bdw->windows);
290 return true;
291}
292
047fc8a1
RZ		 293static bool add_idt(struct acpi_nfit_desc *acpi_desc,
294 struct acpi_nfit_interleave *idt)
295{
296 struct device *dev = acpi_desc->dev;
297 struct nfit_idt *nfit_idt = devm_kzalloc(dev, sizeof(*nfit_idt),
298 GFP_KERNEL);
299
300 if (!nfit_idt)
301 return false;
302 INIT_LIST_HEAD(&nfit_idt->list);
303 nfit_idt->idt = idt;
304 list_add_tail(&nfit_idt->list, &acpi_desc->idts);
305 dev_dbg(dev, "%s: idt index: %d num_lines: %d\n", __func__,
306 idt->interleave_index, idt->line_count);
307 return true;
308}
309
c2ad2954
RZ		 310static bool add_flush(struct acpi_nfit_desc *acpi_desc,
311 struct acpi_nfit_flush_address *flush)
312{
313 struct device *dev = acpi_desc->dev;
314 struct nfit_flush *nfit_flush = devm_kzalloc(dev, sizeof(*nfit_flush),
315 GFP_KERNEL);
316
317 if (!nfit_flush)
318 return false;
319 INIT_LIST_HEAD(&nfit_flush->list);
320 nfit_flush->flush = flush;
321 list_add_tail(&nfit_flush->list, &acpi_desc->flushes);
322 dev_dbg(dev, "%s: nfit_flush handle: %d hint_count: %d\n", __func__,
323 flush->device_handle, flush->hint_count);
324 return true;
325}
326
b94d5230
DW		 327static void *add_table(struct acpi_nfit_desc *acpi_desc, void *table,
328 const void *end)
329{
330 struct device *dev = acpi_desc->dev;
331 struct acpi_nfit_header *hdr;
332 void *err = ERR_PTR(-ENOMEM);
333
334 if (table >= end)
335 return NULL;
336
337 hdr = table;
564d5011
VV		 338 if (!hdr->length) {
339 dev_warn(dev, "found a zero length table '%d' parsing nfit\n",
340 hdr->type);
341 return NULL;
342 }
343
b94d5230
DW		 344 switch (hdr->type) {
345 case ACPI_NFIT_TYPE_SYSTEM_ADDRESS:
346 if (!add_spa(acpi_desc, table))
347 return err;
348 break;
349 case ACPI_NFIT_TYPE_MEMORY_MAP:
350 if (!add_memdev(acpi_desc, table))
351 return err;
352 break;
353 case ACPI_NFIT_TYPE_CONTROL_REGION:
354 if (!add_dcr(acpi_desc, table))
355 return err;
356 break;
357 case ACPI_NFIT_TYPE_DATA_REGION:
358 if (!add_bdw(acpi_desc, table))
359 return err;
360 break;
b94d5230 361 case ACPI_NFIT_TYPE_INTERLEAVE:
047fc8a1
RZ		 362 if (!add_idt(acpi_desc, table))
363 return err;
b94d5230
DW		 364 break;
365 case ACPI_NFIT_TYPE_FLUSH_ADDRESS:
c2ad2954
RZ		 366 if (!add_flush(acpi_desc, table))
367 return err;
b94d5230
DW		 368 break;
369 case ACPI_NFIT_TYPE_SMBIOS:
370 dev_dbg(dev, "%s: smbios\n", __func__);
371 break;
372 default:
373 dev_err(dev, "unknown table '%d' parsing nfit\n", hdr->type);
374 break;
375 }
376
377 return table + hdr->length;
378}
379
380static void nfit_mem_find_spa_bdw(struct acpi_nfit_desc *acpi_desc,
381 struct nfit_mem *nfit_mem)
382{
383 u32 device_handle = __to_nfit_memdev(nfit_mem)->device_handle;
384 u16 dcr = nfit_mem->dcr->region_index;
385 struct nfit_spa *nfit_spa;
386
387 list_for_each_entry(nfit_spa, &acpi_desc->spas, list) {
388 u16 range_index = nfit_spa->spa->range_index;
389 int type = nfit_spa_type(nfit_spa->spa);
390 struct nfit_memdev *nfit_memdev;
391
392 if (type != NFIT_SPA_BDW)
393 continue;
394
395 list_for_each_entry(nfit_memdev, &acpi_desc->memdevs, list) {
396 if (nfit_memdev->memdev->range_index != range_index)
397 continue;
398 if (nfit_memdev->memdev->device_handle != device_handle)
399 continue;
400 if (nfit_memdev->memdev->region_index != dcr)
401 continue;
402
403 nfit_mem->spa_bdw = nfit_spa->spa;
404 return;
405 }
406 }
407
408 dev_dbg(acpi_desc->dev, "SPA-BDW not found for SPA-DCR %d\n",
409 nfit_mem->spa_dcr->range_index);
410 nfit_mem->bdw = NULL;
411}
412
413static int nfit_mem_add(struct acpi_nfit_desc *acpi_desc,
414 struct nfit_mem *nfit_mem, struct acpi_nfit_system_address *spa)
415{
416 u16 dcr = __to_nfit_memdev(nfit_mem)->region_index;
047fc8a1 417 struct nfit_memdev *nfit_memdev;
c2ad2954 418 struct nfit_flush *nfit_flush;
b94d5230
DW		 419 struct nfit_dcr *nfit_dcr;
420 struct nfit_bdw *nfit_bdw;
047fc8a1
RZ		 421 struct nfit_idt *nfit_idt;
422 u16 idt_idx, range_index;
b94d5230
DW		 423
424 list_for_each_entry(nfit_dcr, &acpi_desc->dcrs, list) {
425 if (nfit_dcr->dcr->region_index != dcr)
426 continue;
427 nfit_mem->dcr = nfit_dcr->dcr;
428 break;
429 }
430
431 if (!nfit_mem->dcr) {
432 dev_dbg(acpi_desc->dev, "SPA %d missing:%s%s\n",
433 spa->range_index, __to_nfit_memdev(nfit_mem)
434 ? "" : " MEMDEV", nfit_mem->dcr ? "" : " DCR");
435 return -ENODEV;
436 }
437
438 /*
439 * We've found enough to create an nvdimm, optionally
440 * find an associated BDW
441 */
442 list_add(&nfit_mem->list, &acpi_desc->dimms);
443
444 list_for_each_entry(nfit_bdw, &acpi_desc->bdws, list) {
445 if (nfit_bdw->bdw->region_index != dcr)
446 continue;
447 nfit_mem->bdw = nfit_bdw->bdw;
448 break;
449 }
450
451 if (!nfit_mem->bdw)
452 return 0;
453
454 nfit_mem_find_spa_bdw(acpi_desc, nfit_mem);
047fc8a1
RZ		 455
456 if (!nfit_mem->spa_bdw)
457 return 0;
458
459 range_index = nfit_mem->spa_bdw->range_index;
460 list_for_each_entry(nfit_memdev, &acpi_desc->memdevs, list) {
461 if (nfit_memdev->memdev->range_index != range_index ||
462 nfit_memdev->memdev->region_index != dcr)
463 continue;
464 nfit_mem->memdev_bdw = nfit_memdev->memdev;
465 idt_idx = nfit_memdev->memdev->interleave_index;
466 list_for_each_entry(nfit_idt, &acpi_desc->idts, list) {
467 if (nfit_idt->idt->interleave_index != idt_idx)
468 continue;
469 nfit_mem->idt_bdw = nfit_idt->idt;
470 break;
471 }
c2ad2954
RZ		 472
473 list_for_each_entry(nfit_flush, &acpi_desc->flushes, list) {
474 if (nfit_flush->flush->device_handle !=
475 nfit_memdev->memdev->device_handle)
476 continue;
477 nfit_mem->nfit_flush = nfit_flush;
478 break;
479 }
047fc8a1
RZ		 480 break;
481 }
482
b94d5230
DW		 483 return 0;
484}
485
486static int nfit_mem_dcr_init(struct acpi_nfit_desc *acpi_desc,
487 struct acpi_nfit_system_address *spa)
488{
489 struct nfit_mem *nfit_mem, *found;
490 struct nfit_memdev *nfit_memdev;
491 int type = nfit_spa_type(spa);
492 u16 dcr;
493
494 switch (type) {
495 case NFIT_SPA_DCR:
496 case NFIT_SPA_PM:
497 break;
498 default:
499 return 0;
500 }
501
502 list_for_each_entry(nfit_memdev, &acpi_desc->memdevs, list) {
503 int rc;
504
505 if (nfit_memdev->memdev->range_index != spa->range_index)
506 continue;
507 found = NULL;
508 dcr = nfit_memdev->memdev->region_index;
509 list_for_each_entry(nfit_mem, &acpi_desc->dimms, list)
510 if (__to_nfit_memdev(nfit_mem)->region_index == dcr) {
511 found = nfit_mem;
512 break;
513 }
514
515 if (found)
516 nfit_mem = found;
517 else {
518 nfit_mem = devm_kzalloc(acpi_desc->dev,
519 sizeof(*nfit_mem), GFP_KERNEL);
520 if (!nfit_mem)
521 return -ENOMEM;
522 INIT_LIST_HEAD(&nfit_mem->list);
523 }
524
525 if (type == NFIT_SPA_DCR) {
047fc8a1
RZ		 526 struct nfit_idt *nfit_idt;
527 u16 idt_idx;
528
b94d5230
DW		 529 /* multiple dimms may share a SPA when interleaved */
530 nfit_mem->spa_dcr = spa;
531 nfit_mem->memdev_dcr = nfit_memdev->memdev;
047fc8a1
RZ		 532 idt_idx = nfit_memdev->memdev->interleave_index;
533 list_for_each_entry(nfit_idt, &acpi_desc->idts, list) {
534 if (nfit_idt->idt->interleave_index != idt_idx)
535 continue;
536 nfit_mem->idt_dcr = nfit_idt->idt;
537 break;
538 }
b94d5230
DW		 539 } else {
540 /*
541 * A single dimm may belong to multiple SPA-PM
542 * ranges, record at least one in addition to
543 * any SPA-DCR range.
544 */
545 nfit_mem->memdev_pmem = nfit_memdev->memdev;
546 }
547
548 if (found)
549 continue;
550
551 rc = nfit_mem_add(acpi_desc, nfit_mem, spa);
552 if (rc)
553 return rc;
554 }
555
556 return 0;
557}
558
559static int nfit_mem_cmp(void *priv, struct list_head *_a, struct list_head *_b)
560{
561 struct nfit_mem *a = container_of(_a, typeof(*a), list);
562 struct nfit_mem *b = container_of(_b, typeof(*b), list);
563 u32 handleA, handleB;
564
565 handleA = __to_nfit_memdev(a)->device_handle;
566 handleB = __to_nfit_memdev(b)->device_handle;
567 if (handleA < handleB)
568 return -1;
569 else if (handleA > handleB)
570 return 1;
571 return 0;
572}
573
574static int nfit_mem_init(struct acpi_nfit_desc *acpi_desc)
575{
576 struct nfit_spa *nfit_spa;
577
578 /*
579 * For each SPA-DCR or SPA-PMEM address range find its
580 * corresponding MEMDEV(s). From each MEMDEV find the
581 * corresponding DCR. Then, if we're operating on a SPA-DCR,
582 * try to find a SPA-BDW and a corresponding BDW that references
583 * the DCR. Throw it all into an nfit_mem object. Note, that
584 * BDWs are optional.
585 */
586 list_for_each_entry(nfit_spa, &acpi_desc->spas, list) {
587 int rc;
588
589 rc = nfit_mem_dcr_init(acpi_desc, nfit_spa->spa);
590 if (rc)
591 return rc;
592 }
593
594 list_sort(NULL, &acpi_desc->dimms, nfit_mem_cmp);
595
596 return 0;
597}
598
45def22c
DW		 599static ssize_t revision_show(struct device *dev,
600 struct device_attribute *attr, char *buf)
601{
602 struct nvdimm_bus *nvdimm_bus = to_nvdimm_bus(dev);
603 struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus);
604 struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
605
606 return sprintf(buf, "%d\n", acpi_desc->nfit->header.revision);
607}
608static DEVICE_ATTR_RO(revision);
609
610static struct attribute *acpi_nfit_attributes[] = {
611 &dev_attr_revision.attr,
612 NULL,
613};
614
615static struct attribute_group acpi_nfit_attribute_group = {
616 .name = "nfit",
617 .attrs = acpi_nfit_attributes,
618};
619
6bc75619 620const struct attribute_group *acpi_nfit_attribute_groups[] = {
45def22c
DW		 621 &nvdimm_bus_attribute_group,
622 &acpi_nfit_attribute_group,
623 NULL,
624};
6bc75619 625EXPORT_SYMBOL_GPL(acpi_nfit_attribute_groups);
45def22c 626
e6dfb2de
DW		 627static struct acpi_nfit_memory_map *to_nfit_memdev(struct device *dev)
628{
629 struct nvdimm *nvdimm = to_nvdimm(dev);
630 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
631
632 return __to_nfit_memdev(nfit_mem);
633}
634
635static struct acpi_nfit_control_region *to_nfit_dcr(struct device *dev)
636{
637 struct nvdimm *nvdimm = to_nvdimm(dev);
638 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
639
640 return nfit_mem->dcr;
641}
642
643static ssize_t handle_show(struct device *dev,
644 struct device_attribute *attr, char *buf)
645{
646 struct acpi_nfit_memory_map *memdev = to_nfit_memdev(dev);
647
648 return sprintf(buf, "%#x\n", memdev->device_handle);
649}
650static DEVICE_ATTR_RO(handle);
651
652static ssize_t phys_id_show(struct device *dev,
653 struct device_attribute *attr, char *buf)
654{
655 struct acpi_nfit_memory_map *memdev = to_nfit_memdev(dev);
656
657 return sprintf(buf, "%#x\n", memdev->physical_id);
658}
659static DEVICE_ATTR_RO(phys_id);
660
661static ssize_t vendor_show(struct device *dev,
662 struct device_attribute *attr, char *buf)
663{
664 struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);
665
666 return sprintf(buf, "%#x\n", dcr->vendor_id);
667}
668static DEVICE_ATTR_RO(vendor);
669
670static ssize_t rev_id_show(struct device *dev,
671 struct device_attribute *attr, char *buf)
672{
673 struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);
674
675 return sprintf(buf, "%#x\n", dcr->revision_id);
676}
677static DEVICE_ATTR_RO(rev_id);
678
679static ssize_t device_show(struct device *dev,
680 struct device_attribute *attr, char *buf)
681{
682 struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);
683
684 return sprintf(buf, "%#x\n", dcr->device_id);
685}
686static DEVICE_ATTR_RO(device);
687
688static ssize_t format_show(struct device *dev,
689 struct device_attribute *attr, char *buf)
690{
691 struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);
692
693 return sprintf(buf, "%#x\n", dcr->code);
694}
695static DEVICE_ATTR_RO(format);
696
697static ssize_t serial_show(struct device *dev,
698 struct device_attribute *attr, char *buf)
699{
700 struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);
701
702 return sprintf(buf, "%#x\n", dcr->serial_number);
703}
704static DEVICE_ATTR_RO(serial);
705
58138820
DW		 706static ssize_t flags_show(struct device *dev,
707 struct device_attribute *attr, char *buf)
708{
709 u16 flags = to_nfit_memdev(dev)->flags;
710
711 return sprintf(buf, "%s%s%s%s%s\n",
402bae59
TK		 712 flags & ACPI_NFIT_MEM_SAVE_FAILED ? "save_fail " : "",
713 flags & ACPI_NFIT_MEM_RESTORE_FAILED ? "restore_fail " : "",
714 flags & ACPI_NFIT_MEM_FLUSH_FAILED ? "flush_fail " : "",
715 flags & ACPI_NFIT_MEM_ARMED ? "not_armed " : "",
716 flags & ACPI_NFIT_MEM_HEALTH_OBSERVED ? "smart_event " : "");
58138820
DW		 717}
718static DEVICE_ATTR_RO(flags);
719
e6dfb2de
DW		 720static struct attribute *acpi_nfit_dimm_attributes[] = {
721 &dev_attr_handle.attr,
722 &dev_attr_phys_id.attr,
723 &dev_attr_vendor.attr,
724 &dev_attr_device.attr,
725 &dev_attr_format.attr,
726 &dev_attr_serial.attr,
727 &dev_attr_rev_id.attr,
58138820 728 &dev_attr_flags.attr,
e6dfb2de
DW		 729 NULL,
730};
731
732static umode_t acpi_nfit_dimm_attr_visible(struct kobject *kobj,
733 struct attribute *a, int n)
734{
735 struct device *dev = container_of(kobj, struct device, kobj);
736
737 if (to_nfit_dcr(dev))
738 return a->mode;
739 else
740 return 0;
741}
742
743static struct attribute_group acpi_nfit_dimm_attribute_group = {
744 .name = "nfit",
745 .attrs = acpi_nfit_dimm_attributes,
746 .is_visible = acpi_nfit_dimm_attr_visible,
747};
748
749static const struct attribute_group *acpi_nfit_dimm_attribute_groups[] = {
62232e45 750 &nvdimm_attribute_group,
4d88a97a 751 &nd_device_attribute_group,
e6dfb2de
DW		 752 &acpi_nfit_dimm_attribute_group,
753 NULL,
754};
755
756static struct nvdimm *acpi_nfit_dimm_by_handle(struct acpi_nfit_desc *acpi_desc,
757 u32 device_handle)
758{
759 struct nfit_mem *nfit_mem;
760
761 list_for_each_entry(nfit_mem, &acpi_desc->dimms, list)
762 if (__to_nfit_memdev(nfit_mem)->device_handle == device_handle)
763 return nfit_mem->nvdimm;
764
765 return NULL;
766}
767
62232e45
DW		 768static int acpi_nfit_add_dimm(struct acpi_nfit_desc *acpi_desc,
769 struct nfit_mem *nfit_mem, u32 device_handle)
770{
771 struct acpi_device *adev, *adev_dimm;
772 struct device *dev = acpi_desc->dev;
773 const u8 *uuid = to_nfit_uuid(NFIT_DEV_DIMM);
60e95f43 774 int i;
62232e45
DW		 775
776 nfit_mem->dsm_mask = acpi_desc->dimm_dsm_force_en;
777 adev = to_acpi_dev(acpi_desc);
778 if (!adev)
779 return 0;
780
781 adev_dimm = acpi_find_child_device(adev, device_handle, false);
782 nfit_mem->adev = adev_dimm;
783 if (!adev_dimm) {
784 dev_err(dev, "no ACPI.NFIT device with _ADR %#x, disabling...\n",
785 device_handle);
4d88a97a 786 return force_enable_dimms ? 0 : -ENODEV;
62232e45
DW		 787 }
788
62232e45
DW		 789 for (i = ND_CMD_SMART; i <= ND_CMD_VENDOR; i++)
790 if (acpi_check_dsm(adev_dimm->handle, uuid, 1, 1ULL << i))
791 set_bit(i, &nfit_mem->dsm_mask);
792
60e95f43 793 return 0;
62232e45
DW		 794}
795
e6dfb2de
DW		 796static int acpi_nfit_register_dimms(struct acpi_nfit_desc *acpi_desc)
797{
798 struct nfit_mem *nfit_mem;
4d88a97a 799 int dimm_count = 0;
e6dfb2de
DW		 800
801 list_for_each_entry(nfit_mem, &acpi_desc->dimms, list) {
802 struct nvdimm *nvdimm;
803 unsigned long flags = 0;
804 u32 device_handle;
58138820 805 u16 mem_flags;
62232e45 806 int rc;
e6dfb2de
DW		 807
808 device_handle = __to_nfit_memdev(nfit_mem)->device_handle;
809 nvdimm = acpi_nfit_dimm_by_handle(acpi_desc, device_handle);
810 if (nvdimm) {
811 /*
812 * If for some reason we find multiple DCRs the
813 * first one wins
814 */
815 dev_err(acpi_desc->dev, "duplicate DCR detected: %s\n",
816 nvdimm_name(nvdimm));
817 continue;
818 }
819
820 if (nfit_mem->bdw && nfit_mem->memdev_pmem)
821 flags |= NDD_ALIASING;
822
58138820
DW		 823 mem_flags = __to_nfit_memdev(nfit_mem)->flags;
824 if (mem_flags & ACPI_NFIT_MEM_ARMED)
825 flags |= NDD_UNARMED;
826
62232e45
DW		 827 rc = acpi_nfit_add_dimm(acpi_desc, nfit_mem, device_handle);
828 if (rc)
829 continue;
830
e6dfb2de 831 nvdimm = nvdimm_create(acpi_desc->nvdimm_bus, nfit_mem,
62232e45
DW		 832 acpi_nfit_dimm_attribute_groups,
833 flags, &nfit_mem->dsm_mask);
e6dfb2de
DW		 834 if (!nvdimm)
835 return -ENOMEM;
836
837 nfit_mem->nvdimm = nvdimm;
4d88a97a 838 dimm_count++;
58138820
DW		 839
840 if ((mem_flags & ACPI_NFIT_MEM_FAILED_MASK) == 0)
841 continue;
842
402bae59 843 dev_info(acpi_desc->dev, "%s flags:%s%s%s%s\n",
58138820 844 nvdimm_name(nvdimm),
402bae59
TK		 845 mem_flags & ACPI_NFIT_MEM_SAVE_FAILED ? " save_fail" : "",
846 mem_flags & ACPI_NFIT_MEM_RESTORE_FAILED ? " restore_fail":"",
847 mem_flags & ACPI_NFIT_MEM_FLUSH_FAILED ? " flush_fail" : "",
848 mem_flags & ACPI_NFIT_MEM_ARMED ? " not_armed" : "");
58138820 849
e6dfb2de
DW		 850 }
851
4d88a97a 852 return nvdimm_bus_check_dimm_count(acpi_desc->nvdimm_bus, dimm_count);
e6dfb2de
DW		 853}
854
62232e45
DW		 855static void acpi_nfit_init_dsms(struct acpi_nfit_desc *acpi_desc)
856{
857 struct nvdimm_bus_descriptor *nd_desc = &acpi_desc->nd_desc;
858 const u8 *uuid = to_nfit_uuid(NFIT_DEV_BUS);
859 struct acpi_device *adev;
860 int i;
861
39c686b8 862 nd_desc->dsm_mask = acpi_desc->bus_dsm_force_en;
62232e45
DW		 863 adev = to_acpi_dev(acpi_desc);
864 if (!adev)
865 return;
866
867 for (i = ND_CMD_ARS_CAP; i <= ND_CMD_ARS_STATUS; i++)
868 if (acpi_check_dsm(adev->handle, uuid, 1, 1ULL << i))
869 set_bit(i, &nd_desc->dsm_mask);
870}
871
1f7df6f8
DW		 872static ssize_t range_index_show(struct device *dev,
873 struct device_attribute *attr, char *buf)
874{
875 struct nd_region *nd_region = to_nd_region(dev);
876 struct nfit_spa *nfit_spa = nd_region_provider_data(nd_region);
877
878 return sprintf(buf, "%d\n", nfit_spa->spa->range_index);
879}
880static DEVICE_ATTR_RO(range_index);
881
882static struct attribute *acpi_nfit_region_attributes[] = {
883 &dev_attr_range_index.attr,
884 NULL,
885};
886
887static struct attribute_group acpi_nfit_region_attribute_group = {
888 .name = "nfit",
889 .attrs = acpi_nfit_region_attributes,
890};
891
892static const struct attribute_group *acpi_nfit_region_attribute_groups[] = {
893 &nd_region_attribute_group,
894 &nd_mapping_attribute_group,
3d88002e 895 &nd_device_attribute_group,
74ae66c3 896 &nd_numa_attribute_group,
1f7df6f8
DW		 897 &acpi_nfit_region_attribute_group,
898 NULL,
899};
900
eaf96153
DW		 901/* enough info to uniquely specify an interleave set */
902struct nfit_set_info {
903 struct nfit_set_info_map {
904 u64 region_offset;
905 u32 serial_number;
906 u32 pad;
907 } mapping[0];
908};
909
910static size_t sizeof_nfit_set_info(int num_mappings)
911{
912 return sizeof(struct nfit_set_info)
913 + num_mappings * sizeof(struct nfit_set_info_map);
914}
915
916static int cmp_map(const void *m0, const void *m1)
917{
918 const struct nfit_set_info_map *map0 = m0;
919 const struct nfit_set_info_map *map1 = m1;
920
921 return memcmp(&map0->region_offset, &map1->region_offset,
922 sizeof(u64));
923}
924
925/* Retrieve the nth entry referencing this spa */
926static struct acpi_nfit_memory_map *memdev_from_spa(
927 struct acpi_nfit_desc *acpi_desc, u16 range_index, int n)
928{
929 struct nfit_memdev *nfit_memdev;
930
931 list_for_each_entry(nfit_memdev, &acpi_desc->memdevs, list)
932 if (nfit_memdev->memdev->range_index == range_index)
933 if (n-- == 0)
934 return nfit_memdev->memdev;
935 return NULL;
936}
937
938static int acpi_nfit_init_interleave_set(struct acpi_nfit_desc *acpi_desc,
939 struct nd_region_desc *ndr_desc,
940 struct acpi_nfit_system_address *spa)
941{
942 int i, spa_type = nfit_spa_type(spa);
943 struct device *dev = acpi_desc->dev;
944 struct nd_interleave_set *nd_set;
945 u16 nr = ndr_desc->num_mappings;
946 struct nfit_set_info *info;
947
948 if (spa_type == NFIT_SPA_PM || spa_type == NFIT_SPA_VOLATILE)
949 /* pass */;
950 else
951 return 0;
952
953 nd_set = devm_kzalloc(dev, sizeof(*nd_set), GFP_KERNEL);
954 if (!nd_set)
955 return -ENOMEM;
956
957 info = devm_kzalloc(dev, sizeof_nfit_set_info(nr), GFP_KERNEL);
958 if (!info)
959 return -ENOMEM;
960 for (i = 0; i < nr; i++) {
961 struct nd_mapping *nd_mapping = &ndr_desc->nd_mapping[i];
962 struct nfit_set_info_map *map = &info->mapping[i];
963 struct nvdimm *nvdimm = nd_mapping->nvdimm;
964 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
965 struct acpi_nfit_memory_map *memdev = memdev_from_spa(acpi_desc,
966 spa->range_index, i);
967
968 if (!memdev || !nfit_mem->dcr) {
969 dev_err(dev, "%s: failed to find DCR\n", __func__);
970 return -ENODEV;
971 }
972
973 map->region_offset = memdev->region_offset;
974 map->serial_number = nfit_mem->dcr->serial_number;
975 }
976
977 sort(&info->mapping[0], nr, sizeof(struct nfit_set_info_map),
978 cmp_map, NULL);
979 nd_set->cookie = nd_fletcher64(info, sizeof_nfit_set_info(nr), 0);
980 ndr_desc->nd_set = nd_set;
981 devm_kfree(dev, info);
982
983 return 0;
984}
985
047fc8a1
RZ		 986static u64 to_interleave_offset(u64 offset, struct nfit_blk_mmio *mmio)
987{
988 struct acpi_nfit_interleave *idt = mmio->idt;
989 u32 sub_line_offset, line_index, line_offset;
990 u64 line_no, table_skip_count, table_offset;
991
992 line_no = div_u64_rem(offset, mmio->line_size, &sub_line_offset);
993 table_skip_count = div_u64_rem(line_no, mmio->num_lines, &line_index);
994 line_offset = idt->line_offset[line_index]
995 * mmio->line_size;
996 table_offset = table_skip_count * mmio->table_size;
997
998 return mmio->base_offset + line_offset + table_offset + sub_line_offset;
999}
1000
c2ad2954
RZ		 1001static void wmb_blk(struct nfit_blk *nfit_blk)
1002{
1003
1004 if (nfit_blk->nvdimm_flush) {
1005 /*
1006 * The first wmb() is needed to 'sfence' all previous writes
1007 * such that they are architecturally visible for the platform
1008 * buffer flush. Note that we've already arranged for pmem
1009 * writes to avoid the cache via arch_memcpy_to_pmem(). The
1010 * final wmb() ensures ordering for the NVDIMM flush write.
1011 */
1012 wmb();
1013 writeq(1, nfit_blk->nvdimm_flush);
1014 wmb();
1015 } else
1016 wmb_pmem();
1017}
1018
de4a196c 1019static u32 read_blk_stat(struct nfit_blk *nfit_blk, unsigned int bw)
047fc8a1
RZ		 1020{
1021 struct nfit_blk_mmio *mmio = &nfit_blk->mmio[DCR];
1022 u64 offset = nfit_blk->stat_offset + mmio->size * bw;
1023
1024 if (mmio->num_lines)
1025 offset = to_interleave_offset(offset, mmio);
1026
12f03ee6 1027 return readl(mmio->addr.base + offset);
047fc8a1
RZ		 1028}
1029
1030static void write_blk_ctl(struct nfit_blk *nfit_blk, unsigned int bw,
1031 resource_size_t dpa, unsigned int len, unsigned int write)
1032{
1033 u64 cmd, offset;
1034 struct nfit_blk_mmio *mmio = &nfit_blk->mmio[DCR];
1035
1036 enum {
1037 BCW_OFFSET_MASK = (1ULL << 48)-1,
1038 BCW_LEN_SHIFT = 48,
1039 BCW_LEN_MASK = (1ULL << 8) - 1,
1040 BCW_CMD_SHIFT = 56,
1041 };
1042
1043 cmd = (dpa >> L1_CACHE_SHIFT) & BCW_OFFSET_MASK;
1044 len = len >> L1_CACHE_SHIFT;
1045 cmd |= ((u64) len & BCW_LEN_MASK) << BCW_LEN_SHIFT;
1046 cmd |= ((u64) write) << BCW_CMD_SHIFT;
1047
1048 offset = nfit_blk->cmd_offset + mmio->size * bw;
1049 if (mmio->num_lines)
1050 offset = to_interleave_offset(offset, mmio);
1051
67a3e8fe 1052 writeq(cmd, mmio->addr.base + offset);
c2ad2954 1053 wmb_blk(nfit_blk);
f0f2c072
RZ		 1054
1055 if (nfit_blk->dimm_flags & ND_BLK_DCR_LATCH)
67a3e8fe 1056 readq(mmio->addr.base + offset);
047fc8a1
RZ		 1057}
1058
1059static int acpi_nfit_blk_single_io(struct nfit_blk *nfit_blk,
1060 resource_size_t dpa, void *iobuf, size_t len, int rw,
1061 unsigned int lane)
1062{
1063 struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW];
1064 unsigned int copied = 0;
1065 u64 base_offset;
1066 int rc;
1067
1068 base_offset = nfit_blk->bdw_offset + dpa % L1_CACHE_BYTES
1069 + lane * mmio->size;
047fc8a1
RZ		 1070 write_blk_ctl(nfit_blk, lane, dpa, len, rw);
1071 while (len) {
1072 unsigned int c;
1073 u64 offset;
1074
1075 if (mmio->num_lines) {
1076 u32 line_offset;
1077
1078 offset = to_interleave_offset(base_offset + copied,
1079 mmio);
1080 div_u64_rem(offset, mmio->line_size, &line_offset);
1081 c = min_t(size_t, len, mmio->line_size - line_offset);
1082 } else {
1083 offset = base_offset + nfit_blk->bdw_offset;
1084 c = len;
1085 }
1086
1087 if (rw)
67a3e8fe 1088 memcpy_to_pmem(mmio->addr.aperture + offset,
c2ad2954 1089 iobuf + copied, c);
67a3e8fe
RZ		 1090 else {
1091 if (nfit_blk->dimm_flags & ND_BLK_READ_FLUSH)
1092 mmio_flush_range((void __force *)
1093 mmio->addr.aperture + offset, c);
1094
c2ad2954 1095 memcpy_from_pmem(iobuf + copied,
67a3e8fe
RZ		 1096 mmio->addr.aperture + offset, c);
1097 }
047fc8a1
RZ		 1098
1099 copied += c;
1100 len -= c;
1101 }
c2ad2954
RZ		 1102
1103 if (rw)
1104 wmb_blk(nfit_blk);
1105
047fc8a1
RZ		 1106 rc = read_blk_stat(nfit_blk, lane) ? -EIO : 0;
1107 return rc;
1108}
1109
1110static int acpi_nfit_blk_region_do_io(struct nd_blk_region *ndbr,
1111 resource_size_t dpa, void *iobuf, u64 len, int rw)
1112{
1113 struct nfit_blk *nfit_blk = nd_blk_region_provider_data(ndbr);
1114 struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW];
1115 struct nd_region *nd_region = nfit_blk->nd_region;
1116 unsigned int lane, copied = 0;
1117 int rc = 0;
1118
1119 lane = nd_region_acquire_lane(nd_region);
1120 while (len) {
1121 u64 c = min(len, mmio->size);
1122
1123 rc = acpi_nfit_blk_single_io(nfit_blk, dpa + copied,
1124 iobuf + copied, c, rw, lane);
1125 if (rc)
1126 break;
1127
1128 copied += c;
1129 len -= c;
1130 }
1131 nd_region_release_lane(nd_region, lane);
1132
1133 return rc;
1134}
1135
1136static void nfit_spa_mapping_release(struct kref *kref)
1137{
1138 struct nfit_spa_mapping *spa_map = to_spa_map(kref);
1139 struct acpi_nfit_system_address *spa = spa_map->spa;
1140 struct acpi_nfit_desc *acpi_desc = spa_map->acpi_desc;
1141
1142 WARN_ON(!mutex_is_locked(&acpi_desc->spa_map_mutex));
1143 dev_dbg(acpi_desc->dev, "%s: SPA%d\n", __func__, spa->range_index);
67a3e8fe
RZ		 1144 if (spa_map->type == SPA_MAP_APERTURE)
1145 memunmap((void __force *)spa_map->addr.aperture);
1146 else
1147 iounmap(spa_map->addr.base);
047fc8a1
RZ		 1148 release_mem_region(spa->address, spa->length);
1149 list_del(&spa_map->list);
1150 kfree(spa_map);
1151}
1152
1153static struct nfit_spa_mapping *find_spa_mapping(
1154 struct acpi_nfit_desc *acpi_desc,
1155 struct acpi_nfit_system_address *spa)
1156{
1157 struct nfit_spa_mapping *spa_map;
1158
1159 WARN_ON(!mutex_is_locked(&acpi_desc->spa_map_mutex));
1160 list_for_each_entry(spa_map, &acpi_desc->spa_maps, list)
1161 if (spa_map->spa == spa)
1162 return spa_map;
1163
1164 return NULL;
1165}
1166
1167static void nfit_spa_unmap(struct acpi_nfit_desc *acpi_desc,
1168 struct acpi_nfit_system_address *spa)
1169{
1170 struct nfit_spa_mapping *spa_map;
1171
1172 mutex_lock(&acpi_desc->spa_map_mutex);
1173 spa_map = find_spa_mapping(acpi_desc, spa);
1174
1175 if (spa_map)
1176 kref_put(&spa_map->kref, nfit_spa_mapping_release);
1177 mutex_unlock(&acpi_desc->spa_map_mutex);
1178}
1179
1180static void __iomem *__nfit_spa_map(struct acpi_nfit_desc *acpi_desc,
c2ad2954 1181 struct acpi_nfit_system_address *spa, enum spa_map_type type)
047fc8a1
RZ		 1182{
1183 resource_size_t start = spa->address;
1184 resource_size_t n = spa->length;
1185 struct nfit_spa_mapping *spa_map;
1186 struct resource *res;
1187
1188 WARN_ON(!mutex_is_locked(&acpi_desc->spa_map_mutex));
1189
1190 spa_map = find_spa_mapping(acpi_desc, spa);
1191 if (spa_map) {
1192 kref_get(&spa_map->kref);
67a3e8fe 1193 return spa_map->addr.base;
047fc8a1
RZ		 1194 }
1195
1196 spa_map = kzalloc(sizeof(*spa_map), GFP_KERNEL);
1197 if (!spa_map)
1198 return NULL;
1199
1200 INIT_LIST_HEAD(&spa_map->list);
1201 spa_map->spa = spa;
1202 kref_init(&spa_map->kref);
1203 spa_map->acpi_desc = acpi_desc;
1204
1205 res = request_mem_region(start, n, dev_name(acpi_desc->dev));
1206 if (!res)
1207 goto err_mem;
1208
67a3e8fe
RZ		 1209 spa_map->type = type;
1210 if (type == SPA_MAP_APERTURE)
1211 spa_map->addr.aperture = (void __pmem *)memremap(start, n,
1212 ARCH_MEMREMAP_PMEM);
1213 else
1214 spa_map->addr.base = ioremap_nocache(start, n);
1215
c2ad2954 1216
67a3e8fe 1217 if (!spa_map->addr.base)
047fc8a1
RZ		 1218 goto err_map;
1219
1220 list_add_tail(&spa_map->list, &acpi_desc->spa_maps);
67a3e8fe 1221 return spa_map->addr.base;
047fc8a1
RZ		 1222
1223 err_map:
1224 release_mem_region(start, n);
1225 err_mem:
1226 kfree(spa_map);
1227 return NULL;
1228}
1229
1230/**
1231 * nfit_spa_map - interleave-aware managed-mappings of acpi_nfit_system_address ranges
1232 * @nvdimm_bus: NFIT-bus that provided the spa table entry
1233 * @nfit_spa: spa table to map
c2ad2954 1234 * @type: aperture or control region
047fc8a1
RZ		 1235 *
1236 * In the case where block-data-window apertures and
1237 * dimm-control-regions are interleaved they will end up sharing a
1238 * single request_mem_region() + ioremap() for the address range. In
1239 * the style of devm nfit_spa_map() mappings are automatically dropped
1240 * when all region devices referencing the same mapping are disabled /
1241 * unbound.
1242 */
1243static void __iomem *nfit_spa_map(struct acpi_nfit_desc *acpi_desc,
c2ad2954 1244 struct acpi_nfit_system_address *spa, enum spa_map_type type)
047fc8a1
RZ		 1245{
1246 void __iomem *iomem;
1247
1248 mutex_lock(&acpi_desc->spa_map_mutex);
c2ad2954 1249 iomem = __nfit_spa_map(acpi_desc, spa, type);
047fc8a1
RZ		 1250 mutex_unlock(&acpi_desc->spa_map_mutex);
1251
1252 return iomem;
1253}
1254
1255static int nfit_blk_init_interleave(struct nfit_blk_mmio *mmio,
1256 struct acpi_nfit_interleave *idt, u16 interleave_ways)
1257{
1258 if (idt) {
1259 mmio->num_lines = idt->line_count;
1260 mmio->line_size = idt->line_size;
1261 if (interleave_ways == 0)
1262 return -ENXIO;
1263 mmio->table_size = mmio->num_lines * interleave_ways
1264 * mmio->line_size;
1265 }
1266
1267 return 0;
1268}
1269
f0f2c072
RZ		 1270static int acpi_nfit_blk_get_flags(struct nvdimm_bus_descriptor *nd_desc,
1271 struct nvdimm *nvdimm, struct nfit_blk *nfit_blk)
1272{
1273 struct nd_cmd_dimm_flags flags;
1274 int rc;
1275
1276 memset(&flags, 0, sizeof(flags));
1277 rc = nd_desc->ndctl(nd_desc, nvdimm, ND_CMD_DIMM_FLAGS, &flags,
1278 sizeof(flags));
1279
1280 if (rc >= 0 && flags.status == 0)
1281 nfit_blk->dimm_flags = flags.flags;
1282 else if (rc == -ENOTTY) {
1283 /* fall back to a conservative default */
67a3e8fe 1284 nfit_blk->dimm_flags = ND_BLK_DCR_LATCH | ND_BLK_READ_FLUSH;
f0f2c072
RZ		 1285 rc = 0;
1286 } else
1287 rc = -ENXIO;
1288
1289 return rc;
1290}
1291
047fc8a1
RZ		 1292static int acpi_nfit_blk_region_enable(struct nvdimm_bus *nvdimm_bus,
1293 struct device *dev)
1294{
1295 struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus);
1296 struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
1297 struct nd_blk_region *ndbr = to_nd_blk_region(dev);
c2ad2954 1298 struct nfit_flush *nfit_flush;
047fc8a1
RZ		 1299 struct nfit_blk_mmio *mmio;
1300 struct nfit_blk *nfit_blk;
1301 struct nfit_mem *nfit_mem;
1302 struct nvdimm *nvdimm;
1303 int rc;
1304
1305 nvdimm = nd_blk_region_to_dimm(ndbr);
1306 nfit_mem = nvdimm_provider_data(nvdimm);
1307 if (!nfit_mem || !nfit_mem->dcr || !nfit_mem->bdw) {
1308 dev_dbg(dev, "%s: missing%s%s%s\n", __func__,
1309 nfit_mem ? "" : " nfit_mem",
193ccca4
DW		 1310 (nfit_mem && nfit_mem->dcr) ? "" : " dcr",
1311 (nfit_mem && nfit_mem->bdw) ? "" : " bdw");
047fc8a1
RZ		 1312 return -ENXIO;
1313 }
1314
1315 nfit_blk = devm_kzalloc(dev, sizeof(*nfit_blk), GFP_KERNEL);
1316 if (!nfit_blk)
1317 return -ENOMEM;
1318 nd_blk_region_set_provider_data(ndbr, nfit_blk);
1319 nfit_blk->nd_region = to_nd_region(dev);
1320
1321 /* map block aperture memory */
1322 nfit_blk->bdw_offset = nfit_mem->bdw->offset;
1323 mmio = &nfit_blk->mmio[BDW];
67a3e8fe 1324 mmio->addr.base = nfit_spa_map(acpi_desc, nfit_mem->spa_bdw,
c2ad2954 1325 SPA_MAP_APERTURE);
67a3e8fe 1326 if (!mmio->addr.base) {
047fc8a1
RZ		 1327 dev_dbg(dev, "%s: %s failed to map bdw\n", __func__,
1328 nvdimm_name(nvdimm));
1329 return -ENOMEM;
1330 }
1331 mmio->size = nfit_mem->bdw->size;
1332 mmio->base_offset = nfit_mem->memdev_bdw->region_offset;
1333 mmio->idt = nfit_mem->idt_bdw;
1334 mmio->spa = nfit_mem->spa_bdw;
1335 rc = nfit_blk_init_interleave(mmio, nfit_mem->idt_bdw,
1336 nfit_mem->memdev_bdw->interleave_ways);
1337 if (rc) {
1338 dev_dbg(dev, "%s: %s failed to init bdw interleave\n",
1339 __func__, nvdimm_name(nvdimm));
1340 return rc;
1341 }
1342
1343 /* map block control memory */
1344 nfit_blk->cmd_offset = nfit_mem->dcr->command_offset;
1345 nfit_blk->stat_offset = nfit_mem->dcr->status_offset;
1346 mmio = &nfit_blk->mmio[DCR];
67a3e8fe 1347 mmio->addr.base = nfit_spa_map(acpi_desc, nfit_mem->spa_dcr,
c2ad2954 1348 SPA_MAP_CONTROL);
67a3e8fe 1349 if (!mmio->addr.base) {
047fc8a1
RZ		 1350 dev_dbg(dev, "%s: %s failed to map dcr\n", __func__,
1351 nvdimm_name(nvdimm));
1352 return -ENOMEM;
1353 }
1354 mmio->size = nfit_mem->dcr->window_size;
1355 mmio->base_offset = nfit_mem->memdev_dcr->region_offset;
1356 mmio->idt = nfit_mem->idt_dcr;
1357 mmio->spa = nfit_mem->spa_dcr;
1358 rc = nfit_blk_init_interleave(mmio, nfit_mem->idt_dcr,
1359 nfit_mem->memdev_dcr->interleave_ways);
1360 if (rc) {
1361 dev_dbg(dev, "%s: %s failed to init dcr interleave\n",
1362 __func__, nvdimm_name(nvdimm));
1363 return rc;
1364 }
1365
f0f2c072
RZ		 1366 rc = acpi_nfit_blk_get_flags(nd_desc, nvdimm, nfit_blk);
1367 if (rc < 0) {
1368 dev_dbg(dev, "%s: %s failed get DIMM flags\n",
1369 __func__, nvdimm_name(nvdimm));
1370 return rc;
1371 }
1372
c2ad2954
RZ		 1373 nfit_flush = nfit_mem->nfit_flush;
1374 if (nfit_flush && nfit_flush->flush->hint_count != 0) {
1375 nfit_blk->nvdimm_flush = devm_ioremap_nocache(dev,
1376 nfit_flush->flush->hint_address[0], 8);
1377 if (!nfit_blk->nvdimm_flush)
1378 return -ENOMEM;
1379 }
1380
96601adb 1381 if (!arch_has_wmb_pmem() && !nfit_blk->nvdimm_flush)
c2ad2954
RZ		 1382 dev_warn(dev, "unable to guarantee persistence of writes\n");
1383
047fc8a1
RZ		 1384 if (mmio->line_size == 0)
1385 return 0;
1386
1387 if ((u32) nfit_blk->cmd_offset % mmio->line_size
1388 + 8 > mmio->line_size) {
1389 dev_dbg(dev, "cmd_offset crosses interleave boundary\n");
1390 return -ENXIO;
1391 } else if ((u32) nfit_blk->stat_offset % mmio->line_size
1392 + 8 > mmio->line_size) {
1393 dev_dbg(dev, "stat_offset crosses interleave boundary\n");
1394 return -ENXIO;
1395 }
1396
1397 return 0;
1398}
1399
1400static void acpi_nfit_blk_region_disable(struct nvdimm_bus *nvdimm_bus,
1401 struct device *dev)
1402{
1403 struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus);
1404 struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
1405 struct nd_blk_region *ndbr = to_nd_blk_region(dev);
1406 struct nfit_blk *nfit_blk = nd_blk_region_provider_data(ndbr);
1407 int i;
1408
1409 if (!nfit_blk)
1410 return; /* never enabled */
1411
1412 /* auto-free BLK spa mappings */
1413 for (i = 0; i < 2; i++) {
1414 struct nfit_blk_mmio *mmio = &nfit_blk->mmio[i];
1415
67a3e8fe 1416 if (mmio->addr.base)
047fc8a1
RZ		 1417 nfit_spa_unmap(acpi_desc, mmio->spa);
1418 }
1419 nd_blk_region_set_provider_data(ndbr, NULL);
1420 /* devm will free nfit_blk */
1421}
1422
1f7df6f8
DW		 1423static int acpi_nfit_init_mapping(struct acpi_nfit_desc *acpi_desc,
1424 struct nd_mapping *nd_mapping, struct nd_region_desc *ndr_desc,
1425 struct acpi_nfit_memory_map *memdev,
1426 struct acpi_nfit_system_address *spa)
1427{
1428 struct nvdimm *nvdimm = acpi_nfit_dimm_by_handle(acpi_desc,
1429 memdev->device_handle);
047fc8a1 1430 struct nd_blk_region_desc *ndbr_desc;
1f7df6f8
DW		 1431 struct nfit_mem *nfit_mem;
1432 int blk_valid = 0;
1433
1434 if (!nvdimm) {
1435 dev_err(acpi_desc->dev, "spa%d dimm: %#x not found\n",
1436 spa->range_index, memdev->device_handle);
1437 return -ENODEV;
1438 }
1439
1440 nd_mapping->nvdimm = nvdimm;
1441 switch (nfit_spa_type(spa)) {
1442 case NFIT_SPA_PM:
1443 case NFIT_SPA_VOLATILE:
1444 nd_mapping->start = memdev->address;
1445 nd_mapping->size = memdev->region_size;
1446 break;
1447 case NFIT_SPA_DCR:
1448 nfit_mem = nvdimm_provider_data(nvdimm);
1449 if (!nfit_mem || !nfit_mem->bdw) {
1450 dev_dbg(acpi_desc->dev, "spa%d %s missing bdw\n",
1451 spa->range_index, nvdimm_name(nvdimm));
1452 } else {
1453 nd_mapping->size = nfit_mem->bdw->capacity;
1454 nd_mapping->start = nfit_mem->bdw->start_address;
5212e11f 1455 ndr_desc->num_lanes = nfit_mem->bdw->windows;
1f7df6f8
DW		 1456 blk_valid = 1;
1457 }
1458
1459 ndr_desc->nd_mapping = nd_mapping;
1460 ndr_desc->num_mappings = blk_valid;
047fc8a1
RZ		 1461 ndbr_desc = to_blk_region_desc(ndr_desc);
1462 ndbr_desc->enable = acpi_nfit_blk_region_enable;
1463 ndbr_desc->disable = acpi_nfit_blk_region_disable;
6bc75619 1464 ndbr_desc->do_io = acpi_desc->blk_do_io;
1f7df6f8
DW		 1465 if (!nvdimm_blk_region_create(acpi_desc->nvdimm_bus, ndr_desc))
1466 return -ENOMEM;
1467 break;
1468 }
1469
1470 return 0;
1471}
1472
1473static int acpi_nfit_register_region(struct acpi_nfit_desc *acpi_desc,
1474 struct nfit_spa *nfit_spa)
1475{
1476 static struct nd_mapping nd_mappings[ND_MAX_MAPPINGS];
1477 struct acpi_nfit_system_address *spa = nfit_spa->spa;
047fc8a1
RZ		 1478 struct nd_blk_region_desc ndbr_desc;
1479 struct nd_region_desc *ndr_desc;
1f7df6f8 1480 struct nfit_memdev *nfit_memdev;
1f7df6f8
DW		 1481 struct nvdimm_bus *nvdimm_bus;
1482 struct resource res;
eaf96153 1483 int count = 0, rc;
1f7df6f8
DW		 1484
1485 if (spa->range_index == 0) {
1486 dev_dbg(acpi_desc->dev, "%s: detected invalid spa index\n",
1487 __func__);
1488 return 0;
1489 }
1490
1491 memset(&res, 0, sizeof(res));
1492 memset(&nd_mappings, 0, sizeof(nd_mappings));
047fc8a1 1493 memset(&ndbr_desc, 0, sizeof(ndbr_desc));
1f7df6f8
DW		 1494 res.start = spa->address;
1495 res.end = res.start + spa->length - 1;
047fc8a1
RZ		 1496 ndr_desc = &ndbr_desc.ndr_desc;
1497 ndr_desc->res = &res;
1498 ndr_desc->provider_data = nfit_spa;
1499 ndr_desc->attr_groups = acpi_nfit_region_attribute_groups;
41d7a6d6
TK		 1500 if (spa->flags & ACPI_NFIT_PROXIMITY_VALID)
1501 ndr_desc->numa_node = acpi_map_pxm_to_online_node(
1502 spa->proximity_domain);
1503 else
1504 ndr_desc->numa_node = NUMA_NO_NODE;
1505
1f7df6f8
DW		 1506 list_for_each_entry(nfit_memdev, &acpi_desc->memdevs, list) {
1507 struct acpi_nfit_memory_map *memdev = nfit_memdev->memdev;
1508 struct nd_mapping *nd_mapping;
1f7df6f8
DW		 1509
1510 if (memdev->range_index != spa->range_index)
1511 continue;
1512 if (count >= ND_MAX_MAPPINGS) {
1513 dev_err(acpi_desc->dev, "spa%d exceeds max mappings %d\n",
1514 spa->range_index, ND_MAX_MAPPINGS);
1515 return -ENXIO;
1516 }
1517 nd_mapping = &nd_mappings[count++];
047fc8a1 1518 rc = acpi_nfit_init_mapping(acpi_desc, nd_mapping, ndr_desc,
1f7df6f8
DW		 1519 memdev, spa);
1520 if (rc)
1521 return rc;
1522 }
1523
047fc8a1
RZ		 1524 ndr_desc->nd_mapping = nd_mappings;
1525 ndr_desc->num_mappings = count;
1526 rc = acpi_nfit_init_interleave_set(acpi_desc, ndr_desc, spa);
eaf96153
DW		 1527 if (rc)
1528 return rc;
1529
1f7df6f8
DW		 1530 nvdimm_bus = acpi_desc->nvdimm_bus;
1531 if (nfit_spa_type(spa) == NFIT_SPA_PM) {
047fc8a1 1532 if (!nvdimm_pmem_region_create(nvdimm_bus, ndr_desc))
1f7df6f8
DW		 1533 return -ENOMEM;
1534 } else if (nfit_spa_type(spa) == NFIT_SPA_VOLATILE) {
047fc8a1 1535 if (!nvdimm_volatile_region_create(nvdimm_bus, ndr_desc))
1f7df6f8
DW		 1536 return -ENOMEM;
1537 }
1538 return 0;
1539}
1540
1541static int acpi_nfit_register_regions(struct acpi_nfit_desc *acpi_desc)
1542{
1543 struct nfit_spa *nfit_spa;
1544
1545 list_for_each_entry(nfit_spa, &acpi_desc->spas, list) {
1546 int rc = acpi_nfit_register_region(acpi_desc, nfit_spa);
1547
1548 if (rc)
1549 return rc;
1550 }
1551 return 0;
1552}
1553
6bc75619 1554int acpi_nfit_init(struct acpi_nfit_desc *acpi_desc, acpi_size sz)
b94d5230
DW		 1555{
1556 struct device *dev = acpi_desc->dev;
1557 const void *end;
1558 u8 *data;
1f7df6f8 1559 int rc;
b94d5230 1560
047fc8a1 1561 INIT_LIST_HEAD(&acpi_desc->spa_maps);
b94d5230
DW		 1562 INIT_LIST_HEAD(&acpi_desc->spas);
1563 INIT_LIST_HEAD(&acpi_desc->dcrs);
1564 INIT_LIST_HEAD(&acpi_desc->bdws);
047fc8a1 1565 INIT_LIST_HEAD(&acpi_desc->idts);
c2ad2954 1566 INIT_LIST_HEAD(&acpi_desc->flushes);
b94d5230
DW		 1567 INIT_LIST_HEAD(&acpi_desc->memdevs);
1568 INIT_LIST_HEAD(&acpi_desc->dimms);
047fc8a1 1569 mutex_init(&acpi_desc->spa_map_mutex);
b94d5230
DW		 1570
1571 data = (u8 *) acpi_desc->nfit;
1572 end = data + sz;
1573 data += sizeof(struct acpi_table_nfit);
1574 while (!IS_ERR_OR_NULL(data))
1575 data = add_table(acpi_desc, data, end);
1576
1577 if (IS_ERR(data)) {
1578 dev_dbg(dev, "%s: nfit table parsing error: %ld\n", __func__,
1579 PTR_ERR(data));
1580 return PTR_ERR(data);
1581 }
1582
1583 if (nfit_mem_init(acpi_desc) != 0)
1584 return -ENOMEM;
1585
62232e45
DW		 1586 acpi_nfit_init_dsms(acpi_desc);
1587
1f7df6f8
DW		 1588 rc = acpi_nfit_register_dimms(acpi_desc);
1589 if (rc)
1590 return rc;
1591
1592 return acpi_nfit_register_regions(acpi_desc);
b94d5230 1593}
6bc75619 1594EXPORT_SYMBOL_GPL(acpi_nfit_init);
b94d5230
DW		 1595
1596static int acpi_nfit_add(struct acpi_device *adev)
1597{
1598 struct nvdimm_bus_descriptor *nd_desc;
1599 struct acpi_nfit_desc *acpi_desc;
1600 struct device *dev = &adev->dev;
1601 struct acpi_table_header *tbl;
1602 acpi_status status = AE_OK;
1603 acpi_size sz;
1604 int rc;
1605
1606 status = acpi_get_table_with_size("NFIT", 0, &tbl, &sz);
1607 if (ACPI_FAILURE(status)) {
1608 dev_err(dev, "failed to find NFIT\n");
1609 return -ENXIO;
1610 }
1611
1612 acpi_desc = devm_kzalloc(dev, sizeof(*acpi_desc), GFP_KERNEL);
1613 if (!acpi_desc)
1614 return -ENOMEM;
1615
1616 dev_set_drvdata(dev, acpi_desc);
1617 acpi_desc->dev = dev;
1618 acpi_desc->nfit = (struct acpi_table_nfit *) tbl;
6bc75619 1619 acpi_desc->blk_do_io = acpi_nfit_blk_region_do_io;
b94d5230
DW		 1620 nd_desc = &acpi_desc->nd_desc;
1621 nd_desc->provider_name = "ACPI.NFIT";
1622 nd_desc->ndctl = acpi_nfit_ctl;
45def22c 1623 nd_desc->attr_groups = acpi_nfit_attribute_groups;
b94d5230
DW		 1624
1625 acpi_desc->nvdimm_bus = nvdimm_bus_register(dev, nd_desc);
1626 if (!acpi_desc->nvdimm_bus)
1627 return -ENXIO;
1628
1629 rc = acpi_nfit_init(acpi_desc, sz);
1630 if (rc) {
1631 nvdimm_bus_unregister(acpi_desc->nvdimm_bus);
1632 return rc;
1633 }
1634 return 0;
1635}
1636
1637static int acpi_nfit_remove(struct acpi_device *adev)
1638{
1639 struct acpi_nfit_desc *acpi_desc = dev_get_drvdata(&adev->dev);
1640
1641 nvdimm_bus_unregister(acpi_desc->nvdimm_bus);
1642 return 0;
1643}
1644
1645static const struct acpi_device_id acpi_nfit_ids[] = {
1646 { "ACPI0012", 0 },
1647 { "", 0 },
1648};
1649MODULE_DEVICE_TABLE(acpi, acpi_nfit_ids);
1650
1651static struct acpi_driver acpi_nfit_driver = {
1652 .name = KBUILD_MODNAME,
1653 .ids = acpi_nfit_ids,
1654 .ops = {
1655 .add = acpi_nfit_add,
1656 .remove = acpi_nfit_remove,
1657 },
1658};
1659
1660static __init int nfit_init(void)
1661{
1662 BUILD_BUG_ON(sizeof(struct acpi_table_nfit) != 40);
1663 BUILD_BUG_ON(sizeof(struct acpi_nfit_system_address) != 56);
1664 BUILD_BUG_ON(sizeof(struct acpi_nfit_memory_map) != 48);
1665 BUILD_BUG_ON(sizeof(struct acpi_nfit_interleave) != 20);
1666 BUILD_BUG_ON(sizeof(struct acpi_nfit_smbios) != 9);
1667 BUILD_BUG_ON(sizeof(struct acpi_nfit_control_region) != 80);
1668 BUILD_BUG_ON(sizeof(struct acpi_nfit_data_region) != 40);
1669
1670 acpi_str_to_uuid(UUID_VOLATILE_MEMORY, nfit_uuid[NFIT_SPA_VOLATILE]);
1671 acpi_str_to_uuid(UUID_PERSISTENT_MEMORY, nfit_uuid[NFIT_SPA_PM]);
1672 acpi_str_to_uuid(UUID_CONTROL_REGION, nfit_uuid[NFIT_SPA_DCR]);
1673 acpi_str_to_uuid(UUID_DATA_REGION, nfit_uuid[NFIT_SPA_BDW]);
1674 acpi_str_to_uuid(UUID_VOLATILE_VIRTUAL_DISK, nfit_uuid[NFIT_SPA_VDISK]);
1675 acpi_str_to_uuid(UUID_VOLATILE_VIRTUAL_CD, nfit_uuid[NFIT_SPA_VCD]);
1676 acpi_str_to_uuid(UUID_PERSISTENT_VIRTUAL_DISK, nfit_uuid[NFIT_SPA_PDISK]);
1677 acpi_str_to_uuid(UUID_PERSISTENT_VIRTUAL_CD, nfit_uuid[NFIT_SPA_PCD]);
1678 acpi_str_to_uuid(UUID_NFIT_BUS, nfit_uuid[NFIT_DEV_BUS]);
1679 acpi_str_to_uuid(UUID_NFIT_DIMM, nfit_uuid[NFIT_DEV_DIMM]);
1680
1681 return acpi_bus_register_driver(&acpi_nfit_driver);
1682}
1683
1684static __exit void nfit_exit(void)
1685{
1686 acpi_bus_unregister_driver(&acpi_nfit_driver);
1687}
1688
1689module_init(nfit_init);
1690module_exit(nfit_exit);
1691MODULE_LICENSE("GPL v2");
1692MODULE_AUTHOR("Intel Corporation");
Linux kernel - Deliverables
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